xref: /openbmc/linux/drivers/net/wan/pc300too.c (revision b6dcefde)
1 /*
2  * Cyclades PC300 synchronous serial card driver for Linux
3  *
4  * Copyright (C) 2000-2008 Krzysztof Halasa <khc@pm.waw.pl>
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of version 2 of the GNU General Public License
8  * as published by the Free Software Foundation.
9  *
10  * For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/>.
11  *
12  * Sources of information:
13  *    Hitachi HD64572 SCA-II User's Manual
14  *    Original Cyclades PC300 Linux driver
15  *
16  * This driver currently supports only PC300/RSV (V.24/V.35) and
17  * PC300/X21 cards.
18  */
19 
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/slab.h>
23 #include <linux/sched.h>
24 #include <linux/types.h>
25 #include <linux/fcntl.h>
26 #include <linux/in.h>
27 #include <linux/string.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/ioport.h>
31 #include <linux/moduleparam.h>
32 #include <linux/netdevice.h>
33 #include <linux/hdlc.h>
34 #include <linux/pci.h>
35 #include <linux/delay.h>
36 #include <asm/io.h>
37 
38 #include "hd64572.h"
39 
40 #undef DEBUG_PKT
41 #define DEBUG_RINGS
42 
43 #define PC300_PLX_SIZE		0x80    /* PLX control window size (128 B) */
44 #define PC300_SCA_SIZE		0x400   /* SCA window size (1 KB) */
45 #define MAX_TX_BUFFERS		10
46 
47 static int pci_clock_freq = 33000000;
48 static int use_crystal_clock = 0;
49 static unsigned int CLOCK_BASE;
50 
51 /* Masks to access the init_ctrl PLX register */
52 #define PC300_CLKSEL_MASK	 (0x00000004UL)
53 #define PC300_CHMEDIA_MASK(port) (0x00000020UL << ((port) * 3))
54 #define PC300_CTYPE_MASK	 (0x00000800UL)
55 
56 
57 enum { PC300_RSV = 1, PC300_X21, PC300_TE }; /* card types */
58 
59 /*
60  *      PLX PCI9050-1 local configuration and shared runtime registers.
61  *      This structure can be used to access 9050 registers (memory mapped).
62  */
63 typedef struct {
64 	u32 loc_addr_range[4];	/* 00-0Ch : Local Address Ranges */
65 	u32 loc_rom_range;	/* 10h : Local ROM Range */
66 	u32 loc_addr_base[4];	/* 14-20h : Local Address Base Addrs */
67 	u32 loc_rom_base;	/* 24h : Local ROM Base */
68 	u32 loc_bus_descr[4];	/* 28-34h : Local Bus Descriptors */
69 	u32 rom_bus_descr;	/* 38h : ROM Bus Descriptor */
70 	u32 cs_base[4];		/* 3C-48h : Chip Select Base Addrs */
71 	u32 intr_ctrl_stat;	/* 4Ch : Interrupt Control/Status */
72 	u32 init_ctrl;		/* 50h : EEPROM ctrl, Init Ctrl, etc */
73 }plx9050;
74 
75 
76 
77 typedef struct port_s {
78 	struct napi_struct napi;
79 	struct net_device *netdev;
80 	struct card_s *card;
81 	spinlock_t lock;	/* TX lock */
82 	sync_serial_settings settings;
83 	int rxpart;		/* partial frame received, next frame invalid*/
84 	unsigned short encoding;
85 	unsigned short parity;
86 	unsigned int iface;
87 	u16 rxin;		/* rx ring buffer 'in' pointer */
88 	u16 txin;		/* tx ring buffer 'in' and 'last' pointers */
89 	u16 txlast;
90 	u8 rxs, txs, tmc;	/* SCA registers */
91 	u8 chan;		/* physical port # - 0 or 1 */
92 }port_t;
93 
94 
95 
96 typedef struct card_s {
97 	int type;		/* RSV, X21, etc. */
98 	int n_ports;		/* 1 or 2 ports */
99 	u8 __iomem *rambase;	/* buffer memory base (virtual) */
100 	u8 __iomem *scabase;	/* SCA memory base (virtual) */
101 	plx9050 __iomem *plxbase; /* PLX registers memory base (virtual) */
102 	u32 init_ctrl_value;	/* Saved value - 9050 bug workaround */
103 	u16 rx_ring_buffers;	/* number of buffers in a ring */
104 	u16 tx_ring_buffers;
105 	u16 buff_offset;	/* offset of first buffer of first channel */
106 	u8 irq;			/* interrupt request level */
107 
108 	port_t ports[2];
109 }card_t;
110 
111 
112 #define get_port(card, port)	     ((port) < (card)->n_ports ? \
113 					 (&(card)->ports[port]) : (NULL))
114 
115 #include "hd64572.c"
116 
117 
118 static void pc300_set_iface(port_t *port)
119 {
120 	card_t *card = port->card;
121 	u32 __iomem * init_ctrl = &card->plxbase->init_ctrl;
122 	u16 msci = get_msci(port);
123 	u8 rxs = port->rxs & CLK_BRG_MASK;
124 	u8 txs = port->txs & CLK_BRG_MASK;
125 
126 	sca_out(EXS_TES1, (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
127 		port->card);
128 	switch(port->settings.clock_type) {
129 	case CLOCK_INT:
130 		rxs |= CLK_BRG; /* BRG output */
131 		txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
132 		break;
133 
134 	case CLOCK_TXINT:
135 		rxs |= CLK_LINE; /* RXC input */
136 		txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */
137 		break;
138 
139 	case CLOCK_TXFROMRX:
140 		rxs |= CLK_LINE; /* RXC input */
141 		txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
142 		break;
143 
144 	default:		/* EXTernal clock */
145 		rxs |= CLK_LINE; /* RXC input */
146 		txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */
147 		break;
148 	}
149 
150 	port->rxs = rxs;
151 	port->txs = txs;
152 	sca_out(rxs, msci + RXS, card);
153 	sca_out(txs, msci + TXS, card);
154 	sca_set_port(port);
155 
156 	if (port->card->type == PC300_RSV) {
157 		if (port->iface == IF_IFACE_V35)
158 			writel(card->init_ctrl_value |
159 			       PC300_CHMEDIA_MASK(port->chan), init_ctrl);
160 		else
161 			writel(card->init_ctrl_value &
162 			       ~PC300_CHMEDIA_MASK(port->chan), init_ctrl);
163 	}
164 }
165 
166 
167 
168 static int pc300_open(struct net_device *dev)
169 {
170 	port_t *port = dev_to_port(dev);
171 
172 	int result = hdlc_open(dev);
173 	if (result)
174 		return result;
175 
176 	sca_open(dev);
177 	pc300_set_iface(port);
178 	return 0;
179 }
180 
181 
182 
183 static int pc300_close(struct net_device *dev)
184 {
185 	sca_close(dev);
186 	hdlc_close(dev);
187 	return 0;
188 }
189 
190 
191 
192 static int pc300_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
193 {
194 	const size_t size = sizeof(sync_serial_settings);
195 	sync_serial_settings new_line;
196 	sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
197 	int new_type;
198 	port_t *port = dev_to_port(dev);
199 
200 #ifdef DEBUG_RINGS
201 	if (cmd == SIOCDEVPRIVATE) {
202 		sca_dump_rings(dev);
203 		return 0;
204 	}
205 #endif
206 	if (cmd != SIOCWANDEV)
207 		return hdlc_ioctl(dev, ifr, cmd);
208 
209 	if (ifr->ifr_settings.type == IF_GET_IFACE) {
210 		ifr->ifr_settings.type = port->iface;
211 		if (ifr->ifr_settings.size < size) {
212 			ifr->ifr_settings.size = size; /* data size wanted */
213 			return -ENOBUFS;
214 		}
215 		if (copy_to_user(line, &port->settings, size))
216 			return -EFAULT;
217 		return 0;
218 
219 	}
220 
221 	if (port->card->type == PC300_X21 &&
222 	    (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL ||
223 	     ifr->ifr_settings.type == IF_IFACE_X21))
224 		new_type = IF_IFACE_X21;
225 
226 	else if (port->card->type == PC300_RSV &&
227 		 (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL ||
228 		  ifr->ifr_settings.type == IF_IFACE_V35))
229 		new_type = IF_IFACE_V35;
230 
231 	else if (port->card->type == PC300_RSV &&
232 		 ifr->ifr_settings.type == IF_IFACE_V24)
233 		new_type = IF_IFACE_V24;
234 
235 	else
236 		return hdlc_ioctl(dev, ifr, cmd);
237 
238 	if (!capable(CAP_NET_ADMIN))
239 		return -EPERM;
240 
241 	if (copy_from_user(&new_line, line, size))
242 		return -EFAULT;
243 
244 	if (new_line.clock_type != CLOCK_EXT &&
245 	    new_line.clock_type != CLOCK_TXFROMRX &&
246 	    new_line.clock_type != CLOCK_INT &&
247 	    new_line.clock_type != CLOCK_TXINT)
248 		return -EINVAL;	/* No such clock setting */
249 
250 	if (new_line.loopback != 0 && new_line.loopback != 1)
251 		return -EINVAL;
252 
253 	memcpy(&port->settings, &new_line, size); /* Update settings */
254 	port->iface = new_type;
255 	pc300_set_iface(port);
256 	return 0;
257 }
258 
259 
260 
261 static void pc300_pci_remove_one(struct pci_dev *pdev)
262 {
263 	int i;
264 	card_t *card = pci_get_drvdata(pdev);
265 
266 	for (i = 0; i < 2; i++)
267 		if (card->ports[i].card)
268 			unregister_hdlc_device(card->ports[i].netdev);
269 
270 	if (card->irq)
271 		free_irq(card->irq, card);
272 
273 	if (card->rambase)
274 		iounmap(card->rambase);
275 	if (card->scabase)
276 		iounmap(card->scabase);
277 	if (card->plxbase)
278 		iounmap(card->plxbase);
279 
280 	pci_release_regions(pdev);
281 	pci_disable_device(pdev);
282 	pci_set_drvdata(pdev, NULL);
283 	if (card->ports[0].netdev)
284 		free_netdev(card->ports[0].netdev);
285 	if (card->ports[1].netdev)
286 		free_netdev(card->ports[1].netdev);
287 	kfree(card);
288 }
289 
290 static const struct net_device_ops pc300_ops = {
291 	.ndo_open       = pc300_open,
292 	.ndo_stop       = pc300_close,
293 	.ndo_change_mtu = hdlc_change_mtu,
294 	.ndo_start_xmit = hdlc_start_xmit,
295 	.ndo_do_ioctl   = pc300_ioctl,
296 };
297 
298 static int __devinit pc300_pci_init_one(struct pci_dev *pdev,
299 					const struct pci_device_id *ent)
300 {
301 	card_t *card;
302 	u32 __iomem *p;
303 	int i;
304 	u32 ramsize;
305 	u32 ramphys;		/* buffer memory base */
306 	u32 scaphys;		/* SCA memory base */
307 	u32 plxphys;		/* PLX registers memory base */
308 
309 	i = pci_enable_device(pdev);
310 	if (i)
311 		return i;
312 
313 	i = pci_request_regions(pdev, "PC300");
314 	if (i) {
315 		pci_disable_device(pdev);
316 		return i;
317 	}
318 
319 	card = kzalloc(sizeof(card_t), GFP_KERNEL);
320 	if (card == NULL) {
321 		printk(KERN_ERR "pc300: unable to allocate memory\n");
322 		pci_release_regions(pdev);
323 		pci_disable_device(pdev);
324 		return -ENOBUFS;
325 	}
326 	pci_set_drvdata(pdev, card);
327 
328 	if (pci_resource_len(pdev, 0) != PC300_PLX_SIZE ||
329 	    pci_resource_len(pdev, 2) != PC300_SCA_SIZE ||
330 	    pci_resource_len(pdev, 3) < 16384) {
331 		printk(KERN_ERR "pc300: invalid card EEPROM parameters\n");
332 		pc300_pci_remove_one(pdev);
333 		return -EFAULT;
334 	}
335 
336 	plxphys = pci_resource_start(pdev, 0) & PCI_BASE_ADDRESS_MEM_MASK;
337 	card->plxbase = ioremap(plxphys, PC300_PLX_SIZE);
338 
339 	scaphys = pci_resource_start(pdev, 2) & PCI_BASE_ADDRESS_MEM_MASK;
340 	card->scabase = ioremap(scaphys, PC300_SCA_SIZE);
341 
342 	ramphys = pci_resource_start(pdev, 3) & PCI_BASE_ADDRESS_MEM_MASK;
343 	card->rambase = pci_ioremap_bar(pdev, 3);
344 
345 	if (card->plxbase == NULL ||
346 	    card->scabase == NULL ||
347 	    card->rambase == NULL) {
348 		printk(KERN_ERR "pc300: ioremap() failed\n");
349 		pc300_pci_remove_one(pdev);
350 	}
351 
352 	/* PLX PCI 9050 workaround for local configuration register read bug */
353 	pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, scaphys);
354 	card->init_ctrl_value = readl(&((plx9050 __iomem *)card->scabase)->init_ctrl);
355 	pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, plxphys);
356 
357 	if (pdev->device == PCI_DEVICE_ID_PC300_TE_1 ||
358 	    pdev->device == PCI_DEVICE_ID_PC300_TE_2)
359 		card->type = PC300_TE; /* not fully supported */
360 	else if (card->init_ctrl_value & PC300_CTYPE_MASK)
361 		card->type = PC300_X21;
362 	else
363 		card->type = PC300_RSV;
364 
365 	if (pdev->device == PCI_DEVICE_ID_PC300_RX_1 ||
366 	    pdev->device == PCI_DEVICE_ID_PC300_TE_1)
367 		card->n_ports = 1;
368 	else
369 		card->n_ports = 2;
370 
371 	for (i = 0; i < card->n_ports; i++)
372 		if (!(card->ports[i].netdev = alloc_hdlcdev(&card->ports[i]))) {
373 			printk(KERN_ERR "pc300: unable to allocate memory\n");
374 			pc300_pci_remove_one(pdev);
375 			return -ENOMEM;
376 		}
377 
378 	/* Reset PLX */
379 	p = &card->plxbase->init_ctrl;
380 	writel(card->init_ctrl_value | 0x40000000, p);
381 	readl(p);		/* Flush the write - do not use sca_flush */
382 	udelay(1);
383 
384 	writel(card->init_ctrl_value, p);
385 	readl(p);		/* Flush the write - do not use sca_flush */
386 	udelay(1);
387 
388 	/* Reload Config. Registers from EEPROM */
389 	writel(card->init_ctrl_value | 0x20000000, p);
390 	readl(p);		/* Flush the write - do not use sca_flush */
391 	udelay(1);
392 
393 	writel(card->init_ctrl_value, p);
394 	readl(p);		/* Flush the write - do not use sca_flush */
395 	udelay(1);
396 
397 	ramsize = sca_detect_ram(card, card->rambase,
398 				 pci_resource_len(pdev, 3));
399 
400 	if (use_crystal_clock)
401 		card->init_ctrl_value &= ~PC300_CLKSEL_MASK;
402 	else
403 		card->init_ctrl_value |= PC300_CLKSEL_MASK;
404 
405 	writel(card->init_ctrl_value, &card->plxbase->init_ctrl);
406 	/* number of TX + RX buffers for one port */
407 	i = ramsize / (card->n_ports * (sizeof(pkt_desc) + HDLC_MAX_MRU));
408 	card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
409 	card->rx_ring_buffers = i - card->tx_ring_buffers;
410 
411 	card->buff_offset = card->n_ports * sizeof(pkt_desc) *
412 		(card->tx_ring_buffers + card->rx_ring_buffers);
413 
414 	printk(KERN_INFO "pc300: PC300/%s, %u KB RAM at 0x%x, IRQ%u, "
415 	       "using %u TX + %u RX packets rings\n",
416 	       card->type == PC300_X21 ? "X21" :
417 	       card->type == PC300_TE ? "TE" : "RSV",
418 	       ramsize / 1024, ramphys, pdev->irq,
419 	       card->tx_ring_buffers, card->rx_ring_buffers);
420 
421 	if (card->tx_ring_buffers < 1) {
422 		printk(KERN_ERR "pc300: RAM test failed\n");
423 		pc300_pci_remove_one(pdev);
424 		return -EFAULT;
425 	}
426 
427 	/* Enable interrupts on the PCI bridge, LINTi1 active low */
428 	writew(0x0041, &card->plxbase->intr_ctrl_stat);
429 
430 	/* Allocate IRQ */
431 	if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, "pc300", card)) {
432 		printk(KERN_WARNING "pc300: could not allocate IRQ%d.\n",
433 		       pdev->irq);
434 		pc300_pci_remove_one(pdev);
435 		return -EBUSY;
436 	}
437 	card->irq = pdev->irq;
438 
439 	sca_init(card, 0);
440 
441 	// COTE not set - allows better TX DMA settings
442 	// sca_out(sca_in(PCR, card) | PCR_COTE, PCR, card);
443 
444 	sca_out(0x10, BTCR, card);
445 
446 	for (i = 0; i < card->n_ports; i++) {
447 		port_t *port = &card->ports[i];
448 		struct net_device *dev = port->netdev;
449 		hdlc_device *hdlc = dev_to_hdlc(dev);
450 		port->chan = i;
451 
452 		spin_lock_init(&port->lock);
453 		dev->irq = card->irq;
454 		dev->mem_start = ramphys;
455 		dev->mem_end = ramphys + ramsize - 1;
456 		dev->tx_queue_len = 50;
457 		dev->netdev_ops = &pc300_ops;
458 		hdlc->attach = sca_attach;
459 		hdlc->xmit = sca_xmit;
460 		port->settings.clock_type = CLOCK_EXT;
461 		port->card = card;
462 		if (card->type == PC300_X21)
463 			port->iface = IF_IFACE_X21;
464 		else
465 			port->iface = IF_IFACE_V35;
466 
467 		sca_init_port(port);
468 		if (register_hdlc_device(dev)) {
469 			printk(KERN_ERR "pc300: unable to register hdlc "
470 			       "device\n");
471 			port->card = NULL;
472 			pc300_pci_remove_one(pdev);
473 			return -ENOBUFS;
474 		}
475 
476 		printk(KERN_INFO "%s: PC300 channel %d\n",
477 		       dev->name, port->chan);
478 	}
479 	return 0;
480 }
481 
482 
483 
484 static struct pci_device_id pc300_pci_tbl[] __devinitdata = {
485 	{ PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_1, PCI_ANY_ID,
486 	  PCI_ANY_ID, 0, 0, 0 },
487 	{ PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_2, PCI_ANY_ID,
488 	  PCI_ANY_ID, 0, 0, 0 },
489 	{ PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_1, PCI_ANY_ID,
490 	  PCI_ANY_ID, 0, 0, 0 },
491 	{ PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_2, PCI_ANY_ID,
492 	  PCI_ANY_ID, 0, 0, 0 },
493 	{ 0, }
494 };
495 
496 
497 static struct pci_driver pc300_pci_driver = {
498 	.name =          "PC300",
499 	.id_table =      pc300_pci_tbl,
500 	.probe =         pc300_pci_init_one,
501 	.remove =        pc300_pci_remove_one,
502 };
503 
504 
505 static int __init pc300_init_module(void)
506 {
507 	if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) {
508 		printk(KERN_ERR "pc300: Invalid PCI clock frequency\n");
509 		return -EINVAL;
510 	}
511 	if (use_crystal_clock != 0 && use_crystal_clock != 1) {
512 		printk(KERN_ERR "pc300: Invalid 'use_crystal_clock' value\n");
513 		return -EINVAL;
514 	}
515 
516 	CLOCK_BASE = use_crystal_clock ? 24576000 : pci_clock_freq;
517 
518 	return pci_register_driver(&pc300_pci_driver);
519 }
520 
521 
522 
523 static void __exit pc300_cleanup_module(void)
524 {
525 	pci_unregister_driver(&pc300_pci_driver);
526 }
527 
528 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
529 MODULE_DESCRIPTION("Cyclades PC300 serial port driver");
530 MODULE_LICENSE("GPL v2");
531 MODULE_DEVICE_TABLE(pci, pc300_pci_tbl);
532 module_param(pci_clock_freq, int, 0444);
533 MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz");
534 module_param(use_crystal_clock, int, 0444);
535 MODULE_PARM_DESC(use_crystal_clock,
536 		 "Use 24.576 MHz clock instead of PCI clock");
537 module_init(pc300_init_module);
538 module_exit(pc300_cleanup_module);
539