1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * SDL Inc. RISCom/N2 synchronous serial card driver for Linux 4 * 5 * Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl> 6 * 7 * For information see <https://www.kernel.org/pub/linux/utils/net/hdlc/> 8 * 9 * Note: integrated CSU/DSU/DDS are not supported by this driver 10 * 11 * Sources of information: 12 * Hitachi HD64570 SCA User's Manual 13 * SDL Inc. PPP/HDLC/CISCO driver 14 */ 15 16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 17 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/capability.h> 21 #include <linux/slab.h> 22 #include <linux/types.h> 23 #include <linux/fcntl.h> 24 #include <linux/in.h> 25 #include <linux/string.h> 26 #include <linux/errno.h> 27 #include <linux/init.h> 28 #include <linux/ioport.h> 29 #include <linux/moduleparam.h> 30 #include <linux/netdevice.h> 31 #include <linux/hdlc.h> 32 #include <asm/io.h> 33 #include "hd64570.h" 34 35 static const char *version = "SDL RISCom/N2 driver version: 1.15"; 36 static const char *devname = "RISCom/N2"; 37 38 #undef DEBUG_PKT 39 #define DEBUG_RINGS 40 41 #define USE_WINDOWSIZE 16384 42 #define USE_BUS16BITS 1 43 #define CLOCK_BASE 9830400 /* 9.8304 MHz */ 44 #define MAX_PAGES 16 /* 16 RAM pages at max */ 45 #define MAX_RAM_SIZE 0x80000 /* 512 KB */ 46 #if MAX_RAM_SIZE > MAX_PAGES * USE_WINDOWSIZE 47 #undef MAX_RAM_SIZE 48 #define MAX_RAM_SIZE (MAX_PAGES * USE_WINDOWSIZE) 49 #endif 50 #define N2_IOPORTS 0x10 51 #define NEED_DETECT_RAM 52 #define NEED_SCA_MSCI_INTR 53 #define MAX_TX_BUFFERS 10 54 55 static char *hw; /* pointer to hw=xxx command line string */ 56 57 /* RISCom/N2 Board Registers */ 58 59 /* PC Control Register */ 60 #define N2_PCR 0 61 #define PCR_RUNSCA 1 /* Run 64570 */ 62 #define PCR_VPM 2 /* Enable VPM - needed if using RAM above 1 MB */ 63 #define PCR_ENWIN 4 /* Open window */ 64 #define PCR_BUS16 8 /* 16-bit bus */ 65 66 /* Memory Base Address Register */ 67 #define N2_BAR 2 68 69 /* Page Scan Register */ 70 #define N2_PSR 4 71 #define WIN16K 0x00 72 #define WIN32K 0x20 73 #define WIN64K 0x40 74 #define PSR_WINBITS 0x60 75 #define PSR_DMAEN 0x80 76 #define PSR_PAGEBITS 0x0F 77 78 /* Modem Control Reg */ 79 #define N2_MCR 6 80 #define CLOCK_OUT_PORT1 0x80 81 #define CLOCK_OUT_PORT0 0x40 82 #define TX422_PORT1 0x20 83 #define TX422_PORT0 0x10 84 #define DSR_PORT1 0x08 85 #define DSR_PORT0 0x04 86 #define DTR_PORT1 0x02 87 #define DTR_PORT0 0x01 88 89 typedef struct port_s { 90 struct net_device *dev; 91 struct card_s *card; 92 spinlock_t lock; /* TX lock */ 93 sync_serial_settings settings; 94 int valid; /* port enabled */ 95 int rxpart; /* partial frame received, next frame invalid*/ 96 unsigned short encoding; 97 unsigned short parity; 98 u16 rxin; /* rx ring buffer 'in' pointer */ 99 u16 txin; /* tx ring buffer 'in' and 'last' pointers */ 100 u16 txlast; 101 u8 rxs, txs, tmc; /* SCA registers */ 102 u8 phy_node; /* physical port # - 0 or 1 */ 103 u8 log_node; /* logical port # */ 104 } port_t; 105 106 typedef struct card_s { 107 u8 __iomem *winbase; /* ISA window base address */ 108 u32 phy_winbase; /* ISA physical base address */ 109 u32 ram_size; /* number of bytes */ 110 u16 io; /* IO Base address */ 111 u16 buff_offset; /* offset of first buffer of first channel */ 112 u16 rx_ring_buffers; /* number of buffers in a ring */ 113 u16 tx_ring_buffers; 114 u8 irq; /* IRQ (3-15) */ 115 116 port_t ports[2]; 117 struct card_s *next_card; 118 } card_t; 119 120 static card_t *first_card; 121 static card_t **new_card = &first_card; 122 123 #define sca_reg(reg, card) (0x8000 | (card)->io | \ 124 ((reg) & 0x0F) | (((reg) & 0xF0) << 6)) 125 #define sca_in(reg, card) inb(sca_reg(reg, card)) 126 #define sca_out(value, reg, card) outb(value, sca_reg(reg, card)) 127 #define sca_inw(reg, card) inw(sca_reg(reg, card)) 128 #define sca_outw(value, reg, card) outw(value, sca_reg(reg, card)) 129 130 #define port_to_card(port) ((port)->card) 131 #define log_node(port) ((port)->log_node) 132 #define phy_node(port) ((port)->phy_node) 133 #define winsize(card) (USE_WINDOWSIZE) 134 #define winbase(card) ((card)->winbase) 135 #define get_port(card, port) ((card)->ports[port].valid ? \ 136 &(card)->ports[port] : NULL) 137 138 static __inline__ u8 sca_get_page(card_t *card) 139 { 140 return inb(card->io + N2_PSR) & PSR_PAGEBITS; 141 } 142 143 static __inline__ void openwin(card_t *card, u8 page) 144 { 145 u8 psr = inb(card->io + N2_PSR); 146 147 outb((psr & ~PSR_PAGEBITS) | page, card->io + N2_PSR); 148 } 149 150 #include "hd64570.c" 151 152 static void n2_set_iface(port_t *port) 153 { 154 card_t *card = port->card; 155 int io = card->io; 156 u8 mcr = inb(io + N2_MCR); 157 u8 msci = get_msci(port); 158 u8 rxs = port->rxs & CLK_BRG_MASK; 159 u8 txs = port->txs & CLK_BRG_MASK; 160 161 switch (port->settings.clock_type) { 162 case CLOCK_INT: 163 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0; 164 rxs |= CLK_BRG_RX; /* BRG output */ 165 txs |= CLK_RXCLK_TX; /* RX clock */ 166 break; 167 168 case CLOCK_TXINT: 169 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0; 170 rxs |= CLK_LINE_RX; /* RXC input */ 171 txs |= CLK_BRG_TX; /* BRG output */ 172 break; 173 174 case CLOCK_TXFROMRX: 175 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0; 176 rxs |= CLK_LINE_RX; /* RXC input */ 177 txs |= CLK_RXCLK_TX; /* RX clock */ 178 break; 179 180 default: /* Clock EXTernal */ 181 mcr &= port->phy_node ? ~CLOCK_OUT_PORT1 : ~CLOCK_OUT_PORT0; 182 rxs |= CLK_LINE_RX; /* RXC input */ 183 txs |= CLK_LINE_TX; /* TXC input */ 184 } 185 186 outb(mcr, io + N2_MCR); 187 port->rxs = rxs; 188 port->txs = txs; 189 sca_out(rxs, msci + RXS, card); 190 sca_out(txs, msci + TXS, card); 191 sca_set_port(port); 192 } 193 194 static int n2_open(struct net_device *dev) 195 { 196 port_t *port = dev_to_port(dev); 197 int io = port->card->io; 198 u8 mcr = inb(io + N2_MCR) | 199 (port->phy_node ? TX422_PORT1 : TX422_PORT0); 200 int result; 201 202 result = hdlc_open(dev); 203 if (result) 204 return result; 205 206 mcr &= port->phy_node ? ~DTR_PORT1 : ~DTR_PORT0; /* set DTR ON */ 207 outb(mcr, io + N2_MCR); 208 209 outb(inb(io + N2_PCR) | PCR_ENWIN, io + N2_PCR); /* open window */ 210 outb(inb(io + N2_PSR) | PSR_DMAEN, io + N2_PSR); /* enable dma */ 211 sca_open(dev); 212 n2_set_iface(port); 213 return 0; 214 } 215 216 static int n2_close(struct net_device *dev) 217 { 218 port_t *port = dev_to_port(dev); 219 int io = port->card->io; 220 u8 mcr = inb(io + N2_MCR) | 221 (port->phy_node ? TX422_PORT1 : TX422_PORT0); 222 223 sca_close(dev); 224 mcr |= port->phy_node ? DTR_PORT1 : DTR_PORT0; /* set DTR OFF */ 225 outb(mcr, io + N2_MCR); 226 hdlc_close(dev); 227 return 0; 228 } 229 230 static int n2_siocdevprivate(struct net_device *dev, struct ifreq *ifr, 231 void __user *data, int cmd) 232 { 233 #ifdef DEBUG_RINGS 234 if (cmd == SIOCDEVPRIVATE) { 235 sca_dump_rings(dev); 236 return 0; 237 } 238 #endif 239 return -EOPNOTSUPP; 240 } 241 242 static int n2_ioctl(struct net_device *dev, struct if_settings *ifs) 243 { 244 const size_t size = sizeof(sync_serial_settings); 245 sync_serial_settings new_line; 246 sync_serial_settings __user *line = ifs->ifs_ifsu.sync; 247 port_t *port = dev_to_port(dev); 248 249 switch (ifs->type) { 250 case IF_GET_IFACE: 251 ifs->type = IF_IFACE_SYNC_SERIAL; 252 if (ifs->size < size) { 253 ifs->size = size; /* data size wanted */ 254 return -ENOBUFS; 255 } 256 if (copy_to_user(line, &port->settings, size)) 257 return -EFAULT; 258 return 0; 259 260 case IF_IFACE_SYNC_SERIAL: 261 if (!capable(CAP_NET_ADMIN)) 262 return -EPERM; 263 264 if (copy_from_user(&new_line, line, size)) 265 return -EFAULT; 266 267 if (new_line.clock_type != CLOCK_EXT && 268 new_line.clock_type != CLOCK_TXFROMRX && 269 new_line.clock_type != CLOCK_INT && 270 new_line.clock_type != CLOCK_TXINT) 271 return -EINVAL; /* No such clock setting */ 272 273 if (new_line.loopback != 0 && new_line.loopback != 1) 274 return -EINVAL; 275 276 memcpy(&port->settings, &new_line, size); /* Update settings */ 277 n2_set_iface(port); 278 return 0; 279 280 default: 281 return hdlc_ioctl(dev, ifs); 282 } 283 } 284 285 static void n2_destroy_card(card_t *card) 286 { 287 int cnt; 288 289 for (cnt = 0; cnt < 2; cnt++) 290 if (card->ports[cnt].card) { 291 struct net_device *dev = port_to_dev(&card->ports[cnt]); 292 293 unregister_hdlc_device(dev); 294 } 295 296 if (card->irq) 297 free_irq(card->irq, card); 298 299 if (card->winbase) { 300 iounmap(card->winbase); 301 release_mem_region(card->phy_winbase, USE_WINDOWSIZE); 302 } 303 304 if (card->io) 305 release_region(card->io, N2_IOPORTS); 306 if (card->ports[0].dev) 307 free_netdev(card->ports[0].dev); 308 if (card->ports[1].dev) 309 free_netdev(card->ports[1].dev); 310 kfree(card); 311 } 312 313 static const struct net_device_ops n2_ops = { 314 .ndo_open = n2_open, 315 .ndo_stop = n2_close, 316 .ndo_start_xmit = hdlc_start_xmit, 317 .ndo_siocwandev = n2_ioctl, 318 .ndo_siocdevprivate = n2_siocdevprivate, 319 }; 320 321 static int __init n2_run(unsigned long io, unsigned long irq, 322 unsigned long winbase, long valid0, long valid1) 323 { 324 card_t *card; 325 u8 cnt, pcr; 326 int i; 327 328 if (io < 0x200 || io > 0x3FF || (io % N2_IOPORTS) != 0) { 329 pr_err("invalid I/O port value\n"); 330 return -ENODEV; 331 } 332 333 if (irq < 3 || irq > 15 || irq == 6) /* FIXME */ { 334 pr_err("invalid IRQ value\n"); 335 return -ENODEV; 336 } 337 338 if (winbase < 0xA0000 || winbase > 0xFFFFF || (winbase & 0xFFF) != 0) { 339 pr_err("invalid RAM value\n"); 340 return -ENODEV; 341 } 342 343 card = kzalloc(sizeof(card_t), GFP_KERNEL); 344 if (!card) 345 return -ENOBUFS; 346 347 card->ports[0].dev = alloc_hdlcdev(&card->ports[0]); 348 card->ports[1].dev = alloc_hdlcdev(&card->ports[1]); 349 if (!card->ports[0].dev || !card->ports[1].dev) { 350 pr_err("unable to allocate memory\n"); 351 n2_destroy_card(card); 352 return -ENOMEM; 353 } 354 355 if (!request_region(io, N2_IOPORTS, devname)) { 356 pr_err("I/O port region in use\n"); 357 n2_destroy_card(card); 358 return -EBUSY; 359 } 360 card->io = io; 361 362 if (request_irq(irq, sca_intr, 0, devname, card)) { 363 pr_err("could not allocate IRQ\n"); 364 n2_destroy_card(card); 365 return -EBUSY; 366 } 367 card->irq = irq; 368 369 if (!request_mem_region(winbase, USE_WINDOWSIZE, devname)) { 370 pr_err("could not request RAM window\n"); 371 n2_destroy_card(card); 372 return -EBUSY; 373 } 374 card->phy_winbase = winbase; 375 card->winbase = ioremap(winbase, USE_WINDOWSIZE); 376 if (!card->winbase) { 377 pr_err("ioremap() failed\n"); 378 n2_destroy_card(card); 379 return -EFAULT; 380 } 381 382 outb(0, io + N2_PCR); 383 outb(winbase >> 12, io + N2_BAR); 384 385 switch (USE_WINDOWSIZE) { 386 case 16384: 387 outb(WIN16K, io + N2_PSR); 388 break; 389 390 case 32768: 391 outb(WIN32K, io + N2_PSR); 392 break; 393 394 case 65536: 395 outb(WIN64K, io + N2_PSR); 396 break; 397 398 default: 399 pr_err("invalid window size\n"); 400 n2_destroy_card(card); 401 return -ENODEV; 402 } 403 404 pcr = PCR_ENWIN | PCR_VPM | (USE_BUS16BITS ? PCR_BUS16 : 0); 405 outb(pcr, io + N2_PCR); 406 407 card->ram_size = sca_detect_ram(card, card->winbase, MAX_RAM_SIZE); 408 409 /* number of TX + RX buffers for one port */ 410 i = card->ram_size / ((valid0 + valid1) * (sizeof(pkt_desc) + 411 HDLC_MAX_MRU)); 412 413 card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS); 414 card->rx_ring_buffers = i - card->tx_ring_buffers; 415 416 card->buff_offset = (valid0 + valid1) * sizeof(pkt_desc) * 417 (card->tx_ring_buffers + card->rx_ring_buffers); 418 419 pr_info("RISCom/N2 %u KB RAM, IRQ%u, using %u TX + %u RX packets rings\n", 420 card->ram_size / 1024, card->irq, 421 card->tx_ring_buffers, card->rx_ring_buffers); 422 423 if (card->tx_ring_buffers < 1) { 424 pr_err("RAM test failed\n"); 425 n2_destroy_card(card); 426 return -EIO; 427 } 428 429 pcr |= PCR_RUNSCA; /* run SCA */ 430 outb(pcr, io + N2_PCR); 431 outb(0, io + N2_MCR); 432 433 sca_init(card, 0); 434 for (cnt = 0; cnt < 2; cnt++) { 435 port_t *port = &card->ports[cnt]; 436 struct net_device *dev = port_to_dev(port); 437 hdlc_device *hdlc = dev_to_hdlc(dev); 438 439 if ((cnt == 0 && !valid0) || (cnt == 1 && !valid1)) 440 continue; 441 442 port->phy_node = cnt; 443 port->valid = 1; 444 445 if ((cnt == 1) && valid0) 446 port->log_node = 1; 447 448 spin_lock_init(&port->lock); 449 dev->irq = irq; 450 dev->mem_start = winbase; 451 dev->mem_end = winbase + USE_WINDOWSIZE - 1; 452 dev->tx_queue_len = 50; 453 dev->netdev_ops = &n2_ops; 454 hdlc->attach = sca_attach; 455 hdlc->xmit = sca_xmit; 456 port->settings.clock_type = CLOCK_EXT; 457 port->card = card; 458 459 if (register_hdlc_device(dev)) { 460 pr_warn("unable to register hdlc device\n"); 461 port->card = NULL; 462 n2_destroy_card(card); 463 return -ENOBUFS; 464 } 465 sca_init_port(port); /* Set up SCA memory */ 466 467 netdev_info(dev, "RISCom/N2 node %d\n", port->phy_node); 468 } 469 470 *new_card = card; 471 new_card = &card->next_card; 472 473 return 0; 474 } 475 476 static int __init n2_init(void) 477 { 478 if (!hw) { 479 #ifdef MODULE 480 pr_info("no card initialized\n"); 481 #endif 482 return -EINVAL; /* no parameters specified, abort */ 483 } 484 485 pr_info("%s\n", version); 486 487 do { 488 unsigned long io, irq, ram; 489 long valid[2] = { 0, 0 }; /* Default = both ports disabled */ 490 491 io = simple_strtoul(hw, &hw, 0); 492 493 if (*hw++ != ',') 494 break; 495 irq = simple_strtoul(hw, &hw, 0); 496 497 if (*hw++ != ',') 498 break; 499 ram = simple_strtoul(hw, &hw, 0); 500 501 if (*hw++ != ',') 502 break; 503 while (1) { 504 if (*hw == '0' && !valid[0]) 505 valid[0] = 1; /* Port 0 enabled */ 506 else if (*hw == '1' && !valid[1]) 507 valid[1] = 1; /* Port 1 enabled */ 508 else 509 break; 510 hw++; 511 } 512 513 if (!valid[0] && !valid[1]) 514 break; /* at least one port must be used */ 515 516 if (*hw == ':' || *hw == '\x0') 517 n2_run(io, irq, ram, valid[0], valid[1]); 518 519 if (*hw == '\x0') 520 return first_card ? 0 : -EINVAL; 521 } while (*hw++ == ':'); 522 523 pr_err("invalid hardware parameters\n"); 524 return first_card ? 0 : -EINVAL; 525 } 526 527 static void __exit n2_cleanup(void) 528 { 529 card_t *card = first_card; 530 531 while (card) { 532 card_t *ptr = card; 533 534 card = card->next_card; 535 n2_destroy_card(ptr); 536 } 537 } 538 539 module_init(n2_init); 540 module_exit(n2_cleanup); 541 542 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>"); 543 MODULE_DESCRIPTION("RISCom/N2 serial port driver"); 544 MODULE_LICENSE("GPL v2"); 545 module_param(hw, charp, 0444); 546 MODULE_PARM_DESC(hw, "io,irq,ram,ports:io,irq,..."); 547