1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel IXP4xx HSS (synchronous serial port) driver for Linux 4 * 5 * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl> 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/module.h> 11 #include <linux/bitops.h> 12 #include <linux/cdev.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/dmapool.h> 15 #include <linux/fs.h> 16 #include <linux/hdlc.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/platform_device.h> 20 #include <linux/poll.h> 21 #include <linux/slab.h> 22 #include <linux/gpio/consumer.h> 23 #include <linux/of.h> 24 #include <linux/soc/ixp4xx/npe.h> 25 #include <linux/soc/ixp4xx/qmgr.h> 26 #include <linux/soc/ixp4xx/cpu.h> 27 28 /* This is what all IXP4xx platforms we know uses, if more frequencies 29 * are needed, we need to migrate to the clock framework. 30 */ 31 #define IXP4XX_TIMER_FREQ 66666000 32 33 #define DEBUG_DESC 0 34 #define DEBUG_RX 0 35 #define DEBUG_TX 0 36 #define DEBUG_PKT_BYTES 0 37 #define DEBUG_CLOSE 0 38 39 #define DRV_NAME "ixp4xx_hss" 40 41 #define PKT_EXTRA_FLAGS 0 /* orig 1 */ 42 #define PKT_NUM_PIPES 1 /* 1, 2 or 4 */ 43 #define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */ 44 45 #define RX_DESCS 16 /* also length of all RX queues */ 46 #define TX_DESCS 16 /* also length of all TX queues */ 47 48 #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) 49 #define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */ 50 #define MAX_CLOSE_WAIT 1000 /* microseconds */ 51 #define HSS_COUNT 2 52 #define FRAME_SIZE 256 /* doesn't matter at this point */ 53 #define FRAME_OFFSET 0 54 #define MAX_CHANNELS (FRAME_SIZE / 8) 55 56 #define NAPI_WEIGHT 16 57 58 /* Queue IDs */ 59 #define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */ 60 #define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */ 61 #define HSS0_PKT_TX1_QUEUE 15 62 #define HSS0_PKT_TX2_QUEUE 16 63 #define HSS0_PKT_TX3_QUEUE 17 64 #define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */ 65 #define HSS0_PKT_RXFREE1_QUEUE 19 66 #define HSS0_PKT_RXFREE2_QUEUE 20 67 #define HSS0_PKT_RXFREE3_QUEUE 21 68 #define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */ 69 70 #define HSS1_PKT_RX_QUEUE 0 71 #define HSS1_PKT_TX0_QUEUE 5 72 #define HSS1_PKT_TX1_QUEUE 6 73 #define HSS1_PKT_TX2_QUEUE 7 74 #define HSS1_PKT_TX3_QUEUE 8 75 #define HSS1_PKT_RXFREE0_QUEUE 1 76 #define HSS1_PKT_RXFREE1_QUEUE 2 77 #define HSS1_PKT_RXFREE2_QUEUE 3 78 #define HSS1_PKT_RXFREE3_QUEUE 4 79 #define HSS1_PKT_TXDONE_QUEUE 9 80 81 #define NPE_PKT_MODE_HDLC 0 82 #define NPE_PKT_MODE_RAW 1 83 #define NPE_PKT_MODE_56KMODE 2 84 #define NPE_PKT_MODE_56KENDIAN_MSB 4 85 86 /* PKT_PIPE_HDLC_CFG_WRITE flags */ 87 #define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */ 88 #define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */ 89 #define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */ 90 91 /* hss_config, PCRs */ 92 /* Frame sync sampling, default = active low */ 93 #define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000 94 #define PCR_FRM_SYNC_FALLINGEDGE 0x80000000 95 #define PCR_FRM_SYNC_RISINGEDGE 0xC0000000 96 97 /* Frame sync pin: input (default) or output generated off a given clk edge */ 98 #define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000 99 #define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000 100 101 /* Frame and data clock sampling on edge, default = falling */ 102 #define PCR_FCLK_EDGE_RISING 0x08000000 103 #define PCR_DCLK_EDGE_RISING 0x04000000 104 105 /* Clock direction, default = input */ 106 #define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000 107 108 /* Generate/Receive frame pulses, default = enabled */ 109 #define PCR_FRM_PULSE_DISABLED 0x01000000 110 111 /* Data rate is full (default) or half the configured clk speed */ 112 #define PCR_HALF_CLK_RATE 0x00200000 113 114 /* Invert data between NPE and HSS FIFOs? (default = no) */ 115 #define PCR_DATA_POLARITY_INVERT 0x00100000 116 117 /* TX/RX endianness, default = LSB */ 118 #define PCR_MSB_ENDIAN 0x00080000 119 120 /* Normal (default) / open drain mode (TX only) */ 121 #define PCR_TX_PINS_OPEN_DRAIN 0x00040000 122 123 /* No framing bit transmitted and expected on RX? (default = framing bit) */ 124 #define PCR_SOF_NO_FBIT 0x00020000 125 126 /* Drive data pins? */ 127 #define PCR_TX_DATA_ENABLE 0x00010000 128 129 /* Voice 56k type: drive the data pins low (default), high, high Z */ 130 #define PCR_TX_V56K_HIGH 0x00002000 131 #define PCR_TX_V56K_HIGH_IMP 0x00004000 132 133 /* Unassigned type: drive the data pins low (default), high, high Z */ 134 #define PCR_TX_UNASS_HIGH 0x00000800 135 #define PCR_TX_UNASS_HIGH_IMP 0x00001000 136 137 /* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */ 138 #define PCR_TX_FB_HIGH_IMP 0x00000400 139 140 /* 56k data endiannes - which bit unused: high (default) or low */ 141 #define PCR_TX_56KE_BIT_0_UNUSED 0x00000200 142 143 /* 56k data transmission type: 32/8 bit data (default) or 56K data */ 144 #define PCR_TX_56KS_56K_DATA 0x00000100 145 146 /* hss_config, cCR */ 147 /* Number of packetized clients, default = 1 */ 148 #define CCR_NPE_HFIFO_2_HDLC 0x04000000 149 #define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000 150 151 /* default = no loopback */ 152 #define CCR_LOOPBACK 0x02000000 153 154 /* HSS number, default = 0 (first) */ 155 #define CCR_SECOND_HSS 0x01000000 156 157 /* hss_config, clkCR: main:10, num:10, denom:12 */ 158 #define CLK42X_SPEED_EXP ((0x3FF << 22) | (2 << 12) | 15) /*65 KHz*/ 159 160 #define CLK42X_SPEED_512KHZ ((130 << 22) | (2 << 12) | 15) 161 #define CLK42X_SPEED_1536KHZ ((43 << 22) | (18 << 12) | 47) 162 #define CLK42X_SPEED_1544KHZ ((43 << 22) | (33 << 12) | 192) 163 #define CLK42X_SPEED_2048KHZ ((32 << 22) | (34 << 12) | 63) 164 #define CLK42X_SPEED_4096KHZ ((16 << 22) | (34 << 12) | 127) 165 #define CLK42X_SPEED_8192KHZ ((8 << 22) | (34 << 12) | 255) 166 167 #define CLK46X_SPEED_512KHZ ((130 << 22) | (24 << 12) | 127) 168 #define CLK46X_SPEED_1536KHZ ((43 << 22) | (152 << 12) | 383) 169 #define CLK46X_SPEED_1544KHZ ((43 << 22) | (66 << 12) | 385) 170 #define CLK46X_SPEED_2048KHZ ((32 << 22) | (280 << 12) | 511) 171 #define CLK46X_SPEED_4096KHZ ((16 << 22) | (280 << 12) | 1023) 172 #define CLK46X_SPEED_8192KHZ ((8 << 22) | (280 << 12) | 2047) 173 174 /* HSS_CONFIG_CLOCK_CR register consists of 3 parts: 175 * A (10 bits), B (10 bits) and C (12 bits). 176 * IXP42x HSS clock generator operation (verified with an oscilloscope): 177 * Each clock bit takes 7.5 ns (1 / 133.xx MHz). 178 * The clock sequence consists of (C - B) states of 0s and 1s, each state is 179 * A bits wide. It's followed by (B + 1) states of 0s and 1s, each state is 180 * (A + 1) bits wide. 181 * 182 * The resulting average clock frequency (assuming 33.333 MHz oscillator) is: 183 * freq = 66.666 MHz / (A + (B + 1) / (C + 1)) 184 * minimum freq = 66.666 MHz / (A + 1) 185 * maximum freq = 66.666 MHz / A 186 * 187 * Example: A = 2, B = 2, C = 7, CLOCK_CR register = 2 << 22 | 2 << 12 | 7 188 * freq = 66.666 MHz / (2 + (2 + 1) / (7 + 1)) = 28.07 MHz (Mb/s). 189 * The clock sequence is: 1100110011 (5 doubles) 000111000 (3 triples). 190 * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits 191 * = 19 bits (each 7.5 ns long) = 142.5 ns (then the sequence repeats). 192 * The sequence consists of 4 complete clock periods, thus the average 193 * frequency (= clock rate) is 4 / 142.5 ns = 28.07 MHz (Mb/s). 194 * (max specified clock rate for IXP42x HSS is 8.192 Mb/s). 195 */ 196 197 /* hss_config, LUT entries */ 198 #define TDMMAP_UNASSIGNED 0 199 #define TDMMAP_HDLC 1 /* HDLC - packetized */ 200 #define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */ 201 #define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */ 202 203 /* offsets into HSS config */ 204 #define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */ 205 #define HSS_CONFIG_RX_PCR 0x04 206 #define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */ 207 #define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */ 208 #define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */ 209 #define HSS_CONFIG_RX_FCR 0x14 210 #define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */ 211 #define HSS_CONFIG_RX_LUT 0x38 212 213 /* NPE command codes */ 214 /* writes the ConfigWord value to the location specified by offset */ 215 #define PORT_CONFIG_WRITE 0x40 216 217 /* triggers the NPE to load the contents of the configuration table */ 218 #define PORT_CONFIG_LOAD 0x41 219 220 /* triggers the NPE to return an HssErrorReadResponse message */ 221 #define PORT_ERROR_READ 0x42 222 223 /* triggers the NPE to reset internal status and enable the HssPacketized 224 * operation for the flow specified by pPipe 225 */ 226 #define PKT_PIPE_FLOW_ENABLE 0x50 227 #define PKT_PIPE_FLOW_DISABLE 0x51 228 #define PKT_NUM_PIPES_WRITE 0x52 229 #define PKT_PIPE_FIFO_SIZEW_WRITE 0x53 230 #define PKT_PIPE_HDLC_CFG_WRITE 0x54 231 #define PKT_PIPE_IDLE_PATTERN_WRITE 0x55 232 #define PKT_PIPE_RX_SIZE_WRITE 0x56 233 #define PKT_PIPE_MODE_WRITE 0x57 234 235 /* HDLC packet status values - desc->status */ 236 #define ERR_SHUTDOWN 1 /* stop or shutdown occurrence */ 237 #define ERR_HDLC_ALIGN 2 /* HDLC alignment error */ 238 #define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */ 239 #define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving 240 * this packet (if buf_len < pkt_len) 241 */ 242 #define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */ 243 #define ERR_HDLC_ABORT 6 /* abort sequence received */ 244 #define ERR_DISCONNECTING 7 /* disconnect is in progress */ 245 246 #ifdef __ARMEB__ 247 typedef struct sk_buff buffer_t; 248 #define free_buffer dev_kfree_skb 249 #define free_buffer_irq dev_consume_skb_irq 250 #else 251 typedef void buffer_t; 252 #define free_buffer kfree 253 #define free_buffer_irq kfree 254 #endif 255 256 struct port { 257 struct device *dev; 258 struct npe *npe; 259 unsigned int txreadyq; 260 unsigned int rxtrigq; 261 unsigned int rxfreeq; 262 unsigned int rxq; 263 unsigned int txq; 264 unsigned int txdoneq; 265 struct gpio_desc *cts; 266 struct gpio_desc *rts; 267 struct gpio_desc *dcd; 268 struct gpio_desc *dtr; 269 struct gpio_desc *clk_internal; 270 struct net_device *netdev; 271 struct napi_struct napi; 272 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS]; 273 struct desc *desc_tab; /* coherent */ 274 dma_addr_t desc_tab_phys; 275 unsigned int id; 276 unsigned int clock_type, clock_rate, loopback; 277 unsigned int initialized, carrier; 278 u8 hdlc_cfg; 279 u32 clock_reg; 280 }; 281 282 /* NPE message structure */ 283 struct msg { 284 #ifdef __ARMEB__ 285 u8 cmd, unused, hss_port, index; 286 union { 287 struct { u8 data8a, data8b, data8c, data8d; }; 288 struct { u16 data16a, data16b; }; 289 struct { u32 data32; }; 290 }; 291 #else 292 u8 index, hss_port, unused, cmd; 293 union { 294 struct { u8 data8d, data8c, data8b, data8a; }; 295 struct { u16 data16b, data16a; }; 296 struct { u32 data32; }; 297 }; 298 #endif 299 }; 300 301 /* HDLC packet descriptor */ 302 struct desc { 303 u32 next; /* pointer to next buffer, unused */ 304 305 #ifdef __ARMEB__ 306 u16 buf_len; /* buffer length */ 307 u16 pkt_len; /* packet length */ 308 u32 data; /* pointer to data buffer in RAM */ 309 u8 status; 310 u8 error_count; 311 u16 __reserved; 312 #else 313 u16 pkt_len; /* packet length */ 314 u16 buf_len; /* buffer length */ 315 u32 data; /* pointer to data buffer in RAM */ 316 u16 __reserved; 317 u8 error_count; 318 u8 status; 319 #endif 320 u32 __reserved1[4]; 321 }; 322 323 #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ 324 (n) * sizeof(struct desc)) 325 #define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) 326 327 #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ 328 ((n) + RX_DESCS) * sizeof(struct desc)) 329 #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) 330 331 /***************************************************************************** 332 * global variables 333 ****************************************************************************/ 334 335 static int ports_open; 336 static struct dma_pool *dma_pool; 337 static DEFINE_SPINLOCK(npe_lock); 338 339 /***************************************************************************** 340 * utility functions 341 ****************************************************************************/ 342 343 static inline struct port *dev_to_port(struct net_device *dev) 344 { 345 return dev_to_hdlc(dev)->priv; 346 } 347 348 #ifndef __ARMEB__ 349 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) 350 { 351 int i; 352 353 for (i = 0; i < cnt; i++) 354 dest[i] = swab32(src[i]); 355 } 356 #endif 357 358 /***************************************************************************** 359 * HSS access 360 ****************************************************************************/ 361 362 static void hss_npe_send(struct port *port, struct msg *msg, const char *what) 363 { 364 u32 *val = (u32 *)msg; 365 366 if (npe_send_message(port->npe, msg, what)) { 367 pr_crit("HSS-%i: unable to send command [%08X:%08X] to %s\n", 368 port->id, val[0], val[1], npe_name(port->npe)); 369 BUG(); 370 } 371 } 372 373 static void hss_config_set_lut(struct port *port) 374 { 375 struct msg msg; 376 int ch; 377 378 memset(&msg, 0, sizeof(msg)); 379 msg.cmd = PORT_CONFIG_WRITE; 380 msg.hss_port = port->id; 381 382 for (ch = 0; ch < MAX_CHANNELS; ch++) { 383 msg.data32 >>= 2; 384 msg.data32 |= TDMMAP_HDLC << 30; 385 386 if (ch % 16 == 15) { 387 msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3); 388 hss_npe_send(port, &msg, "HSS_SET_TX_LUT"); 389 390 msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT; 391 hss_npe_send(port, &msg, "HSS_SET_RX_LUT"); 392 } 393 } 394 } 395 396 static void hss_config(struct port *port) 397 { 398 struct msg msg; 399 400 memset(&msg, 0, sizeof(msg)); 401 msg.cmd = PORT_CONFIG_WRITE; 402 msg.hss_port = port->id; 403 msg.index = HSS_CONFIG_TX_PCR; 404 msg.data32 = PCR_FRM_PULSE_DISABLED | PCR_MSB_ENDIAN | 405 PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT; 406 if (port->clock_type == CLOCK_INT) 407 msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT; 408 hss_npe_send(port, &msg, "HSS_SET_TX_PCR"); 409 410 msg.index = HSS_CONFIG_RX_PCR; 411 msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING; 412 hss_npe_send(port, &msg, "HSS_SET_RX_PCR"); 413 414 memset(&msg, 0, sizeof(msg)); 415 msg.cmd = PORT_CONFIG_WRITE; 416 msg.hss_port = port->id; 417 msg.index = HSS_CONFIG_CORE_CR; 418 msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) | 419 (port->id ? CCR_SECOND_HSS : 0); 420 hss_npe_send(port, &msg, "HSS_SET_CORE_CR"); 421 422 memset(&msg, 0, sizeof(msg)); 423 msg.cmd = PORT_CONFIG_WRITE; 424 msg.hss_port = port->id; 425 msg.index = HSS_CONFIG_CLOCK_CR; 426 msg.data32 = port->clock_reg; 427 hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR"); 428 429 memset(&msg, 0, sizeof(msg)); 430 msg.cmd = PORT_CONFIG_WRITE; 431 msg.hss_port = port->id; 432 msg.index = HSS_CONFIG_TX_FCR; 433 msg.data16a = FRAME_OFFSET; 434 msg.data16b = FRAME_SIZE - 1; 435 hss_npe_send(port, &msg, "HSS_SET_TX_FCR"); 436 437 memset(&msg, 0, sizeof(msg)); 438 msg.cmd = PORT_CONFIG_WRITE; 439 msg.hss_port = port->id; 440 msg.index = HSS_CONFIG_RX_FCR; 441 msg.data16a = FRAME_OFFSET; 442 msg.data16b = FRAME_SIZE - 1; 443 hss_npe_send(port, &msg, "HSS_SET_RX_FCR"); 444 445 hss_config_set_lut(port); 446 447 memset(&msg, 0, sizeof(msg)); 448 msg.cmd = PORT_CONFIG_LOAD; 449 msg.hss_port = port->id; 450 hss_npe_send(port, &msg, "HSS_LOAD_CONFIG"); 451 452 if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") || 453 /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */ 454 msg.cmd != PORT_CONFIG_LOAD || msg.data32) { 455 pr_crit("HSS-%i: HSS_LOAD_CONFIG failed\n", port->id); 456 BUG(); 457 } 458 459 /* HDLC may stop working without this - check FIXME */ 460 npe_recv_message(port->npe, &msg, "FLUSH_IT"); 461 } 462 463 static void hss_set_hdlc_cfg(struct port *port) 464 { 465 struct msg msg; 466 467 memset(&msg, 0, sizeof(msg)); 468 msg.cmd = PKT_PIPE_HDLC_CFG_WRITE; 469 msg.hss_port = port->id; 470 msg.data8a = port->hdlc_cfg; /* rx_cfg */ 471 msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */ 472 hss_npe_send(port, &msg, "HSS_SET_HDLC_CFG"); 473 } 474 475 static u32 hss_get_status(struct port *port) 476 { 477 struct msg msg; 478 479 memset(&msg, 0, sizeof(msg)); 480 msg.cmd = PORT_ERROR_READ; 481 msg.hss_port = port->id; 482 hss_npe_send(port, &msg, "PORT_ERROR_READ"); 483 if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) { 484 pr_crit("HSS-%i: unable to read HSS status\n", port->id); 485 BUG(); 486 } 487 488 return msg.data32; 489 } 490 491 static void hss_start_hdlc(struct port *port) 492 { 493 struct msg msg; 494 495 memset(&msg, 0, sizeof(msg)); 496 msg.cmd = PKT_PIPE_FLOW_ENABLE; 497 msg.hss_port = port->id; 498 msg.data32 = 0; 499 hss_npe_send(port, &msg, "HSS_ENABLE_PKT_PIPE"); 500 } 501 502 static void hss_stop_hdlc(struct port *port) 503 { 504 struct msg msg; 505 506 memset(&msg, 0, sizeof(msg)); 507 msg.cmd = PKT_PIPE_FLOW_DISABLE; 508 msg.hss_port = port->id; 509 hss_npe_send(port, &msg, "HSS_DISABLE_PKT_PIPE"); 510 hss_get_status(port); /* make sure it's halted */ 511 } 512 513 static int hss_load_firmware(struct port *port) 514 { 515 struct msg msg; 516 int err; 517 518 if (port->initialized) 519 return 0; 520 521 if (!npe_running(port->npe)) { 522 err = npe_load_firmware(port->npe, npe_name(port->npe), 523 port->dev); 524 if (err) 525 return err; 526 } 527 528 /* HDLC mode configuration */ 529 memset(&msg, 0, sizeof(msg)); 530 msg.cmd = PKT_NUM_PIPES_WRITE; 531 msg.hss_port = port->id; 532 msg.data8a = PKT_NUM_PIPES; 533 hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES"); 534 535 msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE; 536 msg.data8a = PKT_PIPE_FIFO_SIZEW; 537 hss_npe_send(port, &msg, "HSS_SET_PKT_FIFO"); 538 539 msg.cmd = PKT_PIPE_MODE_WRITE; 540 msg.data8a = NPE_PKT_MODE_HDLC; 541 /* msg.data8b = inv_mask */ 542 /* msg.data8c = or_mask */ 543 hss_npe_send(port, &msg, "HSS_SET_PKT_MODE"); 544 545 msg.cmd = PKT_PIPE_RX_SIZE_WRITE; 546 msg.data16a = HDLC_MAX_MRU; /* including CRC */ 547 hss_npe_send(port, &msg, "HSS_SET_PKT_RX_SIZE"); 548 549 msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE; 550 msg.data32 = 0x7F7F7F7F; /* ??? FIXME */ 551 hss_npe_send(port, &msg, "HSS_SET_PKT_IDLE"); 552 553 port->initialized = 1; 554 return 0; 555 } 556 557 /***************************************************************************** 558 * packetized (HDLC) operation 559 ****************************************************************************/ 560 561 static inline void debug_pkt(struct net_device *dev, const char *func, 562 u8 *data, int len) 563 { 564 #if DEBUG_PKT_BYTES 565 int i; 566 567 printk(KERN_DEBUG "%s: %s(%i)", dev->name, func, len); 568 for (i = 0; i < len; i++) { 569 if (i >= DEBUG_PKT_BYTES) 570 break; 571 printk("%s%02X", !(i % 4) ? " " : "", data[i]); 572 } 573 printk("\n"); 574 #endif 575 } 576 577 static inline void debug_desc(u32 phys, struct desc *desc) 578 { 579 #if DEBUG_DESC 580 printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n", 581 phys, desc->next, desc->buf_len, desc->pkt_len, 582 desc->data, desc->status, desc->error_count); 583 #endif 584 } 585 586 static inline int queue_get_desc(unsigned int queue, struct port *port, 587 int is_tx) 588 { 589 u32 phys, tab_phys, n_desc; 590 struct desc *tab; 591 592 phys = qmgr_get_entry(queue); 593 if (!phys) 594 return -1; 595 596 BUG_ON(phys & 0x1F); 597 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0); 598 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0); 599 n_desc = (phys - tab_phys) / sizeof(struct desc); 600 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS)); 601 debug_desc(phys, &tab[n_desc]); 602 BUG_ON(tab[n_desc].next); 603 return n_desc; 604 } 605 606 static inline void queue_put_desc(unsigned int queue, u32 phys, 607 struct desc *desc) 608 { 609 debug_desc(phys, desc); 610 BUG_ON(phys & 0x1F); 611 qmgr_put_entry(queue, phys); 612 /* Don't check for queue overflow here, we've allocated sufficient 613 * length and queues >= 32 don't support this check anyway. 614 */ 615 } 616 617 static inline void dma_unmap_tx(struct port *port, struct desc *desc) 618 { 619 #ifdef __ARMEB__ 620 dma_unmap_single(&port->netdev->dev, desc->data, 621 desc->buf_len, DMA_TO_DEVICE); 622 #else 623 dma_unmap_single(&port->netdev->dev, desc->data & ~3, 624 ALIGN((desc->data & 3) + desc->buf_len, 4), 625 DMA_TO_DEVICE); 626 #endif 627 } 628 629 static void hss_hdlc_set_carrier(void *pdev, int carrier) 630 { 631 struct net_device *netdev = pdev; 632 struct port *port = dev_to_port(netdev); 633 unsigned long flags; 634 635 spin_lock_irqsave(&npe_lock, flags); 636 port->carrier = carrier; 637 if (!port->loopback) { 638 if (carrier) 639 netif_carrier_on(netdev); 640 else 641 netif_carrier_off(netdev); 642 } 643 spin_unlock_irqrestore(&npe_lock, flags); 644 } 645 646 static void hss_hdlc_rx_irq(void *pdev) 647 { 648 struct net_device *dev = pdev; 649 struct port *port = dev_to_port(dev); 650 651 #if DEBUG_RX 652 printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name); 653 #endif 654 qmgr_disable_irq(port->rxq); 655 napi_schedule(&port->napi); 656 } 657 658 static int hss_hdlc_poll(struct napi_struct *napi, int budget) 659 { 660 struct port *port = container_of(napi, struct port, napi); 661 struct net_device *dev = port->netdev; 662 unsigned int rxq = port->rxq; 663 unsigned int rxfreeq = port->rxfreeq; 664 int received = 0; 665 666 #if DEBUG_RX 667 printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name); 668 #endif 669 670 while (received < budget) { 671 struct sk_buff *skb; 672 struct desc *desc; 673 int n; 674 #ifdef __ARMEB__ 675 struct sk_buff *temp; 676 u32 phys; 677 #endif 678 679 n = queue_get_desc(rxq, port, 0); 680 if (n < 0) { 681 #if DEBUG_RX 682 printk(KERN_DEBUG "%s: hss_hdlc_poll" 683 " napi_complete\n", dev->name); 684 #endif 685 napi_complete(napi); 686 qmgr_enable_irq(rxq); 687 if (!qmgr_stat_empty(rxq) && 688 napi_reschedule(napi)) { 689 #if DEBUG_RX 690 printk(KERN_DEBUG "%s: hss_hdlc_poll" 691 " napi_reschedule succeeded\n", 692 dev->name); 693 #endif 694 qmgr_disable_irq(rxq); 695 continue; 696 } 697 #if DEBUG_RX 698 printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n", 699 dev->name); 700 #endif 701 return received; /* all work done */ 702 } 703 704 desc = rx_desc_ptr(port, n); 705 #if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */ 706 if (desc->error_count) 707 printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X" 708 " errors %u\n", dev->name, desc->status, 709 desc->error_count); 710 #endif 711 skb = NULL; 712 switch (desc->status) { 713 case 0: 714 #ifdef __ARMEB__ 715 skb = netdev_alloc_skb(dev, RX_SIZE); 716 if (skb) { 717 phys = dma_map_single(&dev->dev, skb->data, 718 RX_SIZE, 719 DMA_FROM_DEVICE); 720 if (dma_mapping_error(&dev->dev, phys)) { 721 dev_kfree_skb(skb); 722 skb = NULL; 723 } 724 } 725 #else 726 skb = netdev_alloc_skb(dev, desc->pkt_len); 727 #endif 728 if (!skb) 729 dev->stats.rx_dropped++; 730 break; 731 case ERR_HDLC_ALIGN: 732 case ERR_HDLC_ABORT: 733 dev->stats.rx_frame_errors++; 734 dev->stats.rx_errors++; 735 break; 736 case ERR_HDLC_FCS: 737 dev->stats.rx_crc_errors++; 738 dev->stats.rx_errors++; 739 break; 740 case ERR_HDLC_TOO_LONG: 741 dev->stats.rx_length_errors++; 742 dev->stats.rx_errors++; 743 break; 744 default: /* FIXME - remove printk */ 745 netdev_err(dev, "hss_hdlc_poll: status 0x%02X errors %u\n", 746 desc->status, desc->error_count); 747 dev->stats.rx_errors++; 748 } 749 750 if (!skb) { 751 /* put the desc back on RX-ready queue */ 752 desc->buf_len = RX_SIZE; 753 desc->pkt_len = desc->status = 0; 754 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); 755 continue; 756 } 757 758 /* process received frame */ 759 #ifdef __ARMEB__ 760 temp = skb; 761 skb = port->rx_buff_tab[n]; 762 dma_unmap_single(&dev->dev, desc->data, 763 RX_SIZE, DMA_FROM_DEVICE); 764 #else 765 dma_sync_single_for_cpu(&dev->dev, desc->data, 766 RX_SIZE, DMA_FROM_DEVICE); 767 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], 768 ALIGN(desc->pkt_len, 4) / 4); 769 #endif 770 skb_put(skb, desc->pkt_len); 771 772 debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len); 773 774 skb->protocol = hdlc_type_trans(skb, dev); 775 dev->stats.rx_packets++; 776 dev->stats.rx_bytes += skb->len; 777 netif_receive_skb(skb); 778 779 /* put the new buffer on RX-free queue */ 780 #ifdef __ARMEB__ 781 port->rx_buff_tab[n] = temp; 782 desc->data = phys; 783 #endif 784 desc->buf_len = RX_SIZE; 785 desc->pkt_len = 0; 786 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); 787 received++; 788 } 789 #if DEBUG_RX 790 printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n"); 791 #endif 792 return received; /* not all work done */ 793 } 794 795 static void hss_hdlc_txdone_irq(void *pdev) 796 { 797 struct net_device *dev = pdev; 798 struct port *port = dev_to_port(dev); 799 int n_desc; 800 801 #if DEBUG_TX 802 printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n"); 803 #endif 804 while ((n_desc = queue_get_desc(port->txdoneq, 805 port, 1)) >= 0) { 806 struct desc *desc; 807 int start; 808 809 desc = tx_desc_ptr(port, n_desc); 810 811 dev->stats.tx_packets++; 812 dev->stats.tx_bytes += desc->pkt_len; 813 814 dma_unmap_tx(port, desc); 815 #if DEBUG_TX 816 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n", 817 dev->name, port->tx_buff_tab[n_desc]); 818 #endif 819 free_buffer_irq(port->tx_buff_tab[n_desc]); 820 port->tx_buff_tab[n_desc] = NULL; 821 822 start = qmgr_stat_below_low_watermark(port->txreadyq); 823 queue_put_desc(port->txreadyq, 824 tx_desc_phys(port, n_desc), desc); 825 if (start) { /* TX-ready queue was empty */ 826 #if DEBUG_TX 827 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit" 828 " ready\n", dev->name); 829 #endif 830 netif_wake_queue(dev); 831 } 832 } 833 } 834 835 static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev) 836 { 837 struct port *port = dev_to_port(dev); 838 unsigned int txreadyq = port->txreadyq; 839 int len, offset, bytes, n; 840 void *mem; 841 u32 phys; 842 struct desc *desc; 843 844 #if DEBUG_TX 845 printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name); 846 #endif 847 848 if (unlikely(skb->len > HDLC_MAX_MRU)) { 849 dev_kfree_skb(skb); 850 dev->stats.tx_errors++; 851 return NETDEV_TX_OK; 852 } 853 854 debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len); 855 856 len = skb->len; 857 #ifdef __ARMEB__ 858 offset = 0; /* no need to keep alignment */ 859 bytes = len; 860 mem = skb->data; 861 #else 862 offset = (int)skb->data & 3; /* keep 32-bit alignment */ 863 bytes = ALIGN(offset + len, 4); 864 mem = kmalloc(bytes, GFP_ATOMIC); 865 if (!mem) { 866 dev_kfree_skb(skb); 867 dev->stats.tx_dropped++; 868 return NETDEV_TX_OK; 869 } 870 memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4); 871 dev_kfree_skb(skb); 872 #endif 873 874 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); 875 if (dma_mapping_error(&dev->dev, phys)) { 876 #ifdef __ARMEB__ 877 dev_kfree_skb(skb); 878 #else 879 kfree(mem); 880 #endif 881 dev->stats.tx_dropped++; 882 return NETDEV_TX_OK; 883 } 884 885 n = queue_get_desc(txreadyq, port, 1); 886 BUG_ON(n < 0); 887 desc = tx_desc_ptr(port, n); 888 889 #ifdef __ARMEB__ 890 port->tx_buff_tab[n] = skb; 891 #else 892 port->tx_buff_tab[n] = mem; 893 #endif 894 desc->data = phys + offset; 895 desc->buf_len = desc->pkt_len = len; 896 897 wmb(); 898 queue_put_desc(port->txq, tx_desc_phys(port, n), desc); 899 900 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */ 901 #if DEBUG_TX 902 printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name); 903 #endif 904 netif_stop_queue(dev); 905 /* we could miss TX ready interrupt */ 906 if (!qmgr_stat_below_low_watermark(txreadyq)) { 907 #if DEBUG_TX 908 printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n", 909 dev->name); 910 #endif 911 netif_wake_queue(dev); 912 } 913 } 914 915 #if DEBUG_TX 916 printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name); 917 #endif 918 return NETDEV_TX_OK; 919 } 920 921 static int request_hdlc_queues(struct port *port) 922 { 923 int err; 924 925 err = qmgr_request_queue(port->rxfreeq, RX_DESCS, 0, 0, 926 "%s:RX-free", port->netdev->name); 927 if (err) 928 return err; 929 930 err = qmgr_request_queue(port->rxq, RX_DESCS, 0, 0, 931 "%s:RX", port->netdev->name); 932 if (err) 933 goto rel_rxfree; 934 935 err = qmgr_request_queue(port->txq, TX_DESCS, 0, 0, 936 "%s:TX", port->netdev->name); 937 if (err) 938 goto rel_rx; 939 940 err = qmgr_request_queue(port->txreadyq, TX_DESCS, 0, 0, 941 "%s:TX-ready", port->netdev->name); 942 if (err) 943 goto rel_tx; 944 945 err = qmgr_request_queue(port->txdoneq, TX_DESCS, 0, 0, 946 "%s:TX-done", port->netdev->name); 947 if (err) 948 goto rel_txready; 949 return 0; 950 951 rel_txready: 952 qmgr_release_queue(port->txreadyq); 953 rel_tx: 954 qmgr_release_queue(port->txq); 955 rel_rx: 956 qmgr_release_queue(port->rxq); 957 rel_rxfree: 958 qmgr_release_queue(port->rxfreeq); 959 printk(KERN_DEBUG "%s: unable to request hardware queues\n", 960 port->netdev->name); 961 return err; 962 } 963 964 static void release_hdlc_queues(struct port *port) 965 { 966 qmgr_release_queue(port->rxfreeq); 967 qmgr_release_queue(port->rxq); 968 qmgr_release_queue(port->txdoneq); 969 qmgr_release_queue(port->txq); 970 qmgr_release_queue(port->txreadyq); 971 } 972 973 static int init_hdlc_queues(struct port *port) 974 { 975 int i; 976 977 if (!ports_open) { 978 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev, 979 POOL_ALLOC_SIZE, 32, 0); 980 if (!dma_pool) 981 return -ENOMEM; 982 } 983 984 port->desc_tab = dma_pool_zalloc(dma_pool, GFP_KERNEL, 985 &port->desc_tab_phys); 986 if (!port->desc_tab) 987 return -ENOMEM; 988 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */ 989 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab)); 990 991 /* Setup RX buffers */ 992 for (i = 0; i < RX_DESCS; i++) { 993 struct desc *desc = rx_desc_ptr(port, i); 994 buffer_t *buff; 995 void *data; 996 #ifdef __ARMEB__ 997 buff = netdev_alloc_skb(port->netdev, RX_SIZE); 998 if (!buff) 999 return -ENOMEM; 1000 data = buff->data; 1001 #else 1002 buff = kmalloc(RX_SIZE, GFP_KERNEL); 1003 if (!buff) 1004 return -ENOMEM; 1005 data = buff; 1006 #endif 1007 desc->buf_len = RX_SIZE; 1008 desc->data = dma_map_single(&port->netdev->dev, data, 1009 RX_SIZE, DMA_FROM_DEVICE); 1010 if (dma_mapping_error(&port->netdev->dev, desc->data)) { 1011 free_buffer(buff); 1012 return -EIO; 1013 } 1014 port->rx_buff_tab[i] = buff; 1015 } 1016 1017 return 0; 1018 } 1019 1020 static void destroy_hdlc_queues(struct port *port) 1021 { 1022 int i; 1023 1024 if (port->desc_tab) { 1025 for (i = 0; i < RX_DESCS; i++) { 1026 struct desc *desc = rx_desc_ptr(port, i); 1027 buffer_t *buff = port->rx_buff_tab[i]; 1028 1029 if (buff) { 1030 dma_unmap_single(&port->netdev->dev, 1031 desc->data, RX_SIZE, 1032 DMA_FROM_DEVICE); 1033 free_buffer(buff); 1034 } 1035 } 1036 for (i = 0; i < TX_DESCS; i++) { 1037 struct desc *desc = tx_desc_ptr(port, i); 1038 buffer_t *buff = port->tx_buff_tab[i]; 1039 1040 if (buff) { 1041 dma_unmap_tx(port, desc); 1042 free_buffer(buff); 1043 } 1044 } 1045 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys); 1046 port->desc_tab = NULL; 1047 } 1048 1049 if (!ports_open && dma_pool) { 1050 dma_pool_destroy(dma_pool); 1051 dma_pool = NULL; 1052 } 1053 } 1054 1055 static irqreturn_t hss_hdlc_dcd_irq(int irq, void *data) 1056 { 1057 struct net_device *dev = data; 1058 struct port *port = dev_to_port(dev); 1059 int val; 1060 1061 val = gpiod_get_value(port->dcd); 1062 hss_hdlc_set_carrier(dev, val); 1063 1064 return IRQ_HANDLED; 1065 } 1066 1067 static int hss_hdlc_open(struct net_device *dev) 1068 { 1069 struct port *port = dev_to_port(dev); 1070 unsigned long flags; 1071 int i, err = 0; 1072 int val; 1073 1074 err = hdlc_open(dev); 1075 if (err) 1076 return err; 1077 1078 err = hss_load_firmware(port); 1079 if (err) 1080 goto err_hdlc_close; 1081 1082 err = request_hdlc_queues(port); 1083 if (err) 1084 goto err_hdlc_close; 1085 1086 err = init_hdlc_queues(port); 1087 if (err) 1088 goto err_destroy_queues; 1089 1090 spin_lock_irqsave(&npe_lock, flags); 1091 1092 /* Set the carrier, the GPIO is flagged active low so this will return 1093 * 1 if DCD is asserted. 1094 */ 1095 val = gpiod_get_value(port->dcd); 1096 hss_hdlc_set_carrier(dev, val); 1097 1098 /* Set up an IRQ for DCD */ 1099 err = request_irq(gpiod_to_irq(port->dcd), hss_hdlc_dcd_irq, 0, "IXP4xx HSS", dev); 1100 if (err) { 1101 dev_err(&dev->dev, "ixp4xx_hss: failed to request DCD IRQ (%i)\n", err); 1102 goto err_unlock; 1103 } 1104 1105 /* GPIOs are flagged active low so this asserts DTR and RTS */ 1106 gpiod_set_value(port->dtr, 1); 1107 gpiod_set_value(port->rts, 1); 1108 1109 spin_unlock_irqrestore(&npe_lock, flags); 1110 1111 /* Populate queues with buffers, no failure after this point */ 1112 for (i = 0; i < TX_DESCS; i++) 1113 queue_put_desc(port->txreadyq, 1114 tx_desc_phys(port, i), tx_desc_ptr(port, i)); 1115 1116 for (i = 0; i < RX_DESCS; i++) 1117 queue_put_desc(port->rxfreeq, 1118 rx_desc_phys(port, i), rx_desc_ptr(port, i)); 1119 1120 napi_enable(&port->napi); 1121 netif_start_queue(dev); 1122 1123 qmgr_set_irq(port->rxq, QUEUE_IRQ_SRC_NOT_EMPTY, 1124 hss_hdlc_rx_irq, dev); 1125 1126 qmgr_set_irq(port->txdoneq, QUEUE_IRQ_SRC_NOT_EMPTY, 1127 hss_hdlc_txdone_irq, dev); 1128 qmgr_enable_irq(port->txdoneq); 1129 1130 ports_open++; 1131 1132 hss_set_hdlc_cfg(port); 1133 hss_config(port); 1134 1135 hss_start_hdlc(port); 1136 1137 /* we may already have RX data, enables IRQ */ 1138 napi_schedule(&port->napi); 1139 return 0; 1140 1141 err_unlock: 1142 spin_unlock_irqrestore(&npe_lock, flags); 1143 err_destroy_queues: 1144 destroy_hdlc_queues(port); 1145 release_hdlc_queues(port); 1146 err_hdlc_close: 1147 hdlc_close(dev); 1148 return err; 1149 } 1150 1151 static int hss_hdlc_close(struct net_device *dev) 1152 { 1153 struct port *port = dev_to_port(dev); 1154 unsigned long flags; 1155 int i, buffs = RX_DESCS; /* allocated RX buffers */ 1156 1157 spin_lock_irqsave(&npe_lock, flags); 1158 ports_open--; 1159 qmgr_disable_irq(port->rxq); 1160 netif_stop_queue(dev); 1161 napi_disable(&port->napi); 1162 1163 hss_stop_hdlc(port); 1164 1165 while (queue_get_desc(port->rxfreeq, port, 0) >= 0) 1166 buffs--; 1167 while (queue_get_desc(port->rxq, port, 0) >= 0) 1168 buffs--; 1169 1170 if (buffs) 1171 netdev_crit(dev, "unable to drain RX queue, %i buffer(s) left in NPE\n", 1172 buffs); 1173 1174 buffs = TX_DESCS; 1175 while (queue_get_desc(port->txq, port, 1) >= 0) 1176 buffs--; /* cancel TX */ 1177 1178 i = 0; 1179 do { 1180 while (queue_get_desc(port->txreadyq, port, 1) >= 0) 1181 buffs--; 1182 if (!buffs) 1183 break; 1184 } while (++i < MAX_CLOSE_WAIT); 1185 1186 if (buffs) 1187 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) left in NPE\n", 1188 buffs); 1189 #if DEBUG_CLOSE 1190 if (!buffs) 1191 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i); 1192 #endif 1193 qmgr_disable_irq(port->txdoneq); 1194 1195 free_irq(gpiod_to_irq(port->dcd), dev); 1196 /* GPIOs are flagged active low so this de-asserts DTR and RTS */ 1197 gpiod_set_value(port->dtr, 0); 1198 gpiod_set_value(port->rts, 0); 1199 spin_unlock_irqrestore(&npe_lock, flags); 1200 1201 destroy_hdlc_queues(port); 1202 release_hdlc_queues(port); 1203 hdlc_close(dev); 1204 return 0; 1205 } 1206 1207 static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding, 1208 unsigned short parity) 1209 { 1210 struct port *port = dev_to_port(dev); 1211 1212 if (encoding != ENCODING_NRZ) 1213 return -EINVAL; 1214 1215 switch (parity) { 1216 case PARITY_CRC16_PR1_CCITT: 1217 port->hdlc_cfg = 0; 1218 return 0; 1219 1220 case PARITY_CRC32_PR1_CCITT: 1221 port->hdlc_cfg = PKT_HDLC_CRC_32; 1222 return 0; 1223 1224 default: 1225 return -EINVAL; 1226 } 1227 } 1228 1229 static u32 check_clock(u32 timer_freq, u32 rate, u32 a, u32 b, u32 c, 1230 u32 *best, u32 *best_diff, u32 *reg) 1231 { 1232 /* a is 10-bit, b is 10-bit, c is 12-bit */ 1233 u64 new_rate; 1234 u32 new_diff; 1235 1236 new_rate = timer_freq * (u64)(c + 1); 1237 do_div(new_rate, a * (c + 1) + b + 1); 1238 new_diff = abs((u32)new_rate - rate); 1239 1240 if (new_diff < *best_diff) { 1241 *best = new_rate; 1242 *best_diff = new_diff; 1243 *reg = (a << 22) | (b << 12) | c; 1244 } 1245 return new_diff; 1246 } 1247 1248 static void find_best_clock(u32 timer_freq, u32 rate, u32 *best, u32 *reg) 1249 { 1250 u32 a, b, diff = 0xFFFFFFFF; 1251 1252 a = timer_freq / rate; 1253 1254 if (a > 0x3FF) { /* 10-bit value - we can go as slow as ca. 65 kb/s */ 1255 check_clock(timer_freq, rate, 0x3FF, 1, 1, best, &diff, reg); 1256 return; 1257 } 1258 if (a == 0) { /* > 66.666 MHz */ 1259 a = 1; /* minimum divider is 1 (a = 0, b = 1, c = 1) */ 1260 rate = timer_freq; 1261 } 1262 1263 if (rate * a == timer_freq) { /* don't divide by 0 later */ 1264 check_clock(timer_freq, rate, a - 1, 1, 1, best, &diff, reg); 1265 return; 1266 } 1267 1268 for (b = 0; b < 0x400; b++) { 1269 u64 c = (b + 1) * (u64)rate; 1270 1271 do_div(c, timer_freq - rate * a); 1272 c--; 1273 if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */ 1274 if (b == 0 && /* also try a bit higher rate */ 1275 !check_clock(timer_freq, rate, a - 1, 1, 1, best, 1276 &diff, reg)) 1277 return; 1278 check_clock(timer_freq, rate, a, b, 0xFFF, best, 1279 &diff, reg); 1280 return; 1281 } 1282 if (!check_clock(timer_freq, rate, a, b, c, best, &diff, reg)) 1283 return; 1284 if (!check_clock(timer_freq, rate, a, b, c + 1, best, &diff, 1285 reg)) 1286 return; 1287 } 1288 } 1289 1290 static int hss_hdlc_set_clock(struct port *port, unsigned int clock_type) 1291 { 1292 switch (clock_type) { 1293 case CLOCK_DEFAULT: 1294 case CLOCK_EXT: 1295 gpiod_set_value(port->clk_internal, 0); 1296 return CLOCK_EXT; 1297 case CLOCK_INT: 1298 gpiod_set_value(port->clk_internal, 1); 1299 return CLOCK_INT; 1300 default: 1301 return -EINVAL; 1302 } 1303 } 1304 1305 static int hss_hdlc_ioctl(struct net_device *dev, struct if_settings *ifs) 1306 { 1307 const size_t size = sizeof(sync_serial_settings); 1308 sync_serial_settings new_line; 1309 sync_serial_settings __user *line = ifs->ifs_ifsu.sync; 1310 struct port *port = dev_to_port(dev); 1311 unsigned long flags; 1312 int clk; 1313 1314 switch (ifs->type) { 1315 case IF_GET_IFACE: 1316 ifs->type = IF_IFACE_V35; 1317 if (ifs->size < size) { 1318 ifs->size = size; /* data size wanted */ 1319 return -ENOBUFS; 1320 } 1321 memset(&new_line, 0, sizeof(new_line)); 1322 new_line.clock_type = port->clock_type; 1323 new_line.clock_rate = port->clock_rate; 1324 new_line.loopback = port->loopback; 1325 if (copy_to_user(line, &new_line, size)) 1326 return -EFAULT; 1327 return 0; 1328 1329 case IF_IFACE_SYNC_SERIAL: 1330 case IF_IFACE_V35: 1331 if (!capable(CAP_NET_ADMIN)) 1332 return -EPERM; 1333 if (copy_from_user(&new_line, line, size)) 1334 return -EFAULT; 1335 1336 clk = new_line.clock_type; 1337 hss_hdlc_set_clock(port, clk); 1338 1339 if (clk != CLOCK_EXT && clk != CLOCK_INT) 1340 return -EINVAL; /* No such clock setting */ 1341 1342 if (new_line.loopback != 0 && new_line.loopback != 1) 1343 return -EINVAL; 1344 1345 port->clock_type = clk; /* Update settings */ 1346 if (clk == CLOCK_INT) { 1347 find_best_clock(IXP4XX_TIMER_FREQ, 1348 new_line.clock_rate, 1349 &port->clock_rate, &port->clock_reg); 1350 } else { 1351 port->clock_rate = 0; 1352 port->clock_reg = CLK42X_SPEED_2048KHZ; 1353 } 1354 port->loopback = new_line.loopback; 1355 1356 spin_lock_irqsave(&npe_lock, flags); 1357 1358 if (dev->flags & IFF_UP) 1359 hss_config(port); 1360 1361 if (port->loopback || port->carrier) 1362 netif_carrier_on(port->netdev); 1363 else 1364 netif_carrier_off(port->netdev); 1365 spin_unlock_irqrestore(&npe_lock, flags); 1366 1367 return 0; 1368 1369 default: 1370 return hdlc_ioctl(dev, ifs); 1371 } 1372 } 1373 1374 /***************************************************************************** 1375 * initialization 1376 ****************************************************************************/ 1377 1378 static const struct net_device_ops hss_hdlc_ops = { 1379 .ndo_open = hss_hdlc_open, 1380 .ndo_stop = hss_hdlc_close, 1381 .ndo_start_xmit = hdlc_start_xmit, 1382 .ndo_siocwandev = hss_hdlc_ioctl, 1383 }; 1384 1385 static int ixp4xx_hss_probe(struct platform_device *pdev) 1386 { 1387 struct of_phandle_args queue_spec; 1388 struct of_phandle_args npe_spec; 1389 struct device *dev = &pdev->dev; 1390 struct net_device *ndev; 1391 struct device_node *np; 1392 struct port *port; 1393 hdlc_device *hdlc; 1394 int err; 1395 1396 np = dev->of_node; 1397 1398 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 1399 if (!port) 1400 return -ENOMEM; 1401 1402 err = of_parse_phandle_with_fixed_args(np, "intel,npe-handle", 1, 0, 1403 &npe_spec); 1404 if (err) 1405 return dev_err_probe(dev, err, "no NPE engine specified\n"); 1406 /* NPE ID 0x00, 0x10, 0x20... */ 1407 port->npe = npe_request(npe_spec.args[0] << 4); 1408 if (!port->npe) { 1409 dev_err(dev, "unable to obtain NPE instance\n"); 1410 return -ENODEV; 1411 } 1412 1413 /* Get the TX ready queue as resource from queue manager */ 1414 err = of_parse_phandle_with_fixed_args(np, "intek,queue-chl-txready", 1, 0, 1415 &queue_spec); 1416 if (err) 1417 return dev_err_probe(dev, err, "no txready queue phandle\n"); 1418 port->txreadyq = queue_spec.args[0]; 1419 /* Get the RX trig queue as resource from queue manager */ 1420 err = of_parse_phandle_with_fixed_args(np, "intek,queue-chl-rxtrig", 1, 0, 1421 &queue_spec); 1422 if (err) 1423 return dev_err_probe(dev, err, "no rxtrig queue phandle\n"); 1424 port->rxtrigq = queue_spec.args[0]; 1425 /* Get the RX queue as resource from queue manager */ 1426 err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-rx", 1, 0, 1427 &queue_spec); 1428 if (err) 1429 return dev_err_probe(dev, err, "no RX queue phandle\n"); 1430 port->rxq = queue_spec.args[0]; 1431 /* Get the TX queue as resource from queue manager */ 1432 err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-tx", 1, 0, 1433 &queue_spec); 1434 if (err) 1435 return dev_err_probe(dev, err, "no RX queue phandle\n"); 1436 port->txq = queue_spec.args[0]; 1437 /* Get the RX free queue as resource from queue manager */ 1438 err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-rxfree", 1, 0, 1439 &queue_spec); 1440 if (err) 1441 return dev_err_probe(dev, err, "no RX free queue phandle\n"); 1442 port->rxfreeq = queue_spec.args[0]; 1443 /* Get the TX done queue as resource from queue manager */ 1444 err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-txdone", 1, 0, 1445 &queue_spec); 1446 if (err) 1447 return dev_err_probe(dev, err, "no TX done queue phandle\n"); 1448 port->txdoneq = queue_spec.args[0]; 1449 1450 /* Obtain all the line control GPIOs */ 1451 port->cts = devm_gpiod_get(dev, "cts", GPIOD_OUT_LOW); 1452 if (IS_ERR(port->cts)) 1453 return dev_err_probe(dev, PTR_ERR(port->cts), "unable to get CTS GPIO\n"); 1454 port->rts = devm_gpiod_get(dev, "rts", GPIOD_OUT_LOW); 1455 if (IS_ERR(port->rts)) 1456 return dev_err_probe(dev, PTR_ERR(port->rts), "unable to get RTS GPIO\n"); 1457 port->dcd = devm_gpiod_get(dev, "dcd", GPIOD_IN); 1458 if (IS_ERR(port->dcd)) 1459 return dev_err_probe(dev, PTR_ERR(port->dcd), "unable to get DCD GPIO\n"); 1460 port->dtr = devm_gpiod_get(dev, "dtr", GPIOD_OUT_LOW); 1461 if (IS_ERR(port->dtr)) 1462 return dev_err_probe(dev, PTR_ERR(port->dtr), "unable to get DTR GPIO\n"); 1463 port->clk_internal = devm_gpiod_get(dev, "clk-internal", GPIOD_OUT_LOW); 1464 if (IS_ERR(port->clk_internal)) 1465 return dev_err_probe(dev, PTR_ERR(port->clk_internal), 1466 "unable to get CLK internal GPIO\n"); 1467 1468 ndev = alloc_hdlcdev(port); 1469 port->netdev = alloc_hdlcdev(port); 1470 if (!port->netdev) { 1471 err = -ENOMEM; 1472 goto err_plat; 1473 } 1474 1475 SET_NETDEV_DEV(ndev, &pdev->dev); 1476 hdlc = dev_to_hdlc(ndev); 1477 hdlc->attach = hss_hdlc_attach; 1478 hdlc->xmit = hss_hdlc_xmit; 1479 ndev->netdev_ops = &hss_hdlc_ops; 1480 ndev->tx_queue_len = 100; 1481 port->clock_type = CLOCK_EXT; 1482 port->clock_rate = 0; 1483 port->clock_reg = CLK42X_SPEED_2048KHZ; 1484 port->id = pdev->id; 1485 port->dev = &pdev->dev; 1486 netif_napi_add(ndev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT); 1487 1488 err = register_hdlc_device(ndev); 1489 if (err) 1490 goto err_free_netdev; 1491 1492 platform_set_drvdata(pdev, port); 1493 1494 netdev_info(ndev, "initialized\n"); 1495 return 0; 1496 1497 err_free_netdev: 1498 free_netdev(ndev); 1499 err_plat: 1500 npe_release(port->npe); 1501 return err; 1502 } 1503 1504 static int ixp4xx_hss_remove(struct platform_device *pdev) 1505 { 1506 struct port *port = platform_get_drvdata(pdev); 1507 1508 unregister_hdlc_device(port->netdev); 1509 free_netdev(port->netdev); 1510 npe_release(port->npe); 1511 return 0; 1512 } 1513 1514 static struct platform_driver ixp4xx_hss_driver = { 1515 .driver.name = DRV_NAME, 1516 .probe = ixp4xx_hss_probe, 1517 .remove = ixp4xx_hss_remove, 1518 }; 1519 1520 static int __init hss_init_module(void) 1521 { 1522 if ((ixp4xx_read_feature_bits() & 1523 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) != 1524 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) 1525 return -ENODEV; 1526 1527 return platform_driver_register(&ixp4xx_hss_driver); 1528 } 1529 1530 static void __exit hss_cleanup_module(void) 1531 { 1532 platform_driver_unregister(&ixp4xx_hss_driver); 1533 } 1534 1535 MODULE_AUTHOR("Krzysztof Halasa"); 1536 MODULE_DESCRIPTION("Intel IXP4xx HSS driver"); 1537 MODULE_LICENSE("GPL v2"); 1538 MODULE_ALIAS("platform:ixp4xx_hss"); 1539 module_init(hss_init_module); 1540 module_exit(hss_cleanup_module); 1541