1 /* 2 * Intel IXP4xx HSS (synchronous serial port) driver for Linux 3 * 4 * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License 8 * as published by the Free Software Foundation. 9 */ 10 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/bitops.h> 14 #include <linux/cdev.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/dmapool.h> 17 #include <linux/fs.h> 18 #include <linux/hdlc.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/platform_device.h> 22 #include <linux/poll.h> 23 #include <linux/slab.h> 24 #include <mach/npe.h> 25 #include <mach/qmgr.h> 26 27 #define DEBUG_DESC 0 28 #define DEBUG_RX 0 29 #define DEBUG_TX 0 30 #define DEBUG_PKT_BYTES 0 31 #define DEBUG_CLOSE 0 32 33 #define DRV_NAME "ixp4xx_hss" 34 35 #define PKT_EXTRA_FLAGS 0 /* orig 1 */ 36 #define PKT_NUM_PIPES 1 /* 1, 2 or 4 */ 37 #define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */ 38 39 #define RX_DESCS 16 /* also length of all RX queues */ 40 #define TX_DESCS 16 /* also length of all TX queues */ 41 42 #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) 43 #define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */ 44 #define MAX_CLOSE_WAIT 1000 /* microseconds */ 45 #define HSS_COUNT 2 46 #define FRAME_SIZE 256 /* doesn't matter at this point */ 47 #define FRAME_OFFSET 0 48 #define MAX_CHANNELS (FRAME_SIZE / 8) 49 50 #define NAPI_WEIGHT 16 51 52 /* Queue IDs */ 53 #define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */ 54 #define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */ 55 #define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */ 56 #define HSS0_PKT_TX1_QUEUE 15 57 #define HSS0_PKT_TX2_QUEUE 16 58 #define HSS0_PKT_TX3_QUEUE 17 59 #define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */ 60 #define HSS0_PKT_RXFREE1_QUEUE 19 61 #define HSS0_PKT_RXFREE2_QUEUE 20 62 #define HSS0_PKT_RXFREE3_QUEUE 21 63 #define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */ 64 65 #define HSS1_CHL_RXTRIG_QUEUE 10 66 #define HSS1_PKT_RX_QUEUE 0 67 #define HSS1_PKT_TX0_QUEUE 5 68 #define HSS1_PKT_TX1_QUEUE 6 69 #define HSS1_PKT_TX2_QUEUE 7 70 #define HSS1_PKT_TX3_QUEUE 8 71 #define HSS1_PKT_RXFREE0_QUEUE 1 72 #define HSS1_PKT_RXFREE1_QUEUE 2 73 #define HSS1_PKT_RXFREE2_QUEUE 3 74 #define HSS1_PKT_RXFREE3_QUEUE 4 75 #define HSS1_PKT_TXDONE_QUEUE 9 76 77 #define NPE_PKT_MODE_HDLC 0 78 #define NPE_PKT_MODE_RAW 1 79 #define NPE_PKT_MODE_56KMODE 2 80 #define NPE_PKT_MODE_56KENDIAN_MSB 4 81 82 /* PKT_PIPE_HDLC_CFG_WRITE flags */ 83 #define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */ 84 #define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */ 85 #define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */ 86 87 88 /* hss_config, PCRs */ 89 /* Frame sync sampling, default = active low */ 90 #define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000 91 #define PCR_FRM_SYNC_FALLINGEDGE 0x80000000 92 #define PCR_FRM_SYNC_RISINGEDGE 0xC0000000 93 94 /* Frame sync pin: input (default) or output generated off a given clk edge */ 95 #define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000 96 #define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000 97 98 /* Frame and data clock sampling on edge, default = falling */ 99 #define PCR_FCLK_EDGE_RISING 0x08000000 100 #define PCR_DCLK_EDGE_RISING 0x04000000 101 102 /* Clock direction, default = input */ 103 #define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000 104 105 /* Generate/Receive frame pulses, default = enabled */ 106 #define PCR_FRM_PULSE_DISABLED 0x01000000 107 108 /* Data rate is full (default) or half the configured clk speed */ 109 #define PCR_HALF_CLK_RATE 0x00200000 110 111 /* Invert data between NPE and HSS FIFOs? (default = no) */ 112 #define PCR_DATA_POLARITY_INVERT 0x00100000 113 114 /* TX/RX endianness, default = LSB */ 115 #define PCR_MSB_ENDIAN 0x00080000 116 117 /* Normal (default) / open drain mode (TX only) */ 118 #define PCR_TX_PINS_OPEN_DRAIN 0x00040000 119 120 /* No framing bit transmitted and expected on RX? (default = framing bit) */ 121 #define PCR_SOF_NO_FBIT 0x00020000 122 123 /* Drive data pins? */ 124 #define PCR_TX_DATA_ENABLE 0x00010000 125 126 /* Voice 56k type: drive the data pins low (default), high, high Z */ 127 #define PCR_TX_V56K_HIGH 0x00002000 128 #define PCR_TX_V56K_HIGH_IMP 0x00004000 129 130 /* Unassigned type: drive the data pins low (default), high, high Z */ 131 #define PCR_TX_UNASS_HIGH 0x00000800 132 #define PCR_TX_UNASS_HIGH_IMP 0x00001000 133 134 /* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */ 135 #define PCR_TX_FB_HIGH_IMP 0x00000400 136 137 /* 56k data endiannes - which bit unused: high (default) or low */ 138 #define PCR_TX_56KE_BIT_0_UNUSED 0x00000200 139 140 /* 56k data transmission type: 32/8 bit data (default) or 56K data */ 141 #define PCR_TX_56KS_56K_DATA 0x00000100 142 143 /* hss_config, cCR */ 144 /* Number of packetized clients, default = 1 */ 145 #define CCR_NPE_HFIFO_2_HDLC 0x04000000 146 #define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000 147 148 /* default = no loopback */ 149 #define CCR_LOOPBACK 0x02000000 150 151 /* HSS number, default = 0 (first) */ 152 #define CCR_SECOND_HSS 0x01000000 153 154 155 /* hss_config, clkCR: main:10, num:10, denom:12 */ 156 #define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/ 157 158 #define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15) 159 #define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47) 160 #define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192) 161 #define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63) 162 #define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127) 163 #define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255) 164 165 #define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127) 166 #define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383) 167 #define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385) 168 #define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511) 169 #define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023) 170 #define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047) 171 172 /* 173 * HSS_CONFIG_CLOCK_CR register consists of 3 parts: 174 * A (10 bits), B (10 bits) and C (12 bits). 175 * IXP42x HSS clock generator operation (verified with an oscilloscope): 176 * Each clock bit takes 7.5 ns (1 / 133.xx MHz). 177 * The clock sequence consists of (C - B) states of 0s and 1s, each state is 178 * A bits wide. It's followed by (B + 1) states of 0s and 1s, each state is 179 * (A + 1) bits wide. 180 * 181 * The resulting average clock frequency (assuming 33.333 MHz oscillator) is: 182 * freq = 66.666 MHz / (A + (B + 1) / (C + 1)) 183 * minimum freq = 66.666 MHz / (A + 1) 184 * maximum freq = 66.666 MHz / A 185 * 186 * Example: A = 2, B = 2, C = 7, CLOCK_CR register = 2 << 22 | 2 << 12 | 7 187 * freq = 66.666 MHz / (2 + (2 + 1) / (7 + 1)) = 28.07 MHz (Mb/s). 188 * The clock sequence is: 1100110011 (5 doubles) 000111000 (3 triples). 189 * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits 190 * = 19 bits (each 7.5 ns long) = 142.5 ns (then the sequence repeats). 191 * The sequence consists of 4 complete clock periods, thus the average 192 * frequency (= clock rate) is 4 / 142.5 ns = 28.07 MHz (Mb/s). 193 * (max specified clock rate for IXP42x HSS is 8.192 Mb/s). 194 */ 195 196 /* hss_config, LUT entries */ 197 #define TDMMAP_UNASSIGNED 0 198 #define TDMMAP_HDLC 1 /* HDLC - packetized */ 199 #define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */ 200 #define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */ 201 202 /* offsets into HSS config */ 203 #define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */ 204 #define HSS_CONFIG_RX_PCR 0x04 205 #define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */ 206 #define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */ 207 #define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */ 208 #define HSS_CONFIG_RX_FCR 0x14 209 #define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */ 210 #define HSS_CONFIG_RX_LUT 0x38 211 212 213 /* NPE command codes */ 214 /* writes the ConfigWord value to the location specified by offset */ 215 #define PORT_CONFIG_WRITE 0x40 216 217 /* triggers the NPE to load the contents of the configuration table */ 218 #define PORT_CONFIG_LOAD 0x41 219 220 /* triggers the NPE to return an HssErrorReadResponse message */ 221 #define PORT_ERROR_READ 0x42 222 223 /* triggers the NPE to reset internal status and enable the HssPacketized 224 operation for the flow specified by pPipe */ 225 #define PKT_PIPE_FLOW_ENABLE 0x50 226 #define PKT_PIPE_FLOW_DISABLE 0x51 227 #define PKT_NUM_PIPES_WRITE 0x52 228 #define PKT_PIPE_FIFO_SIZEW_WRITE 0x53 229 #define PKT_PIPE_HDLC_CFG_WRITE 0x54 230 #define PKT_PIPE_IDLE_PATTERN_WRITE 0x55 231 #define PKT_PIPE_RX_SIZE_WRITE 0x56 232 #define PKT_PIPE_MODE_WRITE 0x57 233 234 /* HDLC packet status values - desc->status */ 235 #define ERR_SHUTDOWN 1 /* stop or shutdown occurrence */ 236 #define ERR_HDLC_ALIGN 2 /* HDLC alignment error */ 237 #define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */ 238 #define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving 239 this packet (if buf_len < pkt_len) */ 240 #define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */ 241 #define ERR_HDLC_ABORT 6 /* abort sequence received */ 242 #define ERR_DISCONNECTING 7 /* disconnect is in progress */ 243 244 245 #ifdef __ARMEB__ 246 typedef struct sk_buff buffer_t; 247 #define free_buffer dev_kfree_skb 248 #define free_buffer_irq dev_kfree_skb_irq 249 #else 250 typedef void buffer_t; 251 #define free_buffer kfree 252 #define free_buffer_irq kfree 253 #endif 254 255 struct port { 256 struct device *dev; 257 struct npe *npe; 258 struct net_device *netdev; 259 struct napi_struct napi; 260 struct hss_plat_info *plat; 261 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS]; 262 struct desc *desc_tab; /* coherent */ 263 u32 desc_tab_phys; 264 unsigned int id; 265 unsigned int clock_type, clock_rate, loopback; 266 unsigned int initialized, carrier; 267 u8 hdlc_cfg; 268 u32 clock_reg; 269 }; 270 271 /* NPE message structure */ 272 struct msg { 273 #ifdef __ARMEB__ 274 u8 cmd, unused, hss_port, index; 275 union { 276 struct { u8 data8a, data8b, data8c, data8d; }; 277 struct { u16 data16a, data16b; }; 278 struct { u32 data32; }; 279 }; 280 #else 281 u8 index, hss_port, unused, cmd; 282 union { 283 struct { u8 data8d, data8c, data8b, data8a; }; 284 struct { u16 data16b, data16a; }; 285 struct { u32 data32; }; 286 }; 287 #endif 288 }; 289 290 /* HDLC packet descriptor */ 291 struct desc { 292 u32 next; /* pointer to next buffer, unused */ 293 294 #ifdef __ARMEB__ 295 u16 buf_len; /* buffer length */ 296 u16 pkt_len; /* packet length */ 297 u32 data; /* pointer to data buffer in RAM */ 298 u8 status; 299 u8 error_count; 300 u16 __reserved; 301 #else 302 u16 pkt_len; /* packet length */ 303 u16 buf_len; /* buffer length */ 304 u32 data; /* pointer to data buffer in RAM */ 305 u16 __reserved; 306 u8 error_count; 307 u8 status; 308 #endif 309 u32 __reserved1[4]; 310 }; 311 312 313 #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ 314 (n) * sizeof(struct desc)) 315 #define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) 316 317 #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ 318 ((n) + RX_DESCS) * sizeof(struct desc)) 319 #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) 320 321 /***************************************************************************** 322 * global variables 323 ****************************************************************************/ 324 325 static int ports_open; 326 static struct dma_pool *dma_pool; 327 static spinlock_t npe_lock; 328 329 static const struct { 330 int tx, txdone, rx, rxfree; 331 }queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE, 332 HSS0_PKT_RXFREE0_QUEUE}, 333 {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE, 334 HSS1_PKT_RXFREE0_QUEUE}, 335 }; 336 337 /***************************************************************************** 338 * utility functions 339 ****************************************************************************/ 340 341 static inline struct port* dev_to_port(struct net_device *dev) 342 { 343 return dev_to_hdlc(dev)->priv; 344 } 345 346 #ifndef __ARMEB__ 347 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) 348 { 349 int i; 350 for (i = 0; i < cnt; i++) 351 dest[i] = swab32(src[i]); 352 } 353 #endif 354 355 /***************************************************************************** 356 * HSS access 357 ****************************************************************************/ 358 359 static void hss_npe_send(struct port *port, struct msg *msg, const char* what) 360 { 361 u32 *val = (u32*)msg; 362 if (npe_send_message(port->npe, msg, what)) { 363 pr_crit("HSS-%i: unable to send command [%08X:%08X] to %s\n", 364 port->id, val[0], val[1], npe_name(port->npe)); 365 BUG(); 366 } 367 } 368 369 static void hss_config_set_lut(struct port *port) 370 { 371 struct msg msg; 372 int ch; 373 374 memset(&msg, 0, sizeof(msg)); 375 msg.cmd = PORT_CONFIG_WRITE; 376 msg.hss_port = port->id; 377 378 for (ch = 0; ch < MAX_CHANNELS; ch++) { 379 msg.data32 >>= 2; 380 msg.data32 |= TDMMAP_HDLC << 30; 381 382 if (ch % 16 == 15) { 383 msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3); 384 hss_npe_send(port, &msg, "HSS_SET_TX_LUT"); 385 386 msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT; 387 hss_npe_send(port, &msg, "HSS_SET_RX_LUT"); 388 } 389 } 390 } 391 392 static void hss_config(struct port *port) 393 { 394 struct msg msg; 395 396 memset(&msg, 0, sizeof(msg)); 397 msg.cmd = PORT_CONFIG_WRITE; 398 msg.hss_port = port->id; 399 msg.index = HSS_CONFIG_TX_PCR; 400 msg.data32 = PCR_FRM_PULSE_DISABLED | PCR_MSB_ENDIAN | 401 PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT; 402 if (port->clock_type == CLOCK_INT) 403 msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT; 404 hss_npe_send(port, &msg, "HSS_SET_TX_PCR"); 405 406 msg.index = HSS_CONFIG_RX_PCR; 407 msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING; 408 hss_npe_send(port, &msg, "HSS_SET_RX_PCR"); 409 410 memset(&msg, 0, sizeof(msg)); 411 msg.cmd = PORT_CONFIG_WRITE; 412 msg.hss_port = port->id; 413 msg.index = HSS_CONFIG_CORE_CR; 414 msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) | 415 (port->id ? CCR_SECOND_HSS : 0); 416 hss_npe_send(port, &msg, "HSS_SET_CORE_CR"); 417 418 memset(&msg, 0, sizeof(msg)); 419 msg.cmd = PORT_CONFIG_WRITE; 420 msg.hss_port = port->id; 421 msg.index = HSS_CONFIG_CLOCK_CR; 422 msg.data32 = port->clock_reg; 423 hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR"); 424 425 memset(&msg, 0, sizeof(msg)); 426 msg.cmd = PORT_CONFIG_WRITE; 427 msg.hss_port = port->id; 428 msg.index = HSS_CONFIG_TX_FCR; 429 msg.data16a = FRAME_OFFSET; 430 msg.data16b = FRAME_SIZE - 1; 431 hss_npe_send(port, &msg, "HSS_SET_TX_FCR"); 432 433 memset(&msg, 0, sizeof(msg)); 434 msg.cmd = PORT_CONFIG_WRITE; 435 msg.hss_port = port->id; 436 msg.index = HSS_CONFIG_RX_FCR; 437 msg.data16a = FRAME_OFFSET; 438 msg.data16b = FRAME_SIZE - 1; 439 hss_npe_send(port, &msg, "HSS_SET_RX_FCR"); 440 441 hss_config_set_lut(port); 442 443 memset(&msg, 0, sizeof(msg)); 444 msg.cmd = PORT_CONFIG_LOAD; 445 msg.hss_port = port->id; 446 hss_npe_send(port, &msg, "HSS_LOAD_CONFIG"); 447 448 if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") || 449 /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */ 450 msg.cmd != PORT_CONFIG_LOAD || msg.data32) { 451 pr_crit("HSS-%i: HSS_LOAD_CONFIG failed\n", port->id); 452 BUG(); 453 } 454 455 /* HDLC may stop working without this - check FIXME */ 456 npe_recv_message(port->npe, &msg, "FLUSH_IT"); 457 } 458 459 static void hss_set_hdlc_cfg(struct port *port) 460 { 461 struct msg msg; 462 463 memset(&msg, 0, sizeof(msg)); 464 msg.cmd = PKT_PIPE_HDLC_CFG_WRITE; 465 msg.hss_port = port->id; 466 msg.data8a = port->hdlc_cfg; /* rx_cfg */ 467 msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */ 468 hss_npe_send(port, &msg, "HSS_SET_HDLC_CFG"); 469 } 470 471 static u32 hss_get_status(struct port *port) 472 { 473 struct msg msg; 474 475 memset(&msg, 0, sizeof(msg)); 476 msg.cmd = PORT_ERROR_READ; 477 msg.hss_port = port->id; 478 hss_npe_send(port, &msg, "PORT_ERROR_READ"); 479 if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) { 480 pr_crit("HSS-%i: unable to read HSS status\n", port->id); 481 BUG(); 482 } 483 484 return msg.data32; 485 } 486 487 static void hss_start_hdlc(struct port *port) 488 { 489 struct msg msg; 490 491 memset(&msg, 0, sizeof(msg)); 492 msg.cmd = PKT_PIPE_FLOW_ENABLE; 493 msg.hss_port = port->id; 494 msg.data32 = 0; 495 hss_npe_send(port, &msg, "HSS_ENABLE_PKT_PIPE"); 496 } 497 498 static void hss_stop_hdlc(struct port *port) 499 { 500 struct msg msg; 501 502 memset(&msg, 0, sizeof(msg)); 503 msg.cmd = PKT_PIPE_FLOW_DISABLE; 504 msg.hss_port = port->id; 505 hss_npe_send(port, &msg, "HSS_DISABLE_PKT_PIPE"); 506 hss_get_status(port); /* make sure it's halted */ 507 } 508 509 static int hss_load_firmware(struct port *port) 510 { 511 struct msg msg; 512 int err; 513 514 if (port->initialized) 515 return 0; 516 517 if (!npe_running(port->npe) && 518 (err = npe_load_firmware(port->npe, npe_name(port->npe), 519 port->dev))) 520 return err; 521 522 /* HDLC mode configuration */ 523 memset(&msg, 0, sizeof(msg)); 524 msg.cmd = PKT_NUM_PIPES_WRITE; 525 msg.hss_port = port->id; 526 msg.data8a = PKT_NUM_PIPES; 527 hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES"); 528 529 msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE; 530 msg.data8a = PKT_PIPE_FIFO_SIZEW; 531 hss_npe_send(port, &msg, "HSS_SET_PKT_FIFO"); 532 533 msg.cmd = PKT_PIPE_MODE_WRITE; 534 msg.data8a = NPE_PKT_MODE_HDLC; 535 /* msg.data8b = inv_mask */ 536 /* msg.data8c = or_mask */ 537 hss_npe_send(port, &msg, "HSS_SET_PKT_MODE"); 538 539 msg.cmd = PKT_PIPE_RX_SIZE_WRITE; 540 msg.data16a = HDLC_MAX_MRU; /* including CRC */ 541 hss_npe_send(port, &msg, "HSS_SET_PKT_RX_SIZE"); 542 543 msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE; 544 msg.data32 = 0x7F7F7F7F; /* ??? FIXME */ 545 hss_npe_send(port, &msg, "HSS_SET_PKT_IDLE"); 546 547 port->initialized = 1; 548 return 0; 549 } 550 551 /***************************************************************************** 552 * packetized (HDLC) operation 553 ****************************************************************************/ 554 555 static inline void debug_pkt(struct net_device *dev, const char *func, 556 u8 *data, int len) 557 { 558 #if DEBUG_PKT_BYTES 559 int i; 560 561 printk(KERN_DEBUG "%s: %s(%i)", dev->name, func, len); 562 for (i = 0; i < len; i++) { 563 if (i >= DEBUG_PKT_BYTES) 564 break; 565 printk("%s%02X", !(i % 4) ? " " : "", data[i]); 566 } 567 printk("\n"); 568 #endif 569 } 570 571 572 static inline void debug_desc(u32 phys, struct desc *desc) 573 { 574 #if DEBUG_DESC 575 printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n", 576 phys, desc->next, desc->buf_len, desc->pkt_len, 577 desc->data, desc->status, desc->error_count); 578 #endif 579 } 580 581 static inline int queue_get_desc(unsigned int queue, struct port *port, 582 int is_tx) 583 { 584 u32 phys, tab_phys, n_desc; 585 struct desc *tab; 586 587 if (!(phys = qmgr_get_entry(queue))) 588 return -1; 589 590 BUG_ON(phys & 0x1F); 591 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0); 592 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0); 593 n_desc = (phys - tab_phys) / sizeof(struct desc); 594 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS)); 595 debug_desc(phys, &tab[n_desc]); 596 BUG_ON(tab[n_desc].next); 597 return n_desc; 598 } 599 600 static inline void queue_put_desc(unsigned int queue, u32 phys, 601 struct desc *desc) 602 { 603 debug_desc(phys, desc); 604 BUG_ON(phys & 0x1F); 605 qmgr_put_entry(queue, phys); 606 /* Don't check for queue overflow here, we've allocated sufficient 607 length and queues >= 32 don't support this check anyway. */ 608 } 609 610 611 static inline void dma_unmap_tx(struct port *port, struct desc *desc) 612 { 613 #ifdef __ARMEB__ 614 dma_unmap_single(&port->netdev->dev, desc->data, 615 desc->buf_len, DMA_TO_DEVICE); 616 #else 617 dma_unmap_single(&port->netdev->dev, desc->data & ~3, 618 ALIGN((desc->data & 3) + desc->buf_len, 4), 619 DMA_TO_DEVICE); 620 #endif 621 } 622 623 624 static void hss_hdlc_set_carrier(void *pdev, int carrier) 625 { 626 struct net_device *netdev = pdev; 627 struct port *port = dev_to_port(netdev); 628 unsigned long flags; 629 630 spin_lock_irqsave(&npe_lock, flags); 631 port->carrier = carrier; 632 if (!port->loopback) { 633 if (carrier) 634 netif_carrier_on(netdev); 635 else 636 netif_carrier_off(netdev); 637 } 638 spin_unlock_irqrestore(&npe_lock, flags); 639 } 640 641 static void hss_hdlc_rx_irq(void *pdev) 642 { 643 struct net_device *dev = pdev; 644 struct port *port = dev_to_port(dev); 645 646 #if DEBUG_RX 647 printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name); 648 #endif 649 qmgr_disable_irq(queue_ids[port->id].rx); 650 napi_schedule(&port->napi); 651 } 652 653 static int hss_hdlc_poll(struct napi_struct *napi, int budget) 654 { 655 struct port *port = container_of(napi, struct port, napi); 656 struct net_device *dev = port->netdev; 657 unsigned int rxq = queue_ids[port->id].rx; 658 unsigned int rxfreeq = queue_ids[port->id].rxfree; 659 int received = 0; 660 661 #if DEBUG_RX 662 printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name); 663 #endif 664 665 while (received < budget) { 666 struct sk_buff *skb; 667 struct desc *desc; 668 int n; 669 #ifdef __ARMEB__ 670 struct sk_buff *temp; 671 u32 phys; 672 #endif 673 674 if ((n = queue_get_desc(rxq, port, 0)) < 0) { 675 #if DEBUG_RX 676 printk(KERN_DEBUG "%s: hss_hdlc_poll" 677 " napi_complete\n", dev->name); 678 #endif 679 napi_complete(napi); 680 qmgr_enable_irq(rxq); 681 if (!qmgr_stat_empty(rxq) && 682 napi_reschedule(napi)) { 683 #if DEBUG_RX 684 printk(KERN_DEBUG "%s: hss_hdlc_poll" 685 " napi_reschedule succeeded\n", 686 dev->name); 687 #endif 688 qmgr_disable_irq(rxq); 689 continue; 690 } 691 #if DEBUG_RX 692 printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n", 693 dev->name); 694 #endif 695 return received; /* all work done */ 696 } 697 698 desc = rx_desc_ptr(port, n); 699 #if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */ 700 if (desc->error_count) 701 printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X" 702 " errors %u\n", dev->name, desc->status, 703 desc->error_count); 704 #endif 705 skb = NULL; 706 switch (desc->status) { 707 case 0: 708 #ifdef __ARMEB__ 709 if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) { 710 phys = dma_map_single(&dev->dev, skb->data, 711 RX_SIZE, 712 DMA_FROM_DEVICE); 713 if (dma_mapping_error(&dev->dev, phys)) { 714 dev_kfree_skb(skb); 715 skb = NULL; 716 } 717 } 718 #else 719 skb = netdev_alloc_skb(dev, desc->pkt_len); 720 #endif 721 if (!skb) 722 dev->stats.rx_dropped++; 723 break; 724 case ERR_HDLC_ALIGN: 725 case ERR_HDLC_ABORT: 726 dev->stats.rx_frame_errors++; 727 dev->stats.rx_errors++; 728 break; 729 case ERR_HDLC_FCS: 730 dev->stats.rx_crc_errors++; 731 dev->stats.rx_errors++; 732 break; 733 case ERR_HDLC_TOO_LONG: 734 dev->stats.rx_length_errors++; 735 dev->stats.rx_errors++; 736 break; 737 default: /* FIXME - remove printk */ 738 netdev_err(dev, "hss_hdlc_poll: status 0x%02X errors %u\n", 739 desc->status, desc->error_count); 740 dev->stats.rx_errors++; 741 } 742 743 if (!skb) { 744 /* put the desc back on RX-ready queue */ 745 desc->buf_len = RX_SIZE; 746 desc->pkt_len = desc->status = 0; 747 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); 748 continue; 749 } 750 751 /* process received frame */ 752 #ifdef __ARMEB__ 753 temp = skb; 754 skb = port->rx_buff_tab[n]; 755 dma_unmap_single(&dev->dev, desc->data, 756 RX_SIZE, DMA_FROM_DEVICE); 757 #else 758 dma_sync_single_for_cpu(&dev->dev, desc->data, 759 RX_SIZE, DMA_FROM_DEVICE); 760 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], 761 ALIGN(desc->pkt_len, 4) / 4); 762 #endif 763 skb_put(skb, desc->pkt_len); 764 765 debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len); 766 767 skb->protocol = hdlc_type_trans(skb, dev); 768 dev->stats.rx_packets++; 769 dev->stats.rx_bytes += skb->len; 770 netif_receive_skb(skb); 771 772 /* put the new buffer on RX-free queue */ 773 #ifdef __ARMEB__ 774 port->rx_buff_tab[n] = temp; 775 desc->data = phys; 776 #endif 777 desc->buf_len = RX_SIZE; 778 desc->pkt_len = 0; 779 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); 780 received++; 781 } 782 #if DEBUG_RX 783 printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n"); 784 #endif 785 return received; /* not all work done */ 786 } 787 788 789 static void hss_hdlc_txdone_irq(void *pdev) 790 { 791 struct net_device *dev = pdev; 792 struct port *port = dev_to_port(dev); 793 int n_desc; 794 795 #if DEBUG_TX 796 printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n"); 797 #endif 798 while ((n_desc = queue_get_desc(queue_ids[port->id].txdone, 799 port, 1)) >= 0) { 800 struct desc *desc; 801 int start; 802 803 desc = tx_desc_ptr(port, n_desc); 804 805 dev->stats.tx_packets++; 806 dev->stats.tx_bytes += desc->pkt_len; 807 808 dma_unmap_tx(port, desc); 809 #if DEBUG_TX 810 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n", 811 dev->name, port->tx_buff_tab[n_desc]); 812 #endif 813 free_buffer_irq(port->tx_buff_tab[n_desc]); 814 port->tx_buff_tab[n_desc] = NULL; 815 816 start = qmgr_stat_below_low_watermark(port->plat->txreadyq); 817 queue_put_desc(port->plat->txreadyq, 818 tx_desc_phys(port, n_desc), desc); 819 if (start) { /* TX-ready queue was empty */ 820 #if DEBUG_TX 821 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit" 822 " ready\n", dev->name); 823 #endif 824 netif_wake_queue(dev); 825 } 826 } 827 } 828 829 static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev) 830 { 831 struct port *port = dev_to_port(dev); 832 unsigned int txreadyq = port->plat->txreadyq; 833 int len, offset, bytes, n; 834 void *mem; 835 u32 phys; 836 struct desc *desc; 837 838 #if DEBUG_TX 839 printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name); 840 #endif 841 842 if (unlikely(skb->len > HDLC_MAX_MRU)) { 843 dev_kfree_skb(skb); 844 dev->stats.tx_errors++; 845 return NETDEV_TX_OK; 846 } 847 848 debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len); 849 850 len = skb->len; 851 #ifdef __ARMEB__ 852 offset = 0; /* no need to keep alignment */ 853 bytes = len; 854 mem = skb->data; 855 #else 856 offset = (int)skb->data & 3; /* keep 32-bit alignment */ 857 bytes = ALIGN(offset + len, 4); 858 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) { 859 dev_kfree_skb(skb); 860 dev->stats.tx_dropped++; 861 return NETDEV_TX_OK; 862 } 863 memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4); 864 dev_kfree_skb(skb); 865 #endif 866 867 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); 868 if (dma_mapping_error(&dev->dev, phys)) { 869 #ifdef __ARMEB__ 870 dev_kfree_skb(skb); 871 #else 872 kfree(mem); 873 #endif 874 dev->stats.tx_dropped++; 875 return NETDEV_TX_OK; 876 } 877 878 n = queue_get_desc(txreadyq, port, 1); 879 BUG_ON(n < 0); 880 desc = tx_desc_ptr(port, n); 881 882 #ifdef __ARMEB__ 883 port->tx_buff_tab[n] = skb; 884 #else 885 port->tx_buff_tab[n] = mem; 886 #endif 887 desc->data = phys + offset; 888 desc->buf_len = desc->pkt_len = len; 889 890 wmb(); 891 queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc); 892 893 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */ 894 #if DEBUG_TX 895 printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name); 896 #endif 897 netif_stop_queue(dev); 898 /* we could miss TX ready interrupt */ 899 if (!qmgr_stat_below_low_watermark(txreadyq)) { 900 #if DEBUG_TX 901 printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n", 902 dev->name); 903 #endif 904 netif_wake_queue(dev); 905 } 906 } 907 908 #if DEBUG_TX 909 printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name); 910 #endif 911 return NETDEV_TX_OK; 912 } 913 914 915 static int request_hdlc_queues(struct port *port) 916 { 917 int err; 918 919 err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0, 920 "%s:RX-free", port->netdev->name); 921 if (err) 922 return err; 923 924 err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0, 925 "%s:RX", port->netdev->name); 926 if (err) 927 goto rel_rxfree; 928 929 err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0, 930 "%s:TX", port->netdev->name); 931 if (err) 932 goto rel_rx; 933 934 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0, 935 "%s:TX-ready", port->netdev->name); 936 if (err) 937 goto rel_tx; 938 939 err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0, 940 "%s:TX-done", port->netdev->name); 941 if (err) 942 goto rel_txready; 943 return 0; 944 945 rel_txready: 946 qmgr_release_queue(port->plat->txreadyq); 947 rel_tx: 948 qmgr_release_queue(queue_ids[port->id].tx); 949 rel_rx: 950 qmgr_release_queue(queue_ids[port->id].rx); 951 rel_rxfree: 952 qmgr_release_queue(queue_ids[port->id].rxfree); 953 printk(KERN_DEBUG "%s: unable to request hardware queues\n", 954 port->netdev->name); 955 return err; 956 } 957 958 static void release_hdlc_queues(struct port *port) 959 { 960 qmgr_release_queue(queue_ids[port->id].rxfree); 961 qmgr_release_queue(queue_ids[port->id].rx); 962 qmgr_release_queue(queue_ids[port->id].txdone); 963 qmgr_release_queue(queue_ids[port->id].tx); 964 qmgr_release_queue(port->plat->txreadyq); 965 } 966 967 static int init_hdlc_queues(struct port *port) 968 { 969 int i; 970 971 if (!ports_open) 972 if (!(dma_pool = dma_pool_create(DRV_NAME, NULL, 973 POOL_ALLOC_SIZE, 32, 0))) 974 return -ENOMEM; 975 976 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL, 977 &port->desc_tab_phys))) 978 return -ENOMEM; 979 memset(port->desc_tab, 0, POOL_ALLOC_SIZE); 980 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */ 981 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab)); 982 983 /* Setup RX buffers */ 984 for (i = 0; i < RX_DESCS; i++) { 985 struct desc *desc = rx_desc_ptr(port, i); 986 buffer_t *buff; 987 void *data; 988 #ifdef __ARMEB__ 989 if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE))) 990 return -ENOMEM; 991 data = buff->data; 992 #else 993 if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL))) 994 return -ENOMEM; 995 data = buff; 996 #endif 997 desc->buf_len = RX_SIZE; 998 desc->data = dma_map_single(&port->netdev->dev, data, 999 RX_SIZE, DMA_FROM_DEVICE); 1000 if (dma_mapping_error(&port->netdev->dev, desc->data)) { 1001 free_buffer(buff); 1002 return -EIO; 1003 } 1004 port->rx_buff_tab[i] = buff; 1005 } 1006 1007 return 0; 1008 } 1009 1010 static void destroy_hdlc_queues(struct port *port) 1011 { 1012 int i; 1013 1014 if (port->desc_tab) { 1015 for (i = 0; i < RX_DESCS; i++) { 1016 struct desc *desc = rx_desc_ptr(port, i); 1017 buffer_t *buff = port->rx_buff_tab[i]; 1018 if (buff) { 1019 dma_unmap_single(&port->netdev->dev, 1020 desc->data, RX_SIZE, 1021 DMA_FROM_DEVICE); 1022 free_buffer(buff); 1023 } 1024 } 1025 for (i = 0; i < TX_DESCS; i++) { 1026 struct desc *desc = tx_desc_ptr(port, i); 1027 buffer_t *buff = port->tx_buff_tab[i]; 1028 if (buff) { 1029 dma_unmap_tx(port, desc); 1030 free_buffer(buff); 1031 } 1032 } 1033 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys); 1034 port->desc_tab = NULL; 1035 } 1036 1037 if (!ports_open && dma_pool) { 1038 dma_pool_destroy(dma_pool); 1039 dma_pool = NULL; 1040 } 1041 } 1042 1043 static int hss_hdlc_open(struct net_device *dev) 1044 { 1045 struct port *port = dev_to_port(dev); 1046 unsigned long flags; 1047 int i, err = 0; 1048 1049 if ((err = hdlc_open(dev))) 1050 return err; 1051 1052 if ((err = hss_load_firmware(port))) 1053 goto err_hdlc_close; 1054 1055 if ((err = request_hdlc_queues(port))) 1056 goto err_hdlc_close; 1057 1058 if ((err = init_hdlc_queues(port))) 1059 goto err_destroy_queues; 1060 1061 spin_lock_irqsave(&npe_lock, flags); 1062 if (port->plat->open) 1063 if ((err = port->plat->open(port->id, dev, 1064 hss_hdlc_set_carrier))) 1065 goto err_unlock; 1066 spin_unlock_irqrestore(&npe_lock, flags); 1067 1068 /* Populate queues with buffers, no failure after this point */ 1069 for (i = 0; i < TX_DESCS; i++) 1070 queue_put_desc(port->plat->txreadyq, 1071 tx_desc_phys(port, i), tx_desc_ptr(port, i)); 1072 1073 for (i = 0; i < RX_DESCS; i++) 1074 queue_put_desc(queue_ids[port->id].rxfree, 1075 rx_desc_phys(port, i), rx_desc_ptr(port, i)); 1076 1077 napi_enable(&port->napi); 1078 netif_start_queue(dev); 1079 1080 qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY, 1081 hss_hdlc_rx_irq, dev); 1082 1083 qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY, 1084 hss_hdlc_txdone_irq, dev); 1085 qmgr_enable_irq(queue_ids[port->id].txdone); 1086 1087 ports_open++; 1088 1089 hss_set_hdlc_cfg(port); 1090 hss_config(port); 1091 1092 hss_start_hdlc(port); 1093 1094 /* we may already have RX data, enables IRQ */ 1095 napi_schedule(&port->napi); 1096 return 0; 1097 1098 err_unlock: 1099 spin_unlock_irqrestore(&npe_lock, flags); 1100 err_destroy_queues: 1101 destroy_hdlc_queues(port); 1102 release_hdlc_queues(port); 1103 err_hdlc_close: 1104 hdlc_close(dev); 1105 return err; 1106 } 1107 1108 static int hss_hdlc_close(struct net_device *dev) 1109 { 1110 struct port *port = dev_to_port(dev); 1111 unsigned long flags; 1112 int i, buffs = RX_DESCS; /* allocated RX buffers */ 1113 1114 spin_lock_irqsave(&npe_lock, flags); 1115 ports_open--; 1116 qmgr_disable_irq(queue_ids[port->id].rx); 1117 netif_stop_queue(dev); 1118 napi_disable(&port->napi); 1119 1120 hss_stop_hdlc(port); 1121 1122 while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0) 1123 buffs--; 1124 while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0) 1125 buffs--; 1126 1127 if (buffs) 1128 netdev_crit(dev, "unable to drain RX queue, %i buffer(s) left in NPE\n", 1129 buffs); 1130 1131 buffs = TX_DESCS; 1132 while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0) 1133 buffs--; /* cancel TX */ 1134 1135 i = 0; 1136 do { 1137 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0) 1138 buffs--; 1139 if (!buffs) 1140 break; 1141 } while (++i < MAX_CLOSE_WAIT); 1142 1143 if (buffs) 1144 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) left in NPE\n", 1145 buffs); 1146 #if DEBUG_CLOSE 1147 if (!buffs) 1148 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i); 1149 #endif 1150 qmgr_disable_irq(queue_ids[port->id].txdone); 1151 1152 if (port->plat->close) 1153 port->plat->close(port->id, dev); 1154 spin_unlock_irqrestore(&npe_lock, flags); 1155 1156 destroy_hdlc_queues(port); 1157 release_hdlc_queues(port); 1158 hdlc_close(dev); 1159 return 0; 1160 } 1161 1162 1163 static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding, 1164 unsigned short parity) 1165 { 1166 struct port *port = dev_to_port(dev); 1167 1168 if (encoding != ENCODING_NRZ) 1169 return -EINVAL; 1170 1171 switch(parity) { 1172 case PARITY_CRC16_PR1_CCITT: 1173 port->hdlc_cfg = 0; 1174 return 0; 1175 1176 case PARITY_CRC32_PR1_CCITT: 1177 port->hdlc_cfg = PKT_HDLC_CRC_32; 1178 return 0; 1179 1180 default: 1181 return -EINVAL; 1182 } 1183 } 1184 1185 static u32 check_clock(u32 rate, u32 a, u32 b, u32 c, 1186 u32 *best, u32 *best_diff, u32 *reg) 1187 { 1188 /* a is 10-bit, b is 10-bit, c is 12-bit */ 1189 u64 new_rate; 1190 u32 new_diff; 1191 1192 new_rate = ixp4xx_timer_freq * (u64)(c + 1); 1193 do_div(new_rate, a * (c + 1) + b + 1); 1194 new_diff = abs((u32)new_rate - rate); 1195 1196 if (new_diff < *best_diff) { 1197 *best = new_rate; 1198 *best_diff = new_diff; 1199 *reg = (a << 22) | (b << 12) | c; 1200 } 1201 return new_diff; 1202 } 1203 1204 static void find_best_clock(u32 rate, u32 *best, u32 *reg) 1205 { 1206 u32 a, b, diff = 0xFFFFFFFF; 1207 1208 a = ixp4xx_timer_freq / rate; 1209 1210 if (a > 0x3FF) { /* 10-bit value - we can go as slow as ca. 65 kb/s */ 1211 check_clock(rate, 0x3FF, 1, 1, best, &diff, reg); 1212 return; 1213 } 1214 if (a == 0) { /* > 66.666 MHz */ 1215 a = 1; /* minimum divider is 1 (a = 0, b = 1, c = 1) */ 1216 rate = ixp4xx_timer_freq; 1217 } 1218 1219 if (rate * a == ixp4xx_timer_freq) { /* don't divide by 0 later */ 1220 check_clock(rate, a - 1, 1, 1, best, &diff, reg); 1221 return; 1222 } 1223 1224 for (b = 0; b < 0x400; b++) { 1225 u64 c = (b + 1) * (u64)rate; 1226 do_div(c, ixp4xx_timer_freq - rate * a); 1227 c--; 1228 if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */ 1229 if (b == 0 && /* also try a bit higher rate */ 1230 !check_clock(rate, a - 1, 1, 1, best, &diff, reg)) 1231 return; 1232 check_clock(rate, a, b, 0xFFF, best, &diff, reg); 1233 return; 1234 } 1235 if (!check_clock(rate, a, b, c, best, &diff, reg)) 1236 return; 1237 if (!check_clock(rate, a, b, c + 1, best, &diff, reg)) 1238 return; 1239 } 1240 } 1241 1242 static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1243 { 1244 const size_t size = sizeof(sync_serial_settings); 1245 sync_serial_settings new_line; 1246 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; 1247 struct port *port = dev_to_port(dev); 1248 unsigned long flags; 1249 int clk; 1250 1251 if (cmd != SIOCWANDEV) 1252 return hdlc_ioctl(dev, ifr, cmd); 1253 1254 switch(ifr->ifr_settings.type) { 1255 case IF_GET_IFACE: 1256 ifr->ifr_settings.type = IF_IFACE_V35; 1257 if (ifr->ifr_settings.size < size) { 1258 ifr->ifr_settings.size = size; /* data size wanted */ 1259 return -ENOBUFS; 1260 } 1261 memset(&new_line, 0, sizeof(new_line)); 1262 new_line.clock_type = port->clock_type; 1263 new_line.clock_rate = port->clock_rate; 1264 new_line.loopback = port->loopback; 1265 if (copy_to_user(line, &new_line, size)) 1266 return -EFAULT; 1267 return 0; 1268 1269 case IF_IFACE_SYNC_SERIAL: 1270 case IF_IFACE_V35: 1271 if(!capable(CAP_NET_ADMIN)) 1272 return -EPERM; 1273 if (copy_from_user(&new_line, line, size)) 1274 return -EFAULT; 1275 1276 clk = new_line.clock_type; 1277 if (port->plat->set_clock) 1278 clk = port->plat->set_clock(port->id, clk); 1279 1280 if (clk != CLOCK_EXT && clk != CLOCK_INT) 1281 return -EINVAL; /* No such clock setting */ 1282 1283 if (new_line.loopback != 0 && new_line.loopback != 1) 1284 return -EINVAL; 1285 1286 port->clock_type = clk; /* Update settings */ 1287 if (clk == CLOCK_INT) 1288 find_best_clock(new_line.clock_rate, &port->clock_rate, 1289 &port->clock_reg); 1290 else { 1291 port->clock_rate = 0; 1292 port->clock_reg = CLK42X_SPEED_2048KHZ; 1293 } 1294 port->loopback = new_line.loopback; 1295 1296 spin_lock_irqsave(&npe_lock, flags); 1297 1298 if (dev->flags & IFF_UP) 1299 hss_config(port); 1300 1301 if (port->loopback || port->carrier) 1302 netif_carrier_on(port->netdev); 1303 else 1304 netif_carrier_off(port->netdev); 1305 spin_unlock_irqrestore(&npe_lock, flags); 1306 1307 return 0; 1308 1309 default: 1310 return hdlc_ioctl(dev, ifr, cmd); 1311 } 1312 } 1313 1314 /***************************************************************************** 1315 * initialization 1316 ****************************************************************************/ 1317 1318 static const struct net_device_ops hss_hdlc_ops = { 1319 .ndo_open = hss_hdlc_open, 1320 .ndo_stop = hss_hdlc_close, 1321 .ndo_change_mtu = hdlc_change_mtu, 1322 .ndo_start_xmit = hdlc_start_xmit, 1323 .ndo_do_ioctl = hss_hdlc_ioctl, 1324 }; 1325 1326 static int __devinit hss_init_one(struct platform_device *pdev) 1327 { 1328 struct port *port; 1329 struct net_device *dev; 1330 hdlc_device *hdlc; 1331 int err; 1332 1333 if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL) 1334 return -ENOMEM; 1335 1336 if ((port->npe = npe_request(0)) == NULL) { 1337 err = -ENODEV; 1338 goto err_free; 1339 } 1340 1341 if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) { 1342 err = -ENOMEM; 1343 goto err_plat; 1344 } 1345 1346 SET_NETDEV_DEV(dev, &pdev->dev); 1347 hdlc = dev_to_hdlc(dev); 1348 hdlc->attach = hss_hdlc_attach; 1349 hdlc->xmit = hss_hdlc_xmit; 1350 dev->netdev_ops = &hss_hdlc_ops; 1351 dev->tx_queue_len = 100; 1352 port->clock_type = CLOCK_EXT; 1353 port->clock_rate = 0; 1354 port->clock_reg = CLK42X_SPEED_2048KHZ; 1355 port->id = pdev->id; 1356 port->dev = &pdev->dev; 1357 port->plat = pdev->dev.platform_data; 1358 netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT); 1359 1360 if ((err = register_hdlc_device(dev))) 1361 goto err_free_netdev; 1362 1363 platform_set_drvdata(pdev, port); 1364 1365 netdev_info(dev, "HSS-%i\n", port->id); 1366 return 0; 1367 1368 err_free_netdev: 1369 free_netdev(dev); 1370 err_plat: 1371 npe_release(port->npe); 1372 err_free: 1373 kfree(port); 1374 return err; 1375 } 1376 1377 static int __devexit hss_remove_one(struct platform_device *pdev) 1378 { 1379 struct port *port = platform_get_drvdata(pdev); 1380 1381 unregister_hdlc_device(port->netdev); 1382 free_netdev(port->netdev); 1383 npe_release(port->npe); 1384 platform_set_drvdata(pdev, NULL); 1385 kfree(port); 1386 return 0; 1387 } 1388 1389 static struct platform_driver ixp4xx_hss_driver = { 1390 .driver.name = DRV_NAME, 1391 .probe = hss_init_one, 1392 .remove = hss_remove_one, 1393 }; 1394 1395 static int __init hss_init_module(void) 1396 { 1397 if ((ixp4xx_read_feature_bits() & 1398 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) != 1399 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) 1400 return -ENODEV; 1401 1402 spin_lock_init(&npe_lock); 1403 1404 return platform_driver_register(&ixp4xx_hss_driver); 1405 } 1406 1407 static void __exit hss_cleanup_module(void) 1408 { 1409 platform_driver_unregister(&ixp4xx_hss_driver); 1410 } 1411 1412 MODULE_AUTHOR("Krzysztof Halasa"); 1413 MODULE_DESCRIPTION("Intel IXP4xx HSS driver"); 1414 MODULE_LICENSE("GPL v2"); 1415 MODULE_ALIAS("platform:ixp4xx_hss"); 1416 module_init(hss_init_module); 1417 module_exit(hss_cleanup_module); 1418