1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Hitachi (now Renesas) SCA-II HD64572 driver for Linux 4 * 5 * Copyright (C) 1998-2008 Krzysztof Halasa <khc@pm.waw.pl> 6 * 7 * Source of information: HD64572 SCA-II User's Manual 8 * 9 * We use the following SCA memory map: 10 * 11 * Packet buffer descriptor rings - starting from card->rambase: 12 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring 13 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring 14 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used) 15 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used) 16 * 17 * Packet data buffers - starting from card->rambase + buff_offset: 18 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers 19 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers 20 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers (if used) 21 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers (if used) 22 */ 23 24 #include <linux/bitops.h> 25 #include <linux/errno.h> 26 #include <linux/fcntl.h> 27 #include <linux/hdlc.h> 28 #include <linux/in.h> 29 #include <linux/interrupt.h> 30 #include <linux/ioport.h> 31 #include <linux/jiffies.h> 32 #include <linux/kernel.h> 33 #include <linux/module.h> 34 #include <linux/netdevice.h> 35 #include <linux/skbuff.h> 36 #include <linux/string.h> 37 #include <linux/types.h> 38 #include <asm/io.h> 39 #include <linux/uaccess.h> 40 #include "hd64572.h" 41 42 #define NAPI_WEIGHT 16 43 44 #define get_msci(port) ((port)->chan ? MSCI1_OFFSET : MSCI0_OFFSET) 45 #define get_dmac_rx(port) ((port)->chan ? DMAC1RX_OFFSET : DMAC0RX_OFFSET) 46 #define get_dmac_tx(port) ((port)->chan ? DMAC1TX_OFFSET : DMAC0TX_OFFSET) 47 48 #define sca_in(reg, card) readb((card)->scabase + (reg)) 49 #define sca_out(value, reg, card) writeb(value, (card)->scabase + (reg)) 50 #define sca_inw(reg, card) readw((card)->scabase + (reg)) 51 #define sca_outw(value, reg, card) writew(value, (card)->scabase + (reg)) 52 #define sca_inl(reg, card) readl((card)->scabase + (reg)) 53 #define sca_outl(value, reg, card) writel(value, (card)->scabase + (reg)) 54 55 static int sca_poll(struct napi_struct *napi, int budget); 56 57 static inline port_t *dev_to_port(struct net_device *dev) 58 { 59 return dev_to_hdlc(dev)->priv; 60 } 61 62 static inline void enable_intr(port_t *port) 63 { 64 /* enable DMIB and MSCI RXINTA interrupts */ 65 sca_outl(sca_inl(IER0, port->card) | 66 (port->chan ? 0x08002200 : 0x00080022), IER0, port->card); 67 } 68 69 static inline void disable_intr(port_t *port) 70 { 71 sca_outl(sca_inl(IER0, port->card) & 72 (port->chan ? 0x00FF00FF : 0xFF00FF00), IER0, port->card); 73 } 74 75 static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit) 76 { 77 u16 rx_buffs = port->card->rx_ring_buffers; 78 u16 tx_buffs = port->card->tx_ring_buffers; 79 80 desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc. 81 return port->chan * (rx_buffs + tx_buffs) + transmit * rx_buffs + desc; 82 } 83 84 static inline u16 desc_offset(port_t *port, u16 desc, int transmit) 85 { 86 /* Descriptor offset always fits in 16 bits */ 87 return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc); 88 } 89 90 static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc, 91 int transmit) 92 { 93 return (pkt_desc __iomem *)(port->card->rambase + 94 desc_offset(port, desc, transmit)); 95 } 96 97 static inline u32 buffer_offset(port_t *port, u16 desc, int transmit) 98 { 99 return port->card->buff_offset + 100 desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU; 101 } 102 103 static inline void sca_set_carrier(port_t *port) 104 { 105 if (!(sca_in(get_msci(port) + ST3, port->card) & ST3_DCD)) { 106 #ifdef DEBUG_LINK 107 printk(KERN_DEBUG "%s: sca_set_carrier on\n", 108 port->netdev.name); 109 #endif 110 netif_carrier_on(port->netdev); 111 } else { 112 #ifdef DEBUG_LINK 113 printk(KERN_DEBUG "%s: sca_set_carrier off\n", 114 port->netdev.name); 115 #endif 116 netif_carrier_off(port->netdev); 117 } 118 } 119 120 static void sca_init_port(port_t *port) 121 { 122 card_t *card = port->card; 123 u16 dmac_rx = get_dmac_rx(port), dmac_tx = get_dmac_tx(port); 124 int transmit, i; 125 126 port->rxin = 0; 127 port->txin = 0; 128 port->txlast = 0; 129 130 for (transmit = 0; transmit < 2; transmit++) { 131 u16 buffs = transmit ? card->tx_ring_buffers 132 : card->rx_ring_buffers; 133 134 for (i = 0; i < buffs; i++) { 135 pkt_desc __iomem *desc = desc_address(port, i, transmit); 136 u16 chain_off = desc_offset(port, i + 1, transmit); 137 u32 buff_off = buffer_offset(port, i, transmit); 138 139 writel(chain_off, &desc->cp); 140 writel(buff_off, &desc->bp); 141 writew(0, &desc->len); 142 writeb(0, &desc->stat); 143 } 144 } 145 146 /* DMA disable - to halt state */ 147 sca_out(0, DSR_RX(port->chan), card); 148 sca_out(0, DSR_TX(port->chan), card); 149 150 /* software ABORT - to initial state */ 151 sca_out(DCR_ABORT, DCR_RX(port->chan), card); 152 sca_out(DCR_ABORT, DCR_TX(port->chan), card); 153 154 /* current desc addr */ 155 sca_outl(desc_offset(port, 0, 0), dmac_rx + CDAL, card); 156 sca_outl(desc_offset(port, card->tx_ring_buffers - 1, 0), 157 dmac_rx + EDAL, card); 158 sca_outl(desc_offset(port, 0, 1), dmac_tx + CDAL, card); 159 sca_outl(desc_offset(port, 0, 1), dmac_tx + EDAL, card); 160 161 /* clear frame end interrupt counter */ 162 sca_out(DCR_CLEAR_EOF, DCR_RX(port->chan), card); 163 sca_out(DCR_CLEAR_EOF, DCR_TX(port->chan), card); 164 165 /* Receive */ 166 sca_outw(HDLC_MAX_MRU, dmac_rx + BFLL, card); /* set buffer length */ 167 sca_out(0x14, DMR_RX(port->chan), card); /* Chain mode, Multi-frame */ 168 sca_out(DIR_EOME, DIR_RX(port->chan), card); /* enable interrupts */ 169 sca_out(DSR_DE, DSR_RX(port->chan), card); /* DMA enable */ 170 171 /* Transmit */ 172 sca_out(0x14, DMR_TX(port->chan), card); /* Chain mode, Multi-frame */ 173 sca_out(DIR_EOME, DIR_TX(port->chan), card); /* enable interrupts */ 174 175 sca_set_carrier(port); 176 netif_napi_add_weight(port->netdev, &port->napi, sca_poll, 177 NAPI_WEIGHT); 178 } 179 180 /* MSCI interrupt service */ 181 static inline void sca_msci_intr(port_t *port) 182 { 183 u16 msci = get_msci(port); 184 card_t *card = port->card; 185 186 if (sca_in(msci + ST1, card) & ST1_CDCD) { 187 /* Reset MSCI CDCD status bit */ 188 sca_out(ST1_CDCD, msci + ST1, card); 189 sca_set_carrier(port); 190 } 191 } 192 193 static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc, 194 u16 rxin) 195 { 196 struct net_device *dev = port->netdev; 197 struct sk_buff *skb; 198 u16 len; 199 u32 buff; 200 201 len = readw(&desc->len); 202 skb = dev_alloc_skb(len); 203 if (!skb) { 204 dev->stats.rx_dropped++; 205 return; 206 } 207 208 buff = buffer_offset(port, rxin, 0); 209 memcpy_fromio(skb->data, card->rambase + buff, len); 210 211 skb_put(skb, len); 212 #ifdef DEBUG_PKT 213 printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len); 214 debug_frame(skb); 215 #endif 216 dev->stats.rx_packets++; 217 dev->stats.rx_bytes += skb->len; 218 skb->protocol = hdlc_type_trans(skb, dev); 219 netif_receive_skb(skb); 220 } 221 222 /* Receive DMA service */ 223 static inline int sca_rx_done(port_t *port, int budget) 224 { 225 struct net_device *dev = port->netdev; 226 u16 dmac = get_dmac_rx(port); 227 card_t *card = port->card; 228 u8 stat = sca_in(DSR_RX(port->chan), card); /* read DMA Status */ 229 int received = 0; 230 231 /* Reset DSR status bits */ 232 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, 233 DSR_RX(port->chan), card); 234 235 if (stat & DSR_BOF) 236 /* Dropped one or more frames */ 237 dev->stats.rx_over_errors++; 238 239 while (received < budget) { 240 u32 desc_off = desc_offset(port, port->rxin, 0); 241 pkt_desc __iomem *desc; 242 u32 cda = sca_inl(dmac + CDAL, card); 243 244 if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc))) 245 break; /* No frame received */ 246 247 desc = desc_address(port, port->rxin, 0); 248 stat = readb(&desc->stat); 249 if (!(stat & ST_RX_EOM)) 250 port->rxpart = 1; /* partial frame received */ 251 else if ((stat & ST_ERROR_MASK) || port->rxpart) { 252 dev->stats.rx_errors++; 253 if (stat & ST_RX_OVERRUN) 254 dev->stats.rx_fifo_errors++; 255 else if ((stat & (ST_RX_SHORT | ST_RX_ABORT | 256 ST_RX_RESBIT)) || port->rxpart) 257 dev->stats.rx_frame_errors++; 258 else if (stat & ST_RX_CRC) 259 dev->stats.rx_crc_errors++; 260 if (stat & ST_RX_EOM) 261 port->rxpart = 0; /* received last fragment */ 262 } else { 263 sca_rx(card, port, desc, port->rxin); 264 received++; 265 } 266 267 /* Set new error descriptor address */ 268 sca_outl(desc_off, dmac + EDAL, card); 269 port->rxin = (port->rxin + 1) % card->rx_ring_buffers; 270 } 271 272 /* make sure RX DMA is enabled */ 273 sca_out(DSR_DE, DSR_RX(port->chan), card); 274 return received; 275 } 276 277 /* Transmit DMA service */ 278 static inline void sca_tx_done(port_t *port) 279 { 280 struct net_device *dev = port->netdev; 281 card_t *card = port->card; 282 u8 stat; 283 unsigned count = 0; 284 285 spin_lock(&port->lock); 286 287 stat = sca_in(DSR_TX(port->chan), card); /* read DMA Status */ 288 289 /* Reset DSR status bits */ 290 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, 291 DSR_TX(port->chan), card); 292 293 while (1) { 294 pkt_desc __iomem *desc = desc_address(port, port->txlast, 1); 295 u8 stat = readb(&desc->stat); 296 297 if (!(stat & ST_TX_OWNRSHP)) 298 break; /* not yet transmitted */ 299 if (stat & ST_TX_UNDRRUN) { 300 dev->stats.tx_errors++; 301 dev->stats.tx_fifo_errors++; 302 } else { 303 dev->stats.tx_packets++; 304 dev->stats.tx_bytes += readw(&desc->len); 305 } 306 writeb(0, &desc->stat); /* Free descriptor */ 307 count++; 308 port->txlast = (port->txlast + 1) % card->tx_ring_buffers; 309 } 310 311 if (count) 312 netif_wake_queue(dev); 313 spin_unlock(&port->lock); 314 } 315 316 static int sca_poll(struct napi_struct *napi, int budget) 317 { 318 port_t *port = container_of(napi, port_t, napi); 319 u32 isr0 = sca_inl(ISR0, port->card); 320 int received = 0; 321 322 if (isr0 & (port->chan ? 0x08000000 : 0x00080000)) 323 sca_msci_intr(port); 324 325 if (isr0 & (port->chan ? 0x00002000 : 0x00000020)) 326 sca_tx_done(port); 327 328 if (isr0 & (port->chan ? 0x00000200 : 0x00000002)) 329 received = sca_rx_done(port, budget); 330 331 if (received < budget) { 332 napi_complete_done(napi, received); 333 enable_intr(port); 334 } 335 336 return received; 337 } 338 339 static irqreturn_t sca_intr(int irq, void *dev_id) 340 { 341 card_t *card = dev_id; 342 u32 isr0 = sca_inl(ISR0, card); 343 int i, handled = 0; 344 345 for (i = 0; i < 2; i++) { 346 port_t *port = get_port(card, i); 347 if (port && (isr0 & (i ? 0x08002200 : 0x00080022))) { 348 handled = 1; 349 disable_intr(port); 350 napi_schedule(&port->napi); 351 } 352 } 353 354 return IRQ_RETVAL(handled); 355 } 356 357 static void sca_set_port(port_t *port) 358 { 359 card_t *card = port->card; 360 u16 msci = get_msci(port); 361 u8 md2 = sca_in(msci + MD2, card); 362 unsigned int tmc, br = 10, brv = 1024; 363 364 if (port->settings.clock_rate > 0) { 365 /* Try lower br for better accuracy*/ 366 do { 367 br--; 368 brv >>= 1; /* brv = 2^9 = 512 max in specs */ 369 370 /* Baud Rate = CLOCK_BASE / TMC / 2^BR */ 371 tmc = CLOCK_BASE / brv / port->settings.clock_rate; 372 } while (br > 1 && tmc <= 128); 373 374 if (tmc < 1) { 375 tmc = 1; 376 br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */ 377 brv = 1; 378 } else if (tmc > 255) { 379 tmc = 256; /* tmc=0 means 256 - low baud rates */ 380 } 381 382 port->settings.clock_rate = CLOCK_BASE / brv / tmc; 383 } else { 384 br = 9; /* Minimum clock rate */ 385 tmc = 256; /* 8bit = 0 */ 386 port->settings.clock_rate = CLOCK_BASE / (256 * 512); 387 } 388 389 port->rxs = (port->rxs & ~CLK_BRG_MASK) | br; 390 port->txs = (port->txs & ~CLK_BRG_MASK) | br; 391 port->tmc = tmc; 392 393 /* baud divisor - time constant*/ 394 sca_out(port->tmc, msci + TMCR, card); 395 sca_out(port->tmc, msci + TMCT, card); 396 397 /* Set BRG bits */ 398 sca_out(port->rxs, msci + RXS, card); 399 sca_out(port->txs, msci + TXS, card); 400 401 if (port->settings.loopback) 402 md2 |= MD2_LOOPBACK; 403 else 404 md2 &= ~MD2_LOOPBACK; 405 406 sca_out(md2, msci + MD2, card); 407 } 408 409 static void sca_open(struct net_device *dev) 410 { 411 port_t *port = dev_to_port(dev); 412 card_t *card = port->card; 413 u16 msci = get_msci(port); 414 u8 md0, md2; 415 416 switch (port->encoding) { 417 case ENCODING_NRZ: 418 md2 = MD2_NRZ; 419 break; 420 case ENCODING_NRZI: 421 md2 = MD2_NRZI; 422 break; 423 case ENCODING_FM_MARK: 424 md2 = MD2_FM_MARK; 425 break; 426 case ENCODING_FM_SPACE: 427 md2 = MD2_FM_SPACE; 428 break; 429 default: 430 md2 = MD2_MANCHESTER; 431 } 432 433 if (port->settings.loopback) 434 md2 |= MD2_LOOPBACK; 435 436 switch (port->parity) { 437 case PARITY_CRC16_PR0: 438 md0 = MD0_HDLC | MD0_CRC_16_0; 439 break; 440 case PARITY_CRC16_PR1: 441 md0 = MD0_HDLC | MD0_CRC_16; 442 break; 443 case PARITY_CRC32_PR1_CCITT: 444 md0 = MD0_HDLC | MD0_CRC_ITU32; 445 break; 446 case PARITY_CRC16_PR1_CCITT: 447 md0 = MD0_HDLC | MD0_CRC_ITU; 448 break; 449 default: 450 md0 = MD0_HDLC | MD0_CRC_NONE; 451 } 452 453 sca_out(CMD_RESET, msci + CMD, card); 454 sca_out(md0, msci + MD0, card); 455 sca_out(0x00, msci + MD1, card); /* no address field check */ 456 sca_out(md2, msci + MD2, card); 457 sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */ 458 /* Skip the rest of underrun frame */ 459 sca_out(CTL_IDLE | CTL_URCT | CTL_URSKP, msci + CTL, card); 460 sca_out(0x0F, msci + RNR, card); /* +1=RX DMA activation condition */ 461 sca_out(0x3C, msci + TFS, card); /* +1 = TX start */ 462 sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */ 463 sca_out(0x38, msci + TNR0, card); /* =TX DMA activation condition */ 464 sca_out(0x3F, msci + TNR1, card); /* +1=TX DMA deactivation condition*/ 465 466 /* We're using the following interrupts: 467 - RXINTA (DCD changes only) 468 - DMIB (EOM - single frame transfer complete) 469 */ 470 sca_outl(IE0_RXINTA | IE0_CDCD, msci + IE0, card); 471 472 sca_out(port->tmc, msci + TMCR, card); 473 sca_out(port->tmc, msci + TMCT, card); 474 sca_out(port->rxs, msci + RXS, card); 475 sca_out(port->txs, msci + TXS, card); 476 sca_out(CMD_TX_ENABLE, msci + CMD, card); 477 sca_out(CMD_RX_ENABLE, msci + CMD, card); 478 479 sca_set_carrier(port); 480 enable_intr(port); 481 napi_enable(&port->napi); 482 netif_start_queue(dev); 483 } 484 485 static void sca_close(struct net_device *dev) 486 { 487 port_t *port = dev_to_port(dev); 488 489 /* reset channel */ 490 sca_out(CMD_RESET, get_msci(port) + CMD, port->card); 491 disable_intr(port); 492 napi_disable(&port->napi); 493 netif_stop_queue(dev); 494 } 495 496 static int sca_attach(struct net_device *dev, unsigned short encoding, 497 unsigned short parity) 498 { 499 if (encoding != ENCODING_NRZ && 500 encoding != ENCODING_NRZI && 501 encoding != ENCODING_FM_MARK && 502 encoding != ENCODING_FM_SPACE && 503 encoding != ENCODING_MANCHESTER) 504 return -EINVAL; 505 506 if (parity != PARITY_NONE && 507 parity != PARITY_CRC16_PR0 && 508 parity != PARITY_CRC16_PR1 && 509 parity != PARITY_CRC32_PR1_CCITT && 510 parity != PARITY_CRC16_PR1_CCITT) 511 return -EINVAL; 512 513 dev_to_port(dev)->encoding = encoding; 514 dev_to_port(dev)->parity = parity; 515 return 0; 516 } 517 518 #ifdef DEBUG_RINGS 519 static void sca_dump_rings(struct net_device *dev) 520 { 521 port_t *port = dev_to_port(dev); 522 card_t *card = port->card; 523 u16 cnt; 524 525 printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive", 526 sca_inl(get_dmac_rx(port) + CDAL, card), 527 sca_inl(get_dmac_rx(port) + EDAL, card), 528 sca_in(DSR_RX(port->chan), card), port->rxin, 529 sca_in(DSR_RX(port->chan), card) & DSR_DE ? "" : "in"); 530 for (cnt = 0; cnt < port->card->rx_ring_buffers; cnt++) 531 pr_cont(" %02X", readb(&(desc_address(port, cnt, 0)->stat))); 532 pr_cont("\n"); 533 534 printk(KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u " 535 "last=%u %sactive", 536 sca_inl(get_dmac_tx(port) + CDAL, card), 537 sca_inl(get_dmac_tx(port) + EDAL, card), 538 sca_in(DSR_TX(port->chan), card), port->txin, port->txlast, 539 sca_in(DSR_TX(port->chan), card) & DSR_DE ? "" : "in"); 540 541 for (cnt = 0; cnt < port->card->tx_ring_buffers; cnt++) 542 pr_cont(" %02X", readb(&(desc_address(port, cnt, 1)->stat))); 543 pr_cont("\n"); 544 545 printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x," 546 " ST: %02x %02x %02x %02x %02x, FST: %02x CST: %02x %02x\n", 547 sca_in(get_msci(port) + MD0, card), 548 sca_in(get_msci(port) + MD1, card), 549 sca_in(get_msci(port) + MD2, card), 550 sca_in(get_msci(port) + ST0, card), 551 sca_in(get_msci(port) + ST1, card), 552 sca_in(get_msci(port) + ST2, card), 553 sca_in(get_msci(port) + ST3, card), 554 sca_in(get_msci(port) + ST4, card), 555 sca_in(get_msci(port) + FST, card), 556 sca_in(get_msci(port) + CST0, card), 557 sca_in(get_msci(port) + CST1, card)); 558 559 printk(KERN_DEBUG "ILAR: %02x ISR: %08x %08x\n", sca_in(ILAR, card), 560 sca_inl(ISR0, card), sca_inl(ISR1, card)); 561 } 562 #endif /* DEBUG_RINGS */ 563 564 static netdev_tx_t sca_xmit(struct sk_buff *skb, struct net_device *dev) 565 { 566 port_t *port = dev_to_port(dev); 567 card_t *card = port->card; 568 pkt_desc __iomem *desc; 569 u32 buff, len; 570 571 spin_lock_irq(&port->lock); 572 573 desc = desc_address(port, port->txin + 1, 1); 574 BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */ 575 576 #ifdef DEBUG_PKT 577 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len); 578 debug_frame(skb); 579 #endif 580 581 desc = desc_address(port, port->txin, 1); 582 buff = buffer_offset(port, port->txin, 1); 583 len = skb->len; 584 memcpy_toio(card->rambase + buff, skb->data, len); 585 586 writew(len, &desc->len); 587 writeb(ST_TX_EOM, &desc->stat); 588 589 port->txin = (port->txin + 1) % card->tx_ring_buffers; 590 sca_outl(desc_offset(port, port->txin, 1), 591 get_dmac_tx(port) + EDAL, card); 592 593 sca_out(DSR_DE, DSR_TX(port->chan), card); /* Enable TX DMA */ 594 595 desc = desc_address(port, port->txin + 1, 1); 596 if (readb(&desc->stat)) /* allow 1 packet gap */ 597 netif_stop_queue(dev); 598 599 spin_unlock_irq(&port->lock); 600 601 dev_kfree_skb(skb); 602 return NETDEV_TX_OK; 603 } 604 605 static u32 sca_detect_ram(card_t *card, u8 __iomem *rambase, u32 ramsize) 606 { 607 /* Round RAM size to 32 bits, fill from end to start */ 608 u32 i = ramsize &= ~3; 609 610 do { 611 i -= 4; 612 writel(i ^ 0x12345678, rambase + i); 613 } while (i > 0); 614 615 for (i = 0; i < ramsize ; i += 4) { 616 if (readl(rambase + i) != (i ^ 0x12345678)) 617 break; 618 } 619 620 return i; 621 } 622 623 static void sca_init(card_t *card, int wait_states) 624 { 625 sca_out(wait_states, WCRL, card); /* Wait Control */ 626 sca_out(wait_states, WCRM, card); 627 sca_out(wait_states, WCRH, card); 628 629 sca_out(0, DMER, card); /* DMA Master disable */ 630 sca_out(0x03, PCR, card); /* DMA priority */ 631 sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */ 632 sca_out(0, DSR_TX(0), card); 633 sca_out(0, DSR_RX(1), card); 634 sca_out(0, DSR_TX(1), card); 635 sca_out(DMER_DME, DMER, card); /* DMA Master enable */ 636 } 637