1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Hitachi SCA HD64570 driver for Linux 4 * 5 * Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl> 6 * 7 * Source of information: Hitachi HD64570 SCA User's Manual 8 * 9 * We use the following SCA memory map: 10 * 11 * Packet buffer descriptor rings - starting from winbase or win0base: 12 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring 13 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring 14 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used) 15 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used) 16 * 17 * Packet data buffers - starting from winbase + buff_offset: 18 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers 19 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers 20 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers (if used) 21 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers (if used) 22 */ 23 24 #include <linux/bitops.h> 25 #include <linux/errno.h> 26 #include <linux/fcntl.h> 27 #include <linux/hdlc.h> 28 #include <linux/in.h> 29 #include <linux/interrupt.h> 30 #include <linux/ioport.h> 31 #include <linux/jiffies.h> 32 #include <linux/kernel.h> 33 #include <linux/module.h> 34 #include <linux/netdevice.h> 35 #include <linux/skbuff.h> 36 #include <linux/string.h> 37 #include <linux/types.h> 38 #include <asm/io.h> 39 #include <linux/uaccess.h> 40 #include "hd64570.h" 41 42 #define get_msci(port) (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET) 43 #define get_dmac_rx(port) (phy_node(port) ? DMAC1RX_OFFSET : DMAC0RX_OFFSET) 44 #define get_dmac_tx(port) (phy_node(port) ? DMAC1TX_OFFSET : DMAC0TX_OFFSET) 45 46 #define SCA_INTR_MSCI(node) (node ? 0x10 : 0x01) 47 #define SCA_INTR_DMAC_RX(node) (node ? 0x20 : 0x02) 48 #define SCA_INTR_DMAC_TX(node) (node ? 0x40 : 0x04) 49 50 51 static inline struct net_device *port_to_dev(port_t *port) 52 { 53 return port->dev; 54 } 55 56 static inline int sca_intr_status(card_t *card) 57 { 58 u8 result = 0; 59 u8 isr0 = sca_in(ISR0, card); 60 u8 isr1 = sca_in(ISR1, card); 61 62 if (isr1 & 0x03) result |= SCA_INTR_DMAC_RX(0); 63 if (isr1 & 0x0C) result |= SCA_INTR_DMAC_TX(0); 64 if (isr1 & 0x30) result |= SCA_INTR_DMAC_RX(1); 65 if (isr1 & 0xC0) result |= SCA_INTR_DMAC_TX(1); 66 if (isr0 & 0x0F) result |= SCA_INTR_MSCI(0); 67 if (isr0 & 0xF0) result |= SCA_INTR_MSCI(1); 68 69 if (!(result & SCA_INTR_DMAC_TX(0))) 70 if (sca_in(DSR_TX(0), card) & DSR_EOM) 71 result |= SCA_INTR_DMAC_TX(0); 72 if (!(result & SCA_INTR_DMAC_TX(1))) 73 if (sca_in(DSR_TX(1), card) & DSR_EOM) 74 result |= SCA_INTR_DMAC_TX(1); 75 76 return result; 77 } 78 79 static inline port_t* dev_to_port(struct net_device *dev) 80 { 81 return dev_to_hdlc(dev)->priv; 82 } 83 84 static inline u16 next_desc(port_t *port, u16 desc, int transmit) 85 { 86 return (desc + 1) % (transmit ? port_to_card(port)->tx_ring_buffers 87 : port_to_card(port)->rx_ring_buffers); 88 } 89 90 91 static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit) 92 { 93 u16 rx_buffs = port_to_card(port)->rx_ring_buffers; 94 u16 tx_buffs = port_to_card(port)->tx_ring_buffers; 95 96 desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc. 97 return log_node(port) * (rx_buffs + tx_buffs) + 98 transmit * rx_buffs + desc; 99 } 100 101 102 static inline u16 desc_offset(port_t *port, u16 desc, int transmit) 103 { 104 /* Descriptor offset always fits in 16 bits */ 105 return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc); 106 } 107 108 109 static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc, 110 int transmit) 111 { 112 #ifdef PAGE0_ALWAYS_MAPPED 113 return (pkt_desc __iomem *)(win0base(port_to_card(port)) 114 + desc_offset(port, desc, transmit)); 115 #else 116 return (pkt_desc __iomem *)(winbase(port_to_card(port)) 117 + desc_offset(port, desc, transmit)); 118 #endif 119 } 120 121 122 static inline u32 buffer_offset(port_t *port, u16 desc, int transmit) 123 { 124 return port_to_card(port)->buff_offset + 125 desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU; 126 } 127 128 129 static inline void sca_set_carrier(port_t *port) 130 { 131 if (!(sca_in(get_msci(port) + ST3, port_to_card(port)) & ST3_DCD)) { 132 #ifdef DEBUG_LINK 133 printk(KERN_DEBUG "%s: sca_set_carrier on\n", 134 port_to_dev(port)->name); 135 #endif 136 netif_carrier_on(port_to_dev(port)); 137 } else { 138 #ifdef DEBUG_LINK 139 printk(KERN_DEBUG "%s: sca_set_carrier off\n", 140 port_to_dev(port)->name); 141 #endif 142 netif_carrier_off(port_to_dev(port)); 143 } 144 } 145 146 147 static void sca_init_port(port_t *port) 148 { 149 card_t *card = port_to_card(port); 150 int transmit, i; 151 152 port->rxin = 0; 153 port->txin = 0; 154 port->txlast = 0; 155 156 #ifndef PAGE0_ALWAYS_MAPPED 157 openwin(card, 0); 158 #endif 159 160 for (transmit = 0; transmit < 2; transmit++) { 161 u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port); 162 u16 buffs = transmit ? card->tx_ring_buffers 163 : card->rx_ring_buffers; 164 165 for (i = 0; i < buffs; i++) { 166 pkt_desc __iomem *desc = desc_address(port, i, transmit); 167 u16 chain_off = desc_offset(port, i + 1, transmit); 168 u32 buff_off = buffer_offset(port, i, transmit); 169 170 writew(chain_off, &desc->cp); 171 writel(buff_off, &desc->bp); 172 writew(0, &desc->len); 173 writeb(0, &desc->stat); 174 } 175 176 /* DMA disable - to halt state */ 177 sca_out(0, transmit ? DSR_TX(phy_node(port)) : 178 DSR_RX(phy_node(port)), card); 179 /* software ABORT - to initial state */ 180 sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) : 181 DCR_RX(phy_node(port)), card); 182 183 /* current desc addr */ 184 sca_out(0, dmac + CPB, card); /* pointer base */ 185 sca_outw(desc_offset(port, 0, transmit), dmac + CDAL, card); 186 if (!transmit) 187 sca_outw(desc_offset(port, buffs - 1, transmit), 188 dmac + EDAL, card); 189 else 190 sca_outw(desc_offset(port, 0, transmit), dmac + EDAL, 191 card); 192 193 /* clear frame end interrupt counter */ 194 sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) : 195 DCR_RX(phy_node(port)), card); 196 197 if (!transmit) { /* Receive */ 198 /* set buffer length */ 199 sca_outw(HDLC_MAX_MRU, dmac + BFLL, card); 200 /* Chain mode, Multi-frame */ 201 sca_out(0x14, DMR_RX(phy_node(port)), card); 202 sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)), 203 card); 204 /* DMA enable */ 205 sca_out(DSR_DE, DSR_RX(phy_node(port)), card); 206 } else { /* Transmit */ 207 /* Chain mode, Multi-frame */ 208 sca_out(0x14, DMR_TX(phy_node(port)), card); 209 /* enable underflow interrupts */ 210 sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card); 211 } 212 } 213 sca_set_carrier(port); 214 } 215 216 217 #ifdef NEED_SCA_MSCI_INTR 218 /* MSCI interrupt service */ 219 static inline void sca_msci_intr(port_t *port) 220 { 221 u16 msci = get_msci(port); 222 card_t* card = port_to_card(port); 223 u8 stat = sca_in(msci + ST1, card); /* read MSCI ST1 status */ 224 225 /* Reset MSCI TX underrun and CDCD status bit */ 226 sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card); 227 228 if (stat & ST1_UDRN) { 229 /* TX Underrun error detected */ 230 port_to_dev(port)->stats.tx_errors++; 231 port_to_dev(port)->stats.tx_fifo_errors++; 232 } 233 234 if (stat & ST1_CDCD) 235 sca_set_carrier(port); 236 } 237 #endif 238 239 240 static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc, 241 u16 rxin) 242 { 243 struct net_device *dev = port_to_dev(port); 244 struct sk_buff *skb; 245 u16 len; 246 u32 buff; 247 u32 maxlen; 248 u8 page; 249 250 len = readw(&desc->len); 251 skb = dev_alloc_skb(len); 252 if (!skb) { 253 dev->stats.rx_dropped++; 254 return; 255 } 256 257 buff = buffer_offset(port, rxin, 0); 258 page = buff / winsize(card); 259 buff = buff % winsize(card); 260 maxlen = winsize(card) - buff; 261 262 openwin(card, page); 263 264 if (len > maxlen) { 265 memcpy_fromio(skb->data, winbase(card) + buff, maxlen); 266 openwin(card, page + 1); 267 memcpy_fromio(skb->data + maxlen, winbase(card), len - maxlen); 268 } else 269 memcpy_fromio(skb->data, winbase(card) + buff, len); 270 271 #ifndef PAGE0_ALWAYS_MAPPED 272 openwin(card, 0); /* select pkt_desc table page back */ 273 #endif 274 skb_put(skb, len); 275 #ifdef DEBUG_PKT 276 printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len); 277 debug_frame(skb); 278 #endif 279 dev->stats.rx_packets++; 280 dev->stats.rx_bytes += skb->len; 281 skb->protocol = hdlc_type_trans(skb, dev); 282 netif_rx(skb); 283 } 284 285 286 /* Receive DMA interrupt service */ 287 static inline void sca_rx_intr(port_t *port) 288 { 289 struct net_device *dev = port_to_dev(port); 290 u16 dmac = get_dmac_rx(port); 291 card_t *card = port_to_card(port); 292 u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */ 293 294 /* Reset DSR status bits */ 295 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, 296 DSR_RX(phy_node(port)), card); 297 298 if (stat & DSR_BOF) 299 /* Dropped one or more frames */ 300 dev->stats.rx_over_errors++; 301 302 while (1) { 303 u32 desc_off = desc_offset(port, port->rxin, 0); 304 pkt_desc __iomem *desc; 305 u32 cda = sca_inw(dmac + CDAL, card); 306 307 if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc))) 308 break; /* No frame received */ 309 310 desc = desc_address(port, port->rxin, 0); 311 stat = readb(&desc->stat); 312 if (!(stat & ST_RX_EOM)) 313 port->rxpart = 1; /* partial frame received */ 314 else if ((stat & ST_ERROR_MASK) || port->rxpart) { 315 dev->stats.rx_errors++; 316 if (stat & ST_RX_OVERRUN) 317 dev->stats.rx_fifo_errors++; 318 else if ((stat & (ST_RX_SHORT | ST_RX_ABORT | 319 ST_RX_RESBIT)) || port->rxpart) 320 dev->stats.rx_frame_errors++; 321 else if (stat & ST_RX_CRC) 322 dev->stats.rx_crc_errors++; 323 if (stat & ST_RX_EOM) 324 port->rxpart = 0; /* received last fragment */ 325 } else 326 sca_rx(card, port, desc, port->rxin); 327 328 /* Set new error descriptor address */ 329 sca_outw(desc_off, dmac + EDAL, card); 330 port->rxin = next_desc(port, port->rxin, 0); 331 } 332 333 /* make sure RX DMA is enabled */ 334 sca_out(DSR_DE, DSR_RX(phy_node(port)), card); 335 } 336 337 338 /* Transmit DMA interrupt service */ 339 static inline void sca_tx_intr(port_t *port) 340 { 341 struct net_device *dev = port_to_dev(port); 342 u16 dmac = get_dmac_tx(port); 343 card_t* card = port_to_card(port); 344 u8 stat; 345 346 spin_lock(&port->lock); 347 348 stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */ 349 350 /* Reset DSR status bits */ 351 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, 352 DSR_TX(phy_node(port)), card); 353 354 while (1) { 355 pkt_desc __iomem *desc; 356 357 u32 desc_off = desc_offset(port, port->txlast, 1); 358 u32 cda = sca_inw(dmac + CDAL, card); 359 if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc))) 360 break; /* Transmitter is/will_be sending this frame */ 361 362 desc = desc_address(port, port->txlast, 1); 363 dev->stats.tx_packets++; 364 dev->stats.tx_bytes += readw(&desc->len); 365 writeb(0, &desc->stat); /* Free descriptor */ 366 port->txlast = next_desc(port, port->txlast, 1); 367 } 368 369 netif_wake_queue(dev); 370 spin_unlock(&port->lock); 371 } 372 373 374 static irqreturn_t sca_intr(int irq, void* dev_id) 375 { 376 card_t *card = dev_id; 377 int i; 378 u8 stat; 379 int handled = 0; 380 u8 page = sca_get_page(card); 381 382 while((stat = sca_intr_status(card)) != 0) { 383 handled = 1; 384 for (i = 0; i < 2; i++) { 385 port_t *port = get_port(card, i); 386 if (port) { 387 if (stat & SCA_INTR_MSCI(i)) 388 sca_msci_intr(port); 389 390 if (stat & SCA_INTR_DMAC_RX(i)) 391 sca_rx_intr(port); 392 393 if (stat & SCA_INTR_DMAC_TX(i)) 394 sca_tx_intr(port); 395 } 396 } 397 } 398 399 openwin(card, page); /* Restore original page */ 400 return IRQ_RETVAL(handled); 401 } 402 403 404 static void sca_set_port(port_t *port) 405 { 406 card_t* card = port_to_card(port); 407 u16 msci = get_msci(port); 408 u8 md2 = sca_in(msci + MD2, card); 409 unsigned int tmc, br = 10, brv = 1024; 410 411 412 if (port->settings.clock_rate > 0) { 413 /* Try lower br for better accuracy*/ 414 do { 415 br--; 416 brv >>= 1; /* brv = 2^9 = 512 max in specs */ 417 418 /* Baud Rate = CLOCK_BASE / TMC / 2^BR */ 419 tmc = CLOCK_BASE / brv / port->settings.clock_rate; 420 }while (br > 1 && tmc <= 128); 421 422 if (tmc < 1) { 423 tmc = 1; 424 br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */ 425 brv = 1; 426 } else if (tmc > 255) 427 tmc = 256; /* tmc=0 means 256 - low baud rates */ 428 429 port->settings.clock_rate = CLOCK_BASE / brv / tmc; 430 } else { 431 br = 9; /* Minimum clock rate */ 432 tmc = 256; /* 8bit = 0 */ 433 port->settings.clock_rate = CLOCK_BASE / (256 * 512); 434 } 435 436 port->rxs = (port->rxs & ~CLK_BRG_MASK) | br; 437 port->txs = (port->txs & ~CLK_BRG_MASK) | br; 438 port->tmc = tmc; 439 440 /* baud divisor - time constant*/ 441 sca_out(port->tmc, msci + TMC, card); 442 443 /* Set BRG bits */ 444 sca_out(port->rxs, msci + RXS, card); 445 sca_out(port->txs, msci + TXS, card); 446 447 if (port->settings.loopback) 448 md2 |= MD2_LOOPBACK; 449 else 450 md2 &= ~MD2_LOOPBACK; 451 452 sca_out(md2, msci + MD2, card); 453 454 } 455 456 457 static void sca_open(struct net_device *dev) 458 { 459 port_t *port = dev_to_port(dev); 460 card_t* card = port_to_card(port); 461 u16 msci = get_msci(port); 462 u8 md0, md2; 463 464 switch(port->encoding) { 465 case ENCODING_NRZ: md2 = MD2_NRZ; break; 466 case ENCODING_NRZI: md2 = MD2_NRZI; break; 467 case ENCODING_FM_MARK: md2 = MD2_FM_MARK; break; 468 case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE; break; 469 default: md2 = MD2_MANCHESTER; 470 } 471 472 if (port->settings.loopback) 473 md2 |= MD2_LOOPBACK; 474 475 switch(port->parity) { 476 case PARITY_CRC16_PR0: md0 = MD0_HDLC | MD0_CRC_16_0; break; 477 case PARITY_CRC16_PR1: md0 = MD0_HDLC | MD0_CRC_16; break; 478 case PARITY_CRC16_PR0_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU_0; break; 479 case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU; break; 480 default: md0 = MD0_HDLC | MD0_CRC_NONE; 481 } 482 483 sca_out(CMD_RESET, msci + CMD, card); 484 sca_out(md0, msci + MD0, card); 485 sca_out(0x00, msci + MD1, card); /* no address field check */ 486 sca_out(md2, msci + MD2, card); 487 sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */ 488 sca_out(CTL_IDLE, msci + CTL, card); 489 490 /* Allow at least 8 bytes before requesting RX DMA operation */ 491 /* TX with higher priority and possibly with shorter transfers */ 492 sca_out(0x07, msci + RRC, card); /* +1=RXRDY/DMA activation condition*/ 493 sca_out(0x10, msci + TRC0, card); /* = TXRDY/DMA activation condition*/ 494 sca_out(0x14, msci + TRC1, card); /* +1=TXRDY/DMA deactiv condition */ 495 496 /* We're using the following interrupts: 497 - TXINT (DMAC completed all transmisions, underrun or DCD change) 498 - all DMA interrupts 499 */ 500 sca_set_carrier(port); 501 502 /* MSCI TX INT and RX INT A IRQ enable */ 503 sca_out(IE0_TXINT | IE0_RXINTA, msci + IE0, card); 504 sca_out(IE1_UDRN | IE1_CDCD, msci + IE1, card); 505 sca_out(sca_in(IER0, card) | (phy_node(port) ? 0xC0 : 0x0C), 506 IER0, card); /* TXINT and RXINT */ 507 /* enable DMA IRQ */ 508 sca_out(sca_in(IER1, card) | (phy_node(port) ? 0xF0 : 0x0F), 509 IER1, card); 510 511 sca_out(port->tmc, msci + TMC, card); /* Restore registers */ 512 sca_out(port->rxs, msci + RXS, card); 513 sca_out(port->txs, msci + TXS, card); 514 sca_out(CMD_TX_ENABLE, msci + CMD, card); 515 sca_out(CMD_RX_ENABLE, msci + CMD, card); 516 517 netif_start_queue(dev); 518 } 519 520 521 static void sca_close(struct net_device *dev) 522 { 523 port_t *port = dev_to_port(dev); 524 card_t* card = port_to_card(port); 525 526 /* reset channel */ 527 sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port)); 528 /* disable MSCI interrupts */ 529 sca_out(sca_in(IER0, card) & (phy_node(port) ? 0x0F : 0xF0), 530 IER0, card); 531 /* disable DMA interrupts */ 532 sca_out(sca_in(IER1, card) & (phy_node(port) ? 0x0F : 0xF0), 533 IER1, card); 534 535 netif_stop_queue(dev); 536 } 537 538 539 static int sca_attach(struct net_device *dev, unsigned short encoding, 540 unsigned short parity) 541 { 542 if (encoding != ENCODING_NRZ && 543 encoding != ENCODING_NRZI && 544 encoding != ENCODING_FM_MARK && 545 encoding != ENCODING_FM_SPACE && 546 encoding != ENCODING_MANCHESTER) 547 return -EINVAL; 548 549 if (parity != PARITY_NONE && 550 parity != PARITY_CRC16_PR0 && 551 parity != PARITY_CRC16_PR1 && 552 parity != PARITY_CRC16_PR0_CCITT && 553 parity != PARITY_CRC16_PR1_CCITT) 554 return -EINVAL; 555 556 dev_to_port(dev)->encoding = encoding; 557 dev_to_port(dev)->parity = parity; 558 return 0; 559 } 560 561 562 #ifdef DEBUG_RINGS 563 static void sca_dump_rings(struct net_device *dev) 564 { 565 port_t *port = dev_to_port(dev); 566 card_t *card = port_to_card(port); 567 u16 cnt; 568 #ifndef PAGE0_ALWAYS_MAPPED 569 u8 page = sca_get_page(card); 570 571 openwin(card, 0); 572 #endif 573 574 printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive", 575 sca_inw(get_dmac_rx(port) + CDAL, card), 576 sca_inw(get_dmac_rx(port) + EDAL, card), 577 sca_in(DSR_RX(phy_node(port)), card), port->rxin, 578 sca_in(DSR_RX(phy_node(port)), card) & DSR_DE ? "" : "in"); 579 for (cnt = 0; cnt < port_to_card(port)->rx_ring_buffers; cnt++) 580 pr_cont(" %02X", readb(&(desc_address(port, cnt, 0)->stat))); 581 pr_cont("\n"); 582 583 printk(KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u " 584 "last=%u %sactive", 585 sca_inw(get_dmac_tx(port) + CDAL, card), 586 sca_inw(get_dmac_tx(port) + EDAL, card), 587 sca_in(DSR_TX(phy_node(port)), card), port->txin, port->txlast, 588 sca_in(DSR_TX(phy_node(port)), card) & DSR_DE ? "" : "in"); 589 590 for (cnt = 0; cnt < port_to_card(port)->tx_ring_buffers; cnt++) 591 pr_cont(" %02X", readb(&(desc_address(port, cnt, 1)->stat))); 592 pr_cont("\n"); 593 594 printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x, ST: %02x %02x %02x %02x," 595 " FST: %02x CST: %02x %02x\n", 596 sca_in(get_msci(port) + MD0, card), 597 sca_in(get_msci(port) + MD1, card), 598 sca_in(get_msci(port) + MD2, card), 599 sca_in(get_msci(port) + ST0, card), 600 sca_in(get_msci(port) + ST1, card), 601 sca_in(get_msci(port) + ST2, card), 602 sca_in(get_msci(port) + ST3, card), 603 sca_in(get_msci(port) + FST, card), 604 sca_in(get_msci(port) + CST0, card), 605 sca_in(get_msci(port) + CST1, card)); 606 607 printk(KERN_DEBUG "ISR: %02x %02x %02x\n", sca_in(ISR0, card), 608 sca_in(ISR1, card), sca_in(ISR2, card)); 609 610 #ifndef PAGE0_ALWAYS_MAPPED 611 openwin(card, page); /* Restore original page */ 612 #endif 613 } 614 #endif /* DEBUG_RINGS */ 615 616 617 static netdev_tx_t sca_xmit(struct sk_buff *skb, struct net_device *dev) 618 { 619 port_t *port = dev_to_port(dev); 620 card_t *card = port_to_card(port); 621 pkt_desc __iomem *desc; 622 u32 buff, len; 623 u8 page; 624 u32 maxlen; 625 626 spin_lock_irq(&port->lock); 627 628 desc = desc_address(port, port->txin + 1, 1); 629 BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */ 630 631 #ifdef DEBUG_PKT 632 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len); 633 debug_frame(skb); 634 #endif 635 636 desc = desc_address(port, port->txin, 1); 637 buff = buffer_offset(port, port->txin, 1); 638 len = skb->len; 639 page = buff / winsize(card); 640 buff = buff % winsize(card); 641 maxlen = winsize(card) - buff; 642 643 openwin(card, page); 644 if (len > maxlen) { 645 memcpy_toio(winbase(card) + buff, skb->data, maxlen); 646 openwin(card, page + 1); 647 memcpy_toio(winbase(card), skb->data + maxlen, len - maxlen); 648 } else 649 memcpy_toio(winbase(card) + buff, skb->data, len); 650 651 #ifndef PAGE0_ALWAYS_MAPPED 652 openwin(card, 0); /* select pkt_desc table page back */ 653 #endif 654 writew(len, &desc->len); 655 writeb(ST_TX_EOM, &desc->stat); 656 657 port->txin = next_desc(port, port->txin, 1); 658 sca_outw(desc_offset(port, port->txin, 1), 659 get_dmac_tx(port) + EDAL, card); 660 661 sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */ 662 663 desc = desc_address(port, port->txin + 1, 1); 664 if (readb(&desc->stat)) /* allow 1 packet gap */ 665 netif_stop_queue(dev); 666 667 spin_unlock_irq(&port->lock); 668 669 dev_kfree_skb(skb); 670 return NETDEV_TX_OK; 671 } 672 673 674 #ifdef NEED_DETECT_RAM 675 static u32 sca_detect_ram(card_t *card, u8 __iomem *rambase, u32 ramsize) 676 { 677 /* Round RAM size to 32 bits, fill from end to start */ 678 u32 i = ramsize &= ~3; 679 u32 size = winsize(card); 680 681 openwin(card, (i - 4) / size); /* select last window */ 682 683 do { 684 i -= 4; 685 if ((i + 4) % size == 0) 686 openwin(card, i / size); 687 writel(i ^ 0x12345678, rambase + i % size); 688 } while (i > 0); 689 690 for (i = 0; i < ramsize ; i += 4) { 691 if (i % size == 0) 692 openwin(card, i / size); 693 694 if (readl(rambase + i % size) != (i ^ 0x12345678)) 695 break; 696 } 697 698 return i; 699 } 700 #endif /* NEED_DETECT_RAM */ 701 702 703 static void sca_init(card_t *card, int wait_states) 704 { 705 sca_out(wait_states, WCRL, card); /* Wait Control */ 706 sca_out(wait_states, WCRM, card); 707 sca_out(wait_states, WCRH, card); 708 709 sca_out(0, DMER, card); /* DMA Master disable */ 710 sca_out(0x03, PCR, card); /* DMA priority */ 711 sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */ 712 sca_out(0, DSR_TX(0), card); 713 sca_out(0, DSR_RX(1), card); 714 sca_out(0, DSR_TX(1), card); 715 sca_out(DMER_DME, DMER, card); /* DMA Master enable */ 716 } 717