1 /* 2 * FarSync WAN driver for Linux (2.6.x kernel version) 3 * 4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards 5 * 6 * Copyright (C) 2001-2004 FarSite Communications Ltd. 7 * www.farsite.co.uk 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk> 15 * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk> 16 */ 17 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/version.h> 21 #include <linux/pci.h> 22 #include <linux/ioport.h> 23 #include <linux/init.h> 24 #include <linux/if.h> 25 #include <linux/hdlc.h> 26 #include <asm/io.h> 27 #include <asm/uaccess.h> 28 29 #include "farsync.h" 30 31 /* 32 * Module info 33 */ 34 MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>"); 35 MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd."); 36 MODULE_LICENSE("GPL"); 37 38 /* Driver configuration and global parameters 39 * ========================================== 40 */ 41 42 /* Number of ports (per card) and cards supported 43 */ 44 #define FST_MAX_PORTS 4 45 #define FST_MAX_CARDS 32 46 47 /* Default parameters for the link 48 */ 49 #define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is 50 * useful, the syncppp module forces 51 * this down assuming a slower line I 52 * guess. 53 */ 54 #define FST_TXQ_DEPTH 16 /* This one is for the buffering 55 * of frames on the way down to the card 56 * so that we can keep the card busy 57 * and maximise throughput 58 */ 59 #define FST_HIGH_WATER_MARK 12 /* Point at which we flow control 60 * network layer */ 61 #define FST_LOW_WATER_MARK 8 /* Point at which we remove flow 62 * control from network layer */ 63 #define FST_MAX_MTU 8000 /* Huge but possible */ 64 #define FST_DEF_MTU 1500 /* Common sane value */ 65 66 #define FST_TX_TIMEOUT (2*HZ) 67 68 #ifdef ARPHRD_RAWHDLC 69 #define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */ 70 #else 71 #define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */ 72 #endif 73 74 /* 75 * Modules parameters and associated varaibles 76 */ 77 static int fst_txq_low = FST_LOW_WATER_MARK; 78 static int fst_txq_high = FST_HIGH_WATER_MARK; 79 static int fst_max_reads = 7; 80 static int fst_excluded_cards = 0; 81 static int fst_excluded_list[FST_MAX_CARDS]; 82 83 module_param(fst_txq_low, int, 0); 84 module_param(fst_txq_high, int, 0); 85 module_param(fst_max_reads, int, 0); 86 module_param(fst_excluded_cards, int, 0); 87 module_param_array(fst_excluded_list, int, NULL, 0); 88 89 /* Card shared memory layout 90 * ========================= 91 */ 92 #pragma pack(1) 93 94 /* This information is derived in part from the FarSite FarSync Smc.h 95 * file. Unfortunately various name clashes and the non-portability of the 96 * bit field declarations in that file have meant that I have chosen to 97 * recreate the information here. 98 * 99 * The SMC (Shared Memory Configuration) has a version number that is 100 * incremented every time there is a significant change. This number can 101 * be used to check that we have not got out of step with the firmware 102 * contained in the .CDE files. 103 */ 104 #define SMC_VERSION 24 105 106 #define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */ 107 108 #define SMC_BASE 0x00002000L /* Base offset of the shared memory window main 109 * configuration structure */ 110 #define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA 111 * buffers */ 112 113 #define LEN_TX_BUFFER 8192 /* Size of packet buffers */ 114 #define LEN_RX_BUFFER 8192 115 116 #define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */ 117 #define LEN_SMALL_RX_BUFFER 256 118 119 #define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */ 120 #define NUM_RX_BUFFER 8 121 122 /* Interrupt retry time in milliseconds */ 123 #define INT_RETRY_TIME 2 124 125 /* The Am186CH/CC processors support a SmartDMA mode using circular pools 126 * of buffer descriptors. The structure is almost identical to that used 127 * in the LANCE Ethernet controllers. Details available as PDF from the 128 * AMD web site: http://www.amd.com/products/epd/processors/\ 129 * 2.16bitcont/3.am186cxfa/a21914/21914.pdf 130 */ 131 struct txdesc { /* Transmit descriptor */ 132 volatile u16 ladr; /* Low order address of packet. This is a 133 * linear address in the Am186 memory space 134 */ 135 volatile u8 hadr; /* High order address. Low 4 bits only, high 4 136 * bits must be zero 137 */ 138 volatile u8 bits; /* Status and config */ 139 volatile u16 bcnt; /* 2s complement of packet size in low 15 bits. 140 * Transmit terminal count interrupt enable in 141 * top bit. 142 */ 143 u16 unused; /* Not used in Tx */ 144 }; 145 146 struct rxdesc { /* Receive descriptor */ 147 volatile u16 ladr; /* Low order address of packet */ 148 volatile u8 hadr; /* High order address */ 149 volatile u8 bits; /* Status and config */ 150 volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits. 151 * Receive terminal count interrupt enable in 152 * top bit. 153 */ 154 volatile u16 mcnt; /* Message byte count (15 bits) */ 155 }; 156 157 /* Convert a length into the 15 bit 2's complement */ 158 /* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */ 159 /* Since we need to set the high bit to enable the completion interrupt this 160 * can be made a lot simpler 161 */ 162 #define cnv_bcnt(len) (-(len)) 163 164 /* Status and config bits for the above */ 165 #define DMA_OWN 0x80 /* SmartDMA owns the descriptor */ 166 #define TX_STP 0x02 /* Tx: start of packet */ 167 #define TX_ENP 0x01 /* Tx: end of packet */ 168 #define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */ 169 #define RX_FRAM 0x20 /* Rx: framing error */ 170 #define RX_OFLO 0x10 /* Rx: overflow error */ 171 #define RX_CRC 0x08 /* Rx: CRC error */ 172 #define RX_HBUF 0x04 /* Rx: buffer error */ 173 #define RX_STP 0x02 /* Rx: start of packet */ 174 #define RX_ENP 0x01 /* Rx: end of packet */ 175 176 /* Interrupts from the card are caused by various events which are presented 177 * in a circular buffer as several events may be processed on one physical int 178 */ 179 #define MAX_CIRBUFF 32 180 181 struct cirbuff { 182 u8 rdindex; /* read, then increment and wrap */ 183 u8 wrindex; /* write, then increment and wrap */ 184 u8 evntbuff[MAX_CIRBUFF]; 185 }; 186 187 /* Interrupt event codes. 188 * Where appropriate the two low order bits indicate the port number 189 */ 190 #define CTLA_CHG 0x18 /* Control signal changed */ 191 #define CTLB_CHG 0x19 192 #define CTLC_CHG 0x1A 193 #define CTLD_CHG 0x1B 194 195 #define INIT_CPLT 0x20 /* Initialisation complete */ 196 #define INIT_FAIL 0x21 /* Initialisation failed */ 197 198 #define ABTA_SENT 0x24 /* Abort sent */ 199 #define ABTB_SENT 0x25 200 #define ABTC_SENT 0x26 201 #define ABTD_SENT 0x27 202 203 #define TXA_UNDF 0x28 /* Transmission underflow */ 204 #define TXB_UNDF 0x29 205 #define TXC_UNDF 0x2A 206 #define TXD_UNDF 0x2B 207 208 #define F56_INT 0x2C 209 #define M32_INT 0x2D 210 211 #define TE1_ALMA 0x30 212 213 /* Port physical configuration. See farsync.h for field values */ 214 struct port_cfg { 215 u16 lineInterface; /* Physical interface type */ 216 u8 x25op; /* Unused at present */ 217 u8 internalClock; /* 1 => internal clock, 0 => external */ 218 u8 transparentMode; /* 1 => on, 0 => off */ 219 u8 invertClock; /* 0 => normal, 1 => inverted */ 220 u8 padBytes[6]; /* Padding */ 221 u32 lineSpeed; /* Speed in bps */ 222 }; 223 224 /* TE1 port physical configuration */ 225 struct su_config { 226 u32 dataRate; 227 u8 clocking; 228 u8 framing; 229 u8 structure; 230 u8 interface; 231 u8 coding; 232 u8 lineBuildOut; 233 u8 equalizer; 234 u8 transparentMode; 235 u8 loopMode; 236 u8 range; 237 u8 txBufferMode; 238 u8 rxBufferMode; 239 u8 startingSlot; 240 u8 losThreshold; 241 u8 enableIdleCode; 242 u8 idleCode; 243 u8 spare[44]; 244 }; 245 246 /* TE1 Status */ 247 struct su_status { 248 u32 receiveBufferDelay; 249 u32 framingErrorCount; 250 u32 codeViolationCount; 251 u32 crcErrorCount; 252 u32 lineAttenuation; 253 u8 portStarted; 254 u8 lossOfSignal; 255 u8 receiveRemoteAlarm; 256 u8 alarmIndicationSignal; 257 u8 spare[40]; 258 }; 259 260 /* Finally sling all the above together into the shared memory structure. 261 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been 262 * evolving under NT for some time so I guess we're stuck with it. 263 * The structure starts at offset SMC_BASE. 264 * See farsync.h for some field values. 265 */ 266 struct fst_shared { 267 /* DMA descriptor rings */ 268 struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER]; 269 struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER]; 270 271 /* Obsolete small buffers */ 272 u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER]; 273 u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER]; 274 275 u8 taskStatus; /* 0x00 => initialising, 0x01 => running, 276 * 0xFF => halted 277 */ 278 279 u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt, 280 * set to 0xEE by host to acknowledge interrupt 281 */ 282 283 u16 smcVersion; /* Must match SMC_VERSION */ 284 285 u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major 286 * version, RR = revision and BB = build 287 */ 288 289 u16 txa_done; /* Obsolete completion flags */ 290 u16 rxa_done; 291 u16 txb_done; 292 u16 rxb_done; 293 u16 txc_done; 294 u16 rxc_done; 295 u16 txd_done; 296 u16 rxd_done; 297 298 u16 mailbox[4]; /* Diagnostics mailbox. Not used */ 299 300 struct cirbuff interruptEvent; /* interrupt causes */ 301 302 u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */ 303 u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */ 304 305 struct port_cfg portConfig[FST_MAX_PORTS]; 306 307 u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */ 308 309 u16 cableStatus; /* lsb: 0=> present, 1=> absent */ 310 311 u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */ 312 u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */ 313 314 u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */ 315 u16 cardMailbox[4]; /* Not used */ 316 317 /* Number of times the card thinks the host has 318 * missed an interrupt by not acknowledging 319 * within 2mS (I guess NT has problems) 320 */ 321 u32 interruptRetryCount; 322 323 /* Driver private data used as an ID. We'll not 324 * use this as I'd rather keep such things 325 * in main memory rather than on the PCI bus 326 */ 327 u32 portHandle[FST_MAX_PORTS]; 328 329 /* Count of Tx underflows for stats */ 330 u32 transmitBufferUnderflow[FST_MAX_PORTS]; 331 332 /* Debounced V.24 control input status */ 333 u32 v24DebouncedSts[FST_MAX_PORTS]; 334 335 /* Adapter debounce timers. Don't touch */ 336 u32 ctsTimer[FST_MAX_PORTS]; 337 u32 ctsTimerRun[FST_MAX_PORTS]; 338 u32 dcdTimer[FST_MAX_PORTS]; 339 u32 dcdTimerRun[FST_MAX_PORTS]; 340 341 u32 numberOfPorts; /* Number of ports detected at startup */ 342 343 u16 _reserved[64]; 344 345 u16 cardMode; /* Bit-mask to enable features: 346 * Bit 0: 1 enables LED identify mode 347 */ 348 349 u16 portScheduleOffset; 350 351 struct su_config suConfig; /* TE1 Bits */ 352 struct su_status suStatus; 353 354 u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of 355 * the structure and marks the end of shared 356 * memory. Adapter code initializes it as 357 * END_SIG. 358 */ 359 }; 360 361 /* endOfSmcSignature value */ 362 #define END_SIG 0x12345678 363 364 /* Mailbox values. (portMailbox) */ 365 #define NOP 0 /* No operation */ 366 #define ACK 1 /* Positive acknowledgement to PC driver */ 367 #define NAK 2 /* Negative acknowledgement to PC driver */ 368 #define STARTPORT 3 /* Start an HDLC port */ 369 #define STOPPORT 4 /* Stop an HDLC port */ 370 #define ABORTTX 5 /* Abort the transmitter for a port */ 371 #define SETV24O 6 /* Set V24 outputs */ 372 373 /* PLX Chip Register Offsets */ 374 #define CNTRL_9052 0x50 /* Control Register */ 375 #define CNTRL_9054 0x6c /* Control Register */ 376 377 #define INTCSR_9052 0x4c /* Interrupt control/status register */ 378 #define INTCSR_9054 0x68 /* Interrupt control/status register */ 379 380 /* 9054 DMA Registers */ 381 /* 382 * Note that we will be using DMA Channel 0 for copying rx data 383 * and Channel 1 for copying tx data 384 */ 385 #define DMAMODE0 0x80 386 #define DMAPADR0 0x84 387 #define DMALADR0 0x88 388 #define DMASIZ0 0x8c 389 #define DMADPR0 0x90 390 #define DMAMODE1 0x94 391 #define DMAPADR1 0x98 392 #define DMALADR1 0x9c 393 #define DMASIZ1 0xa0 394 #define DMADPR1 0xa4 395 #define DMACSR0 0xa8 396 #define DMACSR1 0xa9 397 #define DMAARB 0xac 398 #define DMATHR 0xb0 399 #define DMADAC0 0xb4 400 #define DMADAC1 0xb8 401 #define DMAMARBR 0xac 402 403 #define FST_MIN_DMA_LEN 64 404 #define FST_RX_DMA_INT 0x01 405 #define FST_TX_DMA_INT 0x02 406 #define FST_CARD_INT 0x04 407 408 /* Larger buffers are positioned in memory at offset BFM_BASE */ 409 struct buf_window { 410 u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER]; 411 u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER]; 412 }; 413 414 /* Calculate offset of a buffer object within the shared memory window */ 415 #define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X)) 416 417 #pragma pack() 418 419 /* Device driver private information 420 * ================================= 421 */ 422 /* Per port (line or channel) information 423 */ 424 struct fst_port_info { 425 struct net_device *dev; /* Device struct - must be first */ 426 struct fst_card_info *card; /* Card we're associated with */ 427 int index; /* Port index on the card */ 428 int hwif; /* Line hardware (lineInterface copy) */ 429 int run; /* Port is running */ 430 int mode; /* Normal or FarSync raw */ 431 int rxpos; /* Next Rx buffer to use */ 432 int txpos; /* Next Tx buffer to use */ 433 int txipos; /* Next Tx buffer to check for free */ 434 int start; /* Indication of start/stop to network */ 435 /* 436 * A sixteen entry transmit queue 437 */ 438 int txqs; /* index to get next buffer to tx */ 439 int txqe; /* index to queue next packet */ 440 struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */ 441 int rxqdepth; 442 }; 443 444 /* Per card information 445 */ 446 struct fst_card_info { 447 char __iomem *mem; /* Card memory mapped to kernel space */ 448 char __iomem *ctlmem; /* Control memory for PCI cards */ 449 unsigned int phys_mem; /* Physical memory window address */ 450 unsigned int phys_ctlmem; /* Physical control memory address */ 451 unsigned int irq; /* Interrupt request line number */ 452 unsigned int nports; /* Number of serial ports */ 453 unsigned int type; /* Type index of card */ 454 unsigned int state; /* State of card */ 455 spinlock_t card_lock; /* Lock for SMP access */ 456 unsigned short pci_conf; /* PCI card config in I/O space */ 457 /* Per port info */ 458 struct fst_port_info ports[FST_MAX_PORTS]; 459 struct pci_dev *device; /* Information about the pci device */ 460 int card_no; /* Inst of the card on the system */ 461 int family; /* TxP or TxU */ 462 int dmarx_in_progress; 463 int dmatx_in_progress; 464 unsigned long int_count; 465 unsigned long int_time_ave; 466 void *rx_dma_handle_host; 467 dma_addr_t rx_dma_handle_card; 468 void *tx_dma_handle_host; 469 dma_addr_t tx_dma_handle_card; 470 struct sk_buff *dma_skb_rx; 471 struct fst_port_info *dma_port_rx; 472 struct fst_port_info *dma_port_tx; 473 int dma_len_rx; 474 int dma_len_tx; 475 int dma_txpos; 476 int dma_rxpos; 477 }; 478 479 /* Convert an HDLC device pointer into a port info pointer and similar */ 480 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 481 #define port_to_dev(P) ((P)->dev) 482 483 484 /* 485 * Shared memory window access macros 486 * 487 * We have a nice memory based structure above, which could be directly 488 * mapped on i386 but might not work on other architectures unless we use 489 * the readb,w,l and writeb,w,l macros. Unfortunately these macros take 490 * physical offsets so we have to convert. The only saving grace is that 491 * this should all collapse back to a simple indirection eventually. 492 */ 493 #define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X)) 494 495 #define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E)) 496 #define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E)) 497 #define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E)) 498 499 #define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E)) 500 #define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E)) 501 #define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E)) 502 503 /* 504 * Debug support 505 */ 506 #if FST_DEBUG 507 508 static int fst_debug_mask = { FST_DEBUG }; 509 510 /* Most common debug activity is to print something if the corresponding bit 511 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to 512 * support variable numbers of macro parameters. The inverted if prevents us 513 * eating someone else's else clause. 514 */ 515 #define dbg(F,fmt,A...) if ( ! ( fst_debug_mask & (F))) \ 516 ; \ 517 else \ 518 printk ( KERN_DEBUG FST_NAME ": " fmt, ## A ) 519 520 #else 521 #define dbg(X...) /* NOP */ 522 #endif 523 524 /* Printing short cuts 525 */ 526 #define printk_err(fmt,A...) printk ( KERN_ERR FST_NAME ": " fmt, ## A ) 527 #define printk_warn(fmt,A...) printk ( KERN_WARNING FST_NAME ": " fmt, ## A ) 528 #define printk_info(fmt,A...) printk ( KERN_INFO FST_NAME ": " fmt, ## A ) 529 530 /* 531 * PCI ID lookup table 532 */ 533 static struct pci_device_id fst_pci_dev_id[] __devinitdata = { 534 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID, 535 PCI_ANY_ID, 0, 0, FST_TYPE_T2P}, 536 537 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID, 538 PCI_ANY_ID, 0, 0, FST_TYPE_T4P}, 539 540 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID, 541 PCI_ANY_ID, 0, 0, FST_TYPE_T1U}, 542 543 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID, 544 PCI_ANY_ID, 0, 0, FST_TYPE_T2U}, 545 546 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID, 547 PCI_ANY_ID, 0, 0, FST_TYPE_T4U}, 548 549 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID, 550 PCI_ANY_ID, 0, 0, FST_TYPE_TE1}, 551 552 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID, 553 PCI_ANY_ID, 0, 0, FST_TYPE_TE1}, 554 {0,} /* End */ 555 }; 556 557 MODULE_DEVICE_TABLE(pci, fst_pci_dev_id); 558 559 /* 560 * Device Driver Work Queues 561 * 562 * So that we don't spend too much time processing events in the 563 * Interrupt Service routine, we will declare a work queue per Card 564 * and make the ISR schedule a task in the queue for later execution. 565 * In the 2.4 Kernel we used to use the immediate queue for BH's 566 * Now that they are gone, tasklets seem to be much better than work 567 * queues. 568 */ 569 570 static void do_bottom_half_tx(struct fst_card_info *card); 571 static void do_bottom_half_rx(struct fst_card_info *card); 572 static void fst_process_tx_work_q(unsigned long work_q); 573 static void fst_process_int_work_q(unsigned long work_q); 574 575 static DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q, 0); 576 static DECLARE_TASKLET(fst_int_task, fst_process_int_work_q, 0); 577 578 static struct fst_card_info *fst_card_array[FST_MAX_CARDS]; 579 static spinlock_t fst_work_q_lock; 580 static u64 fst_work_txq; 581 static u64 fst_work_intq; 582 583 static void 584 fst_q_work_item(u64 * queue, int card_index) 585 { 586 unsigned long flags; 587 u64 mask; 588 589 /* 590 * Grab the queue exclusively 591 */ 592 spin_lock_irqsave(&fst_work_q_lock, flags); 593 594 /* 595 * Making an entry in the queue is simply a matter of setting 596 * a bit for the card indicating that there is work to do in the 597 * bottom half for the card. Note the limitation of 64 cards. 598 * That ought to be enough 599 */ 600 mask = 1 << card_index; 601 *queue |= mask; 602 spin_unlock_irqrestore(&fst_work_q_lock, flags); 603 } 604 605 static void 606 fst_process_tx_work_q(unsigned long /*void **/work_q) 607 { 608 unsigned long flags; 609 u64 work_txq; 610 int i; 611 612 /* 613 * Grab the queue exclusively 614 */ 615 dbg(DBG_TX, "fst_process_tx_work_q\n"); 616 spin_lock_irqsave(&fst_work_q_lock, flags); 617 work_txq = fst_work_txq; 618 fst_work_txq = 0; 619 spin_unlock_irqrestore(&fst_work_q_lock, flags); 620 621 /* 622 * Call the bottom half for each card with work waiting 623 */ 624 for (i = 0; i < FST_MAX_CARDS; i++) { 625 if (work_txq & 0x01) { 626 if (fst_card_array[i] != NULL) { 627 dbg(DBG_TX, "Calling tx bh for card %d\n", i); 628 do_bottom_half_tx(fst_card_array[i]); 629 } 630 } 631 work_txq = work_txq >> 1; 632 } 633 } 634 635 static void 636 fst_process_int_work_q(unsigned long /*void **/work_q) 637 { 638 unsigned long flags; 639 u64 work_intq; 640 int i; 641 642 /* 643 * Grab the queue exclusively 644 */ 645 dbg(DBG_INTR, "fst_process_int_work_q\n"); 646 spin_lock_irqsave(&fst_work_q_lock, flags); 647 work_intq = fst_work_intq; 648 fst_work_intq = 0; 649 spin_unlock_irqrestore(&fst_work_q_lock, flags); 650 651 /* 652 * Call the bottom half for each card with work waiting 653 */ 654 for (i = 0; i < FST_MAX_CARDS; i++) { 655 if (work_intq & 0x01) { 656 if (fst_card_array[i] != NULL) { 657 dbg(DBG_INTR, 658 "Calling rx & tx bh for card %d\n", i); 659 do_bottom_half_rx(fst_card_array[i]); 660 do_bottom_half_tx(fst_card_array[i]); 661 } 662 } 663 work_intq = work_intq >> 1; 664 } 665 } 666 667 /* Card control functions 668 * ====================== 669 */ 670 /* Place the processor in reset state 671 * 672 * Used to be a simple write to card control space but a glitch in the latest 673 * AMD Am186CH processor means that we now have to do it by asserting and de- 674 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register 675 * at offset 9052_CNTRL. Note the updates for the TXU. 676 */ 677 static inline void 678 fst_cpureset(struct fst_card_info *card) 679 { 680 unsigned char interrupt_line_register; 681 unsigned long j = jiffies + 1; 682 unsigned int regval; 683 684 if (card->family == FST_FAMILY_TXU) { 685 if (pci_read_config_byte 686 (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) { 687 dbg(DBG_ASS, 688 "Error in reading interrupt line register\n"); 689 } 690 /* 691 * Assert PLX software reset and Am186 hardware reset 692 * and then deassert the PLX software reset but 186 still in reset 693 */ 694 outw(0x440f, card->pci_conf + CNTRL_9054 + 2); 695 outw(0x040f, card->pci_conf + CNTRL_9054 + 2); 696 /* 697 * We are delaying here to allow the 9054 to reset itself 698 */ 699 j = jiffies + 1; 700 while (jiffies < j) 701 /* Do nothing */ ; 702 outw(0x240f, card->pci_conf + CNTRL_9054 + 2); 703 /* 704 * We are delaying here to allow the 9054 to reload its eeprom 705 */ 706 j = jiffies + 1; 707 while (jiffies < j) 708 /* Do nothing */ ; 709 outw(0x040f, card->pci_conf + CNTRL_9054 + 2); 710 711 if (pci_write_config_byte 712 (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) { 713 dbg(DBG_ASS, 714 "Error in writing interrupt line register\n"); 715 } 716 717 } else { 718 regval = inl(card->pci_conf + CNTRL_9052); 719 720 outl(regval | 0x40000000, card->pci_conf + CNTRL_9052); 721 outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052); 722 } 723 } 724 725 /* Release the processor from reset 726 */ 727 static inline void 728 fst_cpurelease(struct fst_card_info *card) 729 { 730 if (card->family == FST_FAMILY_TXU) { 731 /* 732 * Force posted writes to complete 733 */ 734 (void) readb(card->mem); 735 736 /* 737 * Release LRESET DO = 1 738 * Then release Local Hold, DO = 1 739 */ 740 outw(0x040e, card->pci_conf + CNTRL_9054 + 2); 741 outw(0x040f, card->pci_conf + CNTRL_9054 + 2); 742 } else { 743 (void) readb(card->ctlmem); 744 } 745 } 746 747 /* Clear the cards interrupt flag 748 */ 749 static inline void 750 fst_clear_intr(struct fst_card_info *card) 751 { 752 if (card->family == FST_FAMILY_TXU) { 753 (void) readb(card->ctlmem); 754 } else { 755 /* Poke the appropriate PLX chip register (same as enabling interrupts) 756 */ 757 outw(0x0543, card->pci_conf + INTCSR_9052); 758 } 759 } 760 761 /* Enable card interrupts 762 */ 763 static inline void 764 fst_enable_intr(struct fst_card_info *card) 765 { 766 if (card->family == FST_FAMILY_TXU) { 767 outl(0x0f0c0900, card->pci_conf + INTCSR_9054); 768 } else { 769 outw(0x0543, card->pci_conf + INTCSR_9052); 770 } 771 } 772 773 /* Disable card interrupts 774 */ 775 static inline void 776 fst_disable_intr(struct fst_card_info *card) 777 { 778 if (card->family == FST_FAMILY_TXU) { 779 outl(0x00000000, card->pci_conf + INTCSR_9054); 780 } else { 781 outw(0x0000, card->pci_conf + INTCSR_9052); 782 } 783 } 784 785 /* Process the result of trying to pass a received frame up the stack 786 */ 787 static void 788 fst_process_rx_status(int rx_status, char *name) 789 { 790 switch (rx_status) { 791 case NET_RX_SUCCESS: 792 { 793 /* 794 * Nothing to do here 795 */ 796 break; 797 } 798 799 case NET_RX_CN_LOW: 800 { 801 dbg(DBG_ASS, "%s: Receive Low Congestion\n", name); 802 break; 803 } 804 805 case NET_RX_CN_MOD: 806 { 807 dbg(DBG_ASS, "%s: Receive Moderate Congestion\n", name); 808 break; 809 } 810 811 case NET_RX_CN_HIGH: 812 { 813 dbg(DBG_ASS, "%s: Receive High Congestion\n", name); 814 break; 815 } 816 817 case NET_RX_DROP: 818 { 819 dbg(DBG_ASS, "%s: Received packet dropped\n", name); 820 break; 821 } 822 } 823 } 824 825 /* Initilaise DMA for PLX 9054 826 */ 827 static inline void 828 fst_init_dma(struct fst_card_info *card) 829 { 830 /* 831 * This is only required for the PLX 9054 832 */ 833 if (card->family == FST_FAMILY_TXU) { 834 pci_set_master(card->device); 835 outl(0x00020441, card->pci_conf + DMAMODE0); 836 outl(0x00020441, card->pci_conf + DMAMODE1); 837 outl(0x0, card->pci_conf + DMATHR); 838 } 839 } 840 841 /* Tx dma complete interrupt 842 */ 843 static void 844 fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port, 845 int len, int txpos) 846 { 847 struct net_device *dev = port_to_dev(port); 848 struct net_device_stats *stats = hdlc_stats(dev); 849 850 /* 851 * Everything is now set, just tell the card to go 852 */ 853 dbg(DBG_TX, "fst_tx_dma_complete\n"); 854 FST_WRB(card, txDescrRing[port->index][txpos].bits, 855 DMA_OWN | TX_STP | TX_ENP); 856 stats->tx_packets++; 857 stats->tx_bytes += len; 858 dev->trans_start = jiffies; 859 } 860 861 /* 862 * Mark it for our own raw sockets interface 863 */ 864 static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev) 865 { 866 skb->dev = dev; 867 skb_reset_mac_header(skb); 868 skb->pkt_type = PACKET_HOST; 869 return htons(ETH_P_CUST); 870 } 871 872 /* Rx dma complete interrupt 873 */ 874 static void 875 fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port, 876 int len, struct sk_buff *skb, int rxp) 877 { 878 struct net_device *dev = port_to_dev(port); 879 struct net_device_stats *stats = hdlc_stats(dev); 880 int pi; 881 int rx_status; 882 883 dbg(DBG_TX, "fst_rx_dma_complete\n"); 884 pi = port->index; 885 memcpy(skb_put(skb, len), card->rx_dma_handle_host, len); 886 887 /* Reset buffer descriptor */ 888 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 889 890 /* Update stats */ 891 stats->rx_packets++; 892 stats->rx_bytes += len; 893 894 /* Push upstream */ 895 dbg(DBG_RX, "Pushing the frame up the stack\n"); 896 if (port->mode == FST_RAW) 897 skb->protocol = farsync_type_trans(skb, dev); 898 else 899 skb->protocol = hdlc_type_trans(skb, dev); 900 rx_status = netif_rx(skb); 901 fst_process_rx_status(rx_status, port_to_dev(port)->name); 902 if (rx_status == NET_RX_DROP) 903 stats->rx_dropped++; 904 dev->last_rx = jiffies; 905 } 906 907 /* 908 * Receive a frame through the DMA 909 */ 910 static inline void 911 fst_rx_dma(struct fst_card_info *card, unsigned char *skb, 912 unsigned char *mem, int len) 913 { 914 /* 915 * This routine will setup the DMA and start it 916 */ 917 918 dbg(DBG_RX, "In fst_rx_dma %p %p %d\n", skb, mem, len); 919 if (card->dmarx_in_progress) { 920 dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n"); 921 } 922 923 outl((unsigned long) skb, card->pci_conf + DMAPADR0); /* Copy to here */ 924 outl((unsigned long) mem, card->pci_conf + DMALADR0); /* from here */ 925 outl(len, card->pci_conf + DMASIZ0); /* for this length */ 926 outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */ 927 928 /* 929 * We use the dmarx_in_progress flag to flag the channel as busy 930 */ 931 card->dmarx_in_progress = 1; 932 outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */ 933 } 934 935 /* 936 * Send a frame through the DMA 937 */ 938 static inline void 939 fst_tx_dma(struct fst_card_info *card, unsigned char *skb, 940 unsigned char *mem, int len) 941 { 942 /* 943 * This routine will setup the DMA and start it. 944 */ 945 946 dbg(DBG_TX, "In fst_tx_dma %p %p %d\n", skb, mem, len); 947 if (card->dmatx_in_progress) { 948 dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n"); 949 } 950 951 outl((unsigned long) skb, card->pci_conf + DMAPADR1); /* Copy from here */ 952 outl((unsigned long) mem, card->pci_conf + DMALADR1); /* to here */ 953 outl(len, card->pci_conf + DMASIZ1); /* for this length */ 954 outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */ 955 956 /* 957 * We use the dmatx_in_progress to flag the channel as busy 958 */ 959 card->dmatx_in_progress = 1; 960 outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */ 961 } 962 963 /* Issue a Mailbox command for a port. 964 * Note we issue them on a fire and forget basis, not expecting to see an 965 * error and not waiting for completion. 966 */ 967 static void 968 fst_issue_cmd(struct fst_port_info *port, unsigned short cmd) 969 { 970 struct fst_card_info *card; 971 unsigned short mbval; 972 unsigned long flags; 973 int safety; 974 975 card = port->card; 976 spin_lock_irqsave(&card->card_lock, flags); 977 mbval = FST_RDW(card, portMailbox[port->index][0]); 978 979 safety = 0; 980 /* Wait for any previous command to complete */ 981 while (mbval > NAK) { 982 spin_unlock_irqrestore(&card->card_lock, flags); 983 schedule_timeout_uninterruptible(1); 984 spin_lock_irqsave(&card->card_lock, flags); 985 986 if (++safety > 2000) { 987 printk_err("Mailbox safety timeout\n"); 988 break; 989 } 990 991 mbval = FST_RDW(card, portMailbox[port->index][0]); 992 } 993 if (safety > 0) { 994 dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety); 995 } 996 if (mbval == NAK) { 997 dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n"); 998 } 999 1000 FST_WRW(card, portMailbox[port->index][0], cmd); 1001 1002 if (cmd == ABORTTX || cmd == STARTPORT) { 1003 port->txpos = 0; 1004 port->txipos = 0; 1005 port->start = 0; 1006 } 1007 1008 spin_unlock_irqrestore(&card->card_lock, flags); 1009 } 1010 1011 /* Port output signals control 1012 */ 1013 static inline void 1014 fst_op_raise(struct fst_port_info *port, unsigned int outputs) 1015 { 1016 outputs |= FST_RDL(port->card, v24OpSts[port->index]); 1017 FST_WRL(port->card, v24OpSts[port->index], outputs); 1018 1019 if (port->run) 1020 fst_issue_cmd(port, SETV24O); 1021 } 1022 1023 static inline void 1024 fst_op_lower(struct fst_port_info *port, unsigned int outputs) 1025 { 1026 outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]); 1027 FST_WRL(port->card, v24OpSts[port->index], outputs); 1028 1029 if (port->run) 1030 fst_issue_cmd(port, SETV24O); 1031 } 1032 1033 /* 1034 * Setup port Rx buffers 1035 */ 1036 static void 1037 fst_rx_config(struct fst_port_info *port) 1038 { 1039 int i; 1040 int pi; 1041 unsigned int offset; 1042 unsigned long flags; 1043 struct fst_card_info *card; 1044 1045 pi = port->index; 1046 card = port->card; 1047 spin_lock_irqsave(&card->card_lock, flags); 1048 for (i = 0; i < NUM_RX_BUFFER; i++) { 1049 offset = BUF_OFFSET(rxBuffer[pi][i][0]); 1050 1051 FST_WRW(card, rxDescrRing[pi][i].ladr, (u16) offset); 1052 FST_WRB(card, rxDescrRing[pi][i].hadr, (u8) (offset >> 16)); 1053 FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER)); 1054 FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER); 1055 FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN); 1056 } 1057 port->rxpos = 0; 1058 spin_unlock_irqrestore(&card->card_lock, flags); 1059 } 1060 1061 /* 1062 * Setup port Tx buffers 1063 */ 1064 static void 1065 fst_tx_config(struct fst_port_info *port) 1066 { 1067 int i; 1068 int pi; 1069 unsigned int offset; 1070 unsigned long flags; 1071 struct fst_card_info *card; 1072 1073 pi = port->index; 1074 card = port->card; 1075 spin_lock_irqsave(&card->card_lock, flags); 1076 for (i = 0; i < NUM_TX_BUFFER; i++) { 1077 offset = BUF_OFFSET(txBuffer[pi][i][0]); 1078 1079 FST_WRW(card, txDescrRing[pi][i].ladr, (u16) offset); 1080 FST_WRB(card, txDescrRing[pi][i].hadr, (u8) (offset >> 16)); 1081 FST_WRW(card, txDescrRing[pi][i].bcnt, 0); 1082 FST_WRB(card, txDescrRing[pi][i].bits, 0); 1083 } 1084 port->txpos = 0; 1085 port->txipos = 0; 1086 port->start = 0; 1087 spin_unlock_irqrestore(&card->card_lock, flags); 1088 } 1089 1090 /* TE1 Alarm change interrupt event 1091 */ 1092 static void 1093 fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port) 1094 { 1095 u8 los; 1096 u8 rra; 1097 u8 ais; 1098 1099 los = FST_RDB(card, suStatus.lossOfSignal); 1100 rra = FST_RDB(card, suStatus.receiveRemoteAlarm); 1101 ais = FST_RDB(card, suStatus.alarmIndicationSignal); 1102 1103 if (los) { 1104 /* 1105 * Lost the link 1106 */ 1107 if (netif_carrier_ok(port_to_dev(port))) { 1108 dbg(DBG_INTR, "Net carrier off\n"); 1109 netif_carrier_off(port_to_dev(port)); 1110 } 1111 } else { 1112 /* 1113 * Link available 1114 */ 1115 if (!netif_carrier_ok(port_to_dev(port))) { 1116 dbg(DBG_INTR, "Net carrier on\n"); 1117 netif_carrier_on(port_to_dev(port)); 1118 } 1119 } 1120 1121 if (los) 1122 dbg(DBG_INTR, "Assert LOS Alarm\n"); 1123 else 1124 dbg(DBG_INTR, "De-assert LOS Alarm\n"); 1125 if (rra) 1126 dbg(DBG_INTR, "Assert RRA Alarm\n"); 1127 else 1128 dbg(DBG_INTR, "De-assert RRA Alarm\n"); 1129 1130 if (ais) 1131 dbg(DBG_INTR, "Assert AIS Alarm\n"); 1132 else 1133 dbg(DBG_INTR, "De-assert AIS Alarm\n"); 1134 } 1135 1136 /* Control signal change interrupt event 1137 */ 1138 static void 1139 fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port) 1140 { 1141 int signals; 1142 1143 signals = FST_RDL(card, v24DebouncedSts[port->index]); 1144 1145 if (signals & (((port->hwif == X21) || (port->hwif == X21D)) 1146 ? IPSTS_INDICATE : IPSTS_DCD)) { 1147 if (!netif_carrier_ok(port_to_dev(port))) { 1148 dbg(DBG_INTR, "DCD active\n"); 1149 netif_carrier_on(port_to_dev(port)); 1150 } 1151 } else { 1152 if (netif_carrier_ok(port_to_dev(port))) { 1153 dbg(DBG_INTR, "DCD lost\n"); 1154 netif_carrier_off(port_to_dev(port)); 1155 } 1156 } 1157 } 1158 1159 /* Log Rx Errors 1160 */ 1161 static void 1162 fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port, 1163 unsigned char dmabits, int rxp, unsigned short len) 1164 { 1165 struct net_device *dev = port_to_dev(port); 1166 struct net_device_stats *stats = hdlc_stats(dev); 1167 1168 /* 1169 * Increment the appropriate error counter 1170 */ 1171 stats->rx_errors++; 1172 if (dmabits & RX_OFLO) { 1173 stats->rx_fifo_errors++; 1174 dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n", 1175 card->card_no, port->index, rxp); 1176 } 1177 if (dmabits & RX_CRC) { 1178 stats->rx_crc_errors++; 1179 dbg(DBG_ASS, "Rx crc error on card %d port %d\n", 1180 card->card_no, port->index); 1181 } 1182 if (dmabits & RX_FRAM) { 1183 stats->rx_frame_errors++; 1184 dbg(DBG_ASS, "Rx frame error on card %d port %d\n", 1185 card->card_no, port->index); 1186 } 1187 if (dmabits == (RX_STP | RX_ENP)) { 1188 stats->rx_length_errors++; 1189 dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n", 1190 len, card->card_no, port->index); 1191 } 1192 } 1193 1194 /* Rx Error Recovery 1195 */ 1196 static void 1197 fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port, 1198 unsigned char dmabits, int rxp, unsigned short len) 1199 { 1200 int i; 1201 int pi; 1202 1203 pi = port->index; 1204 /* 1205 * Discard buffer descriptors until we see the start of the 1206 * next frame. Note that for long frames this could be in 1207 * a subsequent interrupt. 1208 */ 1209 i = 0; 1210 while ((dmabits & (DMA_OWN | RX_STP)) == 0) { 1211 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1212 rxp = (rxp+1) % NUM_RX_BUFFER; 1213 if (++i > NUM_RX_BUFFER) { 1214 dbg(DBG_ASS, "intr_rx: Discarding more bufs" 1215 " than we have\n"); 1216 break; 1217 } 1218 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits); 1219 dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits); 1220 } 1221 dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i); 1222 1223 /* Discard the terminal buffer */ 1224 if (!(dmabits & DMA_OWN)) { 1225 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1226 rxp = (rxp+1) % NUM_RX_BUFFER; 1227 } 1228 port->rxpos = rxp; 1229 return; 1230 1231 } 1232 1233 /* Rx complete interrupt 1234 */ 1235 static void 1236 fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port) 1237 { 1238 unsigned char dmabits; 1239 int pi; 1240 int rxp; 1241 int rx_status; 1242 unsigned short len; 1243 struct sk_buff *skb; 1244 struct net_device *dev = port_to_dev(port); 1245 struct net_device_stats *stats = hdlc_stats(dev); 1246 1247 /* Check we have a buffer to process */ 1248 pi = port->index; 1249 rxp = port->rxpos; 1250 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits); 1251 if (dmabits & DMA_OWN) { 1252 dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n", 1253 pi, rxp); 1254 return; 1255 } 1256 if (card->dmarx_in_progress) { 1257 return; 1258 } 1259 1260 /* Get buffer length */ 1261 len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt); 1262 /* Discard the CRC */ 1263 len -= 2; 1264 if (len == 0) { 1265 /* 1266 * This seems to happen on the TE1 interface sometimes 1267 * so throw the frame away and log the event. 1268 */ 1269 printk_err("Frame received with 0 length. Card %d Port %d\n", 1270 card->card_no, port->index); 1271 /* Return descriptor to card */ 1272 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1273 1274 rxp = (rxp+1) % NUM_RX_BUFFER; 1275 port->rxpos = rxp; 1276 return; 1277 } 1278 1279 /* Check buffer length and for other errors. We insist on one packet 1280 * in one buffer. This simplifies things greatly and since we've 1281 * allocated 8K it shouldn't be a real world limitation 1282 */ 1283 dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len); 1284 if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) { 1285 fst_log_rx_error(card, port, dmabits, rxp, len); 1286 fst_recover_rx_error(card, port, dmabits, rxp, len); 1287 return; 1288 } 1289 1290 /* Allocate SKB */ 1291 if ((skb = dev_alloc_skb(len)) == NULL) { 1292 dbg(DBG_RX, "intr_rx: can't allocate buffer\n"); 1293 1294 stats->rx_dropped++; 1295 1296 /* Return descriptor to card */ 1297 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1298 1299 rxp = (rxp+1) % NUM_RX_BUFFER; 1300 port->rxpos = rxp; 1301 return; 1302 } 1303 1304 /* 1305 * We know the length we need to receive, len. 1306 * It's not worth using the DMA for reads of less than 1307 * FST_MIN_DMA_LEN 1308 */ 1309 1310 if ((len < FST_MIN_DMA_LEN) || (card->family == FST_FAMILY_TXP)) { 1311 memcpy_fromio(skb_put(skb, len), 1312 card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]), 1313 len); 1314 1315 /* Reset buffer descriptor */ 1316 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1317 1318 /* Update stats */ 1319 stats->rx_packets++; 1320 stats->rx_bytes += len; 1321 1322 /* Push upstream */ 1323 dbg(DBG_RX, "Pushing frame up the stack\n"); 1324 if (port->mode == FST_RAW) 1325 skb->protocol = farsync_type_trans(skb, dev); 1326 else 1327 skb->protocol = hdlc_type_trans(skb, dev); 1328 rx_status = netif_rx(skb); 1329 fst_process_rx_status(rx_status, port_to_dev(port)->name); 1330 if (rx_status == NET_RX_DROP) { 1331 stats->rx_dropped++; 1332 } 1333 dev->last_rx = jiffies; 1334 } else { 1335 card->dma_skb_rx = skb; 1336 card->dma_port_rx = port; 1337 card->dma_len_rx = len; 1338 card->dma_rxpos = rxp; 1339 fst_rx_dma(card, (char *) card->rx_dma_handle_card, 1340 (char *) BUF_OFFSET(rxBuffer[pi][rxp][0]), len); 1341 } 1342 if (rxp != port->rxpos) { 1343 dbg(DBG_ASS, "About to increment rxpos by more than 1\n"); 1344 dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos); 1345 } 1346 rxp = (rxp+1) % NUM_RX_BUFFER; 1347 port->rxpos = rxp; 1348 } 1349 1350 /* 1351 * The bottom halfs to the ISR 1352 * 1353 */ 1354 1355 static void 1356 do_bottom_half_tx(struct fst_card_info *card) 1357 { 1358 struct fst_port_info *port; 1359 int pi; 1360 int txq_length; 1361 struct sk_buff *skb; 1362 unsigned long flags; 1363 struct net_device *dev; 1364 struct net_device_stats *stats; 1365 1366 /* 1367 * Find a free buffer for the transmit 1368 * Step through each port on this card 1369 */ 1370 1371 dbg(DBG_TX, "do_bottom_half_tx\n"); 1372 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) { 1373 if (!port->run) 1374 continue; 1375 1376 dev = port_to_dev(port); 1377 stats = hdlc_stats(dev); 1378 while (! 1379 (FST_RDB(card, txDescrRing[pi][port->txpos].bits) & 1380 DMA_OWN) 1381 && !(card->dmatx_in_progress)) { 1382 /* 1383 * There doesn't seem to be a txdone event per-se 1384 * We seem to have to deduce it, by checking the DMA_OWN 1385 * bit on the next buffer we think we can use 1386 */ 1387 spin_lock_irqsave(&card->card_lock, flags); 1388 if ((txq_length = port->txqe - port->txqs) < 0) { 1389 /* 1390 * This is the case where one has wrapped and the 1391 * maths gives us a negative number 1392 */ 1393 txq_length = txq_length + FST_TXQ_DEPTH; 1394 } 1395 spin_unlock_irqrestore(&card->card_lock, flags); 1396 if (txq_length > 0) { 1397 /* 1398 * There is something to send 1399 */ 1400 spin_lock_irqsave(&card->card_lock, flags); 1401 skb = port->txq[port->txqs]; 1402 port->txqs++; 1403 if (port->txqs == FST_TXQ_DEPTH) { 1404 port->txqs = 0; 1405 } 1406 spin_unlock_irqrestore(&card->card_lock, flags); 1407 /* 1408 * copy the data and set the required indicators on the 1409 * card. 1410 */ 1411 FST_WRW(card, txDescrRing[pi][port->txpos].bcnt, 1412 cnv_bcnt(skb->len)); 1413 if ((skb->len < FST_MIN_DMA_LEN) 1414 || (card->family == FST_FAMILY_TXP)) { 1415 /* Enqueue the packet with normal io */ 1416 memcpy_toio(card->mem + 1417 BUF_OFFSET(txBuffer[pi] 1418 [port-> 1419 txpos][0]), 1420 skb->data, skb->len); 1421 FST_WRB(card, 1422 txDescrRing[pi][port->txpos]. 1423 bits, 1424 DMA_OWN | TX_STP | TX_ENP); 1425 stats->tx_packets++; 1426 stats->tx_bytes += skb->len; 1427 dev->trans_start = jiffies; 1428 } else { 1429 /* Or do it through dma */ 1430 memcpy(card->tx_dma_handle_host, 1431 skb->data, skb->len); 1432 card->dma_port_tx = port; 1433 card->dma_len_tx = skb->len; 1434 card->dma_txpos = port->txpos; 1435 fst_tx_dma(card, 1436 (char *) card-> 1437 tx_dma_handle_card, 1438 (char *) 1439 BUF_OFFSET(txBuffer[pi] 1440 [port->txpos][0]), 1441 skb->len); 1442 } 1443 if (++port->txpos >= NUM_TX_BUFFER) 1444 port->txpos = 0; 1445 /* 1446 * If we have flow control on, can we now release it? 1447 */ 1448 if (port->start) { 1449 if (txq_length < fst_txq_low) { 1450 netif_wake_queue(port_to_dev 1451 (port)); 1452 port->start = 0; 1453 } 1454 } 1455 dev_kfree_skb(skb); 1456 } else { 1457 /* 1458 * Nothing to send so break out of the while loop 1459 */ 1460 break; 1461 } 1462 } 1463 } 1464 } 1465 1466 static void 1467 do_bottom_half_rx(struct fst_card_info *card) 1468 { 1469 struct fst_port_info *port; 1470 int pi; 1471 int rx_count = 0; 1472 1473 /* Check for rx completions on all ports on this card */ 1474 dbg(DBG_RX, "do_bottom_half_rx\n"); 1475 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) { 1476 if (!port->run) 1477 continue; 1478 1479 while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits) 1480 & DMA_OWN) && !(card->dmarx_in_progress)) { 1481 if (rx_count > fst_max_reads) { 1482 /* 1483 * Don't spend forever in receive processing 1484 * Schedule another event 1485 */ 1486 fst_q_work_item(&fst_work_intq, card->card_no); 1487 tasklet_schedule(&fst_int_task); 1488 break; /* Leave the loop */ 1489 } 1490 fst_intr_rx(card, port); 1491 rx_count++; 1492 } 1493 } 1494 } 1495 1496 /* 1497 * The interrupt service routine 1498 * Dev_id is our fst_card_info pointer 1499 */ 1500 static irqreturn_t 1501 fst_intr(int dummy, void *dev_id) 1502 { 1503 struct fst_card_info *card = dev_id; 1504 struct fst_port_info *port; 1505 int rdidx; /* Event buffer indices */ 1506 int wridx; 1507 int event; /* Actual event for processing */ 1508 unsigned int dma_intcsr = 0; 1509 unsigned int do_card_interrupt; 1510 unsigned int int_retry_count; 1511 1512 /* 1513 * Check to see if the interrupt was for this card 1514 * return if not 1515 * Note that the call to clear the interrupt is important 1516 */ 1517 dbg(DBG_INTR, "intr: %d %p\n", card->irq, card); 1518 if (card->state != FST_RUNNING) { 1519 printk_err 1520 ("Interrupt received for card %d in a non running state (%d)\n", 1521 card->card_no, card->state); 1522 1523 /* 1524 * It is possible to really be running, i.e. we have re-loaded 1525 * a running card 1526 * Clear and reprime the interrupt source 1527 */ 1528 fst_clear_intr(card); 1529 return IRQ_HANDLED; 1530 } 1531 1532 /* Clear and reprime the interrupt source */ 1533 fst_clear_intr(card); 1534 1535 /* 1536 * Is the interrupt for this card (handshake == 1) 1537 */ 1538 do_card_interrupt = 0; 1539 if (FST_RDB(card, interruptHandshake) == 1) { 1540 do_card_interrupt += FST_CARD_INT; 1541 /* Set the software acknowledge */ 1542 FST_WRB(card, interruptHandshake, 0xEE); 1543 } 1544 if (card->family == FST_FAMILY_TXU) { 1545 /* 1546 * Is it a DMA Interrupt 1547 */ 1548 dma_intcsr = inl(card->pci_conf + INTCSR_9054); 1549 if (dma_intcsr & 0x00200000) { 1550 /* 1551 * DMA Channel 0 (Rx transfer complete) 1552 */ 1553 dbg(DBG_RX, "DMA Rx xfer complete\n"); 1554 outb(0x8, card->pci_conf + DMACSR0); 1555 fst_rx_dma_complete(card, card->dma_port_rx, 1556 card->dma_len_rx, card->dma_skb_rx, 1557 card->dma_rxpos); 1558 card->dmarx_in_progress = 0; 1559 do_card_interrupt += FST_RX_DMA_INT; 1560 } 1561 if (dma_intcsr & 0x00400000) { 1562 /* 1563 * DMA Channel 1 (Tx transfer complete) 1564 */ 1565 dbg(DBG_TX, "DMA Tx xfer complete\n"); 1566 outb(0x8, card->pci_conf + DMACSR1); 1567 fst_tx_dma_complete(card, card->dma_port_tx, 1568 card->dma_len_tx, card->dma_txpos); 1569 card->dmatx_in_progress = 0; 1570 do_card_interrupt += FST_TX_DMA_INT; 1571 } 1572 } 1573 1574 /* 1575 * Have we been missing Interrupts 1576 */ 1577 int_retry_count = FST_RDL(card, interruptRetryCount); 1578 if (int_retry_count) { 1579 dbg(DBG_ASS, "Card %d int_retry_count is %d\n", 1580 card->card_no, int_retry_count); 1581 FST_WRL(card, interruptRetryCount, 0); 1582 } 1583 1584 if (!do_card_interrupt) { 1585 return IRQ_HANDLED; 1586 } 1587 1588 /* Scehdule the bottom half of the ISR */ 1589 fst_q_work_item(&fst_work_intq, card->card_no); 1590 tasklet_schedule(&fst_int_task); 1591 1592 /* Drain the event queue */ 1593 rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f; 1594 wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f; 1595 while (rdidx != wridx) { 1596 event = FST_RDB(card, interruptEvent.evntbuff[rdidx]); 1597 port = &card->ports[event & 0x03]; 1598 1599 dbg(DBG_INTR, "Processing Interrupt event: %x\n", event); 1600 1601 switch (event) { 1602 case TE1_ALMA: 1603 dbg(DBG_INTR, "TE1 Alarm intr\n"); 1604 if (port->run) 1605 fst_intr_te1_alarm(card, port); 1606 break; 1607 1608 case CTLA_CHG: 1609 case CTLB_CHG: 1610 case CTLC_CHG: 1611 case CTLD_CHG: 1612 if (port->run) 1613 fst_intr_ctlchg(card, port); 1614 break; 1615 1616 case ABTA_SENT: 1617 case ABTB_SENT: 1618 case ABTC_SENT: 1619 case ABTD_SENT: 1620 dbg(DBG_TX, "Abort complete port %d\n", port->index); 1621 break; 1622 1623 case TXA_UNDF: 1624 case TXB_UNDF: 1625 case TXC_UNDF: 1626 case TXD_UNDF: 1627 /* Difficult to see how we'd get this given that we 1628 * always load up the entire packet for DMA. 1629 */ 1630 dbg(DBG_TX, "Tx underflow port %d\n", port->index); 1631 hdlc_stats(port_to_dev(port))->tx_errors++; 1632 hdlc_stats(port_to_dev(port))->tx_fifo_errors++; 1633 dbg(DBG_ASS, "Tx underflow on card %d port %d\n", 1634 card->card_no, port->index); 1635 break; 1636 1637 case INIT_CPLT: 1638 dbg(DBG_INIT, "Card init OK intr\n"); 1639 break; 1640 1641 case INIT_FAIL: 1642 dbg(DBG_INIT, "Card init FAILED intr\n"); 1643 card->state = FST_IFAILED; 1644 break; 1645 1646 default: 1647 printk_err("intr: unknown card event %d. ignored\n", 1648 event); 1649 break; 1650 } 1651 1652 /* Bump and wrap the index */ 1653 if (++rdidx >= MAX_CIRBUFF) 1654 rdidx = 0; 1655 } 1656 FST_WRB(card, interruptEvent.rdindex, rdidx); 1657 return IRQ_HANDLED; 1658 } 1659 1660 /* Check that the shared memory configuration is one that we can handle 1661 * and that some basic parameters are correct 1662 */ 1663 static void 1664 check_started_ok(struct fst_card_info *card) 1665 { 1666 int i; 1667 1668 /* Check structure version and end marker */ 1669 if (FST_RDW(card, smcVersion) != SMC_VERSION) { 1670 printk_err("Bad shared memory version %d expected %d\n", 1671 FST_RDW(card, smcVersion), SMC_VERSION); 1672 card->state = FST_BADVERSION; 1673 return; 1674 } 1675 if (FST_RDL(card, endOfSmcSignature) != END_SIG) { 1676 printk_err("Missing shared memory signature\n"); 1677 card->state = FST_BADVERSION; 1678 return; 1679 } 1680 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */ 1681 if ((i = FST_RDB(card, taskStatus)) == 0x01) { 1682 card->state = FST_RUNNING; 1683 } else if (i == 0xFF) { 1684 printk_err("Firmware initialisation failed. Card halted\n"); 1685 card->state = FST_HALTED; 1686 return; 1687 } else if (i != 0x00) { 1688 printk_err("Unknown firmware status 0x%x\n", i); 1689 card->state = FST_HALTED; 1690 return; 1691 } 1692 1693 /* Finally check the number of ports reported by firmware against the 1694 * number we assumed at card detection. Should never happen with 1695 * existing firmware etc so we just report it for the moment. 1696 */ 1697 if (FST_RDL(card, numberOfPorts) != card->nports) { 1698 printk_warn("Port count mismatch on card %d." 1699 " Firmware thinks %d we say %d\n", card->card_no, 1700 FST_RDL(card, numberOfPorts), card->nports); 1701 } 1702 } 1703 1704 static int 1705 set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port, 1706 struct fstioc_info *info) 1707 { 1708 int err; 1709 unsigned char my_framing; 1710 1711 /* Set things according to the user set valid flags 1712 * Several of the old options have been invalidated/replaced by the 1713 * generic hdlc package. 1714 */ 1715 err = 0; 1716 if (info->valid & FSTVAL_PROTO) { 1717 if (info->proto == FST_RAW) 1718 port->mode = FST_RAW; 1719 else 1720 port->mode = FST_GEN_HDLC; 1721 } 1722 1723 if (info->valid & FSTVAL_CABLE) 1724 err = -EINVAL; 1725 1726 if (info->valid & FSTVAL_SPEED) 1727 err = -EINVAL; 1728 1729 if (info->valid & FSTVAL_PHASE) 1730 FST_WRB(card, portConfig[port->index].invertClock, 1731 info->invertClock); 1732 if (info->valid & FSTVAL_MODE) 1733 FST_WRW(card, cardMode, info->cardMode); 1734 if (info->valid & FSTVAL_TE1) { 1735 FST_WRL(card, suConfig.dataRate, info->lineSpeed); 1736 FST_WRB(card, suConfig.clocking, info->clockSource); 1737 my_framing = FRAMING_E1; 1738 if (info->framing == E1) 1739 my_framing = FRAMING_E1; 1740 if (info->framing == T1) 1741 my_framing = FRAMING_T1; 1742 if (info->framing == J1) 1743 my_framing = FRAMING_J1; 1744 FST_WRB(card, suConfig.framing, my_framing); 1745 FST_WRB(card, suConfig.structure, info->structure); 1746 FST_WRB(card, suConfig.interface, info->interface); 1747 FST_WRB(card, suConfig.coding, info->coding); 1748 FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut); 1749 FST_WRB(card, suConfig.equalizer, info->equalizer); 1750 FST_WRB(card, suConfig.transparentMode, info->transparentMode); 1751 FST_WRB(card, suConfig.loopMode, info->loopMode); 1752 FST_WRB(card, suConfig.range, info->range); 1753 FST_WRB(card, suConfig.txBufferMode, info->txBufferMode); 1754 FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode); 1755 FST_WRB(card, suConfig.startingSlot, info->startingSlot); 1756 FST_WRB(card, suConfig.losThreshold, info->losThreshold); 1757 if (info->idleCode) 1758 FST_WRB(card, suConfig.enableIdleCode, 1); 1759 else 1760 FST_WRB(card, suConfig.enableIdleCode, 0); 1761 FST_WRB(card, suConfig.idleCode, info->idleCode); 1762 #if FST_DEBUG 1763 if (info->valid & FSTVAL_TE1) { 1764 printk("Setting TE1 data\n"); 1765 printk("Line Speed = %d\n", info->lineSpeed); 1766 printk("Start slot = %d\n", info->startingSlot); 1767 printk("Clock source = %d\n", info->clockSource); 1768 printk("Framing = %d\n", my_framing); 1769 printk("Structure = %d\n", info->structure); 1770 printk("interface = %d\n", info->interface); 1771 printk("Coding = %d\n", info->coding); 1772 printk("Line build out = %d\n", info->lineBuildOut); 1773 printk("Equaliser = %d\n", info->equalizer); 1774 printk("Transparent mode = %d\n", 1775 info->transparentMode); 1776 printk("Loop mode = %d\n", info->loopMode); 1777 printk("Range = %d\n", info->range); 1778 printk("Tx Buffer mode = %d\n", info->txBufferMode); 1779 printk("Rx Buffer mode = %d\n", info->rxBufferMode); 1780 printk("LOS Threshold = %d\n", info->losThreshold); 1781 printk("Idle Code = %d\n", info->idleCode); 1782 } 1783 #endif 1784 } 1785 #if FST_DEBUG 1786 if (info->valid & FSTVAL_DEBUG) { 1787 fst_debug_mask = info->debug; 1788 } 1789 #endif 1790 1791 return err; 1792 } 1793 1794 static void 1795 gather_conf_info(struct fst_card_info *card, struct fst_port_info *port, 1796 struct fstioc_info *info) 1797 { 1798 int i; 1799 1800 memset(info, 0, sizeof (struct fstioc_info)); 1801 1802 i = port->index; 1803 info->kernelVersion = LINUX_VERSION_CODE; 1804 info->nports = card->nports; 1805 info->type = card->type; 1806 info->state = card->state; 1807 info->proto = FST_GEN_HDLC; 1808 info->index = i; 1809 #if FST_DEBUG 1810 info->debug = fst_debug_mask; 1811 #endif 1812 1813 /* Only mark information as valid if card is running. 1814 * Copy the data anyway in case it is useful for diagnostics 1815 */ 1816 info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD) 1817 #if FST_DEBUG 1818 | FSTVAL_DEBUG 1819 #endif 1820 ; 1821 1822 info->lineInterface = FST_RDW(card, portConfig[i].lineInterface); 1823 info->internalClock = FST_RDB(card, portConfig[i].internalClock); 1824 info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed); 1825 info->invertClock = FST_RDB(card, portConfig[i].invertClock); 1826 info->v24IpSts = FST_RDL(card, v24IpSts[i]); 1827 info->v24OpSts = FST_RDL(card, v24OpSts[i]); 1828 info->clockStatus = FST_RDW(card, clockStatus[i]); 1829 info->cableStatus = FST_RDW(card, cableStatus); 1830 info->cardMode = FST_RDW(card, cardMode); 1831 info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion); 1832 1833 /* 1834 * The T2U can report cable presence for both A or B 1835 * in bits 0 and 1 of cableStatus. See which port we are and 1836 * do the mapping. 1837 */ 1838 if (card->family == FST_FAMILY_TXU) { 1839 if (port->index == 0) { 1840 /* 1841 * Port A 1842 */ 1843 info->cableStatus = info->cableStatus & 1; 1844 } else { 1845 /* 1846 * Port B 1847 */ 1848 info->cableStatus = info->cableStatus >> 1; 1849 info->cableStatus = info->cableStatus & 1; 1850 } 1851 } 1852 /* 1853 * Some additional bits if we are TE1 1854 */ 1855 if (card->type == FST_TYPE_TE1) { 1856 info->lineSpeed = FST_RDL(card, suConfig.dataRate); 1857 info->clockSource = FST_RDB(card, suConfig.clocking); 1858 info->framing = FST_RDB(card, suConfig.framing); 1859 info->structure = FST_RDB(card, suConfig.structure); 1860 info->interface = FST_RDB(card, suConfig.interface); 1861 info->coding = FST_RDB(card, suConfig.coding); 1862 info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut); 1863 info->equalizer = FST_RDB(card, suConfig.equalizer); 1864 info->loopMode = FST_RDB(card, suConfig.loopMode); 1865 info->range = FST_RDB(card, suConfig.range); 1866 info->txBufferMode = FST_RDB(card, suConfig.txBufferMode); 1867 info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode); 1868 info->startingSlot = FST_RDB(card, suConfig.startingSlot); 1869 info->losThreshold = FST_RDB(card, suConfig.losThreshold); 1870 if (FST_RDB(card, suConfig.enableIdleCode)) 1871 info->idleCode = FST_RDB(card, suConfig.idleCode); 1872 else 1873 info->idleCode = 0; 1874 info->receiveBufferDelay = 1875 FST_RDL(card, suStatus.receiveBufferDelay); 1876 info->framingErrorCount = 1877 FST_RDL(card, suStatus.framingErrorCount); 1878 info->codeViolationCount = 1879 FST_RDL(card, suStatus.codeViolationCount); 1880 info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount); 1881 info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation); 1882 info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal); 1883 info->receiveRemoteAlarm = 1884 FST_RDB(card, suStatus.receiveRemoteAlarm); 1885 info->alarmIndicationSignal = 1886 FST_RDB(card, suStatus.alarmIndicationSignal); 1887 } 1888 } 1889 1890 static int 1891 fst_set_iface(struct fst_card_info *card, struct fst_port_info *port, 1892 struct ifreq *ifr) 1893 { 1894 sync_serial_settings sync; 1895 int i; 1896 1897 if (ifr->ifr_settings.size != sizeof (sync)) { 1898 return -ENOMEM; 1899 } 1900 1901 if (copy_from_user 1902 (&sync, ifr->ifr_settings.ifs_ifsu.sync, sizeof (sync))) { 1903 return -EFAULT; 1904 } 1905 1906 if (sync.loopback) 1907 return -EINVAL; 1908 1909 i = port->index; 1910 1911 switch (ifr->ifr_settings.type) { 1912 case IF_IFACE_V35: 1913 FST_WRW(card, portConfig[i].lineInterface, V35); 1914 port->hwif = V35; 1915 break; 1916 1917 case IF_IFACE_V24: 1918 FST_WRW(card, portConfig[i].lineInterface, V24); 1919 port->hwif = V24; 1920 break; 1921 1922 case IF_IFACE_X21: 1923 FST_WRW(card, portConfig[i].lineInterface, X21); 1924 port->hwif = X21; 1925 break; 1926 1927 case IF_IFACE_X21D: 1928 FST_WRW(card, portConfig[i].lineInterface, X21D); 1929 port->hwif = X21D; 1930 break; 1931 1932 case IF_IFACE_T1: 1933 FST_WRW(card, portConfig[i].lineInterface, T1); 1934 port->hwif = T1; 1935 break; 1936 1937 case IF_IFACE_E1: 1938 FST_WRW(card, portConfig[i].lineInterface, E1); 1939 port->hwif = E1; 1940 break; 1941 1942 case IF_IFACE_SYNC_SERIAL: 1943 break; 1944 1945 default: 1946 return -EINVAL; 1947 } 1948 1949 switch (sync.clock_type) { 1950 case CLOCK_EXT: 1951 FST_WRB(card, portConfig[i].internalClock, EXTCLK); 1952 break; 1953 1954 case CLOCK_INT: 1955 FST_WRB(card, portConfig[i].internalClock, INTCLK); 1956 break; 1957 1958 default: 1959 return -EINVAL; 1960 } 1961 FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate); 1962 return 0; 1963 } 1964 1965 static int 1966 fst_get_iface(struct fst_card_info *card, struct fst_port_info *port, 1967 struct ifreq *ifr) 1968 { 1969 sync_serial_settings sync; 1970 int i; 1971 1972 /* First check what line type is set, we'll default to reporting X.21 1973 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be 1974 * changed 1975 */ 1976 switch (port->hwif) { 1977 case E1: 1978 ifr->ifr_settings.type = IF_IFACE_E1; 1979 break; 1980 case T1: 1981 ifr->ifr_settings.type = IF_IFACE_T1; 1982 break; 1983 case V35: 1984 ifr->ifr_settings.type = IF_IFACE_V35; 1985 break; 1986 case V24: 1987 ifr->ifr_settings.type = IF_IFACE_V24; 1988 break; 1989 case X21D: 1990 ifr->ifr_settings.type = IF_IFACE_X21D; 1991 break; 1992 case X21: 1993 default: 1994 ifr->ifr_settings.type = IF_IFACE_X21; 1995 break; 1996 } 1997 if (ifr->ifr_settings.size == 0) { 1998 return 0; /* only type requested */ 1999 } 2000 if (ifr->ifr_settings.size < sizeof (sync)) { 2001 return -ENOMEM; 2002 } 2003 2004 i = port->index; 2005 sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed); 2006 /* Lucky card and linux use same encoding here */ 2007 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) == 2008 INTCLK ? CLOCK_INT : CLOCK_EXT; 2009 sync.loopback = 0; 2010 2011 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &sync, sizeof (sync))) { 2012 return -EFAULT; 2013 } 2014 2015 ifr->ifr_settings.size = sizeof (sync); 2016 return 0; 2017 } 2018 2019 static int 2020 fst_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2021 { 2022 struct fst_card_info *card; 2023 struct fst_port_info *port; 2024 struct fstioc_write wrthdr; 2025 struct fstioc_info info; 2026 unsigned long flags; 2027 void *buf; 2028 2029 dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, ifr->ifr_data); 2030 2031 port = dev_to_port(dev); 2032 card = port->card; 2033 2034 if (!capable(CAP_NET_ADMIN)) 2035 return -EPERM; 2036 2037 switch (cmd) { 2038 case FSTCPURESET: 2039 fst_cpureset(card); 2040 card->state = FST_RESET; 2041 return 0; 2042 2043 case FSTCPURELEASE: 2044 fst_cpurelease(card); 2045 card->state = FST_STARTING; 2046 return 0; 2047 2048 case FSTWRITE: /* Code write (download) */ 2049 2050 /* First copy in the header with the length and offset of data 2051 * to write 2052 */ 2053 if (ifr->ifr_data == NULL) { 2054 return -EINVAL; 2055 } 2056 if (copy_from_user(&wrthdr, ifr->ifr_data, 2057 sizeof (struct fstioc_write))) { 2058 return -EFAULT; 2059 } 2060 2061 /* Sanity check the parameters. We don't support partial writes 2062 * when going over the top 2063 */ 2064 if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE 2065 || wrthdr.size + wrthdr.offset > FST_MEMSIZE) { 2066 return -ENXIO; 2067 } 2068 2069 /* Now copy the data to the card. */ 2070 2071 buf = kmalloc(wrthdr.size, GFP_KERNEL); 2072 if (!buf) 2073 return -ENOMEM; 2074 2075 if (copy_from_user(buf, 2076 ifr->ifr_data + sizeof (struct fstioc_write), 2077 wrthdr.size)) { 2078 kfree(buf); 2079 return -EFAULT; 2080 } 2081 2082 memcpy_toio(card->mem + wrthdr.offset, buf, wrthdr.size); 2083 kfree(buf); 2084 2085 /* Writes to the memory of a card in the reset state constitute 2086 * a download 2087 */ 2088 if (card->state == FST_RESET) { 2089 card->state = FST_DOWNLOAD; 2090 } 2091 return 0; 2092 2093 case FSTGETCONF: 2094 2095 /* If card has just been started check the shared memory config 2096 * version and marker 2097 */ 2098 if (card->state == FST_STARTING) { 2099 check_started_ok(card); 2100 2101 /* If everything checked out enable card interrupts */ 2102 if (card->state == FST_RUNNING) { 2103 spin_lock_irqsave(&card->card_lock, flags); 2104 fst_enable_intr(card); 2105 FST_WRB(card, interruptHandshake, 0xEE); 2106 spin_unlock_irqrestore(&card->card_lock, flags); 2107 } 2108 } 2109 2110 if (ifr->ifr_data == NULL) { 2111 return -EINVAL; 2112 } 2113 2114 gather_conf_info(card, port, &info); 2115 2116 if (copy_to_user(ifr->ifr_data, &info, sizeof (info))) { 2117 return -EFAULT; 2118 } 2119 return 0; 2120 2121 case FSTSETCONF: 2122 2123 /* 2124 * Most of the settings have been moved to the generic ioctls 2125 * this just covers debug and board ident now 2126 */ 2127 2128 if (card->state != FST_RUNNING) { 2129 printk_err 2130 ("Attempt to configure card %d in non-running state (%d)\n", 2131 card->card_no, card->state); 2132 return -EIO; 2133 } 2134 if (copy_from_user(&info, ifr->ifr_data, sizeof (info))) { 2135 return -EFAULT; 2136 } 2137 2138 return set_conf_from_info(card, port, &info); 2139 2140 case SIOCWANDEV: 2141 switch (ifr->ifr_settings.type) { 2142 case IF_GET_IFACE: 2143 return fst_get_iface(card, port, ifr); 2144 2145 case IF_IFACE_SYNC_SERIAL: 2146 case IF_IFACE_V35: 2147 case IF_IFACE_V24: 2148 case IF_IFACE_X21: 2149 case IF_IFACE_X21D: 2150 case IF_IFACE_T1: 2151 case IF_IFACE_E1: 2152 return fst_set_iface(card, port, ifr); 2153 2154 case IF_PROTO_RAW: 2155 port->mode = FST_RAW; 2156 return 0; 2157 2158 case IF_GET_PROTO: 2159 if (port->mode == FST_RAW) { 2160 ifr->ifr_settings.type = IF_PROTO_RAW; 2161 return 0; 2162 } 2163 return hdlc_ioctl(dev, ifr, cmd); 2164 2165 default: 2166 port->mode = FST_GEN_HDLC; 2167 dbg(DBG_IOCTL, "Passing this type to hdlc %x\n", 2168 ifr->ifr_settings.type); 2169 return hdlc_ioctl(dev, ifr, cmd); 2170 } 2171 2172 default: 2173 /* Not one of ours. Pass through to HDLC package */ 2174 return hdlc_ioctl(dev, ifr, cmd); 2175 } 2176 } 2177 2178 static void 2179 fst_openport(struct fst_port_info *port) 2180 { 2181 int signals; 2182 int txq_length; 2183 2184 /* Only init things if card is actually running. This allows open to 2185 * succeed for downloads etc. 2186 */ 2187 if (port->card->state == FST_RUNNING) { 2188 if (port->run) { 2189 dbg(DBG_OPEN, "open: found port already running\n"); 2190 2191 fst_issue_cmd(port, STOPPORT); 2192 port->run = 0; 2193 } 2194 2195 fst_rx_config(port); 2196 fst_tx_config(port); 2197 fst_op_raise(port, OPSTS_RTS | OPSTS_DTR); 2198 2199 fst_issue_cmd(port, STARTPORT); 2200 port->run = 1; 2201 2202 signals = FST_RDL(port->card, v24DebouncedSts[port->index]); 2203 if (signals & (((port->hwif == X21) || (port->hwif == X21D)) 2204 ? IPSTS_INDICATE : IPSTS_DCD)) 2205 netif_carrier_on(port_to_dev(port)); 2206 else 2207 netif_carrier_off(port_to_dev(port)); 2208 2209 txq_length = port->txqe - port->txqs; 2210 port->txqe = 0; 2211 port->txqs = 0; 2212 } 2213 2214 } 2215 2216 static void 2217 fst_closeport(struct fst_port_info *port) 2218 { 2219 if (port->card->state == FST_RUNNING) { 2220 if (port->run) { 2221 port->run = 0; 2222 fst_op_lower(port, OPSTS_RTS | OPSTS_DTR); 2223 2224 fst_issue_cmd(port, STOPPORT); 2225 } else { 2226 dbg(DBG_OPEN, "close: port not running\n"); 2227 } 2228 } 2229 } 2230 2231 static int 2232 fst_open(struct net_device *dev) 2233 { 2234 int err; 2235 struct fst_port_info *port; 2236 2237 port = dev_to_port(dev); 2238 if (!try_module_get(THIS_MODULE)) 2239 return -EBUSY; 2240 2241 if (port->mode != FST_RAW) { 2242 err = hdlc_open(dev); 2243 if (err) 2244 return err; 2245 } 2246 2247 fst_openport(port); 2248 netif_wake_queue(dev); 2249 return 0; 2250 } 2251 2252 static int 2253 fst_close(struct net_device *dev) 2254 { 2255 struct fst_port_info *port; 2256 struct fst_card_info *card; 2257 unsigned char tx_dma_done; 2258 unsigned char rx_dma_done; 2259 2260 port = dev_to_port(dev); 2261 card = port->card; 2262 2263 tx_dma_done = inb(card->pci_conf + DMACSR1); 2264 rx_dma_done = inb(card->pci_conf + DMACSR0); 2265 dbg(DBG_OPEN, 2266 "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n", 2267 card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress, 2268 rx_dma_done); 2269 2270 netif_stop_queue(dev); 2271 fst_closeport(dev_to_port(dev)); 2272 if (port->mode != FST_RAW) { 2273 hdlc_close(dev); 2274 } 2275 module_put(THIS_MODULE); 2276 return 0; 2277 } 2278 2279 static int 2280 fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity) 2281 { 2282 /* 2283 * Setting currently fixed in FarSync card so we check and forget 2284 */ 2285 if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT) 2286 return -EINVAL; 2287 return 0; 2288 } 2289 2290 static void 2291 fst_tx_timeout(struct net_device *dev) 2292 { 2293 struct fst_port_info *port; 2294 struct fst_card_info *card; 2295 struct net_device_stats *stats = hdlc_stats(dev); 2296 2297 port = dev_to_port(dev); 2298 card = port->card; 2299 stats->tx_errors++; 2300 stats->tx_aborted_errors++; 2301 dbg(DBG_ASS, "Tx timeout card %d port %d\n", 2302 card->card_no, port->index); 2303 fst_issue_cmd(port, ABORTTX); 2304 2305 dev->trans_start = jiffies; 2306 netif_wake_queue(dev); 2307 port->start = 0; 2308 } 2309 2310 static int 2311 fst_start_xmit(struct sk_buff *skb, struct net_device *dev) 2312 { 2313 struct fst_card_info *card; 2314 struct fst_port_info *port; 2315 struct net_device_stats *stats = hdlc_stats(dev); 2316 unsigned long flags; 2317 int txq_length; 2318 2319 port = dev_to_port(dev); 2320 card = port->card; 2321 dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len); 2322 2323 /* Drop packet with error if we don't have carrier */ 2324 if (!netif_carrier_ok(dev)) { 2325 dev_kfree_skb(skb); 2326 stats->tx_errors++; 2327 stats->tx_carrier_errors++; 2328 dbg(DBG_ASS, 2329 "Tried to transmit but no carrier on card %d port %d\n", 2330 card->card_no, port->index); 2331 return 0; 2332 } 2333 2334 /* Drop it if it's too big! MTU failure ? */ 2335 if (skb->len > LEN_TX_BUFFER) { 2336 dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len, 2337 LEN_TX_BUFFER); 2338 dev_kfree_skb(skb); 2339 stats->tx_errors++; 2340 return 0; 2341 } 2342 2343 /* 2344 * We are always going to queue the packet 2345 * so that the bottom half is the only place we tx from 2346 * Check there is room in the port txq 2347 */ 2348 spin_lock_irqsave(&card->card_lock, flags); 2349 if ((txq_length = port->txqe - port->txqs) < 0) { 2350 /* 2351 * This is the case where the next free has wrapped but the 2352 * last used hasn't 2353 */ 2354 txq_length = txq_length + FST_TXQ_DEPTH; 2355 } 2356 spin_unlock_irqrestore(&card->card_lock, flags); 2357 if (txq_length > fst_txq_high) { 2358 /* 2359 * We have got enough buffers in the pipeline. Ask the network 2360 * layer to stop sending frames down 2361 */ 2362 netif_stop_queue(dev); 2363 port->start = 1; /* I'm using this to signal stop sent up */ 2364 } 2365 2366 if (txq_length == FST_TXQ_DEPTH - 1) { 2367 /* 2368 * This shouldn't have happened but such is life 2369 */ 2370 dev_kfree_skb(skb); 2371 stats->tx_errors++; 2372 dbg(DBG_ASS, "Tx queue overflow card %d port %d\n", 2373 card->card_no, port->index); 2374 return 0; 2375 } 2376 2377 /* 2378 * queue the buffer 2379 */ 2380 spin_lock_irqsave(&card->card_lock, flags); 2381 port->txq[port->txqe] = skb; 2382 port->txqe++; 2383 if (port->txqe == FST_TXQ_DEPTH) 2384 port->txqe = 0; 2385 spin_unlock_irqrestore(&card->card_lock, flags); 2386 2387 /* Scehdule the bottom half which now does transmit processing */ 2388 fst_q_work_item(&fst_work_txq, card->card_no); 2389 tasklet_schedule(&fst_tx_task); 2390 2391 return 0; 2392 } 2393 2394 /* 2395 * Card setup having checked hardware resources. 2396 * Should be pretty bizarre if we get an error here (kernel memory 2397 * exhaustion is one possibility). If we do see a problem we report it 2398 * via a printk and leave the corresponding interface and all that follow 2399 * disabled. 2400 */ 2401 static char *type_strings[] __devinitdata = { 2402 "no hardware", /* Should never be seen */ 2403 "FarSync T2P", 2404 "FarSync T4P", 2405 "FarSync T1U", 2406 "FarSync T2U", 2407 "FarSync T4U", 2408 "FarSync TE1" 2409 }; 2410 2411 static void __devinit 2412 fst_init_card(struct fst_card_info *card) 2413 { 2414 int i; 2415 int err; 2416 2417 /* We're working on a number of ports based on the card ID. If the 2418 * firmware detects something different later (should never happen) 2419 * we'll have to revise it in some way then. 2420 */ 2421 for (i = 0; i < card->nports; i++) { 2422 err = register_hdlc_device(card->ports[i].dev); 2423 if (err < 0) { 2424 int j; 2425 printk_err ("Cannot register HDLC device for port %d" 2426 " (errno %d)\n", i, -err ); 2427 for (j = i; j < card->nports; j++) { 2428 free_netdev(card->ports[j].dev); 2429 card->ports[j].dev = NULL; 2430 } 2431 card->nports = i; 2432 break; 2433 } 2434 } 2435 2436 printk_info("%s-%s: %s IRQ%d, %d ports\n", 2437 port_to_dev(&card->ports[0])->name, 2438 port_to_dev(&card->ports[card->nports - 1])->name, 2439 type_strings[card->type], card->irq, card->nports); 2440 } 2441 2442 /* 2443 * Initialise card when detected. 2444 * Returns 0 to indicate success, or errno otherwise. 2445 */ 2446 static int __devinit 2447 fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent) 2448 { 2449 static int firsttime_done = 0; 2450 static int no_of_cards_added = 0; 2451 struct fst_card_info *card; 2452 int err = 0; 2453 int i; 2454 2455 if (!firsttime_done) { 2456 printk_info("FarSync WAN driver " FST_USER_VERSION 2457 " (c) 2001-2004 FarSite Communications Ltd.\n"); 2458 firsttime_done = 1; 2459 dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask); 2460 } 2461 2462 /* 2463 * We are going to be clever and allow certain cards not to be 2464 * configured. An exclude list can be provided in /etc/modules.conf 2465 */ 2466 if (fst_excluded_cards != 0) { 2467 /* 2468 * There are cards to exclude 2469 * 2470 */ 2471 for (i = 0; i < fst_excluded_cards; i++) { 2472 if ((pdev->devfn) >> 3 == fst_excluded_list[i]) { 2473 printk_info("FarSync PCI device %d not assigned\n", 2474 (pdev->devfn) >> 3); 2475 return -EBUSY; 2476 } 2477 } 2478 } 2479 2480 /* Allocate driver private data */ 2481 card = kzalloc(sizeof (struct fst_card_info), GFP_KERNEL); 2482 if (card == NULL) { 2483 printk_err("FarSync card found but insufficient memory for" 2484 " driver storage\n"); 2485 return -ENOMEM; 2486 } 2487 2488 /* Try to enable the device */ 2489 if ((err = pci_enable_device(pdev)) != 0) { 2490 printk_err("Failed to enable card. Err %d\n", -err); 2491 kfree(card); 2492 return err; 2493 } 2494 2495 if ((err = pci_request_regions(pdev, "FarSync")) !=0) { 2496 printk_err("Failed to allocate regions. Err %d\n", -err); 2497 pci_disable_device(pdev); 2498 kfree(card); 2499 return err; 2500 } 2501 2502 /* Get virtual addresses of memory regions */ 2503 card->pci_conf = pci_resource_start(pdev, 1); 2504 card->phys_mem = pci_resource_start(pdev, 2); 2505 card->phys_ctlmem = pci_resource_start(pdev, 3); 2506 if ((card->mem = ioremap(card->phys_mem, FST_MEMSIZE)) == NULL) { 2507 printk_err("Physical memory remap failed\n"); 2508 pci_release_regions(pdev); 2509 pci_disable_device(pdev); 2510 kfree(card); 2511 return -ENODEV; 2512 } 2513 if ((card->ctlmem = ioremap(card->phys_ctlmem, 0x10)) == NULL) { 2514 printk_err("Control memory remap failed\n"); 2515 pci_release_regions(pdev); 2516 pci_disable_device(pdev); 2517 kfree(card); 2518 return -ENODEV; 2519 } 2520 dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem); 2521 2522 /* Register the interrupt handler */ 2523 if (request_irq(pdev->irq, fst_intr, IRQF_SHARED, FST_DEV_NAME, card)) { 2524 printk_err("Unable to register interrupt %d\n", card->irq); 2525 pci_release_regions(pdev); 2526 pci_disable_device(pdev); 2527 iounmap(card->ctlmem); 2528 iounmap(card->mem); 2529 kfree(card); 2530 return -ENODEV; 2531 } 2532 2533 /* Record info we need */ 2534 card->irq = pdev->irq; 2535 card->type = ent->driver_data; 2536 card->family = ((ent->driver_data == FST_TYPE_T2P) || 2537 (ent->driver_data == FST_TYPE_T4P)) 2538 ? FST_FAMILY_TXP : FST_FAMILY_TXU; 2539 if ((ent->driver_data == FST_TYPE_T1U) || 2540 (ent->driver_data == FST_TYPE_TE1)) 2541 card->nports = 1; 2542 else 2543 card->nports = ((ent->driver_data == FST_TYPE_T2P) || 2544 (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4; 2545 2546 card->state = FST_UNINIT; 2547 spin_lock_init ( &card->card_lock ); 2548 2549 for ( i = 0 ; i < card->nports ; i++ ) { 2550 struct net_device *dev = alloc_hdlcdev(&card->ports[i]); 2551 hdlc_device *hdlc; 2552 if (!dev) { 2553 while (i--) 2554 free_netdev(card->ports[i].dev); 2555 printk_err ("FarSync: out of memory\n"); 2556 free_irq(card->irq, card); 2557 pci_release_regions(pdev); 2558 pci_disable_device(pdev); 2559 iounmap(card->ctlmem); 2560 iounmap(card->mem); 2561 kfree(card); 2562 return -ENODEV; 2563 } 2564 card->ports[i].dev = dev; 2565 card->ports[i].card = card; 2566 card->ports[i].index = i; 2567 card->ports[i].run = 0; 2568 2569 hdlc = dev_to_hdlc(dev); 2570 2571 /* Fill in the net device info */ 2572 /* Since this is a PCI setup this is purely 2573 * informational. Give them the buffer addresses 2574 * and basic card I/O. 2575 */ 2576 dev->mem_start = card->phys_mem 2577 + BUF_OFFSET ( txBuffer[i][0][0]); 2578 dev->mem_end = card->phys_mem 2579 + BUF_OFFSET ( txBuffer[i][NUM_TX_BUFFER][0]); 2580 dev->base_addr = card->pci_conf; 2581 dev->irq = card->irq; 2582 2583 dev->tx_queue_len = FST_TX_QUEUE_LEN; 2584 dev->open = fst_open; 2585 dev->stop = fst_close; 2586 dev->do_ioctl = fst_ioctl; 2587 dev->watchdog_timeo = FST_TX_TIMEOUT; 2588 dev->tx_timeout = fst_tx_timeout; 2589 hdlc->attach = fst_attach; 2590 hdlc->xmit = fst_start_xmit; 2591 } 2592 2593 card->device = pdev; 2594 2595 dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type, 2596 card->nports, card->irq); 2597 dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n", 2598 card->pci_conf, card->phys_mem, card->phys_ctlmem); 2599 2600 /* Reset the card's processor */ 2601 fst_cpureset(card); 2602 card->state = FST_RESET; 2603 2604 /* Initialise DMA (if required) */ 2605 fst_init_dma(card); 2606 2607 /* Record driver data for later use */ 2608 pci_set_drvdata(pdev, card); 2609 2610 /* Remainder of card setup */ 2611 fst_card_array[no_of_cards_added] = card; 2612 card->card_no = no_of_cards_added++; /* Record instance and bump it */ 2613 fst_init_card(card); 2614 if (card->family == FST_FAMILY_TXU) { 2615 /* 2616 * Allocate a dma buffer for transmit and receives 2617 */ 2618 card->rx_dma_handle_host = 2619 pci_alloc_consistent(card->device, FST_MAX_MTU, 2620 &card->rx_dma_handle_card); 2621 if (card->rx_dma_handle_host == NULL) { 2622 printk_err("Could not allocate rx dma buffer\n"); 2623 fst_disable_intr(card); 2624 pci_release_regions(pdev); 2625 pci_disable_device(pdev); 2626 iounmap(card->ctlmem); 2627 iounmap(card->mem); 2628 kfree(card); 2629 return -ENOMEM; 2630 } 2631 card->tx_dma_handle_host = 2632 pci_alloc_consistent(card->device, FST_MAX_MTU, 2633 &card->tx_dma_handle_card); 2634 if (card->tx_dma_handle_host == NULL) { 2635 printk_err("Could not allocate tx dma buffer\n"); 2636 fst_disable_intr(card); 2637 pci_release_regions(pdev); 2638 pci_disable_device(pdev); 2639 iounmap(card->ctlmem); 2640 iounmap(card->mem); 2641 kfree(card); 2642 return -ENOMEM; 2643 } 2644 } 2645 return 0; /* Success */ 2646 } 2647 2648 /* 2649 * Cleanup and close down a card 2650 */ 2651 static void __devexit 2652 fst_remove_one(struct pci_dev *pdev) 2653 { 2654 struct fst_card_info *card; 2655 int i; 2656 2657 card = pci_get_drvdata(pdev); 2658 2659 for (i = 0; i < card->nports; i++) { 2660 struct net_device *dev = port_to_dev(&card->ports[i]); 2661 unregister_hdlc_device(dev); 2662 } 2663 2664 fst_disable_intr(card); 2665 free_irq(card->irq, card); 2666 2667 iounmap(card->ctlmem); 2668 iounmap(card->mem); 2669 pci_release_regions(pdev); 2670 if (card->family == FST_FAMILY_TXU) { 2671 /* 2672 * Free dma buffers 2673 */ 2674 pci_free_consistent(card->device, FST_MAX_MTU, 2675 card->rx_dma_handle_host, 2676 card->rx_dma_handle_card); 2677 pci_free_consistent(card->device, FST_MAX_MTU, 2678 card->tx_dma_handle_host, 2679 card->tx_dma_handle_card); 2680 } 2681 fst_card_array[card->card_no] = NULL; 2682 } 2683 2684 static struct pci_driver fst_driver = { 2685 .name = FST_NAME, 2686 .id_table = fst_pci_dev_id, 2687 .probe = fst_add_one, 2688 .remove = __devexit_p(fst_remove_one), 2689 .suspend = NULL, 2690 .resume = NULL, 2691 }; 2692 2693 static int __init 2694 fst_init(void) 2695 { 2696 int i; 2697 2698 for (i = 0; i < FST_MAX_CARDS; i++) 2699 fst_card_array[i] = NULL; 2700 spin_lock_init(&fst_work_q_lock); 2701 return pci_register_driver(&fst_driver); 2702 } 2703 2704 static void __exit 2705 fst_cleanup_module(void) 2706 { 2707 printk_info("FarSync WAN driver unloading\n"); 2708 pci_unregister_driver(&fst_driver); 2709 } 2710 2711 module_init(fst_init); 2712 module_exit(fst_cleanup_module); 2713