1 /* 2 * Moxa C101 synchronous serial card driver for Linux 3 * 4 * Copyright (C) 2000-2003 Krzysztof Halasa <khc@pm.waw.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License 8 * as published by the Free Software Foundation. 9 * 10 * For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/> 11 * 12 * Sources of information: 13 * Hitachi HD64570 SCA User's Manual 14 * Moxa C101 User's Manual 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/capability.h> 22 #include <linux/slab.h> 23 #include <linux/types.h> 24 #include <linux/string.h> 25 #include <linux/errno.h> 26 #include <linux/init.h> 27 #include <linux/netdevice.h> 28 #include <linux/hdlc.h> 29 #include <linux/delay.h> 30 #include <asm/io.h> 31 32 #include "hd64570.h" 33 34 35 static const char* version = "Moxa C101 driver version: 1.15"; 36 static const char* devname = "C101"; 37 38 #undef DEBUG_PKT 39 #define DEBUG_RINGS 40 41 #define C101_PAGE 0x1D00 42 #define C101_DTR 0x1E00 43 #define C101_SCA 0x1F00 44 #define C101_WINDOW_SIZE 0x2000 45 #define C101_MAPPED_RAM_SIZE 0x4000 46 47 #define RAM_SIZE (256 * 1024) 48 #define TX_RING_BUFFERS 10 49 #define RX_RING_BUFFERS ((RAM_SIZE - C101_WINDOW_SIZE) / \ 50 (sizeof(pkt_desc) + HDLC_MAX_MRU) - TX_RING_BUFFERS) 51 52 #define CLOCK_BASE 9830400 /* 9.8304 MHz */ 53 #define PAGE0_ALWAYS_MAPPED 54 55 static char *hw; /* pointer to hw=xxx command line string */ 56 57 58 typedef struct card_s { 59 struct net_device *dev; 60 spinlock_t lock; /* TX lock */ 61 u8 __iomem *win0base; /* ISA window base address */ 62 u32 phy_winbase; /* ISA physical base address */ 63 sync_serial_settings settings; 64 int rxpart; /* partial frame received, next frame invalid*/ 65 unsigned short encoding; 66 unsigned short parity; 67 u16 rx_ring_buffers; /* number of buffers in a ring */ 68 u16 tx_ring_buffers; 69 u16 buff_offset; /* offset of first buffer of first channel */ 70 u16 rxin; /* rx ring buffer 'in' pointer */ 71 u16 txin; /* tx ring buffer 'in' and 'last' pointers */ 72 u16 txlast; 73 u8 rxs, txs, tmc; /* SCA registers */ 74 u8 irq; /* IRQ (3-15) */ 75 u8 page; 76 77 struct card_s *next_card; 78 }card_t; 79 80 typedef card_t port_t; 81 82 static card_t *first_card; 83 static card_t **new_card = &first_card; 84 85 86 #define sca_in(reg, card) readb((card)->win0base + C101_SCA + (reg)) 87 #define sca_out(value, reg, card) writeb(value, (card)->win0base + C101_SCA + (reg)) 88 #define sca_inw(reg, card) readw((card)->win0base + C101_SCA + (reg)) 89 90 /* EDA address register must be set in EDAL, EDAH order - 8 bit ISA bus */ 91 #define sca_outw(value, reg, card) do { \ 92 writeb(value & 0xFF, (card)->win0base + C101_SCA + (reg)); \ 93 writeb((value >> 8 ) & 0xFF, (card)->win0base + C101_SCA + (reg + 1));\ 94 } while(0) 95 96 #define port_to_card(port) (port) 97 #define log_node(port) (0) 98 #define phy_node(port) (0) 99 #define winsize(card) (C101_WINDOW_SIZE) 100 #define win0base(card) ((card)->win0base) 101 #define winbase(card) ((card)->win0base + 0x2000) 102 #define get_port(card, port) (card) 103 static void sca_msci_intr(port_t *port); 104 105 106 static inline u8 sca_get_page(card_t *card) 107 { 108 return card->page; 109 } 110 111 static inline void openwin(card_t *card, u8 page) 112 { 113 card->page = page; 114 writeb(page, card->win0base + C101_PAGE); 115 } 116 117 118 #include "hd64570.c" 119 120 121 static inline void set_carrier(port_t *port) 122 { 123 if (!(sca_in(MSCI1_OFFSET + ST3, port) & ST3_DCD)) 124 netif_carrier_on(port_to_dev(port)); 125 else 126 netif_carrier_off(port_to_dev(port)); 127 } 128 129 130 static void sca_msci_intr(port_t *port) 131 { 132 u8 stat = sca_in(MSCI0_OFFSET + ST1, port); /* read MSCI ST1 status */ 133 134 /* Reset MSCI TX underrun and CDCD (ignored) status bit */ 135 sca_out(stat & (ST1_UDRN | ST1_CDCD), MSCI0_OFFSET + ST1, port); 136 137 if (stat & ST1_UDRN) { 138 /* TX Underrun error detected */ 139 port_to_dev(port)->stats.tx_errors++; 140 port_to_dev(port)->stats.tx_fifo_errors++; 141 } 142 143 stat = sca_in(MSCI1_OFFSET + ST1, port); /* read MSCI1 ST1 status */ 144 /* Reset MSCI CDCD status bit - uses ch#2 DCD input */ 145 sca_out(stat & ST1_CDCD, MSCI1_OFFSET + ST1, port); 146 147 if (stat & ST1_CDCD) 148 set_carrier(port); 149 } 150 151 152 static void c101_set_iface(port_t *port) 153 { 154 u8 rxs = port->rxs & CLK_BRG_MASK; 155 u8 txs = port->txs & CLK_BRG_MASK; 156 157 switch(port->settings.clock_type) { 158 case CLOCK_INT: 159 rxs |= CLK_BRG_RX; /* TX clock */ 160 txs |= CLK_RXCLK_TX; /* BRG output */ 161 break; 162 163 case CLOCK_TXINT: 164 rxs |= CLK_LINE_RX; /* RXC input */ 165 txs |= CLK_BRG_TX; /* BRG output */ 166 break; 167 168 case CLOCK_TXFROMRX: 169 rxs |= CLK_LINE_RX; /* RXC input */ 170 txs |= CLK_RXCLK_TX; /* RX clock */ 171 break; 172 173 default: /* EXTernal clock */ 174 rxs |= CLK_LINE_RX; /* RXC input */ 175 txs |= CLK_LINE_TX; /* TXC input */ 176 } 177 178 port->rxs = rxs; 179 port->txs = txs; 180 sca_out(rxs, MSCI1_OFFSET + RXS, port); 181 sca_out(txs, MSCI1_OFFSET + TXS, port); 182 sca_set_port(port); 183 } 184 185 186 static int c101_open(struct net_device *dev) 187 { 188 port_t *port = dev_to_port(dev); 189 int result; 190 191 result = hdlc_open(dev); 192 if (result) 193 return result; 194 195 writeb(1, port->win0base + C101_DTR); 196 sca_out(0, MSCI1_OFFSET + CTL, port); /* RTS uses ch#2 output */ 197 sca_open(dev); 198 /* DCD is connected to port 2 !@#$%^& - disable MSCI0 CDCD interrupt */ 199 sca_out(IE1_UDRN, MSCI0_OFFSET + IE1, port); 200 sca_out(IE0_TXINT, MSCI0_OFFSET + IE0, port); 201 202 set_carrier(port); 203 204 /* enable MSCI1 CDCD interrupt */ 205 sca_out(IE1_CDCD, MSCI1_OFFSET + IE1, port); 206 sca_out(IE0_RXINTA, MSCI1_OFFSET + IE0, port); 207 sca_out(0x48, IER0, port); /* TXINT #0 and RXINT #1 */ 208 c101_set_iface(port); 209 return 0; 210 } 211 212 213 static int c101_close(struct net_device *dev) 214 { 215 port_t *port = dev_to_port(dev); 216 217 sca_close(dev); 218 writeb(0, port->win0base + C101_DTR); 219 sca_out(CTL_NORTS, MSCI1_OFFSET + CTL, port); 220 hdlc_close(dev); 221 return 0; 222 } 223 224 225 static int c101_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 226 { 227 const size_t size = sizeof(sync_serial_settings); 228 sync_serial_settings new_line; 229 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; 230 port_t *port = dev_to_port(dev); 231 232 #ifdef DEBUG_RINGS 233 if (cmd == SIOCDEVPRIVATE) { 234 sca_dump_rings(dev); 235 printk(KERN_DEBUG "MSCI1: ST: %02x %02x %02x %02x\n", 236 sca_in(MSCI1_OFFSET + ST0, port), 237 sca_in(MSCI1_OFFSET + ST1, port), 238 sca_in(MSCI1_OFFSET + ST2, port), 239 sca_in(MSCI1_OFFSET + ST3, port)); 240 return 0; 241 } 242 #endif 243 if (cmd != SIOCWANDEV) 244 return hdlc_ioctl(dev, ifr, cmd); 245 246 switch(ifr->ifr_settings.type) { 247 case IF_GET_IFACE: 248 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; 249 if (ifr->ifr_settings.size < size) { 250 ifr->ifr_settings.size = size; /* data size wanted */ 251 return -ENOBUFS; 252 } 253 if (copy_to_user(line, &port->settings, size)) 254 return -EFAULT; 255 return 0; 256 257 case IF_IFACE_SYNC_SERIAL: 258 if(!capable(CAP_NET_ADMIN)) 259 return -EPERM; 260 261 if (copy_from_user(&new_line, line, size)) 262 return -EFAULT; 263 264 if (new_line.clock_type != CLOCK_EXT && 265 new_line.clock_type != CLOCK_TXFROMRX && 266 new_line.clock_type != CLOCK_INT && 267 new_line.clock_type != CLOCK_TXINT) 268 return -EINVAL; /* No such clock setting */ 269 270 if (new_line.loopback != 0 && new_line.loopback != 1) 271 return -EINVAL; 272 273 memcpy(&port->settings, &new_line, size); /* Update settings */ 274 c101_set_iface(port); 275 return 0; 276 277 default: 278 return hdlc_ioctl(dev, ifr, cmd); 279 } 280 } 281 282 283 284 static void c101_destroy_card(card_t *card) 285 { 286 readb(card->win0base + C101_PAGE); /* Resets SCA? */ 287 288 if (card->irq) 289 free_irq(card->irq, card); 290 291 if (card->win0base) { 292 iounmap(card->win0base); 293 release_mem_region(card->phy_winbase, C101_MAPPED_RAM_SIZE); 294 } 295 296 free_netdev(card->dev); 297 298 kfree(card); 299 } 300 301 static const struct net_device_ops c101_ops = { 302 .ndo_open = c101_open, 303 .ndo_stop = c101_close, 304 .ndo_start_xmit = hdlc_start_xmit, 305 .ndo_do_ioctl = c101_ioctl, 306 }; 307 308 static int __init c101_run(unsigned long irq, unsigned long winbase) 309 { 310 struct net_device *dev; 311 hdlc_device *hdlc; 312 card_t *card; 313 int result; 314 315 if (irq<3 || irq>15 || irq == 6) /* FIXME */ { 316 pr_err("invalid IRQ value\n"); 317 return -ENODEV; 318 } 319 320 if (winbase < 0xC0000 || winbase > 0xDFFFF || (winbase & 0x3FFF) !=0) { 321 pr_err("invalid RAM value\n"); 322 return -ENODEV; 323 } 324 325 card = kzalloc(sizeof(card_t), GFP_KERNEL); 326 if (card == NULL) 327 return -ENOBUFS; 328 329 card->dev = alloc_hdlcdev(card); 330 if (!card->dev) { 331 pr_err("unable to allocate memory\n"); 332 kfree(card); 333 return -ENOBUFS; 334 } 335 336 if (request_irq(irq, sca_intr, 0, devname, card)) { 337 pr_err("could not allocate IRQ\n"); 338 c101_destroy_card(card); 339 return -EBUSY; 340 } 341 card->irq = irq; 342 343 if (!request_mem_region(winbase, C101_MAPPED_RAM_SIZE, devname)) { 344 pr_err("could not request RAM window\n"); 345 c101_destroy_card(card); 346 return -EBUSY; 347 } 348 card->phy_winbase = winbase; 349 card->win0base = ioremap(winbase, C101_MAPPED_RAM_SIZE); 350 if (!card->win0base) { 351 pr_err("could not map I/O address\n"); 352 c101_destroy_card(card); 353 return -EFAULT; 354 } 355 356 card->tx_ring_buffers = TX_RING_BUFFERS; 357 card->rx_ring_buffers = RX_RING_BUFFERS; 358 card->buff_offset = C101_WINDOW_SIZE; /* Bytes 1D00-1FFF reserved */ 359 360 readb(card->win0base + C101_PAGE); /* Resets SCA? */ 361 udelay(100); 362 writeb(0, card->win0base + C101_PAGE); 363 writeb(0, card->win0base + C101_DTR); /* Power-up for RAM? */ 364 365 sca_init(card, 0); 366 367 dev = port_to_dev(card); 368 hdlc = dev_to_hdlc(dev); 369 370 spin_lock_init(&card->lock); 371 dev->irq = irq; 372 dev->mem_start = winbase; 373 dev->mem_end = winbase + C101_MAPPED_RAM_SIZE - 1; 374 dev->tx_queue_len = 50; 375 dev->netdev_ops = &c101_ops; 376 hdlc->attach = sca_attach; 377 hdlc->xmit = sca_xmit; 378 card->settings.clock_type = CLOCK_EXT; 379 380 result = register_hdlc_device(dev); 381 if (result) { 382 pr_warn("unable to register hdlc device\n"); 383 c101_destroy_card(card); 384 return result; 385 } 386 387 sca_init_port(card); /* Set up C101 memory */ 388 set_carrier(card); 389 390 netdev_info(dev, "Moxa C101 on IRQ%u, using %u TX + %u RX packets rings\n", 391 card->irq, card->tx_ring_buffers, card->rx_ring_buffers); 392 393 *new_card = card; 394 new_card = &card->next_card; 395 return 0; 396 } 397 398 399 400 static int __init c101_init(void) 401 { 402 if (hw == NULL) { 403 #ifdef MODULE 404 pr_info("no card initialized\n"); 405 #endif 406 return -EINVAL; /* no parameters specified, abort */ 407 } 408 409 pr_info("%s\n", version); 410 411 do { 412 unsigned long irq, ram; 413 414 irq = simple_strtoul(hw, &hw, 0); 415 416 if (*hw++ != ',') 417 break; 418 ram = simple_strtoul(hw, &hw, 0); 419 420 if (*hw == ':' || *hw == '\x0') 421 c101_run(irq, ram); 422 423 if (*hw == '\x0') 424 return first_card ? 0 : -EINVAL; 425 }while(*hw++ == ':'); 426 427 pr_err("invalid hardware parameters\n"); 428 return first_card ? 0 : -EINVAL; 429 } 430 431 432 static void __exit c101_cleanup(void) 433 { 434 card_t *card = first_card; 435 436 while (card) { 437 card_t *ptr = card; 438 card = card->next_card; 439 unregister_hdlc_device(port_to_dev(ptr)); 440 c101_destroy_card(ptr); 441 } 442 } 443 444 445 module_init(c101_init); 446 module_exit(c101_cleanup); 447 448 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>"); 449 MODULE_DESCRIPTION("Moxa C101 serial port driver"); 450 MODULE_LICENSE("GPL v2"); 451 module_param(hw, charp, 0444); 452 MODULE_PARM_DESC(hw, "irq,ram:irq,..."); 453