1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Moxa C101 synchronous serial card driver for Linux 4 * 5 * Copyright (C) 2000-2003 Krzysztof Halasa <khc@pm.waw.pl> 6 * 7 * For information see <https://www.kernel.org/pub/linux/utils/net/hdlc/> 8 * 9 * Sources of information: 10 * Hitachi HD64570 SCA User's Manual 11 * Moxa C101 User's Manual 12 */ 13 14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 15 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/capability.h> 19 #include <linux/slab.h> 20 #include <linux/types.h> 21 #include <linux/string.h> 22 #include <linux/errno.h> 23 #include <linux/init.h> 24 #include <linux/netdevice.h> 25 #include <linux/hdlc.h> 26 #include <linux/delay.h> 27 #include <asm/io.h> 28 29 #include "hd64570.h" 30 31 static const char *version = "Moxa C101 driver version: 1.15"; 32 static const char *devname = "C101"; 33 34 #undef DEBUG_PKT 35 #define DEBUG_RINGS 36 37 #define C101_PAGE 0x1D00 38 #define C101_DTR 0x1E00 39 #define C101_SCA 0x1F00 40 #define C101_WINDOW_SIZE 0x2000 41 #define C101_MAPPED_RAM_SIZE 0x4000 42 43 #define RAM_SIZE (256 * 1024) 44 #define TX_RING_BUFFERS 10 45 #define RX_RING_BUFFERS ((RAM_SIZE - C101_WINDOW_SIZE) / \ 46 (sizeof(pkt_desc) + HDLC_MAX_MRU) - TX_RING_BUFFERS) 47 48 #define CLOCK_BASE 9830400 /* 9.8304 MHz */ 49 #define PAGE0_ALWAYS_MAPPED 50 51 static char *hw; /* pointer to hw=xxx command line string */ 52 53 typedef struct card_s { 54 struct net_device *dev; 55 spinlock_t lock; /* TX lock */ 56 u8 __iomem *win0base; /* ISA window base address */ 57 u32 phy_winbase; /* ISA physical base address */ 58 sync_serial_settings settings; 59 int rxpart; /* partial frame received, next frame invalid*/ 60 unsigned short encoding; 61 unsigned short parity; 62 u16 rx_ring_buffers; /* number of buffers in a ring */ 63 u16 tx_ring_buffers; 64 u16 buff_offset; /* offset of first buffer of first channel */ 65 u16 rxin; /* rx ring buffer 'in' pointer */ 66 u16 txin; /* tx ring buffer 'in' and 'last' pointers */ 67 u16 txlast; 68 u8 rxs, txs, tmc; /* SCA registers */ 69 u8 irq; /* IRQ (3-15) */ 70 u8 page; 71 72 struct card_s *next_card; 73 } card_t; 74 75 typedef card_t port_t; 76 77 static card_t *first_card; 78 static card_t **new_card = &first_card; 79 80 #define sca_in(reg, card) readb((card)->win0base + C101_SCA + (reg)) 81 #define sca_out(value, reg, card) writeb(value, (card)->win0base + C101_SCA + (reg)) 82 #define sca_inw(reg, card) readw((card)->win0base + C101_SCA + (reg)) 83 84 /* EDA address register must be set in EDAL, EDAH order - 8 bit ISA bus */ 85 #define sca_outw(value, reg, card) do { \ 86 writeb(value & 0xFF, (card)->win0base + C101_SCA + (reg)); \ 87 writeb((value >> 8) & 0xFF, (card)->win0base + C101_SCA + (reg + 1));\ 88 } while (0) 89 90 #define port_to_card(port) (port) 91 #define log_node(port) (0) 92 #define phy_node(port) (0) 93 #define winsize(card) (C101_WINDOW_SIZE) 94 #define win0base(card) ((card)->win0base) 95 #define winbase(card) ((card)->win0base + 0x2000) 96 #define get_port(card, port) (card) 97 static void sca_msci_intr(port_t *port); 98 99 static inline u8 sca_get_page(card_t *card) 100 { 101 return card->page; 102 } 103 104 static inline void openwin(card_t *card, u8 page) 105 { 106 card->page = page; 107 writeb(page, card->win0base + C101_PAGE); 108 } 109 110 #include "hd64570.c" 111 112 static inline void set_carrier(port_t *port) 113 { 114 if (!(sca_in(MSCI1_OFFSET + ST3, port) & ST3_DCD)) 115 netif_carrier_on(port_to_dev(port)); 116 else 117 netif_carrier_off(port_to_dev(port)); 118 } 119 120 static void sca_msci_intr(port_t *port) 121 { 122 u8 stat = sca_in(MSCI0_OFFSET + ST1, port); /* read MSCI ST1 status */ 123 124 /* Reset MSCI TX underrun and CDCD (ignored) status bit */ 125 sca_out(stat & (ST1_UDRN | ST1_CDCD), MSCI0_OFFSET + ST1, port); 126 127 if (stat & ST1_UDRN) { 128 /* TX Underrun error detected */ 129 port_to_dev(port)->stats.tx_errors++; 130 port_to_dev(port)->stats.tx_fifo_errors++; 131 } 132 133 stat = sca_in(MSCI1_OFFSET + ST1, port); /* read MSCI1 ST1 status */ 134 /* Reset MSCI CDCD status bit - uses ch#2 DCD input */ 135 sca_out(stat & ST1_CDCD, MSCI1_OFFSET + ST1, port); 136 137 if (stat & ST1_CDCD) 138 set_carrier(port); 139 } 140 141 static void c101_set_iface(port_t *port) 142 { 143 u8 rxs = port->rxs & CLK_BRG_MASK; 144 u8 txs = port->txs & CLK_BRG_MASK; 145 146 switch (port->settings.clock_type) { 147 case CLOCK_INT: 148 rxs |= CLK_BRG_RX; /* TX clock */ 149 txs |= CLK_RXCLK_TX; /* BRG output */ 150 break; 151 152 case CLOCK_TXINT: 153 rxs |= CLK_LINE_RX; /* RXC input */ 154 txs |= CLK_BRG_TX; /* BRG output */ 155 break; 156 157 case CLOCK_TXFROMRX: 158 rxs |= CLK_LINE_RX; /* RXC input */ 159 txs |= CLK_RXCLK_TX; /* RX clock */ 160 break; 161 162 default: /* EXTernal clock */ 163 rxs |= CLK_LINE_RX; /* RXC input */ 164 txs |= CLK_LINE_TX; /* TXC input */ 165 } 166 167 port->rxs = rxs; 168 port->txs = txs; 169 sca_out(rxs, MSCI1_OFFSET + RXS, port); 170 sca_out(txs, MSCI1_OFFSET + TXS, port); 171 sca_set_port(port); 172 } 173 174 static int c101_open(struct net_device *dev) 175 { 176 port_t *port = dev_to_port(dev); 177 int result; 178 179 result = hdlc_open(dev); 180 if (result) 181 return result; 182 183 writeb(1, port->win0base + C101_DTR); 184 sca_out(0, MSCI1_OFFSET + CTL, port); /* RTS uses ch#2 output */ 185 sca_open(dev); 186 /* DCD is connected to port 2 !@#$%^& - disable MSCI0 CDCD interrupt */ 187 sca_out(IE1_UDRN, MSCI0_OFFSET + IE1, port); 188 sca_out(IE0_TXINT, MSCI0_OFFSET + IE0, port); 189 190 set_carrier(port); 191 192 /* enable MSCI1 CDCD interrupt */ 193 sca_out(IE1_CDCD, MSCI1_OFFSET + IE1, port); 194 sca_out(IE0_RXINTA, MSCI1_OFFSET + IE0, port); 195 sca_out(0x48, IER0, port); /* TXINT #0 and RXINT #1 */ 196 c101_set_iface(port); 197 return 0; 198 } 199 200 static int c101_close(struct net_device *dev) 201 { 202 port_t *port = dev_to_port(dev); 203 204 sca_close(dev); 205 writeb(0, port->win0base + C101_DTR); 206 sca_out(CTL_NORTS, MSCI1_OFFSET + CTL, port); 207 hdlc_close(dev); 208 return 0; 209 } 210 211 static int c101_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 212 { 213 const size_t size = sizeof(sync_serial_settings); 214 sync_serial_settings new_line; 215 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; 216 port_t *port = dev_to_port(dev); 217 218 #ifdef DEBUG_RINGS 219 if (cmd == SIOCDEVPRIVATE) { 220 sca_dump_rings(dev); 221 printk(KERN_DEBUG "MSCI1: ST: %02x %02x %02x %02x\n", 222 sca_in(MSCI1_OFFSET + ST0, port), 223 sca_in(MSCI1_OFFSET + ST1, port), 224 sca_in(MSCI1_OFFSET + ST2, port), 225 sca_in(MSCI1_OFFSET + ST3, port)); 226 return 0; 227 } 228 #endif 229 if (cmd != SIOCWANDEV) 230 return hdlc_ioctl(dev, ifr, cmd); 231 232 switch (ifr->ifr_settings.type) { 233 case IF_GET_IFACE: 234 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; 235 if (ifr->ifr_settings.size < size) { 236 ifr->ifr_settings.size = size; /* data size wanted */ 237 return -ENOBUFS; 238 } 239 if (copy_to_user(line, &port->settings, size)) 240 return -EFAULT; 241 return 0; 242 243 case IF_IFACE_SYNC_SERIAL: 244 if (!capable(CAP_NET_ADMIN)) 245 return -EPERM; 246 247 if (copy_from_user(&new_line, line, size)) 248 return -EFAULT; 249 250 if (new_line.clock_type != CLOCK_EXT && 251 new_line.clock_type != CLOCK_TXFROMRX && 252 new_line.clock_type != CLOCK_INT && 253 new_line.clock_type != CLOCK_TXINT) 254 return -EINVAL; /* No such clock setting */ 255 256 if (new_line.loopback != 0 && new_line.loopback != 1) 257 return -EINVAL; 258 259 memcpy(&port->settings, &new_line, size); /* Update settings */ 260 c101_set_iface(port); 261 return 0; 262 263 default: 264 return hdlc_ioctl(dev, ifr, cmd); 265 } 266 } 267 268 static void c101_destroy_card(card_t *card) 269 { 270 readb(card->win0base + C101_PAGE); /* Resets SCA? */ 271 272 if (card->irq) 273 free_irq(card->irq, card); 274 275 if (card->win0base) { 276 iounmap(card->win0base); 277 release_mem_region(card->phy_winbase, C101_MAPPED_RAM_SIZE); 278 } 279 280 free_netdev(card->dev); 281 282 kfree(card); 283 } 284 285 static const struct net_device_ops c101_ops = { 286 .ndo_open = c101_open, 287 .ndo_stop = c101_close, 288 .ndo_start_xmit = hdlc_start_xmit, 289 .ndo_do_ioctl = c101_ioctl, 290 }; 291 292 static int __init c101_run(unsigned long irq, unsigned long winbase) 293 { 294 struct net_device *dev; 295 hdlc_device *hdlc; 296 card_t *card; 297 int result; 298 299 if (irq < 3 || irq > 15 || irq == 6) /* FIXME */ { 300 pr_err("invalid IRQ value\n"); 301 return -ENODEV; 302 } 303 304 if (winbase < 0xC0000 || winbase > 0xDFFFF || (winbase & 0x3FFF) != 0) { 305 pr_err("invalid RAM value\n"); 306 return -ENODEV; 307 } 308 309 card = kzalloc(sizeof(card_t), GFP_KERNEL); 310 if (!card) 311 return -ENOBUFS; 312 313 card->dev = alloc_hdlcdev(card); 314 if (!card->dev) { 315 pr_err("unable to allocate memory\n"); 316 kfree(card); 317 return -ENOBUFS; 318 } 319 320 if (request_irq(irq, sca_intr, 0, devname, card)) { 321 pr_err("could not allocate IRQ\n"); 322 c101_destroy_card(card); 323 return -EBUSY; 324 } 325 card->irq = irq; 326 327 if (!request_mem_region(winbase, C101_MAPPED_RAM_SIZE, devname)) { 328 pr_err("could not request RAM window\n"); 329 c101_destroy_card(card); 330 return -EBUSY; 331 } 332 card->phy_winbase = winbase; 333 card->win0base = ioremap(winbase, C101_MAPPED_RAM_SIZE); 334 if (!card->win0base) { 335 pr_err("could not map I/O address\n"); 336 c101_destroy_card(card); 337 return -EFAULT; 338 } 339 340 card->tx_ring_buffers = TX_RING_BUFFERS; 341 card->rx_ring_buffers = RX_RING_BUFFERS; 342 card->buff_offset = C101_WINDOW_SIZE; /* Bytes 1D00-1FFF reserved */ 343 344 readb(card->win0base + C101_PAGE); /* Resets SCA? */ 345 udelay(100); 346 writeb(0, card->win0base + C101_PAGE); 347 writeb(0, card->win0base + C101_DTR); /* Power-up for RAM? */ 348 349 sca_init(card, 0); 350 351 dev = port_to_dev(card); 352 hdlc = dev_to_hdlc(dev); 353 354 spin_lock_init(&card->lock); 355 dev->irq = irq; 356 dev->mem_start = winbase; 357 dev->mem_end = winbase + C101_MAPPED_RAM_SIZE - 1; 358 dev->tx_queue_len = 50; 359 dev->netdev_ops = &c101_ops; 360 hdlc->attach = sca_attach; 361 hdlc->xmit = sca_xmit; 362 card->settings.clock_type = CLOCK_EXT; 363 364 result = register_hdlc_device(dev); 365 if (result) { 366 pr_warn("unable to register hdlc device\n"); 367 c101_destroy_card(card); 368 return result; 369 } 370 371 sca_init_port(card); /* Set up C101 memory */ 372 set_carrier(card); 373 374 netdev_info(dev, "Moxa C101 on IRQ%u, using %u TX + %u RX packets rings\n", 375 card->irq, card->tx_ring_buffers, card->rx_ring_buffers); 376 377 *new_card = card; 378 new_card = &card->next_card; 379 return 0; 380 } 381 382 static int __init c101_init(void) 383 { 384 if (!hw) { 385 #ifdef MODULE 386 pr_info("no card initialized\n"); 387 #endif 388 return -EINVAL; /* no parameters specified, abort */ 389 } 390 391 pr_info("%s\n", version); 392 393 do { 394 unsigned long irq, ram; 395 396 irq = simple_strtoul(hw, &hw, 0); 397 398 if (*hw++ != ',') 399 break; 400 ram = simple_strtoul(hw, &hw, 0); 401 402 if (*hw == ':' || *hw == '\x0') 403 c101_run(irq, ram); 404 405 if (*hw == '\x0') 406 return first_card ? 0 : -EINVAL; 407 } while (*hw++ == ':'); 408 409 pr_err("invalid hardware parameters\n"); 410 return first_card ? 0 : -EINVAL; 411 } 412 413 static void __exit c101_cleanup(void) 414 { 415 card_t *card = first_card; 416 417 while (card) { 418 card_t *ptr = card; 419 420 card = card->next_card; 421 unregister_hdlc_device(port_to_dev(ptr)); 422 c101_destroy_card(ptr); 423 } 424 } 425 426 module_init(c101_init); 427 module_exit(c101_cleanup); 428 429 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>"); 430 MODULE_DESCRIPTION("Moxa C101 serial port driver"); 431 MODULE_LICENSE("GPL v2"); 432 module_param(hw, charp, 0444); 433 MODULE_PARM_DESC(hw, "irq,ram:irq,..."); 434