1d1a890faSShreyas Bhatewara /*
2d1a890faSShreyas Bhatewara  * Linux driver for VMware's vmxnet3 ethernet NIC.
3d1a890faSShreyas Bhatewara  *
4d1a890faSShreyas Bhatewara  * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
5d1a890faSShreyas Bhatewara  *
6d1a890faSShreyas Bhatewara  * This program is free software; you can redistribute it and/or modify it
7d1a890faSShreyas Bhatewara  * under the terms of the GNU General Public License as published by the
8d1a890faSShreyas Bhatewara  * Free Software Foundation; version 2 of the License and no later version.
9d1a890faSShreyas Bhatewara  *
10d1a890faSShreyas Bhatewara  * This program is distributed in the hope that it will be useful, but
11d1a890faSShreyas Bhatewara  * WITHOUT ANY WARRANTY; without even the implied warranty of
12d1a890faSShreyas Bhatewara  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13d1a890faSShreyas Bhatewara  * NON INFRINGEMENT.  See the GNU General Public License for more
14d1a890faSShreyas Bhatewara  * details.
15d1a890faSShreyas Bhatewara  *
16d1a890faSShreyas Bhatewara  * You should have received a copy of the GNU General Public License
17d1a890faSShreyas Bhatewara  * along with this program; if not, write to the Free Software
18d1a890faSShreyas Bhatewara  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19d1a890faSShreyas Bhatewara  *
20d1a890faSShreyas Bhatewara  * The full GNU General Public License is included in this distribution in
21d1a890faSShreyas Bhatewara  * the file called "COPYING".
22d1a890faSShreyas Bhatewara  *
23d1a890faSShreyas Bhatewara  * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
24d1a890faSShreyas Bhatewara  *
25d1a890faSShreyas Bhatewara  */
26d1a890faSShreyas Bhatewara 
27d1a890faSShreyas Bhatewara #ifndef _VMXNET3_INT_H
28d1a890faSShreyas Bhatewara #define _VMXNET3_INT_H
29d1a890faSShreyas Bhatewara 
3072e85c45SJesse Gross #include <linux/bitops.h>
31d1a890faSShreyas Bhatewara #include <linux/ethtool.h>
32d1a890faSShreyas Bhatewara #include <linux/delay.h>
33d1a890faSShreyas Bhatewara #include <linux/netdevice.h>
34d1a890faSShreyas Bhatewara #include <linux/pci.h>
35d1a890faSShreyas Bhatewara #include <linux/compiler.h>
36d1a890faSShreyas Bhatewara #include <linux/slab.h>
37d1a890faSShreyas Bhatewara #include <linux/spinlock.h>
38d1a890faSShreyas Bhatewara #include <linux/ioport.h>
39d1a890faSShreyas Bhatewara #include <linux/highmem.h>
40d1a890faSShreyas Bhatewara #include <linux/init.h>
41d1a890faSShreyas Bhatewara #include <linux/timer.h>
42d1a890faSShreyas Bhatewara #include <linux/skbuff.h>
43d1a890faSShreyas Bhatewara #include <linux/interrupt.h>
44d1a890faSShreyas Bhatewara #include <linux/workqueue.h>
45d1a890faSShreyas Bhatewara #include <linux/uaccess.h>
46d1a890faSShreyas Bhatewara #include <asm/dma.h>
47d1a890faSShreyas Bhatewara #include <asm/page.h>
48d1a890faSShreyas Bhatewara 
49d1a890faSShreyas Bhatewara #include <linux/tcp.h>
50d1a890faSShreyas Bhatewara #include <linux/udp.h>
51d1a890faSShreyas Bhatewara #include <linux/ip.h>
52d1a890faSShreyas Bhatewara #include <linux/ipv6.h>
53d1a890faSShreyas Bhatewara #include <linux/in.h>
54d1a890faSShreyas Bhatewara #include <linux/etherdevice.h>
55d1a890faSShreyas Bhatewara #include <asm/checksum.h>
56d1a890faSShreyas Bhatewara #include <linux/if_vlan.h>
57d1a890faSShreyas Bhatewara #include <linux/if_arp.h>
58d1a890faSShreyas Bhatewara #include <linux/inetdevice.h>
59d1a890faSShreyas Bhatewara 
60d1a890faSShreyas Bhatewara #include "vmxnet3_defs.h"
61d1a890faSShreyas Bhatewara 
62d1a890faSShreyas Bhatewara #ifdef DEBUG
63d1a890faSShreyas Bhatewara # define VMXNET3_DRIVER_VERSION_REPORT VMXNET3_DRIVER_VERSION_STRING"-NAPI(debug)"
64d1a890faSShreyas Bhatewara #else
65d1a890faSShreyas Bhatewara # define VMXNET3_DRIVER_VERSION_REPORT VMXNET3_DRIVER_VERSION_STRING"-NAPI"
66d1a890faSShreyas Bhatewara #endif
67d1a890faSShreyas Bhatewara 
68d1a890faSShreyas Bhatewara 
69d1a890faSShreyas Bhatewara /*
70d1a890faSShreyas Bhatewara  * Version numbers
71d1a890faSShreyas Bhatewara  */
72e154b639SShreyas Bhatewara #define VMXNET3_DRIVER_VERSION_STRING   "1.1.9.0-k"
73d1a890faSShreyas Bhatewara 
74d1a890faSShreyas Bhatewara /* a 32-bit int, each byte encode a verion number in VMXNET3_DRIVER_VERSION */
75e154b639SShreyas Bhatewara #define VMXNET3_DRIVER_VERSION_NUM      0x01010900
76d1a890faSShreyas Bhatewara 
7709c5088eSShreyas Bhatewara #if defined(CONFIG_PCI_MSI)
7809c5088eSShreyas Bhatewara 	/* RSS only makes sense if MSI-X is supported. */
7909c5088eSShreyas Bhatewara 	#define VMXNET3_RSS
8009c5088eSShreyas Bhatewara #endif
81d1a890faSShreyas Bhatewara 
82d1a890faSShreyas Bhatewara /*
83d1a890faSShreyas Bhatewara  * Capabilities
84d1a890faSShreyas Bhatewara  */
85d1a890faSShreyas Bhatewara 
86d1a890faSShreyas Bhatewara enum {
87d1a890faSShreyas Bhatewara 	VMNET_CAP_SG	        = 0x0001, /* Can do scatter-gather transmits. */
88d1a890faSShreyas Bhatewara 	VMNET_CAP_IP4_CSUM      = 0x0002, /* Can checksum only TCP/UDP over
89d1a890faSShreyas Bhatewara 					   * IPv4 */
90d1a890faSShreyas Bhatewara 	VMNET_CAP_HW_CSUM       = 0x0004, /* Can checksum all packets. */
91d1a890faSShreyas Bhatewara 	VMNET_CAP_HIGH_DMA      = 0x0008, /* Can DMA to high memory. */
92d1a890faSShreyas Bhatewara 	VMNET_CAP_TOE	        = 0x0010, /* Supports TCP/IP offload. */
93d1a890faSShreyas Bhatewara 	VMNET_CAP_TSO	        = 0x0020, /* Supports TCP Segmentation
94d1a890faSShreyas Bhatewara 					   * offload */
95d1a890faSShreyas Bhatewara 	VMNET_CAP_SW_TSO        = 0x0040, /* Supports SW TCP Segmentation */
96d1a890faSShreyas Bhatewara 	VMNET_CAP_VMXNET_APROM  = 0x0080, /* Vmxnet APROM support */
97d1a890faSShreyas Bhatewara 	VMNET_CAP_HW_TX_VLAN    = 0x0100, /* Can we do VLAN tagging in HW */
98d1a890faSShreyas Bhatewara 	VMNET_CAP_HW_RX_VLAN    = 0x0200, /* Can we do VLAN untagging in HW */
99d1a890faSShreyas Bhatewara 	VMNET_CAP_SW_VLAN       = 0x0400, /* VLAN tagging/untagging in SW */
100d1a890faSShreyas Bhatewara 	VMNET_CAP_WAKE_PCKT_RCV = 0x0800, /* Can wake on network packet recv? */
101d1a890faSShreyas Bhatewara 	VMNET_CAP_ENABLE_INT_INLINE = 0x1000,  /* Enable Interrupt Inline */
102d1a890faSShreyas Bhatewara 	VMNET_CAP_ENABLE_HEADER_COPY = 0x2000,  /* copy header for vmkernel */
103d1a890faSShreyas Bhatewara 	VMNET_CAP_TX_CHAIN      = 0x4000, /* Guest can use multiple tx entries
104d1a890faSShreyas Bhatewara 					  * for a pkt */
105d1a890faSShreyas Bhatewara 	VMNET_CAP_RX_CHAIN      = 0x8000, /* pkt can span multiple rx entries */
106d1a890faSShreyas Bhatewara 	VMNET_CAP_LPD           = 0x10000, /* large pkt delivery */
107d1a890faSShreyas Bhatewara 	VMNET_CAP_BPF           = 0x20000, /* BPF Support in VMXNET Virtual HW*/
108d1a890faSShreyas Bhatewara 	VMNET_CAP_SG_SPAN_PAGES = 0x40000, /* Scatter-gather can span multiple*/
109d1a890faSShreyas Bhatewara 					   /* pages transmits */
110d1a890faSShreyas Bhatewara 	VMNET_CAP_IP6_CSUM      = 0x80000, /* Can do IPv6 csum offload. */
111d1a890faSShreyas Bhatewara 	VMNET_CAP_TSO6         = 0x100000, /* TSO seg. offload for IPv6 pkts. */
112d1a890faSShreyas Bhatewara 	VMNET_CAP_TSO256k      = 0x200000, /* Can do TSO seg offload for */
113d1a890faSShreyas Bhatewara 					   /* pkts up to 256kB. */
114d1a890faSShreyas Bhatewara 	VMNET_CAP_UPT          = 0x400000  /* Support UPT */
115d1a890faSShreyas Bhatewara };
116d1a890faSShreyas Bhatewara 
117d1a890faSShreyas Bhatewara /*
118d1a890faSShreyas Bhatewara  * PCI vendor and device IDs.
119d1a890faSShreyas Bhatewara  */
120d1a890faSShreyas Bhatewara #define PCI_VENDOR_ID_VMWARE            0x15AD
121d1a890faSShreyas Bhatewara #define PCI_DEVICE_ID_VMWARE_VMXNET3    0x07B0
122d1a890faSShreyas Bhatewara #define MAX_ETHERNET_CARDS		10
123d1a890faSShreyas Bhatewara #define MAX_PCI_PASSTHRU_DEVICE		6
124d1a890faSShreyas Bhatewara 
125d1a890faSShreyas Bhatewara struct vmxnet3_cmd_ring {
126d1a890faSShreyas Bhatewara 	union Vmxnet3_GenericDesc *base;
127d1a890faSShreyas Bhatewara 	u32		size;
128d1a890faSShreyas Bhatewara 	u32		next2fill;
129d1a890faSShreyas Bhatewara 	u32		next2comp;
130d1a890faSShreyas Bhatewara 	u8		gen;
131d1a890faSShreyas Bhatewara 	dma_addr_t	basePA;
132d1a890faSShreyas Bhatewara };
133d1a890faSShreyas Bhatewara 
134d1a890faSShreyas Bhatewara static inline void
135d1a890faSShreyas Bhatewara vmxnet3_cmd_ring_adv_next2fill(struct vmxnet3_cmd_ring *ring)
136d1a890faSShreyas Bhatewara {
137d1a890faSShreyas Bhatewara 	ring->next2fill++;
138d1a890faSShreyas Bhatewara 	if (unlikely(ring->next2fill == ring->size)) {
139d1a890faSShreyas Bhatewara 		ring->next2fill = 0;
140d1a890faSShreyas Bhatewara 		VMXNET3_FLIP_RING_GEN(ring->gen);
141d1a890faSShreyas Bhatewara 	}
142d1a890faSShreyas Bhatewara }
143d1a890faSShreyas Bhatewara 
144d1a890faSShreyas Bhatewara static inline void
145d1a890faSShreyas Bhatewara vmxnet3_cmd_ring_adv_next2comp(struct vmxnet3_cmd_ring *ring)
146d1a890faSShreyas Bhatewara {
147d1a890faSShreyas Bhatewara 	VMXNET3_INC_RING_IDX_ONLY(ring->next2comp, ring->size);
148d1a890faSShreyas Bhatewara }
149d1a890faSShreyas Bhatewara 
150d1a890faSShreyas Bhatewara static inline int
151d1a890faSShreyas Bhatewara vmxnet3_cmd_ring_desc_avail(struct vmxnet3_cmd_ring *ring)
152d1a890faSShreyas Bhatewara {
153d1a890faSShreyas Bhatewara 	return (ring->next2comp > ring->next2fill ? 0 : ring->size) +
154d1a890faSShreyas Bhatewara 		ring->next2comp - ring->next2fill - 1;
155d1a890faSShreyas Bhatewara }
156d1a890faSShreyas Bhatewara 
157d1a890faSShreyas Bhatewara struct vmxnet3_comp_ring {
158d1a890faSShreyas Bhatewara 	union Vmxnet3_GenericDesc *base;
159d1a890faSShreyas Bhatewara 	u32               size;
160d1a890faSShreyas Bhatewara 	u32               next2proc;
161d1a890faSShreyas Bhatewara 	u8                gen;
162d1a890faSShreyas Bhatewara 	u8                intr_idx;
163d1a890faSShreyas Bhatewara 	dma_addr_t           basePA;
164d1a890faSShreyas Bhatewara };
165d1a890faSShreyas Bhatewara 
166d1a890faSShreyas Bhatewara static inline void
167d1a890faSShreyas Bhatewara vmxnet3_comp_ring_adv_next2proc(struct vmxnet3_comp_ring *ring)
168d1a890faSShreyas Bhatewara {
169d1a890faSShreyas Bhatewara 	ring->next2proc++;
170d1a890faSShreyas Bhatewara 	if (unlikely(ring->next2proc == ring->size)) {
171d1a890faSShreyas Bhatewara 		ring->next2proc = 0;
172d1a890faSShreyas Bhatewara 		VMXNET3_FLIP_RING_GEN(ring->gen);
173d1a890faSShreyas Bhatewara 	}
174d1a890faSShreyas Bhatewara }
175d1a890faSShreyas Bhatewara 
176d1a890faSShreyas Bhatewara struct vmxnet3_tx_data_ring {
177d1a890faSShreyas Bhatewara 	struct Vmxnet3_TxDataDesc *base;
178d1a890faSShreyas Bhatewara 	u32              size;
179d1a890faSShreyas Bhatewara 	dma_addr_t          basePA;
180d1a890faSShreyas Bhatewara };
181d1a890faSShreyas Bhatewara 
182d1a890faSShreyas Bhatewara enum vmxnet3_buf_map_type {
183d1a890faSShreyas Bhatewara 	VMXNET3_MAP_INVALID = 0,
184d1a890faSShreyas Bhatewara 	VMXNET3_MAP_NONE,
185d1a890faSShreyas Bhatewara 	VMXNET3_MAP_SINGLE,
186d1a890faSShreyas Bhatewara 	VMXNET3_MAP_PAGE,
187d1a890faSShreyas Bhatewara };
188d1a890faSShreyas Bhatewara 
189d1a890faSShreyas Bhatewara struct vmxnet3_tx_buf_info {
190d1a890faSShreyas Bhatewara 	u32      map_type;
191d1a890faSShreyas Bhatewara 	u16      len;
192d1a890faSShreyas Bhatewara 	u16      sop_idx;
193d1a890faSShreyas Bhatewara 	dma_addr_t  dma_addr;
194d1a890faSShreyas Bhatewara 	struct sk_buff *skb;
195d1a890faSShreyas Bhatewara };
196d1a890faSShreyas Bhatewara 
197d1a890faSShreyas Bhatewara struct vmxnet3_tq_driver_stats {
198d1a890faSShreyas Bhatewara 	u64 drop_total;     /* # of pkts dropped by the driver, the
199d1a890faSShreyas Bhatewara 				* counters below track droppings due to
200d1a890faSShreyas Bhatewara 				* different reasons
201d1a890faSShreyas Bhatewara 				*/
202d1a890faSShreyas Bhatewara 	u64 drop_too_many_frags;
203d1a890faSShreyas Bhatewara 	u64 drop_oversized_hdr;
204d1a890faSShreyas Bhatewara 	u64 drop_hdr_inspect_err;
205d1a890faSShreyas Bhatewara 	u64 drop_tso;
206d1a890faSShreyas Bhatewara 
207d1a890faSShreyas Bhatewara 	u64 tx_ring_full;
208d1a890faSShreyas Bhatewara 	u64 linearized;         /* # of pkts linearized */
209d1a890faSShreyas Bhatewara 	u64 copy_skb_header;    /* # of times we have to copy skb header */
210d1a890faSShreyas Bhatewara 	u64 oversized_hdr;
211d1a890faSShreyas Bhatewara };
212d1a890faSShreyas Bhatewara 
213d1a890faSShreyas Bhatewara struct vmxnet3_tx_ctx {
214d1a890faSShreyas Bhatewara 	bool   ipv4;
215d1a890faSShreyas Bhatewara 	u16 mss;
216d1a890faSShreyas Bhatewara 	u32 eth_ip_hdr_size; /* only valid for pkts requesting tso or csum
217d1a890faSShreyas Bhatewara 				 * offloading
218d1a890faSShreyas Bhatewara 				 */
219d1a890faSShreyas Bhatewara 	u32 l4_hdr_size;     /* only valid if mss != 0 */
220d1a890faSShreyas Bhatewara 	u32 copy_size;       /* # of bytes copied into the data ring */
221d1a890faSShreyas Bhatewara 	union Vmxnet3_GenericDesc *sop_txd;
222d1a890faSShreyas Bhatewara 	union Vmxnet3_GenericDesc *eop_txd;
223d1a890faSShreyas Bhatewara };
224d1a890faSShreyas Bhatewara 
225d1a890faSShreyas Bhatewara struct vmxnet3_tx_queue {
22609c5088eSShreyas Bhatewara 	char			name[IFNAMSIZ+8]; /* To identify interrupt */
22709c5088eSShreyas Bhatewara 	struct vmxnet3_adapter		*adapter;
228d1a890faSShreyas Bhatewara 	spinlock_t                      tx_lock;
229d1a890faSShreyas Bhatewara 	struct vmxnet3_cmd_ring         tx_ring;
230d1a890faSShreyas Bhatewara 	struct vmxnet3_tx_buf_info      *buf_info;
231d1a890faSShreyas Bhatewara 	struct vmxnet3_tx_data_ring     data_ring;
232d1a890faSShreyas Bhatewara 	struct vmxnet3_comp_ring        comp_ring;
233d1a890faSShreyas Bhatewara 	struct Vmxnet3_TxQueueCtrl      *shared;
234d1a890faSShreyas Bhatewara 	struct vmxnet3_tq_driver_stats  stats;
235d1a890faSShreyas Bhatewara 	bool                            stopped;
236d1a890faSShreyas Bhatewara 	int                             num_stop;  /* # of times the queue is
237d1a890faSShreyas Bhatewara 						    * stopped */
23809c5088eSShreyas Bhatewara 	int				qid;
239d1a890faSShreyas Bhatewara } __attribute__((__aligned__(SMP_CACHE_BYTES)));
240d1a890faSShreyas Bhatewara 
241d1a890faSShreyas Bhatewara enum vmxnet3_rx_buf_type {
242d1a890faSShreyas Bhatewara 	VMXNET3_RX_BUF_NONE = 0,
243d1a890faSShreyas Bhatewara 	VMXNET3_RX_BUF_SKB = 1,
244d1a890faSShreyas Bhatewara 	VMXNET3_RX_BUF_PAGE = 2
245d1a890faSShreyas Bhatewara };
246d1a890faSShreyas Bhatewara 
247d1a890faSShreyas Bhatewara struct vmxnet3_rx_buf_info {
248d1a890faSShreyas Bhatewara 	enum vmxnet3_rx_buf_type buf_type;
249d1a890faSShreyas Bhatewara 	u16     len;
250d1a890faSShreyas Bhatewara 	union {
251d1a890faSShreyas Bhatewara 		struct sk_buff *skb;
252d1a890faSShreyas Bhatewara 		struct page    *page;
253d1a890faSShreyas Bhatewara 	};
254d1a890faSShreyas Bhatewara 	dma_addr_t dma_addr;
255d1a890faSShreyas Bhatewara };
256d1a890faSShreyas Bhatewara 
257d1a890faSShreyas Bhatewara struct vmxnet3_rx_ctx {
258d1a890faSShreyas Bhatewara 	struct sk_buff *skb;
259d1a890faSShreyas Bhatewara 	u32 sop_idx;
260d1a890faSShreyas Bhatewara };
261d1a890faSShreyas Bhatewara 
262d1a890faSShreyas Bhatewara struct vmxnet3_rq_driver_stats {
263d1a890faSShreyas Bhatewara 	u64 drop_total;
264d1a890faSShreyas Bhatewara 	u64 drop_err;
265d1a890faSShreyas Bhatewara 	u64 drop_fcs;
266d1a890faSShreyas Bhatewara 	u64 rx_buf_alloc_failure;
267d1a890faSShreyas Bhatewara };
268d1a890faSShreyas Bhatewara 
269d1a890faSShreyas Bhatewara struct vmxnet3_rx_queue {
27009c5088eSShreyas Bhatewara 	char			name[IFNAMSIZ + 8]; /* To identify interrupt */
27109c5088eSShreyas Bhatewara 	struct vmxnet3_adapter	  *adapter;
27209c5088eSShreyas Bhatewara 	struct napi_struct        napi;
273d1a890faSShreyas Bhatewara 	struct vmxnet3_cmd_ring   rx_ring[2];
274d1a890faSShreyas Bhatewara 	struct vmxnet3_comp_ring  comp_ring;
275d1a890faSShreyas Bhatewara 	struct vmxnet3_rx_ctx     rx_ctx;
276d1a890faSShreyas Bhatewara 	u32 qid;            /* rqID in RCD for buffer from 1st ring */
277d1a890faSShreyas Bhatewara 	u32 qid2;           /* rqID in RCD for buffer from 2nd ring */
278d1a890faSShreyas Bhatewara 	u32 uncommitted[2]; /* # of buffers allocated since last RXPROD
279d1a890faSShreyas Bhatewara 				* update */
280d1a890faSShreyas Bhatewara 	struct vmxnet3_rx_buf_info     *buf_info[2];
281d1a890faSShreyas Bhatewara 	struct Vmxnet3_RxQueueCtrl            *shared;
282d1a890faSShreyas Bhatewara 	struct vmxnet3_rq_driver_stats  stats;
283d1a890faSShreyas Bhatewara } __attribute__((__aligned__(SMP_CACHE_BYTES)));
284d1a890faSShreyas Bhatewara 
28509c5088eSShreyas Bhatewara #define VMXNET3_DEVICE_MAX_TX_QUEUES 8
28609c5088eSShreyas Bhatewara #define VMXNET3_DEVICE_MAX_RX_QUEUES 8   /* Keep this value as a power of 2 */
28709c5088eSShreyas Bhatewara 
28809c5088eSShreyas Bhatewara /* Should be less than UPT1_RSS_MAX_IND_TABLE_SIZE */
28909c5088eSShreyas Bhatewara #define VMXNET3_RSS_IND_TABLE_SIZE (VMXNET3_DEVICE_MAX_RX_QUEUES * 4)
29009c5088eSShreyas Bhatewara 
29109c5088eSShreyas Bhatewara #define VMXNET3_LINUX_MAX_MSIX_VECT     (VMXNET3_DEVICE_MAX_TX_QUEUES + \
29209c5088eSShreyas Bhatewara 					 VMXNET3_DEVICE_MAX_RX_QUEUES + 1)
2937e96fbf2SShreyas Bhatewara #define VMXNET3_LINUX_MIN_MSIX_VECT     2 /* 1 for tx-rx pair and 1 for event */
29409c5088eSShreyas Bhatewara 
295d1a890faSShreyas Bhatewara 
296d1a890faSShreyas Bhatewara struct vmxnet3_intr {
297d1a890faSShreyas Bhatewara 	enum vmxnet3_intr_mask_mode  mask_mode;
298d1a890faSShreyas Bhatewara 	enum vmxnet3_intr_type       type;	/* MSI-X, MSI, or INTx? */
299d1a890faSShreyas Bhatewara 	u8  num_intrs;			/* # of intr vectors */
300d1a890faSShreyas Bhatewara 	u8  event_intr_idx;		/* idx of the intr vector for event */
301d1a890faSShreyas Bhatewara 	u8  mod_levels[VMXNET3_LINUX_MAX_MSIX_VECT]; /* moderation level */
30209c5088eSShreyas Bhatewara 	char	event_msi_vector_name[IFNAMSIZ+11];
303d1a890faSShreyas Bhatewara #ifdef CONFIG_PCI_MSI
304d1a890faSShreyas Bhatewara 	struct msix_entry msix_entries[VMXNET3_LINUX_MAX_MSIX_VECT];
305d1a890faSShreyas Bhatewara #endif
306d1a890faSShreyas Bhatewara };
307d1a890faSShreyas Bhatewara 
30809c5088eSShreyas Bhatewara /* Interrupt sharing schemes, share_intr */
30909c5088eSShreyas Bhatewara #define VMXNET3_INTR_BUDDYSHARE 0    /* Corresponding tx,rx queues share irq */
31009c5088eSShreyas Bhatewara #define VMXNET3_INTR_TXSHARE 1	     /* All tx queues share one irq */
31109c5088eSShreyas Bhatewara #define VMXNET3_INTR_DONTSHARE 2     /* each queue has its own irq */
31209c5088eSShreyas Bhatewara 
31309c5088eSShreyas Bhatewara 
314d1a890faSShreyas Bhatewara #define VMXNET3_STATE_BIT_RESETTING   0
315d1a890faSShreyas Bhatewara #define VMXNET3_STATE_BIT_QUIESCED    1
316d1a890faSShreyas Bhatewara struct vmxnet3_adapter {
31709c5088eSShreyas Bhatewara 	struct vmxnet3_tx_queue		tx_queue[VMXNET3_DEVICE_MAX_TX_QUEUES];
31809c5088eSShreyas Bhatewara 	struct vmxnet3_rx_queue		rx_queue[VMXNET3_DEVICE_MAX_RX_QUEUES];
31972e85c45SJesse Gross 	unsigned long			active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
320d1a890faSShreyas Bhatewara 	struct vmxnet3_intr		intr;
32183d0feffSShreyas Bhatewara 	spinlock_t			cmd_lock;
322d1a890faSShreyas Bhatewara 	struct Vmxnet3_DriverShared	*shared;
323d1a890faSShreyas Bhatewara 	struct Vmxnet3_PMConf		*pm_conf;
32409c5088eSShreyas Bhatewara 	struct Vmxnet3_TxQueueDesc	*tqd_start;     /* all tx queue desc */
32509c5088eSShreyas Bhatewara 	struct Vmxnet3_RxQueueDesc	*rqd_start;	/* all rx queue desc */
326d1a890faSShreyas Bhatewara 	struct net_device		*netdev;
327d1a890faSShreyas Bhatewara 	struct pci_dev			*pdev;
328d1a890faSShreyas Bhatewara 
32981e8e560SHarvey Harrison 	u8			__iomem *hw_addr0; /* for BAR 0 */
33081e8e560SHarvey Harrison 	u8			__iomem *hw_addr1; /* for BAR 1 */
331d1a890faSShreyas Bhatewara 
33209c5088eSShreyas Bhatewara #ifdef VMXNET3_RSS
33309c5088eSShreyas Bhatewara 	struct UPT1_RSSConf		*rss_conf;
33409c5088eSShreyas Bhatewara 	bool				rss;
33509c5088eSShreyas Bhatewara #endif
33609c5088eSShreyas Bhatewara 	u32				num_rx_queues;
33709c5088eSShreyas Bhatewara 	u32				num_tx_queues;
338d1a890faSShreyas Bhatewara 
339d1a890faSShreyas Bhatewara 	/* rx buffer related */
340d1a890faSShreyas Bhatewara 	unsigned			skb_buf_size;
341d1a890faSShreyas Bhatewara 	int		rx_buf_per_pkt;  /* only apply to the 1st ring */
342d1a890faSShreyas Bhatewara 	dma_addr_t			shared_pa;
343d1a890faSShreyas Bhatewara 	dma_addr_t queue_desc_pa;
344d1a890faSShreyas Bhatewara 
345d1a890faSShreyas Bhatewara 	/* Wake-on-LAN */
346d1a890faSShreyas Bhatewara 	u32     wol;
347d1a890faSShreyas Bhatewara 
348d1a890faSShreyas Bhatewara 	/* Link speed */
349d1a890faSShreyas Bhatewara 	u32     link_speed; /* in mbps */
350d1a890faSShreyas Bhatewara 
351d1a890faSShreyas Bhatewara 	u64     tx_timeout_count;
352d1a890faSShreyas Bhatewara 	struct work_struct work;
353d1a890faSShreyas Bhatewara 
354d1a890faSShreyas Bhatewara 	unsigned long  state;    /* VMXNET3_STATE_BIT_xxx */
355d1a890faSShreyas Bhatewara 
356d1a890faSShreyas Bhatewara 	int dev_number;
35709c5088eSShreyas Bhatewara 	int share_intr;
358d1a890faSShreyas Bhatewara };
359d1a890faSShreyas Bhatewara 
360d1a890faSShreyas Bhatewara #define VMXNET3_WRITE_BAR0_REG(adapter, reg, val)  \
361b8744cabSHarvey Harrison 	writel((val), (adapter)->hw_addr0 + (reg))
362d1a890faSShreyas Bhatewara #define VMXNET3_READ_BAR0_REG(adapter, reg)        \
363b8744cabSHarvey Harrison 	readl((adapter)->hw_addr0 + (reg))
364d1a890faSShreyas Bhatewara 
365d1a890faSShreyas Bhatewara #define VMXNET3_WRITE_BAR1_REG(adapter, reg, val)  \
366b8744cabSHarvey Harrison 	writel((val), (adapter)->hw_addr1 + (reg))
367d1a890faSShreyas Bhatewara #define VMXNET3_READ_BAR1_REG(adapter, reg)        \
368b8744cabSHarvey Harrison 	readl((adapter)->hw_addr1 + (reg))
369d1a890faSShreyas Bhatewara 
370d1a890faSShreyas Bhatewara #define VMXNET3_WAKE_QUEUE_THRESHOLD(tq)  (5)
371d1a890faSShreyas Bhatewara #define VMXNET3_RX_ALLOC_THRESHOLD(rq, ring_idx, adapter) \
372d1a890faSShreyas Bhatewara 	((rq)->rx_ring[ring_idx].size >> 3)
373d1a890faSShreyas Bhatewara 
374d1a890faSShreyas Bhatewara #define VMXNET3_GET_ADDR_LO(dma)   ((u32)(dma))
375d1a890faSShreyas Bhatewara #define VMXNET3_GET_ADDR_HI(dma)   ((u32)(((u64)(dma)) >> 32))
376d1a890faSShreyas Bhatewara 
377d1a890faSShreyas Bhatewara /* must be a multiple of VMXNET3_RING_SIZE_ALIGN */
378d1a890faSShreyas Bhatewara #define VMXNET3_DEF_TX_RING_SIZE    512
379d1a890faSShreyas Bhatewara #define VMXNET3_DEF_RX_RING_SIZE    256
380d1a890faSShreyas Bhatewara 
381d1a890faSShreyas Bhatewara #define VMXNET3_MAX_ETH_HDR_SIZE    22
382d1a890faSShreyas Bhatewara #define VMXNET3_MAX_SKB_BUF_SIZE    (3*1024)
383d1a890faSShreyas Bhatewara 
384d1a890faSShreyas Bhatewara int
385d1a890faSShreyas Bhatewara vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter);
386d1a890faSShreyas Bhatewara 
387d1a890faSShreyas Bhatewara int
388d1a890faSShreyas Bhatewara vmxnet3_activate_dev(struct vmxnet3_adapter *adapter);
389d1a890faSShreyas Bhatewara 
390d1a890faSShreyas Bhatewara void
391d1a890faSShreyas Bhatewara vmxnet3_force_close(struct vmxnet3_adapter *adapter);
392d1a890faSShreyas Bhatewara 
393d1a890faSShreyas Bhatewara void
394d1a890faSShreyas Bhatewara vmxnet3_reset_dev(struct vmxnet3_adapter *adapter);
395d1a890faSShreyas Bhatewara 
396d1a890faSShreyas Bhatewara void
39709c5088eSShreyas Bhatewara vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter);
398d1a890faSShreyas Bhatewara 
399d1a890faSShreyas Bhatewara void
40009c5088eSShreyas Bhatewara vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter);
401d1a890faSShreyas Bhatewara 
402d1a890faSShreyas Bhatewara int
403a0d2730cSMichał Mirosław vmxnet3_set_features(struct net_device *netdev, u32 features);
404a0d2730cSMichał Mirosław 
405a0d2730cSMichał Mirosław int
406d1a890faSShreyas Bhatewara vmxnet3_create_queues(struct vmxnet3_adapter *adapter,
407d1a890faSShreyas Bhatewara 		      u32 tx_ring_size, u32 rx_ring_size, u32 rx_ring2_size);
408d1a890faSShreyas Bhatewara 
409d1a890faSShreyas Bhatewara extern void vmxnet3_set_ethtool_ops(struct net_device *netdev);
41095305f6cSstephen hemminger 
41195305f6cSstephen hemminger extern struct rtnl_link_stats64 *
41295305f6cSstephen hemminger vmxnet3_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats);
413d1a890faSShreyas Bhatewara 
414d1a890faSShreyas Bhatewara extern char vmxnet3_driver_name[];
415d1a890faSShreyas Bhatewara #endif
416