1 /* 2 * Linux driver for VMware's vmxnet3 ethernet NIC. 3 * 4 * Copyright (C) 2008-2016, VMware, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; version 2 of the License and no later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 13 * NON INFRINGEMENT. See the GNU General Public License for more 14 * details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * The full GNU General Public License is included in this distribution in 21 * the file called "COPYING". 22 * 23 * Maintained by: pv-drivers@vmware.com 24 * 25 */ 26 27 #include <linux/module.h> 28 #include <net/ip6_checksum.h> 29 30 #include "vmxnet3_int.h" 31 32 char vmxnet3_driver_name[] = "vmxnet3"; 33 #define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver" 34 35 /* 36 * PCI Device ID Table 37 * Last entry must be all 0s 38 */ 39 static const struct pci_device_id vmxnet3_pciid_table[] = { 40 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)}, 41 {0} 42 }; 43 44 MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table); 45 46 static int enable_mq = 1; 47 48 static void 49 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac); 50 51 /* 52 * Enable/Disable the given intr 53 */ 54 static void 55 vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx) 56 { 57 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0); 58 } 59 60 61 static void 62 vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx) 63 { 64 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1); 65 } 66 67 68 /* 69 * Enable/Disable all intrs used by the device 70 */ 71 static void 72 vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter) 73 { 74 int i; 75 76 for (i = 0; i < adapter->intr.num_intrs; i++) 77 vmxnet3_enable_intr(adapter, i); 78 adapter->shared->devRead.intrConf.intrCtrl &= 79 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL); 80 } 81 82 83 static void 84 vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter) 85 { 86 int i; 87 88 adapter->shared->devRead.intrConf.intrCtrl |= 89 cpu_to_le32(VMXNET3_IC_DISABLE_ALL); 90 for (i = 0; i < adapter->intr.num_intrs; i++) 91 vmxnet3_disable_intr(adapter, i); 92 } 93 94 95 static void 96 vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events) 97 { 98 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events); 99 } 100 101 102 static bool 103 vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 104 { 105 return tq->stopped; 106 } 107 108 109 static void 110 vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 111 { 112 tq->stopped = false; 113 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue); 114 } 115 116 117 static void 118 vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 119 { 120 tq->stopped = false; 121 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue)); 122 } 123 124 125 static void 126 vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 127 { 128 tq->stopped = true; 129 tq->num_stop++; 130 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue)); 131 } 132 133 134 /* 135 * Check the link state. This may start or stop the tx queue. 136 */ 137 static void 138 vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue) 139 { 140 u32 ret; 141 int i; 142 unsigned long flags; 143 144 spin_lock_irqsave(&adapter->cmd_lock, flags); 145 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 146 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 147 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 148 149 adapter->link_speed = ret >> 16; 150 if (ret & 1) { /* Link is up. */ 151 netdev_info(adapter->netdev, "NIC Link is Up %d Mbps\n", 152 adapter->link_speed); 153 netif_carrier_on(adapter->netdev); 154 155 if (affectTxQueue) { 156 for (i = 0; i < adapter->num_tx_queues; i++) 157 vmxnet3_tq_start(&adapter->tx_queue[i], 158 adapter); 159 } 160 } else { 161 netdev_info(adapter->netdev, "NIC Link is Down\n"); 162 netif_carrier_off(adapter->netdev); 163 164 if (affectTxQueue) { 165 for (i = 0; i < adapter->num_tx_queues; i++) 166 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter); 167 } 168 } 169 } 170 171 static void 172 vmxnet3_process_events(struct vmxnet3_adapter *adapter) 173 { 174 int i; 175 unsigned long flags; 176 u32 events = le32_to_cpu(adapter->shared->ecr); 177 if (!events) 178 return; 179 180 vmxnet3_ack_events(adapter, events); 181 182 /* Check if link state has changed */ 183 if (events & VMXNET3_ECR_LINK) 184 vmxnet3_check_link(adapter, true); 185 186 /* Check if there is an error on xmit/recv queues */ 187 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 188 spin_lock_irqsave(&adapter->cmd_lock, flags); 189 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 190 VMXNET3_CMD_GET_QUEUE_STATUS); 191 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 192 193 for (i = 0; i < adapter->num_tx_queues; i++) 194 if (adapter->tqd_start[i].status.stopped) 195 dev_err(&adapter->netdev->dev, 196 "%s: tq[%d] error 0x%x\n", 197 adapter->netdev->name, i, le32_to_cpu( 198 adapter->tqd_start[i].status.error)); 199 for (i = 0; i < adapter->num_rx_queues; i++) 200 if (adapter->rqd_start[i].status.stopped) 201 dev_err(&adapter->netdev->dev, 202 "%s: rq[%d] error 0x%x\n", 203 adapter->netdev->name, i, 204 adapter->rqd_start[i].status.error); 205 206 schedule_work(&adapter->work); 207 } 208 } 209 210 #ifdef __BIG_ENDIAN_BITFIELD 211 /* 212 * The device expects the bitfields in shared structures to be written in 213 * little endian. When CPU is big endian, the following routines are used to 214 * correctly read and write into ABI. 215 * The general technique used here is : double word bitfields are defined in 216 * opposite order for big endian architecture. Then before reading them in 217 * driver the complete double word is translated using le32_to_cpu. Similarly 218 * After the driver writes into bitfields, cpu_to_le32 is used to translate the 219 * double words into required format. 220 * In order to avoid touching bits in shared structure more than once, temporary 221 * descriptors are used. These are passed as srcDesc to following functions. 222 */ 223 static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc, 224 struct Vmxnet3_RxDesc *dstDesc) 225 { 226 u32 *src = (u32 *)srcDesc + 2; 227 u32 *dst = (u32 *)dstDesc + 2; 228 dstDesc->addr = le64_to_cpu(srcDesc->addr); 229 *dst = le32_to_cpu(*src); 230 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1); 231 } 232 233 static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc, 234 struct Vmxnet3_TxDesc *dstDesc) 235 { 236 int i; 237 u32 *src = (u32 *)(srcDesc + 1); 238 u32 *dst = (u32 *)(dstDesc + 1); 239 240 /* Working backwards so that the gen bit is set at the end. */ 241 for (i = 2; i > 0; i--) { 242 src--; 243 dst--; 244 *dst = cpu_to_le32(*src); 245 } 246 } 247 248 249 static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc, 250 struct Vmxnet3_RxCompDesc *dstDesc) 251 { 252 int i = 0; 253 u32 *src = (u32 *)srcDesc; 254 u32 *dst = (u32 *)dstDesc; 255 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) { 256 *dst = le32_to_cpu(*src); 257 src++; 258 dst++; 259 } 260 } 261 262 263 /* Used to read bitfield values from double words. */ 264 static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size) 265 { 266 u32 temp = le32_to_cpu(*bitfield); 267 u32 mask = ((1 << size) - 1) << pos; 268 temp &= mask; 269 temp >>= pos; 270 return temp; 271 } 272 273 274 275 #endif /* __BIG_ENDIAN_BITFIELD */ 276 277 #ifdef __BIG_ENDIAN_BITFIELD 278 279 # define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \ 280 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \ 281 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE) 282 # define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \ 283 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \ 284 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE) 285 # define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \ 286 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \ 287 VMXNET3_TCD_GEN_SIZE) 288 # define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \ 289 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE) 290 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \ 291 (dstrcd) = (tmp); \ 292 vmxnet3_RxCompToCPU((rcd), (tmp)); \ 293 } while (0) 294 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \ 295 (dstrxd) = (tmp); \ 296 vmxnet3_RxDescToCPU((rxd), (tmp)); \ 297 } while (0) 298 299 #else 300 301 # define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen) 302 # define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop) 303 # define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen) 304 # define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx) 305 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd) 306 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd) 307 308 #endif /* __BIG_ENDIAN_BITFIELD */ 309 310 311 static void 312 vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi, 313 struct pci_dev *pdev) 314 { 315 if (tbi->map_type == VMXNET3_MAP_SINGLE) 316 dma_unmap_single(&pdev->dev, tbi->dma_addr, tbi->len, 317 PCI_DMA_TODEVICE); 318 else if (tbi->map_type == VMXNET3_MAP_PAGE) 319 dma_unmap_page(&pdev->dev, tbi->dma_addr, tbi->len, 320 PCI_DMA_TODEVICE); 321 else 322 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE); 323 324 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */ 325 } 326 327 328 static int 329 vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq, 330 struct pci_dev *pdev, struct vmxnet3_adapter *adapter) 331 { 332 struct sk_buff *skb; 333 int entries = 0; 334 335 /* no out of order completion */ 336 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp); 337 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1); 338 339 skb = tq->buf_info[eop_idx].skb; 340 BUG_ON(skb == NULL); 341 tq->buf_info[eop_idx].skb = NULL; 342 343 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size); 344 345 while (tq->tx_ring.next2comp != eop_idx) { 346 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp, 347 pdev); 348 349 /* update next2comp w/o tx_lock. Since we are marking more, 350 * instead of less, tx ring entries avail, the worst case is 351 * that the tx routine incorrectly re-queues a pkt due to 352 * insufficient tx ring entries. 353 */ 354 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring); 355 entries++; 356 } 357 358 dev_kfree_skb_any(skb); 359 return entries; 360 } 361 362 363 static int 364 vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq, 365 struct vmxnet3_adapter *adapter) 366 { 367 int completed = 0; 368 union Vmxnet3_GenericDesc *gdesc; 369 370 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; 371 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) { 372 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX( 373 &gdesc->tcd), tq, adapter->pdev, 374 adapter); 375 376 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring); 377 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; 378 } 379 380 if (completed) { 381 spin_lock(&tq->tx_lock); 382 if (unlikely(vmxnet3_tq_stopped(tq, adapter) && 383 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) > 384 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) && 385 netif_carrier_ok(adapter->netdev))) { 386 vmxnet3_tq_wake(tq, adapter); 387 } 388 spin_unlock(&tq->tx_lock); 389 } 390 return completed; 391 } 392 393 394 static void 395 vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq, 396 struct vmxnet3_adapter *adapter) 397 { 398 int i; 399 400 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) { 401 struct vmxnet3_tx_buf_info *tbi; 402 403 tbi = tq->buf_info + tq->tx_ring.next2comp; 404 405 vmxnet3_unmap_tx_buf(tbi, adapter->pdev); 406 if (tbi->skb) { 407 dev_kfree_skb_any(tbi->skb); 408 tbi->skb = NULL; 409 } 410 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring); 411 } 412 413 /* sanity check, verify all buffers are indeed unmapped and freed */ 414 for (i = 0; i < tq->tx_ring.size; i++) { 415 BUG_ON(tq->buf_info[i].skb != NULL || 416 tq->buf_info[i].map_type != VMXNET3_MAP_NONE); 417 } 418 419 tq->tx_ring.gen = VMXNET3_INIT_GEN; 420 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0; 421 422 tq->comp_ring.gen = VMXNET3_INIT_GEN; 423 tq->comp_ring.next2proc = 0; 424 } 425 426 427 static void 428 vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq, 429 struct vmxnet3_adapter *adapter) 430 { 431 if (tq->tx_ring.base) { 432 dma_free_coherent(&adapter->pdev->dev, tq->tx_ring.size * 433 sizeof(struct Vmxnet3_TxDesc), 434 tq->tx_ring.base, tq->tx_ring.basePA); 435 tq->tx_ring.base = NULL; 436 } 437 if (tq->data_ring.base) { 438 dma_free_coherent(&adapter->pdev->dev, 439 tq->data_ring.size * tq->txdata_desc_size, 440 tq->data_ring.base, tq->data_ring.basePA); 441 tq->data_ring.base = NULL; 442 } 443 if (tq->comp_ring.base) { 444 dma_free_coherent(&adapter->pdev->dev, tq->comp_ring.size * 445 sizeof(struct Vmxnet3_TxCompDesc), 446 tq->comp_ring.base, tq->comp_ring.basePA); 447 tq->comp_ring.base = NULL; 448 } 449 if (tq->buf_info) { 450 dma_free_coherent(&adapter->pdev->dev, 451 tq->tx_ring.size * sizeof(tq->buf_info[0]), 452 tq->buf_info, tq->buf_info_pa); 453 tq->buf_info = NULL; 454 } 455 } 456 457 458 /* Destroy all tx queues */ 459 void 460 vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter) 461 { 462 int i; 463 464 for (i = 0; i < adapter->num_tx_queues; i++) 465 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter); 466 } 467 468 469 static void 470 vmxnet3_tq_init(struct vmxnet3_tx_queue *tq, 471 struct vmxnet3_adapter *adapter) 472 { 473 int i; 474 475 /* reset the tx ring contents to 0 and reset the tx ring states */ 476 memset(tq->tx_ring.base, 0, tq->tx_ring.size * 477 sizeof(struct Vmxnet3_TxDesc)); 478 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0; 479 tq->tx_ring.gen = VMXNET3_INIT_GEN; 480 481 memset(tq->data_ring.base, 0, 482 tq->data_ring.size * tq->txdata_desc_size); 483 484 /* reset the tx comp ring contents to 0 and reset comp ring states */ 485 memset(tq->comp_ring.base, 0, tq->comp_ring.size * 486 sizeof(struct Vmxnet3_TxCompDesc)); 487 tq->comp_ring.next2proc = 0; 488 tq->comp_ring.gen = VMXNET3_INIT_GEN; 489 490 /* reset the bookkeeping data */ 491 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size); 492 for (i = 0; i < tq->tx_ring.size; i++) 493 tq->buf_info[i].map_type = VMXNET3_MAP_NONE; 494 495 /* stats are not reset */ 496 } 497 498 499 static int 500 vmxnet3_tq_create(struct vmxnet3_tx_queue *tq, 501 struct vmxnet3_adapter *adapter) 502 { 503 size_t sz; 504 505 BUG_ON(tq->tx_ring.base || tq->data_ring.base || 506 tq->comp_ring.base || tq->buf_info); 507 508 tq->tx_ring.base = dma_alloc_coherent(&adapter->pdev->dev, 509 tq->tx_ring.size * sizeof(struct Vmxnet3_TxDesc), 510 &tq->tx_ring.basePA, GFP_KERNEL); 511 if (!tq->tx_ring.base) { 512 netdev_err(adapter->netdev, "failed to allocate tx ring\n"); 513 goto err; 514 } 515 516 tq->data_ring.base = dma_alloc_coherent(&adapter->pdev->dev, 517 tq->data_ring.size * tq->txdata_desc_size, 518 &tq->data_ring.basePA, GFP_KERNEL); 519 if (!tq->data_ring.base) { 520 netdev_err(adapter->netdev, "failed to allocate tx data ring\n"); 521 goto err; 522 } 523 524 tq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, 525 tq->comp_ring.size * sizeof(struct Vmxnet3_TxCompDesc), 526 &tq->comp_ring.basePA, GFP_KERNEL); 527 if (!tq->comp_ring.base) { 528 netdev_err(adapter->netdev, "failed to allocate tx comp ring\n"); 529 goto err; 530 } 531 532 sz = tq->tx_ring.size * sizeof(tq->buf_info[0]); 533 tq->buf_info = dma_zalloc_coherent(&adapter->pdev->dev, sz, 534 &tq->buf_info_pa, GFP_KERNEL); 535 if (!tq->buf_info) 536 goto err; 537 538 return 0; 539 540 err: 541 vmxnet3_tq_destroy(tq, adapter); 542 return -ENOMEM; 543 } 544 545 static void 546 vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter) 547 { 548 int i; 549 550 for (i = 0; i < adapter->num_tx_queues; i++) 551 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter); 552 } 553 554 /* 555 * starting from ring->next2fill, allocate rx buffers for the given ring 556 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers 557 * are allocated or allocation fails 558 */ 559 560 static int 561 vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx, 562 int num_to_alloc, struct vmxnet3_adapter *adapter) 563 { 564 int num_allocated = 0; 565 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx]; 566 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx]; 567 u32 val; 568 569 while (num_allocated <= num_to_alloc) { 570 struct vmxnet3_rx_buf_info *rbi; 571 union Vmxnet3_GenericDesc *gd; 572 573 rbi = rbi_base + ring->next2fill; 574 gd = ring->base + ring->next2fill; 575 576 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) { 577 if (rbi->skb == NULL) { 578 rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev, 579 rbi->len, 580 GFP_KERNEL); 581 if (unlikely(rbi->skb == NULL)) { 582 rq->stats.rx_buf_alloc_failure++; 583 break; 584 } 585 586 rbi->dma_addr = dma_map_single( 587 &adapter->pdev->dev, 588 rbi->skb->data, rbi->len, 589 PCI_DMA_FROMDEVICE); 590 if (dma_mapping_error(&adapter->pdev->dev, 591 rbi->dma_addr)) { 592 dev_kfree_skb_any(rbi->skb); 593 rq->stats.rx_buf_alloc_failure++; 594 break; 595 } 596 } else { 597 /* rx buffer skipped by the device */ 598 } 599 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT; 600 } else { 601 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE || 602 rbi->len != PAGE_SIZE); 603 604 if (rbi->page == NULL) { 605 rbi->page = alloc_page(GFP_ATOMIC); 606 if (unlikely(rbi->page == NULL)) { 607 rq->stats.rx_buf_alloc_failure++; 608 break; 609 } 610 rbi->dma_addr = dma_map_page( 611 &adapter->pdev->dev, 612 rbi->page, 0, PAGE_SIZE, 613 PCI_DMA_FROMDEVICE); 614 if (dma_mapping_error(&adapter->pdev->dev, 615 rbi->dma_addr)) { 616 put_page(rbi->page); 617 rq->stats.rx_buf_alloc_failure++; 618 break; 619 } 620 } else { 621 /* rx buffers skipped by the device */ 622 } 623 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT; 624 } 625 626 gd->rxd.addr = cpu_to_le64(rbi->dma_addr); 627 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT) 628 | val | rbi->len); 629 630 /* Fill the last buffer but dont mark it ready, or else the 631 * device will think that the queue is full */ 632 if (num_allocated == num_to_alloc) 633 break; 634 635 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT); 636 num_allocated++; 637 vmxnet3_cmd_ring_adv_next2fill(ring); 638 } 639 640 netdev_dbg(adapter->netdev, 641 "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n", 642 num_allocated, ring->next2fill, ring->next2comp); 643 644 /* so that the device can distinguish a full ring and an empty ring */ 645 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp); 646 647 return num_allocated; 648 } 649 650 651 static void 652 vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd, 653 struct vmxnet3_rx_buf_info *rbi) 654 { 655 struct skb_frag_struct *frag = skb_shinfo(skb)->frags + 656 skb_shinfo(skb)->nr_frags; 657 658 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS); 659 660 __skb_frag_set_page(frag, rbi->page); 661 frag->page_offset = 0; 662 skb_frag_size_set(frag, rcd->len); 663 skb->data_len += rcd->len; 664 skb->truesize += PAGE_SIZE; 665 skb_shinfo(skb)->nr_frags++; 666 } 667 668 669 static int 670 vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx, 671 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev, 672 struct vmxnet3_adapter *adapter) 673 { 674 u32 dw2, len; 675 unsigned long buf_offset; 676 int i; 677 union Vmxnet3_GenericDesc *gdesc; 678 struct vmxnet3_tx_buf_info *tbi = NULL; 679 680 BUG_ON(ctx->copy_size > skb_headlen(skb)); 681 682 /* use the previous gen bit for the SOP desc */ 683 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT; 684 685 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill; 686 gdesc = ctx->sop_txd; /* both loops below can be skipped */ 687 688 /* no need to map the buffer if headers are copied */ 689 if (ctx->copy_size) { 690 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA + 691 tq->tx_ring.next2fill * 692 tq->txdata_desc_size); 693 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size); 694 ctx->sop_txd->dword[3] = 0; 695 696 tbi = tq->buf_info + tq->tx_ring.next2fill; 697 tbi->map_type = VMXNET3_MAP_NONE; 698 699 netdev_dbg(adapter->netdev, 700 "txd[%u]: 0x%Lx 0x%x 0x%x\n", 701 tq->tx_ring.next2fill, 702 le64_to_cpu(ctx->sop_txd->txd.addr), 703 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]); 704 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 705 706 /* use the right gen for non-SOP desc */ 707 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 708 } 709 710 /* linear part can use multiple tx desc if it's big */ 711 len = skb_headlen(skb) - ctx->copy_size; 712 buf_offset = ctx->copy_size; 713 while (len) { 714 u32 buf_size; 715 716 if (len < VMXNET3_MAX_TX_BUF_SIZE) { 717 buf_size = len; 718 dw2 |= len; 719 } else { 720 buf_size = VMXNET3_MAX_TX_BUF_SIZE; 721 /* spec says that for TxDesc.len, 0 == 2^14 */ 722 } 723 724 tbi = tq->buf_info + tq->tx_ring.next2fill; 725 tbi->map_type = VMXNET3_MAP_SINGLE; 726 tbi->dma_addr = dma_map_single(&adapter->pdev->dev, 727 skb->data + buf_offset, buf_size, 728 PCI_DMA_TODEVICE); 729 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr)) 730 return -EFAULT; 731 732 tbi->len = buf_size; 733 734 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; 735 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); 736 737 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); 738 gdesc->dword[2] = cpu_to_le32(dw2); 739 gdesc->dword[3] = 0; 740 741 netdev_dbg(adapter->netdev, 742 "txd[%u]: 0x%Lx 0x%x 0x%x\n", 743 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), 744 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); 745 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 746 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 747 748 len -= buf_size; 749 buf_offset += buf_size; 750 } 751 752 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 753 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 754 u32 buf_size; 755 756 buf_offset = 0; 757 len = skb_frag_size(frag); 758 while (len) { 759 tbi = tq->buf_info + tq->tx_ring.next2fill; 760 if (len < VMXNET3_MAX_TX_BUF_SIZE) { 761 buf_size = len; 762 dw2 |= len; 763 } else { 764 buf_size = VMXNET3_MAX_TX_BUF_SIZE; 765 /* spec says that for TxDesc.len, 0 == 2^14 */ 766 } 767 tbi->map_type = VMXNET3_MAP_PAGE; 768 tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag, 769 buf_offset, buf_size, 770 DMA_TO_DEVICE); 771 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr)) 772 return -EFAULT; 773 774 tbi->len = buf_size; 775 776 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; 777 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); 778 779 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); 780 gdesc->dword[2] = cpu_to_le32(dw2); 781 gdesc->dword[3] = 0; 782 783 netdev_dbg(adapter->netdev, 784 "txd[%u]: 0x%llx %u %u\n", 785 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), 786 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); 787 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 788 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 789 790 len -= buf_size; 791 buf_offset += buf_size; 792 } 793 } 794 795 ctx->eop_txd = gdesc; 796 797 /* set the last buf_info for the pkt */ 798 tbi->skb = skb; 799 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base; 800 801 return 0; 802 } 803 804 805 /* Init all tx queues */ 806 static void 807 vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter) 808 { 809 int i; 810 811 for (i = 0; i < adapter->num_tx_queues; i++) 812 vmxnet3_tq_init(&adapter->tx_queue[i], adapter); 813 } 814 815 816 /* 817 * parse relevant protocol headers: 818 * For a tso pkt, relevant headers are L2/3/4 including options 819 * For a pkt requesting csum offloading, they are L2/3 and may include L4 820 * if it's a TCP/UDP pkt 821 * 822 * Returns: 823 * -1: error happens during parsing 824 * 0: protocol headers parsed, but too big to be copied 825 * 1: protocol headers parsed and copied 826 * 827 * Other effects: 828 * 1. related *ctx fields are updated. 829 * 2. ctx->copy_size is # of bytes copied 830 * 3. the portion to be copied is guaranteed to be in the linear part 831 * 832 */ 833 static int 834 vmxnet3_parse_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 835 struct vmxnet3_tx_ctx *ctx, 836 struct vmxnet3_adapter *adapter) 837 { 838 u8 protocol = 0; 839 840 if (ctx->mss) { /* TSO */ 841 ctx->eth_ip_hdr_size = skb_transport_offset(skb); 842 ctx->l4_hdr_size = tcp_hdrlen(skb); 843 ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size; 844 } else { 845 if (skb->ip_summed == CHECKSUM_PARTIAL) { 846 ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb); 847 848 if (ctx->ipv4) { 849 const struct iphdr *iph = ip_hdr(skb); 850 851 protocol = iph->protocol; 852 } else if (ctx->ipv6) { 853 const struct ipv6hdr *ipv6h = ipv6_hdr(skb); 854 855 protocol = ipv6h->nexthdr; 856 } 857 858 switch (protocol) { 859 case IPPROTO_TCP: 860 ctx->l4_hdr_size = tcp_hdrlen(skb); 861 break; 862 case IPPROTO_UDP: 863 ctx->l4_hdr_size = sizeof(struct udphdr); 864 break; 865 default: 866 ctx->l4_hdr_size = 0; 867 break; 868 } 869 870 ctx->copy_size = min(ctx->eth_ip_hdr_size + 871 ctx->l4_hdr_size, skb->len); 872 } else { 873 ctx->eth_ip_hdr_size = 0; 874 ctx->l4_hdr_size = 0; 875 /* copy as much as allowed */ 876 ctx->copy_size = min_t(unsigned int, 877 tq->txdata_desc_size, 878 skb_headlen(skb)); 879 } 880 881 if (skb->len <= VMXNET3_HDR_COPY_SIZE) 882 ctx->copy_size = skb->len; 883 884 /* make sure headers are accessible directly */ 885 if (unlikely(!pskb_may_pull(skb, ctx->copy_size))) 886 goto err; 887 } 888 889 if (unlikely(ctx->copy_size > tq->txdata_desc_size)) { 890 tq->stats.oversized_hdr++; 891 ctx->copy_size = 0; 892 return 0; 893 } 894 895 return 1; 896 err: 897 return -1; 898 } 899 900 /* 901 * copy relevant protocol headers to the transmit ring: 902 * For a tso pkt, relevant headers are L2/3/4 including options 903 * For a pkt requesting csum offloading, they are L2/3 and may include L4 904 * if it's a TCP/UDP pkt 905 * 906 * 907 * Note that this requires that vmxnet3_parse_hdr be called first to set the 908 * appropriate bits in ctx first 909 */ 910 static void 911 vmxnet3_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 912 struct vmxnet3_tx_ctx *ctx, 913 struct vmxnet3_adapter *adapter) 914 { 915 struct Vmxnet3_TxDataDesc *tdd; 916 917 tdd = (struct Vmxnet3_TxDataDesc *)((u8 *)tq->data_ring.base + 918 tq->tx_ring.next2fill * 919 tq->txdata_desc_size); 920 921 memcpy(tdd->data, skb->data, ctx->copy_size); 922 netdev_dbg(adapter->netdev, 923 "copy %u bytes to dataRing[%u]\n", 924 ctx->copy_size, tq->tx_ring.next2fill); 925 } 926 927 928 static void 929 vmxnet3_prepare_tso(struct sk_buff *skb, 930 struct vmxnet3_tx_ctx *ctx) 931 { 932 struct tcphdr *tcph = tcp_hdr(skb); 933 934 if (ctx->ipv4) { 935 struct iphdr *iph = ip_hdr(skb); 936 937 iph->check = 0; 938 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0, 939 IPPROTO_TCP, 0); 940 } else if (ctx->ipv6) { 941 struct ipv6hdr *iph = ipv6_hdr(skb); 942 943 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0, 944 IPPROTO_TCP, 0); 945 } 946 } 947 948 static int txd_estimate(const struct sk_buff *skb) 949 { 950 int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1; 951 int i; 952 953 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 954 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 955 956 count += VMXNET3_TXD_NEEDED(skb_frag_size(frag)); 957 } 958 return count; 959 } 960 961 /* 962 * Transmits a pkt thru a given tq 963 * Returns: 964 * NETDEV_TX_OK: descriptors are setup successfully 965 * NETDEV_TX_OK: error occurred, the pkt is dropped 966 * NETDEV_TX_BUSY: tx ring is full, queue is stopped 967 * 968 * Side-effects: 969 * 1. tx ring may be changed 970 * 2. tq stats may be updated accordingly 971 * 3. shared->txNumDeferred may be updated 972 */ 973 974 static int 975 vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 976 struct vmxnet3_adapter *adapter, struct net_device *netdev) 977 { 978 int ret; 979 u32 count; 980 int num_pkts; 981 int tx_num_deferred; 982 unsigned long flags; 983 struct vmxnet3_tx_ctx ctx; 984 union Vmxnet3_GenericDesc *gdesc; 985 #ifdef __BIG_ENDIAN_BITFIELD 986 /* Use temporary descriptor to avoid touching bits multiple times */ 987 union Vmxnet3_GenericDesc tempTxDesc; 988 #endif 989 990 count = txd_estimate(skb); 991 992 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP)); 993 ctx.ipv6 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IPV6)); 994 995 ctx.mss = skb_shinfo(skb)->gso_size; 996 if (ctx.mss) { 997 if (skb_header_cloned(skb)) { 998 if (unlikely(pskb_expand_head(skb, 0, 0, 999 GFP_ATOMIC) != 0)) { 1000 tq->stats.drop_tso++; 1001 goto drop_pkt; 1002 } 1003 tq->stats.copy_skb_header++; 1004 } 1005 vmxnet3_prepare_tso(skb, &ctx); 1006 } else { 1007 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) { 1008 1009 /* non-tso pkts must not use more than 1010 * VMXNET3_MAX_TXD_PER_PKT entries 1011 */ 1012 if (skb_linearize(skb) != 0) { 1013 tq->stats.drop_too_many_frags++; 1014 goto drop_pkt; 1015 } 1016 tq->stats.linearized++; 1017 1018 /* recalculate the # of descriptors to use */ 1019 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1; 1020 } 1021 } 1022 1023 ret = vmxnet3_parse_hdr(skb, tq, &ctx, adapter); 1024 if (ret >= 0) { 1025 BUG_ON(ret <= 0 && ctx.copy_size != 0); 1026 /* hdrs parsed, check against other limits */ 1027 if (ctx.mss) { 1028 if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size > 1029 VMXNET3_MAX_TX_BUF_SIZE)) { 1030 tq->stats.drop_oversized_hdr++; 1031 goto drop_pkt; 1032 } 1033 } else { 1034 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1035 if (unlikely(ctx.eth_ip_hdr_size + 1036 skb->csum_offset > 1037 VMXNET3_MAX_CSUM_OFFSET)) { 1038 tq->stats.drop_oversized_hdr++; 1039 goto drop_pkt; 1040 } 1041 } 1042 } 1043 } else { 1044 tq->stats.drop_hdr_inspect_err++; 1045 goto drop_pkt; 1046 } 1047 1048 spin_lock_irqsave(&tq->tx_lock, flags); 1049 1050 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) { 1051 tq->stats.tx_ring_full++; 1052 netdev_dbg(adapter->netdev, 1053 "tx queue stopped on %s, next2comp %u" 1054 " next2fill %u\n", adapter->netdev->name, 1055 tq->tx_ring.next2comp, tq->tx_ring.next2fill); 1056 1057 vmxnet3_tq_stop(tq, adapter); 1058 spin_unlock_irqrestore(&tq->tx_lock, flags); 1059 return NETDEV_TX_BUSY; 1060 } 1061 1062 1063 vmxnet3_copy_hdr(skb, tq, &ctx, adapter); 1064 1065 /* fill tx descs related to addr & len */ 1066 if (vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter)) 1067 goto unlock_drop_pkt; 1068 1069 /* setup the EOP desc */ 1070 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP); 1071 1072 /* setup the SOP desc */ 1073 #ifdef __BIG_ENDIAN_BITFIELD 1074 gdesc = &tempTxDesc; 1075 gdesc->dword[2] = ctx.sop_txd->dword[2]; 1076 gdesc->dword[3] = ctx.sop_txd->dword[3]; 1077 #else 1078 gdesc = ctx.sop_txd; 1079 #endif 1080 tx_num_deferred = le32_to_cpu(tq->shared->txNumDeferred); 1081 if (ctx.mss) { 1082 gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size; 1083 gdesc->txd.om = VMXNET3_OM_TSO; 1084 gdesc->txd.msscof = ctx.mss; 1085 num_pkts = (skb->len - gdesc->txd.hlen + ctx.mss - 1) / ctx.mss; 1086 } else { 1087 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1088 gdesc->txd.hlen = ctx.eth_ip_hdr_size; 1089 gdesc->txd.om = VMXNET3_OM_CSUM; 1090 gdesc->txd.msscof = ctx.eth_ip_hdr_size + 1091 skb->csum_offset; 1092 } else { 1093 gdesc->txd.om = 0; 1094 gdesc->txd.msscof = 0; 1095 } 1096 num_pkts = 1; 1097 } 1098 le32_add_cpu(&tq->shared->txNumDeferred, num_pkts); 1099 tx_num_deferred += num_pkts; 1100 1101 if (skb_vlan_tag_present(skb)) { 1102 gdesc->txd.ti = 1; 1103 gdesc->txd.tci = skb_vlan_tag_get(skb); 1104 } 1105 1106 /* finally flips the GEN bit of the SOP desc. */ 1107 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^ 1108 VMXNET3_TXD_GEN); 1109 #ifdef __BIG_ENDIAN_BITFIELD 1110 /* Finished updating in bitfields of Tx Desc, so write them in original 1111 * place. 1112 */ 1113 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc, 1114 (struct Vmxnet3_TxDesc *)ctx.sop_txd); 1115 gdesc = ctx.sop_txd; 1116 #endif 1117 netdev_dbg(adapter->netdev, 1118 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n", 1119 (u32)(ctx.sop_txd - 1120 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr), 1121 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3])); 1122 1123 spin_unlock_irqrestore(&tq->tx_lock, flags); 1124 1125 if (tx_num_deferred >= le32_to_cpu(tq->shared->txThreshold)) { 1126 tq->shared->txNumDeferred = 0; 1127 VMXNET3_WRITE_BAR0_REG(adapter, 1128 VMXNET3_REG_TXPROD + tq->qid * 8, 1129 tq->tx_ring.next2fill); 1130 } 1131 1132 return NETDEV_TX_OK; 1133 1134 unlock_drop_pkt: 1135 spin_unlock_irqrestore(&tq->tx_lock, flags); 1136 drop_pkt: 1137 tq->stats.drop_total++; 1138 dev_kfree_skb_any(skb); 1139 return NETDEV_TX_OK; 1140 } 1141 1142 1143 static netdev_tx_t 1144 vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 1145 { 1146 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1147 1148 BUG_ON(skb->queue_mapping > adapter->num_tx_queues); 1149 return vmxnet3_tq_xmit(skb, 1150 &adapter->tx_queue[skb->queue_mapping], 1151 adapter, netdev); 1152 } 1153 1154 1155 static void 1156 vmxnet3_rx_csum(struct vmxnet3_adapter *adapter, 1157 struct sk_buff *skb, 1158 union Vmxnet3_GenericDesc *gdesc) 1159 { 1160 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) { 1161 if (gdesc->rcd.v4 && 1162 (le32_to_cpu(gdesc->dword[3]) & 1163 VMXNET3_RCD_CSUM_OK) == VMXNET3_RCD_CSUM_OK) { 1164 skb->ip_summed = CHECKSUM_UNNECESSARY; 1165 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp)); 1166 BUG_ON(gdesc->rcd.frg); 1167 } else if (gdesc->rcd.v6 && (le32_to_cpu(gdesc->dword[3]) & 1168 (1 << VMXNET3_RCD_TUC_SHIFT))) { 1169 skb->ip_summed = CHECKSUM_UNNECESSARY; 1170 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp)); 1171 BUG_ON(gdesc->rcd.frg); 1172 } else { 1173 if (gdesc->rcd.csum) { 1174 skb->csum = htons(gdesc->rcd.csum); 1175 skb->ip_summed = CHECKSUM_PARTIAL; 1176 } else { 1177 skb_checksum_none_assert(skb); 1178 } 1179 } 1180 } else { 1181 skb_checksum_none_assert(skb); 1182 } 1183 } 1184 1185 1186 static void 1187 vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd, 1188 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter) 1189 { 1190 rq->stats.drop_err++; 1191 if (!rcd->fcs) 1192 rq->stats.drop_fcs++; 1193 1194 rq->stats.drop_total++; 1195 1196 /* 1197 * We do not unmap and chain the rx buffer to the skb. 1198 * We basically pretend this buffer is not used and will be recycled 1199 * by vmxnet3_rq_alloc_rx_buf() 1200 */ 1201 1202 /* 1203 * ctx->skb may be NULL if this is the first and the only one 1204 * desc for the pkt 1205 */ 1206 if (ctx->skb) 1207 dev_kfree_skb_irq(ctx->skb); 1208 1209 ctx->skb = NULL; 1210 } 1211 1212 1213 static u32 1214 vmxnet3_get_hdr_len(struct vmxnet3_adapter *adapter, struct sk_buff *skb, 1215 union Vmxnet3_GenericDesc *gdesc) 1216 { 1217 u32 hlen, maplen; 1218 union { 1219 void *ptr; 1220 struct ethhdr *eth; 1221 struct vlan_ethhdr *veth; 1222 struct iphdr *ipv4; 1223 struct ipv6hdr *ipv6; 1224 struct tcphdr *tcp; 1225 } hdr; 1226 BUG_ON(gdesc->rcd.tcp == 0); 1227 1228 maplen = skb_headlen(skb); 1229 if (unlikely(sizeof(struct iphdr) + sizeof(struct tcphdr) > maplen)) 1230 return 0; 1231 1232 if (skb->protocol == cpu_to_be16(ETH_P_8021Q) || 1233 skb->protocol == cpu_to_be16(ETH_P_8021AD)) 1234 hlen = sizeof(struct vlan_ethhdr); 1235 else 1236 hlen = sizeof(struct ethhdr); 1237 1238 hdr.eth = eth_hdr(skb); 1239 if (gdesc->rcd.v4) { 1240 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IP) && 1241 hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IP)); 1242 hdr.ptr += hlen; 1243 BUG_ON(hdr.ipv4->protocol != IPPROTO_TCP); 1244 hlen = hdr.ipv4->ihl << 2; 1245 hdr.ptr += hdr.ipv4->ihl << 2; 1246 } else if (gdesc->rcd.v6) { 1247 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IPV6) && 1248 hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IPV6)); 1249 hdr.ptr += hlen; 1250 /* Use an estimated value, since we also need to handle 1251 * TSO case. 1252 */ 1253 if (hdr.ipv6->nexthdr != IPPROTO_TCP) 1254 return sizeof(struct ipv6hdr) + sizeof(struct tcphdr); 1255 hlen = sizeof(struct ipv6hdr); 1256 hdr.ptr += sizeof(struct ipv6hdr); 1257 } else { 1258 /* Non-IP pkt, dont estimate header length */ 1259 return 0; 1260 } 1261 1262 if (hlen + sizeof(struct tcphdr) > maplen) 1263 return 0; 1264 1265 return (hlen + (hdr.tcp->doff << 2)); 1266 } 1267 1268 static int 1269 vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq, 1270 struct vmxnet3_adapter *adapter, int quota) 1271 { 1272 static const u32 rxprod_reg[2] = { 1273 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2 1274 }; 1275 u32 num_pkts = 0; 1276 bool skip_page_frags = false; 1277 struct Vmxnet3_RxCompDesc *rcd; 1278 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx; 1279 u16 segCnt = 0, mss = 0; 1280 #ifdef __BIG_ENDIAN_BITFIELD 1281 struct Vmxnet3_RxDesc rxCmdDesc; 1282 struct Vmxnet3_RxCompDesc rxComp; 1283 #endif 1284 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, 1285 &rxComp); 1286 while (rcd->gen == rq->comp_ring.gen) { 1287 struct vmxnet3_rx_buf_info *rbi; 1288 struct sk_buff *skb, *new_skb = NULL; 1289 struct page *new_page = NULL; 1290 dma_addr_t new_dma_addr; 1291 int num_to_alloc; 1292 struct Vmxnet3_RxDesc *rxd; 1293 u32 idx, ring_idx; 1294 struct vmxnet3_cmd_ring *ring = NULL; 1295 if (num_pkts >= quota) { 1296 /* we may stop even before we see the EOP desc of 1297 * the current pkt 1298 */ 1299 break; 1300 } 1301 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2 && 1302 rcd->rqID != rq->dataRingQid); 1303 idx = rcd->rxdIdx; 1304 ring_idx = VMXNET3_GET_RING_IDX(adapter, rcd->rqID); 1305 ring = rq->rx_ring + ring_idx; 1306 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd, 1307 &rxCmdDesc); 1308 rbi = rq->buf_info[ring_idx] + idx; 1309 1310 BUG_ON(rxd->addr != rbi->dma_addr || 1311 rxd->len != rbi->len); 1312 1313 if (unlikely(rcd->eop && rcd->err)) { 1314 vmxnet3_rx_error(rq, rcd, ctx, adapter); 1315 goto rcd_done; 1316 } 1317 1318 if (rcd->sop) { /* first buf of the pkt */ 1319 bool rxDataRingUsed; 1320 u16 len; 1321 1322 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD || 1323 (rcd->rqID != rq->qid && 1324 rcd->rqID != rq->dataRingQid)); 1325 1326 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB); 1327 BUG_ON(ctx->skb != NULL || rbi->skb == NULL); 1328 1329 if (unlikely(rcd->len == 0)) { 1330 /* Pretend the rx buffer is skipped. */ 1331 BUG_ON(!(rcd->sop && rcd->eop)); 1332 netdev_dbg(adapter->netdev, 1333 "rxRing[%u][%u] 0 length\n", 1334 ring_idx, idx); 1335 goto rcd_done; 1336 } 1337 1338 skip_page_frags = false; 1339 ctx->skb = rbi->skb; 1340 1341 rxDataRingUsed = 1342 VMXNET3_RX_DATA_RING(adapter, rcd->rqID); 1343 len = rxDataRingUsed ? rcd->len : rbi->len; 1344 new_skb = netdev_alloc_skb_ip_align(adapter->netdev, 1345 len); 1346 if (new_skb == NULL) { 1347 /* Skb allocation failed, do not handover this 1348 * skb to stack. Reuse it. Drop the existing pkt 1349 */ 1350 rq->stats.rx_buf_alloc_failure++; 1351 ctx->skb = NULL; 1352 rq->stats.drop_total++; 1353 skip_page_frags = true; 1354 goto rcd_done; 1355 } 1356 1357 if (rxDataRingUsed) { 1358 size_t sz; 1359 1360 BUG_ON(rcd->len > rq->data_ring.desc_size); 1361 1362 ctx->skb = new_skb; 1363 sz = rcd->rxdIdx * rq->data_ring.desc_size; 1364 memcpy(new_skb->data, 1365 &rq->data_ring.base[sz], rcd->len); 1366 } else { 1367 ctx->skb = rbi->skb; 1368 1369 new_dma_addr = 1370 dma_map_single(&adapter->pdev->dev, 1371 new_skb->data, rbi->len, 1372 PCI_DMA_FROMDEVICE); 1373 if (dma_mapping_error(&adapter->pdev->dev, 1374 new_dma_addr)) { 1375 dev_kfree_skb(new_skb); 1376 /* Skb allocation failed, do not 1377 * handover this skb to stack. Reuse 1378 * it. Drop the existing pkt. 1379 */ 1380 rq->stats.rx_buf_alloc_failure++; 1381 ctx->skb = NULL; 1382 rq->stats.drop_total++; 1383 skip_page_frags = true; 1384 goto rcd_done; 1385 } 1386 1387 dma_unmap_single(&adapter->pdev->dev, 1388 rbi->dma_addr, 1389 rbi->len, 1390 PCI_DMA_FROMDEVICE); 1391 1392 /* Immediate refill */ 1393 rbi->skb = new_skb; 1394 rbi->dma_addr = new_dma_addr; 1395 rxd->addr = cpu_to_le64(rbi->dma_addr); 1396 rxd->len = rbi->len; 1397 } 1398 1399 #ifdef VMXNET3_RSS 1400 if (rcd->rssType != VMXNET3_RCD_RSS_TYPE_NONE && 1401 (adapter->netdev->features & NETIF_F_RXHASH)) 1402 skb_set_hash(ctx->skb, 1403 le32_to_cpu(rcd->rssHash), 1404 PKT_HASH_TYPE_L3); 1405 #endif 1406 skb_put(ctx->skb, rcd->len); 1407 1408 if (VMXNET3_VERSION_GE_2(adapter) && 1409 rcd->type == VMXNET3_CDTYPE_RXCOMP_LRO) { 1410 struct Vmxnet3_RxCompDescExt *rcdlro; 1411 rcdlro = (struct Vmxnet3_RxCompDescExt *)rcd; 1412 1413 segCnt = rcdlro->segCnt; 1414 WARN_ON_ONCE(segCnt == 0); 1415 mss = rcdlro->mss; 1416 if (unlikely(segCnt <= 1)) 1417 segCnt = 0; 1418 } else { 1419 segCnt = 0; 1420 } 1421 } else { 1422 BUG_ON(ctx->skb == NULL && !skip_page_frags); 1423 1424 /* non SOP buffer must be type 1 in most cases */ 1425 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE); 1426 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY); 1427 1428 /* If an sop buffer was dropped, skip all 1429 * following non-sop fragments. They will be reused. 1430 */ 1431 if (skip_page_frags) 1432 goto rcd_done; 1433 1434 if (rcd->len) { 1435 new_page = alloc_page(GFP_ATOMIC); 1436 /* Replacement page frag could not be allocated. 1437 * Reuse this page. Drop the pkt and free the 1438 * skb which contained this page as a frag. Skip 1439 * processing all the following non-sop frags. 1440 */ 1441 if (unlikely(!new_page)) { 1442 rq->stats.rx_buf_alloc_failure++; 1443 dev_kfree_skb(ctx->skb); 1444 ctx->skb = NULL; 1445 skip_page_frags = true; 1446 goto rcd_done; 1447 } 1448 new_dma_addr = dma_map_page(&adapter->pdev->dev, 1449 new_page, 1450 0, PAGE_SIZE, 1451 PCI_DMA_FROMDEVICE); 1452 if (dma_mapping_error(&adapter->pdev->dev, 1453 new_dma_addr)) { 1454 put_page(new_page); 1455 rq->stats.rx_buf_alloc_failure++; 1456 dev_kfree_skb(ctx->skb); 1457 ctx->skb = NULL; 1458 skip_page_frags = true; 1459 goto rcd_done; 1460 } 1461 1462 dma_unmap_page(&adapter->pdev->dev, 1463 rbi->dma_addr, rbi->len, 1464 PCI_DMA_FROMDEVICE); 1465 1466 vmxnet3_append_frag(ctx->skb, rcd, rbi); 1467 1468 /* Immediate refill */ 1469 rbi->page = new_page; 1470 rbi->dma_addr = new_dma_addr; 1471 rxd->addr = cpu_to_le64(rbi->dma_addr); 1472 rxd->len = rbi->len; 1473 } 1474 } 1475 1476 1477 skb = ctx->skb; 1478 if (rcd->eop) { 1479 u32 mtu = adapter->netdev->mtu; 1480 skb->len += skb->data_len; 1481 1482 vmxnet3_rx_csum(adapter, skb, 1483 (union Vmxnet3_GenericDesc *)rcd); 1484 skb->protocol = eth_type_trans(skb, adapter->netdev); 1485 if (!rcd->tcp || 1486 !(adapter->netdev->features & NETIF_F_LRO)) 1487 goto not_lro; 1488 1489 if (segCnt != 0 && mss != 0) { 1490 skb_shinfo(skb)->gso_type = rcd->v4 ? 1491 SKB_GSO_TCPV4 : SKB_GSO_TCPV6; 1492 skb_shinfo(skb)->gso_size = mss; 1493 skb_shinfo(skb)->gso_segs = segCnt; 1494 } else if (segCnt != 0 || skb->len > mtu) { 1495 u32 hlen; 1496 1497 hlen = vmxnet3_get_hdr_len(adapter, skb, 1498 (union Vmxnet3_GenericDesc *)rcd); 1499 if (hlen == 0) 1500 goto not_lro; 1501 1502 skb_shinfo(skb)->gso_type = 1503 rcd->v4 ? SKB_GSO_TCPV4 : SKB_GSO_TCPV6; 1504 if (segCnt != 0) { 1505 skb_shinfo(skb)->gso_segs = segCnt; 1506 skb_shinfo(skb)->gso_size = 1507 DIV_ROUND_UP(skb->len - 1508 hlen, segCnt); 1509 } else { 1510 skb_shinfo(skb)->gso_size = mtu - hlen; 1511 } 1512 } 1513 not_lro: 1514 if (unlikely(rcd->ts)) 1515 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rcd->tci); 1516 1517 if (adapter->netdev->features & NETIF_F_LRO) 1518 netif_receive_skb(skb); 1519 else 1520 napi_gro_receive(&rq->napi, skb); 1521 1522 ctx->skb = NULL; 1523 num_pkts++; 1524 } 1525 1526 rcd_done: 1527 /* device may have skipped some rx descs */ 1528 ring->next2comp = idx; 1529 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring); 1530 ring = rq->rx_ring + ring_idx; 1531 while (num_to_alloc) { 1532 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd, 1533 &rxCmdDesc); 1534 BUG_ON(!rxd->addr); 1535 1536 /* Recv desc is ready to be used by the device */ 1537 rxd->gen = ring->gen; 1538 vmxnet3_cmd_ring_adv_next2fill(ring); 1539 num_to_alloc--; 1540 } 1541 1542 /* if needed, update the register */ 1543 if (unlikely(rq->shared->updateRxProd)) { 1544 VMXNET3_WRITE_BAR0_REG(adapter, 1545 rxprod_reg[ring_idx] + rq->qid * 8, 1546 ring->next2fill); 1547 } 1548 1549 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring); 1550 vmxnet3_getRxComp(rcd, 1551 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp); 1552 } 1553 1554 return num_pkts; 1555 } 1556 1557 1558 static void 1559 vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq, 1560 struct vmxnet3_adapter *adapter) 1561 { 1562 u32 i, ring_idx; 1563 struct Vmxnet3_RxDesc *rxd; 1564 1565 for (ring_idx = 0; ring_idx < 2; ring_idx++) { 1566 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) { 1567 #ifdef __BIG_ENDIAN_BITFIELD 1568 struct Vmxnet3_RxDesc rxDesc; 1569 #endif 1570 vmxnet3_getRxDesc(rxd, 1571 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc); 1572 1573 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD && 1574 rq->buf_info[ring_idx][i].skb) { 1575 dma_unmap_single(&adapter->pdev->dev, rxd->addr, 1576 rxd->len, PCI_DMA_FROMDEVICE); 1577 dev_kfree_skb(rq->buf_info[ring_idx][i].skb); 1578 rq->buf_info[ring_idx][i].skb = NULL; 1579 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY && 1580 rq->buf_info[ring_idx][i].page) { 1581 dma_unmap_page(&adapter->pdev->dev, rxd->addr, 1582 rxd->len, PCI_DMA_FROMDEVICE); 1583 put_page(rq->buf_info[ring_idx][i].page); 1584 rq->buf_info[ring_idx][i].page = NULL; 1585 } 1586 } 1587 1588 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN; 1589 rq->rx_ring[ring_idx].next2fill = 1590 rq->rx_ring[ring_idx].next2comp = 0; 1591 } 1592 1593 rq->comp_ring.gen = VMXNET3_INIT_GEN; 1594 rq->comp_ring.next2proc = 0; 1595 } 1596 1597 1598 static void 1599 vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter) 1600 { 1601 int i; 1602 1603 for (i = 0; i < adapter->num_rx_queues; i++) 1604 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter); 1605 } 1606 1607 1608 static void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq, 1609 struct vmxnet3_adapter *adapter) 1610 { 1611 int i; 1612 int j; 1613 1614 /* all rx buffers must have already been freed */ 1615 for (i = 0; i < 2; i++) { 1616 if (rq->buf_info[i]) { 1617 for (j = 0; j < rq->rx_ring[i].size; j++) 1618 BUG_ON(rq->buf_info[i][j].page != NULL); 1619 } 1620 } 1621 1622 1623 for (i = 0; i < 2; i++) { 1624 if (rq->rx_ring[i].base) { 1625 dma_free_coherent(&adapter->pdev->dev, 1626 rq->rx_ring[i].size 1627 * sizeof(struct Vmxnet3_RxDesc), 1628 rq->rx_ring[i].base, 1629 rq->rx_ring[i].basePA); 1630 rq->rx_ring[i].base = NULL; 1631 } 1632 } 1633 1634 if (rq->data_ring.base) { 1635 dma_free_coherent(&adapter->pdev->dev, 1636 rq->rx_ring[0].size * rq->data_ring.desc_size, 1637 rq->data_ring.base, rq->data_ring.basePA); 1638 rq->data_ring.base = NULL; 1639 } 1640 1641 if (rq->comp_ring.base) { 1642 dma_free_coherent(&adapter->pdev->dev, rq->comp_ring.size 1643 * sizeof(struct Vmxnet3_RxCompDesc), 1644 rq->comp_ring.base, rq->comp_ring.basePA); 1645 rq->comp_ring.base = NULL; 1646 } 1647 1648 if (rq->buf_info[0]) { 1649 size_t sz = sizeof(struct vmxnet3_rx_buf_info) * 1650 (rq->rx_ring[0].size + rq->rx_ring[1].size); 1651 dma_free_coherent(&adapter->pdev->dev, sz, rq->buf_info[0], 1652 rq->buf_info_pa); 1653 rq->buf_info[0] = rq->buf_info[1] = NULL; 1654 } 1655 } 1656 1657 static void 1658 vmxnet3_rq_destroy_all_rxdataring(struct vmxnet3_adapter *adapter) 1659 { 1660 int i; 1661 1662 for (i = 0; i < adapter->num_rx_queues; i++) { 1663 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 1664 1665 if (rq->data_ring.base) { 1666 dma_free_coherent(&adapter->pdev->dev, 1667 (rq->rx_ring[0].size * 1668 rq->data_ring.desc_size), 1669 rq->data_ring.base, 1670 rq->data_ring.basePA); 1671 rq->data_ring.base = NULL; 1672 rq->data_ring.desc_size = 0; 1673 } 1674 } 1675 } 1676 1677 static int 1678 vmxnet3_rq_init(struct vmxnet3_rx_queue *rq, 1679 struct vmxnet3_adapter *adapter) 1680 { 1681 int i; 1682 1683 /* initialize buf_info */ 1684 for (i = 0; i < rq->rx_ring[0].size; i++) { 1685 1686 /* 1st buf for a pkt is skbuff */ 1687 if (i % adapter->rx_buf_per_pkt == 0) { 1688 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB; 1689 rq->buf_info[0][i].len = adapter->skb_buf_size; 1690 } else { /* subsequent bufs for a pkt is frag */ 1691 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE; 1692 rq->buf_info[0][i].len = PAGE_SIZE; 1693 } 1694 } 1695 for (i = 0; i < rq->rx_ring[1].size; i++) { 1696 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE; 1697 rq->buf_info[1][i].len = PAGE_SIZE; 1698 } 1699 1700 /* reset internal state and allocate buffers for both rings */ 1701 for (i = 0; i < 2; i++) { 1702 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0; 1703 1704 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size * 1705 sizeof(struct Vmxnet3_RxDesc)); 1706 rq->rx_ring[i].gen = VMXNET3_INIT_GEN; 1707 } 1708 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1, 1709 adapter) == 0) { 1710 /* at least has 1 rx buffer for the 1st ring */ 1711 return -ENOMEM; 1712 } 1713 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter); 1714 1715 /* reset the comp ring */ 1716 rq->comp_ring.next2proc = 0; 1717 memset(rq->comp_ring.base, 0, rq->comp_ring.size * 1718 sizeof(struct Vmxnet3_RxCompDesc)); 1719 rq->comp_ring.gen = VMXNET3_INIT_GEN; 1720 1721 /* reset rxctx */ 1722 rq->rx_ctx.skb = NULL; 1723 1724 /* stats are not reset */ 1725 return 0; 1726 } 1727 1728 1729 static int 1730 vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter) 1731 { 1732 int i, err = 0; 1733 1734 for (i = 0; i < adapter->num_rx_queues; i++) { 1735 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter); 1736 if (unlikely(err)) { 1737 dev_err(&adapter->netdev->dev, "%s: failed to " 1738 "initialize rx queue%i\n", 1739 adapter->netdev->name, i); 1740 break; 1741 } 1742 } 1743 return err; 1744 1745 } 1746 1747 1748 static int 1749 vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter) 1750 { 1751 int i; 1752 size_t sz; 1753 struct vmxnet3_rx_buf_info *bi; 1754 1755 for (i = 0; i < 2; i++) { 1756 1757 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc); 1758 rq->rx_ring[i].base = dma_alloc_coherent( 1759 &adapter->pdev->dev, sz, 1760 &rq->rx_ring[i].basePA, 1761 GFP_KERNEL); 1762 if (!rq->rx_ring[i].base) { 1763 netdev_err(adapter->netdev, 1764 "failed to allocate rx ring %d\n", i); 1765 goto err; 1766 } 1767 } 1768 1769 if ((adapter->rxdataring_enabled) && (rq->data_ring.desc_size != 0)) { 1770 sz = rq->rx_ring[0].size * rq->data_ring.desc_size; 1771 rq->data_ring.base = 1772 dma_alloc_coherent(&adapter->pdev->dev, sz, 1773 &rq->data_ring.basePA, 1774 GFP_KERNEL); 1775 if (!rq->data_ring.base) { 1776 netdev_err(adapter->netdev, 1777 "rx data ring will be disabled\n"); 1778 adapter->rxdataring_enabled = false; 1779 } 1780 } else { 1781 rq->data_ring.base = NULL; 1782 rq->data_ring.desc_size = 0; 1783 } 1784 1785 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc); 1786 rq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, sz, 1787 &rq->comp_ring.basePA, 1788 GFP_KERNEL); 1789 if (!rq->comp_ring.base) { 1790 netdev_err(adapter->netdev, "failed to allocate rx comp ring\n"); 1791 goto err; 1792 } 1793 1794 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size + 1795 rq->rx_ring[1].size); 1796 bi = dma_zalloc_coherent(&adapter->pdev->dev, sz, &rq->buf_info_pa, 1797 GFP_KERNEL); 1798 if (!bi) 1799 goto err; 1800 1801 rq->buf_info[0] = bi; 1802 rq->buf_info[1] = bi + rq->rx_ring[0].size; 1803 1804 return 0; 1805 1806 err: 1807 vmxnet3_rq_destroy(rq, adapter); 1808 return -ENOMEM; 1809 } 1810 1811 1812 static int 1813 vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter) 1814 { 1815 int i, err = 0; 1816 1817 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter); 1818 1819 for (i = 0; i < adapter->num_rx_queues; i++) { 1820 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter); 1821 if (unlikely(err)) { 1822 dev_err(&adapter->netdev->dev, 1823 "%s: failed to create rx queue%i\n", 1824 adapter->netdev->name, i); 1825 goto err_out; 1826 } 1827 } 1828 1829 if (!adapter->rxdataring_enabled) 1830 vmxnet3_rq_destroy_all_rxdataring(adapter); 1831 1832 return err; 1833 err_out: 1834 vmxnet3_rq_destroy_all(adapter); 1835 return err; 1836 1837 } 1838 1839 /* Multiple queue aware polling function for tx and rx */ 1840 1841 static int 1842 vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget) 1843 { 1844 int rcd_done = 0, i; 1845 if (unlikely(adapter->shared->ecr)) 1846 vmxnet3_process_events(adapter); 1847 for (i = 0; i < adapter->num_tx_queues; i++) 1848 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter); 1849 1850 for (i = 0; i < adapter->num_rx_queues; i++) 1851 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i], 1852 adapter, budget); 1853 return rcd_done; 1854 } 1855 1856 1857 static int 1858 vmxnet3_poll(struct napi_struct *napi, int budget) 1859 { 1860 struct vmxnet3_rx_queue *rx_queue = container_of(napi, 1861 struct vmxnet3_rx_queue, napi); 1862 int rxd_done; 1863 1864 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget); 1865 1866 if (rxd_done < budget) { 1867 napi_complete_done(napi, rxd_done); 1868 vmxnet3_enable_all_intrs(rx_queue->adapter); 1869 } 1870 return rxd_done; 1871 } 1872 1873 /* 1874 * NAPI polling function for MSI-X mode with multiple Rx queues 1875 * Returns the # of the NAPI credit consumed (# of rx descriptors processed) 1876 */ 1877 1878 static int 1879 vmxnet3_poll_rx_only(struct napi_struct *napi, int budget) 1880 { 1881 struct vmxnet3_rx_queue *rq = container_of(napi, 1882 struct vmxnet3_rx_queue, napi); 1883 struct vmxnet3_adapter *adapter = rq->adapter; 1884 int rxd_done; 1885 1886 /* When sharing interrupt with corresponding tx queue, process 1887 * tx completions in that queue as well 1888 */ 1889 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) { 1890 struct vmxnet3_tx_queue *tq = 1891 &adapter->tx_queue[rq - adapter->rx_queue]; 1892 vmxnet3_tq_tx_complete(tq, adapter); 1893 } 1894 1895 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget); 1896 1897 if (rxd_done < budget) { 1898 napi_complete_done(napi, rxd_done); 1899 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx); 1900 } 1901 return rxd_done; 1902 } 1903 1904 1905 #ifdef CONFIG_PCI_MSI 1906 1907 /* 1908 * Handle completion interrupts on tx queues 1909 * Returns whether or not the intr is handled 1910 */ 1911 1912 static irqreturn_t 1913 vmxnet3_msix_tx(int irq, void *data) 1914 { 1915 struct vmxnet3_tx_queue *tq = data; 1916 struct vmxnet3_adapter *adapter = tq->adapter; 1917 1918 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1919 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx); 1920 1921 /* Handle the case where only one irq is allocate for all tx queues */ 1922 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) { 1923 int i; 1924 for (i = 0; i < adapter->num_tx_queues; i++) { 1925 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i]; 1926 vmxnet3_tq_tx_complete(txq, adapter); 1927 } 1928 } else { 1929 vmxnet3_tq_tx_complete(tq, adapter); 1930 } 1931 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx); 1932 1933 return IRQ_HANDLED; 1934 } 1935 1936 1937 /* 1938 * Handle completion interrupts on rx queues. Returns whether or not the 1939 * intr is handled 1940 */ 1941 1942 static irqreturn_t 1943 vmxnet3_msix_rx(int irq, void *data) 1944 { 1945 struct vmxnet3_rx_queue *rq = data; 1946 struct vmxnet3_adapter *adapter = rq->adapter; 1947 1948 /* disable intr if needed */ 1949 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1950 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx); 1951 napi_schedule(&rq->napi); 1952 1953 return IRQ_HANDLED; 1954 } 1955 1956 /* 1957 *---------------------------------------------------------------------------- 1958 * 1959 * vmxnet3_msix_event -- 1960 * 1961 * vmxnet3 msix event intr handler 1962 * 1963 * Result: 1964 * whether or not the intr is handled 1965 * 1966 *---------------------------------------------------------------------------- 1967 */ 1968 1969 static irqreturn_t 1970 vmxnet3_msix_event(int irq, void *data) 1971 { 1972 struct net_device *dev = data; 1973 struct vmxnet3_adapter *adapter = netdev_priv(dev); 1974 1975 /* disable intr if needed */ 1976 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1977 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx); 1978 1979 if (adapter->shared->ecr) 1980 vmxnet3_process_events(adapter); 1981 1982 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx); 1983 1984 return IRQ_HANDLED; 1985 } 1986 1987 #endif /* CONFIG_PCI_MSI */ 1988 1989 1990 /* Interrupt handler for vmxnet3 */ 1991 static irqreturn_t 1992 vmxnet3_intr(int irq, void *dev_id) 1993 { 1994 struct net_device *dev = dev_id; 1995 struct vmxnet3_adapter *adapter = netdev_priv(dev); 1996 1997 if (adapter->intr.type == VMXNET3_IT_INTX) { 1998 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR); 1999 if (unlikely(icr == 0)) 2000 /* not ours */ 2001 return IRQ_NONE; 2002 } 2003 2004 2005 /* disable intr if needed */ 2006 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 2007 vmxnet3_disable_all_intrs(adapter); 2008 2009 napi_schedule(&adapter->rx_queue[0].napi); 2010 2011 return IRQ_HANDLED; 2012 } 2013 2014 #ifdef CONFIG_NET_POLL_CONTROLLER 2015 2016 /* netpoll callback. */ 2017 static void 2018 vmxnet3_netpoll(struct net_device *netdev) 2019 { 2020 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2021 2022 switch (adapter->intr.type) { 2023 #ifdef CONFIG_PCI_MSI 2024 case VMXNET3_IT_MSIX: { 2025 int i; 2026 for (i = 0; i < adapter->num_rx_queues; i++) 2027 vmxnet3_msix_rx(0, &adapter->rx_queue[i]); 2028 break; 2029 } 2030 #endif 2031 case VMXNET3_IT_MSI: 2032 default: 2033 vmxnet3_intr(0, adapter->netdev); 2034 break; 2035 } 2036 2037 } 2038 #endif /* CONFIG_NET_POLL_CONTROLLER */ 2039 2040 static int 2041 vmxnet3_request_irqs(struct vmxnet3_adapter *adapter) 2042 { 2043 struct vmxnet3_intr *intr = &adapter->intr; 2044 int err = 0, i; 2045 int vector = 0; 2046 2047 #ifdef CONFIG_PCI_MSI 2048 if (adapter->intr.type == VMXNET3_IT_MSIX) { 2049 for (i = 0; i < adapter->num_tx_queues; i++) { 2050 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) { 2051 sprintf(adapter->tx_queue[i].name, "%s-tx-%d", 2052 adapter->netdev->name, vector); 2053 err = request_irq( 2054 intr->msix_entries[vector].vector, 2055 vmxnet3_msix_tx, 0, 2056 adapter->tx_queue[i].name, 2057 &adapter->tx_queue[i]); 2058 } else { 2059 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d", 2060 adapter->netdev->name, vector); 2061 } 2062 if (err) { 2063 dev_err(&adapter->netdev->dev, 2064 "Failed to request irq for MSIX, %s, " 2065 "error %d\n", 2066 adapter->tx_queue[i].name, err); 2067 return err; 2068 } 2069 2070 /* Handle the case where only 1 MSIx was allocated for 2071 * all tx queues */ 2072 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) { 2073 for (; i < adapter->num_tx_queues; i++) 2074 adapter->tx_queue[i].comp_ring.intr_idx 2075 = vector; 2076 vector++; 2077 break; 2078 } else { 2079 adapter->tx_queue[i].comp_ring.intr_idx 2080 = vector++; 2081 } 2082 } 2083 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) 2084 vector = 0; 2085 2086 for (i = 0; i < adapter->num_rx_queues; i++) { 2087 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) 2088 sprintf(adapter->rx_queue[i].name, "%s-rx-%d", 2089 adapter->netdev->name, vector); 2090 else 2091 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d", 2092 adapter->netdev->name, vector); 2093 err = request_irq(intr->msix_entries[vector].vector, 2094 vmxnet3_msix_rx, 0, 2095 adapter->rx_queue[i].name, 2096 &(adapter->rx_queue[i])); 2097 if (err) { 2098 netdev_err(adapter->netdev, 2099 "Failed to request irq for MSIX, " 2100 "%s, error %d\n", 2101 adapter->rx_queue[i].name, err); 2102 return err; 2103 } 2104 2105 adapter->rx_queue[i].comp_ring.intr_idx = vector++; 2106 } 2107 2108 sprintf(intr->event_msi_vector_name, "%s-event-%d", 2109 adapter->netdev->name, vector); 2110 err = request_irq(intr->msix_entries[vector].vector, 2111 vmxnet3_msix_event, 0, 2112 intr->event_msi_vector_name, adapter->netdev); 2113 intr->event_intr_idx = vector; 2114 2115 } else if (intr->type == VMXNET3_IT_MSI) { 2116 adapter->num_rx_queues = 1; 2117 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0, 2118 adapter->netdev->name, adapter->netdev); 2119 } else { 2120 #endif 2121 adapter->num_rx_queues = 1; 2122 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 2123 IRQF_SHARED, adapter->netdev->name, 2124 adapter->netdev); 2125 #ifdef CONFIG_PCI_MSI 2126 } 2127 #endif 2128 intr->num_intrs = vector + 1; 2129 if (err) { 2130 netdev_err(adapter->netdev, 2131 "Failed to request irq (intr type:%d), error %d\n", 2132 intr->type, err); 2133 } else { 2134 /* Number of rx queues will not change after this */ 2135 for (i = 0; i < adapter->num_rx_queues; i++) { 2136 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2137 rq->qid = i; 2138 rq->qid2 = i + adapter->num_rx_queues; 2139 rq->dataRingQid = i + 2 * adapter->num_rx_queues; 2140 } 2141 2142 /* init our intr settings */ 2143 for (i = 0; i < intr->num_intrs; i++) 2144 intr->mod_levels[i] = UPT1_IML_ADAPTIVE; 2145 if (adapter->intr.type != VMXNET3_IT_MSIX) { 2146 adapter->intr.event_intr_idx = 0; 2147 for (i = 0; i < adapter->num_tx_queues; i++) 2148 adapter->tx_queue[i].comp_ring.intr_idx = 0; 2149 adapter->rx_queue[0].comp_ring.intr_idx = 0; 2150 } 2151 2152 netdev_info(adapter->netdev, 2153 "intr type %u, mode %u, %u vectors allocated\n", 2154 intr->type, intr->mask_mode, intr->num_intrs); 2155 } 2156 2157 return err; 2158 } 2159 2160 2161 static void 2162 vmxnet3_free_irqs(struct vmxnet3_adapter *adapter) 2163 { 2164 struct vmxnet3_intr *intr = &adapter->intr; 2165 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0); 2166 2167 switch (intr->type) { 2168 #ifdef CONFIG_PCI_MSI 2169 case VMXNET3_IT_MSIX: 2170 { 2171 int i, vector = 0; 2172 2173 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) { 2174 for (i = 0; i < adapter->num_tx_queues; i++) { 2175 free_irq(intr->msix_entries[vector++].vector, 2176 &(adapter->tx_queue[i])); 2177 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) 2178 break; 2179 } 2180 } 2181 2182 for (i = 0; i < adapter->num_rx_queues; i++) { 2183 free_irq(intr->msix_entries[vector++].vector, 2184 &(adapter->rx_queue[i])); 2185 } 2186 2187 free_irq(intr->msix_entries[vector].vector, 2188 adapter->netdev); 2189 BUG_ON(vector >= intr->num_intrs); 2190 break; 2191 } 2192 #endif 2193 case VMXNET3_IT_MSI: 2194 free_irq(adapter->pdev->irq, adapter->netdev); 2195 break; 2196 case VMXNET3_IT_INTX: 2197 free_irq(adapter->pdev->irq, adapter->netdev); 2198 break; 2199 default: 2200 BUG(); 2201 } 2202 } 2203 2204 2205 static void 2206 vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter) 2207 { 2208 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 2209 u16 vid; 2210 2211 /* allow untagged pkts */ 2212 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0); 2213 2214 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2215 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid); 2216 } 2217 2218 2219 static int 2220 vmxnet3_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid) 2221 { 2222 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2223 2224 if (!(netdev->flags & IFF_PROMISC)) { 2225 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 2226 unsigned long flags; 2227 2228 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid); 2229 spin_lock_irqsave(&adapter->cmd_lock, flags); 2230 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2231 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 2232 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2233 } 2234 2235 set_bit(vid, adapter->active_vlans); 2236 2237 return 0; 2238 } 2239 2240 2241 static int 2242 vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid) 2243 { 2244 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2245 2246 if (!(netdev->flags & IFF_PROMISC)) { 2247 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 2248 unsigned long flags; 2249 2250 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid); 2251 spin_lock_irqsave(&adapter->cmd_lock, flags); 2252 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2253 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 2254 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2255 } 2256 2257 clear_bit(vid, adapter->active_vlans); 2258 2259 return 0; 2260 } 2261 2262 2263 static u8 * 2264 vmxnet3_copy_mc(struct net_device *netdev) 2265 { 2266 u8 *buf = NULL; 2267 u32 sz = netdev_mc_count(netdev) * ETH_ALEN; 2268 2269 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */ 2270 if (sz <= 0xffff) { 2271 /* We may be called with BH disabled */ 2272 buf = kmalloc(sz, GFP_ATOMIC); 2273 if (buf) { 2274 struct netdev_hw_addr *ha; 2275 int i = 0; 2276 2277 netdev_for_each_mc_addr(ha, netdev) 2278 memcpy(buf + i++ * ETH_ALEN, ha->addr, 2279 ETH_ALEN); 2280 } 2281 } 2282 return buf; 2283 } 2284 2285 2286 static void 2287 vmxnet3_set_mc(struct net_device *netdev) 2288 { 2289 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2290 unsigned long flags; 2291 struct Vmxnet3_RxFilterConf *rxConf = 2292 &adapter->shared->devRead.rxFilterConf; 2293 u8 *new_table = NULL; 2294 dma_addr_t new_table_pa = 0; 2295 bool new_table_pa_valid = false; 2296 u32 new_mode = VMXNET3_RXM_UCAST; 2297 2298 if (netdev->flags & IFF_PROMISC) { 2299 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 2300 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable)); 2301 2302 new_mode |= VMXNET3_RXM_PROMISC; 2303 } else { 2304 vmxnet3_restore_vlan(adapter); 2305 } 2306 2307 if (netdev->flags & IFF_BROADCAST) 2308 new_mode |= VMXNET3_RXM_BCAST; 2309 2310 if (netdev->flags & IFF_ALLMULTI) 2311 new_mode |= VMXNET3_RXM_ALL_MULTI; 2312 else 2313 if (!netdev_mc_empty(netdev)) { 2314 new_table = vmxnet3_copy_mc(netdev); 2315 if (new_table) { 2316 size_t sz = netdev_mc_count(netdev) * ETH_ALEN; 2317 2318 rxConf->mfTableLen = cpu_to_le16(sz); 2319 new_table_pa = dma_map_single( 2320 &adapter->pdev->dev, 2321 new_table, 2322 sz, 2323 PCI_DMA_TODEVICE); 2324 if (!dma_mapping_error(&adapter->pdev->dev, 2325 new_table_pa)) { 2326 new_mode |= VMXNET3_RXM_MCAST; 2327 new_table_pa_valid = true; 2328 rxConf->mfTablePA = cpu_to_le64( 2329 new_table_pa); 2330 } 2331 } 2332 if (!new_table_pa_valid) { 2333 netdev_info(netdev, 2334 "failed to copy mcast list, setting ALL_MULTI\n"); 2335 new_mode |= VMXNET3_RXM_ALL_MULTI; 2336 } 2337 } 2338 2339 if (!(new_mode & VMXNET3_RXM_MCAST)) { 2340 rxConf->mfTableLen = 0; 2341 rxConf->mfTablePA = 0; 2342 } 2343 2344 spin_lock_irqsave(&adapter->cmd_lock, flags); 2345 if (new_mode != rxConf->rxMode) { 2346 rxConf->rxMode = cpu_to_le32(new_mode); 2347 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2348 VMXNET3_CMD_UPDATE_RX_MODE); 2349 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2350 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 2351 } 2352 2353 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2354 VMXNET3_CMD_UPDATE_MAC_FILTERS); 2355 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2356 2357 if (new_table_pa_valid) 2358 dma_unmap_single(&adapter->pdev->dev, new_table_pa, 2359 rxConf->mfTableLen, PCI_DMA_TODEVICE); 2360 kfree(new_table); 2361 } 2362 2363 void 2364 vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter) 2365 { 2366 int i; 2367 2368 for (i = 0; i < adapter->num_rx_queues; i++) 2369 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter); 2370 } 2371 2372 2373 /* 2374 * Set up driver_shared based on settings in adapter. 2375 */ 2376 2377 static void 2378 vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter) 2379 { 2380 struct Vmxnet3_DriverShared *shared = adapter->shared; 2381 struct Vmxnet3_DSDevRead *devRead = &shared->devRead; 2382 struct Vmxnet3_TxQueueConf *tqc; 2383 struct Vmxnet3_RxQueueConf *rqc; 2384 int i; 2385 2386 memset(shared, 0, sizeof(*shared)); 2387 2388 /* driver settings */ 2389 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC); 2390 devRead->misc.driverInfo.version = cpu_to_le32( 2391 VMXNET3_DRIVER_VERSION_NUM); 2392 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ? 2393 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64); 2394 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 2395 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32( 2396 *((u32 *)&devRead->misc.driverInfo.gos)); 2397 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1); 2398 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1); 2399 2400 devRead->misc.ddPA = cpu_to_le64(adapter->adapter_pa); 2401 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter)); 2402 2403 /* set up feature flags */ 2404 if (adapter->netdev->features & NETIF_F_RXCSUM) 2405 devRead->misc.uptFeatures |= UPT1_F_RXCSUM; 2406 2407 if (adapter->netdev->features & NETIF_F_LRO) { 2408 devRead->misc.uptFeatures |= UPT1_F_LRO; 2409 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS); 2410 } 2411 if (adapter->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 2412 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 2413 2414 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu); 2415 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa); 2416 devRead->misc.queueDescLen = cpu_to_le32( 2417 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 2418 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc)); 2419 2420 /* tx queue settings */ 2421 devRead->misc.numTxQueues = adapter->num_tx_queues; 2422 for (i = 0; i < adapter->num_tx_queues; i++) { 2423 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i]; 2424 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL); 2425 tqc = &adapter->tqd_start[i].conf; 2426 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA); 2427 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA); 2428 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA); 2429 tqc->ddPA = cpu_to_le64(tq->buf_info_pa); 2430 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size); 2431 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size); 2432 tqc->txDataRingDescSize = cpu_to_le32(tq->txdata_desc_size); 2433 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size); 2434 tqc->ddLen = cpu_to_le32( 2435 sizeof(struct vmxnet3_tx_buf_info) * 2436 tqc->txRingSize); 2437 tqc->intrIdx = tq->comp_ring.intr_idx; 2438 } 2439 2440 /* rx queue settings */ 2441 devRead->misc.numRxQueues = adapter->num_rx_queues; 2442 for (i = 0; i < adapter->num_rx_queues; i++) { 2443 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2444 rqc = &adapter->rqd_start[i].conf; 2445 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA); 2446 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA); 2447 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA); 2448 rqc->ddPA = cpu_to_le64(rq->buf_info_pa); 2449 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size); 2450 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size); 2451 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size); 2452 rqc->ddLen = cpu_to_le32( 2453 sizeof(struct vmxnet3_rx_buf_info) * 2454 (rqc->rxRingSize[0] + 2455 rqc->rxRingSize[1])); 2456 rqc->intrIdx = rq->comp_ring.intr_idx; 2457 if (VMXNET3_VERSION_GE_3(adapter)) { 2458 rqc->rxDataRingBasePA = 2459 cpu_to_le64(rq->data_ring.basePA); 2460 rqc->rxDataRingDescSize = 2461 cpu_to_le16(rq->data_ring.desc_size); 2462 } 2463 } 2464 2465 #ifdef VMXNET3_RSS 2466 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf)); 2467 2468 if (adapter->rss) { 2469 struct UPT1_RSSConf *rssConf = adapter->rss_conf; 2470 2471 devRead->misc.uptFeatures |= UPT1_F_RSS; 2472 devRead->misc.numRxQueues = adapter->num_rx_queues; 2473 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 | 2474 UPT1_RSS_HASH_TYPE_IPV4 | 2475 UPT1_RSS_HASH_TYPE_TCP_IPV6 | 2476 UPT1_RSS_HASH_TYPE_IPV6; 2477 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ; 2478 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE; 2479 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE; 2480 netdev_rss_key_fill(rssConf->hashKey, sizeof(rssConf->hashKey)); 2481 2482 for (i = 0; i < rssConf->indTableSize; i++) 2483 rssConf->indTable[i] = ethtool_rxfh_indir_default( 2484 i, adapter->num_rx_queues); 2485 2486 devRead->rssConfDesc.confVer = 1; 2487 devRead->rssConfDesc.confLen = cpu_to_le32(sizeof(*rssConf)); 2488 devRead->rssConfDesc.confPA = 2489 cpu_to_le64(adapter->rss_conf_pa); 2490 } 2491 2492 #endif /* VMXNET3_RSS */ 2493 2494 /* intr settings */ 2495 devRead->intrConf.autoMask = adapter->intr.mask_mode == 2496 VMXNET3_IMM_AUTO; 2497 devRead->intrConf.numIntrs = adapter->intr.num_intrs; 2498 for (i = 0; i < adapter->intr.num_intrs; i++) 2499 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i]; 2500 2501 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx; 2502 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL); 2503 2504 /* rx filter settings */ 2505 devRead->rxFilterConf.rxMode = 0; 2506 vmxnet3_restore_vlan(adapter); 2507 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr); 2508 2509 /* the rest are already zeroed */ 2510 } 2511 2512 static void 2513 vmxnet3_init_coalesce(struct vmxnet3_adapter *adapter) 2514 { 2515 struct Vmxnet3_DriverShared *shared = adapter->shared; 2516 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo; 2517 unsigned long flags; 2518 2519 if (!VMXNET3_VERSION_GE_3(adapter)) 2520 return; 2521 2522 spin_lock_irqsave(&adapter->cmd_lock, flags); 2523 cmdInfo->varConf.confVer = 1; 2524 cmdInfo->varConf.confLen = 2525 cpu_to_le32(sizeof(*adapter->coal_conf)); 2526 cmdInfo->varConf.confPA = cpu_to_le64(adapter->coal_conf_pa); 2527 2528 if (adapter->default_coal_mode) { 2529 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2530 VMXNET3_CMD_GET_COALESCE); 2531 } else { 2532 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2533 VMXNET3_CMD_SET_COALESCE); 2534 } 2535 2536 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2537 } 2538 2539 int 2540 vmxnet3_activate_dev(struct vmxnet3_adapter *adapter) 2541 { 2542 int err, i; 2543 u32 ret; 2544 unsigned long flags; 2545 2546 netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d," 2547 " ring sizes %u %u %u\n", adapter->netdev->name, 2548 adapter->skb_buf_size, adapter->rx_buf_per_pkt, 2549 adapter->tx_queue[0].tx_ring.size, 2550 adapter->rx_queue[0].rx_ring[0].size, 2551 adapter->rx_queue[0].rx_ring[1].size); 2552 2553 vmxnet3_tq_init_all(adapter); 2554 err = vmxnet3_rq_init_all(adapter); 2555 if (err) { 2556 netdev_err(adapter->netdev, 2557 "Failed to init rx queue error %d\n", err); 2558 goto rq_err; 2559 } 2560 2561 err = vmxnet3_request_irqs(adapter); 2562 if (err) { 2563 netdev_err(adapter->netdev, 2564 "Failed to setup irq for error %d\n", err); 2565 goto irq_err; 2566 } 2567 2568 vmxnet3_setup_driver_shared(adapter); 2569 2570 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO( 2571 adapter->shared_pa)); 2572 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI( 2573 adapter->shared_pa)); 2574 spin_lock_irqsave(&adapter->cmd_lock, flags); 2575 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2576 VMXNET3_CMD_ACTIVATE_DEV); 2577 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 2578 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2579 2580 if (ret != 0) { 2581 netdev_err(adapter->netdev, 2582 "Failed to activate dev: error %u\n", ret); 2583 err = -EINVAL; 2584 goto activate_err; 2585 } 2586 2587 vmxnet3_init_coalesce(adapter); 2588 2589 for (i = 0; i < adapter->num_rx_queues; i++) { 2590 VMXNET3_WRITE_BAR0_REG(adapter, 2591 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN, 2592 adapter->rx_queue[i].rx_ring[0].next2fill); 2593 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 + 2594 (i * VMXNET3_REG_ALIGN)), 2595 adapter->rx_queue[i].rx_ring[1].next2fill); 2596 } 2597 2598 /* Apply the rx filter settins last. */ 2599 vmxnet3_set_mc(adapter->netdev); 2600 2601 /* 2602 * Check link state when first activating device. It will start the 2603 * tx queue if the link is up. 2604 */ 2605 vmxnet3_check_link(adapter, true); 2606 for (i = 0; i < adapter->num_rx_queues; i++) 2607 napi_enable(&adapter->rx_queue[i].napi); 2608 vmxnet3_enable_all_intrs(adapter); 2609 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 2610 return 0; 2611 2612 activate_err: 2613 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0); 2614 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0); 2615 vmxnet3_free_irqs(adapter); 2616 irq_err: 2617 rq_err: 2618 /* free up buffers we allocated */ 2619 vmxnet3_rq_cleanup_all(adapter); 2620 return err; 2621 } 2622 2623 2624 void 2625 vmxnet3_reset_dev(struct vmxnet3_adapter *adapter) 2626 { 2627 unsigned long flags; 2628 spin_lock_irqsave(&adapter->cmd_lock, flags); 2629 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 2630 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2631 } 2632 2633 2634 int 2635 vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter) 2636 { 2637 int i; 2638 unsigned long flags; 2639 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state)) 2640 return 0; 2641 2642 2643 spin_lock_irqsave(&adapter->cmd_lock, flags); 2644 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2645 VMXNET3_CMD_QUIESCE_DEV); 2646 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2647 vmxnet3_disable_all_intrs(adapter); 2648 2649 for (i = 0; i < adapter->num_rx_queues; i++) 2650 napi_disable(&adapter->rx_queue[i].napi); 2651 netif_tx_disable(adapter->netdev); 2652 adapter->link_speed = 0; 2653 netif_carrier_off(adapter->netdev); 2654 2655 vmxnet3_tq_cleanup_all(adapter); 2656 vmxnet3_rq_cleanup_all(adapter); 2657 vmxnet3_free_irqs(adapter); 2658 return 0; 2659 } 2660 2661 2662 static void 2663 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac) 2664 { 2665 u32 tmp; 2666 2667 tmp = *(u32 *)mac; 2668 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp); 2669 2670 tmp = (mac[5] << 8) | mac[4]; 2671 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp); 2672 } 2673 2674 2675 static int 2676 vmxnet3_set_mac_addr(struct net_device *netdev, void *p) 2677 { 2678 struct sockaddr *addr = p; 2679 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2680 2681 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 2682 vmxnet3_write_mac_addr(adapter, addr->sa_data); 2683 2684 return 0; 2685 } 2686 2687 2688 /* ==================== initialization and cleanup routines ============ */ 2689 2690 static int 2691 vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64) 2692 { 2693 int err; 2694 unsigned long mmio_start, mmio_len; 2695 struct pci_dev *pdev = adapter->pdev; 2696 2697 err = pci_enable_device(pdev); 2698 if (err) { 2699 dev_err(&pdev->dev, "Failed to enable adapter: error %d\n", err); 2700 return err; 2701 } 2702 2703 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) { 2704 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) { 2705 dev_err(&pdev->dev, 2706 "pci_set_consistent_dma_mask failed\n"); 2707 err = -EIO; 2708 goto err_set_mask; 2709 } 2710 *dma64 = true; 2711 } else { 2712 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) { 2713 dev_err(&pdev->dev, 2714 "pci_set_dma_mask failed\n"); 2715 err = -EIO; 2716 goto err_set_mask; 2717 } 2718 *dma64 = false; 2719 } 2720 2721 err = pci_request_selected_regions(pdev, (1 << 2) - 1, 2722 vmxnet3_driver_name); 2723 if (err) { 2724 dev_err(&pdev->dev, 2725 "Failed to request region for adapter: error %d\n", err); 2726 goto err_set_mask; 2727 } 2728 2729 pci_set_master(pdev); 2730 2731 mmio_start = pci_resource_start(pdev, 0); 2732 mmio_len = pci_resource_len(pdev, 0); 2733 adapter->hw_addr0 = ioremap(mmio_start, mmio_len); 2734 if (!adapter->hw_addr0) { 2735 dev_err(&pdev->dev, "Failed to map bar0\n"); 2736 err = -EIO; 2737 goto err_ioremap; 2738 } 2739 2740 mmio_start = pci_resource_start(pdev, 1); 2741 mmio_len = pci_resource_len(pdev, 1); 2742 adapter->hw_addr1 = ioremap(mmio_start, mmio_len); 2743 if (!adapter->hw_addr1) { 2744 dev_err(&pdev->dev, "Failed to map bar1\n"); 2745 err = -EIO; 2746 goto err_bar1; 2747 } 2748 return 0; 2749 2750 err_bar1: 2751 iounmap(adapter->hw_addr0); 2752 err_ioremap: 2753 pci_release_selected_regions(pdev, (1 << 2) - 1); 2754 err_set_mask: 2755 pci_disable_device(pdev); 2756 return err; 2757 } 2758 2759 2760 static void 2761 vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter) 2762 { 2763 BUG_ON(!adapter->pdev); 2764 2765 iounmap(adapter->hw_addr0); 2766 iounmap(adapter->hw_addr1); 2767 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1); 2768 pci_disable_device(adapter->pdev); 2769 } 2770 2771 2772 static void 2773 vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter) 2774 { 2775 size_t sz, i, ring0_size, ring1_size, comp_size; 2776 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE - 2777 VMXNET3_MAX_ETH_HDR_SIZE) { 2778 adapter->skb_buf_size = adapter->netdev->mtu + 2779 VMXNET3_MAX_ETH_HDR_SIZE; 2780 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE) 2781 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE; 2782 2783 adapter->rx_buf_per_pkt = 1; 2784 } else { 2785 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE; 2786 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE + 2787 VMXNET3_MAX_ETH_HDR_SIZE; 2788 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE; 2789 } 2790 2791 /* 2792 * for simplicity, force the ring0 size to be a multiple of 2793 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN 2794 */ 2795 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN; 2796 ring0_size = adapter->rx_queue[0].rx_ring[0].size; 2797 ring0_size = (ring0_size + sz - 1) / sz * sz; 2798 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE / 2799 sz * sz); 2800 ring1_size = adapter->rx_queue[0].rx_ring[1].size; 2801 ring1_size = (ring1_size + sz - 1) / sz * sz; 2802 ring1_size = min_t(u32, ring1_size, VMXNET3_RX_RING2_MAX_SIZE / 2803 sz * sz); 2804 comp_size = ring0_size + ring1_size; 2805 2806 for (i = 0; i < adapter->num_rx_queues; i++) { 2807 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2808 2809 rq->rx_ring[0].size = ring0_size; 2810 rq->rx_ring[1].size = ring1_size; 2811 rq->comp_ring.size = comp_size; 2812 } 2813 } 2814 2815 2816 int 2817 vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size, 2818 u32 rx_ring_size, u32 rx_ring2_size, 2819 u16 txdata_desc_size, u16 rxdata_desc_size) 2820 { 2821 int err = 0, i; 2822 2823 for (i = 0; i < adapter->num_tx_queues; i++) { 2824 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i]; 2825 tq->tx_ring.size = tx_ring_size; 2826 tq->data_ring.size = tx_ring_size; 2827 tq->comp_ring.size = tx_ring_size; 2828 tq->txdata_desc_size = txdata_desc_size; 2829 tq->shared = &adapter->tqd_start[i].ctrl; 2830 tq->stopped = true; 2831 tq->adapter = adapter; 2832 tq->qid = i; 2833 err = vmxnet3_tq_create(tq, adapter); 2834 /* 2835 * Too late to change num_tx_queues. We cannot do away with 2836 * lesser number of queues than what we asked for 2837 */ 2838 if (err) 2839 goto queue_err; 2840 } 2841 2842 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size; 2843 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size; 2844 vmxnet3_adjust_rx_ring_size(adapter); 2845 2846 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter); 2847 for (i = 0; i < adapter->num_rx_queues; i++) { 2848 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2849 /* qid and qid2 for rx queues will be assigned later when num 2850 * of rx queues is finalized after allocating intrs */ 2851 rq->shared = &adapter->rqd_start[i].ctrl; 2852 rq->adapter = adapter; 2853 rq->data_ring.desc_size = rxdata_desc_size; 2854 err = vmxnet3_rq_create(rq, adapter); 2855 if (err) { 2856 if (i == 0) { 2857 netdev_err(adapter->netdev, 2858 "Could not allocate any rx queues. " 2859 "Aborting.\n"); 2860 goto queue_err; 2861 } else { 2862 netdev_info(adapter->netdev, 2863 "Number of rx queues changed " 2864 "to : %d.\n", i); 2865 adapter->num_rx_queues = i; 2866 err = 0; 2867 break; 2868 } 2869 } 2870 } 2871 2872 if (!adapter->rxdataring_enabled) 2873 vmxnet3_rq_destroy_all_rxdataring(adapter); 2874 2875 return err; 2876 queue_err: 2877 vmxnet3_tq_destroy_all(adapter); 2878 return err; 2879 } 2880 2881 static int 2882 vmxnet3_open(struct net_device *netdev) 2883 { 2884 struct vmxnet3_adapter *adapter; 2885 int err, i; 2886 2887 adapter = netdev_priv(netdev); 2888 2889 for (i = 0; i < adapter->num_tx_queues; i++) 2890 spin_lock_init(&adapter->tx_queue[i].tx_lock); 2891 2892 if (VMXNET3_VERSION_GE_3(adapter)) { 2893 unsigned long flags; 2894 u16 txdata_desc_size; 2895 2896 spin_lock_irqsave(&adapter->cmd_lock, flags); 2897 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2898 VMXNET3_CMD_GET_TXDATA_DESC_SIZE); 2899 txdata_desc_size = VMXNET3_READ_BAR1_REG(adapter, 2900 VMXNET3_REG_CMD); 2901 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2902 2903 if ((txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE) || 2904 (txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE) || 2905 (txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK)) { 2906 adapter->txdata_desc_size = 2907 sizeof(struct Vmxnet3_TxDataDesc); 2908 } else { 2909 adapter->txdata_desc_size = txdata_desc_size; 2910 } 2911 } else { 2912 adapter->txdata_desc_size = sizeof(struct Vmxnet3_TxDataDesc); 2913 } 2914 2915 err = vmxnet3_create_queues(adapter, 2916 adapter->tx_ring_size, 2917 adapter->rx_ring_size, 2918 adapter->rx_ring2_size, 2919 adapter->txdata_desc_size, 2920 adapter->rxdata_desc_size); 2921 if (err) 2922 goto queue_err; 2923 2924 err = vmxnet3_activate_dev(adapter); 2925 if (err) 2926 goto activate_err; 2927 2928 return 0; 2929 2930 activate_err: 2931 vmxnet3_rq_destroy_all(adapter); 2932 vmxnet3_tq_destroy_all(adapter); 2933 queue_err: 2934 return err; 2935 } 2936 2937 2938 static int 2939 vmxnet3_close(struct net_device *netdev) 2940 { 2941 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2942 2943 /* 2944 * Reset_work may be in the middle of resetting the device, wait for its 2945 * completion. 2946 */ 2947 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 2948 msleep(1); 2949 2950 vmxnet3_quiesce_dev(adapter); 2951 2952 vmxnet3_rq_destroy_all(adapter); 2953 vmxnet3_tq_destroy_all(adapter); 2954 2955 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 2956 2957 2958 return 0; 2959 } 2960 2961 2962 void 2963 vmxnet3_force_close(struct vmxnet3_adapter *adapter) 2964 { 2965 int i; 2966 2967 /* 2968 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise 2969 * vmxnet3_close() will deadlock. 2970 */ 2971 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)); 2972 2973 /* we need to enable NAPI, otherwise dev_close will deadlock */ 2974 for (i = 0; i < adapter->num_rx_queues; i++) 2975 napi_enable(&adapter->rx_queue[i].napi); 2976 /* 2977 * Need to clear the quiesce bit to ensure that vmxnet3_close 2978 * can quiesce the device properly 2979 */ 2980 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 2981 dev_close(adapter->netdev); 2982 } 2983 2984 2985 static int 2986 vmxnet3_change_mtu(struct net_device *netdev, int new_mtu) 2987 { 2988 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2989 int err = 0; 2990 2991 netdev->mtu = new_mtu; 2992 2993 /* 2994 * Reset_work may be in the middle of resetting the device, wait for its 2995 * completion. 2996 */ 2997 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 2998 msleep(1); 2999 3000 if (netif_running(netdev)) { 3001 vmxnet3_quiesce_dev(adapter); 3002 vmxnet3_reset_dev(adapter); 3003 3004 /* we need to re-create the rx queue based on the new mtu */ 3005 vmxnet3_rq_destroy_all(adapter); 3006 vmxnet3_adjust_rx_ring_size(adapter); 3007 err = vmxnet3_rq_create_all(adapter); 3008 if (err) { 3009 netdev_err(netdev, 3010 "failed to re-create rx queues, " 3011 " error %d. Closing it.\n", err); 3012 goto out; 3013 } 3014 3015 err = vmxnet3_activate_dev(adapter); 3016 if (err) { 3017 netdev_err(netdev, 3018 "failed to re-activate, error %d. " 3019 "Closing it\n", err); 3020 goto out; 3021 } 3022 } 3023 3024 out: 3025 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3026 if (err) 3027 vmxnet3_force_close(adapter); 3028 3029 return err; 3030 } 3031 3032 3033 static void 3034 vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64) 3035 { 3036 struct net_device *netdev = adapter->netdev; 3037 3038 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM | 3039 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX | 3040 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 | 3041 NETIF_F_LRO; 3042 if (dma64) 3043 netdev->hw_features |= NETIF_F_HIGHDMA; 3044 netdev->vlan_features = netdev->hw_features & 3045 ~(NETIF_F_HW_VLAN_CTAG_TX | 3046 NETIF_F_HW_VLAN_CTAG_RX); 3047 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER; 3048 } 3049 3050 3051 static void 3052 vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac) 3053 { 3054 u32 tmp; 3055 3056 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL); 3057 *(u32 *)mac = tmp; 3058 3059 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH); 3060 mac[4] = tmp & 0xff; 3061 mac[5] = (tmp >> 8) & 0xff; 3062 } 3063 3064 #ifdef CONFIG_PCI_MSI 3065 3066 /* 3067 * Enable MSIx vectors. 3068 * Returns : 3069 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required 3070 * were enabled. 3071 * number of vectors which were enabled otherwise (this number is greater 3072 * than VMXNET3_LINUX_MIN_MSIX_VECT) 3073 */ 3074 3075 static int 3076 vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, int nvec) 3077 { 3078 int ret = pci_enable_msix_range(adapter->pdev, 3079 adapter->intr.msix_entries, nvec, nvec); 3080 3081 if (ret == -ENOSPC && nvec > VMXNET3_LINUX_MIN_MSIX_VECT) { 3082 dev_err(&adapter->netdev->dev, 3083 "Failed to enable %d MSI-X, trying %d\n", 3084 nvec, VMXNET3_LINUX_MIN_MSIX_VECT); 3085 3086 ret = pci_enable_msix_range(adapter->pdev, 3087 adapter->intr.msix_entries, 3088 VMXNET3_LINUX_MIN_MSIX_VECT, 3089 VMXNET3_LINUX_MIN_MSIX_VECT); 3090 } 3091 3092 if (ret < 0) { 3093 dev_err(&adapter->netdev->dev, 3094 "Failed to enable MSI-X, error: %d\n", ret); 3095 } 3096 3097 return ret; 3098 } 3099 3100 3101 #endif /* CONFIG_PCI_MSI */ 3102 3103 static void 3104 vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter) 3105 { 3106 u32 cfg; 3107 unsigned long flags; 3108 3109 /* intr settings */ 3110 spin_lock_irqsave(&adapter->cmd_lock, flags); 3111 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3112 VMXNET3_CMD_GET_CONF_INTR); 3113 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 3114 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3115 adapter->intr.type = cfg & 0x3; 3116 adapter->intr.mask_mode = (cfg >> 2) & 0x3; 3117 3118 if (adapter->intr.type == VMXNET3_IT_AUTO) { 3119 adapter->intr.type = VMXNET3_IT_MSIX; 3120 } 3121 3122 #ifdef CONFIG_PCI_MSI 3123 if (adapter->intr.type == VMXNET3_IT_MSIX) { 3124 int i, nvec; 3125 3126 nvec = adapter->share_intr == VMXNET3_INTR_TXSHARE ? 3127 1 : adapter->num_tx_queues; 3128 nvec += adapter->share_intr == VMXNET3_INTR_BUDDYSHARE ? 3129 0 : adapter->num_rx_queues; 3130 nvec += 1; /* for link event */ 3131 nvec = nvec > VMXNET3_LINUX_MIN_MSIX_VECT ? 3132 nvec : VMXNET3_LINUX_MIN_MSIX_VECT; 3133 3134 for (i = 0; i < nvec; i++) 3135 adapter->intr.msix_entries[i].entry = i; 3136 3137 nvec = vmxnet3_acquire_msix_vectors(adapter, nvec); 3138 if (nvec < 0) 3139 goto msix_err; 3140 3141 /* If we cannot allocate one MSIx vector per queue 3142 * then limit the number of rx queues to 1 3143 */ 3144 if (nvec == VMXNET3_LINUX_MIN_MSIX_VECT) { 3145 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE 3146 || adapter->num_rx_queues != 1) { 3147 adapter->share_intr = VMXNET3_INTR_TXSHARE; 3148 netdev_err(adapter->netdev, 3149 "Number of rx queues : 1\n"); 3150 adapter->num_rx_queues = 1; 3151 } 3152 } 3153 3154 adapter->intr.num_intrs = nvec; 3155 return; 3156 3157 msix_err: 3158 /* If we cannot allocate MSIx vectors use only one rx queue */ 3159 dev_info(&adapter->pdev->dev, 3160 "Failed to enable MSI-X, error %d. " 3161 "Limiting #rx queues to 1, try MSI.\n", nvec); 3162 3163 adapter->intr.type = VMXNET3_IT_MSI; 3164 } 3165 3166 if (adapter->intr.type == VMXNET3_IT_MSI) { 3167 if (!pci_enable_msi(adapter->pdev)) { 3168 adapter->num_rx_queues = 1; 3169 adapter->intr.num_intrs = 1; 3170 return; 3171 } 3172 } 3173 #endif /* CONFIG_PCI_MSI */ 3174 3175 adapter->num_rx_queues = 1; 3176 dev_info(&adapter->netdev->dev, 3177 "Using INTx interrupt, #Rx queues: 1.\n"); 3178 adapter->intr.type = VMXNET3_IT_INTX; 3179 3180 /* INT-X related setting */ 3181 adapter->intr.num_intrs = 1; 3182 } 3183 3184 3185 static void 3186 vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter) 3187 { 3188 if (adapter->intr.type == VMXNET3_IT_MSIX) 3189 pci_disable_msix(adapter->pdev); 3190 else if (adapter->intr.type == VMXNET3_IT_MSI) 3191 pci_disable_msi(adapter->pdev); 3192 else 3193 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX); 3194 } 3195 3196 3197 static void 3198 vmxnet3_tx_timeout(struct net_device *netdev) 3199 { 3200 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3201 adapter->tx_timeout_count++; 3202 3203 netdev_err(adapter->netdev, "tx hang\n"); 3204 schedule_work(&adapter->work); 3205 } 3206 3207 3208 static void 3209 vmxnet3_reset_work(struct work_struct *data) 3210 { 3211 struct vmxnet3_adapter *adapter; 3212 3213 adapter = container_of(data, struct vmxnet3_adapter, work); 3214 3215 /* if another thread is resetting the device, no need to proceed */ 3216 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 3217 return; 3218 3219 /* if the device is closed, we must leave it alone */ 3220 rtnl_lock(); 3221 if (netif_running(adapter->netdev)) { 3222 netdev_notice(adapter->netdev, "resetting\n"); 3223 vmxnet3_quiesce_dev(adapter); 3224 vmxnet3_reset_dev(adapter); 3225 vmxnet3_activate_dev(adapter); 3226 } else { 3227 netdev_info(adapter->netdev, "already closed\n"); 3228 } 3229 rtnl_unlock(); 3230 3231 netif_wake_queue(adapter->netdev); 3232 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3233 } 3234 3235 3236 static int 3237 vmxnet3_probe_device(struct pci_dev *pdev, 3238 const struct pci_device_id *id) 3239 { 3240 static const struct net_device_ops vmxnet3_netdev_ops = { 3241 .ndo_open = vmxnet3_open, 3242 .ndo_stop = vmxnet3_close, 3243 .ndo_start_xmit = vmxnet3_xmit_frame, 3244 .ndo_set_mac_address = vmxnet3_set_mac_addr, 3245 .ndo_change_mtu = vmxnet3_change_mtu, 3246 .ndo_set_features = vmxnet3_set_features, 3247 .ndo_get_stats64 = vmxnet3_get_stats64, 3248 .ndo_tx_timeout = vmxnet3_tx_timeout, 3249 .ndo_set_rx_mode = vmxnet3_set_mc, 3250 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid, 3251 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid, 3252 #ifdef CONFIG_NET_POLL_CONTROLLER 3253 .ndo_poll_controller = vmxnet3_netpoll, 3254 #endif 3255 }; 3256 int err; 3257 bool dma64 = false; /* stupid gcc */ 3258 u32 ver; 3259 struct net_device *netdev; 3260 struct vmxnet3_adapter *adapter; 3261 u8 mac[ETH_ALEN]; 3262 int size; 3263 int num_tx_queues; 3264 int num_rx_queues; 3265 3266 if (!pci_msi_enabled()) 3267 enable_mq = 0; 3268 3269 #ifdef VMXNET3_RSS 3270 if (enable_mq) 3271 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES, 3272 (int)num_online_cpus()); 3273 else 3274 #endif 3275 num_rx_queues = 1; 3276 num_rx_queues = rounddown_pow_of_two(num_rx_queues); 3277 3278 if (enable_mq) 3279 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES, 3280 (int)num_online_cpus()); 3281 else 3282 num_tx_queues = 1; 3283 3284 num_tx_queues = rounddown_pow_of_two(num_tx_queues); 3285 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter), 3286 max(num_tx_queues, num_rx_queues)); 3287 dev_info(&pdev->dev, 3288 "# of Tx queues : %d, # of Rx queues : %d\n", 3289 num_tx_queues, num_rx_queues); 3290 3291 if (!netdev) 3292 return -ENOMEM; 3293 3294 pci_set_drvdata(pdev, netdev); 3295 adapter = netdev_priv(netdev); 3296 adapter->netdev = netdev; 3297 adapter->pdev = pdev; 3298 3299 adapter->tx_ring_size = VMXNET3_DEF_TX_RING_SIZE; 3300 adapter->rx_ring_size = VMXNET3_DEF_RX_RING_SIZE; 3301 adapter->rx_ring2_size = VMXNET3_DEF_RX_RING2_SIZE; 3302 3303 spin_lock_init(&adapter->cmd_lock); 3304 adapter->adapter_pa = dma_map_single(&adapter->pdev->dev, adapter, 3305 sizeof(struct vmxnet3_adapter), 3306 PCI_DMA_TODEVICE); 3307 if (dma_mapping_error(&adapter->pdev->dev, adapter->adapter_pa)) { 3308 dev_err(&pdev->dev, "Failed to map dma\n"); 3309 err = -EFAULT; 3310 goto err_dma_map; 3311 } 3312 adapter->shared = dma_alloc_coherent( 3313 &adapter->pdev->dev, 3314 sizeof(struct Vmxnet3_DriverShared), 3315 &adapter->shared_pa, GFP_KERNEL); 3316 if (!adapter->shared) { 3317 dev_err(&pdev->dev, "Failed to allocate memory\n"); 3318 err = -ENOMEM; 3319 goto err_alloc_shared; 3320 } 3321 3322 adapter->num_rx_queues = num_rx_queues; 3323 adapter->num_tx_queues = num_tx_queues; 3324 adapter->rx_buf_per_pkt = 1; 3325 3326 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues; 3327 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues; 3328 adapter->tqd_start = dma_alloc_coherent(&adapter->pdev->dev, size, 3329 &adapter->queue_desc_pa, 3330 GFP_KERNEL); 3331 3332 if (!adapter->tqd_start) { 3333 dev_err(&pdev->dev, "Failed to allocate memory\n"); 3334 err = -ENOMEM; 3335 goto err_alloc_queue_desc; 3336 } 3337 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start + 3338 adapter->num_tx_queues); 3339 3340 adapter->pm_conf = dma_alloc_coherent(&adapter->pdev->dev, 3341 sizeof(struct Vmxnet3_PMConf), 3342 &adapter->pm_conf_pa, 3343 GFP_KERNEL); 3344 if (adapter->pm_conf == NULL) { 3345 err = -ENOMEM; 3346 goto err_alloc_pm; 3347 } 3348 3349 #ifdef VMXNET3_RSS 3350 3351 adapter->rss_conf = dma_alloc_coherent(&adapter->pdev->dev, 3352 sizeof(struct UPT1_RSSConf), 3353 &adapter->rss_conf_pa, 3354 GFP_KERNEL); 3355 if (adapter->rss_conf == NULL) { 3356 err = -ENOMEM; 3357 goto err_alloc_rss; 3358 } 3359 #endif /* VMXNET3_RSS */ 3360 3361 err = vmxnet3_alloc_pci_resources(adapter, &dma64); 3362 if (err < 0) 3363 goto err_alloc_pci; 3364 3365 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS); 3366 if (ver & (1 << VMXNET3_REV_3)) { 3367 VMXNET3_WRITE_BAR1_REG(adapter, 3368 VMXNET3_REG_VRRS, 3369 1 << VMXNET3_REV_3); 3370 adapter->version = VMXNET3_REV_3 + 1; 3371 } else if (ver & (1 << VMXNET3_REV_2)) { 3372 VMXNET3_WRITE_BAR1_REG(adapter, 3373 VMXNET3_REG_VRRS, 3374 1 << VMXNET3_REV_2); 3375 adapter->version = VMXNET3_REV_2 + 1; 3376 } else if (ver & (1 << VMXNET3_REV_1)) { 3377 VMXNET3_WRITE_BAR1_REG(adapter, 3378 VMXNET3_REG_VRRS, 3379 1 << VMXNET3_REV_1); 3380 adapter->version = VMXNET3_REV_1 + 1; 3381 } else { 3382 dev_err(&pdev->dev, 3383 "Incompatible h/w version (0x%x) for adapter\n", ver); 3384 err = -EBUSY; 3385 goto err_ver; 3386 } 3387 dev_dbg(&pdev->dev, "Using device version %d\n", adapter->version); 3388 3389 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS); 3390 if (ver & 1) { 3391 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1); 3392 } else { 3393 dev_err(&pdev->dev, 3394 "Incompatible upt version (0x%x) for adapter\n", ver); 3395 err = -EBUSY; 3396 goto err_ver; 3397 } 3398 3399 if (VMXNET3_VERSION_GE_3(adapter)) { 3400 adapter->coal_conf = 3401 dma_alloc_coherent(&adapter->pdev->dev, 3402 sizeof(struct Vmxnet3_CoalesceScheme) 3403 , 3404 &adapter->coal_conf_pa, 3405 GFP_KERNEL); 3406 if (!adapter->coal_conf) { 3407 err = -ENOMEM; 3408 goto err_ver; 3409 } 3410 memset(adapter->coal_conf, 0, sizeof(*adapter->coal_conf)); 3411 adapter->coal_conf->coalMode = VMXNET3_COALESCE_DISABLED; 3412 adapter->default_coal_mode = true; 3413 } 3414 3415 SET_NETDEV_DEV(netdev, &pdev->dev); 3416 vmxnet3_declare_features(adapter, dma64); 3417 3418 adapter->rxdata_desc_size = VMXNET3_VERSION_GE_3(adapter) ? 3419 VMXNET3_DEF_RXDATA_DESC_SIZE : 0; 3420 3421 if (adapter->num_tx_queues == adapter->num_rx_queues) 3422 adapter->share_intr = VMXNET3_INTR_BUDDYSHARE; 3423 else 3424 adapter->share_intr = VMXNET3_INTR_DONTSHARE; 3425 3426 vmxnet3_alloc_intr_resources(adapter); 3427 3428 #ifdef VMXNET3_RSS 3429 if (adapter->num_rx_queues > 1 && 3430 adapter->intr.type == VMXNET3_IT_MSIX) { 3431 adapter->rss = true; 3432 netdev->hw_features |= NETIF_F_RXHASH; 3433 netdev->features |= NETIF_F_RXHASH; 3434 dev_dbg(&pdev->dev, "RSS is enabled.\n"); 3435 } else { 3436 adapter->rss = false; 3437 } 3438 #endif 3439 3440 vmxnet3_read_mac_addr(adapter, mac); 3441 memcpy(netdev->dev_addr, mac, netdev->addr_len); 3442 3443 netdev->netdev_ops = &vmxnet3_netdev_ops; 3444 vmxnet3_set_ethtool_ops(netdev); 3445 netdev->watchdog_timeo = 5 * HZ; 3446 3447 /* MTU range: 60 - 9000 */ 3448 netdev->min_mtu = VMXNET3_MIN_MTU; 3449 netdev->max_mtu = VMXNET3_MAX_MTU; 3450 3451 INIT_WORK(&adapter->work, vmxnet3_reset_work); 3452 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 3453 3454 if (adapter->intr.type == VMXNET3_IT_MSIX) { 3455 int i; 3456 for (i = 0; i < adapter->num_rx_queues; i++) { 3457 netif_napi_add(adapter->netdev, 3458 &adapter->rx_queue[i].napi, 3459 vmxnet3_poll_rx_only, 64); 3460 } 3461 } else { 3462 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi, 3463 vmxnet3_poll, 64); 3464 } 3465 3466 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); 3467 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues); 3468 3469 netif_carrier_off(netdev); 3470 err = register_netdev(netdev); 3471 3472 if (err) { 3473 dev_err(&pdev->dev, "Failed to register adapter\n"); 3474 goto err_register; 3475 } 3476 3477 vmxnet3_check_link(adapter, false); 3478 return 0; 3479 3480 err_register: 3481 if (VMXNET3_VERSION_GE_3(adapter)) { 3482 dma_free_coherent(&adapter->pdev->dev, 3483 sizeof(struct Vmxnet3_CoalesceScheme), 3484 adapter->coal_conf, adapter->coal_conf_pa); 3485 } 3486 vmxnet3_free_intr_resources(adapter); 3487 err_ver: 3488 vmxnet3_free_pci_resources(adapter); 3489 err_alloc_pci: 3490 #ifdef VMXNET3_RSS 3491 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf), 3492 adapter->rss_conf, adapter->rss_conf_pa); 3493 err_alloc_rss: 3494 #endif 3495 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf), 3496 adapter->pm_conf, adapter->pm_conf_pa); 3497 err_alloc_pm: 3498 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start, 3499 adapter->queue_desc_pa); 3500 err_alloc_queue_desc: 3501 dma_free_coherent(&adapter->pdev->dev, 3502 sizeof(struct Vmxnet3_DriverShared), 3503 adapter->shared, adapter->shared_pa); 3504 err_alloc_shared: 3505 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa, 3506 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE); 3507 err_dma_map: 3508 free_netdev(netdev); 3509 return err; 3510 } 3511 3512 3513 static void 3514 vmxnet3_remove_device(struct pci_dev *pdev) 3515 { 3516 struct net_device *netdev = pci_get_drvdata(pdev); 3517 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3518 int size = 0; 3519 int num_rx_queues; 3520 3521 #ifdef VMXNET3_RSS 3522 if (enable_mq) 3523 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES, 3524 (int)num_online_cpus()); 3525 else 3526 #endif 3527 num_rx_queues = 1; 3528 num_rx_queues = rounddown_pow_of_two(num_rx_queues); 3529 3530 cancel_work_sync(&adapter->work); 3531 3532 unregister_netdev(netdev); 3533 3534 vmxnet3_free_intr_resources(adapter); 3535 vmxnet3_free_pci_resources(adapter); 3536 if (VMXNET3_VERSION_GE_3(adapter)) { 3537 dma_free_coherent(&adapter->pdev->dev, 3538 sizeof(struct Vmxnet3_CoalesceScheme), 3539 adapter->coal_conf, adapter->coal_conf_pa); 3540 } 3541 #ifdef VMXNET3_RSS 3542 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf), 3543 adapter->rss_conf, adapter->rss_conf_pa); 3544 #endif 3545 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf), 3546 adapter->pm_conf, adapter->pm_conf_pa); 3547 3548 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues; 3549 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues; 3550 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start, 3551 adapter->queue_desc_pa); 3552 dma_free_coherent(&adapter->pdev->dev, 3553 sizeof(struct Vmxnet3_DriverShared), 3554 adapter->shared, adapter->shared_pa); 3555 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa, 3556 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE); 3557 free_netdev(netdev); 3558 } 3559 3560 static void vmxnet3_shutdown_device(struct pci_dev *pdev) 3561 { 3562 struct net_device *netdev = pci_get_drvdata(pdev); 3563 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3564 unsigned long flags; 3565 3566 /* Reset_work may be in the middle of resetting the device, wait for its 3567 * completion. 3568 */ 3569 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 3570 msleep(1); 3571 3572 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, 3573 &adapter->state)) { 3574 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3575 return; 3576 } 3577 spin_lock_irqsave(&adapter->cmd_lock, flags); 3578 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3579 VMXNET3_CMD_QUIESCE_DEV); 3580 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3581 vmxnet3_disable_all_intrs(adapter); 3582 3583 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3584 } 3585 3586 3587 #ifdef CONFIG_PM 3588 3589 static int 3590 vmxnet3_suspend(struct device *device) 3591 { 3592 struct pci_dev *pdev = to_pci_dev(device); 3593 struct net_device *netdev = pci_get_drvdata(pdev); 3594 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3595 struct Vmxnet3_PMConf *pmConf; 3596 struct ethhdr *ehdr; 3597 struct arphdr *ahdr; 3598 u8 *arpreq; 3599 struct in_device *in_dev; 3600 struct in_ifaddr *ifa; 3601 unsigned long flags; 3602 int i = 0; 3603 3604 if (!netif_running(netdev)) 3605 return 0; 3606 3607 for (i = 0; i < adapter->num_rx_queues; i++) 3608 napi_disable(&adapter->rx_queue[i].napi); 3609 3610 vmxnet3_disable_all_intrs(adapter); 3611 vmxnet3_free_irqs(adapter); 3612 vmxnet3_free_intr_resources(adapter); 3613 3614 netif_device_detach(netdev); 3615 netif_tx_stop_all_queues(netdev); 3616 3617 /* Create wake-up filters. */ 3618 pmConf = adapter->pm_conf; 3619 memset(pmConf, 0, sizeof(*pmConf)); 3620 3621 if (adapter->wol & WAKE_UCAST) { 3622 pmConf->filters[i].patternSize = ETH_ALEN; 3623 pmConf->filters[i].maskSize = 1; 3624 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN); 3625 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */ 3626 3627 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER; 3628 i++; 3629 } 3630 3631 if (adapter->wol & WAKE_ARP) { 3632 in_dev = in_dev_get(netdev); 3633 if (!in_dev) 3634 goto skip_arp; 3635 3636 ifa = (struct in_ifaddr *)in_dev->ifa_list; 3637 if (!ifa) 3638 goto skip_arp; 3639 3640 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/ 3641 sizeof(struct arphdr) + /* ARP header */ 3642 2 * ETH_ALEN + /* 2 Ethernet addresses*/ 3643 2 * sizeof(u32); /*2 IPv4 addresses */ 3644 pmConf->filters[i].maskSize = 3645 (pmConf->filters[i].patternSize - 1) / 8 + 1; 3646 3647 /* ETH_P_ARP in Ethernet header. */ 3648 ehdr = (struct ethhdr *)pmConf->filters[i].pattern; 3649 ehdr->h_proto = htons(ETH_P_ARP); 3650 3651 /* ARPOP_REQUEST in ARP header. */ 3652 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN]; 3653 ahdr->ar_op = htons(ARPOP_REQUEST); 3654 arpreq = (u8 *)(ahdr + 1); 3655 3656 /* The Unicast IPv4 address in 'tip' field. */ 3657 arpreq += 2 * ETH_ALEN + sizeof(u32); 3658 *(u32 *)arpreq = ifa->ifa_address; 3659 3660 /* The mask for the relevant bits. */ 3661 pmConf->filters[i].mask[0] = 0x00; 3662 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */ 3663 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */ 3664 pmConf->filters[i].mask[3] = 0x00; 3665 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */ 3666 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */ 3667 in_dev_put(in_dev); 3668 3669 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER; 3670 i++; 3671 } 3672 3673 skip_arp: 3674 if (adapter->wol & WAKE_MAGIC) 3675 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC; 3676 3677 pmConf->numFilters = i; 3678 3679 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1); 3680 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof( 3681 *pmConf)); 3682 adapter->shared->devRead.pmConfDesc.confPA = 3683 cpu_to_le64(adapter->pm_conf_pa); 3684 3685 spin_lock_irqsave(&adapter->cmd_lock, flags); 3686 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3687 VMXNET3_CMD_UPDATE_PMCFG); 3688 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3689 3690 pci_save_state(pdev); 3691 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND), 3692 adapter->wol); 3693 pci_disable_device(pdev); 3694 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND)); 3695 3696 return 0; 3697 } 3698 3699 3700 static int 3701 vmxnet3_resume(struct device *device) 3702 { 3703 int err; 3704 unsigned long flags; 3705 struct pci_dev *pdev = to_pci_dev(device); 3706 struct net_device *netdev = pci_get_drvdata(pdev); 3707 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3708 3709 if (!netif_running(netdev)) 3710 return 0; 3711 3712 pci_set_power_state(pdev, PCI_D0); 3713 pci_restore_state(pdev); 3714 err = pci_enable_device_mem(pdev); 3715 if (err != 0) 3716 return err; 3717 3718 pci_enable_wake(pdev, PCI_D0, 0); 3719 3720 vmxnet3_alloc_intr_resources(adapter); 3721 3722 /* During hibernate and suspend, device has to be reinitialized as the 3723 * device state need not be preserved. 3724 */ 3725 3726 /* Need not check adapter state as other reset tasks cannot run during 3727 * device resume. 3728 */ 3729 spin_lock_irqsave(&adapter->cmd_lock, flags); 3730 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3731 VMXNET3_CMD_QUIESCE_DEV); 3732 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3733 vmxnet3_tq_cleanup_all(adapter); 3734 vmxnet3_rq_cleanup_all(adapter); 3735 3736 vmxnet3_reset_dev(adapter); 3737 err = vmxnet3_activate_dev(adapter); 3738 if (err != 0) { 3739 netdev_err(netdev, 3740 "failed to re-activate on resume, error: %d", err); 3741 vmxnet3_force_close(adapter); 3742 return err; 3743 } 3744 netif_device_attach(netdev); 3745 3746 return 0; 3747 } 3748 3749 static const struct dev_pm_ops vmxnet3_pm_ops = { 3750 .suspend = vmxnet3_suspend, 3751 .resume = vmxnet3_resume, 3752 .freeze = vmxnet3_suspend, 3753 .restore = vmxnet3_resume, 3754 }; 3755 #endif 3756 3757 static struct pci_driver vmxnet3_driver = { 3758 .name = vmxnet3_driver_name, 3759 .id_table = vmxnet3_pciid_table, 3760 .probe = vmxnet3_probe_device, 3761 .remove = vmxnet3_remove_device, 3762 .shutdown = vmxnet3_shutdown_device, 3763 #ifdef CONFIG_PM 3764 .driver.pm = &vmxnet3_pm_ops, 3765 #endif 3766 }; 3767 3768 3769 static int __init 3770 vmxnet3_init_module(void) 3771 { 3772 pr_info("%s - version %s\n", VMXNET3_DRIVER_DESC, 3773 VMXNET3_DRIVER_VERSION_REPORT); 3774 return pci_register_driver(&vmxnet3_driver); 3775 } 3776 3777 module_init(vmxnet3_init_module); 3778 3779 3780 static void 3781 vmxnet3_exit_module(void) 3782 { 3783 pci_unregister_driver(&vmxnet3_driver); 3784 } 3785 3786 module_exit(vmxnet3_exit_module); 3787 3788 MODULE_AUTHOR("VMware, Inc."); 3789 MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC); 3790 MODULE_LICENSE("GPL v2"); 3791 MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING); 3792