1 /* 2 * Linux driver for VMware's vmxnet3 ethernet NIC. 3 * 4 * Copyright (C) 2008-2016, VMware, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; version 2 of the License and no later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 13 * NON INFRINGEMENT. See the GNU General Public License for more 14 * details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * The full GNU General Public License is included in this distribution in 21 * the file called "COPYING". 22 * 23 * Maintained by: pv-drivers@vmware.com 24 * 25 */ 26 27 #include <linux/module.h> 28 #include <net/ip6_checksum.h> 29 30 #include "vmxnet3_int.h" 31 32 char vmxnet3_driver_name[] = "vmxnet3"; 33 #define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver" 34 35 /* 36 * PCI Device ID Table 37 * Last entry must be all 0s 38 */ 39 static const struct pci_device_id vmxnet3_pciid_table[] = { 40 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)}, 41 {0} 42 }; 43 44 MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table); 45 46 static int enable_mq = 1; 47 48 static void 49 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac); 50 51 /* 52 * Enable/Disable the given intr 53 */ 54 static void 55 vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx) 56 { 57 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0); 58 } 59 60 61 static void 62 vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx) 63 { 64 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1); 65 } 66 67 68 /* 69 * Enable/Disable all intrs used by the device 70 */ 71 static void 72 vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter) 73 { 74 int i; 75 76 for (i = 0; i < adapter->intr.num_intrs; i++) 77 vmxnet3_enable_intr(adapter, i); 78 adapter->shared->devRead.intrConf.intrCtrl &= 79 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL); 80 } 81 82 83 static void 84 vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter) 85 { 86 int i; 87 88 adapter->shared->devRead.intrConf.intrCtrl |= 89 cpu_to_le32(VMXNET3_IC_DISABLE_ALL); 90 for (i = 0; i < adapter->intr.num_intrs; i++) 91 vmxnet3_disable_intr(adapter, i); 92 } 93 94 95 static void 96 vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events) 97 { 98 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events); 99 } 100 101 102 static bool 103 vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 104 { 105 return tq->stopped; 106 } 107 108 109 static void 110 vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 111 { 112 tq->stopped = false; 113 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue); 114 } 115 116 117 static void 118 vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 119 { 120 tq->stopped = false; 121 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue)); 122 } 123 124 125 static void 126 vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 127 { 128 tq->stopped = true; 129 tq->num_stop++; 130 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue)); 131 } 132 133 134 /* 135 * Check the link state. This may start or stop the tx queue. 136 */ 137 static void 138 vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue) 139 { 140 u32 ret; 141 int i; 142 unsigned long flags; 143 144 spin_lock_irqsave(&adapter->cmd_lock, flags); 145 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 146 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 147 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 148 149 adapter->link_speed = ret >> 16; 150 if (ret & 1) { /* Link is up. */ 151 netdev_info(adapter->netdev, "NIC Link is Up %d Mbps\n", 152 adapter->link_speed); 153 netif_carrier_on(adapter->netdev); 154 155 if (affectTxQueue) { 156 for (i = 0; i < adapter->num_tx_queues; i++) 157 vmxnet3_tq_start(&adapter->tx_queue[i], 158 adapter); 159 } 160 } else { 161 netdev_info(adapter->netdev, "NIC Link is Down\n"); 162 netif_carrier_off(adapter->netdev); 163 164 if (affectTxQueue) { 165 for (i = 0; i < adapter->num_tx_queues; i++) 166 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter); 167 } 168 } 169 } 170 171 static void 172 vmxnet3_process_events(struct vmxnet3_adapter *adapter) 173 { 174 int i; 175 unsigned long flags; 176 u32 events = le32_to_cpu(adapter->shared->ecr); 177 if (!events) 178 return; 179 180 vmxnet3_ack_events(adapter, events); 181 182 /* Check if link state has changed */ 183 if (events & VMXNET3_ECR_LINK) 184 vmxnet3_check_link(adapter, true); 185 186 /* Check if there is an error on xmit/recv queues */ 187 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 188 spin_lock_irqsave(&adapter->cmd_lock, flags); 189 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 190 VMXNET3_CMD_GET_QUEUE_STATUS); 191 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 192 193 for (i = 0; i < adapter->num_tx_queues; i++) 194 if (adapter->tqd_start[i].status.stopped) 195 dev_err(&adapter->netdev->dev, 196 "%s: tq[%d] error 0x%x\n", 197 adapter->netdev->name, i, le32_to_cpu( 198 adapter->tqd_start[i].status.error)); 199 for (i = 0; i < adapter->num_rx_queues; i++) 200 if (adapter->rqd_start[i].status.stopped) 201 dev_err(&adapter->netdev->dev, 202 "%s: rq[%d] error 0x%x\n", 203 adapter->netdev->name, i, 204 adapter->rqd_start[i].status.error); 205 206 schedule_work(&adapter->work); 207 } 208 } 209 210 #ifdef __BIG_ENDIAN_BITFIELD 211 /* 212 * The device expects the bitfields in shared structures to be written in 213 * little endian. When CPU is big endian, the following routines are used to 214 * correctly read and write into ABI. 215 * The general technique used here is : double word bitfields are defined in 216 * opposite order for big endian architecture. Then before reading them in 217 * driver the complete double word is translated using le32_to_cpu. Similarly 218 * After the driver writes into bitfields, cpu_to_le32 is used to translate the 219 * double words into required format. 220 * In order to avoid touching bits in shared structure more than once, temporary 221 * descriptors are used. These are passed as srcDesc to following functions. 222 */ 223 static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc, 224 struct Vmxnet3_RxDesc *dstDesc) 225 { 226 u32 *src = (u32 *)srcDesc + 2; 227 u32 *dst = (u32 *)dstDesc + 2; 228 dstDesc->addr = le64_to_cpu(srcDesc->addr); 229 *dst = le32_to_cpu(*src); 230 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1); 231 } 232 233 static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc, 234 struct Vmxnet3_TxDesc *dstDesc) 235 { 236 int i; 237 u32 *src = (u32 *)(srcDesc + 1); 238 u32 *dst = (u32 *)(dstDesc + 1); 239 240 /* Working backwards so that the gen bit is set at the end. */ 241 for (i = 2; i > 0; i--) { 242 src--; 243 dst--; 244 *dst = cpu_to_le32(*src); 245 } 246 } 247 248 249 static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc, 250 struct Vmxnet3_RxCompDesc *dstDesc) 251 { 252 int i = 0; 253 u32 *src = (u32 *)srcDesc; 254 u32 *dst = (u32 *)dstDesc; 255 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) { 256 *dst = le32_to_cpu(*src); 257 src++; 258 dst++; 259 } 260 } 261 262 263 /* Used to read bitfield values from double words. */ 264 static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size) 265 { 266 u32 temp = le32_to_cpu(*bitfield); 267 u32 mask = ((1 << size) - 1) << pos; 268 temp &= mask; 269 temp >>= pos; 270 return temp; 271 } 272 273 274 275 #endif /* __BIG_ENDIAN_BITFIELD */ 276 277 #ifdef __BIG_ENDIAN_BITFIELD 278 279 # define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \ 280 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \ 281 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE) 282 # define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \ 283 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \ 284 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE) 285 # define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \ 286 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \ 287 VMXNET3_TCD_GEN_SIZE) 288 # define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \ 289 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE) 290 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \ 291 (dstrcd) = (tmp); \ 292 vmxnet3_RxCompToCPU((rcd), (tmp)); \ 293 } while (0) 294 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \ 295 (dstrxd) = (tmp); \ 296 vmxnet3_RxDescToCPU((rxd), (tmp)); \ 297 } while (0) 298 299 #else 300 301 # define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen) 302 # define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop) 303 # define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen) 304 # define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx) 305 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd) 306 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd) 307 308 #endif /* __BIG_ENDIAN_BITFIELD */ 309 310 311 static void 312 vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi, 313 struct pci_dev *pdev) 314 { 315 if (tbi->map_type == VMXNET3_MAP_SINGLE) 316 dma_unmap_single(&pdev->dev, tbi->dma_addr, tbi->len, 317 PCI_DMA_TODEVICE); 318 else if (tbi->map_type == VMXNET3_MAP_PAGE) 319 dma_unmap_page(&pdev->dev, tbi->dma_addr, tbi->len, 320 PCI_DMA_TODEVICE); 321 else 322 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE); 323 324 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */ 325 } 326 327 328 static int 329 vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq, 330 struct pci_dev *pdev, struct vmxnet3_adapter *adapter) 331 { 332 struct sk_buff *skb; 333 int entries = 0; 334 335 /* no out of order completion */ 336 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp); 337 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1); 338 339 skb = tq->buf_info[eop_idx].skb; 340 BUG_ON(skb == NULL); 341 tq->buf_info[eop_idx].skb = NULL; 342 343 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size); 344 345 while (tq->tx_ring.next2comp != eop_idx) { 346 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp, 347 pdev); 348 349 /* update next2comp w/o tx_lock. Since we are marking more, 350 * instead of less, tx ring entries avail, the worst case is 351 * that the tx routine incorrectly re-queues a pkt due to 352 * insufficient tx ring entries. 353 */ 354 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring); 355 entries++; 356 } 357 358 dev_kfree_skb_any(skb); 359 return entries; 360 } 361 362 363 static int 364 vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq, 365 struct vmxnet3_adapter *adapter) 366 { 367 int completed = 0; 368 union Vmxnet3_GenericDesc *gdesc; 369 370 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; 371 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) { 372 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX( 373 &gdesc->tcd), tq, adapter->pdev, 374 adapter); 375 376 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring); 377 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; 378 } 379 380 if (completed) { 381 spin_lock(&tq->tx_lock); 382 if (unlikely(vmxnet3_tq_stopped(tq, adapter) && 383 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) > 384 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) && 385 netif_carrier_ok(adapter->netdev))) { 386 vmxnet3_tq_wake(tq, adapter); 387 } 388 spin_unlock(&tq->tx_lock); 389 } 390 return completed; 391 } 392 393 394 static void 395 vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq, 396 struct vmxnet3_adapter *adapter) 397 { 398 int i; 399 400 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) { 401 struct vmxnet3_tx_buf_info *tbi; 402 403 tbi = tq->buf_info + tq->tx_ring.next2comp; 404 405 vmxnet3_unmap_tx_buf(tbi, adapter->pdev); 406 if (tbi->skb) { 407 dev_kfree_skb_any(tbi->skb); 408 tbi->skb = NULL; 409 } 410 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring); 411 } 412 413 /* sanity check, verify all buffers are indeed unmapped and freed */ 414 for (i = 0; i < tq->tx_ring.size; i++) { 415 BUG_ON(tq->buf_info[i].skb != NULL || 416 tq->buf_info[i].map_type != VMXNET3_MAP_NONE); 417 } 418 419 tq->tx_ring.gen = VMXNET3_INIT_GEN; 420 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0; 421 422 tq->comp_ring.gen = VMXNET3_INIT_GEN; 423 tq->comp_ring.next2proc = 0; 424 } 425 426 427 static void 428 vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq, 429 struct vmxnet3_adapter *adapter) 430 { 431 if (tq->tx_ring.base) { 432 dma_free_coherent(&adapter->pdev->dev, tq->tx_ring.size * 433 sizeof(struct Vmxnet3_TxDesc), 434 tq->tx_ring.base, tq->tx_ring.basePA); 435 tq->tx_ring.base = NULL; 436 } 437 if (tq->data_ring.base) { 438 dma_free_coherent(&adapter->pdev->dev, 439 tq->data_ring.size * tq->txdata_desc_size, 440 tq->data_ring.base, tq->data_ring.basePA); 441 tq->data_ring.base = NULL; 442 } 443 if (tq->comp_ring.base) { 444 dma_free_coherent(&adapter->pdev->dev, tq->comp_ring.size * 445 sizeof(struct Vmxnet3_TxCompDesc), 446 tq->comp_ring.base, tq->comp_ring.basePA); 447 tq->comp_ring.base = NULL; 448 } 449 if (tq->buf_info) { 450 dma_free_coherent(&adapter->pdev->dev, 451 tq->tx_ring.size * sizeof(tq->buf_info[0]), 452 tq->buf_info, tq->buf_info_pa); 453 tq->buf_info = NULL; 454 } 455 } 456 457 458 /* Destroy all tx queues */ 459 void 460 vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter) 461 { 462 int i; 463 464 for (i = 0; i < adapter->num_tx_queues; i++) 465 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter); 466 } 467 468 469 static void 470 vmxnet3_tq_init(struct vmxnet3_tx_queue *tq, 471 struct vmxnet3_adapter *adapter) 472 { 473 int i; 474 475 /* reset the tx ring contents to 0 and reset the tx ring states */ 476 memset(tq->tx_ring.base, 0, tq->tx_ring.size * 477 sizeof(struct Vmxnet3_TxDesc)); 478 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0; 479 tq->tx_ring.gen = VMXNET3_INIT_GEN; 480 481 memset(tq->data_ring.base, 0, 482 tq->data_ring.size * tq->txdata_desc_size); 483 484 /* reset the tx comp ring contents to 0 and reset comp ring states */ 485 memset(tq->comp_ring.base, 0, tq->comp_ring.size * 486 sizeof(struct Vmxnet3_TxCompDesc)); 487 tq->comp_ring.next2proc = 0; 488 tq->comp_ring.gen = VMXNET3_INIT_GEN; 489 490 /* reset the bookkeeping data */ 491 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size); 492 for (i = 0; i < tq->tx_ring.size; i++) 493 tq->buf_info[i].map_type = VMXNET3_MAP_NONE; 494 495 /* stats are not reset */ 496 } 497 498 499 static int 500 vmxnet3_tq_create(struct vmxnet3_tx_queue *tq, 501 struct vmxnet3_adapter *adapter) 502 { 503 size_t sz; 504 505 BUG_ON(tq->tx_ring.base || tq->data_ring.base || 506 tq->comp_ring.base || tq->buf_info); 507 508 tq->tx_ring.base = dma_alloc_coherent(&adapter->pdev->dev, 509 tq->tx_ring.size * sizeof(struct Vmxnet3_TxDesc), 510 &tq->tx_ring.basePA, GFP_KERNEL); 511 if (!tq->tx_ring.base) { 512 netdev_err(adapter->netdev, "failed to allocate tx ring\n"); 513 goto err; 514 } 515 516 tq->data_ring.base = dma_alloc_coherent(&adapter->pdev->dev, 517 tq->data_ring.size * tq->txdata_desc_size, 518 &tq->data_ring.basePA, GFP_KERNEL); 519 if (!tq->data_ring.base) { 520 netdev_err(adapter->netdev, "failed to allocate tx data ring\n"); 521 goto err; 522 } 523 524 tq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, 525 tq->comp_ring.size * sizeof(struct Vmxnet3_TxCompDesc), 526 &tq->comp_ring.basePA, GFP_KERNEL); 527 if (!tq->comp_ring.base) { 528 netdev_err(adapter->netdev, "failed to allocate tx comp ring\n"); 529 goto err; 530 } 531 532 sz = tq->tx_ring.size * sizeof(tq->buf_info[0]); 533 tq->buf_info = dma_zalloc_coherent(&adapter->pdev->dev, sz, 534 &tq->buf_info_pa, GFP_KERNEL); 535 if (!tq->buf_info) 536 goto err; 537 538 return 0; 539 540 err: 541 vmxnet3_tq_destroy(tq, adapter); 542 return -ENOMEM; 543 } 544 545 static void 546 vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter) 547 { 548 int i; 549 550 for (i = 0; i < adapter->num_tx_queues; i++) 551 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter); 552 } 553 554 /* 555 * starting from ring->next2fill, allocate rx buffers for the given ring 556 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers 557 * are allocated or allocation fails 558 */ 559 560 static int 561 vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx, 562 int num_to_alloc, struct vmxnet3_adapter *adapter) 563 { 564 int num_allocated = 0; 565 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx]; 566 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx]; 567 u32 val; 568 569 while (num_allocated <= num_to_alloc) { 570 struct vmxnet3_rx_buf_info *rbi; 571 union Vmxnet3_GenericDesc *gd; 572 573 rbi = rbi_base + ring->next2fill; 574 gd = ring->base + ring->next2fill; 575 576 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) { 577 if (rbi->skb == NULL) { 578 rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev, 579 rbi->len, 580 GFP_KERNEL); 581 if (unlikely(rbi->skb == NULL)) { 582 rq->stats.rx_buf_alloc_failure++; 583 break; 584 } 585 586 rbi->dma_addr = dma_map_single( 587 &adapter->pdev->dev, 588 rbi->skb->data, rbi->len, 589 PCI_DMA_FROMDEVICE); 590 if (dma_mapping_error(&adapter->pdev->dev, 591 rbi->dma_addr)) { 592 dev_kfree_skb_any(rbi->skb); 593 rq->stats.rx_buf_alloc_failure++; 594 break; 595 } 596 } else { 597 /* rx buffer skipped by the device */ 598 } 599 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT; 600 } else { 601 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE || 602 rbi->len != PAGE_SIZE); 603 604 if (rbi->page == NULL) { 605 rbi->page = alloc_page(GFP_ATOMIC); 606 if (unlikely(rbi->page == NULL)) { 607 rq->stats.rx_buf_alloc_failure++; 608 break; 609 } 610 rbi->dma_addr = dma_map_page( 611 &adapter->pdev->dev, 612 rbi->page, 0, PAGE_SIZE, 613 PCI_DMA_FROMDEVICE); 614 if (dma_mapping_error(&adapter->pdev->dev, 615 rbi->dma_addr)) { 616 put_page(rbi->page); 617 rq->stats.rx_buf_alloc_failure++; 618 break; 619 } 620 } else { 621 /* rx buffers skipped by the device */ 622 } 623 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT; 624 } 625 626 gd->rxd.addr = cpu_to_le64(rbi->dma_addr); 627 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT) 628 | val | rbi->len); 629 630 /* Fill the last buffer but dont mark it ready, or else the 631 * device will think that the queue is full */ 632 if (num_allocated == num_to_alloc) 633 break; 634 635 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT); 636 num_allocated++; 637 vmxnet3_cmd_ring_adv_next2fill(ring); 638 } 639 640 netdev_dbg(adapter->netdev, 641 "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n", 642 num_allocated, ring->next2fill, ring->next2comp); 643 644 /* so that the device can distinguish a full ring and an empty ring */ 645 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp); 646 647 return num_allocated; 648 } 649 650 651 static void 652 vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd, 653 struct vmxnet3_rx_buf_info *rbi) 654 { 655 struct skb_frag_struct *frag = skb_shinfo(skb)->frags + 656 skb_shinfo(skb)->nr_frags; 657 658 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS); 659 660 __skb_frag_set_page(frag, rbi->page); 661 frag->page_offset = 0; 662 skb_frag_size_set(frag, rcd->len); 663 skb->data_len += rcd->len; 664 skb->truesize += PAGE_SIZE; 665 skb_shinfo(skb)->nr_frags++; 666 } 667 668 669 static int 670 vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx, 671 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev, 672 struct vmxnet3_adapter *adapter) 673 { 674 u32 dw2, len; 675 unsigned long buf_offset; 676 int i; 677 union Vmxnet3_GenericDesc *gdesc; 678 struct vmxnet3_tx_buf_info *tbi = NULL; 679 680 BUG_ON(ctx->copy_size > skb_headlen(skb)); 681 682 /* use the previous gen bit for the SOP desc */ 683 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT; 684 685 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill; 686 gdesc = ctx->sop_txd; /* both loops below can be skipped */ 687 688 /* no need to map the buffer if headers are copied */ 689 if (ctx->copy_size) { 690 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA + 691 tq->tx_ring.next2fill * 692 tq->txdata_desc_size); 693 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size); 694 ctx->sop_txd->dword[3] = 0; 695 696 tbi = tq->buf_info + tq->tx_ring.next2fill; 697 tbi->map_type = VMXNET3_MAP_NONE; 698 699 netdev_dbg(adapter->netdev, 700 "txd[%u]: 0x%Lx 0x%x 0x%x\n", 701 tq->tx_ring.next2fill, 702 le64_to_cpu(ctx->sop_txd->txd.addr), 703 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]); 704 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 705 706 /* use the right gen for non-SOP desc */ 707 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 708 } 709 710 /* linear part can use multiple tx desc if it's big */ 711 len = skb_headlen(skb) - ctx->copy_size; 712 buf_offset = ctx->copy_size; 713 while (len) { 714 u32 buf_size; 715 716 if (len < VMXNET3_MAX_TX_BUF_SIZE) { 717 buf_size = len; 718 dw2 |= len; 719 } else { 720 buf_size = VMXNET3_MAX_TX_BUF_SIZE; 721 /* spec says that for TxDesc.len, 0 == 2^14 */ 722 } 723 724 tbi = tq->buf_info + tq->tx_ring.next2fill; 725 tbi->map_type = VMXNET3_MAP_SINGLE; 726 tbi->dma_addr = dma_map_single(&adapter->pdev->dev, 727 skb->data + buf_offset, buf_size, 728 PCI_DMA_TODEVICE); 729 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr)) 730 return -EFAULT; 731 732 tbi->len = buf_size; 733 734 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; 735 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); 736 737 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); 738 gdesc->dword[2] = cpu_to_le32(dw2); 739 gdesc->dword[3] = 0; 740 741 netdev_dbg(adapter->netdev, 742 "txd[%u]: 0x%Lx 0x%x 0x%x\n", 743 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), 744 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); 745 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 746 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 747 748 len -= buf_size; 749 buf_offset += buf_size; 750 } 751 752 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 753 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 754 u32 buf_size; 755 756 buf_offset = 0; 757 len = skb_frag_size(frag); 758 while (len) { 759 tbi = tq->buf_info + tq->tx_ring.next2fill; 760 if (len < VMXNET3_MAX_TX_BUF_SIZE) { 761 buf_size = len; 762 dw2 |= len; 763 } else { 764 buf_size = VMXNET3_MAX_TX_BUF_SIZE; 765 /* spec says that for TxDesc.len, 0 == 2^14 */ 766 } 767 tbi->map_type = VMXNET3_MAP_PAGE; 768 tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag, 769 buf_offset, buf_size, 770 DMA_TO_DEVICE); 771 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr)) 772 return -EFAULT; 773 774 tbi->len = buf_size; 775 776 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; 777 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); 778 779 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); 780 gdesc->dword[2] = cpu_to_le32(dw2); 781 gdesc->dword[3] = 0; 782 783 netdev_dbg(adapter->netdev, 784 "txd[%u]: 0x%llx %u %u\n", 785 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), 786 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); 787 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 788 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 789 790 len -= buf_size; 791 buf_offset += buf_size; 792 } 793 } 794 795 ctx->eop_txd = gdesc; 796 797 /* set the last buf_info for the pkt */ 798 tbi->skb = skb; 799 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base; 800 801 return 0; 802 } 803 804 805 /* Init all tx queues */ 806 static void 807 vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter) 808 { 809 int i; 810 811 for (i = 0; i < adapter->num_tx_queues; i++) 812 vmxnet3_tq_init(&adapter->tx_queue[i], adapter); 813 } 814 815 816 /* 817 * parse relevant protocol headers: 818 * For a tso pkt, relevant headers are L2/3/4 including options 819 * For a pkt requesting csum offloading, they are L2/3 and may include L4 820 * if it's a TCP/UDP pkt 821 * 822 * Returns: 823 * -1: error happens during parsing 824 * 0: protocol headers parsed, but too big to be copied 825 * 1: protocol headers parsed and copied 826 * 827 * Other effects: 828 * 1. related *ctx fields are updated. 829 * 2. ctx->copy_size is # of bytes copied 830 * 3. the portion to be copied is guaranteed to be in the linear part 831 * 832 */ 833 static int 834 vmxnet3_parse_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 835 struct vmxnet3_tx_ctx *ctx, 836 struct vmxnet3_adapter *adapter) 837 { 838 u8 protocol = 0; 839 840 if (ctx->mss) { /* TSO */ 841 ctx->eth_ip_hdr_size = skb_transport_offset(skb); 842 ctx->l4_hdr_size = tcp_hdrlen(skb); 843 ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size; 844 } else { 845 if (skb->ip_summed == CHECKSUM_PARTIAL) { 846 ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb); 847 848 if (ctx->ipv4) { 849 const struct iphdr *iph = ip_hdr(skb); 850 851 protocol = iph->protocol; 852 } else if (ctx->ipv6) { 853 const struct ipv6hdr *ipv6h = ipv6_hdr(skb); 854 855 protocol = ipv6h->nexthdr; 856 } 857 858 switch (protocol) { 859 case IPPROTO_TCP: 860 ctx->l4_hdr_size = tcp_hdrlen(skb); 861 break; 862 case IPPROTO_UDP: 863 ctx->l4_hdr_size = sizeof(struct udphdr); 864 break; 865 default: 866 ctx->l4_hdr_size = 0; 867 break; 868 } 869 870 ctx->copy_size = min(ctx->eth_ip_hdr_size + 871 ctx->l4_hdr_size, skb->len); 872 } else { 873 ctx->eth_ip_hdr_size = 0; 874 ctx->l4_hdr_size = 0; 875 /* copy as much as allowed */ 876 ctx->copy_size = min_t(unsigned int, 877 tq->txdata_desc_size, 878 skb_headlen(skb)); 879 } 880 881 if (skb->len <= VMXNET3_HDR_COPY_SIZE) 882 ctx->copy_size = skb->len; 883 884 /* make sure headers are accessible directly */ 885 if (unlikely(!pskb_may_pull(skb, ctx->copy_size))) 886 goto err; 887 } 888 889 if (unlikely(ctx->copy_size > tq->txdata_desc_size)) { 890 tq->stats.oversized_hdr++; 891 ctx->copy_size = 0; 892 return 0; 893 } 894 895 return 1; 896 err: 897 return -1; 898 } 899 900 /* 901 * copy relevant protocol headers to the transmit ring: 902 * For a tso pkt, relevant headers are L2/3/4 including options 903 * For a pkt requesting csum offloading, they are L2/3 and may include L4 904 * if it's a TCP/UDP pkt 905 * 906 * 907 * Note that this requires that vmxnet3_parse_hdr be called first to set the 908 * appropriate bits in ctx first 909 */ 910 static void 911 vmxnet3_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 912 struct vmxnet3_tx_ctx *ctx, 913 struct vmxnet3_adapter *adapter) 914 { 915 struct Vmxnet3_TxDataDesc *tdd; 916 917 tdd = (struct Vmxnet3_TxDataDesc *)((u8 *)tq->data_ring.base + 918 tq->tx_ring.next2fill * 919 tq->txdata_desc_size); 920 921 memcpy(tdd->data, skb->data, ctx->copy_size); 922 netdev_dbg(adapter->netdev, 923 "copy %u bytes to dataRing[%u]\n", 924 ctx->copy_size, tq->tx_ring.next2fill); 925 } 926 927 928 static void 929 vmxnet3_prepare_tso(struct sk_buff *skb, 930 struct vmxnet3_tx_ctx *ctx) 931 { 932 struct tcphdr *tcph = tcp_hdr(skb); 933 934 if (ctx->ipv4) { 935 struct iphdr *iph = ip_hdr(skb); 936 937 iph->check = 0; 938 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0, 939 IPPROTO_TCP, 0); 940 } else if (ctx->ipv6) { 941 struct ipv6hdr *iph = ipv6_hdr(skb); 942 943 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0, 944 IPPROTO_TCP, 0); 945 } 946 } 947 948 static int txd_estimate(const struct sk_buff *skb) 949 { 950 int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1; 951 int i; 952 953 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 954 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 955 956 count += VMXNET3_TXD_NEEDED(skb_frag_size(frag)); 957 } 958 return count; 959 } 960 961 /* 962 * Transmits a pkt thru a given tq 963 * Returns: 964 * NETDEV_TX_OK: descriptors are setup successfully 965 * NETDEV_TX_OK: error occurred, the pkt is dropped 966 * NETDEV_TX_BUSY: tx ring is full, queue is stopped 967 * 968 * Side-effects: 969 * 1. tx ring may be changed 970 * 2. tq stats may be updated accordingly 971 * 3. shared->txNumDeferred may be updated 972 */ 973 974 static int 975 vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 976 struct vmxnet3_adapter *adapter, struct net_device *netdev) 977 { 978 int ret; 979 u32 count; 980 int num_pkts; 981 int tx_num_deferred; 982 unsigned long flags; 983 struct vmxnet3_tx_ctx ctx; 984 union Vmxnet3_GenericDesc *gdesc; 985 #ifdef __BIG_ENDIAN_BITFIELD 986 /* Use temporary descriptor to avoid touching bits multiple times */ 987 union Vmxnet3_GenericDesc tempTxDesc; 988 #endif 989 990 count = txd_estimate(skb); 991 992 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP)); 993 ctx.ipv6 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IPV6)); 994 995 ctx.mss = skb_shinfo(skb)->gso_size; 996 if (ctx.mss) { 997 if (skb_header_cloned(skb)) { 998 if (unlikely(pskb_expand_head(skb, 0, 0, 999 GFP_ATOMIC) != 0)) { 1000 tq->stats.drop_tso++; 1001 goto drop_pkt; 1002 } 1003 tq->stats.copy_skb_header++; 1004 } 1005 vmxnet3_prepare_tso(skb, &ctx); 1006 } else { 1007 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) { 1008 1009 /* non-tso pkts must not use more than 1010 * VMXNET3_MAX_TXD_PER_PKT entries 1011 */ 1012 if (skb_linearize(skb) != 0) { 1013 tq->stats.drop_too_many_frags++; 1014 goto drop_pkt; 1015 } 1016 tq->stats.linearized++; 1017 1018 /* recalculate the # of descriptors to use */ 1019 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1; 1020 } 1021 } 1022 1023 ret = vmxnet3_parse_hdr(skb, tq, &ctx, adapter); 1024 if (ret >= 0) { 1025 BUG_ON(ret <= 0 && ctx.copy_size != 0); 1026 /* hdrs parsed, check against other limits */ 1027 if (ctx.mss) { 1028 if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size > 1029 VMXNET3_MAX_TX_BUF_SIZE)) { 1030 tq->stats.drop_oversized_hdr++; 1031 goto drop_pkt; 1032 } 1033 } else { 1034 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1035 if (unlikely(ctx.eth_ip_hdr_size + 1036 skb->csum_offset > 1037 VMXNET3_MAX_CSUM_OFFSET)) { 1038 tq->stats.drop_oversized_hdr++; 1039 goto drop_pkt; 1040 } 1041 } 1042 } 1043 } else { 1044 tq->stats.drop_hdr_inspect_err++; 1045 goto drop_pkt; 1046 } 1047 1048 spin_lock_irqsave(&tq->tx_lock, flags); 1049 1050 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) { 1051 tq->stats.tx_ring_full++; 1052 netdev_dbg(adapter->netdev, 1053 "tx queue stopped on %s, next2comp %u" 1054 " next2fill %u\n", adapter->netdev->name, 1055 tq->tx_ring.next2comp, tq->tx_ring.next2fill); 1056 1057 vmxnet3_tq_stop(tq, adapter); 1058 spin_unlock_irqrestore(&tq->tx_lock, flags); 1059 return NETDEV_TX_BUSY; 1060 } 1061 1062 1063 vmxnet3_copy_hdr(skb, tq, &ctx, adapter); 1064 1065 /* fill tx descs related to addr & len */ 1066 if (vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter)) 1067 goto unlock_drop_pkt; 1068 1069 /* setup the EOP desc */ 1070 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP); 1071 1072 /* setup the SOP desc */ 1073 #ifdef __BIG_ENDIAN_BITFIELD 1074 gdesc = &tempTxDesc; 1075 gdesc->dword[2] = ctx.sop_txd->dword[2]; 1076 gdesc->dword[3] = ctx.sop_txd->dword[3]; 1077 #else 1078 gdesc = ctx.sop_txd; 1079 #endif 1080 tx_num_deferred = le32_to_cpu(tq->shared->txNumDeferred); 1081 if (ctx.mss) { 1082 gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size; 1083 gdesc->txd.om = VMXNET3_OM_TSO; 1084 gdesc->txd.msscof = ctx.mss; 1085 num_pkts = (skb->len - gdesc->txd.hlen + ctx.mss - 1) / ctx.mss; 1086 } else { 1087 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1088 gdesc->txd.hlen = ctx.eth_ip_hdr_size; 1089 gdesc->txd.om = VMXNET3_OM_CSUM; 1090 gdesc->txd.msscof = ctx.eth_ip_hdr_size + 1091 skb->csum_offset; 1092 } else { 1093 gdesc->txd.om = 0; 1094 gdesc->txd.msscof = 0; 1095 } 1096 num_pkts = 1; 1097 } 1098 le32_add_cpu(&tq->shared->txNumDeferred, num_pkts); 1099 tx_num_deferred += num_pkts; 1100 1101 if (skb_vlan_tag_present(skb)) { 1102 gdesc->txd.ti = 1; 1103 gdesc->txd.tci = skb_vlan_tag_get(skb); 1104 } 1105 1106 /* finally flips the GEN bit of the SOP desc. */ 1107 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^ 1108 VMXNET3_TXD_GEN); 1109 #ifdef __BIG_ENDIAN_BITFIELD 1110 /* Finished updating in bitfields of Tx Desc, so write them in original 1111 * place. 1112 */ 1113 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc, 1114 (struct Vmxnet3_TxDesc *)ctx.sop_txd); 1115 gdesc = ctx.sop_txd; 1116 #endif 1117 netdev_dbg(adapter->netdev, 1118 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n", 1119 (u32)(ctx.sop_txd - 1120 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr), 1121 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3])); 1122 1123 spin_unlock_irqrestore(&tq->tx_lock, flags); 1124 1125 if (tx_num_deferred >= le32_to_cpu(tq->shared->txThreshold)) { 1126 tq->shared->txNumDeferred = 0; 1127 VMXNET3_WRITE_BAR0_REG(adapter, 1128 VMXNET3_REG_TXPROD + tq->qid * 8, 1129 tq->tx_ring.next2fill); 1130 } 1131 1132 return NETDEV_TX_OK; 1133 1134 unlock_drop_pkt: 1135 spin_unlock_irqrestore(&tq->tx_lock, flags); 1136 drop_pkt: 1137 tq->stats.drop_total++; 1138 dev_kfree_skb_any(skb); 1139 return NETDEV_TX_OK; 1140 } 1141 1142 1143 static netdev_tx_t 1144 vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 1145 { 1146 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1147 1148 BUG_ON(skb->queue_mapping > adapter->num_tx_queues); 1149 return vmxnet3_tq_xmit(skb, 1150 &adapter->tx_queue[skb->queue_mapping], 1151 adapter, netdev); 1152 } 1153 1154 1155 static void 1156 vmxnet3_rx_csum(struct vmxnet3_adapter *adapter, 1157 struct sk_buff *skb, 1158 union Vmxnet3_GenericDesc *gdesc) 1159 { 1160 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) { 1161 if (gdesc->rcd.v4 && 1162 (le32_to_cpu(gdesc->dword[3]) & 1163 VMXNET3_RCD_CSUM_OK) == VMXNET3_RCD_CSUM_OK) { 1164 skb->ip_summed = CHECKSUM_UNNECESSARY; 1165 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp)); 1166 BUG_ON(gdesc->rcd.frg); 1167 } else if (gdesc->rcd.v6 && (le32_to_cpu(gdesc->dword[3]) & 1168 (1 << VMXNET3_RCD_TUC_SHIFT))) { 1169 skb->ip_summed = CHECKSUM_UNNECESSARY; 1170 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp)); 1171 BUG_ON(gdesc->rcd.frg); 1172 } else { 1173 if (gdesc->rcd.csum) { 1174 skb->csum = htons(gdesc->rcd.csum); 1175 skb->ip_summed = CHECKSUM_PARTIAL; 1176 } else { 1177 skb_checksum_none_assert(skb); 1178 } 1179 } 1180 } else { 1181 skb_checksum_none_assert(skb); 1182 } 1183 } 1184 1185 1186 static void 1187 vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd, 1188 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter) 1189 { 1190 rq->stats.drop_err++; 1191 if (!rcd->fcs) 1192 rq->stats.drop_fcs++; 1193 1194 rq->stats.drop_total++; 1195 1196 /* 1197 * We do not unmap and chain the rx buffer to the skb. 1198 * We basically pretend this buffer is not used and will be recycled 1199 * by vmxnet3_rq_alloc_rx_buf() 1200 */ 1201 1202 /* 1203 * ctx->skb may be NULL if this is the first and the only one 1204 * desc for the pkt 1205 */ 1206 if (ctx->skb) 1207 dev_kfree_skb_irq(ctx->skb); 1208 1209 ctx->skb = NULL; 1210 } 1211 1212 1213 static u32 1214 vmxnet3_get_hdr_len(struct vmxnet3_adapter *adapter, struct sk_buff *skb, 1215 union Vmxnet3_GenericDesc *gdesc) 1216 { 1217 u32 hlen, maplen; 1218 union { 1219 void *ptr; 1220 struct ethhdr *eth; 1221 struct iphdr *ipv4; 1222 struct ipv6hdr *ipv6; 1223 struct tcphdr *tcp; 1224 } hdr; 1225 BUG_ON(gdesc->rcd.tcp == 0); 1226 1227 maplen = skb_headlen(skb); 1228 if (unlikely(sizeof(struct iphdr) + sizeof(struct tcphdr) > maplen)) 1229 return 0; 1230 1231 hdr.eth = eth_hdr(skb); 1232 if (gdesc->rcd.v4) { 1233 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IP)); 1234 hdr.ptr += sizeof(struct ethhdr); 1235 BUG_ON(hdr.ipv4->protocol != IPPROTO_TCP); 1236 hlen = hdr.ipv4->ihl << 2; 1237 hdr.ptr += hdr.ipv4->ihl << 2; 1238 } else if (gdesc->rcd.v6) { 1239 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IPV6)); 1240 hdr.ptr += sizeof(struct ethhdr); 1241 /* Use an estimated value, since we also need to handle 1242 * TSO case. 1243 */ 1244 if (hdr.ipv6->nexthdr != IPPROTO_TCP) 1245 return sizeof(struct ipv6hdr) + sizeof(struct tcphdr); 1246 hlen = sizeof(struct ipv6hdr); 1247 hdr.ptr += sizeof(struct ipv6hdr); 1248 } else { 1249 /* Non-IP pkt, dont estimate header length */ 1250 return 0; 1251 } 1252 1253 if (hlen + sizeof(struct tcphdr) > maplen) 1254 return 0; 1255 1256 return (hlen + (hdr.tcp->doff << 2)); 1257 } 1258 1259 static int 1260 vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq, 1261 struct vmxnet3_adapter *adapter, int quota) 1262 { 1263 static const u32 rxprod_reg[2] = { 1264 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2 1265 }; 1266 u32 num_pkts = 0; 1267 bool skip_page_frags = false; 1268 struct Vmxnet3_RxCompDesc *rcd; 1269 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx; 1270 u16 segCnt = 0, mss = 0; 1271 #ifdef __BIG_ENDIAN_BITFIELD 1272 struct Vmxnet3_RxDesc rxCmdDesc; 1273 struct Vmxnet3_RxCompDesc rxComp; 1274 #endif 1275 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, 1276 &rxComp); 1277 while (rcd->gen == rq->comp_ring.gen) { 1278 struct vmxnet3_rx_buf_info *rbi; 1279 struct sk_buff *skb, *new_skb = NULL; 1280 struct page *new_page = NULL; 1281 dma_addr_t new_dma_addr; 1282 int num_to_alloc; 1283 struct Vmxnet3_RxDesc *rxd; 1284 u32 idx, ring_idx; 1285 struct vmxnet3_cmd_ring *ring = NULL; 1286 if (num_pkts >= quota) { 1287 /* we may stop even before we see the EOP desc of 1288 * the current pkt 1289 */ 1290 break; 1291 } 1292 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2 && 1293 rcd->rqID != rq->dataRingQid); 1294 idx = rcd->rxdIdx; 1295 ring_idx = VMXNET3_GET_RING_IDX(adapter, rcd->rqID); 1296 ring = rq->rx_ring + ring_idx; 1297 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd, 1298 &rxCmdDesc); 1299 rbi = rq->buf_info[ring_idx] + idx; 1300 1301 BUG_ON(rxd->addr != rbi->dma_addr || 1302 rxd->len != rbi->len); 1303 1304 if (unlikely(rcd->eop && rcd->err)) { 1305 vmxnet3_rx_error(rq, rcd, ctx, adapter); 1306 goto rcd_done; 1307 } 1308 1309 if (rcd->sop) { /* first buf of the pkt */ 1310 bool rxDataRingUsed; 1311 u16 len; 1312 1313 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD || 1314 (rcd->rqID != rq->qid && 1315 rcd->rqID != rq->dataRingQid)); 1316 1317 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB); 1318 BUG_ON(ctx->skb != NULL || rbi->skb == NULL); 1319 1320 if (unlikely(rcd->len == 0)) { 1321 /* Pretend the rx buffer is skipped. */ 1322 BUG_ON(!(rcd->sop && rcd->eop)); 1323 netdev_dbg(adapter->netdev, 1324 "rxRing[%u][%u] 0 length\n", 1325 ring_idx, idx); 1326 goto rcd_done; 1327 } 1328 1329 skip_page_frags = false; 1330 ctx->skb = rbi->skb; 1331 1332 rxDataRingUsed = 1333 VMXNET3_RX_DATA_RING(adapter, rcd->rqID); 1334 len = rxDataRingUsed ? rcd->len : rbi->len; 1335 new_skb = netdev_alloc_skb_ip_align(adapter->netdev, 1336 len); 1337 if (new_skb == NULL) { 1338 /* Skb allocation failed, do not handover this 1339 * skb to stack. Reuse it. Drop the existing pkt 1340 */ 1341 rq->stats.rx_buf_alloc_failure++; 1342 ctx->skb = NULL; 1343 rq->stats.drop_total++; 1344 skip_page_frags = true; 1345 goto rcd_done; 1346 } 1347 1348 if (rxDataRingUsed) { 1349 size_t sz; 1350 1351 BUG_ON(rcd->len > rq->data_ring.desc_size); 1352 1353 ctx->skb = new_skb; 1354 sz = rcd->rxdIdx * rq->data_ring.desc_size; 1355 memcpy(new_skb->data, 1356 &rq->data_ring.base[sz], rcd->len); 1357 } else { 1358 ctx->skb = rbi->skb; 1359 1360 new_dma_addr = 1361 dma_map_single(&adapter->pdev->dev, 1362 new_skb->data, rbi->len, 1363 PCI_DMA_FROMDEVICE); 1364 if (dma_mapping_error(&adapter->pdev->dev, 1365 new_dma_addr)) { 1366 dev_kfree_skb(new_skb); 1367 /* Skb allocation failed, do not 1368 * handover this skb to stack. Reuse 1369 * it. Drop the existing pkt. 1370 */ 1371 rq->stats.rx_buf_alloc_failure++; 1372 ctx->skb = NULL; 1373 rq->stats.drop_total++; 1374 skip_page_frags = true; 1375 goto rcd_done; 1376 } 1377 1378 dma_unmap_single(&adapter->pdev->dev, 1379 rbi->dma_addr, 1380 rbi->len, 1381 PCI_DMA_FROMDEVICE); 1382 1383 /* Immediate refill */ 1384 rbi->skb = new_skb; 1385 rbi->dma_addr = new_dma_addr; 1386 rxd->addr = cpu_to_le64(rbi->dma_addr); 1387 rxd->len = rbi->len; 1388 } 1389 1390 #ifdef VMXNET3_RSS 1391 if (rcd->rssType != VMXNET3_RCD_RSS_TYPE_NONE && 1392 (adapter->netdev->features & NETIF_F_RXHASH)) 1393 skb_set_hash(ctx->skb, 1394 le32_to_cpu(rcd->rssHash), 1395 PKT_HASH_TYPE_L3); 1396 #endif 1397 skb_put(ctx->skb, rcd->len); 1398 1399 if (VMXNET3_VERSION_GE_2(adapter) && 1400 rcd->type == VMXNET3_CDTYPE_RXCOMP_LRO) { 1401 struct Vmxnet3_RxCompDescExt *rcdlro; 1402 rcdlro = (struct Vmxnet3_RxCompDescExt *)rcd; 1403 1404 segCnt = rcdlro->segCnt; 1405 WARN_ON_ONCE(segCnt == 0); 1406 mss = rcdlro->mss; 1407 if (unlikely(segCnt <= 1)) 1408 segCnt = 0; 1409 } else { 1410 segCnt = 0; 1411 } 1412 } else { 1413 BUG_ON(ctx->skb == NULL && !skip_page_frags); 1414 1415 /* non SOP buffer must be type 1 in most cases */ 1416 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE); 1417 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY); 1418 1419 /* If an sop buffer was dropped, skip all 1420 * following non-sop fragments. They will be reused. 1421 */ 1422 if (skip_page_frags) 1423 goto rcd_done; 1424 1425 if (rcd->len) { 1426 new_page = alloc_page(GFP_ATOMIC); 1427 /* Replacement page frag could not be allocated. 1428 * Reuse this page. Drop the pkt and free the 1429 * skb which contained this page as a frag. Skip 1430 * processing all the following non-sop frags. 1431 */ 1432 if (unlikely(!new_page)) { 1433 rq->stats.rx_buf_alloc_failure++; 1434 dev_kfree_skb(ctx->skb); 1435 ctx->skb = NULL; 1436 skip_page_frags = true; 1437 goto rcd_done; 1438 } 1439 new_dma_addr = dma_map_page(&adapter->pdev->dev, 1440 new_page, 1441 0, PAGE_SIZE, 1442 PCI_DMA_FROMDEVICE); 1443 if (dma_mapping_error(&adapter->pdev->dev, 1444 new_dma_addr)) { 1445 put_page(new_page); 1446 rq->stats.rx_buf_alloc_failure++; 1447 dev_kfree_skb(ctx->skb); 1448 ctx->skb = NULL; 1449 skip_page_frags = true; 1450 goto rcd_done; 1451 } 1452 1453 dma_unmap_page(&adapter->pdev->dev, 1454 rbi->dma_addr, rbi->len, 1455 PCI_DMA_FROMDEVICE); 1456 1457 vmxnet3_append_frag(ctx->skb, rcd, rbi); 1458 1459 /* Immediate refill */ 1460 rbi->page = new_page; 1461 rbi->dma_addr = new_dma_addr; 1462 rxd->addr = cpu_to_le64(rbi->dma_addr); 1463 rxd->len = rbi->len; 1464 } 1465 } 1466 1467 1468 skb = ctx->skb; 1469 if (rcd->eop) { 1470 u32 mtu = adapter->netdev->mtu; 1471 skb->len += skb->data_len; 1472 1473 vmxnet3_rx_csum(adapter, skb, 1474 (union Vmxnet3_GenericDesc *)rcd); 1475 skb->protocol = eth_type_trans(skb, adapter->netdev); 1476 if (!rcd->tcp || 1477 !(adapter->netdev->features & NETIF_F_LRO)) 1478 goto not_lro; 1479 1480 if (segCnt != 0 && mss != 0) { 1481 skb_shinfo(skb)->gso_type = rcd->v4 ? 1482 SKB_GSO_TCPV4 : SKB_GSO_TCPV6; 1483 skb_shinfo(skb)->gso_size = mss; 1484 skb_shinfo(skb)->gso_segs = segCnt; 1485 } else if (segCnt != 0 || skb->len > mtu) { 1486 u32 hlen; 1487 1488 hlen = vmxnet3_get_hdr_len(adapter, skb, 1489 (union Vmxnet3_GenericDesc *)rcd); 1490 if (hlen == 0) 1491 goto not_lro; 1492 1493 skb_shinfo(skb)->gso_type = 1494 rcd->v4 ? SKB_GSO_TCPV4 : SKB_GSO_TCPV6; 1495 if (segCnt != 0) { 1496 skb_shinfo(skb)->gso_segs = segCnt; 1497 skb_shinfo(skb)->gso_size = 1498 DIV_ROUND_UP(skb->len - 1499 hlen, segCnt); 1500 } else { 1501 skb_shinfo(skb)->gso_size = mtu - hlen; 1502 } 1503 } 1504 not_lro: 1505 if (unlikely(rcd->ts)) 1506 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rcd->tci); 1507 1508 if (adapter->netdev->features & NETIF_F_LRO) 1509 netif_receive_skb(skb); 1510 else 1511 napi_gro_receive(&rq->napi, skb); 1512 1513 ctx->skb = NULL; 1514 num_pkts++; 1515 } 1516 1517 rcd_done: 1518 /* device may have skipped some rx descs */ 1519 ring->next2comp = idx; 1520 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring); 1521 ring = rq->rx_ring + ring_idx; 1522 while (num_to_alloc) { 1523 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd, 1524 &rxCmdDesc); 1525 BUG_ON(!rxd->addr); 1526 1527 /* Recv desc is ready to be used by the device */ 1528 rxd->gen = ring->gen; 1529 vmxnet3_cmd_ring_adv_next2fill(ring); 1530 num_to_alloc--; 1531 } 1532 1533 /* if needed, update the register */ 1534 if (unlikely(rq->shared->updateRxProd)) { 1535 VMXNET3_WRITE_BAR0_REG(adapter, 1536 rxprod_reg[ring_idx] + rq->qid * 8, 1537 ring->next2fill); 1538 } 1539 1540 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring); 1541 vmxnet3_getRxComp(rcd, 1542 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp); 1543 } 1544 1545 return num_pkts; 1546 } 1547 1548 1549 static void 1550 vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq, 1551 struct vmxnet3_adapter *adapter) 1552 { 1553 u32 i, ring_idx; 1554 struct Vmxnet3_RxDesc *rxd; 1555 1556 for (ring_idx = 0; ring_idx < 2; ring_idx++) { 1557 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) { 1558 #ifdef __BIG_ENDIAN_BITFIELD 1559 struct Vmxnet3_RxDesc rxDesc; 1560 #endif 1561 vmxnet3_getRxDesc(rxd, 1562 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc); 1563 1564 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD && 1565 rq->buf_info[ring_idx][i].skb) { 1566 dma_unmap_single(&adapter->pdev->dev, rxd->addr, 1567 rxd->len, PCI_DMA_FROMDEVICE); 1568 dev_kfree_skb(rq->buf_info[ring_idx][i].skb); 1569 rq->buf_info[ring_idx][i].skb = NULL; 1570 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY && 1571 rq->buf_info[ring_idx][i].page) { 1572 dma_unmap_page(&adapter->pdev->dev, rxd->addr, 1573 rxd->len, PCI_DMA_FROMDEVICE); 1574 put_page(rq->buf_info[ring_idx][i].page); 1575 rq->buf_info[ring_idx][i].page = NULL; 1576 } 1577 } 1578 1579 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN; 1580 rq->rx_ring[ring_idx].next2fill = 1581 rq->rx_ring[ring_idx].next2comp = 0; 1582 } 1583 1584 rq->comp_ring.gen = VMXNET3_INIT_GEN; 1585 rq->comp_ring.next2proc = 0; 1586 } 1587 1588 1589 static void 1590 vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter) 1591 { 1592 int i; 1593 1594 for (i = 0; i < adapter->num_rx_queues; i++) 1595 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter); 1596 } 1597 1598 1599 static void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq, 1600 struct vmxnet3_adapter *adapter) 1601 { 1602 int i; 1603 int j; 1604 1605 /* all rx buffers must have already been freed */ 1606 for (i = 0; i < 2; i++) { 1607 if (rq->buf_info[i]) { 1608 for (j = 0; j < rq->rx_ring[i].size; j++) 1609 BUG_ON(rq->buf_info[i][j].page != NULL); 1610 } 1611 } 1612 1613 1614 for (i = 0; i < 2; i++) { 1615 if (rq->rx_ring[i].base) { 1616 dma_free_coherent(&adapter->pdev->dev, 1617 rq->rx_ring[i].size 1618 * sizeof(struct Vmxnet3_RxDesc), 1619 rq->rx_ring[i].base, 1620 rq->rx_ring[i].basePA); 1621 rq->rx_ring[i].base = NULL; 1622 } 1623 } 1624 1625 if (rq->data_ring.base) { 1626 dma_free_coherent(&adapter->pdev->dev, 1627 rq->rx_ring[0].size * rq->data_ring.desc_size, 1628 rq->data_ring.base, rq->data_ring.basePA); 1629 rq->data_ring.base = NULL; 1630 } 1631 1632 if (rq->comp_ring.base) { 1633 dma_free_coherent(&adapter->pdev->dev, rq->comp_ring.size 1634 * sizeof(struct Vmxnet3_RxCompDesc), 1635 rq->comp_ring.base, rq->comp_ring.basePA); 1636 rq->comp_ring.base = NULL; 1637 } 1638 1639 if (rq->buf_info[0]) { 1640 size_t sz = sizeof(struct vmxnet3_rx_buf_info) * 1641 (rq->rx_ring[0].size + rq->rx_ring[1].size); 1642 dma_free_coherent(&adapter->pdev->dev, sz, rq->buf_info[0], 1643 rq->buf_info_pa); 1644 rq->buf_info[0] = rq->buf_info[1] = NULL; 1645 } 1646 } 1647 1648 static void 1649 vmxnet3_rq_destroy_all_rxdataring(struct vmxnet3_adapter *adapter) 1650 { 1651 int i; 1652 1653 for (i = 0; i < adapter->num_rx_queues; i++) { 1654 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 1655 1656 if (rq->data_ring.base) { 1657 dma_free_coherent(&adapter->pdev->dev, 1658 (rq->rx_ring[0].size * 1659 rq->data_ring.desc_size), 1660 rq->data_ring.base, 1661 rq->data_ring.basePA); 1662 rq->data_ring.base = NULL; 1663 rq->data_ring.desc_size = 0; 1664 } 1665 } 1666 } 1667 1668 static int 1669 vmxnet3_rq_init(struct vmxnet3_rx_queue *rq, 1670 struct vmxnet3_adapter *adapter) 1671 { 1672 int i; 1673 1674 /* initialize buf_info */ 1675 for (i = 0; i < rq->rx_ring[0].size; i++) { 1676 1677 /* 1st buf for a pkt is skbuff */ 1678 if (i % adapter->rx_buf_per_pkt == 0) { 1679 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB; 1680 rq->buf_info[0][i].len = adapter->skb_buf_size; 1681 } else { /* subsequent bufs for a pkt is frag */ 1682 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE; 1683 rq->buf_info[0][i].len = PAGE_SIZE; 1684 } 1685 } 1686 for (i = 0; i < rq->rx_ring[1].size; i++) { 1687 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE; 1688 rq->buf_info[1][i].len = PAGE_SIZE; 1689 } 1690 1691 /* reset internal state and allocate buffers for both rings */ 1692 for (i = 0; i < 2; i++) { 1693 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0; 1694 1695 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size * 1696 sizeof(struct Vmxnet3_RxDesc)); 1697 rq->rx_ring[i].gen = VMXNET3_INIT_GEN; 1698 } 1699 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1, 1700 adapter) == 0) { 1701 /* at least has 1 rx buffer for the 1st ring */ 1702 return -ENOMEM; 1703 } 1704 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter); 1705 1706 /* reset the comp ring */ 1707 rq->comp_ring.next2proc = 0; 1708 memset(rq->comp_ring.base, 0, rq->comp_ring.size * 1709 sizeof(struct Vmxnet3_RxCompDesc)); 1710 rq->comp_ring.gen = VMXNET3_INIT_GEN; 1711 1712 /* reset rxctx */ 1713 rq->rx_ctx.skb = NULL; 1714 1715 /* stats are not reset */ 1716 return 0; 1717 } 1718 1719 1720 static int 1721 vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter) 1722 { 1723 int i, err = 0; 1724 1725 for (i = 0; i < adapter->num_rx_queues; i++) { 1726 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter); 1727 if (unlikely(err)) { 1728 dev_err(&adapter->netdev->dev, "%s: failed to " 1729 "initialize rx queue%i\n", 1730 adapter->netdev->name, i); 1731 break; 1732 } 1733 } 1734 return err; 1735 1736 } 1737 1738 1739 static int 1740 vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter) 1741 { 1742 int i; 1743 size_t sz; 1744 struct vmxnet3_rx_buf_info *bi; 1745 1746 for (i = 0; i < 2; i++) { 1747 1748 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc); 1749 rq->rx_ring[i].base = dma_alloc_coherent( 1750 &adapter->pdev->dev, sz, 1751 &rq->rx_ring[i].basePA, 1752 GFP_KERNEL); 1753 if (!rq->rx_ring[i].base) { 1754 netdev_err(adapter->netdev, 1755 "failed to allocate rx ring %d\n", i); 1756 goto err; 1757 } 1758 } 1759 1760 if ((adapter->rxdataring_enabled) && (rq->data_ring.desc_size != 0)) { 1761 sz = rq->rx_ring[0].size * rq->data_ring.desc_size; 1762 rq->data_ring.base = 1763 dma_alloc_coherent(&adapter->pdev->dev, sz, 1764 &rq->data_ring.basePA, 1765 GFP_KERNEL); 1766 if (!rq->data_ring.base) { 1767 netdev_err(adapter->netdev, 1768 "rx data ring will be disabled\n"); 1769 adapter->rxdataring_enabled = false; 1770 } 1771 } else { 1772 rq->data_ring.base = NULL; 1773 rq->data_ring.desc_size = 0; 1774 } 1775 1776 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc); 1777 rq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, sz, 1778 &rq->comp_ring.basePA, 1779 GFP_KERNEL); 1780 if (!rq->comp_ring.base) { 1781 netdev_err(adapter->netdev, "failed to allocate rx comp ring\n"); 1782 goto err; 1783 } 1784 1785 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size + 1786 rq->rx_ring[1].size); 1787 bi = dma_zalloc_coherent(&adapter->pdev->dev, sz, &rq->buf_info_pa, 1788 GFP_KERNEL); 1789 if (!bi) 1790 goto err; 1791 1792 rq->buf_info[0] = bi; 1793 rq->buf_info[1] = bi + rq->rx_ring[0].size; 1794 1795 return 0; 1796 1797 err: 1798 vmxnet3_rq_destroy(rq, adapter); 1799 return -ENOMEM; 1800 } 1801 1802 1803 static int 1804 vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter) 1805 { 1806 int i, err = 0; 1807 1808 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter); 1809 1810 for (i = 0; i < adapter->num_rx_queues; i++) { 1811 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter); 1812 if (unlikely(err)) { 1813 dev_err(&adapter->netdev->dev, 1814 "%s: failed to create rx queue%i\n", 1815 adapter->netdev->name, i); 1816 goto err_out; 1817 } 1818 } 1819 1820 if (!adapter->rxdataring_enabled) 1821 vmxnet3_rq_destroy_all_rxdataring(adapter); 1822 1823 return err; 1824 err_out: 1825 vmxnet3_rq_destroy_all(adapter); 1826 return err; 1827 1828 } 1829 1830 /* Multiple queue aware polling function for tx and rx */ 1831 1832 static int 1833 vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget) 1834 { 1835 int rcd_done = 0, i; 1836 if (unlikely(adapter->shared->ecr)) 1837 vmxnet3_process_events(adapter); 1838 for (i = 0; i < adapter->num_tx_queues; i++) 1839 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter); 1840 1841 for (i = 0; i < adapter->num_rx_queues; i++) 1842 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i], 1843 adapter, budget); 1844 return rcd_done; 1845 } 1846 1847 1848 static int 1849 vmxnet3_poll(struct napi_struct *napi, int budget) 1850 { 1851 struct vmxnet3_rx_queue *rx_queue = container_of(napi, 1852 struct vmxnet3_rx_queue, napi); 1853 int rxd_done; 1854 1855 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget); 1856 1857 if (rxd_done < budget) { 1858 napi_complete_done(napi, rxd_done); 1859 vmxnet3_enable_all_intrs(rx_queue->adapter); 1860 } 1861 return rxd_done; 1862 } 1863 1864 /* 1865 * NAPI polling function for MSI-X mode with multiple Rx queues 1866 * Returns the # of the NAPI credit consumed (# of rx descriptors processed) 1867 */ 1868 1869 static int 1870 vmxnet3_poll_rx_only(struct napi_struct *napi, int budget) 1871 { 1872 struct vmxnet3_rx_queue *rq = container_of(napi, 1873 struct vmxnet3_rx_queue, napi); 1874 struct vmxnet3_adapter *adapter = rq->adapter; 1875 int rxd_done; 1876 1877 /* When sharing interrupt with corresponding tx queue, process 1878 * tx completions in that queue as well 1879 */ 1880 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) { 1881 struct vmxnet3_tx_queue *tq = 1882 &adapter->tx_queue[rq - adapter->rx_queue]; 1883 vmxnet3_tq_tx_complete(tq, adapter); 1884 } 1885 1886 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget); 1887 1888 if (rxd_done < budget) { 1889 napi_complete_done(napi, rxd_done); 1890 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx); 1891 } 1892 return rxd_done; 1893 } 1894 1895 1896 #ifdef CONFIG_PCI_MSI 1897 1898 /* 1899 * Handle completion interrupts on tx queues 1900 * Returns whether or not the intr is handled 1901 */ 1902 1903 static irqreturn_t 1904 vmxnet3_msix_tx(int irq, void *data) 1905 { 1906 struct vmxnet3_tx_queue *tq = data; 1907 struct vmxnet3_adapter *adapter = tq->adapter; 1908 1909 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1910 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx); 1911 1912 /* Handle the case where only one irq is allocate for all tx queues */ 1913 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) { 1914 int i; 1915 for (i = 0; i < adapter->num_tx_queues; i++) { 1916 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i]; 1917 vmxnet3_tq_tx_complete(txq, adapter); 1918 } 1919 } else { 1920 vmxnet3_tq_tx_complete(tq, adapter); 1921 } 1922 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx); 1923 1924 return IRQ_HANDLED; 1925 } 1926 1927 1928 /* 1929 * Handle completion interrupts on rx queues. Returns whether or not the 1930 * intr is handled 1931 */ 1932 1933 static irqreturn_t 1934 vmxnet3_msix_rx(int irq, void *data) 1935 { 1936 struct vmxnet3_rx_queue *rq = data; 1937 struct vmxnet3_adapter *adapter = rq->adapter; 1938 1939 /* disable intr if needed */ 1940 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1941 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx); 1942 napi_schedule(&rq->napi); 1943 1944 return IRQ_HANDLED; 1945 } 1946 1947 /* 1948 *---------------------------------------------------------------------------- 1949 * 1950 * vmxnet3_msix_event -- 1951 * 1952 * vmxnet3 msix event intr handler 1953 * 1954 * Result: 1955 * whether or not the intr is handled 1956 * 1957 *---------------------------------------------------------------------------- 1958 */ 1959 1960 static irqreturn_t 1961 vmxnet3_msix_event(int irq, void *data) 1962 { 1963 struct net_device *dev = data; 1964 struct vmxnet3_adapter *adapter = netdev_priv(dev); 1965 1966 /* disable intr if needed */ 1967 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1968 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx); 1969 1970 if (adapter->shared->ecr) 1971 vmxnet3_process_events(adapter); 1972 1973 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx); 1974 1975 return IRQ_HANDLED; 1976 } 1977 1978 #endif /* CONFIG_PCI_MSI */ 1979 1980 1981 /* Interrupt handler for vmxnet3 */ 1982 static irqreturn_t 1983 vmxnet3_intr(int irq, void *dev_id) 1984 { 1985 struct net_device *dev = dev_id; 1986 struct vmxnet3_adapter *adapter = netdev_priv(dev); 1987 1988 if (adapter->intr.type == VMXNET3_IT_INTX) { 1989 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR); 1990 if (unlikely(icr == 0)) 1991 /* not ours */ 1992 return IRQ_NONE; 1993 } 1994 1995 1996 /* disable intr if needed */ 1997 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1998 vmxnet3_disable_all_intrs(adapter); 1999 2000 napi_schedule(&adapter->rx_queue[0].napi); 2001 2002 return IRQ_HANDLED; 2003 } 2004 2005 #ifdef CONFIG_NET_POLL_CONTROLLER 2006 2007 /* netpoll callback. */ 2008 static void 2009 vmxnet3_netpoll(struct net_device *netdev) 2010 { 2011 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2012 2013 switch (adapter->intr.type) { 2014 #ifdef CONFIG_PCI_MSI 2015 case VMXNET3_IT_MSIX: { 2016 int i; 2017 for (i = 0; i < adapter->num_rx_queues; i++) 2018 vmxnet3_msix_rx(0, &adapter->rx_queue[i]); 2019 break; 2020 } 2021 #endif 2022 case VMXNET3_IT_MSI: 2023 default: 2024 vmxnet3_intr(0, adapter->netdev); 2025 break; 2026 } 2027 2028 } 2029 #endif /* CONFIG_NET_POLL_CONTROLLER */ 2030 2031 static int 2032 vmxnet3_request_irqs(struct vmxnet3_adapter *adapter) 2033 { 2034 struct vmxnet3_intr *intr = &adapter->intr; 2035 int err = 0, i; 2036 int vector = 0; 2037 2038 #ifdef CONFIG_PCI_MSI 2039 if (adapter->intr.type == VMXNET3_IT_MSIX) { 2040 for (i = 0; i < adapter->num_tx_queues; i++) { 2041 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) { 2042 sprintf(adapter->tx_queue[i].name, "%s-tx-%d", 2043 adapter->netdev->name, vector); 2044 err = request_irq( 2045 intr->msix_entries[vector].vector, 2046 vmxnet3_msix_tx, 0, 2047 adapter->tx_queue[i].name, 2048 &adapter->tx_queue[i]); 2049 } else { 2050 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d", 2051 adapter->netdev->name, vector); 2052 } 2053 if (err) { 2054 dev_err(&adapter->netdev->dev, 2055 "Failed to request irq for MSIX, %s, " 2056 "error %d\n", 2057 adapter->tx_queue[i].name, err); 2058 return err; 2059 } 2060 2061 /* Handle the case where only 1 MSIx was allocated for 2062 * all tx queues */ 2063 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) { 2064 for (; i < adapter->num_tx_queues; i++) 2065 adapter->tx_queue[i].comp_ring.intr_idx 2066 = vector; 2067 vector++; 2068 break; 2069 } else { 2070 adapter->tx_queue[i].comp_ring.intr_idx 2071 = vector++; 2072 } 2073 } 2074 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) 2075 vector = 0; 2076 2077 for (i = 0; i < adapter->num_rx_queues; i++) { 2078 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) 2079 sprintf(adapter->rx_queue[i].name, "%s-rx-%d", 2080 adapter->netdev->name, vector); 2081 else 2082 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d", 2083 adapter->netdev->name, vector); 2084 err = request_irq(intr->msix_entries[vector].vector, 2085 vmxnet3_msix_rx, 0, 2086 adapter->rx_queue[i].name, 2087 &(adapter->rx_queue[i])); 2088 if (err) { 2089 netdev_err(adapter->netdev, 2090 "Failed to request irq for MSIX, " 2091 "%s, error %d\n", 2092 adapter->rx_queue[i].name, err); 2093 return err; 2094 } 2095 2096 adapter->rx_queue[i].comp_ring.intr_idx = vector++; 2097 } 2098 2099 sprintf(intr->event_msi_vector_name, "%s-event-%d", 2100 adapter->netdev->name, vector); 2101 err = request_irq(intr->msix_entries[vector].vector, 2102 vmxnet3_msix_event, 0, 2103 intr->event_msi_vector_name, adapter->netdev); 2104 intr->event_intr_idx = vector; 2105 2106 } else if (intr->type == VMXNET3_IT_MSI) { 2107 adapter->num_rx_queues = 1; 2108 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0, 2109 adapter->netdev->name, adapter->netdev); 2110 } else { 2111 #endif 2112 adapter->num_rx_queues = 1; 2113 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 2114 IRQF_SHARED, adapter->netdev->name, 2115 adapter->netdev); 2116 #ifdef CONFIG_PCI_MSI 2117 } 2118 #endif 2119 intr->num_intrs = vector + 1; 2120 if (err) { 2121 netdev_err(adapter->netdev, 2122 "Failed to request irq (intr type:%d), error %d\n", 2123 intr->type, err); 2124 } else { 2125 /* Number of rx queues will not change after this */ 2126 for (i = 0; i < adapter->num_rx_queues; i++) { 2127 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2128 rq->qid = i; 2129 rq->qid2 = i + adapter->num_rx_queues; 2130 rq->dataRingQid = i + 2 * adapter->num_rx_queues; 2131 } 2132 2133 /* init our intr settings */ 2134 for (i = 0; i < intr->num_intrs; i++) 2135 intr->mod_levels[i] = UPT1_IML_ADAPTIVE; 2136 if (adapter->intr.type != VMXNET3_IT_MSIX) { 2137 adapter->intr.event_intr_idx = 0; 2138 for (i = 0; i < adapter->num_tx_queues; i++) 2139 adapter->tx_queue[i].comp_ring.intr_idx = 0; 2140 adapter->rx_queue[0].comp_ring.intr_idx = 0; 2141 } 2142 2143 netdev_info(adapter->netdev, 2144 "intr type %u, mode %u, %u vectors allocated\n", 2145 intr->type, intr->mask_mode, intr->num_intrs); 2146 } 2147 2148 return err; 2149 } 2150 2151 2152 static void 2153 vmxnet3_free_irqs(struct vmxnet3_adapter *adapter) 2154 { 2155 struct vmxnet3_intr *intr = &adapter->intr; 2156 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0); 2157 2158 switch (intr->type) { 2159 #ifdef CONFIG_PCI_MSI 2160 case VMXNET3_IT_MSIX: 2161 { 2162 int i, vector = 0; 2163 2164 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) { 2165 for (i = 0; i < adapter->num_tx_queues; i++) { 2166 free_irq(intr->msix_entries[vector++].vector, 2167 &(adapter->tx_queue[i])); 2168 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) 2169 break; 2170 } 2171 } 2172 2173 for (i = 0; i < adapter->num_rx_queues; i++) { 2174 free_irq(intr->msix_entries[vector++].vector, 2175 &(adapter->rx_queue[i])); 2176 } 2177 2178 free_irq(intr->msix_entries[vector].vector, 2179 adapter->netdev); 2180 BUG_ON(vector >= intr->num_intrs); 2181 break; 2182 } 2183 #endif 2184 case VMXNET3_IT_MSI: 2185 free_irq(adapter->pdev->irq, adapter->netdev); 2186 break; 2187 case VMXNET3_IT_INTX: 2188 free_irq(adapter->pdev->irq, adapter->netdev); 2189 break; 2190 default: 2191 BUG(); 2192 } 2193 } 2194 2195 2196 static void 2197 vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter) 2198 { 2199 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 2200 u16 vid; 2201 2202 /* allow untagged pkts */ 2203 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0); 2204 2205 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2206 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid); 2207 } 2208 2209 2210 static int 2211 vmxnet3_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid) 2212 { 2213 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2214 2215 if (!(netdev->flags & IFF_PROMISC)) { 2216 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 2217 unsigned long flags; 2218 2219 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid); 2220 spin_lock_irqsave(&adapter->cmd_lock, flags); 2221 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2222 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 2223 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2224 } 2225 2226 set_bit(vid, adapter->active_vlans); 2227 2228 return 0; 2229 } 2230 2231 2232 static int 2233 vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid) 2234 { 2235 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2236 2237 if (!(netdev->flags & IFF_PROMISC)) { 2238 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 2239 unsigned long flags; 2240 2241 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid); 2242 spin_lock_irqsave(&adapter->cmd_lock, flags); 2243 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2244 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 2245 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2246 } 2247 2248 clear_bit(vid, adapter->active_vlans); 2249 2250 return 0; 2251 } 2252 2253 2254 static u8 * 2255 vmxnet3_copy_mc(struct net_device *netdev) 2256 { 2257 u8 *buf = NULL; 2258 u32 sz = netdev_mc_count(netdev) * ETH_ALEN; 2259 2260 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */ 2261 if (sz <= 0xffff) { 2262 /* We may be called with BH disabled */ 2263 buf = kmalloc(sz, GFP_ATOMIC); 2264 if (buf) { 2265 struct netdev_hw_addr *ha; 2266 int i = 0; 2267 2268 netdev_for_each_mc_addr(ha, netdev) 2269 memcpy(buf + i++ * ETH_ALEN, ha->addr, 2270 ETH_ALEN); 2271 } 2272 } 2273 return buf; 2274 } 2275 2276 2277 static void 2278 vmxnet3_set_mc(struct net_device *netdev) 2279 { 2280 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2281 unsigned long flags; 2282 struct Vmxnet3_RxFilterConf *rxConf = 2283 &adapter->shared->devRead.rxFilterConf; 2284 u8 *new_table = NULL; 2285 dma_addr_t new_table_pa = 0; 2286 bool new_table_pa_valid = false; 2287 u32 new_mode = VMXNET3_RXM_UCAST; 2288 2289 if (netdev->flags & IFF_PROMISC) { 2290 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 2291 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable)); 2292 2293 new_mode |= VMXNET3_RXM_PROMISC; 2294 } else { 2295 vmxnet3_restore_vlan(adapter); 2296 } 2297 2298 if (netdev->flags & IFF_BROADCAST) 2299 new_mode |= VMXNET3_RXM_BCAST; 2300 2301 if (netdev->flags & IFF_ALLMULTI) 2302 new_mode |= VMXNET3_RXM_ALL_MULTI; 2303 else 2304 if (!netdev_mc_empty(netdev)) { 2305 new_table = vmxnet3_copy_mc(netdev); 2306 if (new_table) { 2307 size_t sz = netdev_mc_count(netdev) * ETH_ALEN; 2308 2309 rxConf->mfTableLen = cpu_to_le16(sz); 2310 new_table_pa = dma_map_single( 2311 &adapter->pdev->dev, 2312 new_table, 2313 sz, 2314 PCI_DMA_TODEVICE); 2315 if (!dma_mapping_error(&adapter->pdev->dev, 2316 new_table_pa)) { 2317 new_mode |= VMXNET3_RXM_MCAST; 2318 new_table_pa_valid = true; 2319 rxConf->mfTablePA = cpu_to_le64( 2320 new_table_pa); 2321 } 2322 } 2323 if (!new_table_pa_valid) { 2324 netdev_info(netdev, 2325 "failed to copy mcast list, setting ALL_MULTI\n"); 2326 new_mode |= VMXNET3_RXM_ALL_MULTI; 2327 } 2328 } 2329 2330 if (!(new_mode & VMXNET3_RXM_MCAST)) { 2331 rxConf->mfTableLen = 0; 2332 rxConf->mfTablePA = 0; 2333 } 2334 2335 spin_lock_irqsave(&adapter->cmd_lock, flags); 2336 if (new_mode != rxConf->rxMode) { 2337 rxConf->rxMode = cpu_to_le32(new_mode); 2338 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2339 VMXNET3_CMD_UPDATE_RX_MODE); 2340 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2341 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 2342 } 2343 2344 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2345 VMXNET3_CMD_UPDATE_MAC_FILTERS); 2346 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2347 2348 if (new_table_pa_valid) 2349 dma_unmap_single(&adapter->pdev->dev, new_table_pa, 2350 rxConf->mfTableLen, PCI_DMA_TODEVICE); 2351 kfree(new_table); 2352 } 2353 2354 void 2355 vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter) 2356 { 2357 int i; 2358 2359 for (i = 0; i < adapter->num_rx_queues; i++) 2360 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter); 2361 } 2362 2363 2364 /* 2365 * Set up driver_shared based on settings in adapter. 2366 */ 2367 2368 static void 2369 vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter) 2370 { 2371 struct Vmxnet3_DriverShared *shared = adapter->shared; 2372 struct Vmxnet3_DSDevRead *devRead = &shared->devRead; 2373 struct Vmxnet3_TxQueueConf *tqc; 2374 struct Vmxnet3_RxQueueConf *rqc; 2375 int i; 2376 2377 memset(shared, 0, sizeof(*shared)); 2378 2379 /* driver settings */ 2380 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC); 2381 devRead->misc.driverInfo.version = cpu_to_le32( 2382 VMXNET3_DRIVER_VERSION_NUM); 2383 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ? 2384 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64); 2385 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 2386 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32( 2387 *((u32 *)&devRead->misc.driverInfo.gos)); 2388 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1); 2389 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1); 2390 2391 devRead->misc.ddPA = cpu_to_le64(adapter->adapter_pa); 2392 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter)); 2393 2394 /* set up feature flags */ 2395 if (adapter->netdev->features & NETIF_F_RXCSUM) 2396 devRead->misc.uptFeatures |= UPT1_F_RXCSUM; 2397 2398 if (adapter->netdev->features & NETIF_F_LRO) { 2399 devRead->misc.uptFeatures |= UPT1_F_LRO; 2400 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS); 2401 } 2402 if (adapter->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 2403 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 2404 2405 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu); 2406 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa); 2407 devRead->misc.queueDescLen = cpu_to_le32( 2408 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 2409 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc)); 2410 2411 /* tx queue settings */ 2412 devRead->misc.numTxQueues = adapter->num_tx_queues; 2413 for (i = 0; i < adapter->num_tx_queues; i++) { 2414 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i]; 2415 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL); 2416 tqc = &adapter->tqd_start[i].conf; 2417 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA); 2418 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA); 2419 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA); 2420 tqc->ddPA = cpu_to_le64(tq->buf_info_pa); 2421 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size); 2422 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size); 2423 tqc->txDataRingDescSize = cpu_to_le32(tq->txdata_desc_size); 2424 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size); 2425 tqc->ddLen = cpu_to_le32( 2426 sizeof(struct vmxnet3_tx_buf_info) * 2427 tqc->txRingSize); 2428 tqc->intrIdx = tq->comp_ring.intr_idx; 2429 } 2430 2431 /* rx queue settings */ 2432 devRead->misc.numRxQueues = adapter->num_rx_queues; 2433 for (i = 0; i < adapter->num_rx_queues; i++) { 2434 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2435 rqc = &adapter->rqd_start[i].conf; 2436 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA); 2437 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA); 2438 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA); 2439 rqc->ddPA = cpu_to_le64(rq->buf_info_pa); 2440 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size); 2441 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size); 2442 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size); 2443 rqc->ddLen = cpu_to_le32( 2444 sizeof(struct vmxnet3_rx_buf_info) * 2445 (rqc->rxRingSize[0] + 2446 rqc->rxRingSize[1])); 2447 rqc->intrIdx = rq->comp_ring.intr_idx; 2448 if (VMXNET3_VERSION_GE_3(adapter)) { 2449 rqc->rxDataRingBasePA = 2450 cpu_to_le64(rq->data_ring.basePA); 2451 rqc->rxDataRingDescSize = 2452 cpu_to_le16(rq->data_ring.desc_size); 2453 } 2454 } 2455 2456 #ifdef VMXNET3_RSS 2457 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf)); 2458 2459 if (adapter->rss) { 2460 struct UPT1_RSSConf *rssConf = adapter->rss_conf; 2461 2462 devRead->misc.uptFeatures |= UPT1_F_RSS; 2463 devRead->misc.numRxQueues = adapter->num_rx_queues; 2464 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 | 2465 UPT1_RSS_HASH_TYPE_IPV4 | 2466 UPT1_RSS_HASH_TYPE_TCP_IPV6 | 2467 UPT1_RSS_HASH_TYPE_IPV6; 2468 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ; 2469 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE; 2470 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE; 2471 netdev_rss_key_fill(rssConf->hashKey, sizeof(rssConf->hashKey)); 2472 2473 for (i = 0; i < rssConf->indTableSize; i++) 2474 rssConf->indTable[i] = ethtool_rxfh_indir_default( 2475 i, adapter->num_rx_queues); 2476 2477 devRead->rssConfDesc.confVer = 1; 2478 devRead->rssConfDesc.confLen = cpu_to_le32(sizeof(*rssConf)); 2479 devRead->rssConfDesc.confPA = 2480 cpu_to_le64(adapter->rss_conf_pa); 2481 } 2482 2483 #endif /* VMXNET3_RSS */ 2484 2485 /* intr settings */ 2486 devRead->intrConf.autoMask = adapter->intr.mask_mode == 2487 VMXNET3_IMM_AUTO; 2488 devRead->intrConf.numIntrs = adapter->intr.num_intrs; 2489 for (i = 0; i < adapter->intr.num_intrs; i++) 2490 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i]; 2491 2492 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx; 2493 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL); 2494 2495 /* rx filter settings */ 2496 devRead->rxFilterConf.rxMode = 0; 2497 vmxnet3_restore_vlan(adapter); 2498 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr); 2499 2500 /* the rest are already zeroed */ 2501 } 2502 2503 static void 2504 vmxnet3_init_coalesce(struct vmxnet3_adapter *adapter) 2505 { 2506 struct Vmxnet3_DriverShared *shared = adapter->shared; 2507 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo; 2508 unsigned long flags; 2509 2510 if (!VMXNET3_VERSION_GE_3(adapter)) 2511 return; 2512 2513 spin_lock_irqsave(&adapter->cmd_lock, flags); 2514 cmdInfo->varConf.confVer = 1; 2515 cmdInfo->varConf.confLen = 2516 cpu_to_le32(sizeof(*adapter->coal_conf)); 2517 cmdInfo->varConf.confPA = cpu_to_le64(adapter->coal_conf_pa); 2518 2519 if (adapter->default_coal_mode) { 2520 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2521 VMXNET3_CMD_GET_COALESCE); 2522 } else { 2523 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2524 VMXNET3_CMD_SET_COALESCE); 2525 } 2526 2527 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2528 } 2529 2530 int 2531 vmxnet3_activate_dev(struct vmxnet3_adapter *adapter) 2532 { 2533 int err, i; 2534 u32 ret; 2535 unsigned long flags; 2536 2537 netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d," 2538 " ring sizes %u %u %u\n", adapter->netdev->name, 2539 adapter->skb_buf_size, adapter->rx_buf_per_pkt, 2540 adapter->tx_queue[0].tx_ring.size, 2541 adapter->rx_queue[0].rx_ring[0].size, 2542 adapter->rx_queue[0].rx_ring[1].size); 2543 2544 vmxnet3_tq_init_all(adapter); 2545 err = vmxnet3_rq_init_all(adapter); 2546 if (err) { 2547 netdev_err(adapter->netdev, 2548 "Failed to init rx queue error %d\n", err); 2549 goto rq_err; 2550 } 2551 2552 err = vmxnet3_request_irqs(adapter); 2553 if (err) { 2554 netdev_err(adapter->netdev, 2555 "Failed to setup irq for error %d\n", err); 2556 goto irq_err; 2557 } 2558 2559 vmxnet3_setup_driver_shared(adapter); 2560 2561 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO( 2562 adapter->shared_pa)); 2563 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI( 2564 adapter->shared_pa)); 2565 spin_lock_irqsave(&adapter->cmd_lock, flags); 2566 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2567 VMXNET3_CMD_ACTIVATE_DEV); 2568 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 2569 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2570 2571 if (ret != 0) { 2572 netdev_err(adapter->netdev, 2573 "Failed to activate dev: error %u\n", ret); 2574 err = -EINVAL; 2575 goto activate_err; 2576 } 2577 2578 vmxnet3_init_coalesce(adapter); 2579 2580 for (i = 0; i < adapter->num_rx_queues; i++) { 2581 VMXNET3_WRITE_BAR0_REG(adapter, 2582 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN, 2583 adapter->rx_queue[i].rx_ring[0].next2fill); 2584 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 + 2585 (i * VMXNET3_REG_ALIGN)), 2586 adapter->rx_queue[i].rx_ring[1].next2fill); 2587 } 2588 2589 /* Apply the rx filter settins last. */ 2590 vmxnet3_set_mc(adapter->netdev); 2591 2592 /* 2593 * Check link state when first activating device. It will start the 2594 * tx queue if the link is up. 2595 */ 2596 vmxnet3_check_link(adapter, true); 2597 for (i = 0; i < adapter->num_rx_queues; i++) 2598 napi_enable(&adapter->rx_queue[i].napi); 2599 vmxnet3_enable_all_intrs(adapter); 2600 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 2601 return 0; 2602 2603 activate_err: 2604 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0); 2605 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0); 2606 vmxnet3_free_irqs(adapter); 2607 irq_err: 2608 rq_err: 2609 /* free up buffers we allocated */ 2610 vmxnet3_rq_cleanup_all(adapter); 2611 return err; 2612 } 2613 2614 2615 void 2616 vmxnet3_reset_dev(struct vmxnet3_adapter *adapter) 2617 { 2618 unsigned long flags; 2619 spin_lock_irqsave(&adapter->cmd_lock, flags); 2620 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 2621 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2622 } 2623 2624 2625 int 2626 vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter) 2627 { 2628 int i; 2629 unsigned long flags; 2630 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state)) 2631 return 0; 2632 2633 2634 spin_lock_irqsave(&adapter->cmd_lock, flags); 2635 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2636 VMXNET3_CMD_QUIESCE_DEV); 2637 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2638 vmxnet3_disable_all_intrs(adapter); 2639 2640 for (i = 0; i < adapter->num_rx_queues; i++) 2641 napi_disable(&adapter->rx_queue[i].napi); 2642 netif_tx_disable(adapter->netdev); 2643 adapter->link_speed = 0; 2644 netif_carrier_off(adapter->netdev); 2645 2646 vmxnet3_tq_cleanup_all(adapter); 2647 vmxnet3_rq_cleanup_all(adapter); 2648 vmxnet3_free_irqs(adapter); 2649 return 0; 2650 } 2651 2652 2653 static void 2654 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac) 2655 { 2656 u32 tmp; 2657 2658 tmp = *(u32 *)mac; 2659 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp); 2660 2661 tmp = (mac[5] << 8) | mac[4]; 2662 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp); 2663 } 2664 2665 2666 static int 2667 vmxnet3_set_mac_addr(struct net_device *netdev, void *p) 2668 { 2669 struct sockaddr *addr = p; 2670 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2671 2672 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 2673 vmxnet3_write_mac_addr(adapter, addr->sa_data); 2674 2675 return 0; 2676 } 2677 2678 2679 /* ==================== initialization and cleanup routines ============ */ 2680 2681 static int 2682 vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64) 2683 { 2684 int err; 2685 unsigned long mmio_start, mmio_len; 2686 struct pci_dev *pdev = adapter->pdev; 2687 2688 err = pci_enable_device(pdev); 2689 if (err) { 2690 dev_err(&pdev->dev, "Failed to enable adapter: error %d\n", err); 2691 return err; 2692 } 2693 2694 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) { 2695 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) { 2696 dev_err(&pdev->dev, 2697 "pci_set_consistent_dma_mask failed\n"); 2698 err = -EIO; 2699 goto err_set_mask; 2700 } 2701 *dma64 = true; 2702 } else { 2703 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) { 2704 dev_err(&pdev->dev, 2705 "pci_set_dma_mask failed\n"); 2706 err = -EIO; 2707 goto err_set_mask; 2708 } 2709 *dma64 = false; 2710 } 2711 2712 err = pci_request_selected_regions(pdev, (1 << 2) - 1, 2713 vmxnet3_driver_name); 2714 if (err) { 2715 dev_err(&pdev->dev, 2716 "Failed to request region for adapter: error %d\n", err); 2717 goto err_set_mask; 2718 } 2719 2720 pci_set_master(pdev); 2721 2722 mmio_start = pci_resource_start(pdev, 0); 2723 mmio_len = pci_resource_len(pdev, 0); 2724 adapter->hw_addr0 = ioremap(mmio_start, mmio_len); 2725 if (!adapter->hw_addr0) { 2726 dev_err(&pdev->dev, "Failed to map bar0\n"); 2727 err = -EIO; 2728 goto err_ioremap; 2729 } 2730 2731 mmio_start = pci_resource_start(pdev, 1); 2732 mmio_len = pci_resource_len(pdev, 1); 2733 adapter->hw_addr1 = ioremap(mmio_start, mmio_len); 2734 if (!adapter->hw_addr1) { 2735 dev_err(&pdev->dev, "Failed to map bar1\n"); 2736 err = -EIO; 2737 goto err_bar1; 2738 } 2739 return 0; 2740 2741 err_bar1: 2742 iounmap(adapter->hw_addr0); 2743 err_ioremap: 2744 pci_release_selected_regions(pdev, (1 << 2) - 1); 2745 err_set_mask: 2746 pci_disable_device(pdev); 2747 return err; 2748 } 2749 2750 2751 static void 2752 vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter) 2753 { 2754 BUG_ON(!adapter->pdev); 2755 2756 iounmap(adapter->hw_addr0); 2757 iounmap(adapter->hw_addr1); 2758 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1); 2759 pci_disable_device(adapter->pdev); 2760 } 2761 2762 2763 static void 2764 vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter) 2765 { 2766 size_t sz, i, ring0_size, ring1_size, comp_size; 2767 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE - 2768 VMXNET3_MAX_ETH_HDR_SIZE) { 2769 adapter->skb_buf_size = adapter->netdev->mtu + 2770 VMXNET3_MAX_ETH_HDR_SIZE; 2771 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE) 2772 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE; 2773 2774 adapter->rx_buf_per_pkt = 1; 2775 } else { 2776 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE; 2777 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE + 2778 VMXNET3_MAX_ETH_HDR_SIZE; 2779 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE; 2780 } 2781 2782 /* 2783 * for simplicity, force the ring0 size to be a multiple of 2784 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN 2785 */ 2786 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN; 2787 ring0_size = adapter->rx_queue[0].rx_ring[0].size; 2788 ring0_size = (ring0_size + sz - 1) / sz * sz; 2789 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE / 2790 sz * sz); 2791 ring1_size = adapter->rx_queue[0].rx_ring[1].size; 2792 ring1_size = (ring1_size + sz - 1) / sz * sz; 2793 ring1_size = min_t(u32, ring1_size, VMXNET3_RX_RING2_MAX_SIZE / 2794 sz * sz); 2795 comp_size = ring0_size + ring1_size; 2796 2797 for (i = 0; i < adapter->num_rx_queues; i++) { 2798 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2799 2800 rq->rx_ring[0].size = ring0_size; 2801 rq->rx_ring[1].size = ring1_size; 2802 rq->comp_ring.size = comp_size; 2803 } 2804 } 2805 2806 2807 int 2808 vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size, 2809 u32 rx_ring_size, u32 rx_ring2_size, 2810 u16 txdata_desc_size, u16 rxdata_desc_size) 2811 { 2812 int err = 0, i; 2813 2814 for (i = 0; i < adapter->num_tx_queues; i++) { 2815 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i]; 2816 tq->tx_ring.size = tx_ring_size; 2817 tq->data_ring.size = tx_ring_size; 2818 tq->comp_ring.size = tx_ring_size; 2819 tq->txdata_desc_size = txdata_desc_size; 2820 tq->shared = &adapter->tqd_start[i].ctrl; 2821 tq->stopped = true; 2822 tq->adapter = adapter; 2823 tq->qid = i; 2824 err = vmxnet3_tq_create(tq, adapter); 2825 /* 2826 * Too late to change num_tx_queues. We cannot do away with 2827 * lesser number of queues than what we asked for 2828 */ 2829 if (err) 2830 goto queue_err; 2831 } 2832 2833 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size; 2834 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size; 2835 vmxnet3_adjust_rx_ring_size(adapter); 2836 2837 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter); 2838 for (i = 0; i < adapter->num_rx_queues; i++) { 2839 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2840 /* qid and qid2 for rx queues will be assigned later when num 2841 * of rx queues is finalized after allocating intrs */ 2842 rq->shared = &adapter->rqd_start[i].ctrl; 2843 rq->adapter = adapter; 2844 rq->data_ring.desc_size = rxdata_desc_size; 2845 err = vmxnet3_rq_create(rq, adapter); 2846 if (err) { 2847 if (i == 0) { 2848 netdev_err(adapter->netdev, 2849 "Could not allocate any rx queues. " 2850 "Aborting.\n"); 2851 goto queue_err; 2852 } else { 2853 netdev_info(adapter->netdev, 2854 "Number of rx queues changed " 2855 "to : %d.\n", i); 2856 adapter->num_rx_queues = i; 2857 err = 0; 2858 break; 2859 } 2860 } 2861 } 2862 2863 if (!adapter->rxdataring_enabled) 2864 vmxnet3_rq_destroy_all_rxdataring(adapter); 2865 2866 return err; 2867 queue_err: 2868 vmxnet3_tq_destroy_all(adapter); 2869 return err; 2870 } 2871 2872 static int 2873 vmxnet3_open(struct net_device *netdev) 2874 { 2875 struct vmxnet3_adapter *adapter; 2876 int err, i; 2877 2878 adapter = netdev_priv(netdev); 2879 2880 for (i = 0; i < adapter->num_tx_queues; i++) 2881 spin_lock_init(&adapter->tx_queue[i].tx_lock); 2882 2883 if (VMXNET3_VERSION_GE_3(adapter)) { 2884 unsigned long flags; 2885 u16 txdata_desc_size; 2886 2887 spin_lock_irqsave(&adapter->cmd_lock, flags); 2888 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2889 VMXNET3_CMD_GET_TXDATA_DESC_SIZE); 2890 txdata_desc_size = VMXNET3_READ_BAR1_REG(adapter, 2891 VMXNET3_REG_CMD); 2892 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2893 2894 if ((txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE) || 2895 (txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE) || 2896 (txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK)) { 2897 adapter->txdata_desc_size = 2898 sizeof(struct Vmxnet3_TxDataDesc); 2899 } else { 2900 adapter->txdata_desc_size = txdata_desc_size; 2901 } 2902 } else { 2903 adapter->txdata_desc_size = sizeof(struct Vmxnet3_TxDataDesc); 2904 } 2905 2906 err = vmxnet3_create_queues(adapter, 2907 adapter->tx_ring_size, 2908 adapter->rx_ring_size, 2909 adapter->rx_ring2_size, 2910 adapter->txdata_desc_size, 2911 adapter->rxdata_desc_size); 2912 if (err) 2913 goto queue_err; 2914 2915 err = vmxnet3_activate_dev(adapter); 2916 if (err) 2917 goto activate_err; 2918 2919 return 0; 2920 2921 activate_err: 2922 vmxnet3_rq_destroy_all(adapter); 2923 vmxnet3_tq_destroy_all(adapter); 2924 queue_err: 2925 return err; 2926 } 2927 2928 2929 static int 2930 vmxnet3_close(struct net_device *netdev) 2931 { 2932 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2933 2934 /* 2935 * Reset_work may be in the middle of resetting the device, wait for its 2936 * completion. 2937 */ 2938 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 2939 msleep(1); 2940 2941 vmxnet3_quiesce_dev(adapter); 2942 2943 vmxnet3_rq_destroy_all(adapter); 2944 vmxnet3_tq_destroy_all(adapter); 2945 2946 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 2947 2948 2949 return 0; 2950 } 2951 2952 2953 void 2954 vmxnet3_force_close(struct vmxnet3_adapter *adapter) 2955 { 2956 int i; 2957 2958 /* 2959 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise 2960 * vmxnet3_close() will deadlock. 2961 */ 2962 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)); 2963 2964 /* we need to enable NAPI, otherwise dev_close will deadlock */ 2965 for (i = 0; i < adapter->num_rx_queues; i++) 2966 napi_enable(&adapter->rx_queue[i].napi); 2967 /* 2968 * Need to clear the quiesce bit to ensure that vmxnet3_close 2969 * can quiesce the device properly 2970 */ 2971 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 2972 dev_close(adapter->netdev); 2973 } 2974 2975 2976 static int 2977 vmxnet3_change_mtu(struct net_device *netdev, int new_mtu) 2978 { 2979 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2980 int err = 0; 2981 2982 netdev->mtu = new_mtu; 2983 2984 /* 2985 * Reset_work may be in the middle of resetting the device, wait for its 2986 * completion. 2987 */ 2988 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 2989 msleep(1); 2990 2991 if (netif_running(netdev)) { 2992 vmxnet3_quiesce_dev(adapter); 2993 vmxnet3_reset_dev(adapter); 2994 2995 /* we need to re-create the rx queue based on the new mtu */ 2996 vmxnet3_rq_destroy_all(adapter); 2997 vmxnet3_adjust_rx_ring_size(adapter); 2998 err = vmxnet3_rq_create_all(adapter); 2999 if (err) { 3000 netdev_err(netdev, 3001 "failed to re-create rx queues, " 3002 " error %d. Closing it.\n", err); 3003 goto out; 3004 } 3005 3006 err = vmxnet3_activate_dev(adapter); 3007 if (err) { 3008 netdev_err(netdev, 3009 "failed to re-activate, error %d. " 3010 "Closing it\n", err); 3011 goto out; 3012 } 3013 } 3014 3015 out: 3016 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3017 if (err) 3018 vmxnet3_force_close(adapter); 3019 3020 return err; 3021 } 3022 3023 3024 static void 3025 vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64) 3026 { 3027 struct net_device *netdev = adapter->netdev; 3028 3029 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM | 3030 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX | 3031 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 | 3032 NETIF_F_LRO; 3033 if (dma64) 3034 netdev->hw_features |= NETIF_F_HIGHDMA; 3035 netdev->vlan_features = netdev->hw_features & 3036 ~(NETIF_F_HW_VLAN_CTAG_TX | 3037 NETIF_F_HW_VLAN_CTAG_RX); 3038 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER; 3039 } 3040 3041 3042 static void 3043 vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac) 3044 { 3045 u32 tmp; 3046 3047 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL); 3048 *(u32 *)mac = tmp; 3049 3050 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH); 3051 mac[4] = tmp & 0xff; 3052 mac[5] = (tmp >> 8) & 0xff; 3053 } 3054 3055 #ifdef CONFIG_PCI_MSI 3056 3057 /* 3058 * Enable MSIx vectors. 3059 * Returns : 3060 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required 3061 * were enabled. 3062 * number of vectors which were enabled otherwise (this number is greater 3063 * than VMXNET3_LINUX_MIN_MSIX_VECT) 3064 */ 3065 3066 static int 3067 vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, int nvec) 3068 { 3069 int ret = pci_enable_msix_range(adapter->pdev, 3070 adapter->intr.msix_entries, nvec, nvec); 3071 3072 if (ret == -ENOSPC && nvec > VMXNET3_LINUX_MIN_MSIX_VECT) { 3073 dev_err(&adapter->netdev->dev, 3074 "Failed to enable %d MSI-X, trying %d\n", 3075 nvec, VMXNET3_LINUX_MIN_MSIX_VECT); 3076 3077 ret = pci_enable_msix_range(adapter->pdev, 3078 adapter->intr.msix_entries, 3079 VMXNET3_LINUX_MIN_MSIX_VECT, 3080 VMXNET3_LINUX_MIN_MSIX_VECT); 3081 } 3082 3083 if (ret < 0) { 3084 dev_err(&adapter->netdev->dev, 3085 "Failed to enable MSI-X, error: %d\n", ret); 3086 } 3087 3088 return ret; 3089 } 3090 3091 3092 #endif /* CONFIG_PCI_MSI */ 3093 3094 static void 3095 vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter) 3096 { 3097 u32 cfg; 3098 unsigned long flags; 3099 3100 /* intr settings */ 3101 spin_lock_irqsave(&adapter->cmd_lock, flags); 3102 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3103 VMXNET3_CMD_GET_CONF_INTR); 3104 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 3105 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3106 adapter->intr.type = cfg & 0x3; 3107 adapter->intr.mask_mode = (cfg >> 2) & 0x3; 3108 3109 if (adapter->intr.type == VMXNET3_IT_AUTO) { 3110 adapter->intr.type = VMXNET3_IT_MSIX; 3111 } 3112 3113 #ifdef CONFIG_PCI_MSI 3114 if (adapter->intr.type == VMXNET3_IT_MSIX) { 3115 int i, nvec; 3116 3117 nvec = adapter->share_intr == VMXNET3_INTR_TXSHARE ? 3118 1 : adapter->num_tx_queues; 3119 nvec += adapter->share_intr == VMXNET3_INTR_BUDDYSHARE ? 3120 0 : adapter->num_rx_queues; 3121 nvec += 1; /* for link event */ 3122 nvec = nvec > VMXNET3_LINUX_MIN_MSIX_VECT ? 3123 nvec : VMXNET3_LINUX_MIN_MSIX_VECT; 3124 3125 for (i = 0; i < nvec; i++) 3126 adapter->intr.msix_entries[i].entry = i; 3127 3128 nvec = vmxnet3_acquire_msix_vectors(adapter, nvec); 3129 if (nvec < 0) 3130 goto msix_err; 3131 3132 /* If we cannot allocate one MSIx vector per queue 3133 * then limit the number of rx queues to 1 3134 */ 3135 if (nvec == VMXNET3_LINUX_MIN_MSIX_VECT) { 3136 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE 3137 || adapter->num_rx_queues != 1) { 3138 adapter->share_intr = VMXNET3_INTR_TXSHARE; 3139 netdev_err(adapter->netdev, 3140 "Number of rx queues : 1\n"); 3141 adapter->num_rx_queues = 1; 3142 } 3143 } 3144 3145 adapter->intr.num_intrs = nvec; 3146 return; 3147 3148 msix_err: 3149 /* If we cannot allocate MSIx vectors use only one rx queue */ 3150 dev_info(&adapter->pdev->dev, 3151 "Failed to enable MSI-X, error %d. " 3152 "Limiting #rx queues to 1, try MSI.\n", nvec); 3153 3154 adapter->intr.type = VMXNET3_IT_MSI; 3155 } 3156 3157 if (adapter->intr.type == VMXNET3_IT_MSI) { 3158 if (!pci_enable_msi(adapter->pdev)) { 3159 adapter->num_rx_queues = 1; 3160 adapter->intr.num_intrs = 1; 3161 return; 3162 } 3163 } 3164 #endif /* CONFIG_PCI_MSI */ 3165 3166 adapter->num_rx_queues = 1; 3167 dev_info(&adapter->netdev->dev, 3168 "Using INTx interrupt, #Rx queues: 1.\n"); 3169 adapter->intr.type = VMXNET3_IT_INTX; 3170 3171 /* INT-X related setting */ 3172 adapter->intr.num_intrs = 1; 3173 } 3174 3175 3176 static void 3177 vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter) 3178 { 3179 if (adapter->intr.type == VMXNET3_IT_MSIX) 3180 pci_disable_msix(adapter->pdev); 3181 else if (adapter->intr.type == VMXNET3_IT_MSI) 3182 pci_disable_msi(adapter->pdev); 3183 else 3184 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX); 3185 } 3186 3187 3188 static void 3189 vmxnet3_tx_timeout(struct net_device *netdev) 3190 { 3191 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3192 adapter->tx_timeout_count++; 3193 3194 netdev_err(adapter->netdev, "tx hang\n"); 3195 schedule_work(&adapter->work); 3196 } 3197 3198 3199 static void 3200 vmxnet3_reset_work(struct work_struct *data) 3201 { 3202 struct vmxnet3_adapter *adapter; 3203 3204 adapter = container_of(data, struct vmxnet3_adapter, work); 3205 3206 /* if another thread is resetting the device, no need to proceed */ 3207 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 3208 return; 3209 3210 /* if the device is closed, we must leave it alone */ 3211 rtnl_lock(); 3212 if (netif_running(adapter->netdev)) { 3213 netdev_notice(adapter->netdev, "resetting\n"); 3214 vmxnet3_quiesce_dev(adapter); 3215 vmxnet3_reset_dev(adapter); 3216 vmxnet3_activate_dev(adapter); 3217 } else { 3218 netdev_info(adapter->netdev, "already closed\n"); 3219 } 3220 rtnl_unlock(); 3221 3222 netif_wake_queue(adapter->netdev); 3223 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3224 } 3225 3226 3227 static int 3228 vmxnet3_probe_device(struct pci_dev *pdev, 3229 const struct pci_device_id *id) 3230 { 3231 static const struct net_device_ops vmxnet3_netdev_ops = { 3232 .ndo_open = vmxnet3_open, 3233 .ndo_stop = vmxnet3_close, 3234 .ndo_start_xmit = vmxnet3_xmit_frame, 3235 .ndo_set_mac_address = vmxnet3_set_mac_addr, 3236 .ndo_change_mtu = vmxnet3_change_mtu, 3237 .ndo_set_features = vmxnet3_set_features, 3238 .ndo_get_stats64 = vmxnet3_get_stats64, 3239 .ndo_tx_timeout = vmxnet3_tx_timeout, 3240 .ndo_set_rx_mode = vmxnet3_set_mc, 3241 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid, 3242 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid, 3243 #ifdef CONFIG_NET_POLL_CONTROLLER 3244 .ndo_poll_controller = vmxnet3_netpoll, 3245 #endif 3246 }; 3247 int err; 3248 bool dma64 = false; /* stupid gcc */ 3249 u32 ver; 3250 struct net_device *netdev; 3251 struct vmxnet3_adapter *adapter; 3252 u8 mac[ETH_ALEN]; 3253 int size; 3254 int num_tx_queues; 3255 int num_rx_queues; 3256 3257 if (!pci_msi_enabled()) 3258 enable_mq = 0; 3259 3260 #ifdef VMXNET3_RSS 3261 if (enable_mq) 3262 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES, 3263 (int)num_online_cpus()); 3264 else 3265 #endif 3266 num_rx_queues = 1; 3267 num_rx_queues = rounddown_pow_of_two(num_rx_queues); 3268 3269 if (enable_mq) 3270 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES, 3271 (int)num_online_cpus()); 3272 else 3273 num_tx_queues = 1; 3274 3275 num_tx_queues = rounddown_pow_of_two(num_tx_queues); 3276 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter), 3277 max(num_tx_queues, num_rx_queues)); 3278 dev_info(&pdev->dev, 3279 "# of Tx queues : %d, # of Rx queues : %d\n", 3280 num_tx_queues, num_rx_queues); 3281 3282 if (!netdev) 3283 return -ENOMEM; 3284 3285 pci_set_drvdata(pdev, netdev); 3286 adapter = netdev_priv(netdev); 3287 adapter->netdev = netdev; 3288 adapter->pdev = pdev; 3289 3290 adapter->tx_ring_size = VMXNET3_DEF_TX_RING_SIZE; 3291 adapter->rx_ring_size = VMXNET3_DEF_RX_RING_SIZE; 3292 adapter->rx_ring2_size = VMXNET3_DEF_RX_RING2_SIZE; 3293 3294 spin_lock_init(&adapter->cmd_lock); 3295 adapter->adapter_pa = dma_map_single(&adapter->pdev->dev, adapter, 3296 sizeof(struct vmxnet3_adapter), 3297 PCI_DMA_TODEVICE); 3298 if (dma_mapping_error(&adapter->pdev->dev, adapter->adapter_pa)) { 3299 dev_err(&pdev->dev, "Failed to map dma\n"); 3300 err = -EFAULT; 3301 goto err_dma_map; 3302 } 3303 adapter->shared = dma_alloc_coherent( 3304 &adapter->pdev->dev, 3305 sizeof(struct Vmxnet3_DriverShared), 3306 &adapter->shared_pa, GFP_KERNEL); 3307 if (!adapter->shared) { 3308 dev_err(&pdev->dev, "Failed to allocate memory\n"); 3309 err = -ENOMEM; 3310 goto err_alloc_shared; 3311 } 3312 3313 adapter->num_rx_queues = num_rx_queues; 3314 adapter->num_tx_queues = num_tx_queues; 3315 adapter->rx_buf_per_pkt = 1; 3316 3317 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues; 3318 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues; 3319 adapter->tqd_start = dma_alloc_coherent(&adapter->pdev->dev, size, 3320 &adapter->queue_desc_pa, 3321 GFP_KERNEL); 3322 3323 if (!adapter->tqd_start) { 3324 dev_err(&pdev->dev, "Failed to allocate memory\n"); 3325 err = -ENOMEM; 3326 goto err_alloc_queue_desc; 3327 } 3328 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start + 3329 adapter->num_tx_queues); 3330 3331 adapter->pm_conf = dma_alloc_coherent(&adapter->pdev->dev, 3332 sizeof(struct Vmxnet3_PMConf), 3333 &adapter->pm_conf_pa, 3334 GFP_KERNEL); 3335 if (adapter->pm_conf == NULL) { 3336 err = -ENOMEM; 3337 goto err_alloc_pm; 3338 } 3339 3340 #ifdef VMXNET3_RSS 3341 3342 adapter->rss_conf = dma_alloc_coherent(&adapter->pdev->dev, 3343 sizeof(struct UPT1_RSSConf), 3344 &adapter->rss_conf_pa, 3345 GFP_KERNEL); 3346 if (adapter->rss_conf == NULL) { 3347 err = -ENOMEM; 3348 goto err_alloc_rss; 3349 } 3350 #endif /* VMXNET3_RSS */ 3351 3352 err = vmxnet3_alloc_pci_resources(adapter, &dma64); 3353 if (err < 0) 3354 goto err_alloc_pci; 3355 3356 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS); 3357 if (ver & (1 << VMXNET3_REV_3)) { 3358 VMXNET3_WRITE_BAR1_REG(adapter, 3359 VMXNET3_REG_VRRS, 3360 1 << VMXNET3_REV_3); 3361 adapter->version = VMXNET3_REV_3 + 1; 3362 } else if (ver & (1 << VMXNET3_REV_2)) { 3363 VMXNET3_WRITE_BAR1_REG(adapter, 3364 VMXNET3_REG_VRRS, 3365 1 << VMXNET3_REV_2); 3366 adapter->version = VMXNET3_REV_2 + 1; 3367 } else if (ver & (1 << VMXNET3_REV_1)) { 3368 VMXNET3_WRITE_BAR1_REG(adapter, 3369 VMXNET3_REG_VRRS, 3370 1 << VMXNET3_REV_1); 3371 adapter->version = VMXNET3_REV_1 + 1; 3372 } else { 3373 dev_err(&pdev->dev, 3374 "Incompatible h/w version (0x%x) for adapter\n", ver); 3375 err = -EBUSY; 3376 goto err_ver; 3377 } 3378 dev_dbg(&pdev->dev, "Using device version %d\n", adapter->version); 3379 3380 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS); 3381 if (ver & 1) { 3382 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1); 3383 } else { 3384 dev_err(&pdev->dev, 3385 "Incompatible upt version (0x%x) for adapter\n", ver); 3386 err = -EBUSY; 3387 goto err_ver; 3388 } 3389 3390 if (VMXNET3_VERSION_GE_3(adapter)) { 3391 adapter->coal_conf = 3392 dma_alloc_coherent(&adapter->pdev->dev, 3393 sizeof(struct Vmxnet3_CoalesceScheme) 3394 , 3395 &adapter->coal_conf_pa, 3396 GFP_KERNEL); 3397 if (!adapter->coal_conf) { 3398 err = -ENOMEM; 3399 goto err_ver; 3400 } 3401 memset(adapter->coal_conf, 0, sizeof(*adapter->coal_conf)); 3402 adapter->coal_conf->coalMode = VMXNET3_COALESCE_DISABLED; 3403 adapter->default_coal_mode = true; 3404 } 3405 3406 SET_NETDEV_DEV(netdev, &pdev->dev); 3407 vmxnet3_declare_features(adapter, dma64); 3408 3409 adapter->rxdata_desc_size = VMXNET3_VERSION_GE_3(adapter) ? 3410 VMXNET3_DEF_RXDATA_DESC_SIZE : 0; 3411 3412 if (adapter->num_tx_queues == adapter->num_rx_queues) 3413 adapter->share_intr = VMXNET3_INTR_BUDDYSHARE; 3414 else 3415 adapter->share_intr = VMXNET3_INTR_DONTSHARE; 3416 3417 vmxnet3_alloc_intr_resources(adapter); 3418 3419 #ifdef VMXNET3_RSS 3420 if (adapter->num_rx_queues > 1 && 3421 adapter->intr.type == VMXNET3_IT_MSIX) { 3422 adapter->rss = true; 3423 netdev->hw_features |= NETIF_F_RXHASH; 3424 netdev->features |= NETIF_F_RXHASH; 3425 dev_dbg(&pdev->dev, "RSS is enabled.\n"); 3426 } else { 3427 adapter->rss = false; 3428 } 3429 #endif 3430 3431 vmxnet3_read_mac_addr(adapter, mac); 3432 memcpy(netdev->dev_addr, mac, netdev->addr_len); 3433 3434 netdev->netdev_ops = &vmxnet3_netdev_ops; 3435 vmxnet3_set_ethtool_ops(netdev); 3436 netdev->watchdog_timeo = 5 * HZ; 3437 3438 /* MTU range: 60 - 9000 */ 3439 netdev->min_mtu = VMXNET3_MIN_MTU; 3440 netdev->max_mtu = VMXNET3_MAX_MTU; 3441 3442 INIT_WORK(&adapter->work, vmxnet3_reset_work); 3443 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 3444 3445 if (adapter->intr.type == VMXNET3_IT_MSIX) { 3446 int i; 3447 for (i = 0; i < adapter->num_rx_queues; i++) { 3448 netif_napi_add(adapter->netdev, 3449 &adapter->rx_queue[i].napi, 3450 vmxnet3_poll_rx_only, 64); 3451 } 3452 } else { 3453 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi, 3454 vmxnet3_poll, 64); 3455 } 3456 3457 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); 3458 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues); 3459 3460 netif_carrier_off(netdev); 3461 err = register_netdev(netdev); 3462 3463 if (err) { 3464 dev_err(&pdev->dev, "Failed to register adapter\n"); 3465 goto err_register; 3466 } 3467 3468 vmxnet3_check_link(adapter, false); 3469 return 0; 3470 3471 err_register: 3472 if (VMXNET3_VERSION_GE_3(adapter)) { 3473 dma_free_coherent(&adapter->pdev->dev, 3474 sizeof(struct Vmxnet3_CoalesceScheme), 3475 adapter->coal_conf, adapter->coal_conf_pa); 3476 } 3477 vmxnet3_free_intr_resources(adapter); 3478 err_ver: 3479 vmxnet3_free_pci_resources(adapter); 3480 err_alloc_pci: 3481 #ifdef VMXNET3_RSS 3482 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf), 3483 adapter->rss_conf, adapter->rss_conf_pa); 3484 err_alloc_rss: 3485 #endif 3486 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf), 3487 adapter->pm_conf, adapter->pm_conf_pa); 3488 err_alloc_pm: 3489 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start, 3490 adapter->queue_desc_pa); 3491 err_alloc_queue_desc: 3492 dma_free_coherent(&adapter->pdev->dev, 3493 sizeof(struct Vmxnet3_DriverShared), 3494 adapter->shared, adapter->shared_pa); 3495 err_alloc_shared: 3496 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa, 3497 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE); 3498 err_dma_map: 3499 free_netdev(netdev); 3500 return err; 3501 } 3502 3503 3504 static void 3505 vmxnet3_remove_device(struct pci_dev *pdev) 3506 { 3507 struct net_device *netdev = pci_get_drvdata(pdev); 3508 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3509 int size = 0; 3510 int num_rx_queues; 3511 3512 #ifdef VMXNET3_RSS 3513 if (enable_mq) 3514 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES, 3515 (int)num_online_cpus()); 3516 else 3517 #endif 3518 num_rx_queues = 1; 3519 num_rx_queues = rounddown_pow_of_two(num_rx_queues); 3520 3521 cancel_work_sync(&adapter->work); 3522 3523 unregister_netdev(netdev); 3524 3525 vmxnet3_free_intr_resources(adapter); 3526 vmxnet3_free_pci_resources(adapter); 3527 if (VMXNET3_VERSION_GE_3(adapter)) { 3528 dma_free_coherent(&adapter->pdev->dev, 3529 sizeof(struct Vmxnet3_CoalesceScheme), 3530 adapter->coal_conf, adapter->coal_conf_pa); 3531 } 3532 #ifdef VMXNET3_RSS 3533 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf), 3534 adapter->rss_conf, adapter->rss_conf_pa); 3535 #endif 3536 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf), 3537 adapter->pm_conf, adapter->pm_conf_pa); 3538 3539 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues; 3540 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues; 3541 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start, 3542 adapter->queue_desc_pa); 3543 dma_free_coherent(&adapter->pdev->dev, 3544 sizeof(struct Vmxnet3_DriverShared), 3545 adapter->shared, adapter->shared_pa); 3546 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa, 3547 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE); 3548 free_netdev(netdev); 3549 } 3550 3551 static void vmxnet3_shutdown_device(struct pci_dev *pdev) 3552 { 3553 struct net_device *netdev = pci_get_drvdata(pdev); 3554 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3555 unsigned long flags; 3556 3557 /* Reset_work may be in the middle of resetting the device, wait for its 3558 * completion. 3559 */ 3560 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 3561 msleep(1); 3562 3563 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, 3564 &adapter->state)) { 3565 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3566 return; 3567 } 3568 spin_lock_irqsave(&adapter->cmd_lock, flags); 3569 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3570 VMXNET3_CMD_QUIESCE_DEV); 3571 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3572 vmxnet3_disable_all_intrs(adapter); 3573 3574 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3575 } 3576 3577 3578 #ifdef CONFIG_PM 3579 3580 static int 3581 vmxnet3_suspend(struct device *device) 3582 { 3583 struct pci_dev *pdev = to_pci_dev(device); 3584 struct net_device *netdev = pci_get_drvdata(pdev); 3585 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3586 struct Vmxnet3_PMConf *pmConf; 3587 struct ethhdr *ehdr; 3588 struct arphdr *ahdr; 3589 u8 *arpreq; 3590 struct in_device *in_dev; 3591 struct in_ifaddr *ifa; 3592 unsigned long flags; 3593 int i = 0; 3594 3595 if (!netif_running(netdev)) 3596 return 0; 3597 3598 for (i = 0; i < adapter->num_rx_queues; i++) 3599 napi_disable(&adapter->rx_queue[i].napi); 3600 3601 vmxnet3_disable_all_intrs(adapter); 3602 vmxnet3_free_irqs(adapter); 3603 vmxnet3_free_intr_resources(adapter); 3604 3605 netif_device_detach(netdev); 3606 netif_tx_stop_all_queues(netdev); 3607 3608 /* Create wake-up filters. */ 3609 pmConf = adapter->pm_conf; 3610 memset(pmConf, 0, sizeof(*pmConf)); 3611 3612 if (adapter->wol & WAKE_UCAST) { 3613 pmConf->filters[i].patternSize = ETH_ALEN; 3614 pmConf->filters[i].maskSize = 1; 3615 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN); 3616 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */ 3617 3618 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER; 3619 i++; 3620 } 3621 3622 if (adapter->wol & WAKE_ARP) { 3623 in_dev = in_dev_get(netdev); 3624 if (!in_dev) 3625 goto skip_arp; 3626 3627 ifa = (struct in_ifaddr *)in_dev->ifa_list; 3628 if (!ifa) 3629 goto skip_arp; 3630 3631 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/ 3632 sizeof(struct arphdr) + /* ARP header */ 3633 2 * ETH_ALEN + /* 2 Ethernet addresses*/ 3634 2 * sizeof(u32); /*2 IPv4 addresses */ 3635 pmConf->filters[i].maskSize = 3636 (pmConf->filters[i].patternSize - 1) / 8 + 1; 3637 3638 /* ETH_P_ARP in Ethernet header. */ 3639 ehdr = (struct ethhdr *)pmConf->filters[i].pattern; 3640 ehdr->h_proto = htons(ETH_P_ARP); 3641 3642 /* ARPOP_REQUEST in ARP header. */ 3643 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN]; 3644 ahdr->ar_op = htons(ARPOP_REQUEST); 3645 arpreq = (u8 *)(ahdr + 1); 3646 3647 /* The Unicast IPv4 address in 'tip' field. */ 3648 arpreq += 2 * ETH_ALEN + sizeof(u32); 3649 *(u32 *)arpreq = ifa->ifa_address; 3650 3651 /* The mask for the relevant bits. */ 3652 pmConf->filters[i].mask[0] = 0x00; 3653 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */ 3654 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */ 3655 pmConf->filters[i].mask[3] = 0x00; 3656 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */ 3657 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */ 3658 in_dev_put(in_dev); 3659 3660 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER; 3661 i++; 3662 } 3663 3664 skip_arp: 3665 if (adapter->wol & WAKE_MAGIC) 3666 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC; 3667 3668 pmConf->numFilters = i; 3669 3670 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1); 3671 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof( 3672 *pmConf)); 3673 adapter->shared->devRead.pmConfDesc.confPA = 3674 cpu_to_le64(adapter->pm_conf_pa); 3675 3676 spin_lock_irqsave(&adapter->cmd_lock, flags); 3677 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3678 VMXNET3_CMD_UPDATE_PMCFG); 3679 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3680 3681 pci_save_state(pdev); 3682 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND), 3683 adapter->wol); 3684 pci_disable_device(pdev); 3685 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND)); 3686 3687 return 0; 3688 } 3689 3690 3691 static int 3692 vmxnet3_resume(struct device *device) 3693 { 3694 int err; 3695 unsigned long flags; 3696 struct pci_dev *pdev = to_pci_dev(device); 3697 struct net_device *netdev = pci_get_drvdata(pdev); 3698 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3699 3700 if (!netif_running(netdev)) 3701 return 0; 3702 3703 pci_set_power_state(pdev, PCI_D0); 3704 pci_restore_state(pdev); 3705 err = pci_enable_device_mem(pdev); 3706 if (err != 0) 3707 return err; 3708 3709 pci_enable_wake(pdev, PCI_D0, 0); 3710 3711 vmxnet3_alloc_intr_resources(adapter); 3712 3713 /* During hibernate and suspend, device has to be reinitialized as the 3714 * device state need not be preserved. 3715 */ 3716 3717 /* Need not check adapter state as other reset tasks cannot run during 3718 * device resume. 3719 */ 3720 spin_lock_irqsave(&adapter->cmd_lock, flags); 3721 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3722 VMXNET3_CMD_QUIESCE_DEV); 3723 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3724 vmxnet3_tq_cleanup_all(adapter); 3725 vmxnet3_rq_cleanup_all(adapter); 3726 3727 vmxnet3_reset_dev(adapter); 3728 err = vmxnet3_activate_dev(adapter); 3729 if (err != 0) { 3730 netdev_err(netdev, 3731 "failed to re-activate on resume, error: %d", err); 3732 vmxnet3_force_close(adapter); 3733 return err; 3734 } 3735 netif_device_attach(netdev); 3736 3737 return 0; 3738 } 3739 3740 static const struct dev_pm_ops vmxnet3_pm_ops = { 3741 .suspend = vmxnet3_suspend, 3742 .resume = vmxnet3_resume, 3743 .freeze = vmxnet3_suspend, 3744 .restore = vmxnet3_resume, 3745 }; 3746 #endif 3747 3748 static struct pci_driver vmxnet3_driver = { 3749 .name = vmxnet3_driver_name, 3750 .id_table = vmxnet3_pciid_table, 3751 .probe = vmxnet3_probe_device, 3752 .remove = vmxnet3_remove_device, 3753 .shutdown = vmxnet3_shutdown_device, 3754 #ifdef CONFIG_PM 3755 .driver.pm = &vmxnet3_pm_ops, 3756 #endif 3757 }; 3758 3759 3760 static int __init 3761 vmxnet3_init_module(void) 3762 { 3763 pr_info("%s - version %s\n", VMXNET3_DRIVER_DESC, 3764 VMXNET3_DRIVER_VERSION_REPORT); 3765 return pci_register_driver(&vmxnet3_driver); 3766 } 3767 3768 module_init(vmxnet3_init_module); 3769 3770 3771 static void 3772 vmxnet3_exit_module(void) 3773 { 3774 pci_unregister_driver(&vmxnet3_driver); 3775 } 3776 3777 module_exit(vmxnet3_exit_module); 3778 3779 MODULE_AUTHOR("VMware, Inc."); 3780 MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC); 3781 MODULE_LICENSE("GPL v2"); 3782 MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING); 3783