1 /* 2 * Linux driver for VMware's vmxnet3 ethernet NIC. 3 * 4 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; version 2 of the License and no later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 13 * NON INFRINGEMENT. See the GNU General Public License for more 14 * details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * The full GNU General Public License is included in this distribution in 21 * the file called "COPYING". 22 * 23 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com> 24 * 25 */ 26 27 #include <net/ip6_checksum.h> 28 29 #include "vmxnet3_int.h" 30 31 char vmxnet3_driver_name[] = "vmxnet3"; 32 #define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver" 33 34 /* 35 * PCI Device ID Table 36 * Last entry must be all 0s 37 */ 38 static DEFINE_PCI_DEVICE_TABLE(vmxnet3_pciid_table) = { 39 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)}, 40 {0} 41 }; 42 43 MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table); 44 45 static atomic_t devices_found; 46 47 #define VMXNET3_MAX_DEVICES 10 48 static int enable_mq = 1; 49 static int irq_share_mode; 50 51 static void 52 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac); 53 54 /* 55 * Enable/Disable the given intr 56 */ 57 static void 58 vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx) 59 { 60 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0); 61 } 62 63 64 static void 65 vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx) 66 { 67 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1); 68 } 69 70 71 /* 72 * Enable/Disable all intrs used by the device 73 */ 74 static void 75 vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter) 76 { 77 int i; 78 79 for (i = 0; i < adapter->intr.num_intrs; i++) 80 vmxnet3_enable_intr(adapter, i); 81 adapter->shared->devRead.intrConf.intrCtrl &= 82 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL); 83 } 84 85 86 static void 87 vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter) 88 { 89 int i; 90 91 adapter->shared->devRead.intrConf.intrCtrl |= 92 cpu_to_le32(VMXNET3_IC_DISABLE_ALL); 93 for (i = 0; i < adapter->intr.num_intrs; i++) 94 vmxnet3_disable_intr(adapter, i); 95 } 96 97 98 static void 99 vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events) 100 { 101 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events); 102 } 103 104 105 static bool 106 vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 107 { 108 return tq->stopped; 109 } 110 111 112 static void 113 vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 114 { 115 tq->stopped = false; 116 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue); 117 } 118 119 120 static void 121 vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 122 { 123 tq->stopped = false; 124 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue)); 125 } 126 127 128 static void 129 vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 130 { 131 tq->stopped = true; 132 tq->num_stop++; 133 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue)); 134 } 135 136 137 /* 138 * Check the link state. This may start or stop the tx queue. 139 */ 140 static void 141 vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue) 142 { 143 u32 ret; 144 int i; 145 unsigned long flags; 146 147 spin_lock_irqsave(&adapter->cmd_lock, flags); 148 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 149 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 150 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 151 152 adapter->link_speed = ret >> 16; 153 if (ret & 1) { /* Link is up. */ 154 printk(KERN_INFO "%s: NIC Link is Up %d Mbps\n", 155 adapter->netdev->name, adapter->link_speed); 156 if (!netif_carrier_ok(adapter->netdev)) 157 netif_carrier_on(adapter->netdev); 158 159 if (affectTxQueue) { 160 for (i = 0; i < adapter->num_tx_queues; i++) 161 vmxnet3_tq_start(&adapter->tx_queue[i], 162 adapter); 163 } 164 } else { 165 printk(KERN_INFO "%s: NIC Link is Down\n", 166 adapter->netdev->name); 167 if (netif_carrier_ok(adapter->netdev)) 168 netif_carrier_off(adapter->netdev); 169 170 if (affectTxQueue) { 171 for (i = 0; i < adapter->num_tx_queues; i++) 172 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter); 173 } 174 } 175 } 176 177 static void 178 vmxnet3_process_events(struct vmxnet3_adapter *adapter) 179 { 180 int i; 181 unsigned long flags; 182 u32 events = le32_to_cpu(adapter->shared->ecr); 183 if (!events) 184 return; 185 186 vmxnet3_ack_events(adapter, events); 187 188 /* Check if link state has changed */ 189 if (events & VMXNET3_ECR_LINK) 190 vmxnet3_check_link(adapter, true); 191 192 /* Check if there is an error on xmit/recv queues */ 193 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 194 spin_lock_irqsave(&adapter->cmd_lock, flags); 195 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 196 VMXNET3_CMD_GET_QUEUE_STATUS); 197 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 198 199 for (i = 0; i < adapter->num_tx_queues; i++) 200 if (adapter->tqd_start[i].status.stopped) 201 dev_err(&adapter->netdev->dev, 202 "%s: tq[%d] error 0x%x\n", 203 adapter->netdev->name, i, le32_to_cpu( 204 adapter->tqd_start[i].status.error)); 205 for (i = 0; i < adapter->num_rx_queues; i++) 206 if (adapter->rqd_start[i].status.stopped) 207 dev_err(&adapter->netdev->dev, 208 "%s: rq[%d] error 0x%x\n", 209 adapter->netdev->name, i, 210 adapter->rqd_start[i].status.error); 211 212 schedule_work(&adapter->work); 213 } 214 } 215 216 #ifdef __BIG_ENDIAN_BITFIELD 217 /* 218 * The device expects the bitfields in shared structures to be written in 219 * little endian. When CPU is big endian, the following routines are used to 220 * correctly read and write into ABI. 221 * The general technique used here is : double word bitfields are defined in 222 * opposite order for big endian architecture. Then before reading them in 223 * driver the complete double word is translated using le32_to_cpu. Similarly 224 * After the driver writes into bitfields, cpu_to_le32 is used to translate the 225 * double words into required format. 226 * In order to avoid touching bits in shared structure more than once, temporary 227 * descriptors are used. These are passed as srcDesc to following functions. 228 */ 229 static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc, 230 struct Vmxnet3_RxDesc *dstDesc) 231 { 232 u32 *src = (u32 *)srcDesc + 2; 233 u32 *dst = (u32 *)dstDesc + 2; 234 dstDesc->addr = le64_to_cpu(srcDesc->addr); 235 *dst = le32_to_cpu(*src); 236 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1); 237 } 238 239 static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc, 240 struct Vmxnet3_TxDesc *dstDesc) 241 { 242 int i; 243 u32 *src = (u32 *)(srcDesc + 1); 244 u32 *dst = (u32 *)(dstDesc + 1); 245 246 /* Working backwards so that the gen bit is set at the end. */ 247 for (i = 2; i > 0; i--) { 248 src--; 249 dst--; 250 *dst = cpu_to_le32(*src); 251 } 252 } 253 254 255 static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc, 256 struct Vmxnet3_RxCompDesc *dstDesc) 257 { 258 int i = 0; 259 u32 *src = (u32 *)srcDesc; 260 u32 *dst = (u32 *)dstDesc; 261 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) { 262 *dst = le32_to_cpu(*src); 263 src++; 264 dst++; 265 } 266 } 267 268 269 /* Used to read bitfield values from double words. */ 270 static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size) 271 { 272 u32 temp = le32_to_cpu(*bitfield); 273 u32 mask = ((1 << size) - 1) << pos; 274 temp &= mask; 275 temp >>= pos; 276 return temp; 277 } 278 279 280 281 #endif /* __BIG_ENDIAN_BITFIELD */ 282 283 #ifdef __BIG_ENDIAN_BITFIELD 284 285 # define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \ 286 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \ 287 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE) 288 # define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \ 289 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \ 290 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE) 291 # define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \ 292 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \ 293 VMXNET3_TCD_GEN_SIZE) 294 # define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \ 295 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE) 296 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \ 297 (dstrcd) = (tmp); \ 298 vmxnet3_RxCompToCPU((rcd), (tmp)); \ 299 } while (0) 300 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \ 301 (dstrxd) = (tmp); \ 302 vmxnet3_RxDescToCPU((rxd), (tmp)); \ 303 } while (0) 304 305 #else 306 307 # define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen) 308 # define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop) 309 # define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen) 310 # define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx) 311 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd) 312 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd) 313 314 #endif /* __BIG_ENDIAN_BITFIELD */ 315 316 317 static void 318 vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi, 319 struct pci_dev *pdev) 320 { 321 if (tbi->map_type == VMXNET3_MAP_SINGLE) 322 pci_unmap_single(pdev, tbi->dma_addr, tbi->len, 323 PCI_DMA_TODEVICE); 324 else if (tbi->map_type == VMXNET3_MAP_PAGE) 325 pci_unmap_page(pdev, tbi->dma_addr, tbi->len, 326 PCI_DMA_TODEVICE); 327 else 328 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE); 329 330 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */ 331 } 332 333 334 static int 335 vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq, 336 struct pci_dev *pdev, struct vmxnet3_adapter *adapter) 337 { 338 struct sk_buff *skb; 339 int entries = 0; 340 341 /* no out of order completion */ 342 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp); 343 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1); 344 345 skb = tq->buf_info[eop_idx].skb; 346 BUG_ON(skb == NULL); 347 tq->buf_info[eop_idx].skb = NULL; 348 349 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size); 350 351 while (tq->tx_ring.next2comp != eop_idx) { 352 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp, 353 pdev); 354 355 /* update next2comp w/o tx_lock. Since we are marking more, 356 * instead of less, tx ring entries avail, the worst case is 357 * that the tx routine incorrectly re-queues a pkt due to 358 * insufficient tx ring entries. 359 */ 360 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring); 361 entries++; 362 } 363 364 dev_kfree_skb_any(skb); 365 return entries; 366 } 367 368 369 static int 370 vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq, 371 struct vmxnet3_adapter *adapter) 372 { 373 int completed = 0; 374 union Vmxnet3_GenericDesc *gdesc; 375 376 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; 377 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) { 378 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX( 379 &gdesc->tcd), tq, adapter->pdev, 380 adapter); 381 382 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring); 383 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; 384 } 385 386 if (completed) { 387 spin_lock(&tq->tx_lock); 388 if (unlikely(vmxnet3_tq_stopped(tq, adapter) && 389 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) > 390 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) && 391 netif_carrier_ok(adapter->netdev))) { 392 vmxnet3_tq_wake(tq, adapter); 393 } 394 spin_unlock(&tq->tx_lock); 395 } 396 return completed; 397 } 398 399 400 static void 401 vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq, 402 struct vmxnet3_adapter *adapter) 403 { 404 int i; 405 406 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) { 407 struct vmxnet3_tx_buf_info *tbi; 408 union Vmxnet3_GenericDesc *gdesc; 409 410 tbi = tq->buf_info + tq->tx_ring.next2comp; 411 gdesc = tq->tx_ring.base + tq->tx_ring.next2comp; 412 413 vmxnet3_unmap_tx_buf(tbi, adapter->pdev); 414 if (tbi->skb) { 415 dev_kfree_skb_any(tbi->skb); 416 tbi->skb = NULL; 417 } 418 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring); 419 } 420 421 /* sanity check, verify all buffers are indeed unmapped and freed */ 422 for (i = 0; i < tq->tx_ring.size; i++) { 423 BUG_ON(tq->buf_info[i].skb != NULL || 424 tq->buf_info[i].map_type != VMXNET3_MAP_NONE); 425 } 426 427 tq->tx_ring.gen = VMXNET3_INIT_GEN; 428 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0; 429 430 tq->comp_ring.gen = VMXNET3_INIT_GEN; 431 tq->comp_ring.next2proc = 0; 432 } 433 434 435 static void 436 vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq, 437 struct vmxnet3_adapter *adapter) 438 { 439 if (tq->tx_ring.base) { 440 pci_free_consistent(adapter->pdev, tq->tx_ring.size * 441 sizeof(struct Vmxnet3_TxDesc), 442 tq->tx_ring.base, tq->tx_ring.basePA); 443 tq->tx_ring.base = NULL; 444 } 445 if (tq->data_ring.base) { 446 pci_free_consistent(adapter->pdev, tq->data_ring.size * 447 sizeof(struct Vmxnet3_TxDataDesc), 448 tq->data_ring.base, tq->data_ring.basePA); 449 tq->data_ring.base = NULL; 450 } 451 if (tq->comp_ring.base) { 452 pci_free_consistent(adapter->pdev, tq->comp_ring.size * 453 sizeof(struct Vmxnet3_TxCompDesc), 454 tq->comp_ring.base, tq->comp_ring.basePA); 455 tq->comp_ring.base = NULL; 456 } 457 kfree(tq->buf_info); 458 tq->buf_info = NULL; 459 } 460 461 462 /* Destroy all tx queues */ 463 void 464 vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter) 465 { 466 int i; 467 468 for (i = 0; i < adapter->num_tx_queues; i++) 469 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter); 470 } 471 472 473 static void 474 vmxnet3_tq_init(struct vmxnet3_tx_queue *tq, 475 struct vmxnet3_adapter *adapter) 476 { 477 int i; 478 479 /* reset the tx ring contents to 0 and reset the tx ring states */ 480 memset(tq->tx_ring.base, 0, tq->tx_ring.size * 481 sizeof(struct Vmxnet3_TxDesc)); 482 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0; 483 tq->tx_ring.gen = VMXNET3_INIT_GEN; 484 485 memset(tq->data_ring.base, 0, tq->data_ring.size * 486 sizeof(struct Vmxnet3_TxDataDesc)); 487 488 /* reset the tx comp ring contents to 0 and reset comp ring states */ 489 memset(tq->comp_ring.base, 0, tq->comp_ring.size * 490 sizeof(struct Vmxnet3_TxCompDesc)); 491 tq->comp_ring.next2proc = 0; 492 tq->comp_ring.gen = VMXNET3_INIT_GEN; 493 494 /* reset the bookkeeping data */ 495 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size); 496 for (i = 0; i < tq->tx_ring.size; i++) 497 tq->buf_info[i].map_type = VMXNET3_MAP_NONE; 498 499 /* stats are not reset */ 500 } 501 502 503 static int 504 vmxnet3_tq_create(struct vmxnet3_tx_queue *tq, 505 struct vmxnet3_adapter *adapter) 506 { 507 BUG_ON(tq->tx_ring.base || tq->data_ring.base || 508 tq->comp_ring.base || tq->buf_info); 509 510 tq->tx_ring.base = pci_alloc_consistent(adapter->pdev, tq->tx_ring.size 511 * sizeof(struct Vmxnet3_TxDesc), 512 &tq->tx_ring.basePA); 513 if (!tq->tx_ring.base) { 514 printk(KERN_ERR "%s: failed to allocate tx ring\n", 515 adapter->netdev->name); 516 goto err; 517 } 518 519 tq->data_ring.base = pci_alloc_consistent(adapter->pdev, 520 tq->data_ring.size * 521 sizeof(struct Vmxnet3_TxDataDesc), 522 &tq->data_ring.basePA); 523 if (!tq->data_ring.base) { 524 printk(KERN_ERR "%s: failed to allocate data ring\n", 525 adapter->netdev->name); 526 goto err; 527 } 528 529 tq->comp_ring.base = pci_alloc_consistent(adapter->pdev, 530 tq->comp_ring.size * 531 sizeof(struct Vmxnet3_TxCompDesc), 532 &tq->comp_ring.basePA); 533 if (!tq->comp_ring.base) { 534 printk(KERN_ERR "%s: failed to allocate tx comp ring\n", 535 adapter->netdev->name); 536 goto err; 537 } 538 539 tq->buf_info = kcalloc(tq->tx_ring.size, sizeof(tq->buf_info[0]), 540 GFP_KERNEL); 541 if (!tq->buf_info) { 542 printk(KERN_ERR "%s: failed to allocate tx bufinfo\n", 543 adapter->netdev->name); 544 goto err; 545 } 546 547 return 0; 548 549 err: 550 vmxnet3_tq_destroy(tq, adapter); 551 return -ENOMEM; 552 } 553 554 static void 555 vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter) 556 { 557 int i; 558 559 for (i = 0; i < adapter->num_tx_queues; i++) 560 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter); 561 } 562 563 /* 564 * starting from ring->next2fill, allocate rx buffers for the given ring 565 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers 566 * are allocated or allocation fails 567 */ 568 569 static int 570 vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx, 571 int num_to_alloc, struct vmxnet3_adapter *adapter) 572 { 573 int num_allocated = 0; 574 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx]; 575 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx]; 576 u32 val; 577 578 while (num_allocated < num_to_alloc) { 579 struct vmxnet3_rx_buf_info *rbi; 580 union Vmxnet3_GenericDesc *gd; 581 582 rbi = rbi_base + ring->next2fill; 583 gd = ring->base + ring->next2fill; 584 585 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) { 586 if (rbi->skb == NULL) { 587 rbi->skb = dev_alloc_skb(rbi->len + 588 NET_IP_ALIGN); 589 if (unlikely(rbi->skb == NULL)) { 590 rq->stats.rx_buf_alloc_failure++; 591 break; 592 } 593 rbi->skb->dev = adapter->netdev; 594 595 skb_reserve(rbi->skb, NET_IP_ALIGN); 596 rbi->dma_addr = pci_map_single(adapter->pdev, 597 rbi->skb->data, rbi->len, 598 PCI_DMA_FROMDEVICE); 599 } else { 600 /* rx buffer skipped by the device */ 601 } 602 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT; 603 } else { 604 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE || 605 rbi->len != PAGE_SIZE); 606 607 if (rbi->page == NULL) { 608 rbi->page = alloc_page(GFP_ATOMIC); 609 if (unlikely(rbi->page == NULL)) { 610 rq->stats.rx_buf_alloc_failure++; 611 break; 612 } 613 rbi->dma_addr = pci_map_page(adapter->pdev, 614 rbi->page, 0, PAGE_SIZE, 615 PCI_DMA_FROMDEVICE); 616 } else { 617 /* rx buffers skipped by the device */ 618 } 619 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT; 620 } 621 622 BUG_ON(rbi->dma_addr == 0); 623 gd->rxd.addr = cpu_to_le64(rbi->dma_addr); 624 gd->dword[2] = cpu_to_le32((ring->gen << VMXNET3_RXD_GEN_SHIFT) 625 | val | rbi->len); 626 627 num_allocated++; 628 vmxnet3_cmd_ring_adv_next2fill(ring); 629 } 630 rq->uncommitted[ring_idx] += num_allocated; 631 632 dev_dbg(&adapter->netdev->dev, 633 "alloc_rx_buf: %d allocated, next2fill %u, next2comp " 634 "%u, uncommited %u\n", num_allocated, ring->next2fill, 635 ring->next2comp, rq->uncommitted[ring_idx]); 636 637 /* so that the device can distinguish a full ring and an empty ring */ 638 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp); 639 640 return num_allocated; 641 } 642 643 644 static void 645 vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd, 646 struct vmxnet3_rx_buf_info *rbi) 647 { 648 struct skb_frag_struct *frag = skb_shinfo(skb)->frags + 649 skb_shinfo(skb)->nr_frags; 650 651 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS); 652 653 frag->page = rbi->page; 654 frag->page_offset = 0; 655 frag->size = rcd->len; 656 skb->data_len += frag->size; 657 skb_shinfo(skb)->nr_frags++; 658 } 659 660 661 static void 662 vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx, 663 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev, 664 struct vmxnet3_adapter *adapter) 665 { 666 u32 dw2, len; 667 unsigned long buf_offset; 668 int i; 669 union Vmxnet3_GenericDesc *gdesc; 670 struct vmxnet3_tx_buf_info *tbi = NULL; 671 672 BUG_ON(ctx->copy_size > skb_headlen(skb)); 673 674 /* use the previous gen bit for the SOP desc */ 675 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT; 676 677 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill; 678 gdesc = ctx->sop_txd; /* both loops below can be skipped */ 679 680 /* no need to map the buffer if headers are copied */ 681 if (ctx->copy_size) { 682 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA + 683 tq->tx_ring.next2fill * 684 sizeof(struct Vmxnet3_TxDataDesc)); 685 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size); 686 ctx->sop_txd->dword[3] = 0; 687 688 tbi = tq->buf_info + tq->tx_ring.next2fill; 689 tbi->map_type = VMXNET3_MAP_NONE; 690 691 dev_dbg(&adapter->netdev->dev, 692 "txd[%u]: 0x%Lx 0x%x 0x%x\n", 693 tq->tx_ring.next2fill, 694 le64_to_cpu(ctx->sop_txd->txd.addr), 695 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]); 696 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 697 698 /* use the right gen for non-SOP desc */ 699 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 700 } 701 702 /* linear part can use multiple tx desc if it's big */ 703 len = skb_headlen(skb) - ctx->copy_size; 704 buf_offset = ctx->copy_size; 705 while (len) { 706 u32 buf_size; 707 708 if (len < VMXNET3_MAX_TX_BUF_SIZE) { 709 buf_size = len; 710 dw2 |= len; 711 } else { 712 buf_size = VMXNET3_MAX_TX_BUF_SIZE; 713 /* spec says that for TxDesc.len, 0 == 2^14 */ 714 } 715 716 tbi = tq->buf_info + tq->tx_ring.next2fill; 717 tbi->map_type = VMXNET3_MAP_SINGLE; 718 tbi->dma_addr = pci_map_single(adapter->pdev, 719 skb->data + buf_offset, buf_size, 720 PCI_DMA_TODEVICE); 721 722 tbi->len = buf_size; 723 724 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; 725 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); 726 727 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); 728 gdesc->dword[2] = cpu_to_le32(dw2); 729 gdesc->dword[3] = 0; 730 731 dev_dbg(&adapter->netdev->dev, 732 "txd[%u]: 0x%Lx 0x%x 0x%x\n", 733 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), 734 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); 735 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 736 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 737 738 len -= buf_size; 739 buf_offset += buf_size; 740 } 741 742 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 743 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 744 745 tbi = tq->buf_info + tq->tx_ring.next2fill; 746 tbi->map_type = VMXNET3_MAP_PAGE; 747 tbi->dma_addr = pci_map_page(adapter->pdev, frag->page, 748 frag->page_offset, frag->size, 749 PCI_DMA_TODEVICE); 750 751 tbi->len = frag->size; 752 753 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; 754 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); 755 756 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); 757 gdesc->dword[2] = cpu_to_le32(dw2 | frag->size); 758 gdesc->dword[3] = 0; 759 760 dev_dbg(&adapter->netdev->dev, 761 "txd[%u]: 0x%llu %u %u\n", 762 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), 763 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); 764 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 765 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 766 } 767 768 ctx->eop_txd = gdesc; 769 770 /* set the last buf_info for the pkt */ 771 tbi->skb = skb; 772 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base; 773 } 774 775 776 /* Init all tx queues */ 777 static void 778 vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter) 779 { 780 int i; 781 782 for (i = 0; i < adapter->num_tx_queues; i++) 783 vmxnet3_tq_init(&adapter->tx_queue[i], adapter); 784 } 785 786 787 /* 788 * parse and copy relevant protocol headers: 789 * For a tso pkt, relevant headers are L2/3/4 including options 790 * For a pkt requesting csum offloading, they are L2/3 and may include L4 791 * if it's a TCP/UDP pkt 792 * 793 * Returns: 794 * -1: error happens during parsing 795 * 0: protocol headers parsed, but too big to be copied 796 * 1: protocol headers parsed and copied 797 * 798 * Other effects: 799 * 1. related *ctx fields are updated. 800 * 2. ctx->copy_size is # of bytes copied 801 * 3. the portion copied is guaranteed to be in the linear part 802 * 803 */ 804 static int 805 vmxnet3_parse_and_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 806 struct vmxnet3_tx_ctx *ctx, 807 struct vmxnet3_adapter *adapter) 808 { 809 struct Vmxnet3_TxDataDesc *tdd; 810 811 if (ctx->mss) { /* TSO */ 812 ctx->eth_ip_hdr_size = skb_transport_offset(skb); 813 ctx->l4_hdr_size = ((struct tcphdr *) 814 skb_transport_header(skb))->doff * 4; 815 ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size; 816 } else { 817 if (skb->ip_summed == CHECKSUM_PARTIAL) { 818 ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb); 819 820 if (ctx->ipv4) { 821 struct iphdr *iph = (struct iphdr *) 822 skb_network_header(skb); 823 if (iph->protocol == IPPROTO_TCP) 824 ctx->l4_hdr_size = ((struct tcphdr *) 825 skb_transport_header(skb))->doff * 4; 826 else if (iph->protocol == IPPROTO_UDP) 827 /* 828 * Use tcp header size so that bytes to 829 * be copied are more than required by 830 * the device. 831 */ 832 ctx->l4_hdr_size = 833 sizeof(struct tcphdr); 834 else 835 ctx->l4_hdr_size = 0; 836 } else { 837 /* for simplicity, don't copy L4 headers */ 838 ctx->l4_hdr_size = 0; 839 } 840 ctx->copy_size = ctx->eth_ip_hdr_size + 841 ctx->l4_hdr_size; 842 } else { 843 ctx->eth_ip_hdr_size = 0; 844 ctx->l4_hdr_size = 0; 845 /* copy as much as allowed */ 846 ctx->copy_size = min((unsigned int)VMXNET3_HDR_COPY_SIZE 847 , skb_headlen(skb)); 848 } 849 850 /* make sure headers are accessible directly */ 851 if (unlikely(!pskb_may_pull(skb, ctx->copy_size))) 852 goto err; 853 } 854 855 if (unlikely(ctx->copy_size > VMXNET3_HDR_COPY_SIZE)) { 856 tq->stats.oversized_hdr++; 857 ctx->copy_size = 0; 858 return 0; 859 } 860 861 tdd = tq->data_ring.base + tq->tx_ring.next2fill; 862 863 memcpy(tdd->data, skb->data, ctx->copy_size); 864 dev_dbg(&adapter->netdev->dev, 865 "copy %u bytes to dataRing[%u]\n", 866 ctx->copy_size, tq->tx_ring.next2fill); 867 return 1; 868 869 err: 870 return -1; 871 } 872 873 874 static void 875 vmxnet3_prepare_tso(struct sk_buff *skb, 876 struct vmxnet3_tx_ctx *ctx) 877 { 878 struct tcphdr *tcph = (struct tcphdr *)skb_transport_header(skb); 879 if (ctx->ipv4) { 880 struct iphdr *iph = (struct iphdr *)skb_network_header(skb); 881 iph->check = 0; 882 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0, 883 IPPROTO_TCP, 0); 884 } else { 885 struct ipv6hdr *iph = (struct ipv6hdr *)skb_network_header(skb); 886 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0, 887 IPPROTO_TCP, 0); 888 } 889 } 890 891 892 /* 893 * Transmits a pkt thru a given tq 894 * Returns: 895 * NETDEV_TX_OK: descriptors are setup successfully 896 * NETDEV_TX_OK: error occurred, the pkt is dropped 897 * NETDEV_TX_BUSY: tx ring is full, queue is stopped 898 * 899 * Side-effects: 900 * 1. tx ring may be changed 901 * 2. tq stats may be updated accordingly 902 * 3. shared->txNumDeferred may be updated 903 */ 904 905 static int 906 vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 907 struct vmxnet3_adapter *adapter, struct net_device *netdev) 908 { 909 int ret; 910 u32 count; 911 unsigned long flags; 912 struct vmxnet3_tx_ctx ctx; 913 union Vmxnet3_GenericDesc *gdesc; 914 #ifdef __BIG_ENDIAN_BITFIELD 915 /* Use temporary descriptor to avoid touching bits multiple times */ 916 union Vmxnet3_GenericDesc tempTxDesc; 917 #endif 918 919 /* conservatively estimate # of descriptors to use */ 920 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 921 skb_shinfo(skb)->nr_frags + 1; 922 923 ctx.ipv4 = (skb->protocol == cpu_to_be16(ETH_P_IP)); 924 925 ctx.mss = skb_shinfo(skb)->gso_size; 926 if (ctx.mss) { 927 if (skb_header_cloned(skb)) { 928 if (unlikely(pskb_expand_head(skb, 0, 0, 929 GFP_ATOMIC) != 0)) { 930 tq->stats.drop_tso++; 931 goto drop_pkt; 932 } 933 tq->stats.copy_skb_header++; 934 } 935 vmxnet3_prepare_tso(skb, &ctx); 936 } else { 937 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) { 938 939 /* non-tso pkts must not use more than 940 * VMXNET3_MAX_TXD_PER_PKT entries 941 */ 942 if (skb_linearize(skb) != 0) { 943 tq->stats.drop_too_many_frags++; 944 goto drop_pkt; 945 } 946 tq->stats.linearized++; 947 948 /* recalculate the # of descriptors to use */ 949 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1; 950 } 951 } 952 953 spin_lock_irqsave(&tq->tx_lock, flags); 954 955 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) { 956 tq->stats.tx_ring_full++; 957 dev_dbg(&adapter->netdev->dev, 958 "tx queue stopped on %s, next2comp %u" 959 " next2fill %u\n", adapter->netdev->name, 960 tq->tx_ring.next2comp, tq->tx_ring.next2fill); 961 962 vmxnet3_tq_stop(tq, adapter); 963 spin_unlock_irqrestore(&tq->tx_lock, flags); 964 return NETDEV_TX_BUSY; 965 } 966 967 968 ret = vmxnet3_parse_and_copy_hdr(skb, tq, &ctx, adapter); 969 if (ret >= 0) { 970 BUG_ON(ret <= 0 && ctx.copy_size != 0); 971 /* hdrs parsed, check against other limits */ 972 if (ctx.mss) { 973 if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size > 974 VMXNET3_MAX_TX_BUF_SIZE)) { 975 goto hdr_too_big; 976 } 977 } else { 978 if (skb->ip_summed == CHECKSUM_PARTIAL) { 979 if (unlikely(ctx.eth_ip_hdr_size + 980 skb->csum_offset > 981 VMXNET3_MAX_CSUM_OFFSET)) { 982 goto hdr_too_big; 983 } 984 } 985 } 986 } else { 987 tq->stats.drop_hdr_inspect_err++; 988 goto unlock_drop_pkt; 989 } 990 991 /* fill tx descs related to addr & len */ 992 vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter); 993 994 /* setup the EOP desc */ 995 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP); 996 997 /* setup the SOP desc */ 998 #ifdef __BIG_ENDIAN_BITFIELD 999 gdesc = &tempTxDesc; 1000 gdesc->dword[2] = ctx.sop_txd->dword[2]; 1001 gdesc->dword[3] = ctx.sop_txd->dword[3]; 1002 #else 1003 gdesc = ctx.sop_txd; 1004 #endif 1005 if (ctx.mss) { 1006 gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size; 1007 gdesc->txd.om = VMXNET3_OM_TSO; 1008 gdesc->txd.msscof = ctx.mss; 1009 le32_add_cpu(&tq->shared->txNumDeferred, (skb->len - 1010 gdesc->txd.hlen + ctx.mss - 1) / ctx.mss); 1011 } else { 1012 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1013 gdesc->txd.hlen = ctx.eth_ip_hdr_size; 1014 gdesc->txd.om = VMXNET3_OM_CSUM; 1015 gdesc->txd.msscof = ctx.eth_ip_hdr_size + 1016 skb->csum_offset; 1017 } else { 1018 gdesc->txd.om = 0; 1019 gdesc->txd.msscof = 0; 1020 } 1021 le32_add_cpu(&tq->shared->txNumDeferred, 1); 1022 } 1023 1024 if (vlan_tx_tag_present(skb)) { 1025 gdesc->txd.ti = 1; 1026 gdesc->txd.tci = vlan_tx_tag_get(skb); 1027 } 1028 1029 /* finally flips the GEN bit of the SOP desc. */ 1030 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^ 1031 VMXNET3_TXD_GEN); 1032 #ifdef __BIG_ENDIAN_BITFIELD 1033 /* Finished updating in bitfields of Tx Desc, so write them in original 1034 * place. 1035 */ 1036 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc, 1037 (struct Vmxnet3_TxDesc *)ctx.sop_txd); 1038 gdesc = ctx.sop_txd; 1039 #endif 1040 dev_dbg(&adapter->netdev->dev, 1041 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n", 1042 (u32)((union Vmxnet3_GenericDesc *)ctx.sop_txd - 1043 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr), 1044 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3])); 1045 1046 spin_unlock_irqrestore(&tq->tx_lock, flags); 1047 1048 if (le32_to_cpu(tq->shared->txNumDeferred) >= 1049 le32_to_cpu(tq->shared->txThreshold)) { 1050 tq->shared->txNumDeferred = 0; 1051 VMXNET3_WRITE_BAR0_REG(adapter, 1052 VMXNET3_REG_TXPROD + tq->qid * 8, 1053 tq->tx_ring.next2fill); 1054 } 1055 1056 return NETDEV_TX_OK; 1057 1058 hdr_too_big: 1059 tq->stats.drop_oversized_hdr++; 1060 unlock_drop_pkt: 1061 spin_unlock_irqrestore(&tq->tx_lock, flags); 1062 drop_pkt: 1063 tq->stats.drop_total++; 1064 dev_kfree_skb(skb); 1065 return NETDEV_TX_OK; 1066 } 1067 1068 1069 static netdev_tx_t 1070 vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 1071 { 1072 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1073 1074 BUG_ON(skb->queue_mapping > adapter->num_tx_queues); 1075 return vmxnet3_tq_xmit(skb, 1076 &adapter->tx_queue[skb->queue_mapping], 1077 adapter, netdev); 1078 } 1079 1080 1081 static void 1082 vmxnet3_rx_csum(struct vmxnet3_adapter *adapter, 1083 struct sk_buff *skb, 1084 union Vmxnet3_GenericDesc *gdesc) 1085 { 1086 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) { 1087 /* typical case: TCP/UDP over IP and both csums are correct */ 1088 if ((le32_to_cpu(gdesc->dword[3]) & VMXNET3_RCD_CSUM_OK) == 1089 VMXNET3_RCD_CSUM_OK) { 1090 skb->ip_summed = CHECKSUM_UNNECESSARY; 1091 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp)); 1092 BUG_ON(!(gdesc->rcd.v4 || gdesc->rcd.v6)); 1093 BUG_ON(gdesc->rcd.frg); 1094 } else { 1095 if (gdesc->rcd.csum) { 1096 skb->csum = htons(gdesc->rcd.csum); 1097 skb->ip_summed = CHECKSUM_PARTIAL; 1098 } else { 1099 skb_checksum_none_assert(skb); 1100 } 1101 } 1102 } else { 1103 skb_checksum_none_assert(skb); 1104 } 1105 } 1106 1107 1108 static void 1109 vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd, 1110 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter) 1111 { 1112 rq->stats.drop_err++; 1113 if (!rcd->fcs) 1114 rq->stats.drop_fcs++; 1115 1116 rq->stats.drop_total++; 1117 1118 /* 1119 * We do not unmap and chain the rx buffer to the skb. 1120 * We basically pretend this buffer is not used and will be recycled 1121 * by vmxnet3_rq_alloc_rx_buf() 1122 */ 1123 1124 /* 1125 * ctx->skb may be NULL if this is the first and the only one 1126 * desc for the pkt 1127 */ 1128 if (ctx->skb) 1129 dev_kfree_skb_irq(ctx->skb); 1130 1131 ctx->skb = NULL; 1132 } 1133 1134 1135 static int 1136 vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq, 1137 struct vmxnet3_adapter *adapter, int quota) 1138 { 1139 static const u32 rxprod_reg[2] = { 1140 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2 1141 }; 1142 u32 num_rxd = 0; 1143 struct Vmxnet3_RxCompDesc *rcd; 1144 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx; 1145 #ifdef __BIG_ENDIAN_BITFIELD 1146 struct Vmxnet3_RxDesc rxCmdDesc; 1147 struct Vmxnet3_RxCompDesc rxComp; 1148 #endif 1149 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, 1150 &rxComp); 1151 while (rcd->gen == rq->comp_ring.gen) { 1152 struct vmxnet3_rx_buf_info *rbi; 1153 struct sk_buff *skb; 1154 int num_to_alloc; 1155 struct Vmxnet3_RxDesc *rxd; 1156 u32 idx, ring_idx; 1157 1158 if (num_rxd >= quota) { 1159 /* we may stop even before we see the EOP desc of 1160 * the current pkt 1161 */ 1162 break; 1163 } 1164 num_rxd++; 1165 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2); 1166 idx = rcd->rxdIdx; 1167 ring_idx = rcd->rqID < adapter->num_rx_queues ? 0 : 1; 1168 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd, 1169 &rxCmdDesc); 1170 rbi = rq->buf_info[ring_idx] + idx; 1171 1172 BUG_ON(rxd->addr != rbi->dma_addr || 1173 rxd->len != rbi->len); 1174 1175 if (unlikely(rcd->eop && rcd->err)) { 1176 vmxnet3_rx_error(rq, rcd, ctx, adapter); 1177 goto rcd_done; 1178 } 1179 1180 if (rcd->sop) { /* first buf of the pkt */ 1181 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD || 1182 rcd->rqID != rq->qid); 1183 1184 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB); 1185 BUG_ON(ctx->skb != NULL || rbi->skb == NULL); 1186 1187 if (unlikely(rcd->len == 0)) { 1188 /* Pretend the rx buffer is skipped. */ 1189 BUG_ON(!(rcd->sop && rcd->eop)); 1190 dev_dbg(&adapter->netdev->dev, 1191 "rxRing[%u][%u] 0 length\n", 1192 ring_idx, idx); 1193 goto rcd_done; 1194 } 1195 1196 ctx->skb = rbi->skb; 1197 rbi->skb = NULL; 1198 1199 pci_unmap_single(adapter->pdev, rbi->dma_addr, rbi->len, 1200 PCI_DMA_FROMDEVICE); 1201 1202 skb_put(ctx->skb, rcd->len); 1203 } else { 1204 BUG_ON(ctx->skb == NULL); 1205 /* non SOP buffer must be type 1 in most cases */ 1206 if (rbi->buf_type == VMXNET3_RX_BUF_PAGE) { 1207 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY); 1208 1209 if (rcd->len) { 1210 pci_unmap_page(adapter->pdev, 1211 rbi->dma_addr, rbi->len, 1212 PCI_DMA_FROMDEVICE); 1213 1214 vmxnet3_append_frag(ctx->skb, rcd, rbi); 1215 rbi->page = NULL; 1216 } 1217 } else { 1218 /* 1219 * The only time a non-SOP buffer is type 0 is 1220 * when it's EOP and error flag is raised, which 1221 * has already been handled. 1222 */ 1223 BUG_ON(true); 1224 } 1225 } 1226 1227 skb = ctx->skb; 1228 if (rcd->eop) { 1229 skb->len += skb->data_len; 1230 skb->truesize += skb->data_len; 1231 1232 vmxnet3_rx_csum(adapter, skb, 1233 (union Vmxnet3_GenericDesc *)rcd); 1234 skb->protocol = eth_type_trans(skb, adapter->netdev); 1235 1236 if (unlikely(adapter->vlan_grp && rcd->ts)) { 1237 vlan_hwaccel_receive_skb(skb, 1238 adapter->vlan_grp, rcd->tci); 1239 } else { 1240 netif_receive_skb(skb); 1241 } 1242 1243 ctx->skb = NULL; 1244 } 1245 1246 rcd_done: 1247 /* device may skip some rx descs */ 1248 rq->rx_ring[ring_idx].next2comp = idx; 1249 VMXNET3_INC_RING_IDX_ONLY(rq->rx_ring[ring_idx].next2comp, 1250 rq->rx_ring[ring_idx].size); 1251 1252 /* refill rx buffers frequently to avoid starving the h/w */ 1253 num_to_alloc = vmxnet3_cmd_ring_desc_avail(rq->rx_ring + 1254 ring_idx); 1255 if (unlikely(num_to_alloc > VMXNET3_RX_ALLOC_THRESHOLD(rq, 1256 ring_idx, adapter))) { 1257 vmxnet3_rq_alloc_rx_buf(rq, ring_idx, num_to_alloc, 1258 adapter); 1259 1260 /* if needed, update the register */ 1261 if (unlikely(rq->shared->updateRxProd)) { 1262 VMXNET3_WRITE_BAR0_REG(adapter, 1263 rxprod_reg[ring_idx] + rq->qid * 8, 1264 rq->rx_ring[ring_idx].next2fill); 1265 rq->uncommitted[ring_idx] = 0; 1266 } 1267 } 1268 1269 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring); 1270 vmxnet3_getRxComp(rcd, 1271 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp); 1272 } 1273 1274 return num_rxd; 1275 } 1276 1277 1278 static void 1279 vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq, 1280 struct vmxnet3_adapter *adapter) 1281 { 1282 u32 i, ring_idx; 1283 struct Vmxnet3_RxDesc *rxd; 1284 1285 for (ring_idx = 0; ring_idx < 2; ring_idx++) { 1286 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) { 1287 #ifdef __BIG_ENDIAN_BITFIELD 1288 struct Vmxnet3_RxDesc rxDesc; 1289 #endif 1290 vmxnet3_getRxDesc(rxd, 1291 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc); 1292 1293 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD && 1294 rq->buf_info[ring_idx][i].skb) { 1295 pci_unmap_single(adapter->pdev, rxd->addr, 1296 rxd->len, PCI_DMA_FROMDEVICE); 1297 dev_kfree_skb(rq->buf_info[ring_idx][i].skb); 1298 rq->buf_info[ring_idx][i].skb = NULL; 1299 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY && 1300 rq->buf_info[ring_idx][i].page) { 1301 pci_unmap_page(adapter->pdev, rxd->addr, 1302 rxd->len, PCI_DMA_FROMDEVICE); 1303 put_page(rq->buf_info[ring_idx][i].page); 1304 rq->buf_info[ring_idx][i].page = NULL; 1305 } 1306 } 1307 1308 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN; 1309 rq->rx_ring[ring_idx].next2fill = 1310 rq->rx_ring[ring_idx].next2comp = 0; 1311 rq->uncommitted[ring_idx] = 0; 1312 } 1313 1314 rq->comp_ring.gen = VMXNET3_INIT_GEN; 1315 rq->comp_ring.next2proc = 0; 1316 } 1317 1318 1319 static void 1320 vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter) 1321 { 1322 int i; 1323 1324 for (i = 0; i < adapter->num_rx_queues; i++) 1325 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter); 1326 } 1327 1328 1329 void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq, 1330 struct vmxnet3_adapter *adapter) 1331 { 1332 int i; 1333 int j; 1334 1335 /* all rx buffers must have already been freed */ 1336 for (i = 0; i < 2; i++) { 1337 if (rq->buf_info[i]) { 1338 for (j = 0; j < rq->rx_ring[i].size; j++) 1339 BUG_ON(rq->buf_info[i][j].page != NULL); 1340 } 1341 } 1342 1343 1344 kfree(rq->buf_info[0]); 1345 1346 for (i = 0; i < 2; i++) { 1347 if (rq->rx_ring[i].base) { 1348 pci_free_consistent(adapter->pdev, rq->rx_ring[i].size 1349 * sizeof(struct Vmxnet3_RxDesc), 1350 rq->rx_ring[i].base, 1351 rq->rx_ring[i].basePA); 1352 rq->rx_ring[i].base = NULL; 1353 } 1354 rq->buf_info[i] = NULL; 1355 } 1356 1357 if (rq->comp_ring.base) { 1358 pci_free_consistent(adapter->pdev, rq->comp_ring.size * 1359 sizeof(struct Vmxnet3_RxCompDesc), 1360 rq->comp_ring.base, rq->comp_ring.basePA); 1361 rq->comp_ring.base = NULL; 1362 } 1363 } 1364 1365 1366 static int 1367 vmxnet3_rq_init(struct vmxnet3_rx_queue *rq, 1368 struct vmxnet3_adapter *adapter) 1369 { 1370 int i; 1371 1372 /* initialize buf_info */ 1373 for (i = 0; i < rq->rx_ring[0].size; i++) { 1374 1375 /* 1st buf for a pkt is skbuff */ 1376 if (i % adapter->rx_buf_per_pkt == 0) { 1377 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB; 1378 rq->buf_info[0][i].len = adapter->skb_buf_size; 1379 } else { /* subsequent bufs for a pkt is frag */ 1380 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE; 1381 rq->buf_info[0][i].len = PAGE_SIZE; 1382 } 1383 } 1384 for (i = 0; i < rq->rx_ring[1].size; i++) { 1385 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE; 1386 rq->buf_info[1][i].len = PAGE_SIZE; 1387 } 1388 1389 /* reset internal state and allocate buffers for both rings */ 1390 for (i = 0; i < 2; i++) { 1391 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0; 1392 rq->uncommitted[i] = 0; 1393 1394 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size * 1395 sizeof(struct Vmxnet3_RxDesc)); 1396 rq->rx_ring[i].gen = VMXNET3_INIT_GEN; 1397 } 1398 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1, 1399 adapter) == 0) { 1400 /* at least has 1 rx buffer for the 1st ring */ 1401 return -ENOMEM; 1402 } 1403 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter); 1404 1405 /* reset the comp ring */ 1406 rq->comp_ring.next2proc = 0; 1407 memset(rq->comp_ring.base, 0, rq->comp_ring.size * 1408 sizeof(struct Vmxnet3_RxCompDesc)); 1409 rq->comp_ring.gen = VMXNET3_INIT_GEN; 1410 1411 /* reset rxctx */ 1412 rq->rx_ctx.skb = NULL; 1413 1414 /* stats are not reset */ 1415 return 0; 1416 } 1417 1418 1419 static int 1420 vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter) 1421 { 1422 int i, err = 0; 1423 1424 for (i = 0; i < adapter->num_rx_queues; i++) { 1425 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter); 1426 if (unlikely(err)) { 1427 dev_err(&adapter->netdev->dev, "%s: failed to " 1428 "initialize rx queue%i\n", 1429 adapter->netdev->name, i); 1430 break; 1431 } 1432 } 1433 return err; 1434 1435 } 1436 1437 1438 static int 1439 vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter) 1440 { 1441 int i; 1442 size_t sz; 1443 struct vmxnet3_rx_buf_info *bi; 1444 1445 for (i = 0; i < 2; i++) { 1446 1447 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc); 1448 rq->rx_ring[i].base = pci_alloc_consistent(adapter->pdev, sz, 1449 &rq->rx_ring[i].basePA); 1450 if (!rq->rx_ring[i].base) { 1451 printk(KERN_ERR "%s: failed to allocate rx ring %d\n", 1452 adapter->netdev->name, i); 1453 goto err; 1454 } 1455 } 1456 1457 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc); 1458 rq->comp_ring.base = pci_alloc_consistent(adapter->pdev, sz, 1459 &rq->comp_ring.basePA); 1460 if (!rq->comp_ring.base) { 1461 printk(KERN_ERR "%s: failed to allocate rx comp ring\n", 1462 adapter->netdev->name); 1463 goto err; 1464 } 1465 1466 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size + 1467 rq->rx_ring[1].size); 1468 bi = kzalloc(sz, GFP_KERNEL); 1469 if (!bi) { 1470 printk(KERN_ERR "%s: failed to allocate rx bufinfo\n", 1471 adapter->netdev->name); 1472 goto err; 1473 } 1474 rq->buf_info[0] = bi; 1475 rq->buf_info[1] = bi + rq->rx_ring[0].size; 1476 1477 return 0; 1478 1479 err: 1480 vmxnet3_rq_destroy(rq, adapter); 1481 return -ENOMEM; 1482 } 1483 1484 1485 static int 1486 vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter) 1487 { 1488 int i, err = 0; 1489 1490 for (i = 0; i < adapter->num_rx_queues; i++) { 1491 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter); 1492 if (unlikely(err)) { 1493 dev_err(&adapter->netdev->dev, 1494 "%s: failed to create rx queue%i\n", 1495 adapter->netdev->name, i); 1496 goto err_out; 1497 } 1498 } 1499 return err; 1500 err_out: 1501 vmxnet3_rq_destroy_all(adapter); 1502 return err; 1503 1504 } 1505 1506 /* Multiple queue aware polling function for tx and rx */ 1507 1508 static int 1509 vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget) 1510 { 1511 int rcd_done = 0, i; 1512 if (unlikely(adapter->shared->ecr)) 1513 vmxnet3_process_events(adapter); 1514 for (i = 0; i < adapter->num_tx_queues; i++) 1515 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter); 1516 1517 for (i = 0; i < adapter->num_rx_queues; i++) 1518 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i], 1519 adapter, budget); 1520 return rcd_done; 1521 } 1522 1523 1524 static int 1525 vmxnet3_poll(struct napi_struct *napi, int budget) 1526 { 1527 struct vmxnet3_rx_queue *rx_queue = container_of(napi, 1528 struct vmxnet3_rx_queue, napi); 1529 int rxd_done; 1530 1531 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget); 1532 1533 if (rxd_done < budget) { 1534 napi_complete(napi); 1535 vmxnet3_enable_all_intrs(rx_queue->adapter); 1536 } 1537 return rxd_done; 1538 } 1539 1540 /* 1541 * NAPI polling function for MSI-X mode with multiple Rx queues 1542 * Returns the # of the NAPI credit consumed (# of rx descriptors processed) 1543 */ 1544 1545 static int 1546 vmxnet3_poll_rx_only(struct napi_struct *napi, int budget) 1547 { 1548 struct vmxnet3_rx_queue *rq = container_of(napi, 1549 struct vmxnet3_rx_queue, napi); 1550 struct vmxnet3_adapter *adapter = rq->adapter; 1551 int rxd_done; 1552 1553 /* When sharing interrupt with corresponding tx queue, process 1554 * tx completions in that queue as well 1555 */ 1556 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) { 1557 struct vmxnet3_tx_queue *tq = 1558 &adapter->tx_queue[rq - adapter->rx_queue]; 1559 vmxnet3_tq_tx_complete(tq, adapter); 1560 } 1561 1562 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget); 1563 1564 if (rxd_done < budget) { 1565 napi_complete(napi); 1566 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx); 1567 } 1568 return rxd_done; 1569 } 1570 1571 1572 #ifdef CONFIG_PCI_MSI 1573 1574 /* 1575 * Handle completion interrupts on tx queues 1576 * Returns whether or not the intr is handled 1577 */ 1578 1579 static irqreturn_t 1580 vmxnet3_msix_tx(int irq, void *data) 1581 { 1582 struct vmxnet3_tx_queue *tq = data; 1583 struct vmxnet3_adapter *adapter = tq->adapter; 1584 1585 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1586 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx); 1587 1588 /* Handle the case where only one irq is allocate for all tx queues */ 1589 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) { 1590 int i; 1591 for (i = 0; i < adapter->num_tx_queues; i++) { 1592 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i]; 1593 vmxnet3_tq_tx_complete(txq, adapter); 1594 } 1595 } else { 1596 vmxnet3_tq_tx_complete(tq, adapter); 1597 } 1598 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx); 1599 1600 return IRQ_HANDLED; 1601 } 1602 1603 1604 /* 1605 * Handle completion interrupts on rx queues. Returns whether or not the 1606 * intr is handled 1607 */ 1608 1609 static irqreturn_t 1610 vmxnet3_msix_rx(int irq, void *data) 1611 { 1612 struct vmxnet3_rx_queue *rq = data; 1613 struct vmxnet3_adapter *adapter = rq->adapter; 1614 1615 /* disable intr if needed */ 1616 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1617 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx); 1618 napi_schedule(&rq->napi); 1619 1620 return IRQ_HANDLED; 1621 } 1622 1623 /* 1624 *---------------------------------------------------------------------------- 1625 * 1626 * vmxnet3_msix_event -- 1627 * 1628 * vmxnet3 msix event intr handler 1629 * 1630 * Result: 1631 * whether or not the intr is handled 1632 * 1633 *---------------------------------------------------------------------------- 1634 */ 1635 1636 static irqreturn_t 1637 vmxnet3_msix_event(int irq, void *data) 1638 { 1639 struct net_device *dev = data; 1640 struct vmxnet3_adapter *adapter = netdev_priv(dev); 1641 1642 /* disable intr if needed */ 1643 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1644 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx); 1645 1646 if (adapter->shared->ecr) 1647 vmxnet3_process_events(adapter); 1648 1649 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx); 1650 1651 return IRQ_HANDLED; 1652 } 1653 1654 #endif /* CONFIG_PCI_MSI */ 1655 1656 1657 /* Interrupt handler for vmxnet3 */ 1658 static irqreturn_t 1659 vmxnet3_intr(int irq, void *dev_id) 1660 { 1661 struct net_device *dev = dev_id; 1662 struct vmxnet3_adapter *adapter = netdev_priv(dev); 1663 1664 if (adapter->intr.type == VMXNET3_IT_INTX) { 1665 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR); 1666 if (unlikely(icr == 0)) 1667 /* not ours */ 1668 return IRQ_NONE; 1669 } 1670 1671 1672 /* disable intr if needed */ 1673 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1674 vmxnet3_disable_all_intrs(adapter); 1675 1676 napi_schedule(&adapter->rx_queue[0].napi); 1677 1678 return IRQ_HANDLED; 1679 } 1680 1681 #ifdef CONFIG_NET_POLL_CONTROLLER 1682 1683 /* netpoll callback. */ 1684 static void 1685 vmxnet3_netpoll(struct net_device *netdev) 1686 { 1687 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1688 1689 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1690 vmxnet3_disable_all_intrs(adapter); 1691 1692 vmxnet3_do_poll(adapter, adapter->rx_queue[0].rx_ring[0].size); 1693 vmxnet3_enable_all_intrs(adapter); 1694 1695 } 1696 #endif /* CONFIG_NET_POLL_CONTROLLER */ 1697 1698 static int 1699 vmxnet3_request_irqs(struct vmxnet3_adapter *adapter) 1700 { 1701 struct vmxnet3_intr *intr = &adapter->intr; 1702 int err = 0, i; 1703 int vector = 0; 1704 1705 #ifdef CONFIG_PCI_MSI 1706 if (adapter->intr.type == VMXNET3_IT_MSIX) { 1707 for (i = 0; i < adapter->num_tx_queues; i++) { 1708 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) { 1709 sprintf(adapter->tx_queue[i].name, "%s-tx-%d", 1710 adapter->netdev->name, vector); 1711 err = request_irq( 1712 intr->msix_entries[vector].vector, 1713 vmxnet3_msix_tx, 0, 1714 adapter->tx_queue[i].name, 1715 &adapter->tx_queue[i]); 1716 } else { 1717 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d", 1718 adapter->netdev->name, vector); 1719 } 1720 if (err) { 1721 dev_err(&adapter->netdev->dev, 1722 "Failed to request irq for MSIX, %s, " 1723 "error %d\n", 1724 adapter->tx_queue[i].name, err); 1725 return err; 1726 } 1727 1728 /* Handle the case where only 1 MSIx was allocated for 1729 * all tx queues */ 1730 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) { 1731 for (; i < adapter->num_tx_queues; i++) 1732 adapter->tx_queue[i].comp_ring.intr_idx 1733 = vector; 1734 vector++; 1735 break; 1736 } else { 1737 adapter->tx_queue[i].comp_ring.intr_idx 1738 = vector++; 1739 } 1740 } 1741 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) 1742 vector = 0; 1743 1744 for (i = 0; i < adapter->num_rx_queues; i++) { 1745 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) 1746 sprintf(adapter->rx_queue[i].name, "%s-rx-%d", 1747 adapter->netdev->name, vector); 1748 else 1749 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d", 1750 adapter->netdev->name, vector); 1751 err = request_irq(intr->msix_entries[vector].vector, 1752 vmxnet3_msix_rx, 0, 1753 adapter->rx_queue[i].name, 1754 &(adapter->rx_queue[i])); 1755 if (err) { 1756 printk(KERN_ERR "Failed to request irq for MSIX" 1757 ", %s, error %d\n", 1758 adapter->rx_queue[i].name, err); 1759 return err; 1760 } 1761 1762 adapter->rx_queue[i].comp_ring.intr_idx = vector++; 1763 } 1764 1765 sprintf(intr->event_msi_vector_name, "%s-event-%d", 1766 adapter->netdev->name, vector); 1767 err = request_irq(intr->msix_entries[vector].vector, 1768 vmxnet3_msix_event, 0, 1769 intr->event_msi_vector_name, adapter->netdev); 1770 intr->event_intr_idx = vector; 1771 1772 } else if (intr->type == VMXNET3_IT_MSI) { 1773 adapter->num_rx_queues = 1; 1774 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0, 1775 adapter->netdev->name, adapter->netdev); 1776 } else { 1777 #endif 1778 adapter->num_rx_queues = 1; 1779 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 1780 IRQF_SHARED, adapter->netdev->name, 1781 adapter->netdev); 1782 #ifdef CONFIG_PCI_MSI 1783 } 1784 #endif 1785 intr->num_intrs = vector + 1; 1786 if (err) { 1787 printk(KERN_ERR "Failed to request irq %s (intr type:%d), error" 1788 ":%d\n", adapter->netdev->name, intr->type, err); 1789 } else { 1790 /* Number of rx queues will not change after this */ 1791 for (i = 0; i < adapter->num_rx_queues; i++) { 1792 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 1793 rq->qid = i; 1794 rq->qid2 = i + adapter->num_rx_queues; 1795 } 1796 1797 1798 1799 /* init our intr settings */ 1800 for (i = 0; i < intr->num_intrs; i++) 1801 intr->mod_levels[i] = UPT1_IML_ADAPTIVE; 1802 if (adapter->intr.type != VMXNET3_IT_MSIX) { 1803 adapter->intr.event_intr_idx = 0; 1804 for (i = 0; i < adapter->num_tx_queues; i++) 1805 adapter->tx_queue[i].comp_ring.intr_idx = 0; 1806 adapter->rx_queue[0].comp_ring.intr_idx = 0; 1807 } 1808 1809 printk(KERN_INFO "%s: intr type %u, mode %u, %u vectors " 1810 "allocated\n", adapter->netdev->name, intr->type, 1811 intr->mask_mode, intr->num_intrs); 1812 } 1813 1814 return err; 1815 } 1816 1817 1818 static void 1819 vmxnet3_free_irqs(struct vmxnet3_adapter *adapter) 1820 { 1821 struct vmxnet3_intr *intr = &adapter->intr; 1822 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0); 1823 1824 switch (intr->type) { 1825 #ifdef CONFIG_PCI_MSI 1826 case VMXNET3_IT_MSIX: 1827 { 1828 int i, vector = 0; 1829 1830 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) { 1831 for (i = 0; i < adapter->num_tx_queues; i++) { 1832 free_irq(intr->msix_entries[vector++].vector, 1833 &(adapter->tx_queue[i])); 1834 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) 1835 break; 1836 } 1837 } 1838 1839 for (i = 0; i < adapter->num_rx_queues; i++) { 1840 free_irq(intr->msix_entries[vector++].vector, 1841 &(adapter->rx_queue[i])); 1842 } 1843 1844 free_irq(intr->msix_entries[vector].vector, 1845 adapter->netdev); 1846 BUG_ON(vector >= intr->num_intrs); 1847 break; 1848 } 1849 #endif 1850 case VMXNET3_IT_MSI: 1851 free_irq(adapter->pdev->irq, adapter->netdev); 1852 break; 1853 case VMXNET3_IT_INTX: 1854 free_irq(adapter->pdev->irq, adapter->netdev); 1855 break; 1856 default: 1857 BUG_ON(true); 1858 } 1859 } 1860 1861 static void 1862 vmxnet3_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp) 1863 { 1864 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1865 struct Vmxnet3_DriverShared *shared = adapter->shared; 1866 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 1867 unsigned long flags; 1868 1869 if (grp) { 1870 /* add vlan rx stripping. */ 1871 if (adapter->netdev->features & NETIF_F_HW_VLAN_RX) { 1872 int i; 1873 adapter->vlan_grp = grp; 1874 1875 /* 1876 * Clear entire vfTable; then enable untagged pkts. 1877 * Note: setting one entry in vfTable to non-zero turns 1878 * on VLAN rx filtering. 1879 */ 1880 for (i = 0; i < VMXNET3_VFT_SIZE; i++) 1881 vfTable[i] = 0; 1882 1883 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0); 1884 spin_lock_irqsave(&adapter->cmd_lock, flags); 1885 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 1886 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1887 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 1888 } else { 1889 printk(KERN_ERR "%s: vlan_rx_register when device has " 1890 "no NETIF_F_HW_VLAN_RX\n", netdev->name); 1891 } 1892 } else { 1893 /* remove vlan rx stripping. */ 1894 struct Vmxnet3_DSDevRead *devRead = &shared->devRead; 1895 adapter->vlan_grp = NULL; 1896 1897 if (devRead->misc.uptFeatures & UPT1_F_RXVLAN) { 1898 int i; 1899 1900 for (i = 0; i < VMXNET3_VFT_SIZE; i++) { 1901 /* clear entire vfTable; this also disables 1902 * VLAN rx filtering 1903 */ 1904 vfTable[i] = 0; 1905 } 1906 spin_lock_irqsave(&adapter->cmd_lock, flags); 1907 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 1908 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1909 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 1910 } 1911 } 1912 } 1913 1914 1915 static void 1916 vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter) 1917 { 1918 if (adapter->vlan_grp) { 1919 u16 vid; 1920 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 1921 bool activeVlan = false; 1922 1923 for (vid = 0; vid < VLAN_N_VID; vid++) { 1924 if (vlan_group_get_device(adapter->vlan_grp, vid)) { 1925 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid); 1926 activeVlan = true; 1927 } 1928 } 1929 if (activeVlan) { 1930 /* continue to allow untagged pkts */ 1931 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0); 1932 } 1933 } 1934 } 1935 1936 1937 static void 1938 vmxnet3_vlan_rx_add_vid(struct net_device *netdev, u16 vid) 1939 { 1940 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1941 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 1942 unsigned long flags; 1943 1944 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid); 1945 spin_lock_irqsave(&adapter->cmd_lock, flags); 1946 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 1947 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1948 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 1949 } 1950 1951 1952 static void 1953 vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) 1954 { 1955 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1956 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 1957 unsigned long flags; 1958 1959 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid); 1960 spin_lock_irqsave(&adapter->cmd_lock, flags); 1961 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 1962 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 1963 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 1964 } 1965 1966 1967 static u8 * 1968 vmxnet3_copy_mc(struct net_device *netdev) 1969 { 1970 u8 *buf = NULL; 1971 u32 sz = netdev_mc_count(netdev) * ETH_ALEN; 1972 1973 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */ 1974 if (sz <= 0xffff) { 1975 /* We may be called with BH disabled */ 1976 buf = kmalloc(sz, GFP_ATOMIC); 1977 if (buf) { 1978 struct netdev_hw_addr *ha; 1979 int i = 0; 1980 1981 netdev_for_each_mc_addr(ha, netdev) 1982 memcpy(buf + i++ * ETH_ALEN, ha->addr, 1983 ETH_ALEN); 1984 } 1985 } 1986 return buf; 1987 } 1988 1989 1990 static void 1991 vmxnet3_set_mc(struct net_device *netdev) 1992 { 1993 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1994 unsigned long flags; 1995 struct Vmxnet3_RxFilterConf *rxConf = 1996 &adapter->shared->devRead.rxFilterConf; 1997 u8 *new_table = NULL; 1998 u32 new_mode = VMXNET3_RXM_UCAST; 1999 2000 if (netdev->flags & IFF_PROMISC) 2001 new_mode |= VMXNET3_RXM_PROMISC; 2002 2003 if (netdev->flags & IFF_BROADCAST) 2004 new_mode |= VMXNET3_RXM_BCAST; 2005 2006 if (netdev->flags & IFF_ALLMULTI) 2007 new_mode |= VMXNET3_RXM_ALL_MULTI; 2008 else 2009 if (!netdev_mc_empty(netdev)) { 2010 new_table = vmxnet3_copy_mc(netdev); 2011 if (new_table) { 2012 new_mode |= VMXNET3_RXM_MCAST; 2013 rxConf->mfTableLen = cpu_to_le16( 2014 netdev_mc_count(netdev) * ETH_ALEN); 2015 rxConf->mfTablePA = cpu_to_le64(virt_to_phys( 2016 new_table)); 2017 } else { 2018 printk(KERN_INFO "%s: failed to copy mcast list" 2019 ", setting ALL_MULTI\n", netdev->name); 2020 new_mode |= VMXNET3_RXM_ALL_MULTI; 2021 } 2022 } 2023 2024 2025 if (!(new_mode & VMXNET3_RXM_MCAST)) { 2026 rxConf->mfTableLen = 0; 2027 rxConf->mfTablePA = 0; 2028 } 2029 2030 spin_lock_irqsave(&adapter->cmd_lock, flags); 2031 if (new_mode != rxConf->rxMode) { 2032 rxConf->rxMode = cpu_to_le32(new_mode); 2033 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2034 VMXNET3_CMD_UPDATE_RX_MODE); 2035 } 2036 2037 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2038 VMXNET3_CMD_UPDATE_MAC_FILTERS); 2039 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2040 2041 kfree(new_table); 2042 } 2043 2044 void 2045 vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter) 2046 { 2047 int i; 2048 2049 for (i = 0; i < adapter->num_rx_queues; i++) 2050 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter); 2051 } 2052 2053 2054 /* 2055 * Set up driver_shared based on settings in adapter. 2056 */ 2057 2058 static void 2059 vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter) 2060 { 2061 struct Vmxnet3_DriverShared *shared = adapter->shared; 2062 struct Vmxnet3_DSDevRead *devRead = &shared->devRead; 2063 struct Vmxnet3_TxQueueConf *tqc; 2064 struct Vmxnet3_RxQueueConf *rqc; 2065 int i; 2066 2067 memset(shared, 0, sizeof(*shared)); 2068 2069 /* driver settings */ 2070 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC); 2071 devRead->misc.driverInfo.version = cpu_to_le32( 2072 VMXNET3_DRIVER_VERSION_NUM); 2073 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ? 2074 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64); 2075 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 2076 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32( 2077 *((u32 *)&devRead->misc.driverInfo.gos)); 2078 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1); 2079 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1); 2080 2081 devRead->misc.ddPA = cpu_to_le64(virt_to_phys(adapter)); 2082 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter)); 2083 2084 /* set up feature flags */ 2085 if (adapter->netdev->features & NETIF_F_RXCSUM) 2086 devRead->misc.uptFeatures |= UPT1_F_RXCSUM; 2087 2088 if (adapter->netdev->features & NETIF_F_LRO) { 2089 devRead->misc.uptFeatures |= UPT1_F_LRO; 2090 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS); 2091 } 2092 if (adapter->netdev->features & NETIF_F_HW_VLAN_RX) 2093 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 2094 2095 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu); 2096 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa); 2097 devRead->misc.queueDescLen = cpu_to_le32( 2098 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 2099 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc)); 2100 2101 /* tx queue settings */ 2102 devRead->misc.numTxQueues = adapter->num_tx_queues; 2103 for (i = 0; i < adapter->num_tx_queues; i++) { 2104 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i]; 2105 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL); 2106 tqc = &adapter->tqd_start[i].conf; 2107 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA); 2108 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA); 2109 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA); 2110 tqc->ddPA = cpu_to_le64(virt_to_phys(tq->buf_info)); 2111 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size); 2112 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size); 2113 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size); 2114 tqc->ddLen = cpu_to_le32( 2115 sizeof(struct vmxnet3_tx_buf_info) * 2116 tqc->txRingSize); 2117 tqc->intrIdx = tq->comp_ring.intr_idx; 2118 } 2119 2120 /* rx queue settings */ 2121 devRead->misc.numRxQueues = adapter->num_rx_queues; 2122 for (i = 0; i < adapter->num_rx_queues; i++) { 2123 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2124 rqc = &adapter->rqd_start[i].conf; 2125 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA); 2126 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA); 2127 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA); 2128 rqc->ddPA = cpu_to_le64(virt_to_phys( 2129 rq->buf_info)); 2130 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size); 2131 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size); 2132 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size); 2133 rqc->ddLen = cpu_to_le32( 2134 sizeof(struct vmxnet3_rx_buf_info) * 2135 (rqc->rxRingSize[0] + 2136 rqc->rxRingSize[1])); 2137 rqc->intrIdx = rq->comp_ring.intr_idx; 2138 } 2139 2140 #ifdef VMXNET3_RSS 2141 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf)); 2142 2143 if (adapter->rss) { 2144 struct UPT1_RSSConf *rssConf = adapter->rss_conf; 2145 devRead->misc.uptFeatures |= UPT1_F_RSS; 2146 devRead->misc.numRxQueues = adapter->num_rx_queues; 2147 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 | 2148 UPT1_RSS_HASH_TYPE_IPV4 | 2149 UPT1_RSS_HASH_TYPE_TCP_IPV6 | 2150 UPT1_RSS_HASH_TYPE_IPV6; 2151 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ; 2152 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE; 2153 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE; 2154 get_random_bytes(&rssConf->hashKey[0], rssConf->hashKeySize); 2155 for (i = 0; i < rssConf->indTableSize; i++) 2156 rssConf->indTable[i] = i % adapter->num_rx_queues; 2157 2158 devRead->rssConfDesc.confVer = 1; 2159 devRead->rssConfDesc.confLen = sizeof(*rssConf); 2160 devRead->rssConfDesc.confPA = virt_to_phys(rssConf); 2161 } 2162 2163 #endif /* VMXNET3_RSS */ 2164 2165 /* intr settings */ 2166 devRead->intrConf.autoMask = adapter->intr.mask_mode == 2167 VMXNET3_IMM_AUTO; 2168 devRead->intrConf.numIntrs = adapter->intr.num_intrs; 2169 for (i = 0; i < adapter->intr.num_intrs; i++) 2170 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i]; 2171 2172 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx; 2173 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL); 2174 2175 /* rx filter settings */ 2176 devRead->rxFilterConf.rxMode = 0; 2177 vmxnet3_restore_vlan(adapter); 2178 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr); 2179 2180 /* the rest are already zeroed */ 2181 } 2182 2183 2184 int 2185 vmxnet3_activate_dev(struct vmxnet3_adapter *adapter) 2186 { 2187 int err, i; 2188 u32 ret; 2189 unsigned long flags; 2190 2191 dev_dbg(&adapter->netdev->dev, "%s: skb_buf_size %d, rx_buf_per_pkt %d," 2192 " ring sizes %u %u %u\n", adapter->netdev->name, 2193 adapter->skb_buf_size, adapter->rx_buf_per_pkt, 2194 adapter->tx_queue[0].tx_ring.size, 2195 adapter->rx_queue[0].rx_ring[0].size, 2196 adapter->rx_queue[0].rx_ring[1].size); 2197 2198 vmxnet3_tq_init_all(adapter); 2199 err = vmxnet3_rq_init_all(adapter); 2200 if (err) { 2201 printk(KERN_ERR "Failed to init rx queue for %s: error %d\n", 2202 adapter->netdev->name, err); 2203 goto rq_err; 2204 } 2205 2206 err = vmxnet3_request_irqs(adapter); 2207 if (err) { 2208 printk(KERN_ERR "Failed to setup irq for %s: error %d\n", 2209 adapter->netdev->name, err); 2210 goto irq_err; 2211 } 2212 2213 vmxnet3_setup_driver_shared(adapter); 2214 2215 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO( 2216 adapter->shared_pa)); 2217 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI( 2218 adapter->shared_pa)); 2219 spin_lock_irqsave(&adapter->cmd_lock, flags); 2220 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2221 VMXNET3_CMD_ACTIVATE_DEV); 2222 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 2223 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2224 2225 if (ret != 0) { 2226 printk(KERN_ERR "Failed to activate dev %s: error %u\n", 2227 adapter->netdev->name, ret); 2228 err = -EINVAL; 2229 goto activate_err; 2230 } 2231 2232 for (i = 0; i < adapter->num_rx_queues; i++) { 2233 VMXNET3_WRITE_BAR0_REG(adapter, 2234 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN, 2235 adapter->rx_queue[i].rx_ring[0].next2fill); 2236 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 + 2237 (i * VMXNET3_REG_ALIGN)), 2238 adapter->rx_queue[i].rx_ring[1].next2fill); 2239 } 2240 2241 /* Apply the rx filter settins last. */ 2242 vmxnet3_set_mc(adapter->netdev); 2243 2244 /* 2245 * Check link state when first activating device. It will start the 2246 * tx queue if the link is up. 2247 */ 2248 vmxnet3_check_link(adapter, true); 2249 for (i = 0; i < adapter->num_rx_queues; i++) 2250 napi_enable(&adapter->rx_queue[i].napi); 2251 vmxnet3_enable_all_intrs(adapter); 2252 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 2253 return 0; 2254 2255 activate_err: 2256 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0); 2257 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0); 2258 vmxnet3_free_irqs(adapter); 2259 irq_err: 2260 rq_err: 2261 /* free up buffers we allocated */ 2262 vmxnet3_rq_cleanup_all(adapter); 2263 return err; 2264 } 2265 2266 2267 void 2268 vmxnet3_reset_dev(struct vmxnet3_adapter *adapter) 2269 { 2270 unsigned long flags; 2271 spin_lock_irqsave(&adapter->cmd_lock, flags); 2272 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 2273 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2274 } 2275 2276 2277 int 2278 vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter) 2279 { 2280 int i; 2281 unsigned long flags; 2282 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state)) 2283 return 0; 2284 2285 2286 spin_lock_irqsave(&adapter->cmd_lock, flags); 2287 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2288 VMXNET3_CMD_QUIESCE_DEV); 2289 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2290 vmxnet3_disable_all_intrs(adapter); 2291 2292 for (i = 0; i < adapter->num_rx_queues; i++) 2293 napi_disable(&adapter->rx_queue[i].napi); 2294 netif_tx_disable(adapter->netdev); 2295 adapter->link_speed = 0; 2296 netif_carrier_off(adapter->netdev); 2297 2298 vmxnet3_tq_cleanup_all(adapter); 2299 vmxnet3_rq_cleanup_all(adapter); 2300 vmxnet3_free_irqs(adapter); 2301 return 0; 2302 } 2303 2304 2305 static void 2306 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac) 2307 { 2308 u32 tmp; 2309 2310 tmp = *(u32 *)mac; 2311 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp); 2312 2313 tmp = (mac[5] << 8) | mac[4]; 2314 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp); 2315 } 2316 2317 2318 static int 2319 vmxnet3_set_mac_addr(struct net_device *netdev, void *p) 2320 { 2321 struct sockaddr *addr = p; 2322 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2323 2324 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 2325 vmxnet3_write_mac_addr(adapter, addr->sa_data); 2326 2327 return 0; 2328 } 2329 2330 2331 /* ==================== initialization and cleanup routines ============ */ 2332 2333 static int 2334 vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64) 2335 { 2336 int err; 2337 unsigned long mmio_start, mmio_len; 2338 struct pci_dev *pdev = adapter->pdev; 2339 2340 err = pci_enable_device(pdev); 2341 if (err) { 2342 printk(KERN_ERR "Failed to enable adapter %s: error %d\n", 2343 pci_name(pdev), err); 2344 return err; 2345 } 2346 2347 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) { 2348 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) { 2349 printk(KERN_ERR "pci_set_consistent_dma_mask failed " 2350 "for adapter %s\n", pci_name(pdev)); 2351 err = -EIO; 2352 goto err_set_mask; 2353 } 2354 *dma64 = true; 2355 } else { 2356 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) { 2357 printk(KERN_ERR "pci_set_dma_mask failed for adapter " 2358 "%s\n", pci_name(pdev)); 2359 err = -EIO; 2360 goto err_set_mask; 2361 } 2362 *dma64 = false; 2363 } 2364 2365 err = pci_request_selected_regions(pdev, (1 << 2) - 1, 2366 vmxnet3_driver_name); 2367 if (err) { 2368 printk(KERN_ERR "Failed to request region for adapter %s: " 2369 "error %d\n", pci_name(pdev), err); 2370 goto err_set_mask; 2371 } 2372 2373 pci_set_master(pdev); 2374 2375 mmio_start = pci_resource_start(pdev, 0); 2376 mmio_len = pci_resource_len(pdev, 0); 2377 adapter->hw_addr0 = ioremap(mmio_start, mmio_len); 2378 if (!adapter->hw_addr0) { 2379 printk(KERN_ERR "Failed to map bar0 for adapter %s\n", 2380 pci_name(pdev)); 2381 err = -EIO; 2382 goto err_ioremap; 2383 } 2384 2385 mmio_start = pci_resource_start(pdev, 1); 2386 mmio_len = pci_resource_len(pdev, 1); 2387 adapter->hw_addr1 = ioremap(mmio_start, mmio_len); 2388 if (!adapter->hw_addr1) { 2389 printk(KERN_ERR "Failed to map bar1 for adapter %s\n", 2390 pci_name(pdev)); 2391 err = -EIO; 2392 goto err_bar1; 2393 } 2394 return 0; 2395 2396 err_bar1: 2397 iounmap(adapter->hw_addr0); 2398 err_ioremap: 2399 pci_release_selected_regions(pdev, (1 << 2) - 1); 2400 err_set_mask: 2401 pci_disable_device(pdev); 2402 return err; 2403 } 2404 2405 2406 static void 2407 vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter) 2408 { 2409 BUG_ON(!adapter->pdev); 2410 2411 iounmap(adapter->hw_addr0); 2412 iounmap(adapter->hw_addr1); 2413 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1); 2414 pci_disable_device(adapter->pdev); 2415 } 2416 2417 2418 static void 2419 vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter) 2420 { 2421 size_t sz, i, ring0_size, ring1_size, comp_size; 2422 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[0]; 2423 2424 2425 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE - 2426 VMXNET3_MAX_ETH_HDR_SIZE) { 2427 adapter->skb_buf_size = adapter->netdev->mtu + 2428 VMXNET3_MAX_ETH_HDR_SIZE; 2429 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE) 2430 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE; 2431 2432 adapter->rx_buf_per_pkt = 1; 2433 } else { 2434 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE; 2435 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE + 2436 VMXNET3_MAX_ETH_HDR_SIZE; 2437 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE; 2438 } 2439 2440 /* 2441 * for simplicity, force the ring0 size to be a multiple of 2442 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN 2443 */ 2444 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN; 2445 ring0_size = adapter->rx_queue[0].rx_ring[0].size; 2446 ring0_size = (ring0_size + sz - 1) / sz * sz; 2447 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE / 2448 sz * sz); 2449 ring1_size = adapter->rx_queue[0].rx_ring[1].size; 2450 comp_size = ring0_size + ring1_size; 2451 2452 for (i = 0; i < adapter->num_rx_queues; i++) { 2453 rq = &adapter->rx_queue[i]; 2454 rq->rx_ring[0].size = ring0_size; 2455 rq->rx_ring[1].size = ring1_size; 2456 rq->comp_ring.size = comp_size; 2457 } 2458 } 2459 2460 2461 int 2462 vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size, 2463 u32 rx_ring_size, u32 rx_ring2_size) 2464 { 2465 int err = 0, i; 2466 2467 for (i = 0; i < adapter->num_tx_queues; i++) { 2468 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i]; 2469 tq->tx_ring.size = tx_ring_size; 2470 tq->data_ring.size = tx_ring_size; 2471 tq->comp_ring.size = tx_ring_size; 2472 tq->shared = &adapter->tqd_start[i].ctrl; 2473 tq->stopped = true; 2474 tq->adapter = adapter; 2475 tq->qid = i; 2476 err = vmxnet3_tq_create(tq, adapter); 2477 /* 2478 * Too late to change num_tx_queues. We cannot do away with 2479 * lesser number of queues than what we asked for 2480 */ 2481 if (err) 2482 goto queue_err; 2483 } 2484 2485 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size; 2486 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size; 2487 vmxnet3_adjust_rx_ring_size(adapter); 2488 for (i = 0; i < adapter->num_rx_queues; i++) { 2489 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2490 /* qid and qid2 for rx queues will be assigned later when num 2491 * of rx queues is finalized after allocating intrs */ 2492 rq->shared = &adapter->rqd_start[i].ctrl; 2493 rq->adapter = adapter; 2494 err = vmxnet3_rq_create(rq, adapter); 2495 if (err) { 2496 if (i == 0) { 2497 printk(KERN_ERR "Could not allocate any rx" 2498 "queues. Aborting.\n"); 2499 goto queue_err; 2500 } else { 2501 printk(KERN_INFO "Number of rx queues changed " 2502 "to : %d.\n", i); 2503 adapter->num_rx_queues = i; 2504 err = 0; 2505 break; 2506 } 2507 } 2508 } 2509 return err; 2510 queue_err: 2511 vmxnet3_tq_destroy_all(adapter); 2512 return err; 2513 } 2514 2515 static int 2516 vmxnet3_open(struct net_device *netdev) 2517 { 2518 struct vmxnet3_adapter *adapter; 2519 int err, i; 2520 2521 adapter = netdev_priv(netdev); 2522 2523 for (i = 0; i < adapter->num_tx_queues; i++) 2524 spin_lock_init(&adapter->tx_queue[i].tx_lock); 2525 2526 err = vmxnet3_create_queues(adapter, VMXNET3_DEF_TX_RING_SIZE, 2527 VMXNET3_DEF_RX_RING_SIZE, 2528 VMXNET3_DEF_RX_RING_SIZE); 2529 if (err) 2530 goto queue_err; 2531 2532 err = vmxnet3_activate_dev(adapter); 2533 if (err) 2534 goto activate_err; 2535 2536 return 0; 2537 2538 activate_err: 2539 vmxnet3_rq_destroy_all(adapter); 2540 vmxnet3_tq_destroy_all(adapter); 2541 queue_err: 2542 return err; 2543 } 2544 2545 2546 static int 2547 vmxnet3_close(struct net_device *netdev) 2548 { 2549 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2550 2551 /* 2552 * Reset_work may be in the middle of resetting the device, wait for its 2553 * completion. 2554 */ 2555 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 2556 msleep(1); 2557 2558 vmxnet3_quiesce_dev(adapter); 2559 2560 vmxnet3_rq_destroy_all(adapter); 2561 vmxnet3_tq_destroy_all(adapter); 2562 2563 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 2564 2565 2566 return 0; 2567 } 2568 2569 2570 void 2571 vmxnet3_force_close(struct vmxnet3_adapter *adapter) 2572 { 2573 int i; 2574 2575 /* 2576 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise 2577 * vmxnet3_close() will deadlock. 2578 */ 2579 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)); 2580 2581 /* we need to enable NAPI, otherwise dev_close will deadlock */ 2582 for (i = 0; i < adapter->num_rx_queues; i++) 2583 napi_enable(&adapter->rx_queue[i].napi); 2584 dev_close(adapter->netdev); 2585 } 2586 2587 2588 static int 2589 vmxnet3_change_mtu(struct net_device *netdev, int new_mtu) 2590 { 2591 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2592 int err = 0; 2593 2594 if (new_mtu < VMXNET3_MIN_MTU || new_mtu > VMXNET3_MAX_MTU) 2595 return -EINVAL; 2596 2597 netdev->mtu = new_mtu; 2598 2599 /* 2600 * Reset_work may be in the middle of resetting the device, wait for its 2601 * completion. 2602 */ 2603 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 2604 msleep(1); 2605 2606 if (netif_running(netdev)) { 2607 vmxnet3_quiesce_dev(adapter); 2608 vmxnet3_reset_dev(adapter); 2609 2610 /* we need to re-create the rx queue based on the new mtu */ 2611 vmxnet3_rq_destroy_all(adapter); 2612 vmxnet3_adjust_rx_ring_size(adapter); 2613 err = vmxnet3_rq_create_all(adapter); 2614 if (err) { 2615 printk(KERN_ERR "%s: failed to re-create rx queues," 2616 " error %d. Closing it.\n", netdev->name, err); 2617 goto out; 2618 } 2619 2620 err = vmxnet3_activate_dev(adapter); 2621 if (err) { 2622 printk(KERN_ERR "%s: failed to re-activate, error %d. " 2623 "Closing it\n", netdev->name, err); 2624 goto out; 2625 } 2626 } 2627 2628 out: 2629 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 2630 if (err) 2631 vmxnet3_force_close(adapter); 2632 2633 return err; 2634 } 2635 2636 2637 static void 2638 vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64) 2639 { 2640 struct net_device *netdev = adapter->netdev; 2641 2642 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM | 2643 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_TX | 2644 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_LRO; 2645 if (dma64) 2646 netdev->features |= NETIF_F_HIGHDMA; 2647 netdev->vlan_features = netdev->hw_features & ~NETIF_F_HW_VLAN_TX; 2648 netdev->features = netdev->hw_features | 2649 NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER; 2650 2651 netdev_info(adapter->netdev, 2652 "features: sg csum vlan jf tso tsoIPv6 lro%s\n", 2653 dma64 ? " highDMA" : ""); 2654 } 2655 2656 2657 static void 2658 vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac) 2659 { 2660 u32 tmp; 2661 2662 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL); 2663 *(u32 *)mac = tmp; 2664 2665 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH); 2666 mac[4] = tmp & 0xff; 2667 mac[5] = (tmp >> 8) & 0xff; 2668 } 2669 2670 #ifdef CONFIG_PCI_MSI 2671 2672 /* 2673 * Enable MSIx vectors. 2674 * Returns : 2675 * 0 on successful enabling of required vectors, 2676 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required 2677 * could be enabled. 2678 * number of vectors which can be enabled otherwise (this number is smaller 2679 * than VMXNET3_LINUX_MIN_MSIX_VECT) 2680 */ 2681 2682 static int 2683 vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, 2684 int vectors) 2685 { 2686 int err = 0, vector_threshold; 2687 vector_threshold = VMXNET3_LINUX_MIN_MSIX_VECT; 2688 2689 while (vectors >= vector_threshold) { 2690 err = pci_enable_msix(adapter->pdev, adapter->intr.msix_entries, 2691 vectors); 2692 if (!err) { 2693 adapter->intr.num_intrs = vectors; 2694 return 0; 2695 } else if (err < 0) { 2696 printk(KERN_ERR "Failed to enable MSI-X for %s, error" 2697 " %d\n", adapter->netdev->name, err); 2698 vectors = 0; 2699 } else if (err < vector_threshold) { 2700 break; 2701 } else { 2702 /* If fails to enable required number of MSI-x vectors 2703 * try enabling minimum number of vectors required. 2704 */ 2705 vectors = vector_threshold; 2706 printk(KERN_ERR "Failed to enable %d MSI-X for %s, try" 2707 " %d instead\n", vectors, adapter->netdev->name, 2708 vector_threshold); 2709 } 2710 } 2711 2712 printk(KERN_INFO "Number of MSI-X interrupts which can be allocatedi" 2713 " are lower than min threshold required.\n"); 2714 return err; 2715 } 2716 2717 2718 #endif /* CONFIG_PCI_MSI */ 2719 2720 static void 2721 vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter) 2722 { 2723 u32 cfg; 2724 unsigned long flags; 2725 2726 /* intr settings */ 2727 spin_lock_irqsave(&adapter->cmd_lock, flags); 2728 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2729 VMXNET3_CMD_GET_CONF_INTR); 2730 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 2731 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2732 adapter->intr.type = cfg & 0x3; 2733 adapter->intr.mask_mode = (cfg >> 2) & 0x3; 2734 2735 if (adapter->intr.type == VMXNET3_IT_AUTO) { 2736 adapter->intr.type = VMXNET3_IT_MSIX; 2737 } 2738 2739 #ifdef CONFIG_PCI_MSI 2740 if (adapter->intr.type == VMXNET3_IT_MSIX) { 2741 int vector, err = 0; 2742 2743 adapter->intr.num_intrs = (adapter->share_intr == 2744 VMXNET3_INTR_TXSHARE) ? 1 : 2745 adapter->num_tx_queues; 2746 adapter->intr.num_intrs += (adapter->share_intr == 2747 VMXNET3_INTR_BUDDYSHARE) ? 0 : 2748 adapter->num_rx_queues; 2749 adapter->intr.num_intrs += 1; /* for link event */ 2750 2751 adapter->intr.num_intrs = (adapter->intr.num_intrs > 2752 VMXNET3_LINUX_MIN_MSIX_VECT 2753 ? adapter->intr.num_intrs : 2754 VMXNET3_LINUX_MIN_MSIX_VECT); 2755 2756 for (vector = 0; vector < adapter->intr.num_intrs; vector++) 2757 adapter->intr.msix_entries[vector].entry = vector; 2758 2759 err = vmxnet3_acquire_msix_vectors(adapter, 2760 adapter->intr.num_intrs); 2761 /* If we cannot allocate one MSIx vector per queue 2762 * then limit the number of rx queues to 1 2763 */ 2764 if (err == VMXNET3_LINUX_MIN_MSIX_VECT) { 2765 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE 2766 || adapter->num_rx_queues != 1) { 2767 adapter->share_intr = VMXNET3_INTR_TXSHARE; 2768 printk(KERN_ERR "Number of rx queues : 1\n"); 2769 adapter->num_rx_queues = 1; 2770 adapter->intr.num_intrs = 2771 VMXNET3_LINUX_MIN_MSIX_VECT; 2772 } 2773 return; 2774 } 2775 if (!err) 2776 return; 2777 2778 /* If we cannot allocate MSIx vectors use only one rx queue */ 2779 printk(KERN_INFO "Failed to enable MSI-X for %s, error %d." 2780 "#rx queues : 1, try MSI\n", adapter->netdev->name, err); 2781 2782 adapter->intr.type = VMXNET3_IT_MSI; 2783 } 2784 2785 if (adapter->intr.type == VMXNET3_IT_MSI) { 2786 int err; 2787 err = pci_enable_msi(adapter->pdev); 2788 if (!err) { 2789 adapter->num_rx_queues = 1; 2790 adapter->intr.num_intrs = 1; 2791 return; 2792 } 2793 } 2794 #endif /* CONFIG_PCI_MSI */ 2795 2796 adapter->num_rx_queues = 1; 2797 printk(KERN_INFO "Using INTx interrupt, #Rx queues: 1.\n"); 2798 adapter->intr.type = VMXNET3_IT_INTX; 2799 2800 /* INT-X related setting */ 2801 adapter->intr.num_intrs = 1; 2802 } 2803 2804 2805 static void 2806 vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter) 2807 { 2808 if (adapter->intr.type == VMXNET3_IT_MSIX) 2809 pci_disable_msix(adapter->pdev); 2810 else if (adapter->intr.type == VMXNET3_IT_MSI) 2811 pci_disable_msi(adapter->pdev); 2812 else 2813 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX); 2814 } 2815 2816 2817 static void 2818 vmxnet3_tx_timeout(struct net_device *netdev) 2819 { 2820 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2821 adapter->tx_timeout_count++; 2822 2823 printk(KERN_ERR "%s: tx hang\n", adapter->netdev->name); 2824 schedule_work(&adapter->work); 2825 netif_wake_queue(adapter->netdev); 2826 } 2827 2828 2829 static void 2830 vmxnet3_reset_work(struct work_struct *data) 2831 { 2832 struct vmxnet3_adapter *adapter; 2833 2834 adapter = container_of(data, struct vmxnet3_adapter, work); 2835 2836 /* if another thread is resetting the device, no need to proceed */ 2837 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 2838 return; 2839 2840 /* if the device is closed, we must leave it alone */ 2841 rtnl_lock(); 2842 if (netif_running(adapter->netdev)) { 2843 printk(KERN_INFO "%s: resetting\n", adapter->netdev->name); 2844 vmxnet3_quiesce_dev(adapter); 2845 vmxnet3_reset_dev(adapter); 2846 vmxnet3_activate_dev(adapter); 2847 } else { 2848 printk(KERN_INFO "%s: already closed\n", adapter->netdev->name); 2849 } 2850 rtnl_unlock(); 2851 2852 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 2853 } 2854 2855 2856 static int __devinit 2857 vmxnet3_probe_device(struct pci_dev *pdev, 2858 const struct pci_device_id *id) 2859 { 2860 static const struct net_device_ops vmxnet3_netdev_ops = { 2861 .ndo_open = vmxnet3_open, 2862 .ndo_stop = vmxnet3_close, 2863 .ndo_start_xmit = vmxnet3_xmit_frame, 2864 .ndo_set_mac_address = vmxnet3_set_mac_addr, 2865 .ndo_change_mtu = vmxnet3_change_mtu, 2866 .ndo_set_features = vmxnet3_set_features, 2867 .ndo_get_stats64 = vmxnet3_get_stats64, 2868 .ndo_tx_timeout = vmxnet3_tx_timeout, 2869 .ndo_set_multicast_list = vmxnet3_set_mc, 2870 .ndo_vlan_rx_register = vmxnet3_vlan_rx_register, 2871 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid, 2872 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid, 2873 #ifdef CONFIG_NET_POLL_CONTROLLER 2874 .ndo_poll_controller = vmxnet3_netpoll, 2875 #endif 2876 }; 2877 int err; 2878 bool dma64 = false; /* stupid gcc */ 2879 u32 ver; 2880 struct net_device *netdev; 2881 struct vmxnet3_adapter *adapter; 2882 u8 mac[ETH_ALEN]; 2883 int size; 2884 int num_tx_queues; 2885 int num_rx_queues; 2886 2887 if (!pci_msi_enabled()) 2888 enable_mq = 0; 2889 2890 #ifdef VMXNET3_RSS 2891 if (enable_mq) 2892 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES, 2893 (int)num_online_cpus()); 2894 else 2895 #endif 2896 num_rx_queues = 1; 2897 2898 if (enable_mq) 2899 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES, 2900 (int)num_online_cpus()); 2901 else 2902 num_tx_queues = 1; 2903 2904 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter), 2905 max(num_tx_queues, num_rx_queues)); 2906 printk(KERN_INFO "# of Tx queues : %d, # of Rx queues : %d\n", 2907 num_tx_queues, num_rx_queues); 2908 2909 if (!netdev) { 2910 printk(KERN_ERR "Failed to alloc ethernet device for adapter " 2911 "%s\n", pci_name(pdev)); 2912 return -ENOMEM; 2913 } 2914 2915 pci_set_drvdata(pdev, netdev); 2916 adapter = netdev_priv(netdev); 2917 adapter->netdev = netdev; 2918 adapter->pdev = pdev; 2919 2920 spin_lock_init(&adapter->cmd_lock); 2921 adapter->shared = pci_alloc_consistent(adapter->pdev, 2922 sizeof(struct Vmxnet3_DriverShared), 2923 &adapter->shared_pa); 2924 if (!adapter->shared) { 2925 printk(KERN_ERR "Failed to allocate memory for %s\n", 2926 pci_name(pdev)); 2927 err = -ENOMEM; 2928 goto err_alloc_shared; 2929 } 2930 2931 adapter->num_rx_queues = num_rx_queues; 2932 adapter->num_tx_queues = num_tx_queues; 2933 2934 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues; 2935 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues; 2936 adapter->tqd_start = pci_alloc_consistent(adapter->pdev, size, 2937 &adapter->queue_desc_pa); 2938 2939 if (!adapter->tqd_start) { 2940 printk(KERN_ERR "Failed to allocate memory for %s\n", 2941 pci_name(pdev)); 2942 err = -ENOMEM; 2943 goto err_alloc_queue_desc; 2944 } 2945 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start + 2946 adapter->num_tx_queues); 2947 2948 adapter->pm_conf = kmalloc(sizeof(struct Vmxnet3_PMConf), GFP_KERNEL); 2949 if (adapter->pm_conf == NULL) { 2950 printk(KERN_ERR "Failed to allocate memory for %s\n", 2951 pci_name(pdev)); 2952 err = -ENOMEM; 2953 goto err_alloc_pm; 2954 } 2955 2956 #ifdef VMXNET3_RSS 2957 2958 adapter->rss_conf = kmalloc(sizeof(struct UPT1_RSSConf), GFP_KERNEL); 2959 if (adapter->rss_conf == NULL) { 2960 printk(KERN_ERR "Failed to allocate memory for %s\n", 2961 pci_name(pdev)); 2962 err = -ENOMEM; 2963 goto err_alloc_rss; 2964 } 2965 #endif /* VMXNET3_RSS */ 2966 2967 err = vmxnet3_alloc_pci_resources(adapter, &dma64); 2968 if (err < 0) 2969 goto err_alloc_pci; 2970 2971 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS); 2972 if (ver & 1) { 2973 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_VRRS, 1); 2974 } else { 2975 printk(KERN_ERR "Incompatible h/w version (0x%x) for adapter" 2976 " %s\n", ver, pci_name(pdev)); 2977 err = -EBUSY; 2978 goto err_ver; 2979 } 2980 2981 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS); 2982 if (ver & 1) { 2983 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1); 2984 } else { 2985 printk(KERN_ERR "Incompatible upt version (0x%x) for " 2986 "adapter %s\n", ver, pci_name(pdev)); 2987 err = -EBUSY; 2988 goto err_ver; 2989 } 2990 2991 vmxnet3_declare_features(adapter, dma64); 2992 2993 adapter->dev_number = atomic_read(&devices_found); 2994 2995 adapter->share_intr = irq_share_mode; 2996 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE && 2997 adapter->num_tx_queues != adapter->num_rx_queues) 2998 adapter->share_intr = VMXNET3_INTR_DONTSHARE; 2999 3000 vmxnet3_alloc_intr_resources(adapter); 3001 3002 #ifdef VMXNET3_RSS 3003 if (adapter->num_rx_queues > 1 && 3004 adapter->intr.type == VMXNET3_IT_MSIX) { 3005 adapter->rss = true; 3006 printk(KERN_INFO "RSS is enabled.\n"); 3007 } else { 3008 adapter->rss = false; 3009 } 3010 #endif 3011 3012 vmxnet3_read_mac_addr(adapter, mac); 3013 memcpy(netdev->dev_addr, mac, netdev->addr_len); 3014 3015 netdev->netdev_ops = &vmxnet3_netdev_ops; 3016 vmxnet3_set_ethtool_ops(netdev); 3017 netdev->watchdog_timeo = 5 * HZ; 3018 3019 INIT_WORK(&adapter->work, vmxnet3_reset_work); 3020 3021 if (adapter->intr.type == VMXNET3_IT_MSIX) { 3022 int i; 3023 for (i = 0; i < adapter->num_rx_queues; i++) { 3024 netif_napi_add(adapter->netdev, 3025 &adapter->rx_queue[i].napi, 3026 vmxnet3_poll_rx_only, 64); 3027 } 3028 } else { 3029 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi, 3030 vmxnet3_poll, 64); 3031 } 3032 3033 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); 3034 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues); 3035 3036 SET_NETDEV_DEV(netdev, &pdev->dev); 3037 err = register_netdev(netdev); 3038 3039 if (err) { 3040 printk(KERN_ERR "Failed to register adapter %s\n", 3041 pci_name(pdev)); 3042 goto err_register; 3043 } 3044 3045 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 3046 vmxnet3_check_link(adapter, false); 3047 atomic_inc(&devices_found); 3048 return 0; 3049 3050 err_register: 3051 vmxnet3_free_intr_resources(adapter); 3052 err_ver: 3053 vmxnet3_free_pci_resources(adapter); 3054 err_alloc_pci: 3055 #ifdef VMXNET3_RSS 3056 kfree(adapter->rss_conf); 3057 err_alloc_rss: 3058 #endif 3059 kfree(adapter->pm_conf); 3060 err_alloc_pm: 3061 pci_free_consistent(adapter->pdev, size, adapter->tqd_start, 3062 adapter->queue_desc_pa); 3063 err_alloc_queue_desc: 3064 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared), 3065 adapter->shared, adapter->shared_pa); 3066 err_alloc_shared: 3067 pci_set_drvdata(pdev, NULL); 3068 free_netdev(netdev); 3069 return err; 3070 } 3071 3072 3073 static void __devexit 3074 vmxnet3_remove_device(struct pci_dev *pdev) 3075 { 3076 struct net_device *netdev = pci_get_drvdata(pdev); 3077 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3078 int size = 0; 3079 int num_rx_queues; 3080 3081 #ifdef VMXNET3_RSS 3082 if (enable_mq) 3083 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES, 3084 (int)num_online_cpus()); 3085 else 3086 #endif 3087 num_rx_queues = 1; 3088 3089 cancel_work_sync(&adapter->work); 3090 3091 unregister_netdev(netdev); 3092 3093 vmxnet3_free_intr_resources(adapter); 3094 vmxnet3_free_pci_resources(adapter); 3095 #ifdef VMXNET3_RSS 3096 kfree(adapter->rss_conf); 3097 #endif 3098 kfree(adapter->pm_conf); 3099 3100 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues; 3101 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues; 3102 pci_free_consistent(adapter->pdev, size, adapter->tqd_start, 3103 adapter->queue_desc_pa); 3104 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared), 3105 adapter->shared, adapter->shared_pa); 3106 free_netdev(netdev); 3107 } 3108 3109 3110 #ifdef CONFIG_PM 3111 3112 static int 3113 vmxnet3_suspend(struct device *device) 3114 { 3115 struct pci_dev *pdev = to_pci_dev(device); 3116 struct net_device *netdev = pci_get_drvdata(pdev); 3117 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3118 struct Vmxnet3_PMConf *pmConf; 3119 struct ethhdr *ehdr; 3120 struct arphdr *ahdr; 3121 u8 *arpreq; 3122 struct in_device *in_dev; 3123 struct in_ifaddr *ifa; 3124 unsigned long flags; 3125 int i = 0; 3126 3127 if (!netif_running(netdev)) 3128 return 0; 3129 3130 for (i = 0; i < adapter->num_rx_queues; i++) 3131 napi_disable(&adapter->rx_queue[i].napi); 3132 3133 vmxnet3_disable_all_intrs(adapter); 3134 vmxnet3_free_irqs(adapter); 3135 vmxnet3_free_intr_resources(adapter); 3136 3137 netif_device_detach(netdev); 3138 netif_tx_stop_all_queues(netdev); 3139 3140 /* Create wake-up filters. */ 3141 pmConf = adapter->pm_conf; 3142 memset(pmConf, 0, sizeof(*pmConf)); 3143 3144 if (adapter->wol & WAKE_UCAST) { 3145 pmConf->filters[i].patternSize = ETH_ALEN; 3146 pmConf->filters[i].maskSize = 1; 3147 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN); 3148 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */ 3149 3150 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER; 3151 i++; 3152 } 3153 3154 if (adapter->wol & WAKE_ARP) { 3155 in_dev = in_dev_get(netdev); 3156 if (!in_dev) 3157 goto skip_arp; 3158 3159 ifa = (struct in_ifaddr *)in_dev->ifa_list; 3160 if (!ifa) 3161 goto skip_arp; 3162 3163 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/ 3164 sizeof(struct arphdr) + /* ARP header */ 3165 2 * ETH_ALEN + /* 2 Ethernet addresses*/ 3166 2 * sizeof(u32); /*2 IPv4 addresses */ 3167 pmConf->filters[i].maskSize = 3168 (pmConf->filters[i].patternSize - 1) / 8 + 1; 3169 3170 /* ETH_P_ARP in Ethernet header. */ 3171 ehdr = (struct ethhdr *)pmConf->filters[i].pattern; 3172 ehdr->h_proto = htons(ETH_P_ARP); 3173 3174 /* ARPOP_REQUEST in ARP header. */ 3175 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN]; 3176 ahdr->ar_op = htons(ARPOP_REQUEST); 3177 arpreq = (u8 *)(ahdr + 1); 3178 3179 /* The Unicast IPv4 address in 'tip' field. */ 3180 arpreq += 2 * ETH_ALEN + sizeof(u32); 3181 *(u32 *)arpreq = ifa->ifa_address; 3182 3183 /* The mask for the relevant bits. */ 3184 pmConf->filters[i].mask[0] = 0x00; 3185 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */ 3186 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */ 3187 pmConf->filters[i].mask[3] = 0x00; 3188 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */ 3189 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */ 3190 in_dev_put(in_dev); 3191 3192 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER; 3193 i++; 3194 } 3195 3196 skip_arp: 3197 if (adapter->wol & WAKE_MAGIC) 3198 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC; 3199 3200 pmConf->numFilters = i; 3201 3202 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1); 3203 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof( 3204 *pmConf)); 3205 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys( 3206 pmConf)); 3207 3208 spin_lock_irqsave(&adapter->cmd_lock, flags); 3209 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3210 VMXNET3_CMD_UPDATE_PMCFG); 3211 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3212 3213 pci_save_state(pdev); 3214 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND), 3215 adapter->wol); 3216 pci_disable_device(pdev); 3217 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND)); 3218 3219 return 0; 3220 } 3221 3222 3223 static int 3224 vmxnet3_resume(struct device *device) 3225 { 3226 int err, i = 0; 3227 unsigned long flags; 3228 struct pci_dev *pdev = to_pci_dev(device); 3229 struct net_device *netdev = pci_get_drvdata(pdev); 3230 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3231 struct Vmxnet3_PMConf *pmConf; 3232 3233 if (!netif_running(netdev)) 3234 return 0; 3235 3236 /* Destroy wake-up filters. */ 3237 pmConf = adapter->pm_conf; 3238 memset(pmConf, 0, sizeof(*pmConf)); 3239 3240 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1); 3241 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof( 3242 *pmConf)); 3243 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys( 3244 pmConf)); 3245 3246 netif_device_attach(netdev); 3247 pci_set_power_state(pdev, PCI_D0); 3248 pci_restore_state(pdev); 3249 err = pci_enable_device_mem(pdev); 3250 if (err != 0) 3251 return err; 3252 3253 pci_enable_wake(pdev, PCI_D0, 0); 3254 3255 spin_lock_irqsave(&adapter->cmd_lock, flags); 3256 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3257 VMXNET3_CMD_UPDATE_PMCFG); 3258 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3259 vmxnet3_alloc_intr_resources(adapter); 3260 vmxnet3_request_irqs(adapter); 3261 for (i = 0; i < adapter->num_rx_queues; i++) 3262 napi_enable(&adapter->rx_queue[i].napi); 3263 vmxnet3_enable_all_intrs(adapter); 3264 3265 return 0; 3266 } 3267 3268 static const struct dev_pm_ops vmxnet3_pm_ops = { 3269 .suspend = vmxnet3_suspend, 3270 .resume = vmxnet3_resume, 3271 }; 3272 #endif 3273 3274 static struct pci_driver vmxnet3_driver = { 3275 .name = vmxnet3_driver_name, 3276 .id_table = vmxnet3_pciid_table, 3277 .probe = vmxnet3_probe_device, 3278 .remove = __devexit_p(vmxnet3_remove_device), 3279 #ifdef CONFIG_PM 3280 .driver.pm = &vmxnet3_pm_ops, 3281 #endif 3282 }; 3283 3284 3285 static int __init 3286 vmxnet3_init_module(void) 3287 { 3288 printk(KERN_INFO "%s - version %s\n", VMXNET3_DRIVER_DESC, 3289 VMXNET3_DRIVER_VERSION_REPORT); 3290 return pci_register_driver(&vmxnet3_driver); 3291 } 3292 3293 module_init(vmxnet3_init_module); 3294 3295 3296 static void 3297 vmxnet3_exit_module(void) 3298 { 3299 pci_unregister_driver(&vmxnet3_driver); 3300 } 3301 3302 module_exit(vmxnet3_exit_module); 3303 3304 MODULE_AUTHOR("VMware, Inc."); 3305 MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC); 3306 MODULE_LICENSE("GPL v2"); 3307 MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING); 3308