1d1a890faSShreyas Bhatewara /* 2d1a890faSShreyas Bhatewara * Linux driver for VMware's vmxnet3 ethernet NIC. 3d1a890faSShreyas Bhatewara * 4d1a890faSShreyas Bhatewara * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved. 5d1a890faSShreyas Bhatewara * 6d1a890faSShreyas Bhatewara * This program is free software; you can redistribute it and/or modify it 7d1a890faSShreyas Bhatewara * under the terms of the GNU General Public License as published by the 8d1a890faSShreyas Bhatewara * Free Software Foundation; version 2 of the License and no later version. 9d1a890faSShreyas Bhatewara * 10d1a890faSShreyas Bhatewara * This program is distributed in the hope that it will be useful, but 11d1a890faSShreyas Bhatewara * WITHOUT ANY WARRANTY; without even the implied warranty of 12d1a890faSShreyas Bhatewara * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 13d1a890faSShreyas Bhatewara * NON INFRINGEMENT. See the GNU General Public License for more 14d1a890faSShreyas Bhatewara * details. 15d1a890faSShreyas Bhatewara * 16d1a890faSShreyas Bhatewara * You should have received a copy of the GNU General Public License 17d1a890faSShreyas Bhatewara * along with this program; if not, write to the Free Software 18d1a890faSShreyas Bhatewara * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19d1a890faSShreyas Bhatewara * 20d1a890faSShreyas Bhatewara * The full GNU General Public License is included in this distribution in 21d1a890faSShreyas Bhatewara * the file called "COPYING". 22d1a890faSShreyas Bhatewara * 23d1a890faSShreyas Bhatewara * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com> 24d1a890faSShreyas Bhatewara * 25d1a890faSShreyas Bhatewara */ 26d1a890faSShreyas Bhatewara 279d9779e7SPaul Gortmaker #include <linux/module.h> 28b038b040SStephen Rothwell #include <net/ip6_checksum.h> 29b038b040SStephen Rothwell 30d1a890faSShreyas Bhatewara #include "vmxnet3_int.h" 31d1a890faSShreyas Bhatewara 32d1a890faSShreyas Bhatewara char vmxnet3_driver_name[] = "vmxnet3"; 33d1a890faSShreyas Bhatewara #define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver" 34d1a890faSShreyas Bhatewara 35d1a890faSShreyas Bhatewara /* 36d1a890faSShreyas Bhatewara * PCI Device ID Table 37d1a890faSShreyas Bhatewara * Last entry must be all 0s 38d1a890faSShreyas Bhatewara */ 39a3aa1884SAlexey Dobriyan static DEFINE_PCI_DEVICE_TABLE(vmxnet3_pciid_table) = { 40d1a890faSShreyas Bhatewara {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)}, 41d1a890faSShreyas Bhatewara {0} 42d1a890faSShreyas Bhatewara }; 43d1a890faSShreyas Bhatewara 44d1a890faSShreyas Bhatewara MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table); 45d1a890faSShreyas Bhatewara 46d1a890faSShreyas Bhatewara static atomic_t devices_found; 47d1a890faSShreyas Bhatewara 4809c5088eSShreyas Bhatewara #define VMXNET3_MAX_DEVICES 10 4909c5088eSShreyas Bhatewara static int enable_mq = 1; 5009c5088eSShreyas Bhatewara static int irq_share_mode; 51d1a890faSShreyas Bhatewara 52f9f25026SShreyas Bhatewara static void 53f9f25026SShreyas Bhatewara vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac); 54f9f25026SShreyas Bhatewara 55d1a890faSShreyas Bhatewara /* 56d1a890faSShreyas Bhatewara * Enable/Disable the given intr 57d1a890faSShreyas Bhatewara */ 58d1a890faSShreyas Bhatewara static void 59d1a890faSShreyas Bhatewara vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx) 60d1a890faSShreyas Bhatewara { 61d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0); 62d1a890faSShreyas Bhatewara } 63d1a890faSShreyas Bhatewara 64d1a890faSShreyas Bhatewara 65d1a890faSShreyas Bhatewara static void 66d1a890faSShreyas Bhatewara vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx) 67d1a890faSShreyas Bhatewara { 68d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1); 69d1a890faSShreyas Bhatewara } 70d1a890faSShreyas Bhatewara 71d1a890faSShreyas Bhatewara 72d1a890faSShreyas Bhatewara /* 73d1a890faSShreyas Bhatewara * Enable/Disable all intrs used by the device 74d1a890faSShreyas Bhatewara */ 75d1a890faSShreyas Bhatewara static void 76d1a890faSShreyas Bhatewara vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter) 77d1a890faSShreyas Bhatewara { 78d1a890faSShreyas Bhatewara int i; 79d1a890faSShreyas Bhatewara 80d1a890faSShreyas Bhatewara for (i = 0; i < adapter->intr.num_intrs; i++) 81d1a890faSShreyas Bhatewara vmxnet3_enable_intr(adapter, i); 826929fe8aSRonghua Zang adapter->shared->devRead.intrConf.intrCtrl &= 836929fe8aSRonghua Zang cpu_to_le32(~VMXNET3_IC_DISABLE_ALL); 84d1a890faSShreyas Bhatewara } 85d1a890faSShreyas Bhatewara 86d1a890faSShreyas Bhatewara 87d1a890faSShreyas Bhatewara static void 88d1a890faSShreyas Bhatewara vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter) 89d1a890faSShreyas Bhatewara { 90d1a890faSShreyas Bhatewara int i; 91d1a890faSShreyas Bhatewara 926929fe8aSRonghua Zang adapter->shared->devRead.intrConf.intrCtrl |= 936929fe8aSRonghua Zang cpu_to_le32(VMXNET3_IC_DISABLE_ALL); 94d1a890faSShreyas Bhatewara for (i = 0; i < adapter->intr.num_intrs; i++) 95d1a890faSShreyas Bhatewara vmxnet3_disable_intr(adapter, i); 96d1a890faSShreyas Bhatewara } 97d1a890faSShreyas Bhatewara 98d1a890faSShreyas Bhatewara 99d1a890faSShreyas Bhatewara static void 100d1a890faSShreyas Bhatewara vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events) 101d1a890faSShreyas Bhatewara { 102d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events); 103d1a890faSShreyas Bhatewara } 104d1a890faSShreyas Bhatewara 105d1a890faSShreyas Bhatewara 106d1a890faSShreyas Bhatewara static bool 107d1a890faSShreyas Bhatewara vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 108d1a890faSShreyas Bhatewara { 10909c5088eSShreyas Bhatewara return tq->stopped; 110d1a890faSShreyas Bhatewara } 111d1a890faSShreyas Bhatewara 112d1a890faSShreyas Bhatewara 113d1a890faSShreyas Bhatewara static void 114d1a890faSShreyas Bhatewara vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 115d1a890faSShreyas Bhatewara { 116d1a890faSShreyas Bhatewara tq->stopped = false; 11709c5088eSShreyas Bhatewara netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue); 118d1a890faSShreyas Bhatewara } 119d1a890faSShreyas Bhatewara 120d1a890faSShreyas Bhatewara 121d1a890faSShreyas Bhatewara static void 122d1a890faSShreyas Bhatewara vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 123d1a890faSShreyas Bhatewara { 124d1a890faSShreyas Bhatewara tq->stopped = false; 12509c5088eSShreyas Bhatewara netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue)); 126d1a890faSShreyas Bhatewara } 127d1a890faSShreyas Bhatewara 128d1a890faSShreyas Bhatewara 129d1a890faSShreyas Bhatewara static void 130d1a890faSShreyas Bhatewara vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 131d1a890faSShreyas Bhatewara { 132d1a890faSShreyas Bhatewara tq->stopped = true; 133d1a890faSShreyas Bhatewara tq->num_stop++; 13409c5088eSShreyas Bhatewara netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue)); 135d1a890faSShreyas Bhatewara } 136d1a890faSShreyas Bhatewara 137d1a890faSShreyas Bhatewara 138d1a890faSShreyas Bhatewara /* 139d1a890faSShreyas Bhatewara * Check the link state. This may start or stop the tx queue. 140d1a890faSShreyas Bhatewara */ 141d1a890faSShreyas Bhatewara static void 1424a1745fcSShreyas Bhatewara vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue) 143d1a890faSShreyas Bhatewara { 144d1a890faSShreyas Bhatewara u32 ret; 14509c5088eSShreyas Bhatewara int i; 14683d0feffSShreyas Bhatewara unsigned long flags; 147d1a890faSShreyas Bhatewara 14883d0feffSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 149d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 150d1a890faSShreyas Bhatewara ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 15183d0feffSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 15283d0feffSShreyas Bhatewara 153d1a890faSShreyas Bhatewara adapter->link_speed = ret >> 16; 154d1a890faSShreyas Bhatewara if (ret & 1) { /* Link is up. */ 155d1a890faSShreyas Bhatewara printk(KERN_INFO "%s: NIC Link is Up %d Mbps\n", 156d1a890faSShreyas Bhatewara adapter->netdev->name, adapter->link_speed); 157d1a890faSShreyas Bhatewara if (!netif_carrier_ok(adapter->netdev)) 158d1a890faSShreyas Bhatewara netif_carrier_on(adapter->netdev); 159d1a890faSShreyas Bhatewara 16009c5088eSShreyas Bhatewara if (affectTxQueue) { 16109c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) 16209c5088eSShreyas Bhatewara vmxnet3_tq_start(&adapter->tx_queue[i], 16309c5088eSShreyas Bhatewara adapter); 16409c5088eSShreyas Bhatewara } 165d1a890faSShreyas Bhatewara } else { 166d1a890faSShreyas Bhatewara printk(KERN_INFO "%s: NIC Link is Down\n", 167d1a890faSShreyas Bhatewara adapter->netdev->name); 168d1a890faSShreyas Bhatewara if (netif_carrier_ok(adapter->netdev)) 169d1a890faSShreyas Bhatewara netif_carrier_off(adapter->netdev); 170d1a890faSShreyas Bhatewara 17109c5088eSShreyas Bhatewara if (affectTxQueue) { 17209c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) 17309c5088eSShreyas Bhatewara vmxnet3_tq_stop(&adapter->tx_queue[i], adapter); 17409c5088eSShreyas Bhatewara } 175d1a890faSShreyas Bhatewara } 176d1a890faSShreyas Bhatewara } 177d1a890faSShreyas Bhatewara 178d1a890faSShreyas Bhatewara static void 179d1a890faSShreyas Bhatewara vmxnet3_process_events(struct vmxnet3_adapter *adapter) 180d1a890faSShreyas Bhatewara { 18109c5088eSShreyas Bhatewara int i; 182e328d410SRoland Dreier unsigned long flags; 183115924b6SShreyas Bhatewara u32 events = le32_to_cpu(adapter->shared->ecr); 184d1a890faSShreyas Bhatewara if (!events) 185d1a890faSShreyas Bhatewara return; 186d1a890faSShreyas Bhatewara 187d1a890faSShreyas Bhatewara vmxnet3_ack_events(adapter, events); 188d1a890faSShreyas Bhatewara 189d1a890faSShreyas Bhatewara /* Check if link state has changed */ 190d1a890faSShreyas Bhatewara if (events & VMXNET3_ECR_LINK) 1914a1745fcSShreyas Bhatewara vmxnet3_check_link(adapter, true); 192d1a890faSShreyas Bhatewara 193d1a890faSShreyas Bhatewara /* Check if there is an error on xmit/recv queues */ 194d1a890faSShreyas Bhatewara if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 195e328d410SRoland Dreier spin_lock_irqsave(&adapter->cmd_lock, flags); 196d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 197d1a890faSShreyas Bhatewara VMXNET3_CMD_GET_QUEUE_STATUS); 198e328d410SRoland Dreier spin_unlock_irqrestore(&adapter->cmd_lock, flags); 199d1a890faSShreyas Bhatewara 20009c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) 20109c5088eSShreyas Bhatewara if (adapter->tqd_start[i].status.stopped) 20209c5088eSShreyas Bhatewara dev_err(&adapter->netdev->dev, 20309c5088eSShreyas Bhatewara "%s: tq[%d] error 0x%x\n", 20409c5088eSShreyas Bhatewara adapter->netdev->name, i, le32_to_cpu( 20509c5088eSShreyas Bhatewara adapter->tqd_start[i].status.error)); 20609c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) 20709c5088eSShreyas Bhatewara if (adapter->rqd_start[i].status.stopped) 20809c5088eSShreyas Bhatewara dev_err(&adapter->netdev->dev, 20909c5088eSShreyas Bhatewara "%s: rq[%d] error 0x%x\n", 21009c5088eSShreyas Bhatewara adapter->netdev->name, i, 21109c5088eSShreyas Bhatewara adapter->rqd_start[i].status.error); 212d1a890faSShreyas Bhatewara 213d1a890faSShreyas Bhatewara schedule_work(&adapter->work); 214d1a890faSShreyas Bhatewara } 215d1a890faSShreyas Bhatewara } 216d1a890faSShreyas Bhatewara 217115924b6SShreyas Bhatewara #ifdef __BIG_ENDIAN_BITFIELD 218115924b6SShreyas Bhatewara /* 219115924b6SShreyas Bhatewara * The device expects the bitfields in shared structures to be written in 220115924b6SShreyas Bhatewara * little endian. When CPU is big endian, the following routines are used to 221115924b6SShreyas Bhatewara * correctly read and write into ABI. 222115924b6SShreyas Bhatewara * The general technique used here is : double word bitfields are defined in 223115924b6SShreyas Bhatewara * opposite order for big endian architecture. Then before reading them in 224115924b6SShreyas Bhatewara * driver the complete double word is translated using le32_to_cpu. Similarly 225115924b6SShreyas Bhatewara * After the driver writes into bitfields, cpu_to_le32 is used to translate the 226115924b6SShreyas Bhatewara * double words into required format. 227115924b6SShreyas Bhatewara * In order to avoid touching bits in shared structure more than once, temporary 228115924b6SShreyas Bhatewara * descriptors are used. These are passed as srcDesc to following functions. 229115924b6SShreyas Bhatewara */ 230115924b6SShreyas Bhatewara static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc, 231115924b6SShreyas Bhatewara struct Vmxnet3_RxDesc *dstDesc) 232115924b6SShreyas Bhatewara { 233115924b6SShreyas Bhatewara u32 *src = (u32 *)srcDesc + 2; 234115924b6SShreyas Bhatewara u32 *dst = (u32 *)dstDesc + 2; 235115924b6SShreyas Bhatewara dstDesc->addr = le64_to_cpu(srcDesc->addr); 236115924b6SShreyas Bhatewara *dst = le32_to_cpu(*src); 237115924b6SShreyas Bhatewara dstDesc->ext1 = le32_to_cpu(srcDesc->ext1); 238115924b6SShreyas Bhatewara } 239115924b6SShreyas Bhatewara 240115924b6SShreyas Bhatewara static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc, 241115924b6SShreyas Bhatewara struct Vmxnet3_TxDesc *dstDesc) 242115924b6SShreyas Bhatewara { 243115924b6SShreyas Bhatewara int i; 244115924b6SShreyas Bhatewara u32 *src = (u32 *)(srcDesc + 1); 245115924b6SShreyas Bhatewara u32 *dst = (u32 *)(dstDesc + 1); 246115924b6SShreyas Bhatewara 247115924b6SShreyas Bhatewara /* Working backwards so that the gen bit is set at the end. */ 248115924b6SShreyas Bhatewara for (i = 2; i > 0; i--) { 249115924b6SShreyas Bhatewara src--; 250115924b6SShreyas Bhatewara dst--; 251115924b6SShreyas Bhatewara *dst = cpu_to_le32(*src); 252115924b6SShreyas Bhatewara } 253115924b6SShreyas Bhatewara } 254115924b6SShreyas Bhatewara 255115924b6SShreyas Bhatewara 256115924b6SShreyas Bhatewara static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc, 257115924b6SShreyas Bhatewara struct Vmxnet3_RxCompDesc *dstDesc) 258115924b6SShreyas Bhatewara { 259115924b6SShreyas Bhatewara int i = 0; 260115924b6SShreyas Bhatewara u32 *src = (u32 *)srcDesc; 261115924b6SShreyas Bhatewara u32 *dst = (u32 *)dstDesc; 262115924b6SShreyas Bhatewara for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) { 263115924b6SShreyas Bhatewara *dst = le32_to_cpu(*src); 264115924b6SShreyas Bhatewara src++; 265115924b6SShreyas Bhatewara dst++; 266115924b6SShreyas Bhatewara } 267115924b6SShreyas Bhatewara } 268115924b6SShreyas Bhatewara 269115924b6SShreyas Bhatewara 270115924b6SShreyas Bhatewara /* Used to read bitfield values from double words. */ 271115924b6SShreyas Bhatewara static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size) 272115924b6SShreyas Bhatewara { 273115924b6SShreyas Bhatewara u32 temp = le32_to_cpu(*bitfield); 274115924b6SShreyas Bhatewara u32 mask = ((1 << size) - 1) << pos; 275115924b6SShreyas Bhatewara temp &= mask; 276115924b6SShreyas Bhatewara temp >>= pos; 277115924b6SShreyas Bhatewara return temp; 278115924b6SShreyas Bhatewara } 279115924b6SShreyas Bhatewara 280115924b6SShreyas Bhatewara 281115924b6SShreyas Bhatewara 282115924b6SShreyas Bhatewara #endif /* __BIG_ENDIAN_BITFIELD */ 283115924b6SShreyas Bhatewara 284115924b6SShreyas Bhatewara #ifdef __BIG_ENDIAN_BITFIELD 285115924b6SShreyas Bhatewara 286115924b6SShreyas Bhatewara # define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \ 287115924b6SShreyas Bhatewara txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \ 288115924b6SShreyas Bhatewara VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE) 289115924b6SShreyas Bhatewara # define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \ 290115924b6SShreyas Bhatewara txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \ 291115924b6SShreyas Bhatewara VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE) 292115924b6SShreyas Bhatewara # define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \ 293115924b6SShreyas Bhatewara VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \ 294115924b6SShreyas Bhatewara VMXNET3_TCD_GEN_SIZE) 295115924b6SShreyas Bhatewara # define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \ 296115924b6SShreyas Bhatewara VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE) 297115924b6SShreyas Bhatewara # define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \ 298115924b6SShreyas Bhatewara (dstrcd) = (tmp); \ 299115924b6SShreyas Bhatewara vmxnet3_RxCompToCPU((rcd), (tmp)); \ 300115924b6SShreyas Bhatewara } while (0) 301115924b6SShreyas Bhatewara # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \ 302115924b6SShreyas Bhatewara (dstrxd) = (tmp); \ 303115924b6SShreyas Bhatewara vmxnet3_RxDescToCPU((rxd), (tmp)); \ 304115924b6SShreyas Bhatewara } while (0) 305115924b6SShreyas Bhatewara 306115924b6SShreyas Bhatewara #else 307115924b6SShreyas Bhatewara 308115924b6SShreyas Bhatewara # define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen) 309115924b6SShreyas Bhatewara # define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop) 310115924b6SShreyas Bhatewara # define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen) 311115924b6SShreyas Bhatewara # define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx) 312115924b6SShreyas Bhatewara # define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd) 313115924b6SShreyas Bhatewara # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd) 314115924b6SShreyas Bhatewara 315115924b6SShreyas Bhatewara #endif /* __BIG_ENDIAN_BITFIELD */ 316115924b6SShreyas Bhatewara 317d1a890faSShreyas Bhatewara 318d1a890faSShreyas Bhatewara static void 319d1a890faSShreyas Bhatewara vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi, 320d1a890faSShreyas Bhatewara struct pci_dev *pdev) 321d1a890faSShreyas Bhatewara { 322d1a890faSShreyas Bhatewara if (tbi->map_type == VMXNET3_MAP_SINGLE) 323d1a890faSShreyas Bhatewara pci_unmap_single(pdev, tbi->dma_addr, tbi->len, 324d1a890faSShreyas Bhatewara PCI_DMA_TODEVICE); 325d1a890faSShreyas Bhatewara else if (tbi->map_type == VMXNET3_MAP_PAGE) 326d1a890faSShreyas Bhatewara pci_unmap_page(pdev, tbi->dma_addr, tbi->len, 327d1a890faSShreyas Bhatewara PCI_DMA_TODEVICE); 328d1a890faSShreyas Bhatewara else 329d1a890faSShreyas Bhatewara BUG_ON(tbi->map_type != VMXNET3_MAP_NONE); 330d1a890faSShreyas Bhatewara 331d1a890faSShreyas Bhatewara tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */ 332d1a890faSShreyas Bhatewara } 333d1a890faSShreyas Bhatewara 334d1a890faSShreyas Bhatewara 335d1a890faSShreyas Bhatewara static int 336d1a890faSShreyas Bhatewara vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq, 337d1a890faSShreyas Bhatewara struct pci_dev *pdev, struct vmxnet3_adapter *adapter) 338d1a890faSShreyas Bhatewara { 339d1a890faSShreyas Bhatewara struct sk_buff *skb; 340d1a890faSShreyas Bhatewara int entries = 0; 341d1a890faSShreyas Bhatewara 342d1a890faSShreyas Bhatewara /* no out of order completion */ 343d1a890faSShreyas Bhatewara BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp); 344115924b6SShreyas Bhatewara BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1); 345d1a890faSShreyas Bhatewara 346d1a890faSShreyas Bhatewara skb = tq->buf_info[eop_idx].skb; 347d1a890faSShreyas Bhatewara BUG_ON(skb == NULL); 348d1a890faSShreyas Bhatewara tq->buf_info[eop_idx].skb = NULL; 349d1a890faSShreyas Bhatewara 350d1a890faSShreyas Bhatewara VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size); 351d1a890faSShreyas Bhatewara 352d1a890faSShreyas Bhatewara while (tq->tx_ring.next2comp != eop_idx) { 353d1a890faSShreyas Bhatewara vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp, 354d1a890faSShreyas Bhatewara pdev); 355d1a890faSShreyas Bhatewara 356d1a890faSShreyas Bhatewara /* update next2comp w/o tx_lock. Since we are marking more, 357d1a890faSShreyas Bhatewara * instead of less, tx ring entries avail, the worst case is 358d1a890faSShreyas Bhatewara * that the tx routine incorrectly re-queues a pkt due to 359d1a890faSShreyas Bhatewara * insufficient tx ring entries. 360d1a890faSShreyas Bhatewara */ 361d1a890faSShreyas Bhatewara vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring); 362d1a890faSShreyas Bhatewara entries++; 363d1a890faSShreyas Bhatewara } 364d1a890faSShreyas Bhatewara 365d1a890faSShreyas Bhatewara dev_kfree_skb_any(skb); 366d1a890faSShreyas Bhatewara return entries; 367d1a890faSShreyas Bhatewara } 368d1a890faSShreyas Bhatewara 369d1a890faSShreyas Bhatewara 370d1a890faSShreyas Bhatewara static int 371d1a890faSShreyas Bhatewara vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq, 372d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 373d1a890faSShreyas Bhatewara { 374d1a890faSShreyas Bhatewara int completed = 0; 375d1a890faSShreyas Bhatewara union Vmxnet3_GenericDesc *gdesc; 376d1a890faSShreyas Bhatewara 377d1a890faSShreyas Bhatewara gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; 378115924b6SShreyas Bhatewara while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) { 379115924b6SShreyas Bhatewara completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX( 380115924b6SShreyas Bhatewara &gdesc->tcd), tq, adapter->pdev, 381115924b6SShreyas Bhatewara adapter); 382d1a890faSShreyas Bhatewara 383d1a890faSShreyas Bhatewara vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring); 384d1a890faSShreyas Bhatewara gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; 385d1a890faSShreyas Bhatewara } 386d1a890faSShreyas Bhatewara 387d1a890faSShreyas Bhatewara if (completed) { 388d1a890faSShreyas Bhatewara spin_lock(&tq->tx_lock); 389d1a890faSShreyas Bhatewara if (unlikely(vmxnet3_tq_stopped(tq, adapter) && 390d1a890faSShreyas Bhatewara vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) > 391d1a890faSShreyas Bhatewara VMXNET3_WAKE_QUEUE_THRESHOLD(tq) && 392d1a890faSShreyas Bhatewara netif_carrier_ok(adapter->netdev))) { 393d1a890faSShreyas Bhatewara vmxnet3_tq_wake(tq, adapter); 394d1a890faSShreyas Bhatewara } 395d1a890faSShreyas Bhatewara spin_unlock(&tq->tx_lock); 396d1a890faSShreyas Bhatewara } 397d1a890faSShreyas Bhatewara return completed; 398d1a890faSShreyas Bhatewara } 399d1a890faSShreyas Bhatewara 400d1a890faSShreyas Bhatewara 401d1a890faSShreyas Bhatewara static void 402d1a890faSShreyas Bhatewara vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq, 403d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 404d1a890faSShreyas Bhatewara { 405d1a890faSShreyas Bhatewara int i; 406d1a890faSShreyas Bhatewara 407d1a890faSShreyas Bhatewara while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) { 408d1a890faSShreyas Bhatewara struct vmxnet3_tx_buf_info *tbi; 409d1a890faSShreyas Bhatewara 410d1a890faSShreyas Bhatewara tbi = tq->buf_info + tq->tx_ring.next2comp; 411d1a890faSShreyas Bhatewara 412d1a890faSShreyas Bhatewara vmxnet3_unmap_tx_buf(tbi, adapter->pdev); 413d1a890faSShreyas Bhatewara if (tbi->skb) { 414d1a890faSShreyas Bhatewara dev_kfree_skb_any(tbi->skb); 415d1a890faSShreyas Bhatewara tbi->skb = NULL; 416d1a890faSShreyas Bhatewara } 417d1a890faSShreyas Bhatewara vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring); 418d1a890faSShreyas Bhatewara } 419d1a890faSShreyas Bhatewara 420d1a890faSShreyas Bhatewara /* sanity check, verify all buffers are indeed unmapped and freed */ 421d1a890faSShreyas Bhatewara for (i = 0; i < tq->tx_ring.size; i++) { 422d1a890faSShreyas Bhatewara BUG_ON(tq->buf_info[i].skb != NULL || 423d1a890faSShreyas Bhatewara tq->buf_info[i].map_type != VMXNET3_MAP_NONE); 424d1a890faSShreyas Bhatewara } 425d1a890faSShreyas Bhatewara 426d1a890faSShreyas Bhatewara tq->tx_ring.gen = VMXNET3_INIT_GEN; 427d1a890faSShreyas Bhatewara tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0; 428d1a890faSShreyas Bhatewara 429d1a890faSShreyas Bhatewara tq->comp_ring.gen = VMXNET3_INIT_GEN; 430d1a890faSShreyas Bhatewara tq->comp_ring.next2proc = 0; 431d1a890faSShreyas Bhatewara } 432d1a890faSShreyas Bhatewara 433d1a890faSShreyas Bhatewara 43409c5088eSShreyas Bhatewara static void 435d1a890faSShreyas Bhatewara vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq, 436d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 437d1a890faSShreyas Bhatewara { 438d1a890faSShreyas Bhatewara if (tq->tx_ring.base) { 439d1a890faSShreyas Bhatewara pci_free_consistent(adapter->pdev, tq->tx_ring.size * 440d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_TxDesc), 441d1a890faSShreyas Bhatewara tq->tx_ring.base, tq->tx_ring.basePA); 442d1a890faSShreyas Bhatewara tq->tx_ring.base = NULL; 443d1a890faSShreyas Bhatewara } 444d1a890faSShreyas Bhatewara if (tq->data_ring.base) { 445d1a890faSShreyas Bhatewara pci_free_consistent(adapter->pdev, tq->data_ring.size * 446d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_TxDataDesc), 447d1a890faSShreyas Bhatewara tq->data_ring.base, tq->data_ring.basePA); 448d1a890faSShreyas Bhatewara tq->data_ring.base = NULL; 449d1a890faSShreyas Bhatewara } 450d1a890faSShreyas Bhatewara if (tq->comp_ring.base) { 451d1a890faSShreyas Bhatewara pci_free_consistent(adapter->pdev, tq->comp_ring.size * 452d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_TxCompDesc), 453d1a890faSShreyas Bhatewara tq->comp_ring.base, tq->comp_ring.basePA); 454d1a890faSShreyas Bhatewara tq->comp_ring.base = NULL; 455d1a890faSShreyas Bhatewara } 456d1a890faSShreyas Bhatewara kfree(tq->buf_info); 457d1a890faSShreyas Bhatewara tq->buf_info = NULL; 458d1a890faSShreyas Bhatewara } 459d1a890faSShreyas Bhatewara 460d1a890faSShreyas Bhatewara 46109c5088eSShreyas Bhatewara /* Destroy all tx queues */ 46209c5088eSShreyas Bhatewara void 46309c5088eSShreyas Bhatewara vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter) 46409c5088eSShreyas Bhatewara { 46509c5088eSShreyas Bhatewara int i; 46609c5088eSShreyas Bhatewara 46709c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) 46809c5088eSShreyas Bhatewara vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter); 46909c5088eSShreyas Bhatewara } 47009c5088eSShreyas Bhatewara 47109c5088eSShreyas Bhatewara 472d1a890faSShreyas Bhatewara static void 473d1a890faSShreyas Bhatewara vmxnet3_tq_init(struct vmxnet3_tx_queue *tq, 474d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 475d1a890faSShreyas Bhatewara { 476d1a890faSShreyas Bhatewara int i; 477d1a890faSShreyas Bhatewara 478d1a890faSShreyas Bhatewara /* reset the tx ring contents to 0 and reset the tx ring states */ 479d1a890faSShreyas Bhatewara memset(tq->tx_ring.base, 0, tq->tx_ring.size * 480d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_TxDesc)); 481d1a890faSShreyas Bhatewara tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0; 482d1a890faSShreyas Bhatewara tq->tx_ring.gen = VMXNET3_INIT_GEN; 483d1a890faSShreyas Bhatewara 484d1a890faSShreyas Bhatewara memset(tq->data_ring.base, 0, tq->data_ring.size * 485d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_TxDataDesc)); 486d1a890faSShreyas Bhatewara 487d1a890faSShreyas Bhatewara /* reset the tx comp ring contents to 0 and reset comp ring states */ 488d1a890faSShreyas Bhatewara memset(tq->comp_ring.base, 0, tq->comp_ring.size * 489d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_TxCompDesc)); 490d1a890faSShreyas Bhatewara tq->comp_ring.next2proc = 0; 491d1a890faSShreyas Bhatewara tq->comp_ring.gen = VMXNET3_INIT_GEN; 492d1a890faSShreyas Bhatewara 493d1a890faSShreyas Bhatewara /* reset the bookkeeping data */ 494d1a890faSShreyas Bhatewara memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size); 495d1a890faSShreyas Bhatewara for (i = 0; i < tq->tx_ring.size; i++) 496d1a890faSShreyas Bhatewara tq->buf_info[i].map_type = VMXNET3_MAP_NONE; 497d1a890faSShreyas Bhatewara 498d1a890faSShreyas Bhatewara /* stats are not reset */ 499d1a890faSShreyas Bhatewara } 500d1a890faSShreyas Bhatewara 501d1a890faSShreyas Bhatewara 502d1a890faSShreyas Bhatewara static int 503d1a890faSShreyas Bhatewara vmxnet3_tq_create(struct vmxnet3_tx_queue *tq, 504d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 505d1a890faSShreyas Bhatewara { 506d1a890faSShreyas Bhatewara BUG_ON(tq->tx_ring.base || tq->data_ring.base || 507d1a890faSShreyas Bhatewara tq->comp_ring.base || tq->buf_info); 508d1a890faSShreyas Bhatewara 509d1a890faSShreyas Bhatewara tq->tx_ring.base = pci_alloc_consistent(adapter->pdev, tq->tx_ring.size 510d1a890faSShreyas Bhatewara * sizeof(struct Vmxnet3_TxDesc), 511d1a890faSShreyas Bhatewara &tq->tx_ring.basePA); 512d1a890faSShreyas Bhatewara if (!tq->tx_ring.base) { 513d1a890faSShreyas Bhatewara printk(KERN_ERR "%s: failed to allocate tx ring\n", 514d1a890faSShreyas Bhatewara adapter->netdev->name); 515d1a890faSShreyas Bhatewara goto err; 516d1a890faSShreyas Bhatewara } 517d1a890faSShreyas Bhatewara 518d1a890faSShreyas Bhatewara tq->data_ring.base = pci_alloc_consistent(adapter->pdev, 519d1a890faSShreyas Bhatewara tq->data_ring.size * 520d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_TxDataDesc), 521d1a890faSShreyas Bhatewara &tq->data_ring.basePA); 522d1a890faSShreyas Bhatewara if (!tq->data_ring.base) { 523d1a890faSShreyas Bhatewara printk(KERN_ERR "%s: failed to allocate data ring\n", 524d1a890faSShreyas Bhatewara adapter->netdev->name); 525d1a890faSShreyas Bhatewara goto err; 526d1a890faSShreyas Bhatewara } 527d1a890faSShreyas Bhatewara 528d1a890faSShreyas Bhatewara tq->comp_ring.base = pci_alloc_consistent(adapter->pdev, 529d1a890faSShreyas Bhatewara tq->comp_ring.size * 530d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_TxCompDesc), 531d1a890faSShreyas Bhatewara &tq->comp_ring.basePA); 532d1a890faSShreyas Bhatewara if (!tq->comp_ring.base) { 533d1a890faSShreyas Bhatewara printk(KERN_ERR "%s: failed to allocate tx comp ring\n", 534d1a890faSShreyas Bhatewara adapter->netdev->name); 535d1a890faSShreyas Bhatewara goto err; 536d1a890faSShreyas Bhatewara } 537d1a890faSShreyas Bhatewara 538d1a890faSShreyas Bhatewara tq->buf_info = kcalloc(tq->tx_ring.size, sizeof(tq->buf_info[0]), 539d1a890faSShreyas Bhatewara GFP_KERNEL); 540e404decbSJoe Perches if (!tq->buf_info) 541d1a890faSShreyas Bhatewara goto err; 542d1a890faSShreyas Bhatewara 543d1a890faSShreyas Bhatewara return 0; 544d1a890faSShreyas Bhatewara 545d1a890faSShreyas Bhatewara err: 546d1a890faSShreyas Bhatewara vmxnet3_tq_destroy(tq, adapter); 547d1a890faSShreyas Bhatewara return -ENOMEM; 548d1a890faSShreyas Bhatewara } 549d1a890faSShreyas Bhatewara 55009c5088eSShreyas Bhatewara static void 55109c5088eSShreyas Bhatewara vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter) 55209c5088eSShreyas Bhatewara { 55309c5088eSShreyas Bhatewara int i; 55409c5088eSShreyas Bhatewara 55509c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) 55609c5088eSShreyas Bhatewara vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter); 55709c5088eSShreyas Bhatewara } 558d1a890faSShreyas Bhatewara 559d1a890faSShreyas Bhatewara /* 560d1a890faSShreyas Bhatewara * starting from ring->next2fill, allocate rx buffers for the given ring 561d1a890faSShreyas Bhatewara * of the rx queue and update the rx desc. stop after @num_to_alloc buffers 562d1a890faSShreyas Bhatewara * are allocated or allocation fails 563d1a890faSShreyas Bhatewara */ 564d1a890faSShreyas Bhatewara 565d1a890faSShreyas Bhatewara static int 566d1a890faSShreyas Bhatewara vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx, 567d1a890faSShreyas Bhatewara int num_to_alloc, struct vmxnet3_adapter *adapter) 568d1a890faSShreyas Bhatewara { 569d1a890faSShreyas Bhatewara int num_allocated = 0; 570d1a890faSShreyas Bhatewara struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx]; 571d1a890faSShreyas Bhatewara struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx]; 572d1a890faSShreyas Bhatewara u32 val; 573d1a890faSShreyas Bhatewara 5745318d809SShreyas Bhatewara while (num_allocated <= num_to_alloc) { 575d1a890faSShreyas Bhatewara struct vmxnet3_rx_buf_info *rbi; 576d1a890faSShreyas Bhatewara union Vmxnet3_GenericDesc *gd; 577d1a890faSShreyas Bhatewara 578d1a890faSShreyas Bhatewara rbi = rbi_base + ring->next2fill; 579d1a890faSShreyas Bhatewara gd = ring->base + ring->next2fill; 580d1a890faSShreyas Bhatewara 581d1a890faSShreyas Bhatewara if (rbi->buf_type == VMXNET3_RX_BUF_SKB) { 582d1a890faSShreyas Bhatewara if (rbi->skb == NULL) { 5830d735f13SStephen Hemminger rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev, 5840d735f13SStephen Hemminger rbi->len, 5850d735f13SStephen Hemminger GFP_KERNEL); 586d1a890faSShreyas Bhatewara if (unlikely(rbi->skb == NULL)) { 587d1a890faSShreyas Bhatewara rq->stats.rx_buf_alloc_failure++; 588d1a890faSShreyas Bhatewara break; 589d1a890faSShreyas Bhatewara } 590d1a890faSShreyas Bhatewara 591d1a890faSShreyas Bhatewara rbi->dma_addr = pci_map_single(adapter->pdev, 592d1a890faSShreyas Bhatewara rbi->skb->data, rbi->len, 593d1a890faSShreyas Bhatewara PCI_DMA_FROMDEVICE); 594d1a890faSShreyas Bhatewara } else { 595d1a890faSShreyas Bhatewara /* rx buffer skipped by the device */ 596d1a890faSShreyas Bhatewara } 597d1a890faSShreyas Bhatewara val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT; 598d1a890faSShreyas Bhatewara } else { 599d1a890faSShreyas Bhatewara BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE || 600d1a890faSShreyas Bhatewara rbi->len != PAGE_SIZE); 601d1a890faSShreyas Bhatewara 602d1a890faSShreyas Bhatewara if (rbi->page == NULL) { 603d1a890faSShreyas Bhatewara rbi->page = alloc_page(GFP_ATOMIC); 604d1a890faSShreyas Bhatewara if (unlikely(rbi->page == NULL)) { 605d1a890faSShreyas Bhatewara rq->stats.rx_buf_alloc_failure++; 606d1a890faSShreyas Bhatewara break; 607d1a890faSShreyas Bhatewara } 608d1a890faSShreyas Bhatewara rbi->dma_addr = pci_map_page(adapter->pdev, 609d1a890faSShreyas Bhatewara rbi->page, 0, PAGE_SIZE, 610d1a890faSShreyas Bhatewara PCI_DMA_FROMDEVICE); 611d1a890faSShreyas Bhatewara } else { 612d1a890faSShreyas Bhatewara /* rx buffers skipped by the device */ 613d1a890faSShreyas Bhatewara } 614d1a890faSShreyas Bhatewara val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT; 615d1a890faSShreyas Bhatewara } 616d1a890faSShreyas Bhatewara 617d1a890faSShreyas Bhatewara BUG_ON(rbi->dma_addr == 0); 618115924b6SShreyas Bhatewara gd->rxd.addr = cpu_to_le64(rbi->dma_addr); 6195318d809SShreyas Bhatewara gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT) 620115924b6SShreyas Bhatewara | val | rbi->len); 621d1a890faSShreyas Bhatewara 6225318d809SShreyas Bhatewara /* Fill the last buffer but dont mark it ready, or else the 6235318d809SShreyas Bhatewara * device will think that the queue is full */ 6245318d809SShreyas Bhatewara if (num_allocated == num_to_alloc) 6255318d809SShreyas Bhatewara break; 6265318d809SShreyas Bhatewara 6275318d809SShreyas Bhatewara gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT); 628d1a890faSShreyas Bhatewara num_allocated++; 629d1a890faSShreyas Bhatewara vmxnet3_cmd_ring_adv_next2fill(ring); 630d1a890faSShreyas Bhatewara } 631d1a890faSShreyas Bhatewara 632fdcd79b9SStephen Hemminger netdev_dbg(adapter->netdev, 63369b9a712SStephen Hemminger "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n", 63469b9a712SStephen Hemminger num_allocated, ring->next2fill, ring->next2comp); 635d1a890faSShreyas Bhatewara 636d1a890faSShreyas Bhatewara /* so that the device can distinguish a full ring and an empty ring */ 637d1a890faSShreyas Bhatewara BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp); 638d1a890faSShreyas Bhatewara 639d1a890faSShreyas Bhatewara return num_allocated; 640d1a890faSShreyas Bhatewara } 641d1a890faSShreyas Bhatewara 642d1a890faSShreyas Bhatewara 643d1a890faSShreyas Bhatewara static void 644d1a890faSShreyas Bhatewara vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd, 645d1a890faSShreyas Bhatewara struct vmxnet3_rx_buf_info *rbi) 646d1a890faSShreyas Bhatewara { 647d1a890faSShreyas Bhatewara struct skb_frag_struct *frag = skb_shinfo(skb)->frags + 648d1a890faSShreyas Bhatewara skb_shinfo(skb)->nr_frags; 649d1a890faSShreyas Bhatewara 650d1a890faSShreyas Bhatewara BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS); 651d1a890faSShreyas Bhatewara 6520e0634d2SIan Campbell __skb_frag_set_page(frag, rbi->page); 653d1a890faSShreyas Bhatewara frag->page_offset = 0; 6549e903e08SEric Dumazet skb_frag_size_set(frag, rcd->len); 6559e903e08SEric Dumazet skb->data_len += rcd->len; 6565e6c355cSEric Dumazet skb->truesize += PAGE_SIZE; 657d1a890faSShreyas Bhatewara skb_shinfo(skb)->nr_frags++; 658d1a890faSShreyas Bhatewara } 659d1a890faSShreyas Bhatewara 660d1a890faSShreyas Bhatewara 661d1a890faSShreyas Bhatewara static void 662d1a890faSShreyas Bhatewara vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx, 663d1a890faSShreyas Bhatewara struct vmxnet3_tx_queue *tq, struct pci_dev *pdev, 664d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 665d1a890faSShreyas Bhatewara { 666d1a890faSShreyas Bhatewara u32 dw2, len; 667d1a890faSShreyas Bhatewara unsigned long buf_offset; 668d1a890faSShreyas Bhatewara int i; 669d1a890faSShreyas Bhatewara union Vmxnet3_GenericDesc *gdesc; 670d1a890faSShreyas Bhatewara struct vmxnet3_tx_buf_info *tbi = NULL; 671d1a890faSShreyas Bhatewara 672d1a890faSShreyas Bhatewara BUG_ON(ctx->copy_size > skb_headlen(skb)); 673d1a890faSShreyas Bhatewara 674d1a890faSShreyas Bhatewara /* use the previous gen bit for the SOP desc */ 675d1a890faSShreyas Bhatewara dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT; 676d1a890faSShreyas Bhatewara 677d1a890faSShreyas Bhatewara ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill; 678d1a890faSShreyas Bhatewara gdesc = ctx->sop_txd; /* both loops below can be skipped */ 679d1a890faSShreyas Bhatewara 680d1a890faSShreyas Bhatewara /* no need to map the buffer if headers are copied */ 681d1a890faSShreyas Bhatewara if (ctx->copy_size) { 682115924b6SShreyas Bhatewara ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA + 683d1a890faSShreyas Bhatewara tq->tx_ring.next2fill * 684115924b6SShreyas Bhatewara sizeof(struct Vmxnet3_TxDataDesc)); 685115924b6SShreyas Bhatewara ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size); 686d1a890faSShreyas Bhatewara ctx->sop_txd->dword[3] = 0; 687d1a890faSShreyas Bhatewara 688d1a890faSShreyas Bhatewara tbi = tq->buf_info + tq->tx_ring.next2fill; 689d1a890faSShreyas Bhatewara tbi->map_type = VMXNET3_MAP_NONE; 690d1a890faSShreyas Bhatewara 691fdcd79b9SStephen Hemminger netdev_dbg(adapter->netdev, 692f6965582SRandy Dunlap "txd[%u]: 0x%Lx 0x%x 0x%x\n", 693115924b6SShreyas Bhatewara tq->tx_ring.next2fill, 694115924b6SShreyas Bhatewara le64_to_cpu(ctx->sop_txd->txd.addr), 695d1a890faSShreyas Bhatewara ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]); 696d1a890faSShreyas Bhatewara vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 697d1a890faSShreyas Bhatewara 698d1a890faSShreyas Bhatewara /* use the right gen for non-SOP desc */ 699d1a890faSShreyas Bhatewara dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 700d1a890faSShreyas Bhatewara } 701d1a890faSShreyas Bhatewara 702d1a890faSShreyas Bhatewara /* linear part can use multiple tx desc if it's big */ 703d1a890faSShreyas Bhatewara len = skb_headlen(skb) - ctx->copy_size; 704d1a890faSShreyas Bhatewara buf_offset = ctx->copy_size; 705d1a890faSShreyas Bhatewara while (len) { 706d1a890faSShreyas Bhatewara u32 buf_size; 707d1a890faSShreyas Bhatewara 7081f4b1612SBhavesh Davda if (len < VMXNET3_MAX_TX_BUF_SIZE) { 7091f4b1612SBhavesh Davda buf_size = len; 7101f4b1612SBhavesh Davda dw2 |= len; 7111f4b1612SBhavesh Davda } else { 7121f4b1612SBhavesh Davda buf_size = VMXNET3_MAX_TX_BUF_SIZE; 7131f4b1612SBhavesh Davda /* spec says that for TxDesc.len, 0 == 2^14 */ 7141f4b1612SBhavesh Davda } 715d1a890faSShreyas Bhatewara 716d1a890faSShreyas Bhatewara tbi = tq->buf_info + tq->tx_ring.next2fill; 717d1a890faSShreyas Bhatewara tbi->map_type = VMXNET3_MAP_SINGLE; 718d1a890faSShreyas Bhatewara tbi->dma_addr = pci_map_single(adapter->pdev, 719d1a890faSShreyas Bhatewara skb->data + buf_offset, buf_size, 720d1a890faSShreyas Bhatewara PCI_DMA_TODEVICE); 721d1a890faSShreyas Bhatewara 7221f4b1612SBhavesh Davda tbi->len = buf_size; 723d1a890faSShreyas Bhatewara 724d1a890faSShreyas Bhatewara gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; 725d1a890faSShreyas Bhatewara BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); 726d1a890faSShreyas Bhatewara 727115924b6SShreyas Bhatewara gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); 7281f4b1612SBhavesh Davda gdesc->dword[2] = cpu_to_le32(dw2); 729d1a890faSShreyas Bhatewara gdesc->dword[3] = 0; 730d1a890faSShreyas Bhatewara 731fdcd79b9SStephen Hemminger netdev_dbg(adapter->netdev, 732f6965582SRandy Dunlap "txd[%u]: 0x%Lx 0x%x 0x%x\n", 733115924b6SShreyas Bhatewara tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), 734115924b6SShreyas Bhatewara le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); 735d1a890faSShreyas Bhatewara vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 736d1a890faSShreyas Bhatewara dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 737d1a890faSShreyas Bhatewara 738d1a890faSShreyas Bhatewara len -= buf_size; 739d1a890faSShreyas Bhatewara buf_offset += buf_size; 740d1a890faSShreyas Bhatewara } 741d1a890faSShreyas Bhatewara 742d1a890faSShreyas Bhatewara for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 7439e903e08SEric Dumazet const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 744a4d7e485SEric Dumazet u32 buf_size; 745d1a890faSShreyas Bhatewara 746a4d7e485SEric Dumazet buf_offset = 0; 747a4d7e485SEric Dumazet len = skb_frag_size(frag); 748a4d7e485SEric Dumazet while (len) { 749d1a890faSShreyas Bhatewara tbi = tq->buf_info + tq->tx_ring.next2fill; 750a4d7e485SEric Dumazet if (len < VMXNET3_MAX_TX_BUF_SIZE) { 751a4d7e485SEric Dumazet buf_size = len; 752a4d7e485SEric Dumazet dw2 |= len; 753a4d7e485SEric Dumazet } else { 754a4d7e485SEric Dumazet buf_size = VMXNET3_MAX_TX_BUF_SIZE; 755a4d7e485SEric Dumazet /* spec says that for TxDesc.len, 0 == 2^14 */ 756a4d7e485SEric Dumazet } 757d1a890faSShreyas Bhatewara tbi->map_type = VMXNET3_MAP_PAGE; 7580e0634d2SIan Campbell tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag, 759a4d7e485SEric Dumazet buf_offset, buf_size, 7605d6bcdfeSIan Campbell DMA_TO_DEVICE); 761d1a890faSShreyas Bhatewara 762a4d7e485SEric Dumazet tbi->len = buf_size; 763d1a890faSShreyas Bhatewara 764d1a890faSShreyas Bhatewara gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; 765d1a890faSShreyas Bhatewara BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); 766d1a890faSShreyas Bhatewara 767115924b6SShreyas Bhatewara gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); 768a4d7e485SEric Dumazet gdesc->dword[2] = cpu_to_le32(dw2); 769d1a890faSShreyas Bhatewara gdesc->dword[3] = 0; 770d1a890faSShreyas Bhatewara 771fdcd79b9SStephen Hemminger netdev_dbg(adapter->netdev, 772f6965582SRandy Dunlap "txd[%u]: 0x%llu %u %u\n", 773115924b6SShreyas Bhatewara tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), 774115924b6SShreyas Bhatewara le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); 775d1a890faSShreyas Bhatewara vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 776d1a890faSShreyas Bhatewara dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 777a4d7e485SEric Dumazet 778a4d7e485SEric Dumazet len -= buf_size; 779a4d7e485SEric Dumazet buf_offset += buf_size; 780a4d7e485SEric Dumazet } 781d1a890faSShreyas Bhatewara } 782d1a890faSShreyas Bhatewara 783d1a890faSShreyas Bhatewara ctx->eop_txd = gdesc; 784d1a890faSShreyas Bhatewara 785d1a890faSShreyas Bhatewara /* set the last buf_info for the pkt */ 786d1a890faSShreyas Bhatewara tbi->skb = skb; 787d1a890faSShreyas Bhatewara tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base; 788d1a890faSShreyas Bhatewara } 789d1a890faSShreyas Bhatewara 790d1a890faSShreyas Bhatewara 79109c5088eSShreyas Bhatewara /* Init all tx queues */ 79209c5088eSShreyas Bhatewara static void 79309c5088eSShreyas Bhatewara vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter) 79409c5088eSShreyas Bhatewara { 79509c5088eSShreyas Bhatewara int i; 79609c5088eSShreyas Bhatewara 79709c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) 79809c5088eSShreyas Bhatewara vmxnet3_tq_init(&adapter->tx_queue[i], adapter); 79909c5088eSShreyas Bhatewara } 80009c5088eSShreyas Bhatewara 80109c5088eSShreyas Bhatewara 802d1a890faSShreyas Bhatewara /* 803d1a890faSShreyas Bhatewara * parse and copy relevant protocol headers: 804d1a890faSShreyas Bhatewara * For a tso pkt, relevant headers are L2/3/4 including options 805d1a890faSShreyas Bhatewara * For a pkt requesting csum offloading, they are L2/3 and may include L4 806d1a890faSShreyas Bhatewara * if it's a TCP/UDP pkt 807d1a890faSShreyas Bhatewara * 808d1a890faSShreyas Bhatewara * Returns: 809d1a890faSShreyas Bhatewara * -1: error happens during parsing 810d1a890faSShreyas Bhatewara * 0: protocol headers parsed, but too big to be copied 811d1a890faSShreyas Bhatewara * 1: protocol headers parsed and copied 812d1a890faSShreyas Bhatewara * 813d1a890faSShreyas Bhatewara * Other effects: 814d1a890faSShreyas Bhatewara * 1. related *ctx fields are updated. 815d1a890faSShreyas Bhatewara * 2. ctx->copy_size is # of bytes copied 816d1a890faSShreyas Bhatewara * 3. the portion copied is guaranteed to be in the linear part 817d1a890faSShreyas Bhatewara * 818d1a890faSShreyas Bhatewara */ 819d1a890faSShreyas Bhatewara static int 820d1a890faSShreyas Bhatewara vmxnet3_parse_and_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 821d1a890faSShreyas Bhatewara struct vmxnet3_tx_ctx *ctx, 822d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 823d1a890faSShreyas Bhatewara { 824d1a890faSShreyas Bhatewara struct Vmxnet3_TxDataDesc *tdd; 825d1a890faSShreyas Bhatewara 8260d0b1672SMichał Mirosław if (ctx->mss) { /* TSO */ 827d1a890faSShreyas Bhatewara ctx->eth_ip_hdr_size = skb_transport_offset(skb); 8288bca5d1eSEric Dumazet ctx->l4_hdr_size = tcp_hdrlen(skb); 829d1a890faSShreyas Bhatewara ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size; 830d1a890faSShreyas Bhatewara } else { 831d1a890faSShreyas Bhatewara if (skb->ip_summed == CHECKSUM_PARTIAL) { 8320d0b1672SMichał Mirosław ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb); 833d1a890faSShreyas Bhatewara 834d1a890faSShreyas Bhatewara if (ctx->ipv4) { 8358bca5d1eSEric Dumazet const struct iphdr *iph = ip_hdr(skb); 8368bca5d1eSEric Dumazet 83739d4a96fSShreyas Bhatewara if (iph->protocol == IPPROTO_TCP) 8388bca5d1eSEric Dumazet ctx->l4_hdr_size = tcp_hdrlen(skb); 83939d4a96fSShreyas Bhatewara else if (iph->protocol == IPPROTO_UDP) 840f6a1ad42SDavid S. Miller ctx->l4_hdr_size = sizeof(struct udphdr); 84139d4a96fSShreyas Bhatewara else 842d1a890faSShreyas Bhatewara ctx->l4_hdr_size = 0; 843d1a890faSShreyas Bhatewara } else { 844d1a890faSShreyas Bhatewara /* for simplicity, don't copy L4 headers */ 845d1a890faSShreyas Bhatewara ctx->l4_hdr_size = 0; 846d1a890faSShreyas Bhatewara } 847b203262dSNeil Horman ctx->copy_size = min(ctx->eth_ip_hdr_size + 848b203262dSNeil Horman ctx->l4_hdr_size, skb->len); 849d1a890faSShreyas Bhatewara } else { 850d1a890faSShreyas Bhatewara ctx->eth_ip_hdr_size = 0; 851d1a890faSShreyas Bhatewara ctx->l4_hdr_size = 0; 852d1a890faSShreyas Bhatewara /* copy as much as allowed */ 853d1a890faSShreyas Bhatewara ctx->copy_size = min((unsigned int)VMXNET3_HDR_COPY_SIZE 854d1a890faSShreyas Bhatewara , skb_headlen(skb)); 855d1a890faSShreyas Bhatewara } 856d1a890faSShreyas Bhatewara 857d1a890faSShreyas Bhatewara /* make sure headers are accessible directly */ 858d1a890faSShreyas Bhatewara if (unlikely(!pskb_may_pull(skb, ctx->copy_size))) 859d1a890faSShreyas Bhatewara goto err; 860d1a890faSShreyas Bhatewara } 861d1a890faSShreyas Bhatewara 862d1a890faSShreyas Bhatewara if (unlikely(ctx->copy_size > VMXNET3_HDR_COPY_SIZE)) { 863d1a890faSShreyas Bhatewara tq->stats.oversized_hdr++; 864d1a890faSShreyas Bhatewara ctx->copy_size = 0; 865d1a890faSShreyas Bhatewara return 0; 866d1a890faSShreyas Bhatewara } 867d1a890faSShreyas Bhatewara 868d1a890faSShreyas Bhatewara tdd = tq->data_ring.base + tq->tx_ring.next2fill; 869d1a890faSShreyas Bhatewara 870d1a890faSShreyas Bhatewara memcpy(tdd->data, skb->data, ctx->copy_size); 871fdcd79b9SStephen Hemminger netdev_dbg(adapter->netdev, 872f6965582SRandy Dunlap "copy %u bytes to dataRing[%u]\n", 873d1a890faSShreyas Bhatewara ctx->copy_size, tq->tx_ring.next2fill); 874d1a890faSShreyas Bhatewara return 1; 875d1a890faSShreyas Bhatewara 876d1a890faSShreyas Bhatewara err: 877d1a890faSShreyas Bhatewara return -1; 878d1a890faSShreyas Bhatewara } 879d1a890faSShreyas Bhatewara 880d1a890faSShreyas Bhatewara 881d1a890faSShreyas Bhatewara static void 882d1a890faSShreyas Bhatewara vmxnet3_prepare_tso(struct sk_buff *skb, 883d1a890faSShreyas Bhatewara struct vmxnet3_tx_ctx *ctx) 884d1a890faSShreyas Bhatewara { 8858bca5d1eSEric Dumazet struct tcphdr *tcph = tcp_hdr(skb); 8868bca5d1eSEric Dumazet 887d1a890faSShreyas Bhatewara if (ctx->ipv4) { 8888bca5d1eSEric Dumazet struct iphdr *iph = ip_hdr(skb); 8898bca5d1eSEric Dumazet 890d1a890faSShreyas Bhatewara iph->check = 0; 891d1a890faSShreyas Bhatewara tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0, 892d1a890faSShreyas Bhatewara IPPROTO_TCP, 0); 893d1a890faSShreyas Bhatewara } else { 8948bca5d1eSEric Dumazet struct ipv6hdr *iph = ipv6_hdr(skb); 8958bca5d1eSEric Dumazet 896d1a890faSShreyas Bhatewara tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0, 897d1a890faSShreyas Bhatewara IPPROTO_TCP, 0); 898d1a890faSShreyas Bhatewara } 899d1a890faSShreyas Bhatewara } 900d1a890faSShreyas Bhatewara 901a4d7e485SEric Dumazet static int txd_estimate(const struct sk_buff *skb) 902a4d7e485SEric Dumazet { 903a4d7e485SEric Dumazet int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1; 904a4d7e485SEric Dumazet int i; 905a4d7e485SEric Dumazet 906a4d7e485SEric Dumazet for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 907a4d7e485SEric Dumazet const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 908a4d7e485SEric Dumazet 909a4d7e485SEric Dumazet count += VMXNET3_TXD_NEEDED(skb_frag_size(frag)); 910a4d7e485SEric Dumazet } 911a4d7e485SEric Dumazet return count; 912a4d7e485SEric Dumazet } 913d1a890faSShreyas Bhatewara 914d1a890faSShreyas Bhatewara /* 915d1a890faSShreyas Bhatewara * Transmits a pkt thru a given tq 916d1a890faSShreyas Bhatewara * Returns: 917d1a890faSShreyas Bhatewara * NETDEV_TX_OK: descriptors are setup successfully 91825985edcSLucas De Marchi * NETDEV_TX_OK: error occurred, the pkt is dropped 919d1a890faSShreyas Bhatewara * NETDEV_TX_BUSY: tx ring is full, queue is stopped 920d1a890faSShreyas Bhatewara * 921d1a890faSShreyas Bhatewara * Side-effects: 922d1a890faSShreyas Bhatewara * 1. tx ring may be changed 923d1a890faSShreyas Bhatewara * 2. tq stats may be updated accordingly 924d1a890faSShreyas Bhatewara * 3. shared->txNumDeferred may be updated 925d1a890faSShreyas Bhatewara */ 926d1a890faSShreyas Bhatewara 927d1a890faSShreyas Bhatewara static int 928d1a890faSShreyas Bhatewara vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 929d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter, struct net_device *netdev) 930d1a890faSShreyas Bhatewara { 931d1a890faSShreyas Bhatewara int ret; 932d1a890faSShreyas Bhatewara u32 count; 933d1a890faSShreyas Bhatewara unsigned long flags; 934d1a890faSShreyas Bhatewara struct vmxnet3_tx_ctx ctx; 935d1a890faSShreyas Bhatewara union Vmxnet3_GenericDesc *gdesc; 936115924b6SShreyas Bhatewara #ifdef __BIG_ENDIAN_BITFIELD 937115924b6SShreyas Bhatewara /* Use temporary descriptor to avoid touching bits multiple times */ 938115924b6SShreyas Bhatewara union Vmxnet3_GenericDesc tempTxDesc; 939115924b6SShreyas Bhatewara #endif 940d1a890faSShreyas Bhatewara 941a4d7e485SEric Dumazet count = txd_estimate(skb); 942d1a890faSShreyas Bhatewara 94372e85c45SJesse Gross ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP)); 944d1a890faSShreyas Bhatewara 945d1a890faSShreyas Bhatewara ctx.mss = skb_shinfo(skb)->gso_size; 946d1a890faSShreyas Bhatewara if (ctx.mss) { 947d1a890faSShreyas Bhatewara if (skb_header_cloned(skb)) { 948d1a890faSShreyas Bhatewara if (unlikely(pskb_expand_head(skb, 0, 0, 949d1a890faSShreyas Bhatewara GFP_ATOMIC) != 0)) { 950d1a890faSShreyas Bhatewara tq->stats.drop_tso++; 951d1a890faSShreyas Bhatewara goto drop_pkt; 952d1a890faSShreyas Bhatewara } 953d1a890faSShreyas Bhatewara tq->stats.copy_skb_header++; 954d1a890faSShreyas Bhatewara } 955d1a890faSShreyas Bhatewara vmxnet3_prepare_tso(skb, &ctx); 956d1a890faSShreyas Bhatewara } else { 957d1a890faSShreyas Bhatewara if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) { 958d1a890faSShreyas Bhatewara 959d1a890faSShreyas Bhatewara /* non-tso pkts must not use more than 960d1a890faSShreyas Bhatewara * VMXNET3_MAX_TXD_PER_PKT entries 961d1a890faSShreyas Bhatewara */ 962d1a890faSShreyas Bhatewara if (skb_linearize(skb) != 0) { 963d1a890faSShreyas Bhatewara tq->stats.drop_too_many_frags++; 964d1a890faSShreyas Bhatewara goto drop_pkt; 965d1a890faSShreyas Bhatewara } 966d1a890faSShreyas Bhatewara tq->stats.linearized++; 967d1a890faSShreyas Bhatewara 968d1a890faSShreyas Bhatewara /* recalculate the # of descriptors to use */ 969d1a890faSShreyas Bhatewara count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1; 970d1a890faSShreyas Bhatewara } 971d1a890faSShreyas Bhatewara } 972d1a890faSShreyas Bhatewara 97309c5088eSShreyas Bhatewara spin_lock_irqsave(&tq->tx_lock, flags); 97409c5088eSShreyas Bhatewara 97509c5088eSShreyas Bhatewara if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) { 97609c5088eSShreyas Bhatewara tq->stats.tx_ring_full++; 977fdcd79b9SStephen Hemminger netdev_dbg(adapter->netdev, 97809c5088eSShreyas Bhatewara "tx queue stopped on %s, next2comp %u" 97909c5088eSShreyas Bhatewara " next2fill %u\n", adapter->netdev->name, 98009c5088eSShreyas Bhatewara tq->tx_ring.next2comp, tq->tx_ring.next2fill); 98109c5088eSShreyas Bhatewara 98209c5088eSShreyas Bhatewara vmxnet3_tq_stop(tq, adapter); 98309c5088eSShreyas Bhatewara spin_unlock_irqrestore(&tq->tx_lock, flags); 98409c5088eSShreyas Bhatewara return NETDEV_TX_BUSY; 98509c5088eSShreyas Bhatewara } 98609c5088eSShreyas Bhatewara 98709c5088eSShreyas Bhatewara 988d1a890faSShreyas Bhatewara ret = vmxnet3_parse_and_copy_hdr(skb, tq, &ctx, adapter); 989d1a890faSShreyas Bhatewara if (ret >= 0) { 990d1a890faSShreyas Bhatewara BUG_ON(ret <= 0 && ctx.copy_size != 0); 991d1a890faSShreyas Bhatewara /* hdrs parsed, check against other limits */ 992d1a890faSShreyas Bhatewara if (ctx.mss) { 993d1a890faSShreyas Bhatewara if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size > 994d1a890faSShreyas Bhatewara VMXNET3_MAX_TX_BUF_SIZE)) { 995d1a890faSShreyas Bhatewara goto hdr_too_big; 996d1a890faSShreyas Bhatewara } 997d1a890faSShreyas Bhatewara } else { 998d1a890faSShreyas Bhatewara if (skb->ip_summed == CHECKSUM_PARTIAL) { 999d1a890faSShreyas Bhatewara if (unlikely(ctx.eth_ip_hdr_size + 1000d1a890faSShreyas Bhatewara skb->csum_offset > 1001d1a890faSShreyas Bhatewara VMXNET3_MAX_CSUM_OFFSET)) { 1002d1a890faSShreyas Bhatewara goto hdr_too_big; 1003d1a890faSShreyas Bhatewara } 1004d1a890faSShreyas Bhatewara } 1005d1a890faSShreyas Bhatewara } 1006d1a890faSShreyas Bhatewara } else { 1007d1a890faSShreyas Bhatewara tq->stats.drop_hdr_inspect_err++; 1008f955e141SDan Carpenter goto unlock_drop_pkt; 1009d1a890faSShreyas Bhatewara } 1010d1a890faSShreyas Bhatewara 1011d1a890faSShreyas Bhatewara /* fill tx descs related to addr & len */ 1012d1a890faSShreyas Bhatewara vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter); 1013d1a890faSShreyas Bhatewara 1014d1a890faSShreyas Bhatewara /* setup the EOP desc */ 1015115924b6SShreyas Bhatewara ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP); 1016d1a890faSShreyas Bhatewara 1017d1a890faSShreyas Bhatewara /* setup the SOP desc */ 1018115924b6SShreyas Bhatewara #ifdef __BIG_ENDIAN_BITFIELD 1019115924b6SShreyas Bhatewara gdesc = &tempTxDesc; 1020115924b6SShreyas Bhatewara gdesc->dword[2] = ctx.sop_txd->dword[2]; 1021115924b6SShreyas Bhatewara gdesc->dword[3] = ctx.sop_txd->dword[3]; 1022115924b6SShreyas Bhatewara #else 1023d1a890faSShreyas Bhatewara gdesc = ctx.sop_txd; 1024115924b6SShreyas Bhatewara #endif 1025d1a890faSShreyas Bhatewara if (ctx.mss) { 1026d1a890faSShreyas Bhatewara gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size; 1027d1a890faSShreyas Bhatewara gdesc->txd.om = VMXNET3_OM_TSO; 1028d1a890faSShreyas Bhatewara gdesc->txd.msscof = ctx.mss; 1029115924b6SShreyas Bhatewara le32_add_cpu(&tq->shared->txNumDeferred, (skb->len - 1030115924b6SShreyas Bhatewara gdesc->txd.hlen + ctx.mss - 1) / ctx.mss); 1031d1a890faSShreyas Bhatewara } else { 1032d1a890faSShreyas Bhatewara if (skb->ip_summed == CHECKSUM_PARTIAL) { 1033d1a890faSShreyas Bhatewara gdesc->txd.hlen = ctx.eth_ip_hdr_size; 1034d1a890faSShreyas Bhatewara gdesc->txd.om = VMXNET3_OM_CSUM; 1035d1a890faSShreyas Bhatewara gdesc->txd.msscof = ctx.eth_ip_hdr_size + 1036d1a890faSShreyas Bhatewara skb->csum_offset; 1037d1a890faSShreyas Bhatewara } else { 1038d1a890faSShreyas Bhatewara gdesc->txd.om = 0; 1039d1a890faSShreyas Bhatewara gdesc->txd.msscof = 0; 1040d1a890faSShreyas Bhatewara } 1041115924b6SShreyas Bhatewara le32_add_cpu(&tq->shared->txNumDeferred, 1); 1042d1a890faSShreyas Bhatewara } 1043d1a890faSShreyas Bhatewara 1044d1a890faSShreyas Bhatewara if (vlan_tx_tag_present(skb)) { 1045d1a890faSShreyas Bhatewara gdesc->txd.ti = 1; 1046d1a890faSShreyas Bhatewara gdesc->txd.tci = vlan_tx_tag_get(skb); 1047d1a890faSShreyas Bhatewara } 1048d1a890faSShreyas Bhatewara 1049115924b6SShreyas Bhatewara /* finally flips the GEN bit of the SOP desc. */ 1050115924b6SShreyas Bhatewara gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^ 1051115924b6SShreyas Bhatewara VMXNET3_TXD_GEN); 1052115924b6SShreyas Bhatewara #ifdef __BIG_ENDIAN_BITFIELD 1053115924b6SShreyas Bhatewara /* Finished updating in bitfields of Tx Desc, so write them in original 1054115924b6SShreyas Bhatewara * place. 1055115924b6SShreyas Bhatewara */ 1056115924b6SShreyas Bhatewara vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc, 1057115924b6SShreyas Bhatewara (struct Vmxnet3_TxDesc *)ctx.sop_txd); 1058115924b6SShreyas Bhatewara gdesc = ctx.sop_txd; 1059115924b6SShreyas Bhatewara #endif 1060fdcd79b9SStephen Hemminger netdev_dbg(adapter->netdev, 1061f6965582SRandy Dunlap "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n", 1062c2fd03a0SJoe Perches (u32)(ctx.sop_txd - 1063115924b6SShreyas Bhatewara tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr), 1064115924b6SShreyas Bhatewara le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3])); 1065d1a890faSShreyas Bhatewara 1066d1a890faSShreyas Bhatewara spin_unlock_irqrestore(&tq->tx_lock, flags); 1067d1a890faSShreyas Bhatewara 1068115924b6SShreyas Bhatewara if (le32_to_cpu(tq->shared->txNumDeferred) >= 1069115924b6SShreyas Bhatewara le32_to_cpu(tq->shared->txThreshold)) { 1070d1a890faSShreyas Bhatewara tq->shared->txNumDeferred = 0; 107109c5088eSShreyas Bhatewara VMXNET3_WRITE_BAR0_REG(adapter, 107209c5088eSShreyas Bhatewara VMXNET3_REG_TXPROD + tq->qid * 8, 1073d1a890faSShreyas Bhatewara tq->tx_ring.next2fill); 1074d1a890faSShreyas Bhatewara } 1075d1a890faSShreyas Bhatewara 1076d1a890faSShreyas Bhatewara return NETDEV_TX_OK; 1077d1a890faSShreyas Bhatewara 1078d1a890faSShreyas Bhatewara hdr_too_big: 1079d1a890faSShreyas Bhatewara tq->stats.drop_oversized_hdr++; 1080f955e141SDan Carpenter unlock_drop_pkt: 1081f955e141SDan Carpenter spin_unlock_irqrestore(&tq->tx_lock, flags); 1082d1a890faSShreyas Bhatewara drop_pkt: 1083d1a890faSShreyas Bhatewara tq->stats.drop_total++; 1084d1a890faSShreyas Bhatewara dev_kfree_skb(skb); 1085d1a890faSShreyas Bhatewara return NETDEV_TX_OK; 1086d1a890faSShreyas Bhatewara } 1087d1a890faSShreyas Bhatewara 1088d1a890faSShreyas Bhatewara 1089d1a890faSShreyas Bhatewara static netdev_tx_t 1090d1a890faSShreyas Bhatewara vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 1091d1a890faSShreyas Bhatewara { 1092d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1093d1a890faSShreyas Bhatewara 109409c5088eSShreyas Bhatewara BUG_ON(skb->queue_mapping > adapter->num_tx_queues); 109509c5088eSShreyas Bhatewara return vmxnet3_tq_xmit(skb, 109609c5088eSShreyas Bhatewara &adapter->tx_queue[skb->queue_mapping], 109709c5088eSShreyas Bhatewara adapter, netdev); 1098d1a890faSShreyas Bhatewara } 1099d1a890faSShreyas Bhatewara 1100d1a890faSShreyas Bhatewara 1101d1a890faSShreyas Bhatewara static void 1102d1a890faSShreyas Bhatewara vmxnet3_rx_csum(struct vmxnet3_adapter *adapter, 1103d1a890faSShreyas Bhatewara struct sk_buff *skb, 1104d1a890faSShreyas Bhatewara union Vmxnet3_GenericDesc *gdesc) 1105d1a890faSShreyas Bhatewara { 1106a0d2730cSMichał Mirosław if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) { 1107d1a890faSShreyas Bhatewara /* typical case: TCP/UDP over IP and both csums are correct */ 1108115924b6SShreyas Bhatewara if ((le32_to_cpu(gdesc->dword[3]) & VMXNET3_RCD_CSUM_OK) == 1109d1a890faSShreyas Bhatewara VMXNET3_RCD_CSUM_OK) { 1110d1a890faSShreyas Bhatewara skb->ip_summed = CHECKSUM_UNNECESSARY; 1111d1a890faSShreyas Bhatewara BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp)); 1112d1a890faSShreyas Bhatewara BUG_ON(!(gdesc->rcd.v4 || gdesc->rcd.v6)); 1113d1a890faSShreyas Bhatewara BUG_ON(gdesc->rcd.frg); 1114d1a890faSShreyas Bhatewara } else { 1115d1a890faSShreyas Bhatewara if (gdesc->rcd.csum) { 1116d1a890faSShreyas Bhatewara skb->csum = htons(gdesc->rcd.csum); 1117d1a890faSShreyas Bhatewara skb->ip_summed = CHECKSUM_PARTIAL; 1118d1a890faSShreyas Bhatewara } else { 1119bc8acf2cSEric Dumazet skb_checksum_none_assert(skb); 1120d1a890faSShreyas Bhatewara } 1121d1a890faSShreyas Bhatewara } 1122d1a890faSShreyas Bhatewara } else { 1123bc8acf2cSEric Dumazet skb_checksum_none_assert(skb); 1124d1a890faSShreyas Bhatewara } 1125d1a890faSShreyas Bhatewara } 1126d1a890faSShreyas Bhatewara 1127d1a890faSShreyas Bhatewara 1128d1a890faSShreyas Bhatewara static void 1129d1a890faSShreyas Bhatewara vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd, 1130d1a890faSShreyas Bhatewara struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter) 1131d1a890faSShreyas Bhatewara { 1132d1a890faSShreyas Bhatewara rq->stats.drop_err++; 1133d1a890faSShreyas Bhatewara if (!rcd->fcs) 1134d1a890faSShreyas Bhatewara rq->stats.drop_fcs++; 1135d1a890faSShreyas Bhatewara 1136d1a890faSShreyas Bhatewara rq->stats.drop_total++; 1137d1a890faSShreyas Bhatewara 1138d1a890faSShreyas Bhatewara /* 1139d1a890faSShreyas Bhatewara * We do not unmap and chain the rx buffer to the skb. 1140d1a890faSShreyas Bhatewara * We basically pretend this buffer is not used and will be recycled 1141d1a890faSShreyas Bhatewara * by vmxnet3_rq_alloc_rx_buf() 1142d1a890faSShreyas Bhatewara */ 1143d1a890faSShreyas Bhatewara 1144d1a890faSShreyas Bhatewara /* 1145d1a890faSShreyas Bhatewara * ctx->skb may be NULL if this is the first and the only one 1146d1a890faSShreyas Bhatewara * desc for the pkt 1147d1a890faSShreyas Bhatewara */ 1148d1a890faSShreyas Bhatewara if (ctx->skb) 1149d1a890faSShreyas Bhatewara dev_kfree_skb_irq(ctx->skb); 1150d1a890faSShreyas Bhatewara 1151d1a890faSShreyas Bhatewara ctx->skb = NULL; 1152d1a890faSShreyas Bhatewara } 1153d1a890faSShreyas Bhatewara 1154d1a890faSShreyas Bhatewara 1155d1a890faSShreyas Bhatewara static int 1156d1a890faSShreyas Bhatewara vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq, 1157d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter, int quota) 1158d1a890faSShreyas Bhatewara { 1159215faf9cSJoe Perches static const u32 rxprod_reg[2] = { 1160215faf9cSJoe Perches VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2 1161215faf9cSJoe Perches }; 1162d1a890faSShreyas Bhatewara u32 num_rxd = 0; 11635318d809SShreyas Bhatewara bool skip_page_frags = false; 1164d1a890faSShreyas Bhatewara struct Vmxnet3_RxCompDesc *rcd; 1165d1a890faSShreyas Bhatewara struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx; 1166115924b6SShreyas Bhatewara #ifdef __BIG_ENDIAN_BITFIELD 1167115924b6SShreyas Bhatewara struct Vmxnet3_RxDesc rxCmdDesc; 1168115924b6SShreyas Bhatewara struct Vmxnet3_RxCompDesc rxComp; 1169115924b6SShreyas Bhatewara #endif 1170115924b6SShreyas Bhatewara vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, 1171115924b6SShreyas Bhatewara &rxComp); 1172d1a890faSShreyas Bhatewara while (rcd->gen == rq->comp_ring.gen) { 1173d1a890faSShreyas Bhatewara struct vmxnet3_rx_buf_info *rbi; 11745318d809SShreyas Bhatewara struct sk_buff *skb, *new_skb = NULL; 11755318d809SShreyas Bhatewara struct page *new_page = NULL; 1176d1a890faSShreyas Bhatewara int num_to_alloc; 1177d1a890faSShreyas Bhatewara struct Vmxnet3_RxDesc *rxd; 1178d1a890faSShreyas Bhatewara u32 idx, ring_idx; 11795318d809SShreyas Bhatewara struct vmxnet3_cmd_ring *ring = NULL; 1180d1a890faSShreyas Bhatewara if (num_rxd >= quota) { 1181d1a890faSShreyas Bhatewara /* we may stop even before we see the EOP desc of 1182d1a890faSShreyas Bhatewara * the current pkt 1183d1a890faSShreyas Bhatewara */ 1184d1a890faSShreyas Bhatewara break; 1185d1a890faSShreyas Bhatewara } 1186d1a890faSShreyas Bhatewara num_rxd++; 118709c5088eSShreyas Bhatewara BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2); 1188d1a890faSShreyas Bhatewara idx = rcd->rxdIdx; 118909c5088eSShreyas Bhatewara ring_idx = rcd->rqID < adapter->num_rx_queues ? 0 : 1; 11905318d809SShreyas Bhatewara ring = rq->rx_ring + ring_idx; 1191115924b6SShreyas Bhatewara vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd, 1192115924b6SShreyas Bhatewara &rxCmdDesc); 1193d1a890faSShreyas Bhatewara rbi = rq->buf_info[ring_idx] + idx; 1194d1a890faSShreyas Bhatewara 1195115924b6SShreyas Bhatewara BUG_ON(rxd->addr != rbi->dma_addr || 1196115924b6SShreyas Bhatewara rxd->len != rbi->len); 1197d1a890faSShreyas Bhatewara 1198d1a890faSShreyas Bhatewara if (unlikely(rcd->eop && rcd->err)) { 1199d1a890faSShreyas Bhatewara vmxnet3_rx_error(rq, rcd, ctx, adapter); 1200d1a890faSShreyas Bhatewara goto rcd_done; 1201d1a890faSShreyas Bhatewara } 1202d1a890faSShreyas Bhatewara 1203d1a890faSShreyas Bhatewara if (rcd->sop) { /* first buf of the pkt */ 1204d1a890faSShreyas Bhatewara BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD || 1205d1a890faSShreyas Bhatewara rcd->rqID != rq->qid); 1206d1a890faSShreyas Bhatewara 1207d1a890faSShreyas Bhatewara BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB); 1208d1a890faSShreyas Bhatewara BUG_ON(ctx->skb != NULL || rbi->skb == NULL); 1209d1a890faSShreyas Bhatewara 1210d1a890faSShreyas Bhatewara if (unlikely(rcd->len == 0)) { 1211d1a890faSShreyas Bhatewara /* Pretend the rx buffer is skipped. */ 1212d1a890faSShreyas Bhatewara BUG_ON(!(rcd->sop && rcd->eop)); 1213fdcd79b9SStephen Hemminger netdev_dbg(adapter->netdev, 1214f6965582SRandy Dunlap "rxRing[%u][%u] 0 length\n", 1215d1a890faSShreyas Bhatewara ring_idx, idx); 1216d1a890faSShreyas Bhatewara goto rcd_done; 1217d1a890faSShreyas Bhatewara } 1218d1a890faSShreyas Bhatewara 12195318d809SShreyas Bhatewara skip_page_frags = false; 1220d1a890faSShreyas Bhatewara ctx->skb = rbi->skb; 12210d735f13SStephen Hemminger new_skb = netdev_alloc_skb_ip_align(adapter->netdev, 12220d735f13SStephen Hemminger rbi->len); 12235318d809SShreyas Bhatewara if (new_skb == NULL) { 12245318d809SShreyas Bhatewara /* Skb allocation failed, do not handover this 12255318d809SShreyas Bhatewara * skb to stack. Reuse it. Drop the existing pkt 12265318d809SShreyas Bhatewara */ 12275318d809SShreyas Bhatewara rq->stats.rx_buf_alloc_failure++; 12285318d809SShreyas Bhatewara ctx->skb = NULL; 12295318d809SShreyas Bhatewara rq->stats.drop_total++; 12305318d809SShreyas Bhatewara skip_page_frags = true; 12315318d809SShreyas Bhatewara goto rcd_done; 12325318d809SShreyas Bhatewara } 1233d1a890faSShreyas Bhatewara 1234d1a890faSShreyas Bhatewara pci_unmap_single(adapter->pdev, rbi->dma_addr, rbi->len, 1235d1a890faSShreyas Bhatewara PCI_DMA_FROMDEVICE); 1236d1a890faSShreyas Bhatewara 1237d1a890faSShreyas Bhatewara skb_put(ctx->skb, rcd->len); 12385318d809SShreyas Bhatewara 12395318d809SShreyas Bhatewara /* Immediate refill */ 12405318d809SShreyas Bhatewara rbi->skb = new_skb; 12415318d809SShreyas Bhatewara rbi->dma_addr = pci_map_single(adapter->pdev, 12425318d809SShreyas Bhatewara rbi->skb->data, rbi->len, 12435318d809SShreyas Bhatewara PCI_DMA_FROMDEVICE); 12445318d809SShreyas Bhatewara rxd->addr = cpu_to_le64(rbi->dma_addr); 12455318d809SShreyas Bhatewara rxd->len = rbi->len; 12465318d809SShreyas Bhatewara 1247d1a890faSShreyas Bhatewara } else { 12485318d809SShreyas Bhatewara BUG_ON(ctx->skb == NULL && !skip_page_frags); 12495318d809SShreyas Bhatewara 1250d1a890faSShreyas Bhatewara /* non SOP buffer must be type 1 in most cases */ 12515318d809SShreyas Bhatewara BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE); 1252d1a890faSShreyas Bhatewara BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY); 1253d1a890faSShreyas Bhatewara 12545318d809SShreyas Bhatewara /* If an sop buffer was dropped, skip all 12555318d809SShreyas Bhatewara * following non-sop fragments. They will be reused. 12565318d809SShreyas Bhatewara */ 12575318d809SShreyas Bhatewara if (skip_page_frags) 12585318d809SShreyas Bhatewara goto rcd_done; 12595318d809SShreyas Bhatewara 12605318d809SShreyas Bhatewara new_page = alloc_page(GFP_ATOMIC); 12615318d809SShreyas Bhatewara if (unlikely(new_page == NULL)) { 12625318d809SShreyas Bhatewara /* Replacement page frag could not be allocated. 12635318d809SShreyas Bhatewara * Reuse this page. Drop the pkt and free the 12645318d809SShreyas Bhatewara * skb which contained this page as a frag. Skip 12655318d809SShreyas Bhatewara * processing all the following non-sop frags. 12665318d809SShreyas Bhatewara */ 12675318d809SShreyas Bhatewara rq->stats.rx_buf_alloc_failure++; 12685318d809SShreyas Bhatewara dev_kfree_skb(ctx->skb); 12695318d809SShreyas Bhatewara ctx->skb = NULL; 12705318d809SShreyas Bhatewara skip_page_frags = true; 12715318d809SShreyas Bhatewara goto rcd_done; 12725318d809SShreyas Bhatewara } 12735318d809SShreyas Bhatewara 1274d1a890faSShreyas Bhatewara if (rcd->len) { 1275d1a890faSShreyas Bhatewara pci_unmap_page(adapter->pdev, 1276d1a890faSShreyas Bhatewara rbi->dma_addr, rbi->len, 1277d1a890faSShreyas Bhatewara PCI_DMA_FROMDEVICE); 1278d1a890faSShreyas Bhatewara 1279d1a890faSShreyas Bhatewara vmxnet3_append_frag(ctx->skb, rcd, rbi); 1280d1a890faSShreyas Bhatewara } 12815318d809SShreyas Bhatewara 12825318d809SShreyas Bhatewara /* Immediate refill */ 12835318d809SShreyas Bhatewara rbi->page = new_page; 12845318d809SShreyas Bhatewara rbi->dma_addr = pci_map_page(adapter->pdev, rbi->page, 12855318d809SShreyas Bhatewara 0, PAGE_SIZE, 12865318d809SShreyas Bhatewara PCI_DMA_FROMDEVICE); 12875318d809SShreyas Bhatewara rxd->addr = cpu_to_le64(rbi->dma_addr); 12885318d809SShreyas Bhatewara rxd->len = rbi->len; 1289d1a890faSShreyas Bhatewara } 12905318d809SShreyas Bhatewara 1291d1a890faSShreyas Bhatewara 1292d1a890faSShreyas Bhatewara skb = ctx->skb; 1293d1a890faSShreyas Bhatewara if (rcd->eop) { 1294d1a890faSShreyas Bhatewara skb->len += skb->data_len; 1295d1a890faSShreyas Bhatewara 1296d1a890faSShreyas Bhatewara vmxnet3_rx_csum(adapter, skb, 1297d1a890faSShreyas Bhatewara (union Vmxnet3_GenericDesc *)rcd); 1298d1a890faSShreyas Bhatewara skb->protocol = eth_type_trans(skb, adapter->netdev); 1299d1a890faSShreyas Bhatewara 130072e85c45SJesse Gross if (unlikely(rcd->ts)) 130172e85c45SJesse Gross __vlan_hwaccel_put_tag(skb, rcd->tci); 130272e85c45SJesse Gross 1303213ade8cSJesse Gross if (adapter->netdev->features & NETIF_F_LRO) 1304d1a890faSShreyas Bhatewara netif_receive_skb(skb); 1305213ade8cSJesse Gross else 1306213ade8cSJesse Gross napi_gro_receive(&rq->napi, skb); 1307d1a890faSShreyas Bhatewara 1308d1a890faSShreyas Bhatewara ctx->skb = NULL; 1309d1a890faSShreyas Bhatewara } 1310d1a890faSShreyas Bhatewara 1311d1a890faSShreyas Bhatewara rcd_done: 13125318d809SShreyas Bhatewara /* device may have skipped some rx descs */ 13135318d809SShreyas Bhatewara ring->next2comp = idx; 13145318d809SShreyas Bhatewara num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring); 13155318d809SShreyas Bhatewara ring = rq->rx_ring + ring_idx; 13165318d809SShreyas Bhatewara while (num_to_alloc) { 13175318d809SShreyas Bhatewara vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd, 13185318d809SShreyas Bhatewara &rxCmdDesc); 13195318d809SShreyas Bhatewara BUG_ON(!rxd->addr); 1320d1a890faSShreyas Bhatewara 13215318d809SShreyas Bhatewara /* Recv desc is ready to be used by the device */ 13225318d809SShreyas Bhatewara rxd->gen = ring->gen; 13235318d809SShreyas Bhatewara vmxnet3_cmd_ring_adv_next2fill(ring); 13245318d809SShreyas Bhatewara num_to_alloc--; 13255318d809SShreyas Bhatewara } 1326d1a890faSShreyas Bhatewara 1327d1a890faSShreyas Bhatewara /* if needed, update the register */ 1328d1a890faSShreyas Bhatewara if (unlikely(rq->shared->updateRxProd)) { 1329d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR0_REG(adapter, 1330d1a890faSShreyas Bhatewara rxprod_reg[ring_idx] + rq->qid * 8, 13315318d809SShreyas Bhatewara ring->next2fill); 1332d1a890faSShreyas Bhatewara } 1333d1a890faSShreyas Bhatewara 1334d1a890faSShreyas Bhatewara vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring); 1335115924b6SShreyas Bhatewara vmxnet3_getRxComp(rcd, 1336115924b6SShreyas Bhatewara &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp); 1337d1a890faSShreyas Bhatewara } 1338d1a890faSShreyas Bhatewara 1339d1a890faSShreyas Bhatewara return num_rxd; 1340d1a890faSShreyas Bhatewara } 1341d1a890faSShreyas Bhatewara 1342d1a890faSShreyas Bhatewara 1343d1a890faSShreyas Bhatewara static void 1344d1a890faSShreyas Bhatewara vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq, 1345d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 1346d1a890faSShreyas Bhatewara { 1347d1a890faSShreyas Bhatewara u32 i, ring_idx; 1348d1a890faSShreyas Bhatewara struct Vmxnet3_RxDesc *rxd; 1349d1a890faSShreyas Bhatewara 1350d1a890faSShreyas Bhatewara for (ring_idx = 0; ring_idx < 2; ring_idx++) { 1351d1a890faSShreyas Bhatewara for (i = 0; i < rq->rx_ring[ring_idx].size; i++) { 1352115924b6SShreyas Bhatewara #ifdef __BIG_ENDIAN_BITFIELD 1353115924b6SShreyas Bhatewara struct Vmxnet3_RxDesc rxDesc; 1354115924b6SShreyas Bhatewara #endif 1355115924b6SShreyas Bhatewara vmxnet3_getRxDesc(rxd, 1356115924b6SShreyas Bhatewara &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc); 1357d1a890faSShreyas Bhatewara 1358d1a890faSShreyas Bhatewara if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD && 1359d1a890faSShreyas Bhatewara rq->buf_info[ring_idx][i].skb) { 1360d1a890faSShreyas Bhatewara pci_unmap_single(adapter->pdev, rxd->addr, 1361d1a890faSShreyas Bhatewara rxd->len, PCI_DMA_FROMDEVICE); 1362d1a890faSShreyas Bhatewara dev_kfree_skb(rq->buf_info[ring_idx][i].skb); 1363d1a890faSShreyas Bhatewara rq->buf_info[ring_idx][i].skb = NULL; 1364d1a890faSShreyas Bhatewara } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY && 1365d1a890faSShreyas Bhatewara rq->buf_info[ring_idx][i].page) { 1366d1a890faSShreyas Bhatewara pci_unmap_page(adapter->pdev, rxd->addr, 1367d1a890faSShreyas Bhatewara rxd->len, PCI_DMA_FROMDEVICE); 1368d1a890faSShreyas Bhatewara put_page(rq->buf_info[ring_idx][i].page); 1369d1a890faSShreyas Bhatewara rq->buf_info[ring_idx][i].page = NULL; 1370d1a890faSShreyas Bhatewara } 1371d1a890faSShreyas Bhatewara } 1372d1a890faSShreyas Bhatewara 1373d1a890faSShreyas Bhatewara rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN; 1374d1a890faSShreyas Bhatewara rq->rx_ring[ring_idx].next2fill = 1375d1a890faSShreyas Bhatewara rq->rx_ring[ring_idx].next2comp = 0; 1376d1a890faSShreyas Bhatewara } 1377d1a890faSShreyas Bhatewara 1378d1a890faSShreyas Bhatewara rq->comp_ring.gen = VMXNET3_INIT_GEN; 1379d1a890faSShreyas Bhatewara rq->comp_ring.next2proc = 0; 1380d1a890faSShreyas Bhatewara } 1381d1a890faSShreyas Bhatewara 1382d1a890faSShreyas Bhatewara 138309c5088eSShreyas Bhatewara static void 138409c5088eSShreyas Bhatewara vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter) 138509c5088eSShreyas Bhatewara { 138609c5088eSShreyas Bhatewara int i; 138709c5088eSShreyas Bhatewara 138809c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) 138909c5088eSShreyas Bhatewara vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter); 139009c5088eSShreyas Bhatewara } 139109c5088eSShreyas Bhatewara 139209c5088eSShreyas Bhatewara 1393d1a890faSShreyas Bhatewara void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq, 1394d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 1395d1a890faSShreyas Bhatewara { 1396d1a890faSShreyas Bhatewara int i; 1397d1a890faSShreyas Bhatewara int j; 1398d1a890faSShreyas Bhatewara 1399d1a890faSShreyas Bhatewara /* all rx buffers must have already been freed */ 1400d1a890faSShreyas Bhatewara for (i = 0; i < 2; i++) { 1401d1a890faSShreyas Bhatewara if (rq->buf_info[i]) { 1402d1a890faSShreyas Bhatewara for (j = 0; j < rq->rx_ring[i].size; j++) 1403d1a890faSShreyas Bhatewara BUG_ON(rq->buf_info[i][j].page != NULL); 1404d1a890faSShreyas Bhatewara } 1405d1a890faSShreyas Bhatewara } 1406d1a890faSShreyas Bhatewara 1407d1a890faSShreyas Bhatewara 1408d1a890faSShreyas Bhatewara kfree(rq->buf_info[0]); 1409d1a890faSShreyas Bhatewara 1410d1a890faSShreyas Bhatewara for (i = 0; i < 2; i++) { 1411d1a890faSShreyas Bhatewara if (rq->rx_ring[i].base) { 1412d1a890faSShreyas Bhatewara pci_free_consistent(adapter->pdev, rq->rx_ring[i].size 1413d1a890faSShreyas Bhatewara * sizeof(struct Vmxnet3_RxDesc), 1414d1a890faSShreyas Bhatewara rq->rx_ring[i].base, 1415d1a890faSShreyas Bhatewara rq->rx_ring[i].basePA); 1416d1a890faSShreyas Bhatewara rq->rx_ring[i].base = NULL; 1417d1a890faSShreyas Bhatewara } 1418d1a890faSShreyas Bhatewara rq->buf_info[i] = NULL; 1419d1a890faSShreyas Bhatewara } 1420d1a890faSShreyas Bhatewara 1421d1a890faSShreyas Bhatewara if (rq->comp_ring.base) { 1422d1a890faSShreyas Bhatewara pci_free_consistent(adapter->pdev, rq->comp_ring.size * 1423d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_RxCompDesc), 1424d1a890faSShreyas Bhatewara rq->comp_ring.base, rq->comp_ring.basePA); 1425d1a890faSShreyas Bhatewara rq->comp_ring.base = NULL; 1426d1a890faSShreyas Bhatewara } 1427d1a890faSShreyas Bhatewara } 1428d1a890faSShreyas Bhatewara 1429d1a890faSShreyas Bhatewara 1430d1a890faSShreyas Bhatewara static int 1431d1a890faSShreyas Bhatewara vmxnet3_rq_init(struct vmxnet3_rx_queue *rq, 1432d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 1433d1a890faSShreyas Bhatewara { 1434d1a890faSShreyas Bhatewara int i; 1435d1a890faSShreyas Bhatewara 1436d1a890faSShreyas Bhatewara /* initialize buf_info */ 1437d1a890faSShreyas Bhatewara for (i = 0; i < rq->rx_ring[0].size; i++) { 1438d1a890faSShreyas Bhatewara 1439d1a890faSShreyas Bhatewara /* 1st buf for a pkt is skbuff */ 1440d1a890faSShreyas Bhatewara if (i % adapter->rx_buf_per_pkt == 0) { 1441d1a890faSShreyas Bhatewara rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB; 1442d1a890faSShreyas Bhatewara rq->buf_info[0][i].len = adapter->skb_buf_size; 1443d1a890faSShreyas Bhatewara } else { /* subsequent bufs for a pkt is frag */ 1444d1a890faSShreyas Bhatewara rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE; 1445d1a890faSShreyas Bhatewara rq->buf_info[0][i].len = PAGE_SIZE; 1446d1a890faSShreyas Bhatewara } 1447d1a890faSShreyas Bhatewara } 1448d1a890faSShreyas Bhatewara for (i = 0; i < rq->rx_ring[1].size; i++) { 1449d1a890faSShreyas Bhatewara rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE; 1450d1a890faSShreyas Bhatewara rq->buf_info[1][i].len = PAGE_SIZE; 1451d1a890faSShreyas Bhatewara } 1452d1a890faSShreyas Bhatewara 1453d1a890faSShreyas Bhatewara /* reset internal state and allocate buffers for both rings */ 1454d1a890faSShreyas Bhatewara for (i = 0; i < 2; i++) { 1455d1a890faSShreyas Bhatewara rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0; 1456d1a890faSShreyas Bhatewara 1457d1a890faSShreyas Bhatewara memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size * 1458d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_RxDesc)); 1459d1a890faSShreyas Bhatewara rq->rx_ring[i].gen = VMXNET3_INIT_GEN; 1460d1a890faSShreyas Bhatewara } 1461d1a890faSShreyas Bhatewara if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1, 1462d1a890faSShreyas Bhatewara adapter) == 0) { 1463d1a890faSShreyas Bhatewara /* at least has 1 rx buffer for the 1st ring */ 1464d1a890faSShreyas Bhatewara return -ENOMEM; 1465d1a890faSShreyas Bhatewara } 1466d1a890faSShreyas Bhatewara vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter); 1467d1a890faSShreyas Bhatewara 1468d1a890faSShreyas Bhatewara /* reset the comp ring */ 1469d1a890faSShreyas Bhatewara rq->comp_ring.next2proc = 0; 1470d1a890faSShreyas Bhatewara memset(rq->comp_ring.base, 0, rq->comp_ring.size * 1471d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_RxCompDesc)); 1472d1a890faSShreyas Bhatewara rq->comp_ring.gen = VMXNET3_INIT_GEN; 1473d1a890faSShreyas Bhatewara 1474d1a890faSShreyas Bhatewara /* reset rxctx */ 1475d1a890faSShreyas Bhatewara rq->rx_ctx.skb = NULL; 1476d1a890faSShreyas Bhatewara 1477d1a890faSShreyas Bhatewara /* stats are not reset */ 1478d1a890faSShreyas Bhatewara return 0; 1479d1a890faSShreyas Bhatewara } 1480d1a890faSShreyas Bhatewara 1481d1a890faSShreyas Bhatewara 1482d1a890faSShreyas Bhatewara static int 148309c5088eSShreyas Bhatewara vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter) 148409c5088eSShreyas Bhatewara { 148509c5088eSShreyas Bhatewara int i, err = 0; 148609c5088eSShreyas Bhatewara 148709c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 148809c5088eSShreyas Bhatewara err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter); 148909c5088eSShreyas Bhatewara if (unlikely(err)) { 149009c5088eSShreyas Bhatewara dev_err(&adapter->netdev->dev, "%s: failed to " 149109c5088eSShreyas Bhatewara "initialize rx queue%i\n", 149209c5088eSShreyas Bhatewara adapter->netdev->name, i); 149309c5088eSShreyas Bhatewara break; 149409c5088eSShreyas Bhatewara } 149509c5088eSShreyas Bhatewara } 149609c5088eSShreyas Bhatewara return err; 149709c5088eSShreyas Bhatewara 149809c5088eSShreyas Bhatewara } 149909c5088eSShreyas Bhatewara 150009c5088eSShreyas Bhatewara 150109c5088eSShreyas Bhatewara static int 1502d1a890faSShreyas Bhatewara vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter) 1503d1a890faSShreyas Bhatewara { 1504d1a890faSShreyas Bhatewara int i; 1505d1a890faSShreyas Bhatewara size_t sz; 1506d1a890faSShreyas Bhatewara struct vmxnet3_rx_buf_info *bi; 1507d1a890faSShreyas Bhatewara 1508d1a890faSShreyas Bhatewara for (i = 0; i < 2; i++) { 1509d1a890faSShreyas Bhatewara 1510d1a890faSShreyas Bhatewara sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc); 1511d1a890faSShreyas Bhatewara rq->rx_ring[i].base = pci_alloc_consistent(adapter->pdev, sz, 1512d1a890faSShreyas Bhatewara &rq->rx_ring[i].basePA); 1513d1a890faSShreyas Bhatewara if (!rq->rx_ring[i].base) { 1514d1a890faSShreyas Bhatewara printk(KERN_ERR "%s: failed to allocate rx ring %d\n", 1515d1a890faSShreyas Bhatewara adapter->netdev->name, i); 1516d1a890faSShreyas Bhatewara goto err; 1517d1a890faSShreyas Bhatewara } 1518d1a890faSShreyas Bhatewara } 1519d1a890faSShreyas Bhatewara 1520d1a890faSShreyas Bhatewara sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc); 1521d1a890faSShreyas Bhatewara rq->comp_ring.base = pci_alloc_consistent(adapter->pdev, sz, 1522d1a890faSShreyas Bhatewara &rq->comp_ring.basePA); 1523d1a890faSShreyas Bhatewara if (!rq->comp_ring.base) { 1524d1a890faSShreyas Bhatewara printk(KERN_ERR "%s: failed to allocate rx comp ring\n", 1525d1a890faSShreyas Bhatewara adapter->netdev->name); 1526d1a890faSShreyas Bhatewara goto err; 1527d1a890faSShreyas Bhatewara } 1528d1a890faSShreyas Bhatewara 1529d1a890faSShreyas Bhatewara sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size + 1530d1a890faSShreyas Bhatewara rq->rx_ring[1].size); 1531476c609eSJulia Lawall bi = kzalloc(sz, GFP_KERNEL); 1532e404decbSJoe Perches if (!bi) 1533d1a890faSShreyas Bhatewara goto err; 1534e404decbSJoe Perches 1535d1a890faSShreyas Bhatewara rq->buf_info[0] = bi; 1536d1a890faSShreyas Bhatewara rq->buf_info[1] = bi + rq->rx_ring[0].size; 1537d1a890faSShreyas Bhatewara 1538d1a890faSShreyas Bhatewara return 0; 1539d1a890faSShreyas Bhatewara 1540d1a890faSShreyas Bhatewara err: 1541d1a890faSShreyas Bhatewara vmxnet3_rq_destroy(rq, adapter); 1542d1a890faSShreyas Bhatewara return -ENOMEM; 1543d1a890faSShreyas Bhatewara } 1544d1a890faSShreyas Bhatewara 1545d1a890faSShreyas Bhatewara 1546d1a890faSShreyas Bhatewara static int 154709c5088eSShreyas Bhatewara vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter) 154809c5088eSShreyas Bhatewara { 154909c5088eSShreyas Bhatewara int i, err = 0; 155009c5088eSShreyas Bhatewara 155109c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 155209c5088eSShreyas Bhatewara err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter); 155309c5088eSShreyas Bhatewara if (unlikely(err)) { 155409c5088eSShreyas Bhatewara dev_err(&adapter->netdev->dev, 155509c5088eSShreyas Bhatewara "%s: failed to create rx queue%i\n", 155609c5088eSShreyas Bhatewara adapter->netdev->name, i); 155709c5088eSShreyas Bhatewara goto err_out; 155809c5088eSShreyas Bhatewara } 155909c5088eSShreyas Bhatewara } 156009c5088eSShreyas Bhatewara return err; 156109c5088eSShreyas Bhatewara err_out: 156209c5088eSShreyas Bhatewara vmxnet3_rq_destroy_all(adapter); 156309c5088eSShreyas Bhatewara return err; 156409c5088eSShreyas Bhatewara 156509c5088eSShreyas Bhatewara } 156609c5088eSShreyas Bhatewara 156709c5088eSShreyas Bhatewara /* Multiple queue aware polling function for tx and rx */ 156809c5088eSShreyas Bhatewara 156909c5088eSShreyas Bhatewara static int 1570d1a890faSShreyas Bhatewara vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget) 1571d1a890faSShreyas Bhatewara { 157209c5088eSShreyas Bhatewara int rcd_done = 0, i; 1573d1a890faSShreyas Bhatewara if (unlikely(adapter->shared->ecr)) 1574d1a890faSShreyas Bhatewara vmxnet3_process_events(adapter); 157509c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) 157609c5088eSShreyas Bhatewara vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter); 1577d1a890faSShreyas Bhatewara 157809c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) 157909c5088eSShreyas Bhatewara rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i], 158009c5088eSShreyas Bhatewara adapter, budget); 158109c5088eSShreyas Bhatewara return rcd_done; 1582d1a890faSShreyas Bhatewara } 1583d1a890faSShreyas Bhatewara 1584d1a890faSShreyas Bhatewara 1585d1a890faSShreyas Bhatewara static int 1586d1a890faSShreyas Bhatewara vmxnet3_poll(struct napi_struct *napi, int budget) 1587d1a890faSShreyas Bhatewara { 158809c5088eSShreyas Bhatewara struct vmxnet3_rx_queue *rx_queue = container_of(napi, 158909c5088eSShreyas Bhatewara struct vmxnet3_rx_queue, napi); 1590d1a890faSShreyas Bhatewara int rxd_done; 1591d1a890faSShreyas Bhatewara 159209c5088eSShreyas Bhatewara rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget); 1593d1a890faSShreyas Bhatewara 1594d1a890faSShreyas Bhatewara if (rxd_done < budget) { 1595d1a890faSShreyas Bhatewara napi_complete(napi); 159609c5088eSShreyas Bhatewara vmxnet3_enable_all_intrs(rx_queue->adapter); 1597d1a890faSShreyas Bhatewara } 1598d1a890faSShreyas Bhatewara return rxd_done; 1599d1a890faSShreyas Bhatewara } 1600d1a890faSShreyas Bhatewara 160109c5088eSShreyas Bhatewara /* 160209c5088eSShreyas Bhatewara * NAPI polling function for MSI-X mode with multiple Rx queues 160309c5088eSShreyas Bhatewara * Returns the # of the NAPI credit consumed (# of rx descriptors processed) 160409c5088eSShreyas Bhatewara */ 160509c5088eSShreyas Bhatewara 160609c5088eSShreyas Bhatewara static int 160709c5088eSShreyas Bhatewara vmxnet3_poll_rx_only(struct napi_struct *napi, int budget) 160809c5088eSShreyas Bhatewara { 160909c5088eSShreyas Bhatewara struct vmxnet3_rx_queue *rq = container_of(napi, 161009c5088eSShreyas Bhatewara struct vmxnet3_rx_queue, napi); 161109c5088eSShreyas Bhatewara struct vmxnet3_adapter *adapter = rq->adapter; 161209c5088eSShreyas Bhatewara int rxd_done; 161309c5088eSShreyas Bhatewara 161409c5088eSShreyas Bhatewara /* When sharing interrupt with corresponding tx queue, process 161509c5088eSShreyas Bhatewara * tx completions in that queue as well 161609c5088eSShreyas Bhatewara */ 161709c5088eSShreyas Bhatewara if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) { 161809c5088eSShreyas Bhatewara struct vmxnet3_tx_queue *tq = 161909c5088eSShreyas Bhatewara &adapter->tx_queue[rq - adapter->rx_queue]; 162009c5088eSShreyas Bhatewara vmxnet3_tq_tx_complete(tq, adapter); 162109c5088eSShreyas Bhatewara } 162209c5088eSShreyas Bhatewara 162309c5088eSShreyas Bhatewara rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget); 162409c5088eSShreyas Bhatewara 162509c5088eSShreyas Bhatewara if (rxd_done < budget) { 162609c5088eSShreyas Bhatewara napi_complete(napi); 162709c5088eSShreyas Bhatewara vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx); 162809c5088eSShreyas Bhatewara } 162909c5088eSShreyas Bhatewara return rxd_done; 163009c5088eSShreyas Bhatewara } 163109c5088eSShreyas Bhatewara 163209c5088eSShreyas Bhatewara 163309c5088eSShreyas Bhatewara #ifdef CONFIG_PCI_MSI 163409c5088eSShreyas Bhatewara 163509c5088eSShreyas Bhatewara /* 163609c5088eSShreyas Bhatewara * Handle completion interrupts on tx queues 163709c5088eSShreyas Bhatewara * Returns whether or not the intr is handled 163809c5088eSShreyas Bhatewara */ 163909c5088eSShreyas Bhatewara 164009c5088eSShreyas Bhatewara static irqreturn_t 164109c5088eSShreyas Bhatewara vmxnet3_msix_tx(int irq, void *data) 164209c5088eSShreyas Bhatewara { 164309c5088eSShreyas Bhatewara struct vmxnet3_tx_queue *tq = data; 164409c5088eSShreyas Bhatewara struct vmxnet3_adapter *adapter = tq->adapter; 164509c5088eSShreyas Bhatewara 164609c5088eSShreyas Bhatewara if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 164709c5088eSShreyas Bhatewara vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx); 164809c5088eSShreyas Bhatewara 164909c5088eSShreyas Bhatewara /* Handle the case where only one irq is allocate for all tx queues */ 165009c5088eSShreyas Bhatewara if (adapter->share_intr == VMXNET3_INTR_TXSHARE) { 165109c5088eSShreyas Bhatewara int i; 165209c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) { 165309c5088eSShreyas Bhatewara struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i]; 165409c5088eSShreyas Bhatewara vmxnet3_tq_tx_complete(txq, adapter); 165509c5088eSShreyas Bhatewara } 165609c5088eSShreyas Bhatewara } else { 165709c5088eSShreyas Bhatewara vmxnet3_tq_tx_complete(tq, adapter); 165809c5088eSShreyas Bhatewara } 165909c5088eSShreyas Bhatewara vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx); 166009c5088eSShreyas Bhatewara 166109c5088eSShreyas Bhatewara return IRQ_HANDLED; 166209c5088eSShreyas Bhatewara } 166309c5088eSShreyas Bhatewara 166409c5088eSShreyas Bhatewara 166509c5088eSShreyas Bhatewara /* 166609c5088eSShreyas Bhatewara * Handle completion interrupts on rx queues. Returns whether or not the 166709c5088eSShreyas Bhatewara * intr is handled 166809c5088eSShreyas Bhatewara */ 166909c5088eSShreyas Bhatewara 167009c5088eSShreyas Bhatewara static irqreturn_t 167109c5088eSShreyas Bhatewara vmxnet3_msix_rx(int irq, void *data) 167209c5088eSShreyas Bhatewara { 167309c5088eSShreyas Bhatewara struct vmxnet3_rx_queue *rq = data; 167409c5088eSShreyas Bhatewara struct vmxnet3_adapter *adapter = rq->adapter; 167509c5088eSShreyas Bhatewara 167609c5088eSShreyas Bhatewara /* disable intr if needed */ 167709c5088eSShreyas Bhatewara if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 167809c5088eSShreyas Bhatewara vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx); 167909c5088eSShreyas Bhatewara napi_schedule(&rq->napi); 168009c5088eSShreyas Bhatewara 168109c5088eSShreyas Bhatewara return IRQ_HANDLED; 168209c5088eSShreyas Bhatewara } 168309c5088eSShreyas Bhatewara 168409c5088eSShreyas Bhatewara /* 168509c5088eSShreyas Bhatewara *---------------------------------------------------------------------------- 168609c5088eSShreyas Bhatewara * 168709c5088eSShreyas Bhatewara * vmxnet3_msix_event -- 168809c5088eSShreyas Bhatewara * 168909c5088eSShreyas Bhatewara * vmxnet3 msix event intr handler 169009c5088eSShreyas Bhatewara * 169109c5088eSShreyas Bhatewara * Result: 169209c5088eSShreyas Bhatewara * whether or not the intr is handled 169309c5088eSShreyas Bhatewara * 169409c5088eSShreyas Bhatewara *---------------------------------------------------------------------------- 169509c5088eSShreyas Bhatewara */ 169609c5088eSShreyas Bhatewara 169709c5088eSShreyas Bhatewara static irqreturn_t 169809c5088eSShreyas Bhatewara vmxnet3_msix_event(int irq, void *data) 169909c5088eSShreyas Bhatewara { 170009c5088eSShreyas Bhatewara struct net_device *dev = data; 170109c5088eSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(dev); 170209c5088eSShreyas Bhatewara 170309c5088eSShreyas Bhatewara /* disable intr if needed */ 170409c5088eSShreyas Bhatewara if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 170509c5088eSShreyas Bhatewara vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx); 170609c5088eSShreyas Bhatewara 170709c5088eSShreyas Bhatewara if (adapter->shared->ecr) 170809c5088eSShreyas Bhatewara vmxnet3_process_events(adapter); 170909c5088eSShreyas Bhatewara 171009c5088eSShreyas Bhatewara vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx); 171109c5088eSShreyas Bhatewara 171209c5088eSShreyas Bhatewara return IRQ_HANDLED; 171309c5088eSShreyas Bhatewara } 171409c5088eSShreyas Bhatewara 171509c5088eSShreyas Bhatewara #endif /* CONFIG_PCI_MSI */ 171609c5088eSShreyas Bhatewara 1717d1a890faSShreyas Bhatewara 1718d1a890faSShreyas Bhatewara /* Interrupt handler for vmxnet3 */ 1719d1a890faSShreyas Bhatewara static irqreturn_t 1720d1a890faSShreyas Bhatewara vmxnet3_intr(int irq, void *dev_id) 1721d1a890faSShreyas Bhatewara { 1722d1a890faSShreyas Bhatewara struct net_device *dev = dev_id; 1723d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(dev); 1724d1a890faSShreyas Bhatewara 172509c5088eSShreyas Bhatewara if (adapter->intr.type == VMXNET3_IT_INTX) { 1726d1a890faSShreyas Bhatewara u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR); 1727d1a890faSShreyas Bhatewara if (unlikely(icr == 0)) 1728d1a890faSShreyas Bhatewara /* not ours */ 1729d1a890faSShreyas Bhatewara return IRQ_NONE; 1730d1a890faSShreyas Bhatewara } 1731d1a890faSShreyas Bhatewara 1732d1a890faSShreyas Bhatewara 1733d1a890faSShreyas Bhatewara /* disable intr if needed */ 1734d1a890faSShreyas Bhatewara if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 173509c5088eSShreyas Bhatewara vmxnet3_disable_all_intrs(adapter); 1736d1a890faSShreyas Bhatewara 173709c5088eSShreyas Bhatewara napi_schedule(&adapter->rx_queue[0].napi); 1738d1a890faSShreyas Bhatewara 1739d1a890faSShreyas Bhatewara return IRQ_HANDLED; 1740d1a890faSShreyas Bhatewara } 1741d1a890faSShreyas Bhatewara 1742d1a890faSShreyas Bhatewara #ifdef CONFIG_NET_POLL_CONTROLLER 1743d1a890faSShreyas Bhatewara 1744d1a890faSShreyas Bhatewara /* netpoll callback. */ 1745d1a890faSShreyas Bhatewara static void 1746d1a890faSShreyas Bhatewara vmxnet3_netpoll(struct net_device *netdev) 1747d1a890faSShreyas Bhatewara { 1748d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1749d1a890faSShreyas Bhatewara 175009c5088eSShreyas Bhatewara if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 175109c5088eSShreyas Bhatewara vmxnet3_disable_all_intrs(adapter); 1752d1a890faSShreyas Bhatewara 175309c5088eSShreyas Bhatewara vmxnet3_do_poll(adapter, adapter->rx_queue[0].rx_ring[0].size); 175409c5088eSShreyas Bhatewara vmxnet3_enable_all_intrs(adapter); 175509c5088eSShreyas Bhatewara 1756d1a890faSShreyas Bhatewara } 175709c5088eSShreyas Bhatewara #endif /* CONFIG_NET_POLL_CONTROLLER */ 1758d1a890faSShreyas Bhatewara 1759d1a890faSShreyas Bhatewara static int 1760d1a890faSShreyas Bhatewara vmxnet3_request_irqs(struct vmxnet3_adapter *adapter) 1761d1a890faSShreyas Bhatewara { 176209c5088eSShreyas Bhatewara struct vmxnet3_intr *intr = &adapter->intr; 176309c5088eSShreyas Bhatewara int err = 0, i; 176409c5088eSShreyas Bhatewara int vector = 0; 1765d1a890faSShreyas Bhatewara 17668f7e524cSRandy Dunlap #ifdef CONFIG_PCI_MSI 1767d1a890faSShreyas Bhatewara if (adapter->intr.type == VMXNET3_IT_MSIX) { 176809c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) { 176909c5088eSShreyas Bhatewara if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) { 177009c5088eSShreyas Bhatewara sprintf(adapter->tx_queue[i].name, "%s-tx-%d", 177109c5088eSShreyas Bhatewara adapter->netdev->name, vector); 177209c5088eSShreyas Bhatewara err = request_irq( 177309c5088eSShreyas Bhatewara intr->msix_entries[vector].vector, 177409c5088eSShreyas Bhatewara vmxnet3_msix_tx, 0, 177509c5088eSShreyas Bhatewara adapter->tx_queue[i].name, 177609c5088eSShreyas Bhatewara &adapter->tx_queue[i]); 177709c5088eSShreyas Bhatewara } else { 177809c5088eSShreyas Bhatewara sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d", 177909c5088eSShreyas Bhatewara adapter->netdev->name, vector); 178009c5088eSShreyas Bhatewara } 178109c5088eSShreyas Bhatewara if (err) { 178209c5088eSShreyas Bhatewara dev_err(&adapter->netdev->dev, 178309c5088eSShreyas Bhatewara "Failed to request irq for MSIX, %s, " 178409c5088eSShreyas Bhatewara "error %d\n", 178509c5088eSShreyas Bhatewara adapter->tx_queue[i].name, err); 178609c5088eSShreyas Bhatewara return err; 178709c5088eSShreyas Bhatewara } 178809c5088eSShreyas Bhatewara 178909c5088eSShreyas Bhatewara /* Handle the case where only 1 MSIx was allocated for 179009c5088eSShreyas Bhatewara * all tx queues */ 179109c5088eSShreyas Bhatewara if (adapter->share_intr == VMXNET3_INTR_TXSHARE) { 179209c5088eSShreyas Bhatewara for (; i < adapter->num_tx_queues; i++) 179309c5088eSShreyas Bhatewara adapter->tx_queue[i].comp_ring.intr_idx 179409c5088eSShreyas Bhatewara = vector; 179509c5088eSShreyas Bhatewara vector++; 179609c5088eSShreyas Bhatewara break; 179709c5088eSShreyas Bhatewara } else { 179809c5088eSShreyas Bhatewara adapter->tx_queue[i].comp_ring.intr_idx 179909c5088eSShreyas Bhatewara = vector++; 180009c5088eSShreyas Bhatewara } 180109c5088eSShreyas Bhatewara } 180209c5088eSShreyas Bhatewara if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) 180309c5088eSShreyas Bhatewara vector = 0; 180409c5088eSShreyas Bhatewara 180509c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 180609c5088eSShreyas Bhatewara if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) 180709c5088eSShreyas Bhatewara sprintf(adapter->rx_queue[i].name, "%s-rx-%d", 180809c5088eSShreyas Bhatewara adapter->netdev->name, vector); 180909c5088eSShreyas Bhatewara else 181009c5088eSShreyas Bhatewara sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d", 181109c5088eSShreyas Bhatewara adapter->netdev->name, vector); 181209c5088eSShreyas Bhatewara err = request_irq(intr->msix_entries[vector].vector, 181309c5088eSShreyas Bhatewara vmxnet3_msix_rx, 0, 181409c5088eSShreyas Bhatewara adapter->rx_queue[i].name, 181509c5088eSShreyas Bhatewara &(adapter->rx_queue[i])); 181609c5088eSShreyas Bhatewara if (err) { 181709c5088eSShreyas Bhatewara printk(KERN_ERR "Failed to request irq for MSIX" 181809c5088eSShreyas Bhatewara ", %s, error %d\n", 181909c5088eSShreyas Bhatewara adapter->rx_queue[i].name, err); 182009c5088eSShreyas Bhatewara return err; 182109c5088eSShreyas Bhatewara } 182209c5088eSShreyas Bhatewara 182309c5088eSShreyas Bhatewara adapter->rx_queue[i].comp_ring.intr_idx = vector++; 182409c5088eSShreyas Bhatewara } 182509c5088eSShreyas Bhatewara 182609c5088eSShreyas Bhatewara sprintf(intr->event_msi_vector_name, "%s-event-%d", 182709c5088eSShreyas Bhatewara adapter->netdev->name, vector); 182809c5088eSShreyas Bhatewara err = request_irq(intr->msix_entries[vector].vector, 182909c5088eSShreyas Bhatewara vmxnet3_msix_event, 0, 183009c5088eSShreyas Bhatewara intr->event_msi_vector_name, adapter->netdev); 183109c5088eSShreyas Bhatewara intr->event_intr_idx = vector; 183209c5088eSShreyas Bhatewara 183309c5088eSShreyas Bhatewara } else if (intr->type == VMXNET3_IT_MSI) { 183409c5088eSShreyas Bhatewara adapter->num_rx_queues = 1; 1835d1a890faSShreyas Bhatewara err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0, 1836d1a890faSShreyas Bhatewara adapter->netdev->name, adapter->netdev); 183709c5088eSShreyas Bhatewara } else { 1838115924b6SShreyas Bhatewara #endif 183909c5088eSShreyas Bhatewara adapter->num_rx_queues = 1; 1840d1a890faSShreyas Bhatewara err = request_irq(adapter->pdev->irq, vmxnet3_intr, 1841d1a890faSShreyas Bhatewara IRQF_SHARED, adapter->netdev->name, 1842d1a890faSShreyas Bhatewara adapter->netdev); 184309c5088eSShreyas Bhatewara #ifdef CONFIG_PCI_MSI 184409c5088eSShreyas Bhatewara } 184509c5088eSShreyas Bhatewara #endif 184609c5088eSShreyas Bhatewara intr->num_intrs = vector + 1; 184709c5088eSShreyas Bhatewara if (err) { 184809c5088eSShreyas Bhatewara printk(KERN_ERR "Failed to request irq %s (intr type:%d), error" 184909c5088eSShreyas Bhatewara ":%d\n", adapter->netdev->name, intr->type, err); 185009c5088eSShreyas Bhatewara } else { 185109c5088eSShreyas Bhatewara /* Number of rx queues will not change after this */ 185209c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 185309c5088eSShreyas Bhatewara struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 185409c5088eSShreyas Bhatewara rq->qid = i; 185509c5088eSShreyas Bhatewara rq->qid2 = i + adapter->num_rx_queues; 1856d1a890faSShreyas Bhatewara } 1857d1a890faSShreyas Bhatewara 1858d1a890faSShreyas Bhatewara 1859d1a890faSShreyas Bhatewara 1860d1a890faSShreyas Bhatewara /* init our intr settings */ 186109c5088eSShreyas Bhatewara for (i = 0; i < intr->num_intrs; i++) 186209c5088eSShreyas Bhatewara intr->mod_levels[i] = UPT1_IML_ADAPTIVE; 186309c5088eSShreyas Bhatewara if (adapter->intr.type != VMXNET3_IT_MSIX) { 1864d1a890faSShreyas Bhatewara adapter->intr.event_intr_idx = 0; 186509c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) 186609c5088eSShreyas Bhatewara adapter->tx_queue[i].comp_ring.intr_idx = 0; 186709c5088eSShreyas Bhatewara adapter->rx_queue[0].comp_ring.intr_idx = 0; 186809c5088eSShreyas Bhatewara } 1869d1a890faSShreyas Bhatewara 1870d1a890faSShreyas Bhatewara printk(KERN_INFO "%s: intr type %u, mode %u, %u vectors " 187109c5088eSShreyas Bhatewara "allocated\n", adapter->netdev->name, intr->type, 187209c5088eSShreyas Bhatewara intr->mask_mode, intr->num_intrs); 1873d1a890faSShreyas Bhatewara } 1874d1a890faSShreyas Bhatewara 1875d1a890faSShreyas Bhatewara return err; 1876d1a890faSShreyas Bhatewara } 1877d1a890faSShreyas Bhatewara 1878d1a890faSShreyas Bhatewara 1879d1a890faSShreyas Bhatewara static void 1880d1a890faSShreyas Bhatewara vmxnet3_free_irqs(struct vmxnet3_adapter *adapter) 1881d1a890faSShreyas Bhatewara { 188209c5088eSShreyas Bhatewara struct vmxnet3_intr *intr = &adapter->intr; 188309c5088eSShreyas Bhatewara BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0); 1884d1a890faSShreyas Bhatewara 188509c5088eSShreyas Bhatewara switch (intr->type) { 18868f7e524cSRandy Dunlap #ifdef CONFIG_PCI_MSI 1887d1a890faSShreyas Bhatewara case VMXNET3_IT_MSIX: 1888d1a890faSShreyas Bhatewara { 188909c5088eSShreyas Bhatewara int i, vector = 0; 1890d1a890faSShreyas Bhatewara 189109c5088eSShreyas Bhatewara if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) { 189209c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) { 189309c5088eSShreyas Bhatewara free_irq(intr->msix_entries[vector++].vector, 189409c5088eSShreyas Bhatewara &(adapter->tx_queue[i])); 189509c5088eSShreyas Bhatewara if (adapter->share_intr == VMXNET3_INTR_TXSHARE) 189609c5088eSShreyas Bhatewara break; 189709c5088eSShreyas Bhatewara } 189809c5088eSShreyas Bhatewara } 189909c5088eSShreyas Bhatewara 190009c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 190109c5088eSShreyas Bhatewara free_irq(intr->msix_entries[vector++].vector, 190209c5088eSShreyas Bhatewara &(adapter->rx_queue[i])); 190309c5088eSShreyas Bhatewara } 190409c5088eSShreyas Bhatewara 190509c5088eSShreyas Bhatewara free_irq(intr->msix_entries[vector].vector, 1906d1a890faSShreyas Bhatewara adapter->netdev); 190709c5088eSShreyas Bhatewara BUG_ON(vector >= intr->num_intrs); 1908d1a890faSShreyas Bhatewara break; 1909d1a890faSShreyas Bhatewara } 19108f7e524cSRandy Dunlap #endif 1911d1a890faSShreyas Bhatewara case VMXNET3_IT_MSI: 1912d1a890faSShreyas Bhatewara free_irq(adapter->pdev->irq, adapter->netdev); 1913d1a890faSShreyas Bhatewara break; 1914d1a890faSShreyas Bhatewara case VMXNET3_IT_INTX: 1915d1a890faSShreyas Bhatewara free_irq(adapter->pdev->irq, adapter->netdev); 1916d1a890faSShreyas Bhatewara break; 1917d1a890faSShreyas Bhatewara default: 1918c068e777SSasha Levin BUG(); 1919d1a890faSShreyas Bhatewara } 1920d1a890faSShreyas Bhatewara } 1921d1a890faSShreyas Bhatewara 1922d1a890faSShreyas Bhatewara 1923d1a890faSShreyas Bhatewara static void 1924d1a890faSShreyas Bhatewara vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter) 1925d1a890faSShreyas Bhatewara { 1926d1a890faSShreyas Bhatewara u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 192772e85c45SJesse Gross u16 vid; 1928d1a890faSShreyas Bhatewara 192972e85c45SJesse Gross /* allow untagged pkts */ 1930d1a890faSShreyas Bhatewara VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0); 193172e85c45SJesse Gross 193272e85c45SJesse Gross for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 193372e85c45SJesse Gross VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid); 1934d1a890faSShreyas Bhatewara } 1935d1a890faSShreyas Bhatewara 1936d1a890faSShreyas Bhatewara 19378e586137SJiri Pirko static int 1938d1a890faSShreyas Bhatewara vmxnet3_vlan_rx_add_vid(struct net_device *netdev, u16 vid) 1939d1a890faSShreyas Bhatewara { 1940d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1941f6957f88SJesse Gross 1942f6957f88SJesse Gross if (!(netdev->flags & IFF_PROMISC)) { 1943d1a890faSShreyas Bhatewara u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 194483d0feffSShreyas Bhatewara unsigned long flags; 1945d1a890faSShreyas Bhatewara 1946d1a890faSShreyas Bhatewara VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid); 194783d0feffSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 1948d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 1949d1a890faSShreyas Bhatewara VMXNET3_CMD_UPDATE_VLAN_FILTERS); 195083d0feffSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 1951f6957f88SJesse Gross } 195272e85c45SJesse Gross 195372e85c45SJesse Gross set_bit(vid, adapter->active_vlans); 19548e586137SJiri Pirko 19558e586137SJiri Pirko return 0; 1956d1a890faSShreyas Bhatewara } 1957d1a890faSShreyas Bhatewara 1958d1a890faSShreyas Bhatewara 19598e586137SJiri Pirko static int 1960d1a890faSShreyas Bhatewara vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) 1961d1a890faSShreyas Bhatewara { 1962d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1963f6957f88SJesse Gross 1964f6957f88SJesse Gross if (!(netdev->flags & IFF_PROMISC)) { 1965d1a890faSShreyas Bhatewara u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 196683d0feffSShreyas Bhatewara unsigned long flags; 1967d1a890faSShreyas Bhatewara 1968d1a890faSShreyas Bhatewara VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid); 196983d0feffSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 1970d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 1971d1a890faSShreyas Bhatewara VMXNET3_CMD_UPDATE_VLAN_FILTERS); 197283d0feffSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 1973f6957f88SJesse Gross } 197472e85c45SJesse Gross 197572e85c45SJesse Gross clear_bit(vid, adapter->active_vlans); 19768e586137SJiri Pirko 19778e586137SJiri Pirko return 0; 1978d1a890faSShreyas Bhatewara } 1979d1a890faSShreyas Bhatewara 1980d1a890faSShreyas Bhatewara 1981d1a890faSShreyas Bhatewara static u8 * 1982d1a890faSShreyas Bhatewara vmxnet3_copy_mc(struct net_device *netdev) 1983d1a890faSShreyas Bhatewara { 1984d1a890faSShreyas Bhatewara u8 *buf = NULL; 19854cd24eafSJiri Pirko u32 sz = netdev_mc_count(netdev) * ETH_ALEN; 1986d1a890faSShreyas Bhatewara 1987d1a890faSShreyas Bhatewara /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */ 1988d1a890faSShreyas Bhatewara if (sz <= 0xffff) { 1989d1a890faSShreyas Bhatewara /* We may be called with BH disabled */ 1990d1a890faSShreyas Bhatewara buf = kmalloc(sz, GFP_ATOMIC); 1991d1a890faSShreyas Bhatewara if (buf) { 199222bedad3SJiri Pirko struct netdev_hw_addr *ha; 1993567ec874SJiri Pirko int i = 0; 1994d1a890faSShreyas Bhatewara 199522bedad3SJiri Pirko netdev_for_each_mc_addr(ha, netdev) 199622bedad3SJiri Pirko memcpy(buf + i++ * ETH_ALEN, ha->addr, 1997d1a890faSShreyas Bhatewara ETH_ALEN); 1998d1a890faSShreyas Bhatewara } 1999d1a890faSShreyas Bhatewara } 2000d1a890faSShreyas Bhatewara return buf; 2001d1a890faSShreyas Bhatewara } 2002d1a890faSShreyas Bhatewara 2003d1a890faSShreyas Bhatewara 2004d1a890faSShreyas Bhatewara static void 2005d1a890faSShreyas Bhatewara vmxnet3_set_mc(struct net_device *netdev) 2006d1a890faSShreyas Bhatewara { 2007d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 200883d0feffSShreyas Bhatewara unsigned long flags; 2009d1a890faSShreyas Bhatewara struct Vmxnet3_RxFilterConf *rxConf = 2010d1a890faSShreyas Bhatewara &adapter->shared->devRead.rxFilterConf; 2011d1a890faSShreyas Bhatewara u8 *new_table = NULL; 2012d1a890faSShreyas Bhatewara u32 new_mode = VMXNET3_RXM_UCAST; 2013d1a890faSShreyas Bhatewara 201472e85c45SJesse Gross if (netdev->flags & IFF_PROMISC) { 201572e85c45SJesse Gross u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 201672e85c45SJesse Gross memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable)); 201772e85c45SJesse Gross 2018d1a890faSShreyas Bhatewara new_mode |= VMXNET3_RXM_PROMISC; 201972e85c45SJesse Gross } else { 202072e85c45SJesse Gross vmxnet3_restore_vlan(adapter); 202172e85c45SJesse Gross } 2022d1a890faSShreyas Bhatewara 2023d1a890faSShreyas Bhatewara if (netdev->flags & IFF_BROADCAST) 2024d1a890faSShreyas Bhatewara new_mode |= VMXNET3_RXM_BCAST; 2025d1a890faSShreyas Bhatewara 2026d1a890faSShreyas Bhatewara if (netdev->flags & IFF_ALLMULTI) 2027d1a890faSShreyas Bhatewara new_mode |= VMXNET3_RXM_ALL_MULTI; 2028d1a890faSShreyas Bhatewara else 20294cd24eafSJiri Pirko if (!netdev_mc_empty(netdev)) { 2030d1a890faSShreyas Bhatewara new_table = vmxnet3_copy_mc(netdev); 2031d1a890faSShreyas Bhatewara if (new_table) { 2032d1a890faSShreyas Bhatewara new_mode |= VMXNET3_RXM_MCAST; 2033115924b6SShreyas Bhatewara rxConf->mfTableLen = cpu_to_le16( 20344cd24eafSJiri Pirko netdev_mc_count(netdev) * ETH_ALEN); 2035115924b6SShreyas Bhatewara rxConf->mfTablePA = cpu_to_le64(virt_to_phys( 2036115924b6SShreyas Bhatewara new_table)); 2037d1a890faSShreyas Bhatewara } else { 2038d1a890faSShreyas Bhatewara printk(KERN_INFO "%s: failed to copy mcast list" 2039d1a890faSShreyas Bhatewara ", setting ALL_MULTI\n", netdev->name); 2040d1a890faSShreyas Bhatewara new_mode |= VMXNET3_RXM_ALL_MULTI; 2041d1a890faSShreyas Bhatewara } 2042d1a890faSShreyas Bhatewara } 2043d1a890faSShreyas Bhatewara 2044d1a890faSShreyas Bhatewara 2045d1a890faSShreyas Bhatewara if (!(new_mode & VMXNET3_RXM_MCAST)) { 2046d1a890faSShreyas Bhatewara rxConf->mfTableLen = 0; 2047d1a890faSShreyas Bhatewara rxConf->mfTablePA = 0; 2048d1a890faSShreyas Bhatewara } 2049d1a890faSShreyas Bhatewara 205083d0feffSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 2051d1a890faSShreyas Bhatewara if (new_mode != rxConf->rxMode) { 2052115924b6SShreyas Bhatewara rxConf->rxMode = cpu_to_le32(new_mode); 2053d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2054d1a890faSShreyas Bhatewara VMXNET3_CMD_UPDATE_RX_MODE); 205572e85c45SJesse Gross VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 205672e85c45SJesse Gross VMXNET3_CMD_UPDATE_VLAN_FILTERS); 2057d1a890faSShreyas Bhatewara } 2058d1a890faSShreyas Bhatewara 2059d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2060d1a890faSShreyas Bhatewara VMXNET3_CMD_UPDATE_MAC_FILTERS); 206183d0feffSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2062d1a890faSShreyas Bhatewara 2063d1a890faSShreyas Bhatewara kfree(new_table); 2064d1a890faSShreyas Bhatewara } 2065d1a890faSShreyas Bhatewara 206609c5088eSShreyas Bhatewara void 206709c5088eSShreyas Bhatewara vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter) 206809c5088eSShreyas Bhatewara { 206909c5088eSShreyas Bhatewara int i; 207009c5088eSShreyas Bhatewara 207109c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) 207209c5088eSShreyas Bhatewara vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter); 207309c5088eSShreyas Bhatewara } 207409c5088eSShreyas Bhatewara 2075d1a890faSShreyas Bhatewara 2076d1a890faSShreyas Bhatewara /* 2077d1a890faSShreyas Bhatewara * Set up driver_shared based on settings in adapter. 2078d1a890faSShreyas Bhatewara */ 2079d1a890faSShreyas Bhatewara 2080d1a890faSShreyas Bhatewara static void 2081d1a890faSShreyas Bhatewara vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter) 2082d1a890faSShreyas Bhatewara { 2083d1a890faSShreyas Bhatewara struct Vmxnet3_DriverShared *shared = adapter->shared; 2084d1a890faSShreyas Bhatewara struct Vmxnet3_DSDevRead *devRead = &shared->devRead; 2085d1a890faSShreyas Bhatewara struct Vmxnet3_TxQueueConf *tqc; 2086d1a890faSShreyas Bhatewara struct Vmxnet3_RxQueueConf *rqc; 2087d1a890faSShreyas Bhatewara int i; 2088d1a890faSShreyas Bhatewara 2089d1a890faSShreyas Bhatewara memset(shared, 0, sizeof(*shared)); 2090d1a890faSShreyas Bhatewara 2091d1a890faSShreyas Bhatewara /* driver settings */ 2092115924b6SShreyas Bhatewara shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC); 2093115924b6SShreyas Bhatewara devRead->misc.driverInfo.version = cpu_to_le32( 2094115924b6SShreyas Bhatewara VMXNET3_DRIVER_VERSION_NUM); 2095d1a890faSShreyas Bhatewara devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ? 2096d1a890faSShreyas Bhatewara VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64); 2097d1a890faSShreyas Bhatewara devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 2098115924b6SShreyas Bhatewara *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32( 2099115924b6SShreyas Bhatewara *((u32 *)&devRead->misc.driverInfo.gos)); 2100115924b6SShreyas Bhatewara devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1); 2101115924b6SShreyas Bhatewara devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1); 2102d1a890faSShreyas Bhatewara 2103115924b6SShreyas Bhatewara devRead->misc.ddPA = cpu_to_le64(virt_to_phys(adapter)); 2104115924b6SShreyas Bhatewara devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter)); 2105d1a890faSShreyas Bhatewara 2106d1a890faSShreyas Bhatewara /* set up feature flags */ 2107a0d2730cSMichał Mirosław if (adapter->netdev->features & NETIF_F_RXCSUM) 21083843e515SHarvey Harrison devRead->misc.uptFeatures |= UPT1_F_RXCSUM; 2109d1a890faSShreyas Bhatewara 2110a0d2730cSMichał Mirosław if (adapter->netdev->features & NETIF_F_LRO) { 21113843e515SHarvey Harrison devRead->misc.uptFeatures |= UPT1_F_LRO; 2112115924b6SShreyas Bhatewara devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS); 2113d1a890faSShreyas Bhatewara } 211454da3d00SShreyas Bhatewara if (adapter->netdev->features & NETIF_F_HW_VLAN_RX) 21153843e515SHarvey Harrison devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 2116d1a890faSShreyas Bhatewara 2117115924b6SShreyas Bhatewara devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu); 2118115924b6SShreyas Bhatewara devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa); 2119115924b6SShreyas Bhatewara devRead->misc.queueDescLen = cpu_to_le32( 212009c5088eSShreyas Bhatewara adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 212109c5088eSShreyas Bhatewara adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc)); 2122d1a890faSShreyas Bhatewara 2123d1a890faSShreyas Bhatewara /* tx queue settings */ 212409c5088eSShreyas Bhatewara devRead->misc.numTxQueues = adapter->num_tx_queues; 212509c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) { 212609c5088eSShreyas Bhatewara struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i]; 212709c5088eSShreyas Bhatewara BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL); 212809c5088eSShreyas Bhatewara tqc = &adapter->tqd_start[i].conf; 212909c5088eSShreyas Bhatewara tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA); 213009c5088eSShreyas Bhatewara tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA); 213109c5088eSShreyas Bhatewara tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA); 213209c5088eSShreyas Bhatewara tqc->ddPA = cpu_to_le64(virt_to_phys(tq->buf_info)); 213309c5088eSShreyas Bhatewara tqc->txRingSize = cpu_to_le32(tq->tx_ring.size); 213409c5088eSShreyas Bhatewara tqc->dataRingSize = cpu_to_le32(tq->data_ring.size); 213509c5088eSShreyas Bhatewara tqc->compRingSize = cpu_to_le32(tq->comp_ring.size); 213609c5088eSShreyas Bhatewara tqc->ddLen = cpu_to_le32( 213709c5088eSShreyas Bhatewara sizeof(struct vmxnet3_tx_buf_info) * 2138115924b6SShreyas Bhatewara tqc->txRingSize); 213909c5088eSShreyas Bhatewara tqc->intrIdx = tq->comp_ring.intr_idx; 214009c5088eSShreyas Bhatewara } 2141d1a890faSShreyas Bhatewara 2142d1a890faSShreyas Bhatewara /* rx queue settings */ 214309c5088eSShreyas Bhatewara devRead->misc.numRxQueues = adapter->num_rx_queues; 214409c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 214509c5088eSShreyas Bhatewara struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 214609c5088eSShreyas Bhatewara rqc = &adapter->rqd_start[i].conf; 214709c5088eSShreyas Bhatewara rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA); 214809c5088eSShreyas Bhatewara rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA); 214909c5088eSShreyas Bhatewara rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA); 2150115924b6SShreyas Bhatewara rqc->ddPA = cpu_to_le64(virt_to_phys( 215109c5088eSShreyas Bhatewara rq->buf_info)); 215209c5088eSShreyas Bhatewara rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size); 215309c5088eSShreyas Bhatewara rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size); 215409c5088eSShreyas Bhatewara rqc->compRingSize = cpu_to_le32(rq->comp_ring.size); 215509c5088eSShreyas Bhatewara rqc->ddLen = cpu_to_le32( 215609c5088eSShreyas Bhatewara sizeof(struct vmxnet3_rx_buf_info) * 215709c5088eSShreyas Bhatewara (rqc->rxRingSize[0] + 215809c5088eSShreyas Bhatewara rqc->rxRingSize[1])); 215909c5088eSShreyas Bhatewara rqc->intrIdx = rq->comp_ring.intr_idx; 216009c5088eSShreyas Bhatewara } 216109c5088eSShreyas Bhatewara 216209c5088eSShreyas Bhatewara #ifdef VMXNET3_RSS 216309c5088eSShreyas Bhatewara memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf)); 216409c5088eSShreyas Bhatewara 216509c5088eSShreyas Bhatewara if (adapter->rss) { 216609c5088eSShreyas Bhatewara struct UPT1_RSSConf *rssConf = adapter->rss_conf; 216709c5088eSShreyas Bhatewara devRead->misc.uptFeatures |= UPT1_F_RSS; 216809c5088eSShreyas Bhatewara devRead->misc.numRxQueues = adapter->num_rx_queues; 216909c5088eSShreyas Bhatewara rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 | 217009c5088eSShreyas Bhatewara UPT1_RSS_HASH_TYPE_IPV4 | 217109c5088eSShreyas Bhatewara UPT1_RSS_HASH_TYPE_TCP_IPV6 | 217209c5088eSShreyas Bhatewara UPT1_RSS_HASH_TYPE_IPV6; 217309c5088eSShreyas Bhatewara rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ; 217409c5088eSShreyas Bhatewara rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE; 217509c5088eSShreyas Bhatewara rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE; 217609c5088eSShreyas Bhatewara get_random_bytes(&rssConf->hashKey[0], rssConf->hashKeySize); 217709c5088eSShreyas Bhatewara for (i = 0; i < rssConf->indTableSize; i++) 2178278bc429SBen Hutchings rssConf->indTable[i] = ethtool_rxfh_indir_default( 2179278bc429SBen Hutchings i, adapter->num_rx_queues); 218009c5088eSShreyas Bhatewara 218109c5088eSShreyas Bhatewara devRead->rssConfDesc.confVer = 1; 218209c5088eSShreyas Bhatewara devRead->rssConfDesc.confLen = sizeof(*rssConf); 218309c5088eSShreyas Bhatewara devRead->rssConfDesc.confPA = virt_to_phys(rssConf); 218409c5088eSShreyas Bhatewara } 218509c5088eSShreyas Bhatewara 218609c5088eSShreyas Bhatewara #endif /* VMXNET3_RSS */ 2187d1a890faSShreyas Bhatewara 2188d1a890faSShreyas Bhatewara /* intr settings */ 2189d1a890faSShreyas Bhatewara devRead->intrConf.autoMask = adapter->intr.mask_mode == 2190d1a890faSShreyas Bhatewara VMXNET3_IMM_AUTO; 2191d1a890faSShreyas Bhatewara devRead->intrConf.numIntrs = adapter->intr.num_intrs; 2192d1a890faSShreyas Bhatewara for (i = 0; i < adapter->intr.num_intrs; i++) 2193d1a890faSShreyas Bhatewara devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i]; 2194d1a890faSShreyas Bhatewara 2195d1a890faSShreyas Bhatewara devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx; 21966929fe8aSRonghua Zang devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL); 2197d1a890faSShreyas Bhatewara 2198d1a890faSShreyas Bhatewara /* rx filter settings */ 2199d1a890faSShreyas Bhatewara devRead->rxFilterConf.rxMode = 0; 2200d1a890faSShreyas Bhatewara vmxnet3_restore_vlan(adapter); 2201f9f25026SShreyas Bhatewara vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr); 2202f9f25026SShreyas Bhatewara 2203d1a890faSShreyas Bhatewara /* the rest are already zeroed */ 2204d1a890faSShreyas Bhatewara } 2205d1a890faSShreyas Bhatewara 2206d1a890faSShreyas Bhatewara 2207d1a890faSShreyas Bhatewara int 2208d1a890faSShreyas Bhatewara vmxnet3_activate_dev(struct vmxnet3_adapter *adapter) 2209d1a890faSShreyas Bhatewara { 221009c5088eSShreyas Bhatewara int err, i; 2211d1a890faSShreyas Bhatewara u32 ret; 221283d0feffSShreyas Bhatewara unsigned long flags; 2213d1a890faSShreyas Bhatewara 2214fdcd79b9SStephen Hemminger netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d," 221509c5088eSShreyas Bhatewara " ring sizes %u %u %u\n", adapter->netdev->name, 221609c5088eSShreyas Bhatewara adapter->skb_buf_size, adapter->rx_buf_per_pkt, 221709c5088eSShreyas Bhatewara adapter->tx_queue[0].tx_ring.size, 221809c5088eSShreyas Bhatewara adapter->rx_queue[0].rx_ring[0].size, 221909c5088eSShreyas Bhatewara adapter->rx_queue[0].rx_ring[1].size); 2220d1a890faSShreyas Bhatewara 222109c5088eSShreyas Bhatewara vmxnet3_tq_init_all(adapter); 222209c5088eSShreyas Bhatewara err = vmxnet3_rq_init_all(adapter); 2223d1a890faSShreyas Bhatewara if (err) { 2224d1a890faSShreyas Bhatewara printk(KERN_ERR "Failed to init rx queue for %s: error %d\n", 2225d1a890faSShreyas Bhatewara adapter->netdev->name, err); 2226d1a890faSShreyas Bhatewara goto rq_err; 2227d1a890faSShreyas Bhatewara } 2228d1a890faSShreyas Bhatewara 2229d1a890faSShreyas Bhatewara err = vmxnet3_request_irqs(adapter); 2230d1a890faSShreyas Bhatewara if (err) { 2231d1a890faSShreyas Bhatewara printk(KERN_ERR "Failed to setup irq for %s: error %d\n", 2232d1a890faSShreyas Bhatewara adapter->netdev->name, err); 2233d1a890faSShreyas Bhatewara goto irq_err; 2234d1a890faSShreyas Bhatewara } 2235d1a890faSShreyas Bhatewara 2236d1a890faSShreyas Bhatewara vmxnet3_setup_driver_shared(adapter); 2237d1a890faSShreyas Bhatewara 2238115924b6SShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO( 2239115924b6SShreyas Bhatewara adapter->shared_pa)); 2240115924b6SShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI( 2241115924b6SShreyas Bhatewara adapter->shared_pa)); 224283d0feffSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 2243d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2244d1a890faSShreyas Bhatewara VMXNET3_CMD_ACTIVATE_DEV); 2245d1a890faSShreyas Bhatewara ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 224683d0feffSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2247d1a890faSShreyas Bhatewara 2248d1a890faSShreyas Bhatewara if (ret != 0) { 2249d1a890faSShreyas Bhatewara printk(KERN_ERR "Failed to activate dev %s: error %u\n", 2250d1a890faSShreyas Bhatewara adapter->netdev->name, ret); 2251d1a890faSShreyas Bhatewara err = -EINVAL; 2252d1a890faSShreyas Bhatewara goto activate_err; 2253d1a890faSShreyas Bhatewara } 225409c5088eSShreyas Bhatewara 225509c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 225609c5088eSShreyas Bhatewara VMXNET3_WRITE_BAR0_REG(adapter, 225709c5088eSShreyas Bhatewara VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN, 225809c5088eSShreyas Bhatewara adapter->rx_queue[i].rx_ring[0].next2fill); 225909c5088eSShreyas Bhatewara VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 + 226009c5088eSShreyas Bhatewara (i * VMXNET3_REG_ALIGN)), 226109c5088eSShreyas Bhatewara adapter->rx_queue[i].rx_ring[1].next2fill); 226209c5088eSShreyas Bhatewara } 2263d1a890faSShreyas Bhatewara 2264d1a890faSShreyas Bhatewara /* Apply the rx filter settins last. */ 2265d1a890faSShreyas Bhatewara vmxnet3_set_mc(adapter->netdev); 2266d1a890faSShreyas Bhatewara 2267d1a890faSShreyas Bhatewara /* 2268d1a890faSShreyas Bhatewara * Check link state when first activating device. It will start the 2269d1a890faSShreyas Bhatewara * tx queue if the link is up. 2270d1a890faSShreyas Bhatewara */ 22714a1745fcSShreyas Bhatewara vmxnet3_check_link(adapter, true); 227209c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) 227309c5088eSShreyas Bhatewara napi_enable(&adapter->rx_queue[i].napi); 2274d1a890faSShreyas Bhatewara vmxnet3_enable_all_intrs(adapter); 2275d1a890faSShreyas Bhatewara clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 2276d1a890faSShreyas Bhatewara return 0; 2277d1a890faSShreyas Bhatewara 2278d1a890faSShreyas Bhatewara activate_err: 2279d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0); 2280d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0); 2281d1a890faSShreyas Bhatewara vmxnet3_free_irqs(adapter); 2282d1a890faSShreyas Bhatewara irq_err: 2283d1a890faSShreyas Bhatewara rq_err: 2284d1a890faSShreyas Bhatewara /* free up buffers we allocated */ 228509c5088eSShreyas Bhatewara vmxnet3_rq_cleanup_all(adapter); 2286d1a890faSShreyas Bhatewara return err; 2287d1a890faSShreyas Bhatewara } 2288d1a890faSShreyas Bhatewara 2289d1a890faSShreyas Bhatewara 2290d1a890faSShreyas Bhatewara void 2291d1a890faSShreyas Bhatewara vmxnet3_reset_dev(struct vmxnet3_adapter *adapter) 2292d1a890faSShreyas Bhatewara { 229383d0feffSShreyas Bhatewara unsigned long flags; 229483d0feffSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 2295d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 229683d0feffSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2297d1a890faSShreyas Bhatewara } 2298d1a890faSShreyas Bhatewara 2299d1a890faSShreyas Bhatewara 2300d1a890faSShreyas Bhatewara int 2301d1a890faSShreyas Bhatewara vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter) 2302d1a890faSShreyas Bhatewara { 230309c5088eSShreyas Bhatewara int i; 230483d0feffSShreyas Bhatewara unsigned long flags; 2305d1a890faSShreyas Bhatewara if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state)) 2306d1a890faSShreyas Bhatewara return 0; 2307d1a890faSShreyas Bhatewara 2308d1a890faSShreyas Bhatewara 230983d0feffSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 2310d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2311d1a890faSShreyas Bhatewara VMXNET3_CMD_QUIESCE_DEV); 231283d0feffSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2313d1a890faSShreyas Bhatewara vmxnet3_disable_all_intrs(adapter); 2314d1a890faSShreyas Bhatewara 231509c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) 231609c5088eSShreyas Bhatewara napi_disable(&adapter->rx_queue[i].napi); 2317d1a890faSShreyas Bhatewara netif_tx_disable(adapter->netdev); 2318d1a890faSShreyas Bhatewara adapter->link_speed = 0; 2319d1a890faSShreyas Bhatewara netif_carrier_off(adapter->netdev); 2320d1a890faSShreyas Bhatewara 232109c5088eSShreyas Bhatewara vmxnet3_tq_cleanup_all(adapter); 232209c5088eSShreyas Bhatewara vmxnet3_rq_cleanup_all(adapter); 2323d1a890faSShreyas Bhatewara vmxnet3_free_irqs(adapter); 2324d1a890faSShreyas Bhatewara return 0; 2325d1a890faSShreyas Bhatewara } 2326d1a890faSShreyas Bhatewara 2327d1a890faSShreyas Bhatewara 2328d1a890faSShreyas Bhatewara static void 2329d1a890faSShreyas Bhatewara vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac) 2330d1a890faSShreyas Bhatewara { 2331d1a890faSShreyas Bhatewara u32 tmp; 2332d1a890faSShreyas Bhatewara 2333d1a890faSShreyas Bhatewara tmp = *(u32 *)mac; 2334d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp); 2335d1a890faSShreyas Bhatewara 2336d1a890faSShreyas Bhatewara tmp = (mac[5] << 8) | mac[4]; 2337d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp); 2338d1a890faSShreyas Bhatewara } 2339d1a890faSShreyas Bhatewara 2340d1a890faSShreyas Bhatewara 2341d1a890faSShreyas Bhatewara static int 2342d1a890faSShreyas Bhatewara vmxnet3_set_mac_addr(struct net_device *netdev, void *p) 2343d1a890faSShreyas Bhatewara { 2344d1a890faSShreyas Bhatewara struct sockaddr *addr = p; 2345d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2346d1a890faSShreyas Bhatewara 2347d1a890faSShreyas Bhatewara memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 2348d1a890faSShreyas Bhatewara vmxnet3_write_mac_addr(adapter, addr->sa_data); 2349d1a890faSShreyas Bhatewara 2350d1a890faSShreyas Bhatewara return 0; 2351d1a890faSShreyas Bhatewara } 2352d1a890faSShreyas Bhatewara 2353d1a890faSShreyas Bhatewara 2354d1a890faSShreyas Bhatewara /* ==================== initialization and cleanup routines ============ */ 2355d1a890faSShreyas Bhatewara 2356d1a890faSShreyas Bhatewara static int 2357d1a890faSShreyas Bhatewara vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64) 2358d1a890faSShreyas Bhatewara { 2359d1a890faSShreyas Bhatewara int err; 2360d1a890faSShreyas Bhatewara unsigned long mmio_start, mmio_len; 2361d1a890faSShreyas Bhatewara struct pci_dev *pdev = adapter->pdev; 2362d1a890faSShreyas Bhatewara 2363d1a890faSShreyas Bhatewara err = pci_enable_device(pdev); 2364d1a890faSShreyas Bhatewara if (err) { 2365d1a890faSShreyas Bhatewara printk(KERN_ERR "Failed to enable adapter %s: error %d\n", 2366d1a890faSShreyas Bhatewara pci_name(pdev), err); 2367d1a890faSShreyas Bhatewara return err; 2368d1a890faSShreyas Bhatewara } 2369d1a890faSShreyas Bhatewara 2370d1a890faSShreyas Bhatewara if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) { 2371d1a890faSShreyas Bhatewara if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) { 2372d1a890faSShreyas Bhatewara printk(KERN_ERR "pci_set_consistent_dma_mask failed " 2373d1a890faSShreyas Bhatewara "for adapter %s\n", pci_name(pdev)); 2374d1a890faSShreyas Bhatewara err = -EIO; 2375d1a890faSShreyas Bhatewara goto err_set_mask; 2376d1a890faSShreyas Bhatewara } 2377d1a890faSShreyas Bhatewara *dma64 = true; 2378d1a890faSShreyas Bhatewara } else { 2379d1a890faSShreyas Bhatewara if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) { 2380d1a890faSShreyas Bhatewara printk(KERN_ERR "pci_set_dma_mask failed for adapter " 2381d1a890faSShreyas Bhatewara "%s\n", pci_name(pdev)); 2382d1a890faSShreyas Bhatewara err = -EIO; 2383d1a890faSShreyas Bhatewara goto err_set_mask; 2384d1a890faSShreyas Bhatewara } 2385d1a890faSShreyas Bhatewara *dma64 = false; 2386d1a890faSShreyas Bhatewara } 2387d1a890faSShreyas Bhatewara 2388d1a890faSShreyas Bhatewara err = pci_request_selected_regions(pdev, (1 << 2) - 1, 2389d1a890faSShreyas Bhatewara vmxnet3_driver_name); 2390d1a890faSShreyas Bhatewara if (err) { 2391d1a890faSShreyas Bhatewara printk(KERN_ERR "Failed to request region for adapter %s: " 2392d1a890faSShreyas Bhatewara "error %d\n", pci_name(pdev), err); 2393d1a890faSShreyas Bhatewara goto err_set_mask; 2394d1a890faSShreyas Bhatewara } 2395d1a890faSShreyas Bhatewara 2396d1a890faSShreyas Bhatewara pci_set_master(pdev); 2397d1a890faSShreyas Bhatewara 2398d1a890faSShreyas Bhatewara mmio_start = pci_resource_start(pdev, 0); 2399d1a890faSShreyas Bhatewara mmio_len = pci_resource_len(pdev, 0); 2400d1a890faSShreyas Bhatewara adapter->hw_addr0 = ioremap(mmio_start, mmio_len); 2401d1a890faSShreyas Bhatewara if (!adapter->hw_addr0) { 2402d1a890faSShreyas Bhatewara printk(KERN_ERR "Failed to map bar0 for adapter %s\n", 2403d1a890faSShreyas Bhatewara pci_name(pdev)); 2404d1a890faSShreyas Bhatewara err = -EIO; 2405d1a890faSShreyas Bhatewara goto err_ioremap; 2406d1a890faSShreyas Bhatewara } 2407d1a890faSShreyas Bhatewara 2408d1a890faSShreyas Bhatewara mmio_start = pci_resource_start(pdev, 1); 2409d1a890faSShreyas Bhatewara mmio_len = pci_resource_len(pdev, 1); 2410d1a890faSShreyas Bhatewara adapter->hw_addr1 = ioremap(mmio_start, mmio_len); 2411d1a890faSShreyas Bhatewara if (!adapter->hw_addr1) { 2412d1a890faSShreyas Bhatewara printk(KERN_ERR "Failed to map bar1 for adapter %s\n", 2413d1a890faSShreyas Bhatewara pci_name(pdev)); 2414d1a890faSShreyas Bhatewara err = -EIO; 2415d1a890faSShreyas Bhatewara goto err_bar1; 2416d1a890faSShreyas Bhatewara } 2417d1a890faSShreyas Bhatewara return 0; 2418d1a890faSShreyas Bhatewara 2419d1a890faSShreyas Bhatewara err_bar1: 2420d1a890faSShreyas Bhatewara iounmap(adapter->hw_addr0); 2421d1a890faSShreyas Bhatewara err_ioremap: 2422d1a890faSShreyas Bhatewara pci_release_selected_regions(pdev, (1 << 2) - 1); 2423d1a890faSShreyas Bhatewara err_set_mask: 2424d1a890faSShreyas Bhatewara pci_disable_device(pdev); 2425d1a890faSShreyas Bhatewara return err; 2426d1a890faSShreyas Bhatewara } 2427d1a890faSShreyas Bhatewara 2428d1a890faSShreyas Bhatewara 2429d1a890faSShreyas Bhatewara static void 2430d1a890faSShreyas Bhatewara vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter) 2431d1a890faSShreyas Bhatewara { 2432d1a890faSShreyas Bhatewara BUG_ON(!adapter->pdev); 2433d1a890faSShreyas Bhatewara 2434d1a890faSShreyas Bhatewara iounmap(adapter->hw_addr0); 2435d1a890faSShreyas Bhatewara iounmap(adapter->hw_addr1); 2436d1a890faSShreyas Bhatewara pci_release_selected_regions(adapter->pdev, (1 << 2) - 1); 2437d1a890faSShreyas Bhatewara pci_disable_device(adapter->pdev); 2438d1a890faSShreyas Bhatewara } 2439d1a890faSShreyas Bhatewara 2440d1a890faSShreyas Bhatewara 2441d1a890faSShreyas Bhatewara static void 2442d1a890faSShreyas Bhatewara vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter) 2443d1a890faSShreyas Bhatewara { 244409c5088eSShreyas Bhatewara size_t sz, i, ring0_size, ring1_size, comp_size; 244509c5088eSShreyas Bhatewara struct vmxnet3_rx_queue *rq = &adapter->rx_queue[0]; 244609c5088eSShreyas Bhatewara 2447d1a890faSShreyas Bhatewara 2448d1a890faSShreyas Bhatewara if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE - 2449d1a890faSShreyas Bhatewara VMXNET3_MAX_ETH_HDR_SIZE) { 2450d1a890faSShreyas Bhatewara adapter->skb_buf_size = adapter->netdev->mtu + 2451d1a890faSShreyas Bhatewara VMXNET3_MAX_ETH_HDR_SIZE; 2452d1a890faSShreyas Bhatewara if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE) 2453d1a890faSShreyas Bhatewara adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE; 2454d1a890faSShreyas Bhatewara 2455d1a890faSShreyas Bhatewara adapter->rx_buf_per_pkt = 1; 2456d1a890faSShreyas Bhatewara } else { 2457d1a890faSShreyas Bhatewara adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE; 2458d1a890faSShreyas Bhatewara sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE + 2459d1a890faSShreyas Bhatewara VMXNET3_MAX_ETH_HDR_SIZE; 2460d1a890faSShreyas Bhatewara adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE; 2461d1a890faSShreyas Bhatewara } 2462d1a890faSShreyas Bhatewara 2463d1a890faSShreyas Bhatewara /* 2464d1a890faSShreyas Bhatewara * for simplicity, force the ring0 size to be a multiple of 2465d1a890faSShreyas Bhatewara * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN 2466d1a890faSShreyas Bhatewara */ 2467d1a890faSShreyas Bhatewara sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN; 246809c5088eSShreyas Bhatewara ring0_size = adapter->rx_queue[0].rx_ring[0].size; 246909c5088eSShreyas Bhatewara ring0_size = (ring0_size + sz - 1) / sz * sz; 2470a53255d3SShreyas Bhatewara ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE / 247109c5088eSShreyas Bhatewara sz * sz); 247209c5088eSShreyas Bhatewara ring1_size = adapter->rx_queue[0].rx_ring[1].size; 247309c5088eSShreyas Bhatewara comp_size = ring0_size + ring1_size; 247409c5088eSShreyas Bhatewara 247509c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 247609c5088eSShreyas Bhatewara rq = &adapter->rx_queue[i]; 247709c5088eSShreyas Bhatewara rq->rx_ring[0].size = ring0_size; 247809c5088eSShreyas Bhatewara rq->rx_ring[1].size = ring1_size; 247909c5088eSShreyas Bhatewara rq->comp_ring.size = comp_size; 248009c5088eSShreyas Bhatewara } 2481d1a890faSShreyas Bhatewara } 2482d1a890faSShreyas Bhatewara 2483d1a890faSShreyas Bhatewara 2484d1a890faSShreyas Bhatewara int 2485d1a890faSShreyas Bhatewara vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size, 2486d1a890faSShreyas Bhatewara u32 rx_ring_size, u32 rx_ring2_size) 2487d1a890faSShreyas Bhatewara { 248809c5088eSShreyas Bhatewara int err = 0, i; 2489d1a890faSShreyas Bhatewara 249009c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) { 249109c5088eSShreyas Bhatewara struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i]; 249209c5088eSShreyas Bhatewara tq->tx_ring.size = tx_ring_size; 249309c5088eSShreyas Bhatewara tq->data_ring.size = tx_ring_size; 249409c5088eSShreyas Bhatewara tq->comp_ring.size = tx_ring_size; 249509c5088eSShreyas Bhatewara tq->shared = &adapter->tqd_start[i].ctrl; 249609c5088eSShreyas Bhatewara tq->stopped = true; 249709c5088eSShreyas Bhatewara tq->adapter = adapter; 249809c5088eSShreyas Bhatewara tq->qid = i; 249909c5088eSShreyas Bhatewara err = vmxnet3_tq_create(tq, adapter); 250009c5088eSShreyas Bhatewara /* 250109c5088eSShreyas Bhatewara * Too late to change num_tx_queues. We cannot do away with 250209c5088eSShreyas Bhatewara * lesser number of queues than what we asked for 250309c5088eSShreyas Bhatewara */ 2504d1a890faSShreyas Bhatewara if (err) 250509c5088eSShreyas Bhatewara goto queue_err; 250609c5088eSShreyas Bhatewara } 2507d1a890faSShreyas Bhatewara 250809c5088eSShreyas Bhatewara adapter->rx_queue[0].rx_ring[0].size = rx_ring_size; 250909c5088eSShreyas Bhatewara adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size; 2510d1a890faSShreyas Bhatewara vmxnet3_adjust_rx_ring_size(adapter); 251109c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 251209c5088eSShreyas Bhatewara struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 251309c5088eSShreyas Bhatewara /* qid and qid2 for rx queues will be assigned later when num 251409c5088eSShreyas Bhatewara * of rx queues is finalized after allocating intrs */ 251509c5088eSShreyas Bhatewara rq->shared = &adapter->rqd_start[i].ctrl; 251609c5088eSShreyas Bhatewara rq->adapter = adapter; 251709c5088eSShreyas Bhatewara err = vmxnet3_rq_create(rq, adapter); 251809c5088eSShreyas Bhatewara if (err) { 251909c5088eSShreyas Bhatewara if (i == 0) { 252009c5088eSShreyas Bhatewara printk(KERN_ERR "Could not allocate any rx" 252109c5088eSShreyas Bhatewara "queues. Aborting.\n"); 252209c5088eSShreyas Bhatewara goto queue_err; 252309c5088eSShreyas Bhatewara } else { 252409c5088eSShreyas Bhatewara printk(KERN_INFO "Number of rx queues changed " 252509c5088eSShreyas Bhatewara "to : %d.\n", i); 252609c5088eSShreyas Bhatewara adapter->num_rx_queues = i; 252709c5088eSShreyas Bhatewara err = 0; 252809c5088eSShreyas Bhatewara break; 252909c5088eSShreyas Bhatewara } 253009c5088eSShreyas Bhatewara } 253109c5088eSShreyas Bhatewara } 253209c5088eSShreyas Bhatewara return err; 253309c5088eSShreyas Bhatewara queue_err: 253409c5088eSShreyas Bhatewara vmxnet3_tq_destroy_all(adapter); 2535d1a890faSShreyas Bhatewara return err; 2536d1a890faSShreyas Bhatewara } 2537d1a890faSShreyas Bhatewara 2538d1a890faSShreyas Bhatewara static int 2539d1a890faSShreyas Bhatewara vmxnet3_open(struct net_device *netdev) 2540d1a890faSShreyas Bhatewara { 2541d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter; 254209c5088eSShreyas Bhatewara int err, i; 2543d1a890faSShreyas Bhatewara 2544d1a890faSShreyas Bhatewara adapter = netdev_priv(netdev); 2545d1a890faSShreyas Bhatewara 254609c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) 254709c5088eSShreyas Bhatewara spin_lock_init(&adapter->tx_queue[i].tx_lock); 2548d1a890faSShreyas Bhatewara 2549d1a890faSShreyas Bhatewara err = vmxnet3_create_queues(adapter, VMXNET3_DEF_TX_RING_SIZE, 2550d1a890faSShreyas Bhatewara VMXNET3_DEF_RX_RING_SIZE, 2551d1a890faSShreyas Bhatewara VMXNET3_DEF_RX_RING_SIZE); 2552d1a890faSShreyas Bhatewara if (err) 2553d1a890faSShreyas Bhatewara goto queue_err; 2554d1a890faSShreyas Bhatewara 2555d1a890faSShreyas Bhatewara err = vmxnet3_activate_dev(adapter); 2556d1a890faSShreyas Bhatewara if (err) 2557d1a890faSShreyas Bhatewara goto activate_err; 2558d1a890faSShreyas Bhatewara 2559d1a890faSShreyas Bhatewara return 0; 2560d1a890faSShreyas Bhatewara 2561d1a890faSShreyas Bhatewara activate_err: 256209c5088eSShreyas Bhatewara vmxnet3_rq_destroy_all(adapter); 256309c5088eSShreyas Bhatewara vmxnet3_tq_destroy_all(adapter); 2564d1a890faSShreyas Bhatewara queue_err: 2565d1a890faSShreyas Bhatewara return err; 2566d1a890faSShreyas Bhatewara } 2567d1a890faSShreyas Bhatewara 2568d1a890faSShreyas Bhatewara 2569d1a890faSShreyas Bhatewara static int 2570d1a890faSShreyas Bhatewara vmxnet3_close(struct net_device *netdev) 2571d1a890faSShreyas Bhatewara { 2572d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2573d1a890faSShreyas Bhatewara 2574d1a890faSShreyas Bhatewara /* 2575d1a890faSShreyas Bhatewara * Reset_work may be in the middle of resetting the device, wait for its 2576d1a890faSShreyas Bhatewara * completion. 2577d1a890faSShreyas Bhatewara */ 2578d1a890faSShreyas Bhatewara while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 2579d1a890faSShreyas Bhatewara msleep(1); 2580d1a890faSShreyas Bhatewara 2581d1a890faSShreyas Bhatewara vmxnet3_quiesce_dev(adapter); 2582d1a890faSShreyas Bhatewara 258309c5088eSShreyas Bhatewara vmxnet3_rq_destroy_all(adapter); 258409c5088eSShreyas Bhatewara vmxnet3_tq_destroy_all(adapter); 2585d1a890faSShreyas Bhatewara 2586d1a890faSShreyas Bhatewara clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 2587d1a890faSShreyas Bhatewara 2588d1a890faSShreyas Bhatewara 2589d1a890faSShreyas Bhatewara return 0; 2590d1a890faSShreyas Bhatewara } 2591d1a890faSShreyas Bhatewara 2592d1a890faSShreyas Bhatewara 2593d1a890faSShreyas Bhatewara void 2594d1a890faSShreyas Bhatewara vmxnet3_force_close(struct vmxnet3_adapter *adapter) 2595d1a890faSShreyas Bhatewara { 259609c5088eSShreyas Bhatewara int i; 259709c5088eSShreyas Bhatewara 2598d1a890faSShreyas Bhatewara /* 2599d1a890faSShreyas Bhatewara * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise 2600d1a890faSShreyas Bhatewara * vmxnet3_close() will deadlock. 2601d1a890faSShreyas Bhatewara */ 2602d1a890faSShreyas Bhatewara BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)); 2603d1a890faSShreyas Bhatewara 2604d1a890faSShreyas Bhatewara /* we need to enable NAPI, otherwise dev_close will deadlock */ 260509c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) 260609c5088eSShreyas Bhatewara napi_enable(&adapter->rx_queue[i].napi); 2607d1a890faSShreyas Bhatewara dev_close(adapter->netdev); 2608d1a890faSShreyas Bhatewara } 2609d1a890faSShreyas Bhatewara 2610d1a890faSShreyas Bhatewara 2611d1a890faSShreyas Bhatewara static int 2612d1a890faSShreyas Bhatewara vmxnet3_change_mtu(struct net_device *netdev, int new_mtu) 2613d1a890faSShreyas Bhatewara { 2614d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2615d1a890faSShreyas Bhatewara int err = 0; 2616d1a890faSShreyas Bhatewara 2617d1a890faSShreyas Bhatewara if (new_mtu < VMXNET3_MIN_MTU || new_mtu > VMXNET3_MAX_MTU) 2618d1a890faSShreyas Bhatewara return -EINVAL; 2619d1a890faSShreyas Bhatewara 2620d1a890faSShreyas Bhatewara netdev->mtu = new_mtu; 2621d1a890faSShreyas Bhatewara 2622d1a890faSShreyas Bhatewara /* 2623d1a890faSShreyas Bhatewara * Reset_work may be in the middle of resetting the device, wait for its 2624d1a890faSShreyas Bhatewara * completion. 2625d1a890faSShreyas Bhatewara */ 2626d1a890faSShreyas Bhatewara while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 2627d1a890faSShreyas Bhatewara msleep(1); 2628d1a890faSShreyas Bhatewara 2629d1a890faSShreyas Bhatewara if (netif_running(netdev)) { 2630d1a890faSShreyas Bhatewara vmxnet3_quiesce_dev(adapter); 2631d1a890faSShreyas Bhatewara vmxnet3_reset_dev(adapter); 2632d1a890faSShreyas Bhatewara 2633d1a890faSShreyas Bhatewara /* we need to re-create the rx queue based on the new mtu */ 263409c5088eSShreyas Bhatewara vmxnet3_rq_destroy_all(adapter); 2635d1a890faSShreyas Bhatewara vmxnet3_adjust_rx_ring_size(adapter); 263609c5088eSShreyas Bhatewara err = vmxnet3_rq_create_all(adapter); 2637d1a890faSShreyas Bhatewara if (err) { 263809c5088eSShreyas Bhatewara printk(KERN_ERR "%s: failed to re-create rx queues," 2639d1a890faSShreyas Bhatewara " error %d. Closing it.\n", netdev->name, err); 2640d1a890faSShreyas Bhatewara goto out; 2641d1a890faSShreyas Bhatewara } 2642d1a890faSShreyas Bhatewara 2643d1a890faSShreyas Bhatewara err = vmxnet3_activate_dev(adapter); 2644d1a890faSShreyas Bhatewara if (err) { 2645d1a890faSShreyas Bhatewara printk(KERN_ERR "%s: failed to re-activate, error %d. " 2646d1a890faSShreyas Bhatewara "Closing it\n", netdev->name, err); 2647d1a890faSShreyas Bhatewara goto out; 2648d1a890faSShreyas Bhatewara } 2649d1a890faSShreyas Bhatewara } 2650d1a890faSShreyas Bhatewara 2651d1a890faSShreyas Bhatewara out: 2652d1a890faSShreyas Bhatewara clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 2653d1a890faSShreyas Bhatewara if (err) 2654d1a890faSShreyas Bhatewara vmxnet3_force_close(adapter); 2655d1a890faSShreyas Bhatewara 2656d1a890faSShreyas Bhatewara return err; 2657d1a890faSShreyas Bhatewara } 2658d1a890faSShreyas Bhatewara 2659d1a890faSShreyas Bhatewara 2660d1a890faSShreyas Bhatewara static void 2661d1a890faSShreyas Bhatewara vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64) 2662d1a890faSShreyas Bhatewara { 2663d1a890faSShreyas Bhatewara struct net_device *netdev = adapter->netdev; 2664d1a890faSShreyas Bhatewara 2665a0d2730cSMichał Mirosław netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM | 2666a0d2730cSMichał Mirosław NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_TX | 266772e85c45SJesse Gross NETIF_F_HW_VLAN_RX | NETIF_F_TSO | NETIF_F_TSO6 | 266872e85c45SJesse Gross NETIF_F_LRO; 2669a0d2730cSMichał Mirosław if (dma64) 2670ebbf9295SShreyas Bhatewara netdev->hw_features |= NETIF_F_HIGHDMA; 267172e85c45SJesse Gross netdev->vlan_features = netdev->hw_features & 267272e85c45SJesse Gross ~(NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX); 267372e85c45SJesse Gross netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_FILTER; 2674d1a890faSShreyas Bhatewara } 2675d1a890faSShreyas Bhatewara 2676d1a890faSShreyas Bhatewara 2677d1a890faSShreyas Bhatewara static void 2678d1a890faSShreyas Bhatewara vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac) 2679d1a890faSShreyas Bhatewara { 2680d1a890faSShreyas Bhatewara u32 tmp; 2681d1a890faSShreyas Bhatewara 2682d1a890faSShreyas Bhatewara tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL); 2683d1a890faSShreyas Bhatewara *(u32 *)mac = tmp; 2684d1a890faSShreyas Bhatewara 2685d1a890faSShreyas Bhatewara tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH); 2686d1a890faSShreyas Bhatewara mac[4] = tmp & 0xff; 2687d1a890faSShreyas Bhatewara mac[5] = (tmp >> 8) & 0xff; 2688d1a890faSShreyas Bhatewara } 2689d1a890faSShreyas Bhatewara 269009c5088eSShreyas Bhatewara #ifdef CONFIG_PCI_MSI 269109c5088eSShreyas Bhatewara 269209c5088eSShreyas Bhatewara /* 269309c5088eSShreyas Bhatewara * Enable MSIx vectors. 269409c5088eSShreyas Bhatewara * Returns : 269509c5088eSShreyas Bhatewara * 0 on successful enabling of required vectors, 269625985edcSLucas De Marchi * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required 269709c5088eSShreyas Bhatewara * could be enabled. 269809c5088eSShreyas Bhatewara * number of vectors which can be enabled otherwise (this number is smaller 269909c5088eSShreyas Bhatewara * than VMXNET3_LINUX_MIN_MSIX_VECT) 270009c5088eSShreyas Bhatewara */ 270109c5088eSShreyas Bhatewara 270209c5088eSShreyas Bhatewara static int 270309c5088eSShreyas Bhatewara vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, 270409c5088eSShreyas Bhatewara int vectors) 270509c5088eSShreyas Bhatewara { 270609c5088eSShreyas Bhatewara int err = 0, vector_threshold; 270709c5088eSShreyas Bhatewara vector_threshold = VMXNET3_LINUX_MIN_MSIX_VECT; 270809c5088eSShreyas Bhatewara 270909c5088eSShreyas Bhatewara while (vectors >= vector_threshold) { 271009c5088eSShreyas Bhatewara err = pci_enable_msix(adapter->pdev, adapter->intr.msix_entries, 271109c5088eSShreyas Bhatewara vectors); 271209c5088eSShreyas Bhatewara if (!err) { 271309c5088eSShreyas Bhatewara adapter->intr.num_intrs = vectors; 271409c5088eSShreyas Bhatewara return 0; 271509c5088eSShreyas Bhatewara } else if (err < 0) { 27164bad25faSStephen Hemminger dev_err(&adapter->netdev->dev, 27174c1dc80aSShreyas Bhatewara "Failed to enable MSI-X, error: %d\n", err); 271809c5088eSShreyas Bhatewara vectors = 0; 271909c5088eSShreyas Bhatewara } else if (err < vector_threshold) { 272009c5088eSShreyas Bhatewara break; 272109c5088eSShreyas Bhatewara } else { 272209c5088eSShreyas Bhatewara /* If fails to enable required number of MSI-x vectors 27237e96fbf2SShreyas Bhatewara * try enabling minimum number of vectors required. 272409c5088eSShreyas Bhatewara */ 27254bad25faSStephen Hemminger dev_err(&adapter->netdev->dev, 27264c1dc80aSShreyas Bhatewara "Failed to enable %d MSI-X, trying %d instead\n", 27274c1dc80aSShreyas Bhatewara vectors, vector_threshold); 272809c5088eSShreyas Bhatewara vectors = vector_threshold; 272909c5088eSShreyas Bhatewara } 273009c5088eSShreyas Bhatewara } 273109c5088eSShreyas Bhatewara 27324bad25faSStephen Hemminger dev_info(&adapter->pdev->dev, 27334bad25faSStephen Hemminger "Number of MSI-X interrupts which can be allocated " 27344bad25faSStephen Hemminger "is lower than min threshold required.\n"); 273509c5088eSShreyas Bhatewara return err; 273609c5088eSShreyas Bhatewara } 273709c5088eSShreyas Bhatewara 273809c5088eSShreyas Bhatewara 273909c5088eSShreyas Bhatewara #endif /* CONFIG_PCI_MSI */ 2740d1a890faSShreyas Bhatewara 2741d1a890faSShreyas Bhatewara static void 2742d1a890faSShreyas Bhatewara vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter) 2743d1a890faSShreyas Bhatewara { 2744d1a890faSShreyas Bhatewara u32 cfg; 2745e328d410SRoland Dreier unsigned long flags; 2746d1a890faSShreyas Bhatewara 2747d1a890faSShreyas Bhatewara /* intr settings */ 2748e328d410SRoland Dreier spin_lock_irqsave(&adapter->cmd_lock, flags); 2749d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2750d1a890faSShreyas Bhatewara VMXNET3_CMD_GET_CONF_INTR); 2751d1a890faSShreyas Bhatewara cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 2752e328d410SRoland Dreier spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2753d1a890faSShreyas Bhatewara adapter->intr.type = cfg & 0x3; 2754d1a890faSShreyas Bhatewara adapter->intr.mask_mode = (cfg >> 2) & 0x3; 2755d1a890faSShreyas Bhatewara 2756d1a890faSShreyas Bhatewara if (adapter->intr.type == VMXNET3_IT_AUTO) { 27570bdc0d70SShreyas Bhatewara adapter->intr.type = VMXNET3_IT_MSIX; 27580bdc0d70SShreyas Bhatewara } 2759d1a890faSShreyas Bhatewara 27608f7e524cSRandy Dunlap #ifdef CONFIG_PCI_MSI 27610bdc0d70SShreyas Bhatewara if (adapter->intr.type == VMXNET3_IT_MSIX) { 276209c5088eSShreyas Bhatewara int vector, err = 0; 27630bdc0d70SShreyas Bhatewara 276409c5088eSShreyas Bhatewara adapter->intr.num_intrs = (adapter->share_intr == 276509c5088eSShreyas Bhatewara VMXNET3_INTR_TXSHARE) ? 1 : 276609c5088eSShreyas Bhatewara adapter->num_tx_queues; 276709c5088eSShreyas Bhatewara adapter->intr.num_intrs += (adapter->share_intr == 276809c5088eSShreyas Bhatewara VMXNET3_INTR_BUDDYSHARE) ? 0 : 276909c5088eSShreyas Bhatewara adapter->num_rx_queues; 277009c5088eSShreyas Bhatewara adapter->intr.num_intrs += 1; /* for link event */ 277109c5088eSShreyas Bhatewara 277209c5088eSShreyas Bhatewara adapter->intr.num_intrs = (adapter->intr.num_intrs > 277309c5088eSShreyas Bhatewara VMXNET3_LINUX_MIN_MSIX_VECT 277409c5088eSShreyas Bhatewara ? adapter->intr.num_intrs : 277509c5088eSShreyas Bhatewara VMXNET3_LINUX_MIN_MSIX_VECT); 277609c5088eSShreyas Bhatewara 277709c5088eSShreyas Bhatewara for (vector = 0; vector < adapter->intr.num_intrs; vector++) 277809c5088eSShreyas Bhatewara adapter->intr.msix_entries[vector].entry = vector; 277909c5088eSShreyas Bhatewara 278009c5088eSShreyas Bhatewara err = vmxnet3_acquire_msix_vectors(adapter, 278109c5088eSShreyas Bhatewara adapter->intr.num_intrs); 278209c5088eSShreyas Bhatewara /* If we cannot allocate one MSIx vector per queue 278309c5088eSShreyas Bhatewara * then limit the number of rx queues to 1 278409c5088eSShreyas Bhatewara */ 278509c5088eSShreyas Bhatewara if (err == VMXNET3_LINUX_MIN_MSIX_VECT) { 278609c5088eSShreyas Bhatewara if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE 27877e96fbf2SShreyas Bhatewara || adapter->num_rx_queues != 1) { 278809c5088eSShreyas Bhatewara adapter->share_intr = VMXNET3_INTR_TXSHARE; 278909c5088eSShreyas Bhatewara printk(KERN_ERR "Number of rx queues : 1\n"); 279009c5088eSShreyas Bhatewara adapter->num_rx_queues = 1; 279109c5088eSShreyas Bhatewara adapter->intr.num_intrs = 279209c5088eSShreyas Bhatewara VMXNET3_LINUX_MIN_MSIX_VECT; 279309c5088eSShreyas Bhatewara } 2794d1a890faSShreyas Bhatewara return; 2795d1a890faSShreyas Bhatewara } 279609c5088eSShreyas Bhatewara if (!err) 279709c5088eSShreyas Bhatewara return; 279809c5088eSShreyas Bhatewara 279909c5088eSShreyas Bhatewara /* If we cannot allocate MSIx vectors use only one rx queue */ 28004bad25faSStephen Hemminger dev_info(&adapter->pdev->dev, 28014bad25faSStephen Hemminger "Failed to enable MSI-X, error %d. " 28024bad25faSStephen Hemminger "Limiting #rx queues to 1, try MSI.\n", err); 280309c5088eSShreyas Bhatewara 28040bdc0d70SShreyas Bhatewara adapter->intr.type = VMXNET3_IT_MSI; 28050bdc0d70SShreyas Bhatewara } 2806d1a890faSShreyas Bhatewara 28070bdc0d70SShreyas Bhatewara if (adapter->intr.type == VMXNET3_IT_MSI) { 28080bdc0d70SShreyas Bhatewara int err; 2809d1a890faSShreyas Bhatewara err = pci_enable_msi(adapter->pdev); 2810d1a890faSShreyas Bhatewara if (!err) { 281109c5088eSShreyas Bhatewara adapter->num_rx_queues = 1; 2812d1a890faSShreyas Bhatewara adapter->intr.num_intrs = 1; 2813d1a890faSShreyas Bhatewara return; 2814d1a890faSShreyas Bhatewara } 2815d1a890faSShreyas Bhatewara } 28160bdc0d70SShreyas Bhatewara #endif /* CONFIG_PCI_MSI */ 2817d1a890faSShreyas Bhatewara 281809c5088eSShreyas Bhatewara adapter->num_rx_queues = 1; 281909c5088eSShreyas Bhatewara printk(KERN_INFO "Using INTx interrupt, #Rx queues: 1.\n"); 2820d1a890faSShreyas Bhatewara adapter->intr.type = VMXNET3_IT_INTX; 2821d1a890faSShreyas Bhatewara 2822d1a890faSShreyas Bhatewara /* INT-X related setting */ 2823d1a890faSShreyas Bhatewara adapter->intr.num_intrs = 1; 2824d1a890faSShreyas Bhatewara } 2825d1a890faSShreyas Bhatewara 2826d1a890faSShreyas Bhatewara 2827d1a890faSShreyas Bhatewara static void 2828d1a890faSShreyas Bhatewara vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter) 2829d1a890faSShreyas Bhatewara { 2830d1a890faSShreyas Bhatewara if (adapter->intr.type == VMXNET3_IT_MSIX) 2831d1a890faSShreyas Bhatewara pci_disable_msix(adapter->pdev); 2832d1a890faSShreyas Bhatewara else if (adapter->intr.type == VMXNET3_IT_MSI) 2833d1a890faSShreyas Bhatewara pci_disable_msi(adapter->pdev); 2834d1a890faSShreyas Bhatewara else 2835d1a890faSShreyas Bhatewara BUG_ON(adapter->intr.type != VMXNET3_IT_INTX); 2836d1a890faSShreyas Bhatewara } 2837d1a890faSShreyas Bhatewara 2838d1a890faSShreyas Bhatewara 2839d1a890faSShreyas Bhatewara static void 2840d1a890faSShreyas Bhatewara vmxnet3_tx_timeout(struct net_device *netdev) 2841d1a890faSShreyas Bhatewara { 2842d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2843d1a890faSShreyas Bhatewara adapter->tx_timeout_count++; 2844d1a890faSShreyas Bhatewara 2845d1a890faSShreyas Bhatewara printk(KERN_ERR "%s: tx hang\n", adapter->netdev->name); 2846d1a890faSShreyas Bhatewara schedule_work(&adapter->work); 284709c5088eSShreyas Bhatewara netif_wake_queue(adapter->netdev); 2848d1a890faSShreyas Bhatewara } 2849d1a890faSShreyas Bhatewara 2850d1a890faSShreyas Bhatewara 2851d1a890faSShreyas Bhatewara static void 2852d1a890faSShreyas Bhatewara vmxnet3_reset_work(struct work_struct *data) 2853d1a890faSShreyas Bhatewara { 2854d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter; 2855d1a890faSShreyas Bhatewara 2856d1a890faSShreyas Bhatewara adapter = container_of(data, struct vmxnet3_adapter, work); 2857d1a890faSShreyas Bhatewara 2858d1a890faSShreyas Bhatewara /* if another thread is resetting the device, no need to proceed */ 2859d1a890faSShreyas Bhatewara if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 2860d1a890faSShreyas Bhatewara return; 2861d1a890faSShreyas Bhatewara 2862d1a890faSShreyas Bhatewara /* if the device is closed, we must leave it alone */ 2863d9a5f210SShreyas Bhatewara rtnl_lock(); 2864d1a890faSShreyas Bhatewara if (netif_running(adapter->netdev)) { 2865d1a890faSShreyas Bhatewara printk(KERN_INFO "%s: resetting\n", adapter->netdev->name); 2866d1a890faSShreyas Bhatewara vmxnet3_quiesce_dev(adapter); 2867d1a890faSShreyas Bhatewara vmxnet3_reset_dev(adapter); 2868d1a890faSShreyas Bhatewara vmxnet3_activate_dev(adapter); 2869d1a890faSShreyas Bhatewara } else { 2870d1a890faSShreyas Bhatewara printk(KERN_INFO "%s: already closed\n", adapter->netdev->name); 2871d1a890faSShreyas Bhatewara } 2872d9a5f210SShreyas Bhatewara rtnl_unlock(); 2873d1a890faSShreyas Bhatewara 2874d1a890faSShreyas Bhatewara clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 2875d1a890faSShreyas Bhatewara } 2876d1a890faSShreyas Bhatewara 2877d1a890faSShreyas Bhatewara 28783a4751a3SBill Pemberton static int 2879d1a890faSShreyas Bhatewara vmxnet3_probe_device(struct pci_dev *pdev, 2880d1a890faSShreyas Bhatewara const struct pci_device_id *id) 2881d1a890faSShreyas Bhatewara { 2882d1a890faSShreyas Bhatewara static const struct net_device_ops vmxnet3_netdev_ops = { 2883d1a890faSShreyas Bhatewara .ndo_open = vmxnet3_open, 2884d1a890faSShreyas Bhatewara .ndo_stop = vmxnet3_close, 2885d1a890faSShreyas Bhatewara .ndo_start_xmit = vmxnet3_xmit_frame, 2886d1a890faSShreyas Bhatewara .ndo_set_mac_address = vmxnet3_set_mac_addr, 2887d1a890faSShreyas Bhatewara .ndo_change_mtu = vmxnet3_change_mtu, 2888a0d2730cSMichał Mirosław .ndo_set_features = vmxnet3_set_features, 288995305f6cSstephen hemminger .ndo_get_stats64 = vmxnet3_get_stats64, 2890d1a890faSShreyas Bhatewara .ndo_tx_timeout = vmxnet3_tx_timeout, 2891afc4b13dSJiri Pirko .ndo_set_rx_mode = vmxnet3_set_mc, 2892d1a890faSShreyas Bhatewara .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid, 2893d1a890faSShreyas Bhatewara .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid, 2894d1a890faSShreyas Bhatewara #ifdef CONFIG_NET_POLL_CONTROLLER 2895d1a890faSShreyas Bhatewara .ndo_poll_controller = vmxnet3_netpoll, 2896d1a890faSShreyas Bhatewara #endif 2897d1a890faSShreyas Bhatewara }; 2898d1a890faSShreyas Bhatewara int err; 2899d1a890faSShreyas Bhatewara bool dma64 = false; /* stupid gcc */ 2900d1a890faSShreyas Bhatewara u32 ver; 2901d1a890faSShreyas Bhatewara struct net_device *netdev; 2902d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter; 2903d1a890faSShreyas Bhatewara u8 mac[ETH_ALEN]; 290409c5088eSShreyas Bhatewara int size; 290509c5088eSShreyas Bhatewara int num_tx_queues; 290609c5088eSShreyas Bhatewara int num_rx_queues; 2907d1a890faSShreyas Bhatewara 2908e154b639SShreyas Bhatewara if (!pci_msi_enabled()) 2909e154b639SShreyas Bhatewara enable_mq = 0; 2910e154b639SShreyas Bhatewara 291109c5088eSShreyas Bhatewara #ifdef VMXNET3_RSS 291209c5088eSShreyas Bhatewara if (enable_mq) 291309c5088eSShreyas Bhatewara num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES, 291409c5088eSShreyas Bhatewara (int)num_online_cpus()); 291509c5088eSShreyas Bhatewara else 291609c5088eSShreyas Bhatewara #endif 291709c5088eSShreyas Bhatewara num_rx_queues = 1; 2918eebb02b1SShreyas Bhatewara num_rx_queues = rounddown_pow_of_two(num_rx_queues); 291909c5088eSShreyas Bhatewara 292009c5088eSShreyas Bhatewara if (enable_mq) 292109c5088eSShreyas Bhatewara num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES, 292209c5088eSShreyas Bhatewara (int)num_online_cpus()); 292309c5088eSShreyas Bhatewara else 292409c5088eSShreyas Bhatewara num_tx_queues = 1; 292509c5088eSShreyas Bhatewara 2926eebb02b1SShreyas Bhatewara num_tx_queues = rounddown_pow_of_two(num_tx_queues); 292709c5088eSShreyas Bhatewara netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter), 292809c5088eSShreyas Bhatewara max(num_tx_queues, num_rx_queues)); 292909c5088eSShreyas Bhatewara printk(KERN_INFO "# of Tx queues : %d, # of Rx queues : %d\n", 293009c5088eSShreyas Bhatewara num_tx_queues, num_rx_queues); 293109c5088eSShreyas Bhatewara 293241de8d4cSJoe Perches if (!netdev) 2933d1a890faSShreyas Bhatewara return -ENOMEM; 2934d1a890faSShreyas Bhatewara 2935d1a890faSShreyas Bhatewara pci_set_drvdata(pdev, netdev); 2936d1a890faSShreyas Bhatewara adapter = netdev_priv(netdev); 2937d1a890faSShreyas Bhatewara adapter->netdev = netdev; 2938d1a890faSShreyas Bhatewara adapter->pdev = pdev; 2939d1a890faSShreyas Bhatewara 294083d0feffSShreyas Bhatewara spin_lock_init(&adapter->cmd_lock); 2941d1a890faSShreyas Bhatewara adapter->shared = pci_alloc_consistent(adapter->pdev, 2942d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_DriverShared), 2943d1a890faSShreyas Bhatewara &adapter->shared_pa); 2944d1a890faSShreyas Bhatewara if (!adapter->shared) { 2945d1a890faSShreyas Bhatewara printk(KERN_ERR "Failed to allocate memory for %s\n", 2946d1a890faSShreyas Bhatewara pci_name(pdev)); 2947d1a890faSShreyas Bhatewara err = -ENOMEM; 2948d1a890faSShreyas Bhatewara goto err_alloc_shared; 2949d1a890faSShreyas Bhatewara } 2950d1a890faSShreyas Bhatewara 295109c5088eSShreyas Bhatewara adapter->num_rx_queues = num_rx_queues; 295209c5088eSShreyas Bhatewara adapter->num_tx_queues = num_tx_queues; 295309c5088eSShreyas Bhatewara 295409c5088eSShreyas Bhatewara size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues; 295509c5088eSShreyas Bhatewara size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues; 295609c5088eSShreyas Bhatewara adapter->tqd_start = pci_alloc_consistent(adapter->pdev, size, 2957d1a890faSShreyas Bhatewara &adapter->queue_desc_pa); 2958d1a890faSShreyas Bhatewara 2959d1a890faSShreyas Bhatewara if (!adapter->tqd_start) { 2960d1a890faSShreyas Bhatewara printk(KERN_ERR "Failed to allocate memory for %s\n", 2961d1a890faSShreyas Bhatewara pci_name(pdev)); 2962d1a890faSShreyas Bhatewara err = -ENOMEM; 2963d1a890faSShreyas Bhatewara goto err_alloc_queue_desc; 2964d1a890faSShreyas Bhatewara } 296509c5088eSShreyas Bhatewara adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start + 296609c5088eSShreyas Bhatewara adapter->num_tx_queues); 2967d1a890faSShreyas Bhatewara 2968d1a890faSShreyas Bhatewara adapter->pm_conf = kmalloc(sizeof(struct Vmxnet3_PMConf), GFP_KERNEL); 2969d1a890faSShreyas Bhatewara if (adapter->pm_conf == NULL) { 2970d1a890faSShreyas Bhatewara err = -ENOMEM; 2971d1a890faSShreyas Bhatewara goto err_alloc_pm; 2972d1a890faSShreyas Bhatewara } 2973d1a890faSShreyas Bhatewara 297409c5088eSShreyas Bhatewara #ifdef VMXNET3_RSS 297509c5088eSShreyas Bhatewara 297609c5088eSShreyas Bhatewara adapter->rss_conf = kmalloc(sizeof(struct UPT1_RSSConf), GFP_KERNEL); 297709c5088eSShreyas Bhatewara if (adapter->rss_conf == NULL) { 297809c5088eSShreyas Bhatewara err = -ENOMEM; 297909c5088eSShreyas Bhatewara goto err_alloc_rss; 298009c5088eSShreyas Bhatewara } 298109c5088eSShreyas Bhatewara #endif /* VMXNET3_RSS */ 298209c5088eSShreyas Bhatewara 2983d1a890faSShreyas Bhatewara err = vmxnet3_alloc_pci_resources(adapter, &dma64); 2984d1a890faSShreyas Bhatewara if (err < 0) 2985d1a890faSShreyas Bhatewara goto err_alloc_pci; 2986d1a890faSShreyas Bhatewara 2987d1a890faSShreyas Bhatewara ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS); 2988d1a890faSShreyas Bhatewara if (ver & 1) { 2989d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_VRRS, 1); 2990d1a890faSShreyas Bhatewara } else { 2991d1a890faSShreyas Bhatewara printk(KERN_ERR "Incompatible h/w version (0x%x) for adapter" 2992d1a890faSShreyas Bhatewara " %s\n", ver, pci_name(pdev)); 2993d1a890faSShreyas Bhatewara err = -EBUSY; 2994d1a890faSShreyas Bhatewara goto err_ver; 2995d1a890faSShreyas Bhatewara } 2996d1a890faSShreyas Bhatewara 2997d1a890faSShreyas Bhatewara ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS); 2998d1a890faSShreyas Bhatewara if (ver & 1) { 2999d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1); 3000d1a890faSShreyas Bhatewara } else { 3001d1a890faSShreyas Bhatewara printk(KERN_ERR "Incompatible upt version (0x%x) for " 3002d1a890faSShreyas Bhatewara "adapter %s\n", ver, pci_name(pdev)); 3003d1a890faSShreyas Bhatewara err = -EBUSY; 3004d1a890faSShreyas Bhatewara goto err_ver; 3005d1a890faSShreyas Bhatewara } 3006d1a890faSShreyas Bhatewara 3007e101e7ddSShreyas Bhatewara SET_NETDEV_DEV(netdev, &pdev->dev); 3008d1a890faSShreyas Bhatewara vmxnet3_declare_features(adapter, dma64); 3009d1a890faSShreyas Bhatewara 3010d1a890faSShreyas Bhatewara adapter->dev_number = atomic_read(&devices_found); 301109c5088eSShreyas Bhatewara 301209c5088eSShreyas Bhatewara adapter->share_intr = irq_share_mode; 301309c5088eSShreyas Bhatewara if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE && 301409c5088eSShreyas Bhatewara adapter->num_tx_queues != adapter->num_rx_queues) 301509c5088eSShreyas Bhatewara adapter->share_intr = VMXNET3_INTR_DONTSHARE; 301609c5088eSShreyas Bhatewara 3017d1a890faSShreyas Bhatewara vmxnet3_alloc_intr_resources(adapter); 3018d1a890faSShreyas Bhatewara 301909c5088eSShreyas Bhatewara #ifdef VMXNET3_RSS 302009c5088eSShreyas Bhatewara if (adapter->num_rx_queues > 1 && 302109c5088eSShreyas Bhatewara adapter->intr.type == VMXNET3_IT_MSIX) { 302209c5088eSShreyas Bhatewara adapter->rss = true; 302309c5088eSShreyas Bhatewara printk(KERN_INFO "RSS is enabled.\n"); 302409c5088eSShreyas Bhatewara } else { 302509c5088eSShreyas Bhatewara adapter->rss = false; 302609c5088eSShreyas Bhatewara } 302709c5088eSShreyas Bhatewara #endif 302809c5088eSShreyas Bhatewara 3029d1a890faSShreyas Bhatewara vmxnet3_read_mac_addr(adapter, mac); 3030d1a890faSShreyas Bhatewara memcpy(netdev->dev_addr, mac, netdev->addr_len); 3031d1a890faSShreyas Bhatewara 3032d1a890faSShreyas Bhatewara netdev->netdev_ops = &vmxnet3_netdev_ops; 3033d1a890faSShreyas Bhatewara vmxnet3_set_ethtool_ops(netdev); 303409c5088eSShreyas Bhatewara netdev->watchdog_timeo = 5 * HZ; 3035d1a890faSShreyas Bhatewara 3036d1a890faSShreyas Bhatewara INIT_WORK(&adapter->work, vmxnet3_reset_work); 3037e3bc4ffbSSteve Hodgson set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 3038d1a890faSShreyas Bhatewara 303909c5088eSShreyas Bhatewara if (adapter->intr.type == VMXNET3_IT_MSIX) { 304009c5088eSShreyas Bhatewara int i; 304109c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 304209c5088eSShreyas Bhatewara netif_napi_add(adapter->netdev, 304309c5088eSShreyas Bhatewara &adapter->rx_queue[i].napi, 304409c5088eSShreyas Bhatewara vmxnet3_poll_rx_only, 64); 304509c5088eSShreyas Bhatewara } 304609c5088eSShreyas Bhatewara } else { 304709c5088eSShreyas Bhatewara netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi, 304809c5088eSShreyas Bhatewara vmxnet3_poll, 64); 304909c5088eSShreyas Bhatewara } 305009c5088eSShreyas Bhatewara 305109c5088eSShreyas Bhatewara netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); 305209c5088eSShreyas Bhatewara netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues); 305309c5088eSShreyas Bhatewara 3054d1a890faSShreyas Bhatewara err = register_netdev(netdev); 3055d1a890faSShreyas Bhatewara 3056d1a890faSShreyas Bhatewara if (err) { 3057d1a890faSShreyas Bhatewara printk(KERN_ERR "Failed to register adapter %s\n", 3058d1a890faSShreyas Bhatewara pci_name(pdev)); 3059d1a890faSShreyas Bhatewara goto err_register; 3060d1a890faSShreyas Bhatewara } 3061d1a890faSShreyas Bhatewara 30624a1745fcSShreyas Bhatewara vmxnet3_check_link(adapter, false); 3063d1a890faSShreyas Bhatewara atomic_inc(&devices_found); 3064d1a890faSShreyas Bhatewara return 0; 3065d1a890faSShreyas Bhatewara 3066d1a890faSShreyas Bhatewara err_register: 3067d1a890faSShreyas Bhatewara vmxnet3_free_intr_resources(adapter); 3068d1a890faSShreyas Bhatewara err_ver: 3069d1a890faSShreyas Bhatewara vmxnet3_free_pci_resources(adapter); 3070d1a890faSShreyas Bhatewara err_alloc_pci: 307109c5088eSShreyas Bhatewara #ifdef VMXNET3_RSS 307209c5088eSShreyas Bhatewara kfree(adapter->rss_conf); 307309c5088eSShreyas Bhatewara err_alloc_rss: 307409c5088eSShreyas Bhatewara #endif 3075d1a890faSShreyas Bhatewara kfree(adapter->pm_conf); 3076d1a890faSShreyas Bhatewara err_alloc_pm: 307709c5088eSShreyas Bhatewara pci_free_consistent(adapter->pdev, size, adapter->tqd_start, 307809c5088eSShreyas Bhatewara adapter->queue_desc_pa); 3079d1a890faSShreyas Bhatewara err_alloc_queue_desc: 3080d1a890faSShreyas Bhatewara pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared), 3081d1a890faSShreyas Bhatewara adapter->shared, adapter->shared_pa); 3082d1a890faSShreyas Bhatewara err_alloc_shared: 3083d1a890faSShreyas Bhatewara pci_set_drvdata(pdev, NULL); 3084d1a890faSShreyas Bhatewara free_netdev(netdev); 3085d1a890faSShreyas Bhatewara return err; 3086d1a890faSShreyas Bhatewara } 3087d1a890faSShreyas Bhatewara 3088d1a890faSShreyas Bhatewara 30893a4751a3SBill Pemberton static void 3090d1a890faSShreyas Bhatewara vmxnet3_remove_device(struct pci_dev *pdev) 3091d1a890faSShreyas Bhatewara { 3092d1a890faSShreyas Bhatewara struct net_device *netdev = pci_get_drvdata(pdev); 3093d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 309409c5088eSShreyas Bhatewara int size = 0; 309509c5088eSShreyas Bhatewara int num_rx_queues; 309609c5088eSShreyas Bhatewara 309709c5088eSShreyas Bhatewara #ifdef VMXNET3_RSS 309809c5088eSShreyas Bhatewara if (enable_mq) 309909c5088eSShreyas Bhatewara num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES, 310009c5088eSShreyas Bhatewara (int)num_online_cpus()); 310109c5088eSShreyas Bhatewara else 310209c5088eSShreyas Bhatewara #endif 310309c5088eSShreyas Bhatewara num_rx_queues = 1; 3104eebb02b1SShreyas Bhatewara num_rx_queues = rounddown_pow_of_two(num_rx_queues); 3105d1a890faSShreyas Bhatewara 310623f333a2STejun Heo cancel_work_sync(&adapter->work); 3107d1a890faSShreyas Bhatewara 3108d1a890faSShreyas Bhatewara unregister_netdev(netdev); 3109d1a890faSShreyas Bhatewara 3110d1a890faSShreyas Bhatewara vmxnet3_free_intr_resources(adapter); 3111d1a890faSShreyas Bhatewara vmxnet3_free_pci_resources(adapter); 311209c5088eSShreyas Bhatewara #ifdef VMXNET3_RSS 311309c5088eSShreyas Bhatewara kfree(adapter->rss_conf); 311409c5088eSShreyas Bhatewara #endif 3115d1a890faSShreyas Bhatewara kfree(adapter->pm_conf); 311609c5088eSShreyas Bhatewara 311709c5088eSShreyas Bhatewara size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues; 311809c5088eSShreyas Bhatewara size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues; 311909c5088eSShreyas Bhatewara pci_free_consistent(adapter->pdev, size, adapter->tqd_start, 312009c5088eSShreyas Bhatewara adapter->queue_desc_pa); 3121d1a890faSShreyas Bhatewara pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared), 3122d1a890faSShreyas Bhatewara adapter->shared, adapter->shared_pa); 3123d1a890faSShreyas Bhatewara free_netdev(netdev); 3124d1a890faSShreyas Bhatewara } 3125d1a890faSShreyas Bhatewara 3126d1a890faSShreyas Bhatewara 3127d1a890faSShreyas Bhatewara #ifdef CONFIG_PM 3128d1a890faSShreyas Bhatewara 3129d1a890faSShreyas Bhatewara static int 3130d1a890faSShreyas Bhatewara vmxnet3_suspend(struct device *device) 3131d1a890faSShreyas Bhatewara { 3132d1a890faSShreyas Bhatewara struct pci_dev *pdev = to_pci_dev(device); 3133d1a890faSShreyas Bhatewara struct net_device *netdev = pci_get_drvdata(pdev); 3134d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3135d1a890faSShreyas Bhatewara struct Vmxnet3_PMConf *pmConf; 3136d1a890faSShreyas Bhatewara struct ethhdr *ehdr; 3137d1a890faSShreyas Bhatewara struct arphdr *ahdr; 3138d1a890faSShreyas Bhatewara u8 *arpreq; 3139d1a890faSShreyas Bhatewara struct in_device *in_dev; 3140d1a890faSShreyas Bhatewara struct in_ifaddr *ifa; 314183d0feffSShreyas Bhatewara unsigned long flags; 3142d1a890faSShreyas Bhatewara int i = 0; 3143d1a890faSShreyas Bhatewara 3144d1a890faSShreyas Bhatewara if (!netif_running(netdev)) 3145d1a890faSShreyas Bhatewara return 0; 3146d1a890faSShreyas Bhatewara 314751956cd6SShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) 314851956cd6SShreyas Bhatewara napi_disable(&adapter->rx_queue[i].napi); 314951956cd6SShreyas Bhatewara 3150d1a890faSShreyas Bhatewara vmxnet3_disable_all_intrs(adapter); 3151d1a890faSShreyas Bhatewara vmxnet3_free_irqs(adapter); 3152d1a890faSShreyas Bhatewara vmxnet3_free_intr_resources(adapter); 3153d1a890faSShreyas Bhatewara 3154d1a890faSShreyas Bhatewara netif_device_detach(netdev); 315509c5088eSShreyas Bhatewara netif_tx_stop_all_queues(netdev); 3156d1a890faSShreyas Bhatewara 3157d1a890faSShreyas Bhatewara /* Create wake-up filters. */ 3158d1a890faSShreyas Bhatewara pmConf = adapter->pm_conf; 3159d1a890faSShreyas Bhatewara memset(pmConf, 0, sizeof(*pmConf)); 3160d1a890faSShreyas Bhatewara 3161d1a890faSShreyas Bhatewara if (adapter->wol & WAKE_UCAST) { 3162d1a890faSShreyas Bhatewara pmConf->filters[i].patternSize = ETH_ALEN; 3163d1a890faSShreyas Bhatewara pmConf->filters[i].maskSize = 1; 3164d1a890faSShreyas Bhatewara memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN); 3165d1a890faSShreyas Bhatewara pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */ 3166d1a890faSShreyas Bhatewara 31673843e515SHarvey Harrison pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER; 3168d1a890faSShreyas Bhatewara i++; 3169d1a890faSShreyas Bhatewara } 3170d1a890faSShreyas Bhatewara 3171d1a890faSShreyas Bhatewara if (adapter->wol & WAKE_ARP) { 3172d1a890faSShreyas Bhatewara in_dev = in_dev_get(netdev); 3173d1a890faSShreyas Bhatewara if (!in_dev) 3174d1a890faSShreyas Bhatewara goto skip_arp; 3175d1a890faSShreyas Bhatewara 3176d1a890faSShreyas Bhatewara ifa = (struct in_ifaddr *)in_dev->ifa_list; 3177d1a890faSShreyas Bhatewara if (!ifa) 3178d1a890faSShreyas Bhatewara goto skip_arp; 3179d1a890faSShreyas Bhatewara 3180d1a890faSShreyas Bhatewara pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/ 3181d1a890faSShreyas Bhatewara sizeof(struct arphdr) + /* ARP header */ 3182d1a890faSShreyas Bhatewara 2 * ETH_ALEN + /* 2 Ethernet addresses*/ 3183d1a890faSShreyas Bhatewara 2 * sizeof(u32); /*2 IPv4 addresses */ 3184d1a890faSShreyas Bhatewara pmConf->filters[i].maskSize = 3185d1a890faSShreyas Bhatewara (pmConf->filters[i].patternSize - 1) / 8 + 1; 3186d1a890faSShreyas Bhatewara 3187d1a890faSShreyas Bhatewara /* ETH_P_ARP in Ethernet header. */ 3188d1a890faSShreyas Bhatewara ehdr = (struct ethhdr *)pmConf->filters[i].pattern; 3189d1a890faSShreyas Bhatewara ehdr->h_proto = htons(ETH_P_ARP); 3190d1a890faSShreyas Bhatewara 3191d1a890faSShreyas Bhatewara /* ARPOP_REQUEST in ARP header. */ 3192d1a890faSShreyas Bhatewara ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN]; 3193d1a890faSShreyas Bhatewara ahdr->ar_op = htons(ARPOP_REQUEST); 3194d1a890faSShreyas Bhatewara arpreq = (u8 *)(ahdr + 1); 3195d1a890faSShreyas Bhatewara 3196d1a890faSShreyas Bhatewara /* The Unicast IPv4 address in 'tip' field. */ 3197d1a890faSShreyas Bhatewara arpreq += 2 * ETH_ALEN + sizeof(u32); 3198d1a890faSShreyas Bhatewara *(u32 *)arpreq = ifa->ifa_address; 3199d1a890faSShreyas Bhatewara 3200d1a890faSShreyas Bhatewara /* The mask for the relevant bits. */ 3201d1a890faSShreyas Bhatewara pmConf->filters[i].mask[0] = 0x00; 3202d1a890faSShreyas Bhatewara pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */ 3203d1a890faSShreyas Bhatewara pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */ 3204d1a890faSShreyas Bhatewara pmConf->filters[i].mask[3] = 0x00; 3205d1a890faSShreyas Bhatewara pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */ 3206d1a890faSShreyas Bhatewara pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */ 3207d1a890faSShreyas Bhatewara in_dev_put(in_dev); 3208d1a890faSShreyas Bhatewara 32093843e515SHarvey Harrison pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER; 3210d1a890faSShreyas Bhatewara i++; 3211d1a890faSShreyas Bhatewara } 3212d1a890faSShreyas Bhatewara 3213d1a890faSShreyas Bhatewara skip_arp: 3214d1a890faSShreyas Bhatewara if (adapter->wol & WAKE_MAGIC) 32153843e515SHarvey Harrison pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC; 3216d1a890faSShreyas Bhatewara 3217d1a890faSShreyas Bhatewara pmConf->numFilters = i; 3218d1a890faSShreyas Bhatewara 3219115924b6SShreyas Bhatewara adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1); 3220115924b6SShreyas Bhatewara adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof( 3221115924b6SShreyas Bhatewara *pmConf)); 3222115924b6SShreyas Bhatewara adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys( 3223115924b6SShreyas Bhatewara pmConf)); 3224d1a890faSShreyas Bhatewara 322583d0feffSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 3226d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3227d1a890faSShreyas Bhatewara VMXNET3_CMD_UPDATE_PMCFG); 322883d0feffSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3229d1a890faSShreyas Bhatewara 3230d1a890faSShreyas Bhatewara pci_save_state(pdev); 3231d1a890faSShreyas Bhatewara pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND), 3232d1a890faSShreyas Bhatewara adapter->wol); 3233d1a890faSShreyas Bhatewara pci_disable_device(pdev); 3234d1a890faSShreyas Bhatewara pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND)); 3235d1a890faSShreyas Bhatewara 3236d1a890faSShreyas Bhatewara return 0; 3237d1a890faSShreyas Bhatewara } 3238d1a890faSShreyas Bhatewara 3239d1a890faSShreyas Bhatewara 3240d1a890faSShreyas Bhatewara static int 3241d1a890faSShreyas Bhatewara vmxnet3_resume(struct device *device) 3242d1a890faSShreyas Bhatewara { 324351956cd6SShreyas Bhatewara int err, i = 0; 324483d0feffSShreyas Bhatewara unsigned long flags; 3245d1a890faSShreyas Bhatewara struct pci_dev *pdev = to_pci_dev(device); 3246d1a890faSShreyas Bhatewara struct net_device *netdev = pci_get_drvdata(pdev); 3247d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3248d1a890faSShreyas Bhatewara struct Vmxnet3_PMConf *pmConf; 3249d1a890faSShreyas Bhatewara 3250d1a890faSShreyas Bhatewara if (!netif_running(netdev)) 3251d1a890faSShreyas Bhatewara return 0; 3252d1a890faSShreyas Bhatewara 3253d1a890faSShreyas Bhatewara /* Destroy wake-up filters. */ 3254d1a890faSShreyas Bhatewara pmConf = adapter->pm_conf; 3255d1a890faSShreyas Bhatewara memset(pmConf, 0, sizeof(*pmConf)); 3256d1a890faSShreyas Bhatewara 3257115924b6SShreyas Bhatewara adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1); 3258115924b6SShreyas Bhatewara adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof( 3259115924b6SShreyas Bhatewara *pmConf)); 32600561cf3dSHarvey Harrison adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys( 3261115924b6SShreyas Bhatewara pmConf)); 3262d1a890faSShreyas Bhatewara 3263d1a890faSShreyas Bhatewara netif_device_attach(netdev); 3264d1a890faSShreyas Bhatewara pci_set_power_state(pdev, PCI_D0); 3265d1a890faSShreyas Bhatewara pci_restore_state(pdev); 3266d1a890faSShreyas Bhatewara err = pci_enable_device_mem(pdev); 3267d1a890faSShreyas Bhatewara if (err != 0) 3268d1a890faSShreyas Bhatewara return err; 3269d1a890faSShreyas Bhatewara 3270d1a890faSShreyas Bhatewara pci_enable_wake(pdev, PCI_D0, 0); 3271d1a890faSShreyas Bhatewara 327283d0feffSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 3273d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3274d1a890faSShreyas Bhatewara VMXNET3_CMD_UPDATE_PMCFG); 327583d0feffSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3276d1a890faSShreyas Bhatewara vmxnet3_alloc_intr_resources(adapter); 3277d1a890faSShreyas Bhatewara vmxnet3_request_irqs(adapter); 327851956cd6SShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) 327951956cd6SShreyas Bhatewara napi_enable(&adapter->rx_queue[i].napi); 3280d1a890faSShreyas Bhatewara vmxnet3_enable_all_intrs(adapter); 3281d1a890faSShreyas Bhatewara 3282d1a890faSShreyas Bhatewara return 0; 3283d1a890faSShreyas Bhatewara } 3284d1a890faSShreyas Bhatewara 328547145210SAlexey Dobriyan static const struct dev_pm_ops vmxnet3_pm_ops = { 3286d1a890faSShreyas Bhatewara .suspend = vmxnet3_suspend, 3287d1a890faSShreyas Bhatewara .resume = vmxnet3_resume, 3288d1a890faSShreyas Bhatewara }; 3289d1a890faSShreyas Bhatewara #endif 3290d1a890faSShreyas Bhatewara 3291d1a890faSShreyas Bhatewara static struct pci_driver vmxnet3_driver = { 3292d1a890faSShreyas Bhatewara .name = vmxnet3_driver_name, 3293d1a890faSShreyas Bhatewara .id_table = vmxnet3_pciid_table, 3294d1a890faSShreyas Bhatewara .probe = vmxnet3_probe_device, 32953a4751a3SBill Pemberton .remove = vmxnet3_remove_device, 3296d1a890faSShreyas Bhatewara #ifdef CONFIG_PM 3297d1a890faSShreyas Bhatewara .driver.pm = &vmxnet3_pm_ops, 3298d1a890faSShreyas Bhatewara #endif 3299d1a890faSShreyas Bhatewara }; 3300d1a890faSShreyas Bhatewara 3301d1a890faSShreyas Bhatewara 3302d1a890faSShreyas Bhatewara static int __init 3303d1a890faSShreyas Bhatewara vmxnet3_init_module(void) 3304d1a890faSShreyas Bhatewara { 3305d1a890faSShreyas Bhatewara printk(KERN_INFO "%s - version %s\n", VMXNET3_DRIVER_DESC, 3306d1a890faSShreyas Bhatewara VMXNET3_DRIVER_VERSION_REPORT); 3307d1a890faSShreyas Bhatewara return pci_register_driver(&vmxnet3_driver); 3308d1a890faSShreyas Bhatewara } 3309d1a890faSShreyas Bhatewara 3310d1a890faSShreyas Bhatewara module_init(vmxnet3_init_module); 3311d1a890faSShreyas Bhatewara 3312d1a890faSShreyas Bhatewara 3313d1a890faSShreyas Bhatewara static void 3314d1a890faSShreyas Bhatewara vmxnet3_exit_module(void) 3315d1a890faSShreyas Bhatewara { 3316d1a890faSShreyas Bhatewara pci_unregister_driver(&vmxnet3_driver); 3317d1a890faSShreyas Bhatewara } 3318d1a890faSShreyas Bhatewara 3319d1a890faSShreyas Bhatewara module_exit(vmxnet3_exit_module); 3320d1a890faSShreyas Bhatewara 3321d1a890faSShreyas Bhatewara MODULE_AUTHOR("VMware, Inc."); 3322d1a890faSShreyas Bhatewara MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC); 3323d1a890faSShreyas Bhatewara MODULE_LICENSE("GPL v2"); 3324d1a890faSShreyas Bhatewara MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING); 3325