1d1a890faSShreyas Bhatewara /* 2d1a890faSShreyas Bhatewara * Linux driver for VMware's vmxnet3 ethernet NIC. 3d1a890faSShreyas Bhatewara * 469dbef0dSRonak Doshi * Copyright (C) 2008-2021, VMware, Inc. All Rights Reserved. 5d1a890faSShreyas Bhatewara * 6d1a890faSShreyas Bhatewara * This program is free software; you can redistribute it and/or modify it 7d1a890faSShreyas Bhatewara * under the terms of the GNU General Public License as published by the 8d1a890faSShreyas Bhatewara * Free Software Foundation; version 2 of the License and no later version. 9d1a890faSShreyas Bhatewara * 10d1a890faSShreyas Bhatewara * This program is distributed in the hope that it will be useful, but 11d1a890faSShreyas Bhatewara * WITHOUT ANY WARRANTY; without even the implied warranty of 12d1a890faSShreyas Bhatewara * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 13d1a890faSShreyas Bhatewara * NON INFRINGEMENT. See the GNU General Public License for more 14d1a890faSShreyas Bhatewara * details. 15d1a890faSShreyas Bhatewara * 16d1a890faSShreyas Bhatewara * You should have received a copy of the GNU General Public License 17d1a890faSShreyas Bhatewara * along with this program; if not, write to the Free Software 18d1a890faSShreyas Bhatewara * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19d1a890faSShreyas Bhatewara * 20d1a890faSShreyas Bhatewara * The full GNU General Public License is included in this distribution in 21d1a890faSShreyas Bhatewara * the file called "COPYING". 22d1a890faSShreyas Bhatewara * 23190af10fSShrikrishna Khare * Maintained by: pv-drivers@vmware.com 24d1a890faSShreyas Bhatewara * 25d1a890faSShreyas Bhatewara */ 26d1a890faSShreyas Bhatewara 279d9779e7SPaul Gortmaker #include <linux/module.h> 28b038b040SStephen Rothwell #include <net/ip6_checksum.h> 29b038b040SStephen Rothwell 30d1a890faSShreyas Bhatewara #include "vmxnet3_int.h" 31d1a890faSShreyas Bhatewara 32d1a890faSShreyas Bhatewara char vmxnet3_driver_name[] = "vmxnet3"; 33d1a890faSShreyas Bhatewara #define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver" 34d1a890faSShreyas Bhatewara 35d1a890faSShreyas Bhatewara /* 36d1a890faSShreyas Bhatewara * PCI Device ID Table 37d1a890faSShreyas Bhatewara * Last entry must be all 0s 38d1a890faSShreyas Bhatewara */ 399baa3c34SBenoit Taine static const struct pci_device_id vmxnet3_pciid_table[] = { 40d1a890faSShreyas Bhatewara {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)}, 41d1a890faSShreyas Bhatewara {0} 42d1a890faSShreyas Bhatewara }; 43d1a890faSShreyas Bhatewara 44d1a890faSShreyas Bhatewara MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table); 45d1a890faSShreyas Bhatewara 4609c5088eSShreyas Bhatewara static int enable_mq = 1; 47d1a890faSShreyas Bhatewara 48f9f25026SShreyas Bhatewara static void 498bc7823eSJakub Kicinski vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, const u8 *mac); 50f9f25026SShreyas Bhatewara 51d1a890faSShreyas Bhatewara /* 52d1a890faSShreyas Bhatewara * Enable/Disable the given intr 53d1a890faSShreyas Bhatewara */ 54d1a890faSShreyas Bhatewara static void 55d1a890faSShreyas Bhatewara vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx) 56d1a890faSShreyas Bhatewara { 57d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0); 58d1a890faSShreyas Bhatewara } 59d1a890faSShreyas Bhatewara 60d1a890faSShreyas Bhatewara 61d1a890faSShreyas Bhatewara static void 62d1a890faSShreyas Bhatewara vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx) 63d1a890faSShreyas Bhatewara { 64d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1); 65d1a890faSShreyas Bhatewara } 66d1a890faSShreyas Bhatewara 67d1a890faSShreyas Bhatewara 68d1a890faSShreyas Bhatewara /* 69d1a890faSShreyas Bhatewara * Enable/Disable all intrs used by the device 70d1a890faSShreyas Bhatewara */ 71d1a890faSShreyas Bhatewara static void 72d1a890faSShreyas Bhatewara vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter) 73d1a890faSShreyas Bhatewara { 74d1a890faSShreyas Bhatewara int i; 75d1a890faSShreyas Bhatewara 76d1a890faSShreyas Bhatewara for (i = 0; i < adapter->intr.num_intrs; i++) 77d1a890faSShreyas Bhatewara vmxnet3_enable_intr(adapter, i); 786929fe8aSRonghua Zang adapter->shared->devRead.intrConf.intrCtrl &= 796929fe8aSRonghua Zang cpu_to_le32(~VMXNET3_IC_DISABLE_ALL); 80d1a890faSShreyas Bhatewara } 81d1a890faSShreyas Bhatewara 82d1a890faSShreyas Bhatewara 83d1a890faSShreyas Bhatewara static void 84d1a890faSShreyas Bhatewara vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter) 85d1a890faSShreyas Bhatewara { 86d1a890faSShreyas Bhatewara int i; 87d1a890faSShreyas Bhatewara 886929fe8aSRonghua Zang adapter->shared->devRead.intrConf.intrCtrl |= 896929fe8aSRonghua Zang cpu_to_le32(VMXNET3_IC_DISABLE_ALL); 90d1a890faSShreyas Bhatewara for (i = 0; i < adapter->intr.num_intrs; i++) 91d1a890faSShreyas Bhatewara vmxnet3_disable_intr(adapter, i); 92d1a890faSShreyas Bhatewara } 93d1a890faSShreyas Bhatewara 94d1a890faSShreyas Bhatewara 95d1a890faSShreyas Bhatewara static void 96d1a890faSShreyas Bhatewara vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events) 97d1a890faSShreyas Bhatewara { 98d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events); 99d1a890faSShreyas Bhatewara } 100d1a890faSShreyas Bhatewara 101d1a890faSShreyas Bhatewara 102d1a890faSShreyas Bhatewara static bool 103d1a890faSShreyas Bhatewara vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 104d1a890faSShreyas Bhatewara { 10509c5088eSShreyas Bhatewara return tq->stopped; 106d1a890faSShreyas Bhatewara } 107d1a890faSShreyas Bhatewara 108d1a890faSShreyas Bhatewara 109d1a890faSShreyas Bhatewara static void 110d1a890faSShreyas Bhatewara vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 111d1a890faSShreyas Bhatewara { 112d1a890faSShreyas Bhatewara tq->stopped = false; 11309c5088eSShreyas Bhatewara netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue); 114d1a890faSShreyas Bhatewara } 115d1a890faSShreyas Bhatewara 116d1a890faSShreyas Bhatewara 117d1a890faSShreyas Bhatewara static void 118d1a890faSShreyas Bhatewara vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 119d1a890faSShreyas Bhatewara { 120d1a890faSShreyas Bhatewara tq->stopped = false; 12109c5088eSShreyas Bhatewara netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue)); 122d1a890faSShreyas Bhatewara } 123d1a890faSShreyas Bhatewara 124d1a890faSShreyas Bhatewara 125d1a890faSShreyas Bhatewara static void 126d1a890faSShreyas Bhatewara vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 127d1a890faSShreyas Bhatewara { 128d1a890faSShreyas Bhatewara tq->stopped = true; 129d1a890faSShreyas Bhatewara tq->num_stop++; 13009c5088eSShreyas Bhatewara netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue)); 131d1a890faSShreyas Bhatewara } 132d1a890faSShreyas Bhatewara 133d1a890faSShreyas Bhatewara 134d1a890faSShreyas Bhatewara /* 135d1a890faSShreyas Bhatewara * Check the link state. This may start or stop the tx queue. 136d1a890faSShreyas Bhatewara */ 137d1a890faSShreyas Bhatewara static void 1384a1745fcSShreyas Bhatewara vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue) 139d1a890faSShreyas Bhatewara { 140d1a890faSShreyas Bhatewara u32 ret; 14109c5088eSShreyas Bhatewara int i; 14283d0feffSShreyas Bhatewara unsigned long flags; 143d1a890faSShreyas Bhatewara 14483d0feffSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 145d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 146d1a890faSShreyas Bhatewara ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 14783d0feffSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 14883d0feffSShreyas Bhatewara 149d1a890faSShreyas Bhatewara adapter->link_speed = ret >> 16; 150d1a890faSShreyas Bhatewara if (ret & 1) { /* Link is up. */ 151204a6e65SStephen Hemminger netdev_info(adapter->netdev, "NIC Link is Up %d Mbps\n", 152204a6e65SStephen Hemminger adapter->link_speed); 153d1a890faSShreyas Bhatewara netif_carrier_on(adapter->netdev); 154d1a890faSShreyas Bhatewara 15509c5088eSShreyas Bhatewara if (affectTxQueue) { 15609c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) 15709c5088eSShreyas Bhatewara vmxnet3_tq_start(&adapter->tx_queue[i], 15809c5088eSShreyas Bhatewara adapter); 15909c5088eSShreyas Bhatewara } 160d1a890faSShreyas Bhatewara } else { 161204a6e65SStephen Hemminger netdev_info(adapter->netdev, "NIC Link is Down\n"); 162d1a890faSShreyas Bhatewara netif_carrier_off(adapter->netdev); 163d1a890faSShreyas Bhatewara 16409c5088eSShreyas Bhatewara if (affectTxQueue) { 16509c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) 16609c5088eSShreyas Bhatewara vmxnet3_tq_stop(&adapter->tx_queue[i], adapter); 16709c5088eSShreyas Bhatewara } 168d1a890faSShreyas Bhatewara } 169d1a890faSShreyas Bhatewara } 170d1a890faSShreyas Bhatewara 171d1a890faSShreyas Bhatewara static void 172d1a890faSShreyas Bhatewara vmxnet3_process_events(struct vmxnet3_adapter *adapter) 173d1a890faSShreyas Bhatewara { 17409c5088eSShreyas Bhatewara int i; 175e328d410SRoland Dreier unsigned long flags; 176115924b6SShreyas Bhatewara u32 events = le32_to_cpu(adapter->shared->ecr); 177d1a890faSShreyas Bhatewara if (!events) 178d1a890faSShreyas Bhatewara return; 179d1a890faSShreyas Bhatewara 180d1a890faSShreyas Bhatewara vmxnet3_ack_events(adapter, events); 181d1a890faSShreyas Bhatewara 182d1a890faSShreyas Bhatewara /* Check if link state has changed */ 183d1a890faSShreyas Bhatewara if (events & VMXNET3_ECR_LINK) 1844a1745fcSShreyas Bhatewara vmxnet3_check_link(adapter, true); 185d1a890faSShreyas Bhatewara 186d1a890faSShreyas Bhatewara /* Check if there is an error on xmit/recv queues */ 187d1a890faSShreyas Bhatewara if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 188e328d410SRoland Dreier spin_lock_irqsave(&adapter->cmd_lock, flags); 189d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 190d1a890faSShreyas Bhatewara VMXNET3_CMD_GET_QUEUE_STATUS); 191e328d410SRoland Dreier spin_unlock_irqrestore(&adapter->cmd_lock, flags); 192d1a890faSShreyas Bhatewara 19309c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) 19409c5088eSShreyas Bhatewara if (adapter->tqd_start[i].status.stopped) 19509c5088eSShreyas Bhatewara dev_err(&adapter->netdev->dev, 19609c5088eSShreyas Bhatewara "%s: tq[%d] error 0x%x\n", 19709c5088eSShreyas Bhatewara adapter->netdev->name, i, le32_to_cpu( 19809c5088eSShreyas Bhatewara adapter->tqd_start[i].status.error)); 19909c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) 20009c5088eSShreyas Bhatewara if (adapter->rqd_start[i].status.stopped) 20109c5088eSShreyas Bhatewara dev_err(&adapter->netdev->dev, 20209c5088eSShreyas Bhatewara "%s: rq[%d] error 0x%x\n", 20309c5088eSShreyas Bhatewara adapter->netdev->name, i, 20409c5088eSShreyas Bhatewara adapter->rqd_start[i].status.error); 205d1a890faSShreyas Bhatewara 206d1a890faSShreyas Bhatewara schedule_work(&adapter->work); 207d1a890faSShreyas Bhatewara } 208d1a890faSShreyas Bhatewara } 209d1a890faSShreyas Bhatewara 210115924b6SShreyas Bhatewara #ifdef __BIG_ENDIAN_BITFIELD 211115924b6SShreyas Bhatewara /* 212115924b6SShreyas Bhatewara * The device expects the bitfields in shared structures to be written in 213115924b6SShreyas Bhatewara * little endian. When CPU is big endian, the following routines are used to 214115924b6SShreyas Bhatewara * correctly read and write into ABI. 215115924b6SShreyas Bhatewara * The general technique used here is : double word bitfields are defined in 216115924b6SShreyas Bhatewara * opposite order for big endian architecture. Then before reading them in 217115924b6SShreyas Bhatewara * driver the complete double word is translated using le32_to_cpu. Similarly 218115924b6SShreyas Bhatewara * After the driver writes into bitfields, cpu_to_le32 is used to translate the 219115924b6SShreyas Bhatewara * double words into required format. 220115924b6SShreyas Bhatewara * In order to avoid touching bits in shared structure more than once, temporary 221115924b6SShreyas Bhatewara * descriptors are used. These are passed as srcDesc to following functions. 222115924b6SShreyas Bhatewara */ 223115924b6SShreyas Bhatewara static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc, 224115924b6SShreyas Bhatewara struct Vmxnet3_RxDesc *dstDesc) 225115924b6SShreyas Bhatewara { 226115924b6SShreyas Bhatewara u32 *src = (u32 *)srcDesc + 2; 227115924b6SShreyas Bhatewara u32 *dst = (u32 *)dstDesc + 2; 228115924b6SShreyas Bhatewara dstDesc->addr = le64_to_cpu(srcDesc->addr); 229115924b6SShreyas Bhatewara *dst = le32_to_cpu(*src); 230115924b6SShreyas Bhatewara dstDesc->ext1 = le32_to_cpu(srcDesc->ext1); 231115924b6SShreyas Bhatewara } 232115924b6SShreyas Bhatewara 233115924b6SShreyas Bhatewara static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc, 234115924b6SShreyas Bhatewara struct Vmxnet3_TxDesc *dstDesc) 235115924b6SShreyas Bhatewara { 236115924b6SShreyas Bhatewara int i; 237115924b6SShreyas Bhatewara u32 *src = (u32 *)(srcDesc + 1); 238115924b6SShreyas Bhatewara u32 *dst = (u32 *)(dstDesc + 1); 239115924b6SShreyas Bhatewara 240115924b6SShreyas Bhatewara /* Working backwards so that the gen bit is set at the end. */ 241115924b6SShreyas Bhatewara for (i = 2; i > 0; i--) { 242115924b6SShreyas Bhatewara src--; 243115924b6SShreyas Bhatewara dst--; 244115924b6SShreyas Bhatewara *dst = cpu_to_le32(*src); 245115924b6SShreyas Bhatewara } 246115924b6SShreyas Bhatewara } 247115924b6SShreyas Bhatewara 248115924b6SShreyas Bhatewara 249115924b6SShreyas Bhatewara static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc, 250115924b6SShreyas Bhatewara struct Vmxnet3_RxCompDesc *dstDesc) 251115924b6SShreyas Bhatewara { 252115924b6SShreyas Bhatewara int i = 0; 253115924b6SShreyas Bhatewara u32 *src = (u32 *)srcDesc; 254115924b6SShreyas Bhatewara u32 *dst = (u32 *)dstDesc; 255115924b6SShreyas Bhatewara for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) { 256115924b6SShreyas Bhatewara *dst = le32_to_cpu(*src); 257115924b6SShreyas Bhatewara src++; 258115924b6SShreyas Bhatewara dst++; 259115924b6SShreyas Bhatewara } 260115924b6SShreyas Bhatewara } 261115924b6SShreyas Bhatewara 262115924b6SShreyas Bhatewara 263115924b6SShreyas Bhatewara /* Used to read bitfield values from double words. */ 264115924b6SShreyas Bhatewara static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size) 265115924b6SShreyas Bhatewara { 266115924b6SShreyas Bhatewara u32 temp = le32_to_cpu(*bitfield); 267115924b6SShreyas Bhatewara u32 mask = ((1 << size) - 1) << pos; 268115924b6SShreyas Bhatewara temp &= mask; 269115924b6SShreyas Bhatewara temp >>= pos; 270115924b6SShreyas Bhatewara return temp; 271115924b6SShreyas Bhatewara } 272115924b6SShreyas Bhatewara 273115924b6SShreyas Bhatewara 274115924b6SShreyas Bhatewara 275115924b6SShreyas Bhatewara #endif /* __BIG_ENDIAN_BITFIELD */ 276115924b6SShreyas Bhatewara 277115924b6SShreyas Bhatewara #ifdef __BIG_ENDIAN_BITFIELD 278115924b6SShreyas Bhatewara 279115924b6SShreyas Bhatewara # define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \ 280115924b6SShreyas Bhatewara txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \ 281115924b6SShreyas Bhatewara VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE) 282115924b6SShreyas Bhatewara # define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \ 283115924b6SShreyas Bhatewara txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \ 284115924b6SShreyas Bhatewara VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE) 285115924b6SShreyas Bhatewara # define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \ 286115924b6SShreyas Bhatewara VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \ 287115924b6SShreyas Bhatewara VMXNET3_TCD_GEN_SIZE) 288115924b6SShreyas Bhatewara # define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \ 289115924b6SShreyas Bhatewara VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE) 290115924b6SShreyas Bhatewara # define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \ 291115924b6SShreyas Bhatewara (dstrcd) = (tmp); \ 292115924b6SShreyas Bhatewara vmxnet3_RxCompToCPU((rcd), (tmp)); \ 293115924b6SShreyas Bhatewara } while (0) 294115924b6SShreyas Bhatewara # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \ 295115924b6SShreyas Bhatewara (dstrxd) = (tmp); \ 296115924b6SShreyas Bhatewara vmxnet3_RxDescToCPU((rxd), (tmp)); \ 297115924b6SShreyas Bhatewara } while (0) 298115924b6SShreyas Bhatewara 299115924b6SShreyas Bhatewara #else 300115924b6SShreyas Bhatewara 301115924b6SShreyas Bhatewara # define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen) 302115924b6SShreyas Bhatewara # define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop) 303115924b6SShreyas Bhatewara # define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen) 304115924b6SShreyas Bhatewara # define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx) 305115924b6SShreyas Bhatewara # define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd) 306115924b6SShreyas Bhatewara # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd) 307115924b6SShreyas Bhatewara 308115924b6SShreyas Bhatewara #endif /* __BIG_ENDIAN_BITFIELD */ 309115924b6SShreyas Bhatewara 310d1a890faSShreyas Bhatewara 311d1a890faSShreyas Bhatewara static void 312d1a890faSShreyas Bhatewara vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi, 313d1a890faSShreyas Bhatewara struct pci_dev *pdev) 314d1a890faSShreyas Bhatewara { 315d1a890faSShreyas Bhatewara if (tbi->map_type == VMXNET3_MAP_SINGLE) 316b0eb57cbSAndy King dma_unmap_single(&pdev->dev, tbi->dma_addr, tbi->len, 317bf7bec46SChristophe JAILLET DMA_TO_DEVICE); 318d1a890faSShreyas Bhatewara else if (tbi->map_type == VMXNET3_MAP_PAGE) 319b0eb57cbSAndy King dma_unmap_page(&pdev->dev, tbi->dma_addr, tbi->len, 320bf7bec46SChristophe JAILLET DMA_TO_DEVICE); 321d1a890faSShreyas Bhatewara else 322d1a890faSShreyas Bhatewara BUG_ON(tbi->map_type != VMXNET3_MAP_NONE); 323d1a890faSShreyas Bhatewara 324d1a890faSShreyas Bhatewara tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */ 325d1a890faSShreyas Bhatewara } 326d1a890faSShreyas Bhatewara 327d1a890faSShreyas Bhatewara 328d1a890faSShreyas Bhatewara static int 329d1a890faSShreyas Bhatewara vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq, 330d1a890faSShreyas Bhatewara struct pci_dev *pdev, struct vmxnet3_adapter *adapter) 331d1a890faSShreyas Bhatewara { 332d1a890faSShreyas Bhatewara struct sk_buff *skb; 333d1a890faSShreyas Bhatewara int entries = 0; 334d1a890faSShreyas Bhatewara 335d1a890faSShreyas Bhatewara /* no out of order completion */ 336d1a890faSShreyas Bhatewara BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp); 337115924b6SShreyas Bhatewara BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1); 338d1a890faSShreyas Bhatewara 339d1a890faSShreyas Bhatewara skb = tq->buf_info[eop_idx].skb; 340d1a890faSShreyas Bhatewara BUG_ON(skb == NULL); 341d1a890faSShreyas Bhatewara tq->buf_info[eop_idx].skb = NULL; 342d1a890faSShreyas Bhatewara 343d1a890faSShreyas Bhatewara VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size); 344d1a890faSShreyas Bhatewara 345d1a890faSShreyas Bhatewara while (tq->tx_ring.next2comp != eop_idx) { 346d1a890faSShreyas Bhatewara vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp, 347d1a890faSShreyas Bhatewara pdev); 348d1a890faSShreyas Bhatewara 349d1a890faSShreyas Bhatewara /* update next2comp w/o tx_lock. Since we are marking more, 350d1a890faSShreyas Bhatewara * instead of less, tx ring entries avail, the worst case is 351d1a890faSShreyas Bhatewara * that the tx routine incorrectly re-queues a pkt due to 352d1a890faSShreyas Bhatewara * insufficient tx ring entries. 353d1a890faSShreyas Bhatewara */ 354d1a890faSShreyas Bhatewara vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring); 355d1a890faSShreyas Bhatewara entries++; 356d1a890faSShreyas Bhatewara } 357d1a890faSShreyas Bhatewara 358d1a890faSShreyas Bhatewara dev_kfree_skb_any(skb); 359d1a890faSShreyas Bhatewara return entries; 360d1a890faSShreyas Bhatewara } 361d1a890faSShreyas Bhatewara 362d1a890faSShreyas Bhatewara 363d1a890faSShreyas Bhatewara static int 364d1a890faSShreyas Bhatewara vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq, 365d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 366d1a890faSShreyas Bhatewara { 367d1a890faSShreyas Bhatewara int completed = 0; 368d1a890faSShreyas Bhatewara union Vmxnet3_GenericDesc *gdesc; 369d1a890faSShreyas Bhatewara 370d1a890faSShreyas Bhatewara gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; 371115924b6SShreyas Bhatewara while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) { 372f3002c13Shpreg@vmware.com /* Prevent any &gdesc->tcd field from being (speculatively) 373f3002c13Shpreg@vmware.com * read before (&gdesc->tcd)->gen is read. 374f3002c13Shpreg@vmware.com */ 375f3002c13Shpreg@vmware.com dma_rmb(); 376f3002c13Shpreg@vmware.com 377115924b6SShreyas Bhatewara completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX( 378115924b6SShreyas Bhatewara &gdesc->tcd), tq, adapter->pdev, 379115924b6SShreyas Bhatewara adapter); 380d1a890faSShreyas Bhatewara 381d1a890faSShreyas Bhatewara vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring); 382d1a890faSShreyas Bhatewara gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; 383d1a890faSShreyas Bhatewara } 384d1a890faSShreyas Bhatewara 385d1a890faSShreyas Bhatewara if (completed) { 386d1a890faSShreyas Bhatewara spin_lock(&tq->tx_lock); 387d1a890faSShreyas Bhatewara if (unlikely(vmxnet3_tq_stopped(tq, adapter) && 388d1a890faSShreyas Bhatewara vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) > 389d1a890faSShreyas Bhatewara VMXNET3_WAKE_QUEUE_THRESHOLD(tq) && 390d1a890faSShreyas Bhatewara netif_carrier_ok(adapter->netdev))) { 391d1a890faSShreyas Bhatewara vmxnet3_tq_wake(tq, adapter); 392d1a890faSShreyas Bhatewara } 393d1a890faSShreyas Bhatewara spin_unlock(&tq->tx_lock); 394d1a890faSShreyas Bhatewara } 395d1a890faSShreyas Bhatewara return completed; 396d1a890faSShreyas Bhatewara } 397d1a890faSShreyas Bhatewara 398d1a890faSShreyas Bhatewara 399d1a890faSShreyas Bhatewara static void 400d1a890faSShreyas Bhatewara vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq, 401d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 402d1a890faSShreyas Bhatewara { 403d1a890faSShreyas Bhatewara int i; 404d1a890faSShreyas Bhatewara 405d1a890faSShreyas Bhatewara while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) { 406d1a890faSShreyas Bhatewara struct vmxnet3_tx_buf_info *tbi; 407d1a890faSShreyas Bhatewara 408d1a890faSShreyas Bhatewara tbi = tq->buf_info + tq->tx_ring.next2comp; 409d1a890faSShreyas Bhatewara 410d1a890faSShreyas Bhatewara vmxnet3_unmap_tx_buf(tbi, adapter->pdev); 411d1a890faSShreyas Bhatewara if (tbi->skb) { 412d1a890faSShreyas Bhatewara dev_kfree_skb_any(tbi->skb); 413d1a890faSShreyas Bhatewara tbi->skb = NULL; 414d1a890faSShreyas Bhatewara } 415d1a890faSShreyas Bhatewara vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring); 416d1a890faSShreyas Bhatewara } 417d1a890faSShreyas Bhatewara 418d1a890faSShreyas Bhatewara /* sanity check, verify all buffers are indeed unmapped and freed */ 419d1a890faSShreyas Bhatewara for (i = 0; i < tq->tx_ring.size; i++) { 420d1a890faSShreyas Bhatewara BUG_ON(tq->buf_info[i].skb != NULL || 421d1a890faSShreyas Bhatewara tq->buf_info[i].map_type != VMXNET3_MAP_NONE); 422d1a890faSShreyas Bhatewara } 423d1a890faSShreyas Bhatewara 424d1a890faSShreyas Bhatewara tq->tx_ring.gen = VMXNET3_INIT_GEN; 425d1a890faSShreyas Bhatewara tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0; 426d1a890faSShreyas Bhatewara 427d1a890faSShreyas Bhatewara tq->comp_ring.gen = VMXNET3_INIT_GEN; 428d1a890faSShreyas Bhatewara tq->comp_ring.next2proc = 0; 429d1a890faSShreyas Bhatewara } 430d1a890faSShreyas Bhatewara 431d1a890faSShreyas Bhatewara 43209c5088eSShreyas Bhatewara static void 433d1a890faSShreyas Bhatewara vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq, 434d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 435d1a890faSShreyas Bhatewara { 436d1a890faSShreyas Bhatewara if (tq->tx_ring.base) { 437b0eb57cbSAndy King dma_free_coherent(&adapter->pdev->dev, tq->tx_ring.size * 438d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_TxDesc), 439d1a890faSShreyas Bhatewara tq->tx_ring.base, tq->tx_ring.basePA); 440d1a890faSShreyas Bhatewara tq->tx_ring.base = NULL; 441d1a890faSShreyas Bhatewara } 442d1a890faSShreyas Bhatewara if (tq->data_ring.base) { 4433c8b3efcSShrikrishna Khare dma_free_coherent(&adapter->pdev->dev, 4443c8b3efcSShrikrishna Khare tq->data_ring.size * tq->txdata_desc_size, 445d1a890faSShreyas Bhatewara tq->data_ring.base, tq->data_ring.basePA); 446d1a890faSShreyas Bhatewara tq->data_ring.base = NULL; 447d1a890faSShreyas Bhatewara } 448d1a890faSShreyas Bhatewara if (tq->comp_ring.base) { 449b0eb57cbSAndy King dma_free_coherent(&adapter->pdev->dev, tq->comp_ring.size * 450d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_TxCompDesc), 451d1a890faSShreyas Bhatewara tq->comp_ring.base, tq->comp_ring.basePA); 452d1a890faSShreyas Bhatewara tq->comp_ring.base = NULL; 453d1a890faSShreyas Bhatewara } 454de1da8bcSRonak Doshi kfree(tq->buf_info); 455d1a890faSShreyas Bhatewara tq->buf_info = NULL; 456d1a890faSShreyas Bhatewara } 457d1a890faSShreyas Bhatewara 458d1a890faSShreyas Bhatewara 45909c5088eSShreyas Bhatewara /* Destroy all tx queues */ 46009c5088eSShreyas Bhatewara void 46109c5088eSShreyas Bhatewara vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter) 46209c5088eSShreyas Bhatewara { 46309c5088eSShreyas Bhatewara int i; 46409c5088eSShreyas Bhatewara 46509c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) 46609c5088eSShreyas Bhatewara vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter); 46709c5088eSShreyas Bhatewara } 46809c5088eSShreyas Bhatewara 46909c5088eSShreyas Bhatewara 470d1a890faSShreyas Bhatewara static void 471d1a890faSShreyas Bhatewara vmxnet3_tq_init(struct vmxnet3_tx_queue *tq, 472d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 473d1a890faSShreyas Bhatewara { 474d1a890faSShreyas Bhatewara int i; 475d1a890faSShreyas Bhatewara 476d1a890faSShreyas Bhatewara /* reset the tx ring contents to 0 and reset the tx ring states */ 477d1a890faSShreyas Bhatewara memset(tq->tx_ring.base, 0, tq->tx_ring.size * 478d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_TxDesc)); 479d1a890faSShreyas Bhatewara tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0; 480d1a890faSShreyas Bhatewara tq->tx_ring.gen = VMXNET3_INIT_GEN; 481d1a890faSShreyas Bhatewara 4823c8b3efcSShrikrishna Khare memset(tq->data_ring.base, 0, 4833c8b3efcSShrikrishna Khare tq->data_ring.size * tq->txdata_desc_size); 484d1a890faSShreyas Bhatewara 485d1a890faSShreyas Bhatewara /* reset the tx comp ring contents to 0 and reset comp ring states */ 486d1a890faSShreyas Bhatewara memset(tq->comp_ring.base, 0, tq->comp_ring.size * 487d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_TxCompDesc)); 488d1a890faSShreyas Bhatewara tq->comp_ring.next2proc = 0; 489d1a890faSShreyas Bhatewara tq->comp_ring.gen = VMXNET3_INIT_GEN; 490d1a890faSShreyas Bhatewara 491d1a890faSShreyas Bhatewara /* reset the bookkeeping data */ 492d1a890faSShreyas Bhatewara memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size); 493d1a890faSShreyas Bhatewara for (i = 0; i < tq->tx_ring.size; i++) 494d1a890faSShreyas Bhatewara tq->buf_info[i].map_type = VMXNET3_MAP_NONE; 495d1a890faSShreyas Bhatewara 496d1a890faSShreyas Bhatewara /* stats are not reset */ 497d1a890faSShreyas Bhatewara } 498d1a890faSShreyas Bhatewara 499d1a890faSShreyas Bhatewara 500d1a890faSShreyas Bhatewara static int 501d1a890faSShreyas Bhatewara vmxnet3_tq_create(struct vmxnet3_tx_queue *tq, 502d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 503d1a890faSShreyas Bhatewara { 504d1a890faSShreyas Bhatewara BUG_ON(tq->tx_ring.base || tq->data_ring.base || 505d1a890faSShreyas Bhatewara tq->comp_ring.base || tq->buf_info); 506d1a890faSShreyas Bhatewara 507b0eb57cbSAndy King tq->tx_ring.base = dma_alloc_coherent(&adapter->pdev->dev, 508b0eb57cbSAndy King tq->tx_ring.size * sizeof(struct Vmxnet3_TxDesc), 509b0eb57cbSAndy King &tq->tx_ring.basePA, GFP_KERNEL); 510d1a890faSShreyas Bhatewara if (!tq->tx_ring.base) { 511204a6e65SStephen Hemminger netdev_err(adapter->netdev, "failed to allocate tx ring\n"); 512d1a890faSShreyas Bhatewara goto err; 513d1a890faSShreyas Bhatewara } 514d1a890faSShreyas Bhatewara 515b0eb57cbSAndy King tq->data_ring.base = dma_alloc_coherent(&adapter->pdev->dev, 5163c8b3efcSShrikrishna Khare tq->data_ring.size * tq->txdata_desc_size, 517b0eb57cbSAndy King &tq->data_ring.basePA, GFP_KERNEL); 518d1a890faSShreyas Bhatewara if (!tq->data_ring.base) { 5193c8b3efcSShrikrishna Khare netdev_err(adapter->netdev, "failed to allocate tx data ring\n"); 520d1a890faSShreyas Bhatewara goto err; 521d1a890faSShreyas Bhatewara } 522d1a890faSShreyas Bhatewara 523b0eb57cbSAndy King tq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, 524b0eb57cbSAndy King tq->comp_ring.size * sizeof(struct Vmxnet3_TxCompDesc), 525b0eb57cbSAndy King &tq->comp_ring.basePA, GFP_KERNEL); 526d1a890faSShreyas Bhatewara if (!tq->comp_ring.base) { 527204a6e65SStephen Hemminger netdev_err(adapter->netdev, "failed to allocate tx comp ring\n"); 528d1a890faSShreyas Bhatewara goto err; 529d1a890faSShreyas Bhatewara } 530d1a890faSShreyas Bhatewara 531de1da8bcSRonak Doshi tq->buf_info = kcalloc_node(tq->tx_ring.size, sizeof(tq->buf_info[0]), 532de1da8bcSRonak Doshi GFP_KERNEL, 533de1da8bcSRonak Doshi dev_to_node(&adapter->pdev->dev)); 534e404decbSJoe Perches if (!tq->buf_info) 535d1a890faSShreyas Bhatewara goto err; 536d1a890faSShreyas Bhatewara 537d1a890faSShreyas Bhatewara return 0; 538d1a890faSShreyas Bhatewara 539d1a890faSShreyas Bhatewara err: 540d1a890faSShreyas Bhatewara vmxnet3_tq_destroy(tq, adapter); 541d1a890faSShreyas Bhatewara return -ENOMEM; 542d1a890faSShreyas Bhatewara } 543d1a890faSShreyas Bhatewara 54409c5088eSShreyas Bhatewara static void 54509c5088eSShreyas Bhatewara vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter) 54609c5088eSShreyas Bhatewara { 54709c5088eSShreyas Bhatewara int i; 54809c5088eSShreyas Bhatewara 54909c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) 55009c5088eSShreyas Bhatewara vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter); 55109c5088eSShreyas Bhatewara } 552d1a890faSShreyas Bhatewara 553d1a890faSShreyas Bhatewara /* 554d1a890faSShreyas Bhatewara * starting from ring->next2fill, allocate rx buffers for the given ring 555d1a890faSShreyas Bhatewara * of the rx queue and update the rx desc. stop after @num_to_alloc buffers 556d1a890faSShreyas Bhatewara * are allocated or allocation fails 557d1a890faSShreyas Bhatewara */ 558d1a890faSShreyas Bhatewara 559d1a890faSShreyas Bhatewara static int 560d1a890faSShreyas Bhatewara vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx, 561d1a890faSShreyas Bhatewara int num_to_alloc, struct vmxnet3_adapter *adapter) 562d1a890faSShreyas Bhatewara { 563d1a890faSShreyas Bhatewara int num_allocated = 0; 564d1a890faSShreyas Bhatewara struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx]; 565d1a890faSShreyas Bhatewara struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx]; 566d1a890faSShreyas Bhatewara u32 val; 567d1a890faSShreyas Bhatewara 5685318d809SShreyas Bhatewara while (num_allocated <= num_to_alloc) { 569d1a890faSShreyas Bhatewara struct vmxnet3_rx_buf_info *rbi; 570d1a890faSShreyas Bhatewara union Vmxnet3_GenericDesc *gd; 571d1a890faSShreyas Bhatewara 572d1a890faSShreyas Bhatewara rbi = rbi_base + ring->next2fill; 573d1a890faSShreyas Bhatewara gd = ring->base + ring->next2fill; 574d1a890faSShreyas Bhatewara 575d1a890faSShreyas Bhatewara if (rbi->buf_type == VMXNET3_RX_BUF_SKB) { 576d1a890faSShreyas Bhatewara if (rbi->skb == NULL) { 5770d735f13SStephen Hemminger rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev, 5780d735f13SStephen Hemminger rbi->len, 5790d735f13SStephen Hemminger GFP_KERNEL); 580d1a890faSShreyas Bhatewara if (unlikely(rbi->skb == NULL)) { 581d1a890faSShreyas Bhatewara rq->stats.rx_buf_alloc_failure++; 582d1a890faSShreyas Bhatewara break; 583d1a890faSShreyas Bhatewara } 584d1a890faSShreyas Bhatewara 585b0eb57cbSAndy King rbi->dma_addr = dma_map_single( 586b0eb57cbSAndy King &adapter->pdev->dev, 587d1a890faSShreyas Bhatewara rbi->skb->data, rbi->len, 588bf7bec46SChristophe JAILLET DMA_FROM_DEVICE); 5895738a09dSAlexey Khoroshilov if (dma_mapping_error(&adapter->pdev->dev, 5905738a09dSAlexey Khoroshilov rbi->dma_addr)) { 5915738a09dSAlexey Khoroshilov dev_kfree_skb_any(rbi->skb); 5929e7fef95SZixuan Fu rbi->skb = NULL; 5935738a09dSAlexey Khoroshilov rq->stats.rx_buf_alloc_failure++; 5945738a09dSAlexey Khoroshilov break; 5955738a09dSAlexey Khoroshilov } 596d1a890faSShreyas Bhatewara } else { 597d1a890faSShreyas Bhatewara /* rx buffer skipped by the device */ 598d1a890faSShreyas Bhatewara } 599d1a890faSShreyas Bhatewara val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT; 600d1a890faSShreyas Bhatewara } else { 601d1a890faSShreyas Bhatewara BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE || 602d1a890faSShreyas Bhatewara rbi->len != PAGE_SIZE); 603d1a890faSShreyas Bhatewara 604d1a890faSShreyas Bhatewara if (rbi->page == NULL) { 605d1a890faSShreyas Bhatewara rbi->page = alloc_page(GFP_ATOMIC); 606d1a890faSShreyas Bhatewara if (unlikely(rbi->page == NULL)) { 607d1a890faSShreyas Bhatewara rq->stats.rx_buf_alloc_failure++; 608d1a890faSShreyas Bhatewara break; 609d1a890faSShreyas Bhatewara } 610b0eb57cbSAndy King rbi->dma_addr = dma_map_page( 611b0eb57cbSAndy King &adapter->pdev->dev, 612d1a890faSShreyas Bhatewara rbi->page, 0, PAGE_SIZE, 613bf7bec46SChristophe JAILLET DMA_FROM_DEVICE); 6145738a09dSAlexey Khoroshilov if (dma_mapping_error(&adapter->pdev->dev, 6155738a09dSAlexey Khoroshilov rbi->dma_addr)) { 6165738a09dSAlexey Khoroshilov put_page(rbi->page); 6179e7fef95SZixuan Fu rbi->page = NULL; 6185738a09dSAlexey Khoroshilov rq->stats.rx_buf_alloc_failure++; 6195738a09dSAlexey Khoroshilov break; 6205738a09dSAlexey Khoroshilov } 621d1a890faSShreyas Bhatewara } else { 622d1a890faSShreyas Bhatewara /* rx buffers skipped by the device */ 623d1a890faSShreyas Bhatewara } 624d1a890faSShreyas Bhatewara val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT; 625d1a890faSShreyas Bhatewara } 626d1a890faSShreyas Bhatewara 627115924b6SShreyas Bhatewara gd->rxd.addr = cpu_to_le64(rbi->dma_addr); 6285318d809SShreyas Bhatewara gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT) 629115924b6SShreyas Bhatewara | val | rbi->len); 630d1a890faSShreyas Bhatewara 6315318d809SShreyas Bhatewara /* Fill the last buffer but dont mark it ready, or else the 6325318d809SShreyas Bhatewara * device will think that the queue is full */ 6335318d809SShreyas Bhatewara if (num_allocated == num_to_alloc) 6345318d809SShreyas Bhatewara break; 6355318d809SShreyas Bhatewara 6365318d809SShreyas Bhatewara gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT); 637d1a890faSShreyas Bhatewara num_allocated++; 638d1a890faSShreyas Bhatewara vmxnet3_cmd_ring_adv_next2fill(ring); 639d1a890faSShreyas Bhatewara } 640d1a890faSShreyas Bhatewara 641fdcd79b9SStephen Hemminger netdev_dbg(adapter->netdev, 64269b9a712SStephen Hemminger "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n", 64369b9a712SStephen Hemminger num_allocated, ring->next2fill, ring->next2comp); 644d1a890faSShreyas Bhatewara 645d1a890faSShreyas Bhatewara /* so that the device can distinguish a full ring and an empty ring */ 646d1a890faSShreyas Bhatewara BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp); 647d1a890faSShreyas Bhatewara 648d1a890faSShreyas Bhatewara return num_allocated; 649d1a890faSShreyas Bhatewara } 650d1a890faSShreyas Bhatewara 651d1a890faSShreyas Bhatewara 652d1a890faSShreyas Bhatewara static void 653d1a890faSShreyas Bhatewara vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd, 654d1a890faSShreyas Bhatewara struct vmxnet3_rx_buf_info *rbi) 655d1a890faSShreyas Bhatewara { 656d7840976SMatthew Wilcox (Oracle) skb_frag_t *frag = skb_shinfo(skb)->frags + skb_shinfo(skb)->nr_frags; 657d1a890faSShreyas Bhatewara 658d1a890faSShreyas Bhatewara BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS); 659d1a890faSShreyas Bhatewara 6600e0634d2SIan Campbell __skb_frag_set_page(frag, rbi->page); 661b54c9d5bSJonathan Lemon skb_frag_off_set(frag, 0); 6629e903e08SEric Dumazet skb_frag_size_set(frag, rcd->len); 6639e903e08SEric Dumazet skb->data_len += rcd->len; 6645e6c355cSEric Dumazet skb->truesize += PAGE_SIZE; 665d1a890faSShreyas Bhatewara skb_shinfo(skb)->nr_frags++; 666d1a890faSShreyas Bhatewara } 667d1a890faSShreyas Bhatewara 668d1a890faSShreyas Bhatewara 6695738a09dSAlexey Khoroshilov static int 670d1a890faSShreyas Bhatewara vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx, 671d1a890faSShreyas Bhatewara struct vmxnet3_tx_queue *tq, struct pci_dev *pdev, 672d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 673d1a890faSShreyas Bhatewara { 674d1a890faSShreyas Bhatewara u32 dw2, len; 675d1a890faSShreyas Bhatewara unsigned long buf_offset; 676d1a890faSShreyas Bhatewara int i; 677d1a890faSShreyas Bhatewara union Vmxnet3_GenericDesc *gdesc; 678d1a890faSShreyas Bhatewara struct vmxnet3_tx_buf_info *tbi = NULL; 679d1a890faSShreyas Bhatewara 680d1a890faSShreyas Bhatewara BUG_ON(ctx->copy_size > skb_headlen(skb)); 681d1a890faSShreyas Bhatewara 682d1a890faSShreyas Bhatewara /* use the previous gen bit for the SOP desc */ 683d1a890faSShreyas Bhatewara dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT; 684d1a890faSShreyas Bhatewara 685d1a890faSShreyas Bhatewara ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill; 686d1a890faSShreyas Bhatewara gdesc = ctx->sop_txd; /* both loops below can be skipped */ 687d1a890faSShreyas Bhatewara 688d1a890faSShreyas Bhatewara /* no need to map the buffer if headers are copied */ 689d1a890faSShreyas Bhatewara if (ctx->copy_size) { 690115924b6SShreyas Bhatewara ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA + 691d1a890faSShreyas Bhatewara tq->tx_ring.next2fill * 6923c8b3efcSShrikrishna Khare tq->txdata_desc_size); 693115924b6SShreyas Bhatewara ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size); 694d1a890faSShreyas Bhatewara ctx->sop_txd->dword[3] = 0; 695d1a890faSShreyas Bhatewara 696d1a890faSShreyas Bhatewara tbi = tq->buf_info + tq->tx_ring.next2fill; 697d1a890faSShreyas Bhatewara tbi->map_type = VMXNET3_MAP_NONE; 698d1a890faSShreyas Bhatewara 699fdcd79b9SStephen Hemminger netdev_dbg(adapter->netdev, 700f6965582SRandy Dunlap "txd[%u]: 0x%Lx 0x%x 0x%x\n", 701115924b6SShreyas Bhatewara tq->tx_ring.next2fill, 702115924b6SShreyas Bhatewara le64_to_cpu(ctx->sop_txd->txd.addr), 703d1a890faSShreyas Bhatewara ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]); 704d1a890faSShreyas Bhatewara vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 705d1a890faSShreyas Bhatewara 706d1a890faSShreyas Bhatewara /* use the right gen for non-SOP desc */ 707d1a890faSShreyas Bhatewara dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 708d1a890faSShreyas Bhatewara } 709d1a890faSShreyas Bhatewara 710d1a890faSShreyas Bhatewara /* linear part can use multiple tx desc if it's big */ 711d1a890faSShreyas Bhatewara len = skb_headlen(skb) - ctx->copy_size; 712d1a890faSShreyas Bhatewara buf_offset = ctx->copy_size; 713d1a890faSShreyas Bhatewara while (len) { 714d1a890faSShreyas Bhatewara u32 buf_size; 715d1a890faSShreyas Bhatewara 7161f4b1612SBhavesh Davda if (len < VMXNET3_MAX_TX_BUF_SIZE) { 7171f4b1612SBhavesh Davda buf_size = len; 7181f4b1612SBhavesh Davda dw2 |= len; 7191f4b1612SBhavesh Davda } else { 7201f4b1612SBhavesh Davda buf_size = VMXNET3_MAX_TX_BUF_SIZE; 7211f4b1612SBhavesh Davda /* spec says that for TxDesc.len, 0 == 2^14 */ 7221f4b1612SBhavesh Davda } 723d1a890faSShreyas Bhatewara 724d1a890faSShreyas Bhatewara tbi = tq->buf_info + tq->tx_ring.next2fill; 725d1a890faSShreyas Bhatewara tbi->map_type = VMXNET3_MAP_SINGLE; 726b0eb57cbSAndy King tbi->dma_addr = dma_map_single(&adapter->pdev->dev, 727d1a890faSShreyas Bhatewara skb->data + buf_offset, buf_size, 728bf7bec46SChristophe JAILLET DMA_TO_DEVICE); 7295738a09dSAlexey Khoroshilov if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr)) 7305738a09dSAlexey Khoroshilov return -EFAULT; 731d1a890faSShreyas Bhatewara 7321f4b1612SBhavesh Davda tbi->len = buf_size; 733d1a890faSShreyas Bhatewara 734d1a890faSShreyas Bhatewara gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; 735d1a890faSShreyas Bhatewara BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); 736d1a890faSShreyas Bhatewara 737115924b6SShreyas Bhatewara gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); 7381f4b1612SBhavesh Davda gdesc->dword[2] = cpu_to_le32(dw2); 739d1a890faSShreyas Bhatewara gdesc->dword[3] = 0; 740d1a890faSShreyas Bhatewara 741fdcd79b9SStephen Hemminger netdev_dbg(adapter->netdev, 742f6965582SRandy Dunlap "txd[%u]: 0x%Lx 0x%x 0x%x\n", 743115924b6SShreyas Bhatewara tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), 744115924b6SShreyas Bhatewara le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); 745d1a890faSShreyas Bhatewara vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 746d1a890faSShreyas Bhatewara dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 747d1a890faSShreyas Bhatewara 748d1a890faSShreyas Bhatewara len -= buf_size; 749d1a890faSShreyas Bhatewara buf_offset += buf_size; 750d1a890faSShreyas Bhatewara } 751d1a890faSShreyas Bhatewara 752d1a890faSShreyas Bhatewara for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 753d7840976SMatthew Wilcox (Oracle) const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 754a4d7e485SEric Dumazet u32 buf_size; 755d1a890faSShreyas Bhatewara 756a4d7e485SEric Dumazet buf_offset = 0; 757a4d7e485SEric Dumazet len = skb_frag_size(frag); 758a4d7e485SEric Dumazet while (len) { 759d1a890faSShreyas Bhatewara tbi = tq->buf_info + tq->tx_ring.next2fill; 760a4d7e485SEric Dumazet if (len < VMXNET3_MAX_TX_BUF_SIZE) { 761a4d7e485SEric Dumazet buf_size = len; 762a4d7e485SEric Dumazet dw2 |= len; 763a4d7e485SEric Dumazet } else { 764a4d7e485SEric Dumazet buf_size = VMXNET3_MAX_TX_BUF_SIZE; 765a4d7e485SEric Dumazet /* spec says that for TxDesc.len, 0 == 2^14 */ 766a4d7e485SEric Dumazet } 767d1a890faSShreyas Bhatewara tbi->map_type = VMXNET3_MAP_PAGE; 7680e0634d2SIan Campbell tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag, 769a4d7e485SEric Dumazet buf_offset, buf_size, 7705d6bcdfeSIan Campbell DMA_TO_DEVICE); 7715738a09dSAlexey Khoroshilov if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr)) 7725738a09dSAlexey Khoroshilov return -EFAULT; 773d1a890faSShreyas Bhatewara 774a4d7e485SEric Dumazet tbi->len = buf_size; 775d1a890faSShreyas Bhatewara 776d1a890faSShreyas Bhatewara gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; 777d1a890faSShreyas Bhatewara BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); 778d1a890faSShreyas Bhatewara 779115924b6SShreyas Bhatewara gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); 780a4d7e485SEric Dumazet gdesc->dword[2] = cpu_to_le32(dw2); 781d1a890faSShreyas Bhatewara gdesc->dword[3] = 0; 782d1a890faSShreyas Bhatewara 783fdcd79b9SStephen Hemminger netdev_dbg(adapter->netdev, 7848b429468SHans Wennborg "txd[%u]: 0x%llx %u %u\n", 785115924b6SShreyas Bhatewara tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), 786115924b6SShreyas Bhatewara le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); 787d1a890faSShreyas Bhatewara vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 788d1a890faSShreyas Bhatewara dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 789a4d7e485SEric Dumazet 790a4d7e485SEric Dumazet len -= buf_size; 791a4d7e485SEric Dumazet buf_offset += buf_size; 792a4d7e485SEric Dumazet } 793d1a890faSShreyas Bhatewara } 794d1a890faSShreyas Bhatewara 795d1a890faSShreyas Bhatewara ctx->eop_txd = gdesc; 796d1a890faSShreyas Bhatewara 797d1a890faSShreyas Bhatewara /* set the last buf_info for the pkt */ 798d1a890faSShreyas Bhatewara tbi->skb = skb; 799d1a890faSShreyas Bhatewara tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base; 8005738a09dSAlexey Khoroshilov 8015738a09dSAlexey Khoroshilov return 0; 802d1a890faSShreyas Bhatewara } 803d1a890faSShreyas Bhatewara 804d1a890faSShreyas Bhatewara 80509c5088eSShreyas Bhatewara /* Init all tx queues */ 80609c5088eSShreyas Bhatewara static void 80709c5088eSShreyas Bhatewara vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter) 80809c5088eSShreyas Bhatewara { 80909c5088eSShreyas Bhatewara int i; 81009c5088eSShreyas Bhatewara 81109c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) 81209c5088eSShreyas Bhatewara vmxnet3_tq_init(&adapter->tx_queue[i], adapter); 81309c5088eSShreyas Bhatewara } 81409c5088eSShreyas Bhatewara 81509c5088eSShreyas Bhatewara 816d1a890faSShreyas Bhatewara /* 817cec05562SNeil Horman * parse relevant protocol headers: 818d1a890faSShreyas Bhatewara * For a tso pkt, relevant headers are L2/3/4 including options 819d1a890faSShreyas Bhatewara * For a pkt requesting csum offloading, they are L2/3 and may include L4 820d1a890faSShreyas Bhatewara * if it's a TCP/UDP pkt 821d1a890faSShreyas Bhatewara * 822d1a890faSShreyas Bhatewara * Returns: 823d1a890faSShreyas Bhatewara * -1: error happens during parsing 824d1a890faSShreyas Bhatewara * 0: protocol headers parsed, but too big to be copied 825d1a890faSShreyas Bhatewara * 1: protocol headers parsed and copied 826d1a890faSShreyas Bhatewara * 827d1a890faSShreyas Bhatewara * Other effects: 828d1a890faSShreyas Bhatewara * 1. related *ctx fields are updated. 829d1a890faSShreyas Bhatewara * 2. ctx->copy_size is # of bytes copied 830cec05562SNeil Horman * 3. the portion to be copied is guaranteed to be in the linear part 831d1a890faSShreyas Bhatewara * 832d1a890faSShreyas Bhatewara */ 833d1a890faSShreyas Bhatewara static int 834cec05562SNeil Horman vmxnet3_parse_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 835d1a890faSShreyas Bhatewara struct vmxnet3_tx_ctx *ctx, 836d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 837d1a890faSShreyas Bhatewara { 838759c9359SShrikrishna Khare u8 protocol = 0; 839d1a890faSShreyas Bhatewara 8400d0b1672SMichał Mirosław if (ctx->mss) { /* TSO */ 841dacce2beSRonak Doshi if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) { 842dacce2beSRonak Doshi ctx->l4_offset = skb_inner_transport_offset(skb); 843dacce2beSRonak Doshi ctx->l4_hdr_size = inner_tcp_hdrlen(skb); 844dacce2beSRonak Doshi ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size; 845dacce2beSRonak Doshi } else { 846dacce2beSRonak Doshi ctx->l4_offset = skb_transport_offset(skb); 8478bca5d1eSEric Dumazet ctx->l4_hdr_size = tcp_hdrlen(skb); 848dacce2beSRonak Doshi ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size; 849dacce2beSRonak Doshi } 850d1a890faSShreyas Bhatewara } else { 851d1a890faSShreyas Bhatewara if (skb->ip_summed == CHECKSUM_PARTIAL) { 852dacce2beSRonak Doshi /* For encap packets, skb_checksum_start_offset refers 853dacce2beSRonak Doshi * to inner L4 offset. Thus, below works for encap as 854dacce2beSRonak Doshi * well as non-encap case 855dacce2beSRonak Doshi */ 856dacce2beSRonak Doshi ctx->l4_offset = skb_checksum_start_offset(skb); 857d1a890faSShreyas Bhatewara 85836432797SRonak Doshi if (VMXNET3_VERSION_GE_4(adapter) && 85936432797SRonak Doshi skb->encapsulation) { 86036432797SRonak Doshi struct iphdr *iph = inner_ip_hdr(skb); 86136432797SRonak Doshi 86236432797SRonak Doshi if (iph->version == 4) { 86336432797SRonak Doshi protocol = iph->protocol; 86436432797SRonak Doshi } else { 86536432797SRonak Doshi const struct ipv6hdr *ipv6h; 86636432797SRonak Doshi 86736432797SRonak Doshi ipv6h = inner_ipv6_hdr(skb); 86836432797SRonak Doshi protocol = ipv6h->nexthdr; 86936432797SRonak Doshi } 87036432797SRonak Doshi } else { 871d1a890faSShreyas Bhatewara if (ctx->ipv4) { 8728bca5d1eSEric Dumazet const struct iphdr *iph = ip_hdr(skb); 8738bca5d1eSEric Dumazet 874759c9359SShrikrishna Khare protocol = iph->protocol; 875759c9359SShrikrishna Khare } else if (ctx->ipv6) { 87636432797SRonak Doshi const struct ipv6hdr *ipv6h; 877759c9359SShrikrishna Khare 87836432797SRonak Doshi ipv6h = ipv6_hdr(skb); 879759c9359SShrikrishna Khare protocol = ipv6h->nexthdr; 880d1a890faSShreyas Bhatewara } 88136432797SRonak Doshi } 882759c9359SShrikrishna Khare 883759c9359SShrikrishna Khare switch (protocol) { 884759c9359SShrikrishna Khare case IPPROTO_TCP: 8858a7f280fSRonak Doshi ctx->l4_hdr_size = skb->encapsulation ? inner_tcp_hdrlen(skb) : 8868a7f280fSRonak Doshi tcp_hdrlen(skb); 887759c9359SShrikrishna Khare break; 888759c9359SShrikrishna Khare case IPPROTO_UDP: 889759c9359SShrikrishna Khare ctx->l4_hdr_size = sizeof(struct udphdr); 890759c9359SShrikrishna Khare break; 891759c9359SShrikrishna Khare default: 892759c9359SShrikrishna Khare ctx->l4_hdr_size = 0; 893759c9359SShrikrishna Khare break; 894759c9359SShrikrishna Khare } 895759c9359SShrikrishna Khare 896dacce2beSRonak Doshi ctx->copy_size = min(ctx->l4_offset + 897b203262dSNeil Horman ctx->l4_hdr_size, skb->len); 898d1a890faSShreyas Bhatewara } else { 899dacce2beSRonak Doshi ctx->l4_offset = 0; 900d1a890faSShreyas Bhatewara ctx->l4_hdr_size = 0; 901d1a890faSShreyas Bhatewara /* copy as much as allowed */ 9023c8b3efcSShrikrishna Khare ctx->copy_size = min_t(unsigned int, 9033c8b3efcSShrikrishna Khare tq->txdata_desc_size, 9043c8b3efcSShrikrishna Khare skb_headlen(skb)); 905d1a890faSShreyas Bhatewara } 906d1a890faSShreyas Bhatewara 907c41fcce9SShreyas Bhatewara if (skb->len <= VMXNET3_HDR_COPY_SIZE) 908c41fcce9SShreyas Bhatewara ctx->copy_size = skb->len; 909c41fcce9SShreyas Bhatewara 910d1a890faSShreyas Bhatewara /* make sure headers are accessible directly */ 911d1a890faSShreyas Bhatewara if (unlikely(!pskb_may_pull(skb, ctx->copy_size))) 912d1a890faSShreyas Bhatewara goto err; 913d1a890faSShreyas Bhatewara } 914d1a890faSShreyas Bhatewara 9153c8b3efcSShrikrishna Khare if (unlikely(ctx->copy_size > tq->txdata_desc_size)) { 916d1a890faSShreyas Bhatewara tq->stats.oversized_hdr++; 917d1a890faSShreyas Bhatewara ctx->copy_size = 0; 918d1a890faSShreyas Bhatewara return 0; 919d1a890faSShreyas Bhatewara } 920d1a890faSShreyas Bhatewara 921cec05562SNeil Horman return 1; 922cec05562SNeil Horman err: 923cec05562SNeil Horman return -1; 924cec05562SNeil Horman } 925cec05562SNeil Horman 926cec05562SNeil Horman /* 927cec05562SNeil Horman * copy relevant protocol headers to the transmit ring: 928cec05562SNeil Horman * For a tso pkt, relevant headers are L2/3/4 including options 929cec05562SNeil Horman * For a pkt requesting csum offloading, they are L2/3 and may include L4 930cec05562SNeil Horman * if it's a TCP/UDP pkt 931cec05562SNeil Horman * 932cec05562SNeil Horman * 933cec05562SNeil Horman * Note that this requires that vmxnet3_parse_hdr be called first to set the 934cec05562SNeil Horman * appropriate bits in ctx first 935cec05562SNeil Horman */ 936cec05562SNeil Horman static void 937cec05562SNeil Horman vmxnet3_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 938cec05562SNeil Horman struct vmxnet3_tx_ctx *ctx, 939cec05562SNeil Horman struct vmxnet3_adapter *adapter) 940cec05562SNeil Horman { 941cec05562SNeil Horman struct Vmxnet3_TxDataDesc *tdd; 942cec05562SNeil Horman 943ff2e7d5dSShrikrishna Khare tdd = (struct Vmxnet3_TxDataDesc *)((u8 *)tq->data_ring.base + 944ff2e7d5dSShrikrishna Khare tq->tx_ring.next2fill * 945ff2e7d5dSShrikrishna Khare tq->txdata_desc_size); 946d1a890faSShreyas Bhatewara 947d1a890faSShreyas Bhatewara memcpy(tdd->data, skb->data, ctx->copy_size); 948fdcd79b9SStephen Hemminger netdev_dbg(adapter->netdev, 949f6965582SRandy Dunlap "copy %u bytes to dataRing[%u]\n", 950d1a890faSShreyas Bhatewara ctx->copy_size, tq->tx_ring.next2fill); 951d1a890faSShreyas Bhatewara } 952d1a890faSShreyas Bhatewara 953d1a890faSShreyas Bhatewara 954d1a890faSShreyas Bhatewara static void 955dacce2beSRonak Doshi vmxnet3_prepare_inner_tso(struct sk_buff *skb, 956dacce2beSRonak Doshi struct vmxnet3_tx_ctx *ctx) 957dacce2beSRonak Doshi { 958dacce2beSRonak Doshi struct tcphdr *tcph = inner_tcp_hdr(skb); 959dacce2beSRonak Doshi struct iphdr *iph = inner_ip_hdr(skb); 960dacce2beSRonak Doshi 96136432797SRonak Doshi if (iph->version == 4) { 962dacce2beSRonak Doshi iph->check = 0; 963dacce2beSRonak Doshi tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0, 964dacce2beSRonak Doshi IPPROTO_TCP, 0); 96536432797SRonak Doshi } else { 966dacce2beSRonak Doshi struct ipv6hdr *iph = inner_ipv6_hdr(skb); 967dacce2beSRonak Doshi 968dacce2beSRonak Doshi tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0, 969dacce2beSRonak Doshi IPPROTO_TCP, 0); 970dacce2beSRonak Doshi } 971dacce2beSRonak Doshi } 972dacce2beSRonak Doshi 973dacce2beSRonak Doshi static void 974d1a890faSShreyas Bhatewara vmxnet3_prepare_tso(struct sk_buff *skb, 975d1a890faSShreyas Bhatewara struct vmxnet3_tx_ctx *ctx) 976d1a890faSShreyas Bhatewara { 9778bca5d1eSEric Dumazet struct tcphdr *tcph = tcp_hdr(skb); 9788bca5d1eSEric Dumazet 979d1a890faSShreyas Bhatewara if (ctx->ipv4) { 9808bca5d1eSEric Dumazet struct iphdr *iph = ip_hdr(skb); 9818bca5d1eSEric Dumazet 982d1a890faSShreyas Bhatewara iph->check = 0; 983d1a890faSShreyas Bhatewara tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0, 984d1a890faSShreyas Bhatewara IPPROTO_TCP, 0); 985759c9359SShrikrishna Khare } else if (ctx->ipv6) { 986091c9f82SHeiner Kallweit tcp_v6_gso_csum_prep(skb); 987d1a890faSShreyas Bhatewara } 988d1a890faSShreyas Bhatewara } 989d1a890faSShreyas Bhatewara 990a4d7e485SEric Dumazet static int txd_estimate(const struct sk_buff *skb) 991a4d7e485SEric Dumazet { 992a4d7e485SEric Dumazet int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1; 993a4d7e485SEric Dumazet int i; 994a4d7e485SEric Dumazet 995a4d7e485SEric Dumazet for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 996d7840976SMatthew Wilcox (Oracle) const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 997a4d7e485SEric Dumazet 998a4d7e485SEric Dumazet count += VMXNET3_TXD_NEEDED(skb_frag_size(frag)); 999a4d7e485SEric Dumazet } 1000a4d7e485SEric Dumazet return count; 1001a4d7e485SEric Dumazet } 1002d1a890faSShreyas Bhatewara 1003d1a890faSShreyas Bhatewara /* 1004d1a890faSShreyas Bhatewara * Transmits a pkt thru a given tq 1005d1a890faSShreyas Bhatewara * Returns: 1006d1a890faSShreyas Bhatewara * NETDEV_TX_OK: descriptors are setup successfully 100725985edcSLucas De Marchi * NETDEV_TX_OK: error occurred, the pkt is dropped 1008d1a890faSShreyas Bhatewara * NETDEV_TX_BUSY: tx ring is full, queue is stopped 1009d1a890faSShreyas Bhatewara * 1010d1a890faSShreyas Bhatewara * Side-effects: 1011d1a890faSShreyas Bhatewara * 1. tx ring may be changed 1012d1a890faSShreyas Bhatewara * 2. tq stats may be updated accordingly 1013d1a890faSShreyas Bhatewara * 3. shared->txNumDeferred may be updated 1014d1a890faSShreyas Bhatewara */ 1015d1a890faSShreyas Bhatewara 1016d1a890faSShreyas Bhatewara static int 1017d1a890faSShreyas Bhatewara vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 1018d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter, struct net_device *netdev) 1019d1a890faSShreyas Bhatewara { 1020d1a890faSShreyas Bhatewara int ret; 1021d1a890faSShreyas Bhatewara u32 count; 10227a4c003dSRonak Doshi int num_pkts; 10237a4c003dSRonak Doshi int tx_num_deferred; 1024d1a890faSShreyas Bhatewara unsigned long flags; 1025d1a890faSShreyas Bhatewara struct vmxnet3_tx_ctx ctx; 1026d1a890faSShreyas Bhatewara union Vmxnet3_GenericDesc *gdesc; 1027115924b6SShreyas Bhatewara #ifdef __BIG_ENDIAN_BITFIELD 1028115924b6SShreyas Bhatewara /* Use temporary descriptor to avoid touching bits multiple times */ 1029115924b6SShreyas Bhatewara union Vmxnet3_GenericDesc tempTxDesc; 1030115924b6SShreyas Bhatewara #endif 1031d1a890faSShreyas Bhatewara 1032a4d7e485SEric Dumazet count = txd_estimate(skb); 1033d1a890faSShreyas Bhatewara 103472e85c45SJesse Gross ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP)); 1035759c9359SShrikrishna Khare ctx.ipv6 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IPV6)); 1036d1a890faSShreyas Bhatewara 1037d1a890faSShreyas Bhatewara ctx.mss = skb_shinfo(skb)->gso_size; 1038d1a890faSShreyas Bhatewara if (ctx.mss) { 1039d1a890faSShreyas Bhatewara if (skb_header_cloned(skb)) { 1040d1a890faSShreyas Bhatewara if (unlikely(pskb_expand_head(skb, 0, 0, 1041d1a890faSShreyas Bhatewara GFP_ATOMIC) != 0)) { 1042d1a890faSShreyas Bhatewara tq->stats.drop_tso++; 1043d1a890faSShreyas Bhatewara goto drop_pkt; 1044d1a890faSShreyas Bhatewara } 1045d1a890faSShreyas Bhatewara tq->stats.copy_skb_header++; 1046d1a890faSShreyas Bhatewara } 1047dacce2beSRonak Doshi if (skb->encapsulation) { 1048dacce2beSRonak Doshi vmxnet3_prepare_inner_tso(skb, &ctx); 1049dacce2beSRonak Doshi } else { 1050d1a890faSShreyas Bhatewara vmxnet3_prepare_tso(skb, &ctx); 1051dacce2beSRonak Doshi } 1052d1a890faSShreyas Bhatewara } else { 1053d1a890faSShreyas Bhatewara if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) { 1054d1a890faSShreyas Bhatewara 1055d1a890faSShreyas Bhatewara /* non-tso pkts must not use more than 1056d1a890faSShreyas Bhatewara * VMXNET3_MAX_TXD_PER_PKT entries 1057d1a890faSShreyas Bhatewara */ 1058d1a890faSShreyas Bhatewara if (skb_linearize(skb) != 0) { 1059d1a890faSShreyas Bhatewara tq->stats.drop_too_many_frags++; 1060d1a890faSShreyas Bhatewara goto drop_pkt; 1061d1a890faSShreyas Bhatewara } 1062d1a890faSShreyas Bhatewara tq->stats.linearized++; 1063d1a890faSShreyas Bhatewara 1064d1a890faSShreyas Bhatewara /* recalculate the # of descriptors to use */ 1065d1a890faSShreyas Bhatewara count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1; 1066d1a890faSShreyas Bhatewara } 1067d1a890faSShreyas Bhatewara } 1068d1a890faSShreyas Bhatewara 1069cec05562SNeil Horman ret = vmxnet3_parse_hdr(skb, tq, &ctx, adapter); 1070d1a890faSShreyas Bhatewara if (ret >= 0) { 1071d1a890faSShreyas Bhatewara BUG_ON(ret <= 0 && ctx.copy_size != 0); 1072d1a890faSShreyas Bhatewara /* hdrs parsed, check against other limits */ 1073d1a890faSShreyas Bhatewara if (ctx.mss) { 1074dacce2beSRonak Doshi if (unlikely(ctx.l4_offset + ctx.l4_hdr_size > 1075d1a890faSShreyas Bhatewara VMXNET3_MAX_TX_BUF_SIZE)) { 1076efc21d95SArnd Bergmann tq->stats.drop_oversized_hdr++; 1077efc21d95SArnd Bergmann goto drop_pkt; 1078d1a890faSShreyas Bhatewara } 1079d1a890faSShreyas Bhatewara } else { 1080d1a890faSShreyas Bhatewara if (skb->ip_summed == CHECKSUM_PARTIAL) { 1081dacce2beSRonak Doshi if (unlikely(ctx.l4_offset + 1082d1a890faSShreyas Bhatewara skb->csum_offset > 1083d1a890faSShreyas Bhatewara VMXNET3_MAX_CSUM_OFFSET)) { 1084efc21d95SArnd Bergmann tq->stats.drop_oversized_hdr++; 1085efc21d95SArnd Bergmann goto drop_pkt; 1086d1a890faSShreyas Bhatewara } 1087d1a890faSShreyas Bhatewara } 1088d1a890faSShreyas Bhatewara } 1089d1a890faSShreyas Bhatewara } else { 1090d1a890faSShreyas Bhatewara tq->stats.drop_hdr_inspect_err++; 1091cec05562SNeil Horman goto drop_pkt; 1092d1a890faSShreyas Bhatewara } 1093d1a890faSShreyas Bhatewara 1094cec05562SNeil Horman spin_lock_irqsave(&tq->tx_lock, flags); 1095cec05562SNeil Horman 1096cec05562SNeil Horman if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) { 1097cec05562SNeil Horman tq->stats.tx_ring_full++; 1098cec05562SNeil Horman netdev_dbg(adapter->netdev, 1099cec05562SNeil Horman "tx queue stopped on %s, next2comp %u" 1100cec05562SNeil Horman " next2fill %u\n", adapter->netdev->name, 1101cec05562SNeil Horman tq->tx_ring.next2comp, tq->tx_ring.next2fill); 1102cec05562SNeil Horman 1103cec05562SNeil Horman vmxnet3_tq_stop(tq, adapter); 1104cec05562SNeil Horman spin_unlock_irqrestore(&tq->tx_lock, flags); 1105cec05562SNeil Horman return NETDEV_TX_BUSY; 1106cec05562SNeil Horman } 1107cec05562SNeil Horman 1108cec05562SNeil Horman 1109cec05562SNeil Horman vmxnet3_copy_hdr(skb, tq, &ctx, adapter); 1110cec05562SNeil Horman 1111d1a890faSShreyas Bhatewara /* fill tx descs related to addr & len */ 11125738a09dSAlexey Khoroshilov if (vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter)) 11135738a09dSAlexey Khoroshilov goto unlock_drop_pkt; 1114d1a890faSShreyas Bhatewara 1115d1a890faSShreyas Bhatewara /* setup the EOP desc */ 1116115924b6SShreyas Bhatewara ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP); 1117d1a890faSShreyas Bhatewara 1118d1a890faSShreyas Bhatewara /* setup the SOP desc */ 1119115924b6SShreyas Bhatewara #ifdef __BIG_ENDIAN_BITFIELD 1120115924b6SShreyas Bhatewara gdesc = &tempTxDesc; 1121115924b6SShreyas Bhatewara gdesc->dword[2] = ctx.sop_txd->dword[2]; 1122115924b6SShreyas Bhatewara gdesc->dword[3] = ctx.sop_txd->dword[3]; 1123115924b6SShreyas Bhatewara #else 1124d1a890faSShreyas Bhatewara gdesc = ctx.sop_txd; 1125115924b6SShreyas Bhatewara #endif 11267a4c003dSRonak Doshi tx_num_deferred = le32_to_cpu(tq->shared->txNumDeferred); 1127d1a890faSShreyas Bhatewara if (ctx.mss) { 1128dacce2beSRonak Doshi if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) { 1129dacce2beSRonak Doshi gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size; 1130dacce2beSRonak Doshi gdesc->txd.om = VMXNET3_OM_ENCAP; 1131dacce2beSRonak Doshi gdesc->txd.msscof = ctx.mss; 1132dacce2beSRonak Doshi 11331dac3b1bSRonak Doshi if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM) 1134dacce2beSRonak Doshi gdesc->txd.oco = 1; 1135dacce2beSRonak Doshi } else { 1136dacce2beSRonak Doshi gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size; 1137d1a890faSShreyas Bhatewara gdesc->txd.om = VMXNET3_OM_TSO; 1138d1a890faSShreyas Bhatewara gdesc->txd.msscof = ctx.mss; 1139dacce2beSRonak Doshi } 11407a4c003dSRonak Doshi num_pkts = (skb->len - gdesc->txd.hlen + ctx.mss - 1) / ctx.mss; 1141d1a890faSShreyas Bhatewara } else { 1142d1a890faSShreyas Bhatewara if (skb->ip_summed == CHECKSUM_PARTIAL) { 1143dacce2beSRonak Doshi if (VMXNET3_VERSION_GE_4(adapter) && 1144dacce2beSRonak Doshi skb->encapsulation) { 1145dacce2beSRonak Doshi gdesc->txd.hlen = ctx.l4_offset + 1146dacce2beSRonak Doshi ctx.l4_hdr_size; 1147dacce2beSRonak Doshi gdesc->txd.om = VMXNET3_OM_ENCAP; 1148dacce2beSRonak Doshi gdesc->txd.msscof = 0; /* Reserved */ 1149dacce2beSRonak Doshi } else { 1150dacce2beSRonak Doshi gdesc->txd.hlen = ctx.l4_offset; 1151d1a890faSShreyas Bhatewara gdesc->txd.om = VMXNET3_OM_CSUM; 1152dacce2beSRonak Doshi gdesc->txd.msscof = ctx.l4_offset + 1153d1a890faSShreyas Bhatewara skb->csum_offset; 1154dacce2beSRonak Doshi } 1155d1a890faSShreyas Bhatewara } else { 1156d1a890faSShreyas Bhatewara gdesc->txd.om = 0; 1157d1a890faSShreyas Bhatewara gdesc->txd.msscof = 0; 1158d1a890faSShreyas Bhatewara } 11597a4c003dSRonak Doshi num_pkts = 1; 1160d1a890faSShreyas Bhatewara } 11617a4c003dSRonak Doshi le32_add_cpu(&tq->shared->txNumDeferred, num_pkts); 11627a4c003dSRonak Doshi tx_num_deferred += num_pkts; 1163d1a890faSShreyas Bhatewara 1164df8a39deSJiri Pirko if (skb_vlan_tag_present(skb)) { 1165d1a890faSShreyas Bhatewara gdesc->txd.ti = 1; 1166df8a39deSJiri Pirko gdesc->txd.tci = skb_vlan_tag_get(skb); 1167d1a890faSShreyas Bhatewara } 1168d1a890faSShreyas Bhatewara 1169f3002c13Shpreg@vmware.com /* Ensure that the write to (&gdesc->txd)->gen will be observed after 1170f3002c13Shpreg@vmware.com * all other writes to &gdesc->txd. 1171f3002c13Shpreg@vmware.com */ 1172f3002c13Shpreg@vmware.com dma_wmb(); 1173f3002c13Shpreg@vmware.com 1174115924b6SShreyas Bhatewara /* finally flips the GEN bit of the SOP desc. */ 1175115924b6SShreyas Bhatewara gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^ 1176115924b6SShreyas Bhatewara VMXNET3_TXD_GEN); 1177115924b6SShreyas Bhatewara #ifdef __BIG_ENDIAN_BITFIELD 1178115924b6SShreyas Bhatewara /* Finished updating in bitfields of Tx Desc, so write them in original 1179115924b6SShreyas Bhatewara * place. 1180115924b6SShreyas Bhatewara */ 1181115924b6SShreyas Bhatewara vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc, 1182115924b6SShreyas Bhatewara (struct Vmxnet3_TxDesc *)ctx.sop_txd); 1183115924b6SShreyas Bhatewara gdesc = ctx.sop_txd; 1184115924b6SShreyas Bhatewara #endif 1185fdcd79b9SStephen Hemminger netdev_dbg(adapter->netdev, 1186f6965582SRandy Dunlap "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n", 1187c2fd03a0SJoe Perches (u32)(ctx.sop_txd - 1188115924b6SShreyas Bhatewara tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr), 1189115924b6SShreyas Bhatewara le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3])); 1190d1a890faSShreyas Bhatewara 1191d1a890faSShreyas Bhatewara spin_unlock_irqrestore(&tq->tx_lock, flags); 1192d1a890faSShreyas Bhatewara 11937a4c003dSRonak Doshi if (tx_num_deferred >= le32_to_cpu(tq->shared->txThreshold)) { 1194d1a890faSShreyas Bhatewara tq->shared->txNumDeferred = 0; 119509c5088eSShreyas Bhatewara VMXNET3_WRITE_BAR0_REG(adapter, 119609c5088eSShreyas Bhatewara VMXNET3_REG_TXPROD + tq->qid * 8, 1197d1a890faSShreyas Bhatewara tq->tx_ring.next2fill); 1198d1a890faSShreyas Bhatewara } 1199d1a890faSShreyas Bhatewara 1200d1a890faSShreyas Bhatewara return NETDEV_TX_OK; 1201d1a890faSShreyas Bhatewara 1202f955e141SDan Carpenter unlock_drop_pkt: 1203f955e141SDan Carpenter spin_unlock_irqrestore(&tq->tx_lock, flags); 1204d1a890faSShreyas Bhatewara drop_pkt: 1205d1a890faSShreyas Bhatewara tq->stats.drop_total++; 1206b1b71817SEric W. Biederman dev_kfree_skb_any(skb); 1207d1a890faSShreyas Bhatewara return NETDEV_TX_OK; 1208d1a890faSShreyas Bhatewara } 1209d1a890faSShreyas Bhatewara 1210d1a890faSShreyas Bhatewara 1211d1a890faSShreyas Bhatewara static netdev_tx_t 1212d1a890faSShreyas Bhatewara vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 1213d1a890faSShreyas Bhatewara { 1214d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1215d1a890faSShreyas Bhatewara 121609c5088eSShreyas Bhatewara BUG_ON(skb->queue_mapping > adapter->num_tx_queues); 121709c5088eSShreyas Bhatewara return vmxnet3_tq_xmit(skb, 121809c5088eSShreyas Bhatewara &adapter->tx_queue[skb->queue_mapping], 121909c5088eSShreyas Bhatewara adapter, netdev); 1220d1a890faSShreyas Bhatewara } 1221d1a890faSShreyas Bhatewara 1222d1a890faSShreyas Bhatewara 1223d1a890faSShreyas Bhatewara static void 1224d1a890faSShreyas Bhatewara vmxnet3_rx_csum(struct vmxnet3_adapter *adapter, 1225d1a890faSShreyas Bhatewara struct sk_buff *skb, 1226d1a890faSShreyas Bhatewara union Vmxnet3_GenericDesc *gdesc) 1227d1a890faSShreyas Bhatewara { 1228a0d2730cSMichał Mirosław if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) { 1229f0d43780SShrikrishna Khare if (gdesc->rcd.v4 && 1230f0d43780SShrikrishna Khare (le32_to_cpu(gdesc->dword[3]) & 1231f0d43780SShrikrishna Khare VMXNET3_RCD_CSUM_OK) == VMXNET3_RCD_CSUM_OK) { 1232d1a890faSShreyas Bhatewara skb->ip_summed = CHECKSUM_UNNECESSARY; 1233dacce2beSRonak Doshi WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) && 1234dacce2beSRonak Doshi !(le32_to_cpu(gdesc->dword[0]) & 1235dacce2beSRonak Doshi (1UL << VMXNET3_RCD_HDR_INNER_SHIFT))); 1236dacce2beSRonak Doshi WARN_ON_ONCE(gdesc->rcd.frg && 1237dacce2beSRonak Doshi !(le32_to_cpu(gdesc->dword[0]) & 1238dacce2beSRonak Doshi (1UL << VMXNET3_RCD_HDR_INNER_SHIFT))); 1239f0d43780SShrikrishna Khare } else if (gdesc->rcd.v6 && (le32_to_cpu(gdesc->dword[3]) & 1240f0d43780SShrikrishna Khare (1 << VMXNET3_RCD_TUC_SHIFT))) { 1241f0d43780SShrikrishna Khare skb->ip_summed = CHECKSUM_UNNECESSARY; 1242dacce2beSRonak Doshi WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) && 1243dacce2beSRonak Doshi !(le32_to_cpu(gdesc->dword[0]) & 1244dacce2beSRonak Doshi (1UL << VMXNET3_RCD_HDR_INNER_SHIFT))); 1245dacce2beSRonak Doshi WARN_ON_ONCE(gdesc->rcd.frg && 1246dacce2beSRonak Doshi !(le32_to_cpu(gdesc->dword[0]) & 1247dacce2beSRonak Doshi (1UL << VMXNET3_RCD_HDR_INNER_SHIFT))); 1248d1a890faSShreyas Bhatewara } else { 1249d1a890faSShreyas Bhatewara if (gdesc->rcd.csum) { 1250d1a890faSShreyas Bhatewara skb->csum = htons(gdesc->rcd.csum); 1251d1a890faSShreyas Bhatewara skb->ip_summed = CHECKSUM_PARTIAL; 1252d1a890faSShreyas Bhatewara } else { 1253bc8acf2cSEric Dumazet skb_checksum_none_assert(skb); 1254d1a890faSShreyas Bhatewara } 1255d1a890faSShreyas Bhatewara } 1256d1a890faSShreyas Bhatewara } else { 1257bc8acf2cSEric Dumazet skb_checksum_none_assert(skb); 1258d1a890faSShreyas Bhatewara } 1259d1a890faSShreyas Bhatewara } 1260d1a890faSShreyas Bhatewara 1261d1a890faSShreyas Bhatewara 1262d1a890faSShreyas Bhatewara static void 1263d1a890faSShreyas Bhatewara vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd, 1264d1a890faSShreyas Bhatewara struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter) 1265d1a890faSShreyas Bhatewara { 1266d1a890faSShreyas Bhatewara rq->stats.drop_err++; 1267d1a890faSShreyas Bhatewara if (!rcd->fcs) 1268d1a890faSShreyas Bhatewara rq->stats.drop_fcs++; 1269d1a890faSShreyas Bhatewara 1270d1a890faSShreyas Bhatewara rq->stats.drop_total++; 1271d1a890faSShreyas Bhatewara 1272d1a890faSShreyas Bhatewara /* 1273d1a890faSShreyas Bhatewara * We do not unmap and chain the rx buffer to the skb. 1274d1a890faSShreyas Bhatewara * We basically pretend this buffer is not used and will be recycled 1275d1a890faSShreyas Bhatewara * by vmxnet3_rq_alloc_rx_buf() 1276d1a890faSShreyas Bhatewara */ 1277d1a890faSShreyas Bhatewara 1278d1a890faSShreyas Bhatewara /* 1279d1a890faSShreyas Bhatewara * ctx->skb may be NULL if this is the first and the only one 1280d1a890faSShreyas Bhatewara * desc for the pkt 1281d1a890faSShreyas Bhatewara */ 1282d1a890faSShreyas Bhatewara if (ctx->skb) 1283d1a890faSShreyas Bhatewara dev_kfree_skb_irq(ctx->skb); 1284d1a890faSShreyas Bhatewara 1285d1a890faSShreyas Bhatewara ctx->skb = NULL; 1286d1a890faSShreyas Bhatewara } 1287d1a890faSShreyas Bhatewara 1288d1a890faSShreyas Bhatewara 128945dac1d6SShreyas Bhatewara static u32 129045dac1d6SShreyas Bhatewara vmxnet3_get_hdr_len(struct vmxnet3_adapter *adapter, struct sk_buff *skb, 129145dac1d6SShreyas Bhatewara union Vmxnet3_GenericDesc *gdesc) 129245dac1d6SShreyas Bhatewara { 129345dac1d6SShreyas Bhatewara u32 hlen, maplen; 129445dac1d6SShreyas Bhatewara union { 129545dac1d6SShreyas Bhatewara void *ptr; 129645dac1d6SShreyas Bhatewara struct ethhdr *eth; 129765ec0bd1SRonak Doshi struct vlan_ethhdr *veth; 129845dac1d6SShreyas Bhatewara struct iphdr *ipv4; 129945dac1d6SShreyas Bhatewara struct ipv6hdr *ipv6; 130045dac1d6SShreyas Bhatewara struct tcphdr *tcp; 130145dac1d6SShreyas Bhatewara } hdr; 130245dac1d6SShreyas Bhatewara BUG_ON(gdesc->rcd.tcp == 0); 130345dac1d6SShreyas Bhatewara 130445dac1d6SShreyas Bhatewara maplen = skb_headlen(skb); 130545dac1d6SShreyas Bhatewara if (unlikely(sizeof(struct iphdr) + sizeof(struct tcphdr) > maplen)) 130645dac1d6SShreyas Bhatewara return 0; 130745dac1d6SShreyas Bhatewara 130865ec0bd1SRonak Doshi if (skb->protocol == cpu_to_be16(ETH_P_8021Q) || 130965ec0bd1SRonak Doshi skb->protocol == cpu_to_be16(ETH_P_8021AD)) 131065ec0bd1SRonak Doshi hlen = sizeof(struct vlan_ethhdr); 131165ec0bd1SRonak Doshi else 131265ec0bd1SRonak Doshi hlen = sizeof(struct ethhdr); 131365ec0bd1SRonak Doshi 131445dac1d6SShreyas Bhatewara hdr.eth = eth_hdr(skb); 131545dac1d6SShreyas Bhatewara if (gdesc->rcd.v4) { 131665ec0bd1SRonak Doshi BUG_ON(hdr.eth->h_proto != htons(ETH_P_IP) && 131765ec0bd1SRonak Doshi hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IP)); 131865ec0bd1SRonak Doshi hdr.ptr += hlen; 131945dac1d6SShreyas Bhatewara BUG_ON(hdr.ipv4->protocol != IPPROTO_TCP); 132045dac1d6SShreyas Bhatewara hlen = hdr.ipv4->ihl << 2; 132145dac1d6SShreyas Bhatewara hdr.ptr += hdr.ipv4->ihl << 2; 132245dac1d6SShreyas Bhatewara } else if (gdesc->rcd.v6) { 132365ec0bd1SRonak Doshi BUG_ON(hdr.eth->h_proto != htons(ETH_P_IPV6) && 132465ec0bd1SRonak Doshi hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IPV6)); 132565ec0bd1SRonak Doshi hdr.ptr += hlen; 132645dac1d6SShreyas Bhatewara /* Use an estimated value, since we also need to handle 132745dac1d6SShreyas Bhatewara * TSO case. 132845dac1d6SShreyas Bhatewara */ 132945dac1d6SShreyas Bhatewara if (hdr.ipv6->nexthdr != IPPROTO_TCP) 133045dac1d6SShreyas Bhatewara return sizeof(struct ipv6hdr) + sizeof(struct tcphdr); 133145dac1d6SShreyas Bhatewara hlen = sizeof(struct ipv6hdr); 133245dac1d6SShreyas Bhatewara hdr.ptr += sizeof(struct ipv6hdr); 133345dac1d6SShreyas Bhatewara } else { 133445dac1d6SShreyas Bhatewara /* Non-IP pkt, dont estimate header length */ 133545dac1d6SShreyas Bhatewara return 0; 133645dac1d6SShreyas Bhatewara } 133745dac1d6SShreyas Bhatewara 133845dac1d6SShreyas Bhatewara if (hlen + sizeof(struct tcphdr) > maplen) 133945dac1d6SShreyas Bhatewara return 0; 134045dac1d6SShreyas Bhatewara 134145dac1d6SShreyas Bhatewara return (hlen + (hdr.tcp->doff << 2)); 134245dac1d6SShreyas Bhatewara } 134345dac1d6SShreyas Bhatewara 1344d1a890faSShreyas Bhatewara static int 1345d1a890faSShreyas Bhatewara vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq, 1346d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter, int quota) 1347d1a890faSShreyas Bhatewara { 1348215faf9cSJoe Perches static const u32 rxprod_reg[2] = { 1349215faf9cSJoe Perches VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2 1350215faf9cSJoe Perches }; 13510769636cSNeil Horman u32 num_pkts = 0; 13525318d809SShreyas Bhatewara bool skip_page_frags = false; 1353d1a890faSShreyas Bhatewara struct Vmxnet3_RxCompDesc *rcd; 1354d1a890faSShreyas Bhatewara struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx; 135545dac1d6SShreyas Bhatewara u16 segCnt = 0, mss = 0; 1356115924b6SShreyas Bhatewara #ifdef __BIG_ENDIAN_BITFIELD 1357115924b6SShreyas Bhatewara struct Vmxnet3_RxDesc rxCmdDesc; 1358115924b6SShreyas Bhatewara struct Vmxnet3_RxCompDesc rxComp; 1359115924b6SShreyas Bhatewara #endif 1360115924b6SShreyas Bhatewara vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, 1361115924b6SShreyas Bhatewara &rxComp); 1362d1a890faSShreyas Bhatewara while (rcd->gen == rq->comp_ring.gen) { 1363d1a890faSShreyas Bhatewara struct vmxnet3_rx_buf_info *rbi; 13645318d809SShreyas Bhatewara struct sk_buff *skb, *new_skb = NULL; 13655318d809SShreyas Bhatewara struct page *new_page = NULL; 13665738a09dSAlexey Khoroshilov dma_addr_t new_dma_addr; 1367d1a890faSShreyas Bhatewara int num_to_alloc; 1368d1a890faSShreyas Bhatewara struct Vmxnet3_RxDesc *rxd; 1369d1a890faSShreyas Bhatewara u32 idx, ring_idx; 13705318d809SShreyas Bhatewara struct vmxnet3_cmd_ring *ring = NULL; 13710769636cSNeil Horman if (num_pkts >= quota) { 1372d1a890faSShreyas Bhatewara /* we may stop even before we see the EOP desc of 1373d1a890faSShreyas Bhatewara * the current pkt 1374d1a890faSShreyas Bhatewara */ 1375d1a890faSShreyas Bhatewara break; 1376d1a890faSShreyas Bhatewara } 1377f3002c13Shpreg@vmware.com 1378f3002c13Shpreg@vmware.com /* Prevent any rcd field from being (speculatively) read before 1379f3002c13Shpreg@vmware.com * rcd->gen is read. 1380f3002c13Shpreg@vmware.com */ 1381f3002c13Shpreg@vmware.com dma_rmb(); 1382f3002c13Shpreg@vmware.com 138350a5ce3eSShrikrishna Khare BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2 && 138450a5ce3eSShrikrishna Khare rcd->rqID != rq->dataRingQid); 1385d1a890faSShreyas Bhatewara idx = rcd->rxdIdx; 138650a5ce3eSShrikrishna Khare ring_idx = VMXNET3_GET_RING_IDX(adapter, rcd->rqID); 13875318d809SShreyas Bhatewara ring = rq->rx_ring + ring_idx; 1388115924b6SShreyas Bhatewara vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd, 1389115924b6SShreyas Bhatewara &rxCmdDesc); 1390d1a890faSShreyas Bhatewara rbi = rq->buf_info[ring_idx] + idx; 1391d1a890faSShreyas Bhatewara 1392115924b6SShreyas Bhatewara BUG_ON(rxd->addr != rbi->dma_addr || 1393115924b6SShreyas Bhatewara rxd->len != rbi->len); 1394d1a890faSShreyas Bhatewara 1395d1a890faSShreyas Bhatewara if (unlikely(rcd->eop && rcd->err)) { 1396d1a890faSShreyas Bhatewara vmxnet3_rx_error(rq, rcd, ctx, adapter); 1397d1a890faSShreyas Bhatewara goto rcd_done; 1398d1a890faSShreyas Bhatewara } 1399d1a890faSShreyas Bhatewara 1400d1a890faSShreyas Bhatewara if (rcd->sop) { /* first buf of the pkt */ 140150a5ce3eSShrikrishna Khare bool rxDataRingUsed; 140250a5ce3eSShrikrishna Khare u16 len; 140350a5ce3eSShrikrishna Khare 1404d1a890faSShreyas Bhatewara BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD || 140550a5ce3eSShrikrishna Khare (rcd->rqID != rq->qid && 140650a5ce3eSShrikrishna Khare rcd->rqID != rq->dataRingQid)); 1407d1a890faSShreyas Bhatewara 1408d1a890faSShreyas Bhatewara BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB); 1409d1a890faSShreyas Bhatewara BUG_ON(ctx->skb != NULL || rbi->skb == NULL); 1410d1a890faSShreyas Bhatewara 1411d1a890faSShreyas Bhatewara if (unlikely(rcd->len == 0)) { 1412d1a890faSShreyas Bhatewara /* Pretend the rx buffer is skipped. */ 1413d1a890faSShreyas Bhatewara BUG_ON(!(rcd->sop && rcd->eop)); 1414fdcd79b9SStephen Hemminger netdev_dbg(adapter->netdev, 1415f6965582SRandy Dunlap "rxRing[%u][%u] 0 length\n", 1416d1a890faSShreyas Bhatewara ring_idx, idx); 1417d1a890faSShreyas Bhatewara goto rcd_done; 1418d1a890faSShreyas Bhatewara } 1419d1a890faSShreyas Bhatewara 14205318d809SShreyas Bhatewara skip_page_frags = false; 1421d1a890faSShreyas Bhatewara ctx->skb = rbi->skb; 142250a5ce3eSShrikrishna Khare 142350a5ce3eSShrikrishna Khare rxDataRingUsed = 142450a5ce3eSShrikrishna Khare VMXNET3_RX_DATA_RING(adapter, rcd->rqID); 142550a5ce3eSShrikrishna Khare len = rxDataRingUsed ? rcd->len : rbi->len; 14260d735f13SStephen Hemminger new_skb = netdev_alloc_skb_ip_align(adapter->netdev, 142750a5ce3eSShrikrishna Khare len); 14285318d809SShreyas Bhatewara if (new_skb == NULL) { 14295318d809SShreyas Bhatewara /* Skb allocation failed, do not handover this 14305318d809SShreyas Bhatewara * skb to stack. Reuse it. Drop the existing pkt 14315318d809SShreyas Bhatewara */ 14325318d809SShreyas Bhatewara rq->stats.rx_buf_alloc_failure++; 14335318d809SShreyas Bhatewara ctx->skb = NULL; 14345318d809SShreyas Bhatewara rq->stats.drop_total++; 14355318d809SShreyas Bhatewara skip_page_frags = true; 14365318d809SShreyas Bhatewara goto rcd_done; 14375318d809SShreyas Bhatewara } 143850a5ce3eSShrikrishna Khare 143950a5ce3eSShrikrishna Khare if (rxDataRingUsed) { 144050a5ce3eSShrikrishna Khare size_t sz; 144150a5ce3eSShrikrishna Khare 144250a5ce3eSShrikrishna Khare BUG_ON(rcd->len > rq->data_ring.desc_size); 144350a5ce3eSShrikrishna Khare 144450a5ce3eSShrikrishna Khare ctx->skb = new_skb; 144550a5ce3eSShrikrishna Khare sz = rcd->rxdIdx * rq->data_ring.desc_size; 144650a5ce3eSShrikrishna Khare memcpy(new_skb->data, 144750a5ce3eSShrikrishna Khare &rq->data_ring.base[sz], rcd->len); 144850a5ce3eSShrikrishna Khare } else { 144950a5ce3eSShrikrishna Khare ctx->skb = rbi->skb; 145050a5ce3eSShrikrishna Khare 145150a5ce3eSShrikrishna Khare new_dma_addr = 145250a5ce3eSShrikrishna Khare dma_map_single(&adapter->pdev->dev, 14535738a09dSAlexey Khoroshilov new_skb->data, rbi->len, 1454bf7bec46SChristophe JAILLET DMA_FROM_DEVICE); 14555738a09dSAlexey Khoroshilov if (dma_mapping_error(&adapter->pdev->dev, 14565738a09dSAlexey Khoroshilov new_dma_addr)) { 14575738a09dSAlexey Khoroshilov dev_kfree_skb(new_skb); 145850a5ce3eSShrikrishna Khare /* Skb allocation failed, do not 145950a5ce3eSShrikrishna Khare * handover this skb to stack. Reuse 146050a5ce3eSShrikrishna Khare * it. Drop the existing pkt. 14615738a09dSAlexey Khoroshilov */ 14625738a09dSAlexey Khoroshilov rq->stats.rx_buf_alloc_failure++; 14635738a09dSAlexey Khoroshilov ctx->skb = NULL; 14645738a09dSAlexey Khoroshilov rq->stats.drop_total++; 14655738a09dSAlexey Khoroshilov skip_page_frags = true; 14665738a09dSAlexey Khoroshilov goto rcd_done; 14675738a09dSAlexey Khoroshilov } 1468d1a890faSShreyas Bhatewara 146950a5ce3eSShrikrishna Khare dma_unmap_single(&adapter->pdev->dev, 147050a5ce3eSShrikrishna Khare rbi->dma_addr, 1471b0eb57cbSAndy King rbi->len, 1472bf7bec46SChristophe JAILLET DMA_FROM_DEVICE); 1473d1a890faSShreyas Bhatewara 147450a5ce3eSShrikrishna Khare /* Immediate refill */ 147550a5ce3eSShrikrishna Khare rbi->skb = new_skb; 147650a5ce3eSShrikrishna Khare rbi->dma_addr = new_dma_addr; 147750a5ce3eSShrikrishna Khare rxd->addr = cpu_to_le64(rbi->dma_addr); 147850a5ce3eSShrikrishna Khare rxd->len = rbi->len; 147950a5ce3eSShrikrishna Khare } 148050a5ce3eSShrikrishna Khare 14817db11f75SStephen Hemminger #ifdef VMXNET3_RSS 14827db11f75SStephen Hemminger if (rcd->rssType != VMXNET3_RCD_RSS_TYPE_NONE && 1483b3973bb4SRonak Doshi (adapter->netdev->features & NETIF_F_RXHASH)) { 1484b3973bb4SRonak Doshi enum pkt_hash_types hash_type; 1485b3973bb4SRonak Doshi 1486b3973bb4SRonak Doshi switch (rcd->rssType) { 1487b3973bb4SRonak Doshi case VMXNET3_RCD_RSS_TYPE_IPV4: 1488b3973bb4SRonak Doshi case VMXNET3_RCD_RSS_TYPE_IPV6: 1489b3973bb4SRonak Doshi hash_type = PKT_HASH_TYPE_L3; 1490b3973bb4SRonak Doshi break; 1491b3973bb4SRonak Doshi case VMXNET3_RCD_RSS_TYPE_TCPIPV4: 1492b3973bb4SRonak Doshi case VMXNET3_RCD_RSS_TYPE_TCPIPV6: 1493b3973bb4SRonak Doshi case VMXNET3_RCD_RSS_TYPE_UDPIPV4: 1494b3973bb4SRonak Doshi case VMXNET3_RCD_RSS_TYPE_UDPIPV6: 1495b3973bb4SRonak Doshi hash_type = PKT_HASH_TYPE_L4; 1496b3973bb4SRonak Doshi break; 1497b3973bb4SRonak Doshi default: 1498b3973bb4SRonak Doshi hash_type = PKT_HASH_TYPE_L3; 1499b3973bb4SRonak Doshi break; 1500b3973bb4SRonak Doshi } 15012c15a154SMichal Schmidt skb_set_hash(ctx->skb, 15022c15a154SMichal Schmidt le32_to_cpu(rcd->rssHash), 1503b3973bb4SRonak Doshi hash_type); 1504b3973bb4SRonak Doshi } 15057db11f75SStephen Hemminger #endif 1506d1a890faSShreyas Bhatewara skb_put(ctx->skb, rcd->len); 15075318d809SShreyas Bhatewara 1508190af10fSShrikrishna Khare if (VMXNET3_VERSION_GE_2(adapter) && 150945dac1d6SShreyas Bhatewara rcd->type == VMXNET3_CDTYPE_RXCOMP_LRO) { 151045dac1d6SShreyas Bhatewara struct Vmxnet3_RxCompDescExt *rcdlro; 151145dac1d6SShreyas Bhatewara rcdlro = (struct Vmxnet3_RxCompDescExt *)rcd; 15125318d809SShreyas Bhatewara 151345dac1d6SShreyas Bhatewara segCnt = rcdlro->segCnt; 151450219538SShrikrishna Khare WARN_ON_ONCE(segCnt == 0); 151545dac1d6SShreyas Bhatewara mss = rcdlro->mss; 151645dac1d6SShreyas Bhatewara if (unlikely(segCnt <= 1)) 151745dac1d6SShreyas Bhatewara segCnt = 0; 151845dac1d6SShreyas Bhatewara } else { 151945dac1d6SShreyas Bhatewara segCnt = 0; 152045dac1d6SShreyas Bhatewara } 1521d1a890faSShreyas Bhatewara } else { 15225318d809SShreyas Bhatewara BUG_ON(ctx->skb == NULL && !skip_page_frags); 15235318d809SShreyas Bhatewara 1524d1a890faSShreyas Bhatewara /* non SOP buffer must be type 1 in most cases */ 15255318d809SShreyas Bhatewara BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE); 1526d1a890faSShreyas Bhatewara BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY); 1527d1a890faSShreyas Bhatewara 15285318d809SShreyas Bhatewara /* If an sop buffer was dropped, skip all 15295318d809SShreyas Bhatewara * following non-sop fragments. They will be reused. 15305318d809SShreyas Bhatewara */ 15315318d809SShreyas Bhatewara if (skip_page_frags) 15325318d809SShreyas Bhatewara goto rcd_done; 15335318d809SShreyas Bhatewara 1534c41fcce9SShreyas Bhatewara if (rcd->len) { 15355318d809SShreyas Bhatewara new_page = alloc_page(GFP_ATOMIC); 15365318d809SShreyas Bhatewara /* Replacement page frag could not be allocated. 15375318d809SShreyas Bhatewara * Reuse this page. Drop the pkt and free the 15385318d809SShreyas Bhatewara * skb which contained this page as a frag. Skip 15395318d809SShreyas Bhatewara * processing all the following non-sop frags. 15405318d809SShreyas Bhatewara */ 1541c41fcce9SShreyas Bhatewara if (unlikely(!new_page)) { 15425318d809SShreyas Bhatewara rq->stats.rx_buf_alloc_failure++; 15435318d809SShreyas Bhatewara dev_kfree_skb(ctx->skb); 15445318d809SShreyas Bhatewara ctx->skb = NULL; 15455318d809SShreyas Bhatewara skip_page_frags = true; 15465318d809SShreyas Bhatewara goto rcd_done; 15475318d809SShreyas Bhatewara } 154858caf637SShrikrishna Khare new_dma_addr = dma_map_page(&adapter->pdev->dev, 154958caf637SShrikrishna Khare new_page, 15505738a09dSAlexey Khoroshilov 0, PAGE_SIZE, 1551bf7bec46SChristophe JAILLET DMA_FROM_DEVICE); 15525738a09dSAlexey Khoroshilov if (dma_mapping_error(&adapter->pdev->dev, 15535738a09dSAlexey Khoroshilov new_dma_addr)) { 15545738a09dSAlexey Khoroshilov put_page(new_page); 15555738a09dSAlexey Khoroshilov rq->stats.rx_buf_alloc_failure++; 15565738a09dSAlexey Khoroshilov dev_kfree_skb(ctx->skb); 15575738a09dSAlexey Khoroshilov ctx->skb = NULL; 15585738a09dSAlexey Khoroshilov skip_page_frags = true; 15595738a09dSAlexey Khoroshilov goto rcd_done; 15605738a09dSAlexey Khoroshilov } 15615318d809SShreyas Bhatewara 1562b0eb57cbSAndy King dma_unmap_page(&adapter->pdev->dev, 1563d1a890faSShreyas Bhatewara rbi->dma_addr, rbi->len, 1564bf7bec46SChristophe JAILLET DMA_FROM_DEVICE); 1565d1a890faSShreyas Bhatewara 1566d1a890faSShreyas Bhatewara vmxnet3_append_frag(ctx->skb, rcd, rbi); 15675318d809SShreyas Bhatewara 15685318d809SShreyas Bhatewara /* Immediate refill */ 15695318d809SShreyas Bhatewara rbi->page = new_page; 15705738a09dSAlexey Khoroshilov rbi->dma_addr = new_dma_addr; 15715318d809SShreyas Bhatewara rxd->addr = cpu_to_le64(rbi->dma_addr); 15725318d809SShreyas Bhatewara rxd->len = rbi->len; 1573d1a890faSShreyas Bhatewara } 1574c41fcce9SShreyas Bhatewara } 15755318d809SShreyas Bhatewara 1576d1a890faSShreyas Bhatewara 1577d1a890faSShreyas Bhatewara skb = ctx->skb; 1578d1a890faSShreyas Bhatewara if (rcd->eop) { 157945dac1d6SShreyas Bhatewara u32 mtu = adapter->netdev->mtu; 1580d1a890faSShreyas Bhatewara skb->len += skb->data_len; 1581d1a890faSShreyas Bhatewara 1582d1a890faSShreyas Bhatewara vmxnet3_rx_csum(adapter, skb, 1583d1a890faSShreyas Bhatewara (union Vmxnet3_GenericDesc *)rcd); 1584d1a890faSShreyas Bhatewara skb->protocol = eth_type_trans(skb, adapter->netdev); 1585034f4057SRonak Doshi if (!rcd->tcp || 1586034f4057SRonak Doshi !(adapter->netdev->features & NETIF_F_LRO)) 158745dac1d6SShreyas Bhatewara goto not_lro; 1588d1a890faSShreyas Bhatewara 158945dac1d6SShreyas Bhatewara if (segCnt != 0 && mss != 0) { 159045dac1d6SShreyas Bhatewara skb_shinfo(skb)->gso_type = rcd->v4 ? 159145dac1d6SShreyas Bhatewara SKB_GSO_TCPV4 : SKB_GSO_TCPV6; 159245dac1d6SShreyas Bhatewara skb_shinfo(skb)->gso_size = mss; 159345dac1d6SShreyas Bhatewara skb_shinfo(skb)->gso_segs = segCnt; 159445dac1d6SShreyas Bhatewara } else if (segCnt != 0 || skb->len > mtu) { 159545dac1d6SShreyas Bhatewara u32 hlen; 159645dac1d6SShreyas Bhatewara 159745dac1d6SShreyas Bhatewara hlen = vmxnet3_get_hdr_len(adapter, skb, 159845dac1d6SShreyas Bhatewara (union Vmxnet3_GenericDesc *)rcd); 159945dac1d6SShreyas Bhatewara if (hlen == 0) 160045dac1d6SShreyas Bhatewara goto not_lro; 160145dac1d6SShreyas Bhatewara 160245dac1d6SShreyas Bhatewara skb_shinfo(skb)->gso_type = 160345dac1d6SShreyas Bhatewara rcd->v4 ? SKB_GSO_TCPV4 : SKB_GSO_TCPV6; 160445dac1d6SShreyas Bhatewara if (segCnt != 0) { 160545dac1d6SShreyas Bhatewara skb_shinfo(skb)->gso_segs = segCnt; 160645dac1d6SShreyas Bhatewara skb_shinfo(skb)->gso_size = 160745dac1d6SShreyas Bhatewara DIV_ROUND_UP(skb->len - 160845dac1d6SShreyas Bhatewara hlen, segCnt); 160945dac1d6SShreyas Bhatewara } else { 161045dac1d6SShreyas Bhatewara skb_shinfo(skb)->gso_size = mtu - hlen; 161145dac1d6SShreyas Bhatewara } 161245dac1d6SShreyas Bhatewara } 161345dac1d6SShreyas Bhatewara not_lro: 161472e85c45SJesse Gross if (unlikely(rcd->ts)) 161586a9bad3SPatrick McHardy __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rcd->tci); 161672e85c45SJesse Gross 1617213ade8cSJesse Gross if (adapter->netdev->features & NETIF_F_LRO) 1618d1a890faSShreyas Bhatewara netif_receive_skb(skb); 1619213ade8cSJesse Gross else 1620213ade8cSJesse Gross napi_gro_receive(&rq->napi, skb); 1621d1a890faSShreyas Bhatewara 1622d1a890faSShreyas Bhatewara ctx->skb = NULL; 16230769636cSNeil Horman num_pkts++; 1624d1a890faSShreyas Bhatewara } 1625d1a890faSShreyas Bhatewara 1626d1a890faSShreyas Bhatewara rcd_done: 16275318d809SShreyas Bhatewara /* device may have skipped some rx descs */ 16285318d809SShreyas Bhatewara ring->next2comp = idx; 16295318d809SShreyas Bhatewara num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring); 16305318d809SShreyas Bhatewara ring = rq->rx_ring + ring_idx; 1631f3002c13Shpreg@vmware.com 1632f3002c13Shpreg@vmware.com /* Ensure that the writes to rxd->gen bits will be observed 1633f3002c13Shpreg@vmware.com * after all other writes to rxd objects. 1634f3002c13Shpreg@vmware.com */ 1635f3002c13Shpreg@vmware.com dma_wmb(); 1636f3002c13Shpreg@vmware.com 16375318d809SShreyas Bhatewara while (num_to_alloc) { 16385318d809SShreyas Bhatewara vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd, 16395318d809SShreyas Bhatewara &rxCmdDesc); 16405318d809SShreyas Bhatewara BUG_ON(!rxd->addr); 1641d1a890faSShreyas Bhatewara 16425318d809SShreyas Bhatewara /* Recv desc is ready to be used by the device */ 16435318d809SShreyas Bhatewara rxd->gen = ring->gen; 16445318d809SShreyas Bhatewara vmxnet3_cmd_ring_adv_next2fill(ring); 16455318d809SShreyas Bhatewara num_to_alloc--; 16465318d809SShreyas Bhatewara } 1647d1a890faSShreyas Bhatewara 1648d1a890faSShreyas Bhatewara /* if needed, update the register */ 1649d1a890faSShreyas Bhatewara if (unlikely(rq->shared->updateRxProd)) { 1650d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR0_REG(adapter, 1651d1a890faSShreyas Bhatewara rxprod_reg[ring_idx] + rq->qid * 8, 16525318d809SShreyas Bhatewara ring->next2fill); 1653d1a890faSShreyas Bhatewara } 1654d1a890faSShreyas Bhatewara 1655d1a890faSShreyas Bhatewara vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring); 1656115924b6SShreyas Bhatewara vmxnet3_getRxComp(rcd, 1657115924b6SShreyas Bhatewara &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp); 1658d1a890faSShreyas Bhatewara } 1659d1a890faSShreyas Bhatewara 16600769636cSNeil Horman return num_pkts; 1661d1a890faSShreyas Bhatewara } 1662d1a890faSShreyas Bhatewara 1663d1a890faSShreyas Bhatewara 1664d1a890faSShreyas Bhatewara static void 1665d1a890faSShreyas Bhatewara vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq, 1666d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 1667d1a890faSShreyas Bhatewara { 1668d1a890faSShreyas Bhatewara u32 i, ring_idx; 1669d1a890faSShreyas Bhatewara struct Vmxnet3_RxDesc *rxd; 1670d1a890faSShreyas Bhatewara 1671*edf410cbSZixuan Fu /* ring has already been cleaned up */ 1672*edf410cbSZixuan Fu if (!rq->rx_ring[0].base) 1673*edf410cbSZixuan Fu return; 1674*edf410cbSZixuan Fu 1675d1a890faSShreyas Bhatewara for (ring_idx = 0; ring_idx < 2; ring_idx++) { 1676d1a890faSShreyas Bhatewara for (i = 0; i < rq->rx_ring[ring_idx].size; i++) { 1677115924b6SShreyas Bhatewara #ifdef __BIG_ENDIAN_BITFIELD 1678115924b6SShreyas Bhatewara struct Vmxnet3_RxDesc rxDesc; 1679115924b6SShreyas Bhatewara #endif 1680115924b6SShreyas Bhatewara vmxnet3_getRxDesc(rxd, 1681115924b6SShreyas Bhatewara &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc); 1682d1a890faSShreyas Bhatewara 1683d1a890faSShreyas Bhatewara if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD && 1684d1a890faSShreyas Bhatewara rq->buf_info[ring_idx][i].skb) { 1685b0eb57cbSAndy King dma_unmap_single(&adapter->pdev->dev, rxd->addr, 1686bf7bec46SChristophe JAILLET rxd->len, DMA_FROM_DEVICE); 1687d1a890faSShreyas Bhatewara dev_kfree_skb(rq->buf_info[ring_idx][i].skb); 1688d1a890faSShreyas Bhatewara rq->buf_info[ring_idx][i].skb = NULL; 1689d1a890faSShreyas Bhatewara } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY && 1690d1a890faSShreyas Bhatewara rq->buf_info[ring_idx][i].page) { 1691b0eb57cbSAndy King dma_unmap_page(&adapter->pdev->dev, rxd->addr, 1692bf7bec46SChristophe JAILLET rxd->len, DMA_FROM_DEVICE); 1693d1a890faSShreyas Bhatewara put_page(rq->buf_info[ring_idx][i].page); 1694d1a890faSShreyas Bhatewara rq->buf_info[ring_idx][i].page = NULL; 1695d1a890faSShreyas Bhatewara } 1696d1a890faSShreyas Bhatewara } 1697d1a890faSShreyas Bhatewara 1698d1a890faSShreyas Bhatewara rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN; 1699d1a890faSShreyas Bhatewara rq->rx_ring[ring_idx].next2fill = 1700d1a890faSShreyas Bhatewara rq->rx_ring[ring_idx].next2comp = 0; 1701d1a890faSShreyas Bhatewara } 1702d1a890faSShreyas Bhatewara 1703d1a890faSShreyas Bhatewara rq->comp_ring.gen = VMXNET3_INIT_GEN; 1704d1a890faSShreyas Bhatewara rq->comp_ring.next2proc = 0; 1705d1a890faSShreyas Bhatewara } 1706d1a890faSShreyas Bhatewara 1707d1a890faSShreyas Bhatewara 170809c5088eSShreyas Bhatewara static void 170909c5088eSShreyas Bhatewara vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter) 171009c5088eSShreyas Bhatewara { 171109c5088eSShreyas Bhatewara int i; 171209c5088eSShreyas Bhatewara 171309c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) 171409c5088eSShreyas Bhatewara vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter); 171509c5088eSShreyas Bhatewara } 171609c5088eSShreyas Bhatewara 171709c5088eSShreyas Bhatewara 1718280b74f7Sstephen hemminger static void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq, 1719d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 1720d1a890faSShreyas Bhatewara { 1721d1a890faSShreyas Bhatewara int i; 1722d1a890faSShreyas Bhatewara int j; 1723d1a890faSShreyas Bhatewara 1724d1a890faSShreyas Bhatewara /* all rx buffers must have already been freed */ 1725d1a890faSShreyas Bhatewara for (i = 0; i < 2; i++) { 1726d1a890faSShreyas Bhatewara if (rq->buf_info[i]) { 1727d1a890faSShreyas Bhatewara for (j = 0; j < rq->rx_ring[i].size; j++) 1728d1a890faSShreyas Bhatewara BUG_ON(rq->buf_info[i][j].page != NULL); 1729d1a890faSShreyas Bhatewara } 1730d1a890faSShreyas Bhatewara } 1731d1a890faSShreyas Bhatewara 1732d1a890faSShreyas Bhatewara 1733d1a890faSShreyas Bhatewara for (i = 0; i < 2; i++) { 1734d1a890faSShreyas Bhatewara if (rq->rx_ring[i].base) { 1735b0eb57cbSAndy King dma_free_coherent(&adapter->pdev->dev, 1736b0eb57cbSAndy King rq->rx_ring[i].size 1737d1a890faSShreyas Bhatewara * sizeof(struct Vmxnet3_RxDesc), 1738d1a890faSShreyas Bhatewara rq->rx_ring[i].base, 1739d1a890faSShreyas Bhatewara rq->rx_ring[i].basePA); 1740d1a890faSShreyas Bhatewara rq->rx_ring[i].base = NULL; 1741d1a890faSShreyas Bhatewara } 1742d1a890faSShreyas Bhatewara } 1743d1a890faSShreyas Bhatewara 174450a5ce3eSShrikrishna Khare if (rq->data_ring.base) { 174550a5ce3eSShrikrishna Khare dma_free_coherent(&adapter->pdev->dev, 174650a5ce3eSShrikrishna Khare rq->rx_ring[0].size * rq->data_ring.desc_size, 174750a5ce3eSShrikrishna Khare rq->data_ring.base, rq->data_ring.basePA); 174850a5ce3eSShrikrishna Khare rq->data_ring.base = NULL; 174950a5ce3eSShrikrishna Khare } 175050a5ce3eSShrikrishna Khare 1751d1a890faSShreyas Bhatewara if (rq->comp_ring.base) { 1752b0eb57cbSAndy King dma_free_coherent(&adapter->pdev->dev, rq->comp_ring.size 1753b0eb57cbSAndy King * sizeof(struct Vmxnet3_RxCompDesc), 1754d1a890faSShreyas Bhatewara rq->comp_ring.base, rq->comp_ring.basePA); 1755d1a890faSShreyas Bhatewara rq->comp_ring.base = NULL; 1756d1a890faSShreyas Bhatewara } 1757b0eb57cbSAndy King 1758de1da8bcSRonak Doshi kfree(rq->buf_info[0]); 1759de1da8bcSRonak Doshi rq->buf_info[0] = NULL; 1760de1da8bcSRonak Doshi rq->buf_info[1] = NULL; 1761d1a890faSShreyas Bhatewara } 1762d1a890faSShreyas Bhatewara 1763bb40aca7SWei Yongjun static void 176450a5ce3eSShrikrishna Khare vmxnet3_rq_destroy_all_rxdataring(struct vmxnet3_adapter *adapter) 176550a5ce3eSShrikrishna Khare { 176650a5ce3eSShrikrishna Khare int i; 176750a5ce3eSShrikrishna Khare 176850a5ce3eSShrikrishna Khare for (i = 0; i < adapter->num_rx_queues; i++) { 176950a5ce3eSShrikrishna Khare struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 177050a5ce3eSShrikrishna Khare 177150a5ce3eSShrikrishna Khare if (rq->data_ring.base) { 177250a5ce3eSShrikrishna Khare dma_free_coherent(&adapter->pdev->dev, 177350a5ce3eSShrikrishna Khare (rq->rx_ring[0].size * 177450a5ce3eSShrikrishna Khare rq->data_ring.desc_size), 177550a5ce3eSShrikrishna Khare rq->data_ring.base, 177650a5ce3eSShrikrishna Khare rq->data_ring.basePA); 177750a5ce3eSShrikrishna Khare rq->data_ring.base = NULL; 177850a5ce3eSShrikrishna Khare rq->data_ring.desc_size = 0; 177950a5ce3eSShrikrishna Khare } 178050a5ce3eSShrikrishna Khare } 178150a5ce3eSShrikrishna Khare } 1782d1a890faSShreyas Bhatewara 1783d1a890faSShreyas Bhatewara static int 1784d1a890faSShreyas Bhatewara vmxnet3_rq_init(struct vmxnet3_rx_queue *rq, 1785d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter) 1786d1a890faSShreyas Bhatewara { 1787d1a890faSShreyas Bhatewara int i; 1788d1a890faSShreyas Bhatewara 1789d1a890faSShreyas Bhatewara /* initialize buf_info */ 1790d1a890faSShreyas Bhatewara for (i = 0; i < rq->rx_ring[0].size; i++) { 1791d1a890faSShreyas Bhatewara 1792d1a890faSShreyas Bhatewara /* 1st buf for a pkt is skbuff */ 1793d1a890faSShreyas Bhatewara if (i % adapter->rx_buf_per_pkt == 0) { 1794d1a890faSShreyas Bhatewara rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB; 1795d1a890faSShreyas Bhatewara rq->buf_info[0][i].len = adapter->skb_buf_size; 1796d1a890faSShreyas Bhatewara } else { /* subsequent bufs for a pkt is frag */ 1797d1a890faSShreyas Bhatewara rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE; 1798d1a890faSShreyas Bhatewara rq->buf_info[0][i].len = PAGE_SIZE; 1799d1a890faSShreyas Bhatewara } 1800d1a890faSShreyas Bhatewara } 1801d1a890faSShreyas Bhatewara for (i = 0; i < rq->rx_ring[1].size; i++) { 1802d1a890faSShreyas Bhatewara rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE; 1803d1a890faSShreyas Bhatewara rq->buf_info[1][i].len = PAGE_SIZE; 1804d1a890faSShreyas Bhatewara } 1805d1a890faSShreyas Bhatewara 1806d1a890faSShreyas Bhatewara /* reset internal state and allocate buffers for both rings */ 1807d1a890faSShreyas Bhatewara for (i = 0; i < 2; i++) { 1808d1a890faSShreyas Bhatewara rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0; 1809d1a890faSShreyas Bhatewara 1810d1a890faSShreyas Bhatewara memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size * 1811d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_RxDesc)); 1812d1a890faSShreyas Bhatewara rq->rx_ring[i].gen = VMXNET3_INIT_GEN; 1813d1a890faSShreyas Bhatewara } 1814d1a890faSShreyas Bhatewara if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1, 1815d1a890faSShreyas Bhatewara adapter) == 0) { 1816d1a890faSShreyas Bhatewara /* at least has 1 rx buffer for the 1st ring */ 1817d1a890faSShreyas Bhatewara return -ENOMEM; 1818d1a890faSShreyas Bhatewara } 1819d1a890faSShreyas Bhatewara vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter); 1820d1a890faSShreyas Bhatewara 1821d1a890faSShreyas Bhatewara /* reset the comp ring */ 1822d1a890faSShreyas Bhatewara rq->comp_ring.next2proc = 0; 1823d1a890faSShreyas Bhatewara memset(rq->comp_ring.base, 0, rq->comp_ring.size * 1824d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_RxCompDesc)); 1825d1a890faSShreyas Bhatewara rq->comp_ring.gen = VMXNET3_INIT_GEN; 1826d1a890faSShreyas Bhatewara 1827d1a890faSShreyas Bhatewara /* reset rxctx */ 1828d1a890faSShreyas Bhatewara rq->rx_ctx.skb = NULL; 1829d1a890faSShreyas Bhatewara 1830d1a890faSShreyas Bhatewara /* stats are not reset */ 1831d1a890faSShreyas Bhatewara return 0; 1832d1a890faSShreyas Bhatewara } 1833d1a890faSShreyas Bhatewara 1834d1a890faSShreyas Bhatewara 1835d1a890faSShreyas Bhatewara static int 183609c5088eSShreyas Bhatewara vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter) 183709c5088eSShreyas Bhatewara { 183809c5088eSShreyas Bhatewara int i, err = 0; 183909c5088eSShreyas Bhatewara 184009c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 184109c5088eSShreyas Bhatewara err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter); 184209c5088eSShreyas Bhatewara if (unlikely(err)) { 184309c5088eSShreyas Bhatewara dev_err(&adapter->netdev->dev, "%s: failed to " 184409c5088eSShreyas Bhatewara "initialize rx queue%i\n", 184509c5088eSShreyas Bhatewara adapter->netdev->name, i); 184609c5088eSShreyas Bhatewara break; 184709c5088eSShreyas Bhatewara } 184809c5088eSShreyas Bhatewara } 184909c5088eSShreyas Bhatewara return err; 185009c5088eSShreyas Bhatewara 185109c5088eSShreyas Bhatewara } 185209c5088eSShreyas Bhatewara 185309c5088eSShreyas Bhatewara 185409c5088eSShreyas Bhatewara static int 1855d1a890faSShreyas Bhatewara vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter) 1856d1a890faSShreyas Bhatewara { 1857d1a890faSShreyas Bhatewara int i; 1858d1a890faSShreyas Bhatewara size_t sz; 1859d1a890faSShreyas Bhatewara struct vmxnet3_rx_buf_info *bi; 1860d1a890faSShreyas Bhatewara 1861d1a890faSShreyas Bhatewara for (i = 0; i < 2; i++) { 1862d1a890faSShreyas Bhatewara 1863d1a890faSShreyas Bhatewara sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc); 1864b0eb57cbSAndy King rq->rx_ring[i].base = dma_alloc_coherent( 1865b0eb57cbSAndy King &adapter->pdev->dev, sz, 1866b0eb57cbSAndy King &rq->rx_ring[i].basePA, 1867b0eb57cbSAndy King GFP_KERNEL); 1868d1a890faSShreyas Bhatewara if (!rq->rx_ring[i].base) { 1869204a6e65SStephen Hemminger netdev_err(adapter->netdev, 1870204a6e65SStephen Hemminger "failed to allocate rx ring %d\n", i); 1871d1a890faSShreyas Bhatewara goto err; 1872d1a890faSShreyas Bhatewara } 1873d1a890faSShreyas Bhatewara } 1874d1a890faSShreyas Bhatewara 187550a5ce3eSShrikrishna Khare if ((adapter->rxdataring_enabled) && (rq->data_ring.desc_size != 0)) { 187650a5ce3eSShrikrishna Khare sz = rq->rx_ring[0].size * rq->data_ring.desc_size; 187750a5ce3eSShrikrishna Khare rq->data_ring.base = 187850a5ce3eSShrikrishna Khare dma_alloc_coherent(&adapter->pdev->dev, sz, 187950a5ce3eSShrikrishna Khare &rq->data_ring.basePA, 188050a5ce3eSShrikrishna Khare GFP_KERNEL); 188150a5ce3eSShrikrishna Khare if (!rq->data_ring.base) { 188250a5ce3eSShrikrishna Khare netdev_err(adapter->netdev, 188350a5ce3eSShrikrishna Khare "rx data ring will be disabled\n"); 188450a5ce3eSShrikrishna Khare adapter->rxdataring_enabled = false; 188550a5ce3eSShrikrishna Khare } 188650a5ce3eSShrikrishna Khare } else { 188750a5ce3eSShrikrishna Khare rq->data_ring.base = NULL; 188850a5ce3eSShrikrishna Khare rq->data_ring.desc_size = 0; 188950a5ce3eSShrikrishna Khare } 189050a5ce3eSShrikrishna Khare 1891d1a890faSShreyas Bhatewara sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc); 1892b0eb57cbSAndy King rq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, sz, 1893b0eb57cbSAndy King &rq->comp_ring.basePA, 1894b0eb57cbSAndy King GFP_KERNEL); 1895d1a890faSShreyas Bhatewara if (!rq->comp_ring.base) { 1896204a6e65SStephen Hemminger netdev_err(adapter->netdev, "failed to allocate rx comp ring\n"); 1897d1a890faSShreyas Bhatewara goto err; 1898d1a890faSShreyas Bhatewara } 1899d1a890faSShreyas Bhatewara 1900de1da8bcSRonak Doshi bi = kcalloc_node(rq->rx_ring[0].size + rq->rx_ring[1].size, 1901de1da8bcSRonak Doshi sizeof(rq->buf_info[0][0]), GFP_KERNEL, 1902de1da8bcSRonak Doshi dev_to_node(&adapter->pdev->dev)); 1903e404decbSJoe Perches if (!bi) 1904d1a890faSShreyas Bhatewara goto err; 1905e404decbSJoe Perches 1906d1a890faSShreyas Bhatewara rq->buf_info[0] = bi; 1907d1a890faSShreyas Bhatewara rq->buf_info[1] = bi + rq->rx_ring[0].size; 1908d1a890faSShreyas Bhatewara 1909d1a890faSShreyas Bhatewara return 0; 1910d1a890faSShreyas Bhatewara 1911d1a890faSShreyas Bhatewara err: 1912d1a890faSShreyas Bhatewara vmxnet3_rq_destroy(rq, adapter); 1913d1a890faSShreyas Bhatewara return -ENOMEM; 1914d1a890faSShreyas Bhatewara } 1915d1a890faSShreyas Bhatewara 1916d1a890faSShreyas Bhatewara 1917d1a890faSShreyas Bhatewara static int 191809c5088eSShreyas Bhatewara vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter) 191909c5088eSShreyas Bhatewara { 192009c5088eSShreyas Bhatewara int i, err = 0; 192109c5088eSShreyas Bhatewara 192250a5ce3eSShrikrishna Khare adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter); 192350a5ce3eSShrikrishna Khare 192409c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 192509c5088eSShreyas Bhatewara err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter); 192609c5088eSShreyas Bhatewara if (unlikely(err)) { 192709c5088eSShreyas Bhatewara dev_err(&adapter->netdev->dev, 192809c5088eSShreyas Bhatewara "%s: failed to create rx queue%i\n", 192909c5088eSShreyas Bhatewara adapter->netdev->name, i); 193009c5088eSShreyas Bhatewara goto err_out; 193109c5088eSShreyas Bhatewara } 193209c5088eSShreyas Bhatewara } 193350a5ce3eSShrikrishna Khare 193450a5ce3eSShrikrishna Khare if (!adapter->rxdataring_enabled) 193550a5ce3eSShrikrishna Khare vmxnet3_rq_destroy_all_rxdataring(adapter); 193650a5ce3eSShrikrishna Khare 193709c5088eSShreyas Bhatewara return err; 193809c5088eSShreyas Bhatewara err_out: 193909c5088eSShreyas Bhatewara vmxnet3_rq_destroy_all(adapter); 194009c5088eSShreyas Bhatewara return err; 194109c5088eSShreyas Bhatewara 194209c5088eSShreyas Bhatewara } 194309c5088eSShreyas Bhatewara 194409c5088eSShreyas Bhatewara /* Multiple queue aware polling function for tx and rx */ 194509c5088eSShreyas Bhatewara 194609c5088eSShreyas Bhatewara static int 1947d1a890faSShreyas Bhatewara vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget) 1948d1a890faSShreyas Bhatewara { 194909c5088eSShreyas Bhatewara int rcd_done = 0, i; 1950d1a890faSShreyas Bhatewara if (unlikely(adapter->shared->ecr)) 1951d1a890faSShreyas Bhatewara vmxnet3_process_events(adapter); 195209c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) 195309c5088eSShreyas Bhatewara vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter); 1954d1a890faSShreyas Bhatewara 195509c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) 195609c5088eSShreyas Bhatewara rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i], 195709c5088eSShreyas Bhatewara adapter, budget); 195809c5088eSShreyas Bhatewara return rcd_done; 1959d1a890faSShreyas Bhatewara } 1960d1a890faSShreyas Bhatewara 1961d1a890faSShreyas Bhatewara 1962d1a890faSShreyas Bhatewara static int 1963d1a890faSShreyas Bhatewara vmxnet3_poll(struct napi_struct *napi, int budget) 1964d1a890faSShreyas Bhatewara { 196509c5088eSShreyas Bhatewara struct vmxnet3_rx_queue *rx_queue = container_of(napi, 196609c5088eSShreyas Bhatewara struct vmxnet3_rx_queue, napi); 1967d1a890faSShreyas Bhatewara int rxd_done; 1968d1a890faSShreyas Bhatewara 196909c5088eSShreyas Bhatewara rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget); 1970d1a890faSShreyas Bhatewara 1971d1a890faSShreyas Bhatewara if (rxd_done < budget) { 19726ad20165SEric Dumazet napi_complete_done(napi, rxd_done); 197309c5088eSShreyas Bhatewara vmxnet3_enable_all_intrs(rx_queue->adapter); 1974d1a890faSShreyas Bhatewara } 1975d1a890faSShreyas Bhatewara return rxd_done; 1976d1a890faSShreyas Bhatewara } 1977d1a890faSShreyas Bhatewara 197809c5088eSShreyas Bhatewara /* 197909c5088eSShreyas Bhatewara * NAPI polling function for MSI-X mode with multiple Rx queues 198009c5088eSShreyas Bhatewara * Returns the # of the NAPI credit consumed (# of rx descriptors processed) 198109c5088eSShreyas Bhatewara */ 198209c5088eSShreyas Bhatewara 198309c5088eSShreyas Bhatewara static int 198409c5088eSShreyas Bhatewara vmxnet3_poll_rx_only(struct napi_struct *napi, int budget) 198509c5088eSShreyas Bhatewara { 198609c5088eSShreyas Bhatewara struct vmxnet3_rx_queue *rq = container_of(napi, 198709c5088eSShreyas Bhatewara struct vmxnet3_rx_queue, napi); 198809c5088eSShreyas Bhatewara struct vmxnet3_adapter *adapter = rq->adapter; 198909c5088eSShreyas Bhatewara int rxd_done; 199009c5088eSShreyas Bhatewara 199109c5088eSShreyas Bhatewara /* When sharing interrupt with corresponding tx queue, process 199209c5088eSShreyas Bhatewara * tx completions in that queue as well 199309c5088eSShreyas Bhatewara */ 199409c5088eSShreyas Bhatewara if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) { 199509c5088eSShreyas Bhatewara struct vmxnet3_tx_queue *tq = 199609c5088eSShreyas Bhatewara &adapter->tx_queue[rq - adapter->rx_queue]; 199709c5088eSShreyas Bhatewara vmxnet3_tq_tx_complete(tq, adapter); 199809c5088eSShreyas Bhatewara } 199909c5088eSShreyas Bhatewara 200009c5088eSShreyas Bhatewara rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget); 200109c5088eSShreyas Bhatewara 200209c5088eSShreyas Bhatewara if (rxd_done < budget) { 20036ad20165SEric Dumazet napi_complete_done(napi, rxd_done); 200409c5088eSShreyas Bhatewara vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx); 200509c5088eSShreyas Bhatewara } 200609c5088eSShreyas Bhatewara return rxd_done; 200709c5088eSShreyas Bhatewara } 200809c5088eSShreyas Bhatewara 200909c5088eSShreyas Bhatewara 201009c5088eSShreyas Bhatewara #ifdef CONFIG_PCI_MSI 201109c5088eSShreyas Bhatewara 201209c5088eSShreyas Bhatewara /* 201309c5088eSShreyas Bhatewara * Handle completion interrupts on tx queues 201409c5088eSShreyas Bhatewara * Returns whether or not the intr is handled 201509c5088eSShreyas Bhatewara */ 201609c5088eSShreyas Bhatewara 201709c5088eSShreyas Bhatewara static irqreturn_t 201809c5088eSShreyas Bhatewara vmxnet3_msix_tx(int irq, void *data) 201909c5088eSShreyas Bhatewara { 202009c5088eSShreyas Bhatewara struct vmxnet3_tx_queue *tq = data; 202109c5088eSShreyas Bhatewara struct vmxnet3_adapter *adapter = tq->adapter; 202209c5088eSShreyas Bhatewara 202309c5088eSShreyas Bhatewara if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 202409c5088eSShreyas Bhatewara vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx); 202509c5088eSShreyas Bhatewara 202609c5088eSShreyas Bhatewara /* Handle the case where only one irq is allocate for all tx queues */ 202709c5088eSShreyas Bhatewara if (adapter->share_intr == VMXNET3_INTR_TXSHARE) { 202809c5088eSShreyas Bhatewara int i; 202909c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) { 203009c5088eSShreyas Bhatewara struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i]; 203109c5088eSShreyas Bhatewara vmxnet3_tq_tx_complete(txq, adapter); 203209c5088eSShreyas Bhatewara } 203309c5088eSShreyas Bhatewara } else { 203409c5088eSShreyas Bhatewara vmxnet3_tq_tx_complete(tq, adapter); 203509c5088eSShreyas Bhatewara } 203609c5088eSShreyas Bhatewara vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx); 203709c5088eSShreyas Bhatewara 203809c5088eSShreyas Bhatewara return IRQ_HANDLED; 203909c5088eSShreyas Bhatewara } 204009c5088eSShreyas Bhatewara 204109c5088eSShreyas Bhatewara 204209c5088eSShreyas Bhatewara /* 204309c5088eSShreyas Bhatewara * Handle completion interrupts on rx queues. Returns whether or not the 204409c5088eSShreyas Bhatewara * intr is handled 204509c5088eSShreyas Bhatewara */ 204609c5088eSShreyas Bhatewara 204709c5088eSShreyas Bhatewara static irqreturn_t 204809c5088eSShreyas Bhatewara vmxnet3_msix_rx(int irq, void *data) 204909c5088eSShreyas Bhatewara { 205009c5088eSShreyas Bhatewara struct vmxnet3_rx_queue *rq = data; 205109c5088eSShreyas Bhatewara struct vmxnet3_adapter *adapter = rq->adapter; 205209c5088eSShreyas Bhatewara 205309c5088eSShreyas Bhatewara /* disable intr if needed */ 205409c5088eSShreyas Bhatewara if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 205509c5088eSShreyas Bhatewara vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx); 205609c5088eSShreyas Bhatewara napi_schedule(&rq->napi); 205709c5088eSShreyas Bhatewara 205809c5088eSShreyas Bhatewara return IRQ_HANDLED; 205909c5088eSShreyas Bhatewara } 206009c5088eSShreyas Bhatewara 206109c5088eSShreyas Bhatewara /* 206209c5088eSShreyas Bhatewara *---------------------------------------------------------------------------- 206309c5088eSShreyas Bhatewara * 206409c5088eSShreyas Bhatewara * vmxnet3_msix_event -- 206509c5088eSShreyas Bhatewara * 206609c5088eSShreyas Bhatewara * vmxnet3 msix event intr handler 206709c5088eSShreyas Bhatewara * 206809c5088eSShreyas Bhatewara * Result: 206909c5088eSShreyas Bhatewara * whether or not the intr is handled 207009c5088eSShreyas Bhatewara * 207109c5088eSShreyas Bhatewara *---------------------------------------------------------------------------- 207209c5088eSShreyas Bhatewara */ 207309c5088eSShreyas Bhatewara 207409c5088eSShreyas Bhatewara static irqreturn_t 207509c5088eSShreyas Bhatewara vmxnet3_msix_event(int irq, void *data) 207609c5088eSShreyas Bhatewara { 207709c5088eSShreyas Bhatewara struct net_device *dev = data; 207809c5088eSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(dev); 207909c5088eSShreyas Bhatewara 208009c5088eSShreyas Bhatewara /* disable intr if needed */ 208109c5088eSShreyas Bhatewara if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 208209c5088eSShreyas Bhatewara vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx); 208309c5088eSShreyas Bhatewara 208409c5088eSShreyas Bhatewara if (adapter->shared->ecr) 208509c5088eSShreyas Bhatewara vmxnet3_process_events(adapter); 208609c5088eSShreyas Bhatewara 208709c5088eSShreyas Bhatewara vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx); 208809c5088eSShreyas Bhatewara 208909c5088eSShreyas Bhatewara return IRQ_HANDLED; 209009c5088eSShreyas Bhatewara } 209109c5088eSShreyas Bhatewara 209209c5088eSShreyas Bhatewara #endif /* CONFIG_PCI_MSI */ 209309c5088eSShreyas Bhatewara 2094d1a890faSShreyas Bhatewara 2095d1a890faSShreyas Bhatewara /* Interrupt handler for vmxnet3 */ 2096d1a890faSShreyas Bhatewara static irqreturn_t 2097d1a890faSShreyas Bhatewara vmxnet3_intr(int irq, void *dev_id) 2098d1a890faSShreyas Bhatewara { 2099d1a890faSShreyas Bhatewara struct net_device *dev = dev_id; 2100d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(dev); 2101d1a890faSShreyas Bhatewara 210209c5088eSShreyas Bhatewara if (adapter->intr.type == VMXNET3_IT_INTX) { 2103d1a890faSShreyas Bhatewara u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR); 2104d1a890faSShreyas Bhatewara if (unlikely(icr == 0)) 2105d1a890faSShreyas Bhatewara /* not ours */ 2106d1a890faSShreyas Bhatewara return IRQ_NONE; 2107d1a890faSShreyas Bhatewara } 2108d1a890faSShreyas Bhatewara 2109d1a890faSShreyas Bhatewara 2110d1a890faSShreyas Bhatewara /* disable intr if needed */ 2111d1a890faSShreyas Bhatewara if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 211209c5088eSShreyas Bhatewara vmxnet3_disable_all_intrs(adapter); 2113d1a890faSShreyas Bhatewara 211409c5088eSShreyas Bhatewara napi_schedule(&adapter->rx_queue[0].napi); 2115d1a890faSShreyas Bhatewara 2116d1a890faSShreyas Bhatewara return IRQ_HANDLED; 2117d1a890faSShreyas Bhatewara } 2118d1a890faSShreyas Bhatewara 2119d1a890faSShreyas Bhatewara #ifdef CONFIG_NET_POLL_CONTROLLER 2120d1a890faSShreyas Bhatewara 2121d1a890faSShreyas Bhatewara /* netpoll callback. */ 2122d1a890faSShreyas Bhatewara static void 2123d1a890faSShreyas Bhatewara vmxnet3_netpoll(struct net_device *netdev) 2124d1a890faSShreyas Bhatewara { 2125d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2126d1a890faSShreyas Bhatewara 2127d25f06eaSNeil Horman switch (adapter->intr.type) { 21280a8d8c44SArnd Bergmann #ifdef CONFIG_PCI_MSI 21290a8d8c44SArnd Bergmann case VMXNET3_IT_MSIX: { 21300a8d8c44SArnd Bergmann int i; 2131d25f06eaSNeil Horman for (i = 0; i < adapter->num_rx_queues; i++) 2132d25f06eaSNeil Horman vmxnet3_msix_rx(0, &adapter->rx_queue[i]); 2133d25f06eaSNeil Horman break; 21340a8d8c44SArnd Bergmann } 21350a8d8c44SArnd Bergmann #endif 2136d25f06eaSNeil Horman case VMXNET3_IT_MSI: 2137d25f06eaSNeil Horman default: 2138d25f06eaSNeil Horman vmxnet3_intr(0, adapter->netdev); 2139d25f06eaSNeil Horman break; 2140d25f06eaSNeil Horman } 214109c5088eSShreyas Bhatewara 2142d1a890faSShreyas Bhatewara } 214309c5088eSShreyas Bhatewara #endif /* CONFIG_NET_POLL_CONTROLLER */ 2144d1a890faSShreyas Bhatewara 2145d1a890faSShreyas Bhatewara static int 2146d1a890faSShreyas Bhatewara vmxnet3_request_irqs(struct vmxnet3_adapter *adapter) 2147d1a890faSShreyas Bhatewara { 214809c5088eSShreyas Bhatewara struct vmxnet3_intr *intr = &adapter->intr; 214909c5088eSShreyas Bhatewara int err = 0, i; 215009c5088eSShreyas Bhatewara int vector = 0; 2151d1a890faSShreyas Bhatewara 21528f7e524cSRandy Dunlap #ifdef CONFIG_PCI_MSI 2153d1a890faSShreyas Bhatewara if (adapter->intr.type == VMXNET3_IT_MSIX) { 215409c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) { 215509c5088eSShreyas Bhatewara if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) { 215609c5088eSShreyas Bhatewara sprintf(adapter->tx_queue[i].name, "%s-tx-%d", 215709c5088eSShreyas Bhatewara adapter->netdev->name, vector); 215809c5088eSShreyas Bhatewara err = request_irq( 215909c5088eSShreyas Bhatewara intr->msix_entries[vector].vector, 216009c5088eSShreyas Bhatewara vmxnet3_msix_tx, 0, 216109c5088eSShreyas Bhatewara adapter->tx_queue[i].name, 216209c5088eSShreyas Bhatewara &adapter->tx_queue[i]); 216309c5088eSShreyas Bhatewara } else { 216409c5088eSShreyas Bhatewara sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d", 216509c5088eSShreyas Bhatewara adapter->netdev->name, vector); 216609c5088eSShreyas Bhatewara } 216709c5088eSShreyas Bhatewara if (err) { 216809c5088eSShreyas Bhatewara dev_err(&adapter->netdev->dev, 216909c5088eSShreyas Bhatewara "Failed to request irq for MSIX, %s, " 217009c5088eSShreyas Bhatewara "error %d\n", 217109c5088eSShreyas Bhatewara adapter->tx_queue[i].name, err); 217209c5088eSShreyas Bhatewara return err; 217309c5088eSShreyas Bhatewara } 217409c5088eSShreyas Bhatewara 217509c5088eSShreyas Bhatewara /* Handle the case where only 1 MSIx was allocated for 217609c5088eSShreyas Bhatewara * all tx queues */ 217709c5088eSShreyas Bhatewara if (adapter->share_intr == VMXNET3_INTR_TXSHARE) { 217809c5088eSShreyas Bhatewara for (; i < adapter->num_tx_queues; i++) 217909c5088eSShreyas Bhatewara adapter->tx_queue[i].comp_ring.intr_idx 218009c5088eSShreyas Bhatewara = vector; 218109c5088eSShreyas Bhatewara vector++; 218209c5088eSShreyas Bhatewara break; 218309c5088eSShreyas Bhatewara } else { 218409c5088eSShreyas Bhatewara adapter->tx_queue[i].comp_ring.intr_idx 218509c5088eSShreyas Bhatewara = vector++; 218609c5088eSShreyas Bhatewara } 218709c5088eSShreyas Bhatewara } 218809c5088eSShreyas Bhatewara if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) 218909c5088eSShreyas Bhatewara vector = 0; 219009c5088eSShreyas Bhatewara 219109c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 219209c5088eSShreyas Bhatewara if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) 219309c5088eSShreyas Bhatewara sprintf(adapter->rx_queue[i].name, "%s-rx-%d", 219409c5088eSShreyas Bhatewara adapter->netdev->name, vector); 219509c5088eSShreyas Bhatewara else 219609c5088eSShreyas Bhatewara sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d", 219709c5088eSShreyas Bhatewara adapter->netdev->name, vector); 219809c5088eSShreyas Bhatewara err = request_irq(intr->msix_entries[vector].vector, 219909c5088eSShreyas Bhatewara vmxnet3_msix_rx, 0, 220009c5088eSShreyas Bhatewara adapter->rx_queue[i].name, 220109c5088eSShreyas Bhatewara &(adapter->rx_queue[i])); 220209c5088eSShreyas Bhatewara if (err) { 2203204a6e65SStephen Hemminger netdev_err(adapter->netdev, 2204204a6e65SStephen Hemminger "Failed to request irq for MSIX, " 2205204a6e65SStephen Hemminger "%s, error %d\n", 220609c5088eSShreyas Bhatewara adapter->rx_queue[i].name, err); 220709c5088eSShreyas Bhatewara return err; 220809c5088eSShreyas Bhatewara } 220909c5088eSShreyas Bhatewara 221009c5088eSShreyas Bhatewara adapter->rx_queue[i].comp_ring.intr_idx = vector++; 221109c5088eSShreyas Bhatewara } 221209c5088eSShreyas Bhatewara 221309c5088eSShreyas Bhatewara sprintf(intr->event_msi_vector_name, "%s-event-%d", 221409c5088eSShreyas Bhatewara adapter->netdev->name, vector); 221509c5088eSShreyas Bhatewara err = request_irq(intr->msix_entries[vector].vector, 221609c5088eSShreyas Bhatewara vmxnet3_msix_event, 0, 221709c5088eSShreyas Bhatewara intr->event_msi_vector_name, adapter->netdev); 221809c5088eSShreyas Bhatewara intr->event_intr_idx = vector; 221909c5088eSShreyas Bhatewara 222009c5088eSShreyas Bhatewara } else if (intr->type == VMXNET3_IT_MSI) { 222109c5088eSShreyas Bhatewara adapter->num_rx_queues = 1; 2222d1a890faSShreyas Bhatewara err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0, 2223d1a890faSShreyas Bhatewara adapter->netdev->name, adapter->netdev); 222409c5088eSShreyas Bhatewara } else { 2225115924b6SShreyas Bhatewara #endif 222609c5088eSShreyas Bhatewara adapter->num_rx_queues = 1; 2227d1a890faSShreyas Bhatewara err = request_irq(adapter->pdev->irq, vmxnet3_intr, 2228d1a890faSShreyas Bhatewara IRQF_SHARED, adapter->netdev->name, 2229d1a890faSShreyas Bhatewara adapter->netdev); 223009c5088eSShreyas Bhatewara #ifdef CONFIG_PCI_MSI 223109c5088eSShreyas Bhatewara } 223209c5088eSShreyas Bhatewara #endif 223309c5088eSShreyas Bhatewara intr->num_intrs = vector + 1; 223409c5088eSShreyas Bhatewara if (err) { 2235204a6e65SStephen Hemminger netdev_err(adapter->netdev, 2236204a6e65SStephen Hemminger "Failed to request irq (intr type:%d), error %d\n", 2237204a6e65SStephen Hemminger intr->type, err); 223809c5088eSShreyas Bhatewara } else { 223909c5088eSShreyas Bhatewara /* Number of rx queues will not change after this */ 224009c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 224109c5088eSShreyas Bhatewara struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 224209c5088eSShreyas Bhatewara rq->qid = i; 224309c5088eSShreyas Bhatewara rq->qid2 = i + adapter->num_rx_queues; 224450a5ce3eSShrikrishna Khare rq->dataRingQid = i + 2 * adapter->num_rx_queues; 2245d1a890faSShreyas Bhatewara } 2246d1a890faSShreyas Bhatewara 2247d1a890faSShreyas Bhatewara /* init our intr settings */ 224809c5088eSShreyas Bhatewara for (i = 0; i < intr->num_intrs; i++) 224909c5088eSShreyas Bhatewara intr->mod_levels[i] = UPT1_IML_ADAPTIVE; 225009c5088eSShreyas Bhatewara if (adapter->intr.type != VMXNET3_IT_MSIX) { 2251d1a890faSShreyas Bhatewara adapter->intr.event_intr_idx = 0; 225209c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) 225309c5088eSShreyas Bhatewara adapter->tx_queue[i].comp_ring.intr_idx = 0; 225409c5088eSShreyas Bhatewara adapter->rx_queue[0].comp_ring.intr_idx = 0; 225509c5088eSShreyas Bhatewara } 2256d1a890faSShreyas Bhatewara 2257204a6e65SStephen Hemminger netdev_info(adapter->netdev, 2258204a6e65SStephen Hemminger "intr type %u, mode %u, %u vectors allocated\n", 2259204a6e65SStephen Hemminger intr->type, intr->mask_mode, intr->num_intrs); 2260d1a890faSShreyas Bhatewara } 2261d1a890faSShreyas Bhatewara 2262d1a890faSShreyas Bhatewara return err; 2263d1a890faSShreyas Bhatewara } 2264d1a890faSShreyas Bhatewara 2265d1a890faSShreyas Bhatewara 2266d1a890faSShreyas Bhatewara static void 2267d1a890faSShreyas Bhatewara vmxnet3_free_irqs(struct vmxnet3_adapter *adapter) 2268d1a890faSShreyas Bhatewara { 226909c5088eSShreyas Bhatewara struct vmxnet3_intr *intr = &adapter->intr; 227009c5088eSShreyas Bhatewara BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0); 2271d1a890faSShreyas Bhatewara 227209c5088eSShreyas Bhatewara switch (intr->type) { 22738f7e524cSRandy Dunlap #ifdef CONFIG_PCI_MSI 2274d1a890faSShreyas Bhatewara case VMXNET3_IT_MSIX: 2275d1a890faSShreyas Bhatewara { 227609c5088eSShreyas Bhatewara int i, vector = 0; 2277d1a890faSShreyas Bhatewara 227809c5088eSShreyas Bhatewara if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) { 227909c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) { 228009c5088eSShreyas Bhatewara free_irq(intr->msix_entries[vector++].vector, 228109c5088eSShreyas Bhatewara &(adapter->tx_queue[i])); 228209c5088eSShreyas Bhatewara if (adapter->share_intr == VMXNET3_INTR_TXSHARE) 228309c5088eSShreyas Bhatewara break; 228409c5088eSShreyas Bhatewara } 228509c5088eSShreyas Bhatewara } 228609c5088eSShreyas Bhatewara 228709c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 228809c5088eSShreyas Bhatewara free_irq(intr->msix_entries[vector++].vector, 228909c5088eSShreyas Bhatewara &(adapter->rx_queue[i])); 229009c5088eSShreyas Bhatewara } 229109c5088eSShreyas Bhatewara 229209c5088eSShreyas Bhatewara free_irq(intr->msix_entries[vector].vector, 2293d1a890faSShreyas Bhatewara adapter->netdev); 229409c5088eSShreyas Bhatewara BUG_ON(vector >= intr->num_intrs); 2295d1a890faSShreyas Bhatewara break; 2296d1a890faSShreyas Bhatewara } 22978f7e524cSRandy Dunlap #endif 2298d1a890faSShreyas Bhatewara case VMXNET3_IT_MSI: 2299d1a890faSShreyas Bhatewara free_irq(adapter->pdev->irq, adapter->netdev); 2300d1a890faSShreyas Bhatewara break; 2301d1a890faSShreyas Bhatewara case VMXNET3_IT_INTX: 2302d1a890faSShreyas Bhatewara free_irq(adapter->pdev->irq, adapter->netdev); 2303d1a890faSShreyas Bhatewara break; 2304d1a890faSShreyas Bhatewara default: 2305c068e777SSasha Levin BUG(); 2306d1a890faSShreyas Bhatewara } 2307d1a890faSShreyas Bhatewara } 2308d1a890faSShreyas Bhatewara 2309d1a890faSShreyas Bhatewara 2310d1a890faSShreyas Bhatewara static void 2311d1a890faSShreyas Bhatewara vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter) 2312d1a890faSShreyas Bhatewara { 2313d1a890faSShreyas Bhatewara u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 231472e85c45SJesse Gross u16 vid; 2315d1a890faSShreyas Bhatewara 231672e85c45SJesse Gross /* allow untagged pkts */ 2317d1a890faSShreyas Bhatewara VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0); 231872e85c45SJesse Gross 231972e85c45SJesse Gross for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 232072e85c45SJesse Gross VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid); 2321d1a890faSShreyas Bhatewara } 2322d1a890faSShreyas Bhatewara 2323d1a890faSShreyas Bhatewara 23248e586137SJiri Pirko static int 232580d5c368SPatrick McHardy vmxnet3_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid) 2326d1a890faSShreyas Bhatewara { 2327d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2328f6957f88SJesse Gross 2329f6957f88SJesse Gross if (!(netdev->flags & IFF_PROMISC)) { 2330d1a890faSShreyas Bhatewara u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 233183d0feffSShreyas Bhatewara unsigned long flags; 2332d1a890faSShreyas Bhatewara 2333d1a890faSShreyas Bhatewara VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid); 233483d0feffSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 2335d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2336d1a890faSShreyas Bhatewara VMXNET3_CMD_UPDATE_VLAN_FILTERS); 233783d0feffSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2338f6957f88SJesse Gross } 233972e85c45SJesse Gross 234072e85c45SJesse Gross set_bit(vid, adapter->active_vlans); 23418e586137SJiri Pirko 23428e586137SJiri Pirko return 0; 2343d1a890faSShreyas Bhatewara } 2344d1a890faSShreyas Bhatewara 2345d1a890faSShreyas Bhatewara 23468e586137SJiri Pirko static int 234780d5c368SPatrick McHardy vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid) 2348d1a890faSShreyas Bhatewara { 2349d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2350f6957f88SJesse Gross 2351f6957f88SJesse Gross if (!(netdev->flags & IFF_PROMISC)) { 2352d1a890faSShreyas Bhatewara u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 235383d0feffSShreyas Bhatewara unsigned long flags; 2354d1a890faSShreyas Bhatewara 2355d1a890faSShreyas Bhatewara VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid); 235683d0feffSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 2357d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2358d1a890faSShreyas Bhatewara VMXNET3_CMD_UPDATE_VLAN_FILTERS); 235983d0feffSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2360f6957f88SJesse Gross } 236172e85c45SJesse Gross 236272e85c45SJesse Gross clear_bit(vid, adapter->active_vlans); 23638e586137SJiri Pirko 23648e586137SJiri Pirko return 0; 2365d1a890faSShreyas Bhatewara } 2366d1a890faSShreyas Bhatewara 2367d1a890faSShreyas Bhatewara 2368d1a890faSShreyas Bhatewara static u8 * 2369d1a890faSShreyas Bhatewara vmxnet3_copy_mc(struct net_device *netdev) 2370d1a890faSShreyas Bhatewara { 2371d1a890faSShreyas Bhatewara u8 *buf = NULL; 23724cd24eafSJiri Pirko u32 sz = netdev_mc_count(netdev) * ETH_ALEN; 2373d1a890faSShreyas Bhatewara 2374d1a890faSShreyas Bhatewara /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */ 2375d1a890faSShreyas Bhatewara if (sz <= 0xffff) { 2376d1a890faSShreyas Bhatewara /* We may be called with BH disabled */ 2377d1a890faSShreyas Bhatewara buf = kmalloc(sz, GFP_ATOMIC); 2378d1a890faSShreyas Bhatewara if (buf) { 237922bedad3SJiri Pirko struct netdev_hw_addr *ha; 2380567ec874SJiri Pirko int i = 0; 2381d1a890faSShreyas Bhatewara 238222bedad3SJiri Pirko netdev_for_each_mc_addr(ha, netdev) 238322bedad3SJiri Pirko memcpy(buf + i++ * ETH_ALEN, ha->addr, 2384d1a890faSShreyas Bhatewara ETH_ALEN); 2385d1a890faSShreyas Bhatewara } 2386d1a890faSShreyas Bhatewara } 2387d1a890faSShreyas Bhatewara return buf; 2388d1a890faSShreyas Bhatewara } 2389d1a890faSShreyas Bhatewara 2390d1a890faSShreyas Bhatewara 2391d1a890faSShreyas Bhatewara static void 2392d1a890faSShreyas Bhatewara vmxnet3_set_mc(struct net_device *netdev) 2393d1a890faSShreyas Bhatewara { 2394d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 239583d0feffSShreyas Bhatewara unsigned long flags; 2396d1a890faSShreyas Bhatewara struct Vmxnet3_RxFilterConf *rxConf = 2397d1a890faSShreyas Bhatewara &adapter->shared->devRead.rxFilterConf; 2398d1a890faSShreyas Bhatewara u8 *new_table = NULL; 2399b0eb57cbSAndy King dma_addr_t new_table_pa = 0; 2400fb5c6cfaSAlexey Khoroshilov bool new_table_pa_valid = false; 2401d1a890faSShreyas Bhatewara u32 new_mode = VMXNET3_RXM_UCAST; 2402d1a890faSShreyas Bhatewara 240372e85c45SJesse Gross if (netdev->flags & IFF_PROMISC) { 240472e85c45SJesse Gross u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 240572e85c45SJesse Gross memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable)); 240672e85c45SJesse Gross 2407d1a890faSShreyas Bhatewara new_mode |= VMXNET3_RXM_PROMISC; 240872e85c45SJesse Gross } else { 240972e85c45SJesse Gross vmxnet3_restore_vlan(adapter); 241072e85c45SJesse Gross } 2411d1a890faSShreyas Bhatewara 2412d1a890faSShreyas Bhatewara if (netdev->flags & IFF_BROADCAST) 2413d1a890faSShreyas Bhatewara new_mode |= VMXNET3_RXM_BCAST; 2414d1a890faSShreyas Bhatewara 2415d1a890faSShreyas Bhatewara if (netdev->flags & IFF_ALLMULTI) 2416d1a890faSShreyas Bhatewara new_mode |= VMXNET3_RXM_ALL_MULTI; 2417d1a890faSShreyas Bhatewara else 24184cd24eafSJiri Pirko if (!netdev_mc_empty(netdev)) { 2419d1a890faSShreyas Bhatewara new_table = vmxnet3_copy_mc(netdev); 2420d1a890faSShreyas Bhatewara if (new_table) { 2421d37d5ec8SShrikrishna Khare size_t sz = netdev_mc_count(netdev) * ETH_ALEN; 2422d37d5ec8SShrikrishna Khare 2423d37d5ec8SShrikrishna Khare rxConf->mfTableLen = cpu_to_le16(sz); 2424b0eb57cbSAndy King new_table_pa = dma_map_single( 2425b0eb57cbSAndy King &adapter->pdev->dev, 2426b0eb57cbSAndy King new_table, 2427d37d5ec8SShrikrishna Khare sz, 2428bf7bec46SChristophe JAILLET DMA_TO_DEVICE); 24295738a09dSAlexey Khoroshilov if (!dma_mapping_error(&adapter->pdev->dev, 24305738a09dSAlexey Khoroshilov new_table_pa)) { 24314ad9a64fSAndy King new_mode |= VMXNET3_RXM_MCAST; 2432fb5c6cfaSAlexey Khoroshilov new_table_pa_valid = true; 2433fb5c6cfaSAlexey Khoroshilov rxConf->mfTablePA = cpu_to_le64( 2434fb5c6cfaSAlexey Khoroshilov new_table_pa); 2435fb5c6cfaSAlexey Khoroshilov } 2436fb5c6cfaSAlexey Khoroshilov } 2437fb5c6cfaSAlexey Khoroshilov if (!new_table_pa_valid) { 24384ad9a64fSAndy King netdev_info(netdev, 24394ad9a64fSAndy King "failed to copy mcast list, setting ALL_MULTI\n"); 2440d1a890faSShreyas Bhatewara new_mode |= VMXNET3_RXM_ALL_MULTI; 2441d1a890faSShreyas Bhatewara } 2442d1a890faSShreyas Bhatewara } 2443d1a890faSShreyas Bhatewara 2444d1a890faSShreyas Bhatewara if (!(new_mode & VMXNET3_RXM_MCAST)) { 2445d1a890faSShreyas Bhatewara rxConf->mfTableLen = 0; 2446d1a890faSShreyas Bhatewara rxConf->mfTablePA = 0; 2447d1a890faSShreyas Bhatewara } 2448d1a890faSShreyas Bhatewara 244983d0feffSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 2450d1a890faSShreyas Bhatewara if (new_mode != rxConf->rxMode) { 2451115924b6SShreyas Bhatewara rxConf->rxMode = cpu_to_le32(new_mode); 2452d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2453d1a890faSShreyas Bhatewara VMXNET3_CMD_UPDATE_RX_MODE); 245472e85c45SJesse Gross VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 245572e85c45SJesse Gross VMXNET3_CMD_UPDATE_VLAN_FILTERS); 2456d1a890faSShreyas Bhatewara } 2457d1a890faSShreyas Bhatewara 2458d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2459d1a890faSShreyas Bhatewara VMXNET3_CMD_UPDATE_MAC_FILTERS); 246083d0feffSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2461d1a890faSShreyas Bhatewara 2462fb5c6cfaSAlexey Khoroshilov if (new_table_pa_valid) 2463b0eb57cbSAndy King dma_unmap_single(&adapter->pdev->dev, new_table_pa, 2464bf7bec46SChristophe JAILLET rxConf->mfTableLen, DMA_TO_DEVICE); 2465d1a890faSShreyas Bhatewara kfree(new_table); 2466d1a890faSShreyas Bhatewara } 2467d1a890faSShreyas Bhatewara 246809c5088eSShreyas Bhatewara void 246909c5088eSShreyas Bhatewara vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter) 247009c5088eSShreyas Bhatewara { 247109c5088eSShreyas Bhatewara int i; 247209c5088eSShreyas Bhatewara 247309c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) 247409c5088eSShreyas Bhatewara vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter); 247509c5088eSShreyas Bhatewara } 247609c5088eSShreyas Bhatewara 2477d1a890faSShreyas Bhatewara 2478d1a890faSShreyas Bhatewara /* 2479d1a890faSShreyas Bhatewara * Set up driver_shared based on settings in adapter. 2480d1a890faSShreyas Bhatewara */ 2481d1a890faSShreyas Bhatewara 2482d1a890faSShreyas Bhatewara static void 2483d1a890faSShreyas Bhatewara vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter) 2484d1a890faSShreyas Bhatewara { 2485d1a890faSShreyas Bhatewara struct Vmxnet3_DriverShared *shared = adapter->shared; 2486d1a890faSShreyas Bhatewara struct Vmxnet3_DSDevRead *devRead = &shared->devRead; 248739f9895aSRonak Doshi struct Vmxnet3_DSDevReadExt *devReadExt = &shared->devReadExt; 2488d1a890faSShreyas Bhatewara struct Vmxnet3_TxQueueConf *tqc; 2489d1a890faSShreyas Bhatewara struct Vmxnet3_RxQueueConf *rqc; 2490d1a890faSShreyas Bhatewara int i; 2491d1a890faSShreyas Bhatewara 2492d1a890faSShreyas Bhatewara memset(shared, 0, sizeof(*shared)); 2493d1a890faSShreyas Bhatewara 2494d1a890faSShreyas Bhatewara /* driver settings */ 2495115924b6SShreyas Bhatewara shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC); 2496115924b6SShreyas Bhatewara devRead->misc.driverInfo.version = cpu_to_le32( 2497115924b6SShreyas Bhatewara VMXNET3_DRIVER_VERSION_NUM); 2498d1a890faSShreyas Bhatewara devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ? 2499d1a890faSShreyas Bhatewara VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64); 2500d1a890faSShreyas Bhatewara devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 2501115924b6SShreyas Bhatewara *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32( 2502115924b6SShreyas Bhatewara *((u32 *)&devRead->misc.driverInfo.gos)); 2503115924b6SShreyas Bhatewara devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1); 2504115924b6SShreyas Bhatewara devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1); 2505d1a890faSShreyas Bhatewara 2506b0eb57cbSAndy King devRead->misc.ddPA = cpu_to_le64(adapter->adapter_pa); 2507115924b6SShreyas Bhatewara devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter)); 2508d1a890faSShreyas Bhatewara 2509d1a890faSShreyas Bhatewara /* set up feature flags */ 2510a0d2730cSMichał Mirosław if (adapter->netdev->features & NETIF_F_RXCSUM) 25113843e515SHarvey Harrison devRead->misc.uptFeatures |= UPT1_F_RXCSUM; 2512d1a890faSShreyas Bhatewara 2513a0d2730cSMichał Mirosław if (adapter->netdev->features & NETIF_F_LRO) { 25143843e515SHarvey Harrison devRead->misc.uptFeatures |= UPT1_F_LRO; 2515115924b6SShreyas Bhatewara devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS); 2516d1a890faSShreyas Bhatewara } 2517f646968fSPatrick McHardy if (adapter->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 25183843e515SHarvey Harrison devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 2519d1a890faSShreyas Bhatewara 2520dacce2beSRonak Doshi if (adapter->netdev->features & (NETIF_F_GSO_UDP_TUNNEL | 2521dacce2beSRonak Doshi NETIF_F_GSO_UDP_TUNNEL_CSUM)) 2522dacce2beSRonak Doshi devRead->misc.uptFeatures |= UPT1_F_RXINNEROFLD; 2523dacce2beSRonak Doshi 2524115924b6SShreyas Bhatewara devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu); 2525115924b6SShreyas Bhatewara devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa); 2526115924b6SShreyas Bhatewara devRead->misc.queueDescLen = cpu_to_le32( 252709c5088eSShreyas Bhatewara adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 252809c5088eSShreyas Bhatewara adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc)); 2529d1a890faSShreyas Bhatewara 2530d1a890faSShreyas Bhatewara /* tx queue settings */ 253109c5088eSShreyas Bhatewara devRead->misc.numTxQueues = adapter->num_tx_queues; 253209c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) { 253309c5088eSShreyas Bhatewara struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i]; 253409c5088eSShreyas Bhatewara BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL); 253509c5088eSShreyas Bhatewara tqc = &adapter->tqd_start[i].conf; 253609c5088eSShreyas Bhatewara tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA); 253709c5088eSShreyas Bhatewara tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA); 253809c5088eSShreyas Bhatewara tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA); 2539de1da8bcSRonak Doshi tqc->ddPA = cpu_to_le64(~0ULL); 254009c5088eSShreyas Bhatewara tqc->txRingSize = cpu_to_le32(tq->tx_ring.size); 254109c5088eSShreyas Bhatewara tqc->dataRingSize = cpu_to_le32(tq->data_ring.size); 25423c8b3efcSShrikrishna Khare tqc->txDataRingDescSize = cpu_to_le32(tq->txdata_desc_size); 254309c5088eSShreyas Bhatewara tqc->compRingSize = cpu_to_le32(tq->comp_ring.size); 2544de1da8bcSRonak Doshi tqc->ddLen = cpu_to_le32(0); 254509c5088eSShreyas Bhatewara tqc->intrIdx = tq->comp_ring.intr_idx; 254609c5088eSShreyas Bhatewara } 2547d1a890faSShreyas Bhatewara 2548d1a890faSShreyas Bhatewara /* rx queue settings */ 254909c5088eSShreyas Bhatewara devRead->misc.numRxQueues = adapter->num_rx_queues; 255009c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 255109c5088eSShreyas Bhatewara struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 255209c5088eSShreyas Bhatewara rqc = &adapter->rqd_start[i].conf; 255309c5088eSShreyas Bhatewara rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA); 255409c5088eSShreyas Bhatewara rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA); 255509c5088eSShreyas Bhatewara rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA); 2556de1da8bcSRonak Doshi rqc->ddPA = cpu_to_le64(~0ULL); 255709c5088eSShreyas Bhatewara rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size); 255809c5088eSShreyas Bhatewara rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size); 255909c5088eSShreyas Bhatewara rqc->compRingSize = cpu_to_le32(rq->comp_ring.size); 2560de1da8bcSRonak Doshi rqc->ddLen = cpu_to_le32(0); 256109c5088eSShreyas Bhatewara rqc->intrIdx = rq->comp_ring.intr_idx; 256250a5ce3eSShrikrishna Khare if (VMXNET3_VERSION_GE_3(adapter)) { 256350a5ce3eSShrikrishna Khare rqc->rxDataRingBasePA = 256450a5ce3eSShrikrishna Khare cpu_to_le64(rq->data_ring.basePA); 256550a5ce3eSShrikrishna Khare rqc->rxDataRingDescSize = 256650a5ce3eSShrikrishna Khare cpu_to_le16(rq->data_ring.desc_size); 256750a5ce3eSShrikrishna Khare } 256809c5088eSShreyas Bhatewara } 256909c5088eSShreyas Bhatewara 257009c5088eSShreyas Bhatewara #ifdef VMXNET3_RSS 257109c5088eSShreyas Bhatewara memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf)); 257209c5088eSShreyas Bhatewara 257309c5088eSShreyas Bhatewara if (adapter->rss) { 257409c5088eSShreyas Bhatewara struct UPT1_RSSConf *rssConf = adapter->rss_conf; 257566d35910SStephen Hemminger 257609c5088eSShreyas Bhatewara devRead->misc.uptFeatures |= UPT1_F_RSS; 257709c5088eSShreyas Bhatewara devRead->misc.numRxQueues = adapter->num_rx_queues; 257809c5088eSShreyas Bhatewara rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 | 257909c5088eSShreyas Bhatewara UPT1_RSS_HASH_TYPE_IPV4 | 258009c5088eSShreyas Bhatewara UPT1_RSS_HASH_TYPE_TCP_IPV6 | 258109c5088eSShreyas Bhatewara UPT1_RSS_HASH_TYPE_IPV6; 258209c5088eSShreyas Bhatewara rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ; 258309c5088eSShreyas Bhatewara rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE; 258409c5088eSShreyas Bhatewara rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE; 25856bf79cddSEric Dumazet netdev_rss_key_fill(rssConf->hashKey, sizeof(rssConf->hashKey)); 258666d35910SStephen Hemminger 258709c5088eSShreyas Bhatewara for (i = 0; i < rssConf->indTableSize; i++) 2588278bc429SBen Hutchings rssConf->indTable[i] = ethtool_rxfh_indir_default( 2589278bc429SBen Hutchings i, adapter->num_rx_queues); 259009c5088eSShreyas Bhatewara 259109c5088eSShreyas Bhatewara devRead->rssConfDesc.confVer = 1; 2592b0eb57cbSAndy King devRead->rssConfDesc.confLen = cpu_to_le32(sizeof(*rssConf)); 2593b0eb57cbSAndy King devRead->rssConfDesc.confPA = 2594b0eb57cbSAndy King cpu_to_le64(adapter->rss_conf_pa); 259509c5088eSShreyas Bhatewara } 259609c5088eSShreyas Bhatewara 259709c5088eSShreyas Bhatewara #endif /* VMXNET3_RSS */ 2598d1a890faSShreyas Bhatewara 2599d1a890faSShreyas Bhatewara /* intr settings */ 260039f9895aSRonak Doshi if (!VMXNET3_VERSION_GE_6(adapter) || 260139f9895aSRonak Doshi !adapter->queuesExtEnabled) { 2602d1a890faSShreyas Bhatewara devRead->intrConf.autoMask = adapter->intr.mask_mode == 2603d1a890faSShreyas Bhatewara VMXNET3_IMM_AUTO; 2604d1a890faSShreyas Bhatewara devRead->intrConf.numIntrs = adapter->intr.num_intrs; 2605d1a890faSShreyas Bhatewara for (i = 0; i < adapter->intr.num_intrs; i++) 2606d1a890faSShreyas Bhatewara devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i]; 2607d1a890faSShreyas Bhatewara 2608d1a890faSShreyas Bhatewara devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx; 26096929fe8aSRonghua Zang devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL); 261039f9895aSRonak Doshi } else { 261139f9895aSRonak Doshi devReadExt->intrConfExt.autoMask = adapter->intr.mask_mode == 261239f9895aSRonak Doshi VMXNET3_IMM_AUTO; 261339f9895aSRonak Doshi devReadExt->intrConfExt.numIntrs = adapter->intr.num_intrs; 261439f9895aSRonak Doshi for (i = 0; i < adapter->intr.num_intrs; i++) 261539f9895aSRonak Doshi devReadExt->intrConfExt.modLevels[i] = adapter->intr.mod_levels[i]; 261639f9895aSRonak Doshi 261739f9895aSRonak Doshi devReadExt->intrConfExt.eventIntrIdx = adapter->intr.event_intr_idx; 261839f9895aSRonak Doshi devReadExt->intrConfExt.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL); 261939f9895aSRonak Doshi } 2620d1a890faSShreyas Bhatewara 2621d1a890faSShreyas Bhatewara /* rx filter settings */ 2622d1a890faSShreyas Bhatewara devRead->rxFilterConf.rxMode = 0; 2623d1a890faSShreyas Bhatewara vmxnet3_restore_vlan(adapter); 2624f9f25026SShreyas Bhatewara vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr); 2625f9f25026SShreyas Bhatewara 2626d1a890faSShreyas Bhatewara /* the rest are already zeroed */ 2627d1a890faSShreyas Bhatewara } 2628d1a890faSShreyas Bhatewara 26294edef40eSShrikrishna Khare static void 26304edef40eSShrikrishna Khare vmxnet3_init_coalesce(struct vmxnet3_adapter *adapter) 26314edef40eSShrikrishna Khare { 26324edef40eSShrikrishna Khare struct Vmxnet3_DriverShared *shared = adapter->shared; 26334edef40eSShrikrishna Khare union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo; 26344edef40eSShrikrishna Khare unsigned long flags; 26354edef40eSShrikrishna Khare 26364edef40eSShrikrishna Khare if (!VMXNET3_VERSION_GE_3(adapter)) 26374edef40eSShrikrishna Khare return; 26384edef40eSShrikrishna Khare 26394edef40eSShrikrishna Khare spin_lock_irqsave(&adapter->cmd_lock, flags); 26404edef40eSShrikrishna Khare cmdInfo->varConf.confVer = 1; 26414edef40eSShrikrishna Khare cmdInfo->varConf.confLen = 26424edef40eSShrikrishna Khare cpu_to_le32(sizeof(*adapter->coal_conf)); 26434edef40eSShrikrishna Khare cmdInfo->varConf.confPA = cpu_to_le64(adapter->coal_conf_pa); 26444edef40eSShrikrishna Khare 26454edef40eSShrikrishna Khare if (adapter->default_coal_mode) { 26464edef40eSShrikrishna Khare VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 26474edef40eSShrikrishna Khare VMXNET3_CMD_GET_COALESCE); 26484edef40eSShrikrishna Khare } else { 26494edef40eSShrikrishna Khare VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 26504edef40eSShrikrishna Khare VMXNET3_CMD_SET_COALESCE); 26514edef40eSShrikrishna Khare } 26524edef40eSShrikrishna Khare 26534edef40eSShrikrishna Khare spin_unlock_irqrestore(&adapter->cmd_lock, flags); 26544edef40eSShrikrishna Khare } 2655d1a890faSShreyas Bhatewara 2656d3a8a9e5SRonak Doshi static void 2657d3a8a9e5SRonak Doshi vmxnet3_init_rssfields(struct vmxnet3_adapter *adapter) 2658d3a8a9e5SRonak Doshi { 2659d3a8a9e5SRonak Doshi struct Vmxnet3_DriverShared *shared = adapter->shared; 2660d3a8a9e5SRonak Doshi union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo; 2661d3a8a9e5SRonak Doshi unsigned long flags; 2662d3a8a9e5SRonak Doshi 2663d3a8a9e5SRonak Doshi if (!VMXNET3_VERSION_GE_4(adapter)) 2664d3a8a9e5SRonak Doshi return; 2665d3a8a9e5SRonak Doshi 2666d3a8a9e5SRonak Doshi spin_lock_irqsave(&adapter->cmd_lock, flags); 2667d3a8a9e5SRonak Doshi 2668d3a8a9e5SRonak Doshi if (adapter->default_rss_fields) { 2669d3a8a9e5SRonak Doshi VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2670d3a8a9e5SRonak Doshi VMXNET3_CMD_GET_RSS_FIELDS); 2671d3a8a9e5SRonak Doshi adapter->rss_fields = 2672d3a8a9e5SRonak Doshi VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 2673d3a8a9e5SRonak Doshi } else { 2674d3a8a9e5SRonak Doshi cmdInfo->setRssFields = adapter->rss_fields; 2675d3a8a9e5SRonak Doshi VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2676d3a8a9e5SRonak Doshi VMXNET3_CMD_SET_RSS_FIELDS); 2677d3a8a9e5SRonak Doshi /* Not all requested RSS may get applied, so get and 2678d3a8a9e5SRonak Doshi * cache what was actually applied. 2679d3a8a9e5SRonak Doshi */ 2680d3a8a9e5SRonak Doshi VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2681d3a8a9e5SRonak Doshi VMXNET3_CMD_GET_RSS_FIELDS); 2682d3a8a9e5SRonak Doshi adapter->rss_fields = 2683d3a8a9e5SRonak Doshi VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 2684d3a8a9e5SRonak Doshi } 2685d3a8a9e5SRonak Doshi 2686d3a8a9e5SRonak Doshi spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2687d3a8a9e5SRonak Doshi } 2688d3a8a9e5SRonak Doshi 2689d1a890faSShreyas Bhatewara int 2690d1a890faSShreyas Bhatewara vmxnet3_activate_dev(struct vmxnet3_adapter *adapter) 2691d1a890faSShreyas Bhatewara { 269209c5088eSShreyas Bhatewara int err, i; 2693d1a890faSShreyas Bhatewara u32 ret; 269483d0feffSShreyas Bhatewara unsigned long flags; 2695d1a890faSShreyas Bhatewara 2696fdcd79b9SStephen Hemminger netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d," 269709c5088eSShreyas Bhatewara " ring sizes %u %u %u\n", adapter->netdev->name, 269809c5088eSShreyas Bhatewara adapter->skb_buf_size, adapter->rx_buf_per_pkt, 269909c5088eSShreyas Bhatewara adapter->tx_queue[0].tx_ring.size, 270009c5088eSShreyas Bhatewara adapter->rx_queue[0].rx_ring[0].size, 270109c5088eSShreyas Bhatewara adapter->rx_queue[0].rx_ring[1].size); 2702d1a890faSShreyas Bhatewara 270309c5088eSShreyas Bhatewara vmxnet3_tq_init_all(adapter); 270409c5088eSShreyas Bhatewara err = vmxnet3_rq_init_all(adapter); 2705d1a890faSShreyas Bhatewara if (err) { 2706204a6e65SStephen Hemminger netdev_err(adapter->netdev, 2707204a6e65SStephen Hemminger "Failed to init rx queue error %d\n", err); 2708d1a890faSShreyas Bhatewara goto rq_err; 2709d1a890faSShreyas Bhatewara } 2710d1a890faSShreyas Bhatewara 2711d1a890faSShreyas Bhatewara err = vmxnet3_request_irqs(adapter); 2712d1a890faSShreyas Bhatewara if (err) { 2713204a6e65SStephen Hemminger netdev_err(adapter->netdev, 2714204a6e65SStephen Hemminger "Failed to setup irq for error %d\n", err); 2715d1a890faSShreyas Bhatewara goto irq_err; 2716d1a890faSShreyas Bhatewara } 2717d1a890faSShreyas Bhatewara 2718d1a890faSShreyas Bhatewara vmxnet3_setup_driver_shared(adapter); 2719d1a890faSShreyas Bhatewara 2720115924b6SShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO( 2721115924b6SShreyas Bhatewara adapter->shared_pa)); 2722115924b6SShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI( 2723115924b6SShreyas Bhatewara adapter->shared_pa)); 272483d0feffSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 2725d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2726d1a890faSShreyas Bhatewara VMXNET3_CMD_ACTIVATE_DEV); 2727d1a890faSShreyas Bhatewara ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 272883d0feffSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2729d1a890faSShreyas Bhatewara 2730d1a890faSShreyas Bhatewara if (ret != 0) { 2731204a6e65SStephen Hemminger netdev_err(adapter->netdev, 2732204a6e65SStephen Hemminger "Failed to activate dev: error %u\n", ret); 2733d1a890faSShreyas Bhatewara err = -EINVAL; 2734d1a890faSShreyas Bhatewara goto activate_err; 2735d1a890faSShreyas Bhatewara } 273609c5088eSShreyas Bhatewara 27374edef40eSShrikrishna Khare vmxnet3_init_coalesce(adapter); 2738d3a8a9e5SRonak Doshi vmxnet3_init_rssfields(adapter); 27394edef40eSShrikrishna Khare 274009c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 274109c5088eSShreyas Bhatewara VMXNET3_WRITE_BAR0_REG(adapter, 274209c5088eSShreyas Bhatewara VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN, 274309c5088eSShreyas Bhatewara adapter->rx_queue[i].rx_ring[0].next2fill); 274409c5088eSShreyas Bhatewara VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 + 274509c5088eSShreyas Bhatewara (i * VMXNET3_REG_ALIGN)), 274609c5088eSShreyas Bhatewara adapter->rx_queue[i].rx_ring[1].next2fill); 274709c5088eSShreyas Bhatewara } 2748d1a890faSShreyas Bhatewara 2749d1a890faSShreyas Bhatewara /* Apply the rx filter settins last. */ 2750d1a890faSShreyas Bhatewara vmxnet3_set_mc(adapter->netdev); 2751d1a890faSShreyas Bhatewara 2752d1a890faSShreyas Bhatewara /* 2753d1a890faSShreyas Bhatewara * Check link state when first activating device. It will start the 2754d1a890faSShreyas Bhatewara * tx queue if the link is up. 2755d1a890faSShreyas Bhatewara */ 27564a1745fcSShreyas Bhatewara vmxnet3_check_link(adapter, true); 275739f9895aSRonak Doshi netif_tx_wake_all_queues(adapter->netdev); 275809c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) 275909c5088eSShreyas Bhatewara napi_enable(&adapter->rx_queue[i].napi); 2760d1a890faSShreyas Bhatewara vmxnet3_enable_all_intrs(adapter); 2761d1a890faSShreyas Bhatewara clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 2762d1a890faSShreyas Bhatewara return 0; 2763d1a890faSShreyas Bhatewara 2764d1a890faSShreyas Bhatewara activate_err: 2765d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0); 2766d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0); 2767d1a890faSShreyas Bhatewara vmxnet3_free_irqs(adapter); 2768d1a890faSShreyas Bhatewara irq_err: 2769d1a890faSShreyas Bhatewara rq_err: 2770d1a890faSShreyas Bhatewara /* free up buffers we allocated */ 277109c5088eSShreyas Bhatewara vmxnet3_rq_cleanup_all(adapter); 2772d1a890faSShreyas Bhatewara return err; 2773d1a890faSShreyas Bhatewara } 2774d1a890faSShreyas Bhatewara 2775d1a890faSShreyas Bhatewara 2776d1a890faSShreyas Bhatewara void 2777d1a890faSShreyas Bhatewara vmxnet3_reset_dev(struct vmxnet3_adapter *adapter) 2778d1a890faSShreyas Bhatewara { 277983d0feffSShreyas Bhatewara unsigned long flags; 278083d0feffSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 2781d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 278283d0feffSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2783d1a890faSShreyas Bhatewara } 2784d1a890faSShreyas Bhatewara 2785d1a890faSShreyas Bhatewara 2786d1a890faSShreyas Bhatewara int 2787d1a890faSShreyas Bhatewara vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter) 2788d1a890faSShreyas Bhatewara { 278909c5088eSShreyas Bhatewara int i; 279083d0feffSShreyas Bhatewara unsigned long flags; 2791d1a890faSShreyas Bhatewara if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state)) 2792d1a890faSShreyas Bhatewara return 0; 2793d1a890faSShreyas Bhatewara 2794d1a890faSShreyas Bhatewara 279583d0feffSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 2796d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2797d1a890faSShreyas Bhatewara VMXNET3_CMD_QUIESCE_DEV); 279883d0feffSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2799d1a890faSShreyas Bhatewara vmxnet3_disable_all_intrs(adapter); 2800d1a890faSShreyas Bhatewara 280109c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) 280209c5088eSShreyas Bhatewara napi_disable(&adapter->rx_queue[i].napi); 2803d1a890faSShreyas Bhatewara netif_tx_disable(adapter->netdev); 2804d1a890faSShreyas Bhatewara adapter->link_speed = 0; 2805d1a890faSShreyas Bhatewara netif_carrier_off(adapter->netdev); 2806d1a890faSShreyas Bhatewara 280709c5088eSShreyas Bhatewara vmxnet3_tq_cleanup_all(adapter); 280809c5088eSShreyas Bhatewara vmxnet3_rq_cleanup_all(adapter); 2809d1a890faSShreyas Bhatewara vmxnet3_free_irqs(adapter); 2810d1a890faSShreyas Bhatewara return 0; 2811d1a890faSShreyas Bhatewara } 2812d1a890faSShreyas Bhatewara 2813d1a890faSShreyas Bhatewara 2814d1a890faSShreyas Bhatewara static void 28158bc7823eSJakub Kicinski vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, const u8 *mac) 2816d1a890faSShreyas Bhatewara { 2817d1a890faSShreyas Bhatewara u32 tmp; 2818d1a890faSShreyas Bhatewara 2819d1a890faSShreyas Bhatewara tmp = *(u32 *)mac; 2820d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp); 2821d1a890faSShreyas Bhatewara 2822d1a890faSShreyas Bhatewara tmp = (mac[5] << 8) | mac[4]; 2823d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp); 2824d1a890faSShreyas Bhatewara } 2825d1a890faSShreyas Bhatewara 2826d1a890faSShreyas Bhatewara 2827d1a890faSShreyas Bhatewara static int 2828d1a890faSShreyas Bhatewara vmxnet3_set_mac_addr(struct net_device *netdev, void *p) 2829d1a890faSShreyas Bhatewara { 2830d1a890faSShreyas Bhatewara struct sockaddr *addr = p; 2831d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2832d1a890faSShreyas Bhatewara 2833ea52a0b5SJakub Kicinski dev_addr_set(netdev, addr->sa_data); 2834d1a890faSShreyas Bhatewara vmxnet3_write_mac_addr(adapter, addr->sa_data); 2835d1a890faSShreyas Bhatewara 2836d1a890faSShreyas Bhatewara return 0; 2837d1a890faSShreyas Bhatewara } 2838d1a890faSShreyas Bhatewara 2839d1a890faSShreyas Bhatewara 2840d1a890faSShreyas Bhatewara /* ==================== initialization and cleanup routines ============ */ 2841d1a890faSShreyas Bhatewara 2842d1a890faSShreyas Bhatewara static int 284361aeeceaShpreg@vmware.com vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter) 2844d1a890faSShreyas Bhatewara { 2845d1a890faSShreyas Bhatewara int err; 2846d1a890faSShreyas Bhatewara unsigned long mmio_start, mmio_len; 2847d1a890faSShreyas Bhatewara struct pci_dev *pdev = adapter->pdev; 2848d1a890faSShreyas Bhatewara 2849d1a890faSShreyas Bhatewara err = pci_enable_device(pdev); 2850d1a890faSShreyas Bhatewara if (err) { 2851204a6e65SStephen Hemminger dev_err(&pdev->dev, "Failed to enable adapter: error %d\n", err); 2852d1a890faSShreyas Bhatewara return err; 2853d1a890faSShreyas Bhatewara } 2854d1a890faSShreyas Bhatewara 2855d1a890faSShreyas Bhatewara err = pci_request_selected_regions(pdev, (1 << 2) - 1, 2856d1a890faSShreyas Bhatewara vmxnet3_driver_name); 2857d1a890faSShreyas Bhatewara if (err) { 2858204a6e65SStephen Hemminger dev_err(&pdev->dev, 2859204a6e65SStephen Hemminger "Failed to request region for adapter: error %d\n", err); 286061aeeceaShpreg@vmware.com goto err_enable_device; 2861d1a890faSShreyas Bhatewara } 2862d1a890faSShreyas Bhatewara 2863d1a890faSShreyas Bhatewara pci_set_master(pdev); 2864d1a890faSShreyas Bhatewara 2865d1a890faSShreyas Bhatewara mmio_start = pci_resource_start(pdev, 0); 2866d1a890faSShreyas Bhatewara mmio_len = pci_resource_len(pdev, 0); 2867d1a890faSShreyas Bhatewara adapter->hw_addr0 = ioremap(mmio_start, mmio_len); 2868d1a890faSShreyas Bhatewara if (!adapter->hw_addr0) { 2869204a6e65SStephen Hemminger dev_err(&pdev->dev, "Failed to map bar0\n"); 2870d1a890faSShreyas Bhatewara err = -EIO; 2871d1a890faSShreyas Bhatewara goto err_ioremap; 2872d1a890faSShreyas Bhatewara } 2873d1a890faSShreyas Bhatewara 2874d1a890faSShreyas Bhatewara mmio_start = pci_resource_start(pdev, 1); 2875d1a890faSShreyas Bhatewara mmio_len = pci_resource_len(pdev, 1); 2876d1a890faSShreyas Bhatewara adapter->hw_addr1 = ioremap(mmio_start, mmio_len); 2877d1a890faSShreyas Bhatewara if (!adapter->hw_addr1) { 2878204a6e65SStephen Hemminger dev_err(&pdev->dev, "Failed to map bar1\n"); 2879d1a890faSShreyas Bhatewara err = -EIO; 2880d1a890faSShreyas Bhatewara goto err_bar1; 2881d1a890faSShreyas Bhatewara } 2882d1a890faSShreyas Bhatewara return 0; 2883d1a890faSShreyas Bhatewara 2884d1a890faSShreyas Bhatewara err_bar1: 2885d1a890faSShreyas Bhatewara iounmap(adapter->hw_addr0); 2886d1a890faSShreyas Bhatewara err_ioremap: 2887d1a890faSShreyas Bhatewara pci_release_selected_regions(pdev, (1 << 2) - 1); 288861aeeceaShpreg@vmware.com err_enable_device: 2889d1a890faSShreyas Bhatewara pci_disable_device(pdev); 2890d1a890faSShreyas Bhatewara return err; 2891d1a890faSShreyas Bhatewara } 2892d1a890faSShreyas Bhatewara 2893d1a890faSShreyas Bhatewara 2894d1a890faSShreyas Bhatewara static void 2895d1a890faSShreyas Bhatewara vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter) 2896d1a890faSShreyas Bhatewara { 2897d1a890faSShreyas Bhatewara BUG_ON(!adapter->pdev); 2898d1a890faSShreyas Bhatewara 2899d1a890faSShreyas Bhatewara iounmap(adapter->hw_addr0); 2900d1a890faSShreyas Bhatewara iounmap(adapter->hw_addr1); 2901d1a890faSShreyas Bhatewara pci_release_selected_regions(adapter->pdev, (1 << 2) - 1); 2902d1a890faSShreyas Bhatewara pci_disable_device(adapter->pdev); 2903d1a890faSShreyas Bhatewara } 2904d1a890faSShreyas Bhatewara 2905d1a890faSShreyas Bhatewara 2906d1a890faSShreyas Bhatewara static void 2907d1a890faSShreyas Bhatewara vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter) 2908d1a890faSShreyas Bhatewara { 290909c5088eSShreyas Bhatewara size_t sz, i, ring0_size, ring1_size, comp_size; 2910d1a890faSShreyas Bhatewara if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE - 2911d1a890faSShreyas Bhatewara VMXNET3_MAX_ETH_HDR_SIZE) { 2912d1a890faSShreyas Bhatewara adapter->skb_buf_size = adapter->netdev->mtu + 2913d1a890faSShreyas Bhatewara VMXNET3_MAX_ETH_HDR_SIZE; 2914d1a890faSShreyas Bhatewara if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE) 2915d1a890faSShreyas Bhatewara adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE; 2916d1a890faSShreyas Bhatewara 2917d1a890faSShreyas Bhatewara adapter->rx_buf_per_pkt = 1; 2918d1a890faSShreyas Bhatewara } else { 2919d1a890faSShreyas Bhatewara adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE; 2920d1a890faSShreyas Bhatewara sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE + 2921d1a890faSShreyas Bhatewara VMXNET3_MAX_ETH_HDR_SIZE; 2922d1a890faSShreyas Bhatewara adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE; 2923d1a890faSShreyas Bhatewara } 2924d1a890faSShreyas Bhatewara 2925d1a890faSShreyas Bhatewara /* 2926d1a890faSShreyas Bhatewara * for simplicity, force the ring0 size to be a multiple of 2927d1a890faSShreyas Bhatewara * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN 2928d1a890faSShreyas Bhatewara */ 2929d1a890faSShreyas Bhatewara sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN; 293009c5088eSShreyas Bhatewara ring0_size = adapter->rx_queue[0].rx_ring[0].size; 293109c5088eSShreyas Bhatewara ring0_size = (ring0_size + sz - 1) / sz * sz; 2932a53255d3SShreyas Bhatewara ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE / 293309c5088eSShreyas Bhatewara sz * sz); 293409c5088eSShreyas Bhatewara ring1_size = adapter->rx_queue[0].rx_ring[1].size; 293553831aa1SShrikrishna Khare ring1_size = (ring1_size + sz - 1) / sz * sz; 293653831aa1SShrikrishna Khare ring1_size = min_t(u32, ring1_size, VMXNET3_RX_RING2_MAX_SIZE / 293753831aa1SShrikrishna Khare sz * sz); 293809c5088eSShreyas Bhatewara comp_size = ring0_size + ring1_size; 293909c5088eSShreyas Bhatewara 294009c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 29415e264e2bSColin Ian King struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 29425e264e2bSColin Ian King 294309c5088eSShreyas Bhatewara rq->rx_ring[0].size = ring0_size; 294409c5088eSShreyas Bhatewara rq->rx_ring[1].size = ring1_size; 294509c5088eSShreyas Bhatewara rq->comp_ring.size = comp_size; 294609c5088eSShreyas Bhatewara } 2947d1a890faSShreyas Bhatewara } 2948d1a890faSShreyas Bhatewara 2949d1a890faSShreyas Bhatewara 2950d1a890faSShreyas Bhatewara int 2951d1a890faSShreyas Bhatewara vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size, 29523c8b3efcSShrikrishna Khare u32 rx_ring_size, u32 rx_ring2_size, 295350a5ce3eSShrikrishna Khare u16 txdata_desc_size, u16 rxdata_desc_size) 2954d1a890faSShreyas Bhatewara { 295509c5088eSShreyas Bhatewara int err = 0, i; 2956d1a890faSShreyas Bhatewara 295709c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) { 295809c5088eSShreyas Bhatewara struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i]; 295909c5088eSShreyas Bhatewara tq->tx_ring.size = tx_ring_size; 296009c5088eSShreyas Bhatewara tq->data_ring.size = tx_ring_size; 296109c5088eSShreyas Bhatewara tq->comp_ring.size = tx_ring_size; 29623c8b3efcSShrikrishna Khare tq->txdata_desc_size = txdata_desc_size; 296309c5088eSShreyas Bhatewara tq->shared = &adapter->tqd_start[i].ctrl; 296409c5088eSShreyas Bhatewara tq->stopped = true; 296509c5088eSShreyas Bhatewara tq->adapter = adapter; 296609c5088eSShreyas Bhatewara tq->qid = i; 296709c5088eSShreyas Bhatewara err = vmxnet3_tq_create(tq, adapter); 296809c5088eSShreyas Bhatewara /* 296909c5088eSShreyas Bhatewara * Too late to change num_tx_queues. We cannot do away with 297009c5088eSShreyas Bhatewara * lesser number of queues than what we asked for 297109c5088eSShreyas Bhatewara */ 2972d1a890faSShreyas Bhatewara if (err) 297309c5088eSShreyas Bhatewara goto queue_err; 297409c5088eSShreyas Bhatewara } 2975d1a890faSShreyas Bhatewara 297609c5088eSShreyas Bhatewara adapter->rx_queue[0].rx_ring[0].size = rx_ring_size; 297709c5088eSShreyas Bhatewara adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size; 2978d1a890faSShreyas Bhatewara vmxnet3_adjust_rx_ring_size(adapter); 297950a5ce3eSShrikrishna Khare 298050a5ce3eSShrikrishna Khare adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter); 298109c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 298209c5088eSShreyas Bhatewara struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 298309c5088eSShreyas Bhatewara /* qid and qid2 for rx queues will be assigned later when num 298409c5088eSShreyas Bhatewara * of rx queues is finalized after allocating intrs */ 298509c5088eSShreyas Bhatewara rq->shared = &adapter->rqd_start[i].ctrl; 298609c5088eSShreyas Bhatewara rq->adapter = adapter; 298750a5ce3eSShrikrishna Khare rq->data_ring.desc_size = rxdata_desc_size; 298809c5088eSShreyas Bhatewara err = vmxnet3_rq_create(rq, adapter); 298909c5088eSShreyas Bhatewara if (err) { 299009c5088eSShreyas Bhatewara if (i == 0) { 2991204a6e65SStephen Hemminger netdev_err(adapter->netdev, 2992204a6e65SStephen Hemminger "Could not allocate any rx queues. " 2993204a6e65SStephen Hemminger "Aborting.\n"); 299409c5088eSShreyas Bhatewara goto queue_err; 299509c5088eSShreyas Bhatewara } else { 2996204a6e65SStephen Hemminger netdev_info(adapter->netdev, 2997204a6e65SStephen Hemminger "Number of rx queues changed " 299809c5088eSShreyas Bhatewara "to : %d.\n", i); 299909c5088eSShreyas Bhatewara adapter->num_rx_queues = i; 300009c5088eSShreyas Bhatewara err = 0; 300109c5088eSShreyas Bhatewara break; 300209c5088eSShreyas Bhatewara } 300309c5088eSShreyas Bhatewara } 300409c5088eSShreyas Bhatewara } 300550a5ce3eSShrikrishna Khare 300650a5ce3eSShrikrishna Khare if (!adapter->rxdataring_enabled) 300750a5ce3eSShrikrishna Khare vmxnet3_rq_destroy_all_rxdataring(adapter); 300850a5ce3eSShrikrishna Khare 300909c5088eSShreyas Bhatewara return err; 301009c5088eSShreyas Bhatewara queue_err: 301109c5088eSShreyas Bhatewara vmxnet3_tq_destroy_all(adapter); 3012d1a890faSShreyas Bhatewara return err; 3013d1a890faSShreyas Bhatewara } 3014d1a890faSShreyas Bhatewara 3015d1a890faSShreyas Bhatewara static int 3016d1a890faSShreyas Bhatewara vmxnet3_open(struct net_device *netdev) 3017d1a890faSShreyas Bhatewara { 3018d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter; 301909c5088eSShreyas Bhatewara int err, i; 3020d1a890faSShreyas Bhatewara 3021d1a890faSShreyas Bhatewara adapter = netdev_priv(netdev); 3022d1a890faSShreyas Bhatewara 302309c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_tx_queues; i++) 302409c5088eSShreyas Bhatewara spin_lock_init(&adapter->tx_queue[i].tx_lock); 3025d1a890faSShreyas Bhatewara 30263c8b3efcSShrikrishna Khare if (VMXNET3_VERSION_GE_3(adapter)) { 30273c8b3efcSShrikrishna Khare unsigned long flags; 30283c8b3efcSShrikrishna Khare u16 txdata_desc_size; 30293c8b3efcSShrikrishna Khare 30303c8b3efcSShrikrishna Khare spin_lock_irqsave(&adapter->cmd_lock, flags); 30313c8b3efcSShrikrishna Khare VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 30323c8b3efcSShrikrishna Khare VMXNET3_CMD_GET_TXDATA_DESC_SIZE); 30333c8b3efcSShrikrishna Khare txdata_desc_size = VMXNET3_READ_BAR1_REG(adapter, 30343c8b3efcSShrikrishna Khare VMXNET3_REG_CMD); 30353c8b3efcSShrikrishna Khare spin_unlock_irqrestore(&adapter->cmd_lock, flags); 30363c8b3efcSShrikrishna Khare 30373c8b3efcSShrikrishna Khare if ((txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE) || 30383c8b3efcSShrikrishna Khare (txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE) || 30393c8b3efcSShrikrishna Khare (txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK)) { 30403c8b3efcSShrikrishna Khare adapter->txdata_desc_size = 30413c8b3efcSShrikrishna Khare sizeof(struct Vmxnet3_TxDataDesc); 30423c8b3efcSShrikrishna Khare } else { 30433c8b3efcSShrikrishna Khare adapter->txdata_desc_size = txdata_desc_size; 30443c8b3efcSShrikrishna Khare } 30453c8b3efcSShrikrishna Khare } else { 30463c8b3efcSShrikrishna Khare adapter->txdata_desc_size = sizeof(struct Vmxnet3_TxDataDesc); 30473c8b3efcSShrikrishna Khare } 30483c8b3efcSShrikrishna Khare 30493c8b3efcSShrikrishna Khare err = vmxnet3_create_queues(adapter, 30503c8b3efcSShrikrishna Khare adapter->tx_ring_size, 3051f00e2b0aSNeil Horman adapter->rx_ring_size, 30523c8b3efcSShrikrishna Khare adapter->rx_ring2_size, 305350a5ce3eSShrikrishna Khare adapter->txdata_desc_size, 305450a5ce3eSShrikrishna Khare adapter->rxdata_desc_size); 3055d1a890faSShreyas Bhatewara if (err) 3056d1a890faSShreyas Bhatewara goto queue_err; 3057d1a890faSShreyas Bhatewara 3058d1a890faSShreyas Bhatewara err = vmxnet3_activate_dev(adapter); 3059d1a890faSShreyas Bhatewara if (err) 3060d1a890faSShreyas Bhatewara goto activate_err; 3061d1a890faSShreyas Bhatewara 3062d1a890faSShreyas Bhatewara return 0; 3063d1a890faSShreyas Bhatewara 3064d1a890faSShreyas Bhatewara activate_err: 306509c5088eSShreyas Bhatewara vmxnet3_rq_destroy_all(adapter); 306609c5088eSShreyas Bhatewara vmxnet3_tq_destroy_all(adapter); 3067d1a890faSShreyas Bhatewara queue_err: 3068d1a890faSShreyas Bhatewara return err; 3069d1a890faSShreyas Bhatewara } 3070d1a890faSShreyas Bhatewara 3071d1a890faSShreyas Bhatewara 3072d1a890faSShreyas Bhatewara static int 3073d1a890faSShreyas Bhatewara vmxnet3_close(struct net_device *netdev) 3074d1a890faSShreyas Bhatewara { 3075d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3076d1a890faSShreyas Bhatewara 3077d1a890faSShreyas Bhatewara /* 3078d1a890faSShreyas Bhatewara * Reset_work may be in the middle of resetting the device, wait for its 3079d1a890faSShreyas Bhatewara * completion. 3080d1a890faSShreyas Bhatewara */ 3081d1a890faSShreyas Bhatewara while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 308293c65d13SYueHaibing usleep_range(1000, 2000); 3083d1a890faSShreyas Bhatewara 3084d1a890faSShreyas Bhatewara vmxnet3_quiesce_dev(adapter); 3085d1a890faSShreyas Bhatewara 308609c5088eSShreyas Bhatewara vmxnet3_rq_destroy_all(adapter); 308709c5088eSShreyas Bhatewara vmxnet3_tq_destroy_all(adapter); 3088d1a890faSShreyas Bhatewara 3089d1a890faSShreyas Bhatewara clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3090d1a890faSShreyas Bhatewara 3091d1a890faSShreyas Bhatewara 3092d1a890faSShreyas Bhatewara return 0; 3093d1a890faSShreyas Bhatewara } 3094d1a890faSShreyas Bhatewara 3095d1a890faSShreyas Bhatewara 3096d1a890faSShreyas Bhatewara void 3097d1a890faSShreyas Bhatewara vmxnet3_force_close(struct vmxnet3_adapter *adapter) 3098d1a890faSShreyas Bhatewara { 309909c5088eSShreyas Bhatewara int i; 310009c5088eSShreyas Bhatewara 3101d1a890faSShreyas Bhatewara /* 3102d1a890faSShreyas Bhatewara * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise 3103d1a890faSShreyas Bhatewara * vmxnet3_close() will deadlock. 3104d1a890faSShreyas Bhatewara */ 3105d1a890faSShreyas Bhatewara BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)); 3106d1a890faSShreyas Bhatewara 3107d1a890faSShreyas Bhatewara /* we need to enable NAPI, otherwise dev_close will deadlock */ 310809c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) 310909c5088eSShreyas Bhatewara napi_enable(&adapter->rx_queue[i].napi); 31101c4d5f51SNeil Horman /* 31111c4d5f51SNeil Horman * Need to clear the quiesce bit to ensure that vmxnet3_close 31121c4d5f51SNeil Horman * can quiesce the device properly 31131c4d5f51SNeil Horman */ 31141c4d5f51SNeil Horman clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 3115d1a890faSShreyas Bhatewara dev_close(adapter->netdev); 3116d1a890faSShreyas Bhatewara } 3117d1a890faSShreyas Bhatewara 3118d1a890faSShreyas Bhatewara 3119d1a890faSShreyas Bhatewara static int 3120d1a890faSShreyas Bhatewara vmxnet3_change_mtu(struct net_device *netdev, int new_mtu) 3121d1a890faSShreyas Bhatewara { 3122d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3123d1a890faSShreyas Bhatewara int err = 0; 3124d1a890faSShreyas Bhatewara 3125d1a890faSShreyas Bhatewara netdev->mtu = new_mtu; 3126d1a890faSShreyas Bhatewara 3127d1a890faSShreyas Bhatewara /* 3128d1a890faSShreyas Bhatewara * Reset_work may be in the middle of resetting the device, wait for its 3129d1a890faSShreyas Bhatewara * completion. 3130d1a890faSShreyas Bhatewara */ 3131d1a890faSShreyas Bhatewara while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 313293c65d13SYueHaibing usleep_range(1000, 2000); 3133d1a890faSShreyas Bhatewara 3134d1a890faSShreyas Bhatewara if (netif_running(netdev)) { 3135d1a890faSShreyas Bhatewara vmxnet3_quiesce_dev(adapter); 3136d1a890faSShreyas Bhatewara vmxnet3_reset_dev(adapter); 3137d1a890faSShreyas Bhatewara 3138d1a890faSShreyas Bhatewara /* we need to re-create the rx queue based on the new mtu */ 313909c5088eSShreyas Bhatewara vmxnet3_rq_destroy_all(adapter); 3140d1a890faSShreyas Bhatewara vmxnet3_adjust_rx_ring_size(adapter); 314109c5088eSShreyas Bhatewara err = vmxnet3_rq_create_all(adapter); 3142d1a890faSShreyas Bhatewara if (err) { 3143204a6e65SStephen Hemminger netdev_err(netdev, 3144204a6e65SStephen Hemminger "failed to re-create rx queues, " 3145204a6e65SStephen Hemminger " error %d. Closing it.\n", err); 3146d1a890faSShreyas Bhatewara goto out; 3147d1a890faSShreyas Bhatewara } 3148d1a890faSShreyas Bhatewara 3149d1a890faSShreyas Bhatewara err = vmxnet3_activate_dev(adapter); 3150d1a890faSShreyas Bhatewara if (err) { 3151204a6e65SStephen Hemminger netdev_err(netdev, 3152204a6e65SStephen Hemminger "failed to re-activate, error %d. " 3153204a6e65SStephen Hemminger "Closing it\n", err); 3154d1a890faSShreyas Bhatewara goto out; 3155d1a890faSShreyas Bhatewara } 3156d1a890faSShreyas Bhatewara } 3157d1a890faSShreyas Bhatewara 3158d1a890faSShreyas Bhatewara out: 3159d1a890faSShreyas Bhatewara clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3160d1a890faSShreyas Bhatewara if (err) 3161d1a890faSShreyas Bhatewara vmxnet3_force_close(adapter); 3162d1a890faSShreyas Bhatewara 3163d1a890faSShreyas Bhatewara return err; 3164d1a890faSShreyas Bhatewara } 3165d1a890faSShreyas Bhatewara 3166d1a890faSShreyas Bhatewara 3167d1a890faSShreyas Bhatewara static void 3168c38f3068SChristophe JAILLET vmxnet3_declare_features(struct vmxnet3_adapter *adapter) 3169d1a890faSShreyas Bhatewara { 3170d1a890faSShreyas Bhatewara struct net_device *netdev = adapter->netdev; 3171d1a890faSShreyas Bhatewara 3172a0d2730cSMichał Mirosław netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM | 3173f646968fSPatrick McHardy NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX | 3174f646968fSPatrick McHardy NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 | 3175c38f3068SChristophe JAILLET NETIF_F_LRO | NETIF_F_HIGHDMA; 3176dacce2beSRonak Doshi 3177dacce2beSRonak Doshi if (VMXNET3_VERSION_GE_4(adapter)) { 3178dacce2beSRonak Doshi netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | 3179dacce2beSRonak Doshi NETIF_F_GSO_UDP_TUNNEL_CSUM; 3180dacce2beSRonak Doshi 3181dacce2beSRonak Doshi netdev->hw_enc_features = NETIF_F_SG | NETIF_F_RXCSUM | 3182dacce2beSRonak Doshi NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX | 3183dacce2beSRonak Doshi NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 | 3184dacce2beSRonak Doshi NETIF_F_LRO | NETIF_F_GSO_UDP_TUNNEL | 3185dacce2beSRonak Doshi NETIF_F_GSO_UDP_TUNNEL_CSUM; 3186dacce2beSRonak Doshi } 3187dacce2beSRonak Doshi 318872e85c45SJesse Gross netdev->vlan_features = netdev->hw_features & 3189f646968fSPatrick McHardy ~(NETIF_F_HW_VLAN_CTAG_TX | 3190f646968fSPatrick McHardy NETIF_F_HW_VLAN_CTAG_RX); 3191f646968fSPatrick McHardy netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER; 3192d1a890faSShreyas Bhatewara } 3193d1a890faSShreyas Bhatewara 3194d1a890faSShreyas Bhatewara 3195d1a890faSShreyas Bhatewara static void 3196d1a890faSShreyas Bhatewara vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac) 3197d1a890faSShreyas Bhatewara { 3198d1a890faSShreyas Bhatewara u32 tmp; 3199d1a890faSShreyas Bhatewara 3200d1a890faSShreyas Bhatewara tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL); 3201d1a890faSShreyas Bhatewara *(u32 *)mac = tmp; 3202d1a890faSShreyas Bhatewara 3203d1a890faSShreyas Bhatewara tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH); 3204d1a890faSShreyas Bhatewara mac[4] = tmp & 0xff; 3205d1a890faSShreyas Bhatewara mac[5] = (tmp >> 8) & 0xff; 3206d1a890faSShreyas Bhatewara } 3207d1a890faSShreyas Bhatewara 320809c5088eSShreyas Bhatewara #ifdef CONFIG_PCI_MSI 320909c5088eSShreyas Bhatewara 321009c5088eSShreyas Bhatewara /* 321109c5088eSShreyas Bhatewara * Enable MSIx vectors. 321209c5088eSShreyas Bhatewara * Returns : 321325985edcSLucas De Marchi * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required 3214b60b869dSAlexander Gordeev * were enabled. 3215b60b869dSAlexander Gordeev * number of vectors which were enabled otherwise (this number is greater 321609c5088eSShreyas Bhatewara * than VMXNET3_LINUX_MIN_MSIX_VECT) 321709c5088eSShreyas Bhatewara */ 321809c5088eSShreyas Bhatewara 321909c5088eSShreyas Bhatewara static int 3220b60b869dSAlexander Gordeev vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, int nvec) 322109c5088eSShreyas Bhatewara { 3222c0a1be38SAlexander Gordeev int ret = pci_enable_msix_range(adapter->pdev, 3223c0a1be38SAlexander Gordeev adapter->intr.msix_entries, nvec, nvec); 3224c0a1be38SAlexander Gordeev 3225c0a1be38SAlexander Gordeev if (ret == -ENOSPC && nvec > VMXNET3_LINUX_MIN_MSIX_VECT) { 32264bad25faSStephen Hemminger dev_err(&adapter->netdev->dev, 3227b60b869dSAlexander Gordeev "Failed to enable %d MSI-X, trying %d\n", 3228b60b869dSAlexander Gordeev nvec, VMXNET3_LINUX_MIN_MSIX_VECT); 322909c5088eSShreyas Bhatewara 3230c0a1be38SAlexander Gordeev ret = pci_enable_msix_range(adapter->pdev, 3231c0a1be38SAlexander Gordeev adapter->intr.msix_entries, 3232c0a1be38SAlexander Gordeev VMXNET3_LINUX_MIN_MSIX_VECT, 3233c0a1be38SAlexander Gordeev VMXNET3_LINUX_MIN_MSIX_VECT); 3234c0a1be38SAlexander Gordeev } 3235c0a1be38SAlexander Gordeev 3236c0a1be38SAlexander Gordeev if (ret < 0) { 3237c0a1be38SAlexander Gordeev dev_err(&adapter->netdev->dev, 3238c0a1be38SAlexander Gordeev "Failed to enable MSI-X, error: %d\n", ret); 3239c0a1be38SAlexander Gordeev } 3240c0a1be38SAlexander Gordeev 3241c0a1be38SAlexander Gordeev return ret; 324209c5088eSShreyas Bhatewara } 324309c5088eSShreyas Bhatewara 324409c5088eSShreyas Bhatewara 324509c5088eSShreyas Bhatewara #endif /* CONFIG_PCI_MSI */ 3246d1a890faSShreyas Bhatewara 3247d1a890faSShreyas Bhatewara static void 3248d1a890faSShreyas Bhatewara vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter) 3249d1a890faSShreyas Bhatewara { 3250d1a890faSShreyas Bhatewara u32 cfg; 3251e328d410SRoland Dreier unsigned long flags; 3252d1a890faSShreyas Bhatewara 3253d1a890faSShreyas Bhatewara /* intr settings */ 3254e328d410SRoland Dreier spin_lock_irqsave(&adapter->cmd_lock, flags); 3255d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3256d1a890faSShreyas Bhatewara VMXNET3_CMD_GET_CONF_INTR); 3257d1a890faSShreyas Bhatewara cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 3258e328d410SRoland Dreier spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3259d1a890faSShreyas Bhatewara adapter->intr.type = cfg & 0x3; 3260d1a890faSShreyas Bhatewara adapter->intr.mask_mode = (cfg >> 2) & 0x3; 3261d1a890faSShreyas Bhatewara 3262d1a890faSShreyas Bhatewara if (adapter->intr.type == VMXNET3_IT_AUTO) { 32630bdc0d70SShreyas Bhatewara adapter->intr.type = VMXNET3_IT_MSIX; 32640bdc0d70SShreyas Bhatewara } 3265d1a890faSShreyas Bhatewara 32668f7e524cSRandy Dunlap #ifdef CONFIG_PCI_MSI 32670bdc0d70SShreyas Bhatewara if (adapter->intr.type == VMXNET3_IT_MSIX) { 3268f71ef02fSRonak Doshi int i, nvec, nvec_allocated; 32690bdc0d70SShreyas Bhatewara 3270b60b869dSAlexander Gordeev nvec = adapter->share_intr == VMXNET3_INTR_TXSHARE ? 3271b60b869dSAlexander Gordeev 1 : adapter->num_tx_queues; 3272b60b869dSAlexander Gordeev nvec += adapter->share_intr == VMXNET3_INTR_BUDDYSHARE ? 3273b60b869dSAlexander Gordeev 0 : adapter->num_rx_queues; 3274b60b869dSAlexander Gordeev nvec += 1; /* for link event */ 3275b60b869dSAlexander Gordeev nvec = nvec > VMXNET3_LINUX_MIN_MSIX_VECT ? 3276b60b869dSAlexander Gordeev nvec : VMXNET3_LINUX_MIN_MSIX_VECT; 327709c5088eSShreyas Bhatewara 3278b60b869dSAlexander Gordeev for (i = 0; i < nvec; i++) 3279b60b869dSAlexander Gordeev adapter->intr.msix_entries[i].entry = i; 328009c5088eSShreyas Bhatewara 3281f71ef02fSRonak Doshi nvec_allocated = vmxnet3_acquire_msix_vectors(adapter, nvec); 3282f71ef02fSRonak Doshi if (nvec_allocated < 0) 3283b60b869dSAlexander Gordeev goto msix_err; 328409c5088eSShreyas Bhatewara 328509c5088eSShreyas Bhatewara /* If we cannot allocate one MSIx vector per queue 328609c5088eSShreyas Bhatewara * then limit the number of rx queues to 1 328709c5088eSShreyas Bhatewara */ 3288f71ef02fSRonak Doshi if (nvec_allocated == VMXNET3_LINUX_MIN_MSIX_VECT && 3289f71ef02fSRonak Doshi nvec != VMXNET3_LINUX_MIN_MSIX_VECT) { 329009c5088eSShreyas Bhatewara if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE 32917e96fbf2SShreyas Bhatewara || adapter->num_rx_queues != 1) { 329209c5088eSShreyas Bhatewara adapter->share_intr = VMXNET3_INTR_TXSHARE; 3293204a6e65SStephen Hemminger netdev_err(adapter->netdev, 3294204a6e65SStephen Hemminger "Number of rx queues : 1\n"); 329509c5088eSShreyas Bhatewara adapter->num_rx_queues = 1; 329609c5088eSShreyas Bhatewara } 3297d1a890faSShreyas Bhatewara } 3298b60b869dSAlexander Gordeev 3299f71ef02fSRonak Doshi adapter->intr.num_intrs = nvec_allocated; 330009c5088eSShreyas Bhatewara return; 330109c5088eSShreyas Bhatewara 3302b60b869dSAlexander Gordeev msix_err: 330309c5088eSShreyas Bhatewara /* If we cannot allocate MSIx vectors use only one rx queue */ 33044bad25faSStephen Hemminger dev_info(&adapter->pdev->dev, 33054bad25faSStephen Hemminger "Failed to enable MSI-X, error %d. " 3306f71ef02fSRonak Doshi "Limiting #rx queues to 1, try MSI.\n", nvec_allocated); 330709c5088eSShreyas Bhatewara 33080bdc0d70SShreyas Bhatewara adapter->intr.type = VMXNET3_IT_MSI; 33090bdc0d70SShreyas Bhatewara } 3310d1a890faSShreyas Bhatewara 33110bdc0d70SShreyas Bhatewara if (adapter->intr.type == VMXNET3_IT_MSI) { 3312b60b869dSAlexander Gordeev if (!pci_enable_msi(adapter->pdev)) { 331309c5088eSShreyas Bhatewara adapter->num_rx_queues = 1; 3314d1a890faSShreyas Bhatewara adapter->intr.num_intrs = 1; 3315d1a890faSShreyas Bhatewara return; 3316d1a890faSShreyas Bhatewara } 3317d1a890faSShreyas Bhatewara } 33180bdc0d70SShreyas Bhatewara #endif /* CONFIG_PCI_MSI */ 3319d1a890faSShreyas Bhatewara 332009c5088eSShreyas Bhatewara adapter->num_rx_queues = 1; 3321204a6e65SStephen Hemminger dev_info(&adapter->netdev->dev, 3322204a6e65SStephen Hemminger "Using INTx interrupt, #Rx queues: 1.\n"); 3323d1a890faSShreyas Bhatewara adapter->intr.type = VMXNET3_IT_INTX; 3324d1a890faSShreyas Bhatewara 3325d1a890faSShreyas Bhatewara /* INT-X related setting */ 3326d1a890faSShreyas Bhatewara adapter->intr.num_intrs = 1; 3327d1a890faSShreyas Bhatewara } 3328d1a890faSShreyas Bhatewara 3329d1a890faSShreyas Bhatewara 3330d1a890faSShreyas Bhatewara static void 3331d1a890faSShreyas Bhatewara vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter) 3332d1a890faSShreyas Bhatewara { 3333d1a890faSShreyas Bhatewara if (adapter->intr.type == VMXNET3_IT_MSIX) 3334d1a890faSShreyas Bhatewara pci_disable_msix(adapter->pdev); 3335d1a890faSShreyas Bhatewara else if (adapter->intr.type == VMXNET3_IT_MSI) 3336d1a890faSShreyas Bhatewara pci_disable_msi(adapter->pdev); 3337d1a890faSShreyas Bhatewara else 3338d1a890faSShreyas Bhatewara BUG_ON(adapter->intr.type != VMXNET3_IT_INTX); 3339d1a890faSShreyas Bhatewara } 3340d1a890faSShreyas Bhatewara 3341d1a890faSShreyas Bhatewara 3342d1a890faSShreyas Bhatewara static void 33430290bd29SMichael S. Tsirkin vmxnet3_tx_timeout(struct net_device *netdev, unsigned int txqueue) 3344d1a890faSShreyas Bhatewara { 3345d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3346d1a890faSShreyas Bhatewara adapter->tx_timeout_count++; 3347d1a890faSShreyas Bhatewara 3348204a6e65SStephen Hemminger netdev_err(adapter->netdev, "tx hang\n"); 3349d1a890faSShreyas Bhatewara schedule_work(&adapter->work); 3350d1a890faSShreyas Bhatewara } 3351d1a890faSShreyas Bhatewara 3352d1a890faSShreyas Bhatewara 3353d1a890faSShreyas Bhatewara static void 3354d1a890faSShreyas Bhatewara vmxnet3_reset_work(struct work_struct *data) 3355d1a890faSShreyas Bhatewara { 3356d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter; 3357d1a890faSShreyas Bhatewara 3358d1a890faSShreyas Bhatewara adapter = container_of(data, struct vmxnet3_adapter, work); 3359d1a890faSShreyas Bhatewara 3360d1a890faSShreyas Bhatewara /* if another thread is resetting the device, no need to proceed */ 3361d1a890faSShreyas Bhatewara if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 3362d1a890faSShreyas Bhatewara return; 3363d1a890faSShreyas Bhatewara 3364d1a890faSShreyas Bhatewara /* if the device is closed, we must leave it alone */ 3365d9a5f210SShreyas Bhatewara rtnl_lock(); 3366d1a890faSShreyas Bhatewara if (netif_running(adapter->netdev)) { 3367204a6e65SStephen Hemminger netdev_notice(adapter->netdev, "resetting\n"); 3368d1a890faSShreyas Bhatewara vmxnet3_quiesce_dev(adapter); 3369d1a890faSShreyas Bhatewara vmxnet3_reset_dev(adapter); 3370d1a890faSShreyas Bhatewara vmxnet3_activate_dev(adapter); 3371d1a890faSShreyas Bhatewara } else { 3372204a6e65SStephen Hemminger netdev_info(adapter->netdev, "already closed\n"); 3373d1a890faSShreyas Bhatewara } 3374d9a5f210SShreyas Bhatewara rtnl_unlock(); 3375d1a890faSShreyas Bhatewara 3376277964e1SBenjamin Poirier netif_wake_queue(adapter->netdev); 3377d1a890faSShreyas Bhatewara clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3378d1a890faSShreyas Bhatewara } 3379d1a890faSShreyas Bhatewara 3380d1a890faSShreyas Bhatewara 33813a4751a3SBill Pemberton static int 3382d1a890faSShreyas Bhatewara vmxnet3_probe_device(struct pci_dev *pdev, 3383d1a890faSShreyas Bhatewara const struct pci_device_id *id) 3384d1a890faSShreyas Bhatewara { 3385d1a890faSShreyas Bhatewara static const struct net_device_ops vmxnet3_netdev_ops = { 3386d1a890faSShreyas Bhatewara .ndo_open = vmxnet3_open, 3387d1a890faSShreyas Bhatewara .ndo_stop = vmxnet3_close, 3388d1a890faSShreyas Bhatewara .ndo_start_xmit = vmxnet3_xmit_frame, 3389d1a890faSShreyas Bhatewara .ndo_set_mac_address = vmxnet3_set_mac_addr, 3390d1a890faSShreyas Bhatewara .ndo_change_mtu = vmxnet3_change_mtu, 33913dd7400bSRonak Doshi .ndo_fix_features = vmxnet3_fix_features, 3392a0d2730cSMichał Mirosław .ndo_set_features = vmxnet3_set_features, 33931dac3b1bSRonak Doshi .ndo_features_check = vmxnet3_features_check, 339495305f6cSstephen hemminger .ndo_get_stats64 = vmxnet3_get_stats64, 3395d1a890faSShreyas Bhatewara .ndo_tx_timeout = vmxnet3_tx_timeout, 3396afc4b13dSJiri Pirko .ndo_set_rx_mode = vmxnet3_set_mc, 3397d1a890faSShreyas Bhatewara .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid, 3398d1a890faSShreyas Bhatewara .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid, 3399d1a890faSShreyas Bhatewara #ifdef CONFIG_NET_POLL_CONTROLLER 3400d1a890faSShreyas Bhatewara .ndo_poll_controller = vmxnet3_netpoll, 3401d1a890faSShreyas Bhatewara #endif 3402d1a890faSShreyas Bhatewara }; 3403d1a890faSShreyas Bhatewara int err; 3404d1a890faSShreyas Bhatewara u32 ver; 3405d1a890faSShreyas Bhatewara struct net_device *netdev; 3406d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter; 3407d1a890faSShreyas Bhatewara u8 mac[ETH_ALEN]; 340809c5088eSShreyas Bhatewara int size; 340909c5088eSShreyas Bhatewara int num_tx_queues; 341009c5088eSShreyas Bhatewara int num_rx_queues; 341139f9895aSRonak Doshi int queues; 341239f9895aSRonak Doshi unsigned long flags; 3413d1a890faSShreyas Bhatewara 3414e154b639SShreyas Bhatewara if (!pci_msi_enabled()) 3415e154b639SShreyas Bhatewara enable_mq = 0; 3416e154b639SShreyas Bhatewara 341709c5088eSShreyas Bhatewara #ifdef VMXNET3_RSS 341809c5088eSShreyas Bhatewara if (enable_mq) 341909c5088eSShreyas Bhatewara num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES, 342009c5088eSShreyas Bhatewara (int)num_online_cpus()); 342109c5088eSShreyas Bhatewara else 342209c5088eSShreyas Bhatewara #endif 342309c5088eSShreyas Bhatewara num_rx_queues = 1; 342409c5088eSShreyas Bhatewara 342509c5088eSShreyas Bhatewara if (enable_mq) 342609c5088eSShreyas Bhatewara num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES, 342709c5088eSShreyas Bhatewara (int)num_online_cpus()); 342809c5088eSShreyas Bhatewara else 342909c5088eSShreyas Bhatewara num_tx_queues = 1; 343009c5088eSShreyas Bhatewara 343109c5088eSShreyas Bhatewara netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter), 343209c5088eSShreyas Bhatewara max(num_tx_queues, num_rx_queues)); 343341de8d4cSJoe Perches if (!netdev) 3434d1a890faSShreyas Bhatewara return -ENOMEM; 3435d1a890faSShreyas Bhatewara 3436d1a890faSShreyas Bhatewara pci_set_drvdata(pdev, netdev); 3437d1a890faSShreyas Bhatewara adapter = netdev_priv(netdev); 3438d1a890faSShreyas Bhatewara adapter->netdev = netdev; 3439d1a890faSShreyas Bhatewara adapter->pdev = pdev; 3440d1a890faSShreyas Bhatewara 3441f00e2b0aSNeil Horman adapter->tx_ring_size = VMXNET3_DEF_TX_RING_SIZE; 3442f00e2b0aSNeil Horman adapter->rx_ring_size = VMXNET3_DEF_RX_RING_SIZE; 344353831aa1SShrikrishna Khare adapter->rx_ring2_size = VMXNET3_DEF_RX_RING2_SIZE; 3444f00e2b0aSNeil Horman 3445c38f3068SChristophe JAILLET err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3446bf7bec46SChristophe JAILLET if (err) { 3447bf7bec46SChristophe JAILLET dev_err(&pdev->dev, "dma_set_mask failed\n"); 344861aeeceaShpreg@vmware.com goto err_set_mask; 344961aeeceaShpreg@vmware.com } 345061aeeceaShpreg@vmware.com 345183d0feffSShreyas Bhatewara spin_lock_init(&adapter->cmd_lock); 3452b0eb57cbSAndy King adapter->adapter_pa = dma_map_single(&adapter->pdev->dev, adapter, 3453b0eb57cbSAndy King sizeof(struct vmxnet3_adapter), 3454bf7bec46SChristophe JAILLET DMA_TO_DEVICE); 34555738a09dSAlexey Khoroshilov if (dma_mapping_error(&adapter->pdev->dev, adapter->adapter_pa)) { 34565738a09dSAlexey Khoroshilov dev_err(&pdev->dev, "Failed to map dma\n"); 34575738a09dSAlexey Khoroshilov err = -EFAULT; 345861aeeceaShpreg@vmware.com goto err_set_mask; 34595738a09dSAlexey Khoroshilov } 3460b0eb57cbSAndy King adapter->shared = dma_alloc_coherent( 3461b0eb57cbSAndy King &adapter->pdev->dev, 3462d1a890faSShreyas Bhatewara sizeof(struct Vmxnet3_DriverShared), 3463b0eb57cbSAndy King &adapter->shared_pa, GFP_KERNEL); 3464d1a890faSShreyas Bhatewara if (!adapter->shared) { 3465204a6e65SStephen Hemminger dev_err(&pdev->dev, "Failed to allocate memory\n"); 3466d1a890faSShreyas Bhatewara err = -ENOMEM; 3467d1a890faSShreyas Bhatewara goto err_alloc_shared; 3468d1a890faSShreyas Bhatewara } 3469d1a890faSShreyas Bhatewara 347061aeeceaShpreg@vmware.com err = vmxnet3_alloc_pci_resources(adapter); 3471d1a890faSShreyas Bhatewara if (err < 0) 3472d1a890faSShreyas Bhatewara goto err_alloc_pci; 3473d1a890faSShreyas Bhatewara 3474d1a890faSShreyas Bhatewara ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS); 3475ce2639adSRonak Doshi if (ver & (1 << VMXNET3_REV_6)) { 3476ce2639adSRonak Doshi VMXNET3_WRITE_BAR1_REG(adapter, 3477ce2639adSRonak Doshi VMXNET3_REG_VRRS, 3478ce2639adSRonak Doshi 1 << VMXNET3_REV_6); 3479ce2639adSRonak Doshi adapter->version = VMXNET3_REV_6 + 1; 3480ce2639adSRonak Doshi } else if (ver & (1 << VMXNET3_REV_5)) { 3481ce2639adSRonak Doshi VMXNET3_WRITE_BAR1_REG(adapter, 3482ce2639adSRonak Doshi VMXNET3_REG_VRRS, 3483ce2639adSRonak Doshi 1 << VMXNET3_REV_5); 3484ce2639adSRonak Doshi adapter->version = VMXNET3_REV_5 + 1; 3485ce2639adSRonak Doshi } else if (ver & (1 << VMXNET3_REV_4)) { 3486a31135e3SRonak Doshi VMXNET3_WRITE_BAR1_REG(adapter, 3487a31135e3SRonak Doshi VMXNET3_REG_VRRS, 3488a31135e3SRonak Doshi 1 << VMXNET3_REV_4); 3489a31135e3SRonak Doshi adapter->version = VMXNET3_REV_4 + 1; 3490a31135e3SRonak Doshi } else if (ver & (1 << VMXNET3_REV_3)) { 34916af9d787SShrikrishna Khare VMXNET3_WRITE_BAR1_REG(adapter, 34926af9d787SShrikrishna Khare VMXNET3_REG_VRRS, 34936af9d787SShrikrishna Khare 1 << VMXNET3_REV_3); 34946af9d787SShrikrishna Khare adapter->version = VMXNET3_REV_3 + 1; 34956af9d787SShrikrishna Khare } else if (ver & (1 << VMXNET3_REV_2)) { 3496190af10fSShrikrishna Khare VMXNET3_WRITE_BAR1_REG(adapter, 3497190af10fSShrikrishna Khare VMXNET3_REG_VRRS, 3498190af10fSShrikrishna Khare 1 << VMXNET3_REV_2); 3499190af10fSShrikrishna Khare adapter->version = VMXNET3_REV_2 + 1; 3500190af10fSShrikrishna Khare } else if (ver & (1 << VMXNET3_REV_1)) { 3501190af10fSShrikrishna Khare VMXNET3_WRITE_BAR1_REG(adapter, 3502190af10fSShrikrishna Khare VMXNET3_REG_VRRS, 3503190af10fSShrikrishna Khare 1 << VMXNET3_REV_1); 3504190af10fSShrikrishna Khare adapter->version = VMXNET3_REV_1 + 1; 3505d1a890faSShreyas Bhatewara } else { 3506204a6e65SStephen Hemminger dev_err(&pdev->dev, 3507204a6e65SStephen Hemminger "Incompatible h/w version (0x%x) for adapter\n", ver); 3508d1a890faSShreyas Bhatewara err = -EBUSY; 3509d1a890faSShreyas Bhatewara goto err_ver; 3510d1a890faSShreyas Bhatewara } 351145dac1d6SShreyas Bhatewara dev_dbg(&pdev->dev, "Using device version %d\n", adapter->version); 3512d1a890faSShreyas Bhatewara 3513d1a890faSShreyas Bhatewara ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS); 3514d1a890faSShreyas Bhatewara if (ver & 1) { 3515d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1); 3516d1a890faSShreyas Bhatewara } else { 3517204a6e65SStephen Hemminger dev_err(&pdev->dev, 3518204a6e65SStephen Hemminger "Incompatible upt version (0x%x) for adapter\n", ver); 3519d1a890faSShreyas Bhatewara err = -EBUSY; 3520d1a890faSShreyas Bhatewara goto err_ver; 3521d1a890faSShreyas Bhatewara } 3522d1a890faSShreyas Bhatewara 352339f9895aSRonak Doshi if (VMXNET3_VERSION_GE_6(adapter)) { 352439f9895aSRonak Doshi spin_lock_irqsave(&adapter->cmd_lock, flags); 352539f9895aSRonak Doshi VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 352639f9895aSRonak Doshi VMXNET3_CMD_GET_MAX_QUEUES_CONF); 352739f9895aSRonak Doshi queues = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 352839f9895aSRonak Doshi spin_unlock_irqrestore(&adapter->cmd_lock, flags); 352939f9895aSRonak Doshi if (queues > 0) { 353039f9895aSRonak Doshi adapter->num_rx_queues = min(num_rx_queues, ((queues >> 8) & 0xff)); 353139f9895aSRonak Doshi adapter->num_tx_queues = min(num_tx_queues, (queues & 0xff)); 353239f9895aSRonak Doshi } else { 353339f9895aSRonak Doshi adapter->num_rx_queues = min(num_rx_queues, 353439f9895aSRonak Doshi VMXNET3_DEVICE_DEFAULT_RX_QUEUES); 353539f9895aSRonak Doshi adapter->num_tx_queues = min(num_tx_queues, 353639f9895aSRonak Doshi VMXNET3_DEVICE_DEFAULT_TX_QUEUES); 353739f9895aSRonak Doshi } 353839f9895aSRonak Doshi if (adapter->num_rx_queues > VMXNET3_MAX_RX_QUEUES || 353939f9895aSRonak Doshi adapter->num_tx_queues > VMXNET3_MAX_TX_QUEUES) { 354039f9895aSRonak Doshi adapter->queuesExtEnabled = true; 354139f9895aSRonak Doshi } else { 354239f9895aSRonak Doshi adapter->queuesExtEnabled = false; 354339f9895aSRonak Doshi } 354439f9895aSRonak Doshi } else { 354539f9895aSRonak Doshi adapter->queuesExtEnabled = false; 354615ccf2f4SRonak Doshi num_rx_queues = rounddown_pow_of_two(num_rx_queues); 354715ccf2f4SRonak Doshi num_tx_queues = rounddown_pow_of_two(num_tx_queues); 354839f9895aSRonak Doshi adapter->num_rx_queues = min(num_rx_queues, 354939f9895aSRonak Doshi VMXNET3_DEVICE_DEFAULT_RX_QUEUES); 355039f9895aSRonak Doshi adapter->num_tx_queues = min(num_tx_queues, 355139f9895aSRonak Doshi VMXNET3_DEVICE_DEFAULT_TX_QUEUES); 355239f9895aSRonak Doshi } 355339f9895aSRonak Doshi dev_info(&pdev->dev, 355439f9895aSRonak Doshi "# of Tx queues : %d, # of Rx queues : %d\n", 355539f9895aSRonak Doshi adapter->num_tx_queues, adapter->num_rx_queues); 355639f9895aSRonak Doshi 355739f9895aSRonak Doshi adapter->rx_buf_per_pkt = 1; 355839f9895aSRonak Doshi 355939f9895aSRonak Doshi size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues; 356039f9895aSRonak Doshi size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues; 356139f9895aSRonak Doshi adapter->tqd_start = dma_alloc_coherent(&adapter->pdev->dev, size, 356239f9895aSRonak Doshi &adapter->queue_desc_pa, 356339f9895aSRonak Doshi GFP_KERNEL); 356439f9895aSRonak Doshi 356539f9895aSRonak Doshi if (!adapter->tqd_start) { 356639f9895aSRonak Doshi dev_err(&pdev->dev, "Failed to allocate memory\n"); 356739f9895aSRonak Doshi err = -ENOMEM; 356839f9895aSRonak Doshi goto err_ver; 356939f9895aSRonak Doshi } 357039f9895aSRonak Doshi adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start + 357139f9895aSRonak Doshi adapter->num_tx_queues); 357239f9895aSRonak Doshi 357339f9895aSRonak Doshi adapter->pm_conf = dma_alloc_coherent(&adapter->pdev->dev, 357439f9895aSRonak Doshi sizeof(struct Vmxnet3_PMConf), 357539f9895aSRonak Doshi &adapter->pm_conf_pa, 357639f9895aSRonak Doshi GFP_KERNEL); 357739f9895aSRonak Doshi if (adapter->pm_conf == NULL) { 357839f9895aSRonak Doshi err = -ENOMEM; 357939f9895aSRonak Doshi goto err_alloc_pm; 358039f9895aSRonak Doshi } 358139f9895aSRonak Doshi 358239f9895aSRonak Doshi #ifdef VMXNET3_RSS 358339f9895aSRonak Doshi 358439f9895aSRonak Doshi adapter->rss_conf = dma_alloc_coherent(&adapter->pdev->dev, 358539f9895aSRonak Doshi sizeof(struct UPT1_RSSConf), 358639f9895aSRonak Doshi &adapter->rss_conf_pa, 358739f9895aSRonak Doshi GFP_KERNEL); 358839f9895aSRonak Doshi if (adapter->rss_conf == NULL) { 358939f9895aSRonak Doshi err = -ENOMEM; 359039f9895aSRonak Doshi goto err_alloc_rss; 359139f9895aSRonak Doshi } 359239f9895aSRonak Doshi #endif /* VMXNET3_RSS */ 359339f9895aSRonak Doshi 35944edef40eSShrikrishna Khare if (VMXNET3_VERSION_GE_3(adapter)) { 35954edef40eSShrikrishna Khare adapter->coal_conf = 35964edef40eSShrikrishna Khare dma_alloc_coherent(&adapter->pdev->dev, 35974edef40eSShrikrishna Khare sizeof(struct Vmxnet3_CoalesceScheme) 35984edef40eSShrikrishna Khare , 35994edef40eSShrikrishna Khare &adapter->coal_conf_pa, 36004edef40eSShrikrishna Khare GFP_KERNEL); 36014edef40eSShrikrishna Khare if (!adapter->coal_conf) { 36024edef40eSShrikrishna Khare err = -ENOMEM; 360339f9895aSRonak Doshi goto err_coal_conf; 36044edef40eSShrikrishna Khare } 36054edef40eSShrikrishna Khare adapter->coal_conf->coalMode = VMXNET3_COALESCE_DISABLED; 36064edef40eSShrikrishna Khare adapter->default_coal_mode = true; 36074edef40eSShrikrishna Khare } 36084edef40eSShrikrishna Khare 3609d3a8a9e5SRonak Doshi if (VMXNET3_VERSION_GE_4(adapter)) { 3610d3a8a9e5SRonak Doshi adapter->default_rss_fields = true; 3611d3a8a9e5SRonak Doshi adapter->rss_fields = VMXNET3_RSS_FIELDS_DEFAULT; 3612d3a8a9e5SRonak Doshi } 3613d3a8a9e5SRonak Doshi 3614e101e7ddSShreyas Bhatewara SET_NETDEV_DEV(netdev, &pdev->dev); 3615c38f3068SChristophe JAILLET vmxnet3_declare_features(adapter); 3616d1a890faSShreyas Bhatewara 361750a5ce3eSShrikrishna Khare adapter->rxdata_desc_size = VMXNET3_VERSION_GE_3(adapter) ? 361850a5ce3eSShrikrishna Khare VMXNET3_DEF_RXDATA_DESC_SIZE : 0; 361950a5ce3eSShrikrishna Khare 36204db37a78SStephen Hemminger if (adapter->num_tx_queues == adapter->num_rx_queues) 36214db37a78SStephen Hemminger adapter->share_intr = VMXNET3_INTR_BUDDYSHARE; 36224db37a78SStephen Hemminger else 362309c5088eSShreyas Bhatewara adapter->share_intr = VMXNET3_INTR_DONTSHARE; 362409c5088eSShreyas Bhatewara 3625d1a890faSShreyas Bhatewara vmxnet3_alloc_intr_resources(adapter); 3626d1a890faSShreyas Bhatewara 362709c5088eSShreyas Bhatewara #ifdef VMXNET3_RSS 362809c5088eSShreyas Bhatewara if (adapter->num_rx_queues > 1 && 362909c5088eSShreyas Bhatewara adapter->intr.type == VMXNET3_IT_MSIX) { 363009c5088eSShreyas Bhatewara adapter->rss = true; 36317db11f75SStephen Hemminger netdev->hw_features |= NETIF_F_RXHASH; 36327db11f75SStephen Hemminger netdev->features |= NETIF_F_RXHASH; 3633204a6e65SStephen Hemminger dev_dbg(&pdev->dev, "RSS is enabled.\n"); 363409c5088eSShreyas Bhatewara } else { 363509c5088eSShreyas Bhatewara adapter->rss = false; 363609c5088eSShreyas Bhatewara } 363709c5088eSShreyas Bhatewara #endif 363809c5088eSShreyas Bhatewara 3639d1a890faSShreyas Bhatewara vmxnet3_read_mac_addr(adapter, mac); 3640ea52a0b5SJakub Kicinski dev_addr_set(netdev, mac); 3641d1a890faSShreyas Bhatewara 3642d1a890faSShreyas Bhatewara netdev->netdev_ops = &vmxnet3_netdev_ops; 3643d1a890faSShreyas Bhatewara vmxnet3_set_ethtool_ops(netdev); 364409c5088eSShreyas Bhatewara netdev->watchdog_timeo = 5 * HZ; 3645d1a890faSShreyas Bhatewara 36468c5663e4SRonak Doshi /* MTU range: 60 - 9190 */ 3647d0c2c997SJarod Wilson netdev->min_mtu = VMXNET3_MIN_MTU; 36488c5663e4SRonak Doshi if (VMXNET3_VERSION_GE_6(adapter)) 36498c5663e4SRonak Doshi netdev->max_mtu = VMXNET3_V6_MAX_MTU; 36508c5663e4SRonak Doshi else 3651d0c2c997SJarod Wilson netdev->max_mtu = VMXNET3_MAX_MTU; 3652d0c2c997SJarod Wilson 3653d1a890faSShreyas Bhatewara INIT_WORK(&adapter->work, vmxnet3_reset_work); 3654e3bc4ffbSSteve Hodgson set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 3655d1a890faSShreyas Bhatewara 365609c5088eSShreyas Bhatewara if (adapter->intr.type == VMXNET3_IT_MSIX) { 365709c5088eSShreyas Bhatewara int i; 365809c5088eSShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) { 365909c5088eSShreyas Bhatewara netif_napi_add(adapter->netdev, 366009c5088eSShreyas Bhatewara &adapter->rx_queue[i].napi, 366109c5088eSShreyas Bhatewara vmxnet3_poll_rx_only, 64); 366209c5088eSShreyas Bhatewara } 366309c5088eSShreyas Bhatewara } else { 366409c5088eSShreyas Bhatewara netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi, 366509c5088eSShreyas Bhatewara vmxnet3_poll, 64); 366609c5088eSShreyas Bhatewara } 366709c5088eSShreyas Bhatewara 366809c5088eSShreyas Bhatewara netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); 366909c5088eSShreyas Bhatewara netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues); 367009c5088eSShreyas Bhatewara 36716cdd20c3SNeil Horman netif_carrier_off(netdev); 3672d1a890faSShreyas Bhatewara err = register_netdev(netdev); 3673d1a890faSShreyas Bhatewara 3674d1a890faSShreyas Bhatewara if (err) { 3675204a6e65SStephen Hemminger dev_err(&pdev->dev, "Failed to register adapter\n"); 3676d1a890faSShreyas Bhatewara goto err_register; 3677d1a890faSShreyas Bhatewara } 3678d1a890faSShreyas Bhatewara 36794a1745fcSShreyas Bhatewara vmxnet3_check_link(adapter, false); 3680d1a890faSShreyas Bhatewara return 0; 3681d1a890faSShreyas Bhatewara 3682d1a890faSShreyas Bhatewara err_register: 36834edef40eSShrikrishna Khare if (VMXNET3_VERSION_GE_3(adapter)) { 36844edef40eSShrikrishna Khare dma_free_coherent(&adapter->pdev->dev, 36854edef40eSShrikrishna Khare sizeof(struct Vmxnet3_CoalesceScheme), 36864edef40eSShrikrishna Khare adapter->coal_conf, adapter->coal_conf_pa); 36874edef40eSShrikrishna Khare } 3688d1a890faSShreyas Bhatewara vmxnet3_free_intr_resources(adapter); 368939f9895aSRonak Doshi err_coal_conf: 369009c5088eSShreyas Bhatewara #ifdef VMXNET3_RSS 3691b0eb57cbSAndy King dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf), 3692b0eb57cbSAndy King adapter->rss_conf, adapter->rss_conf_pa); 369309c5088eSShreyas Bhatewara err_alloc_rss: 369409c5088eSShreyas Bhatewara #endif 3695b0eb57cbSAndy King dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf), 3696b0eb57cbSAndy King adapter->pm_conf, adapter->pm_conf_pa); 3697d1a890faSShreyas Bhatewara err_alloc_pm: 3698b0eb57cbSAndy King dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start, 369909c5088eSShreyas Bhatewara adapter->queue_desc_pa); 370039f9895aSRonak Doshi err_ver: 370139f9895aSRonak Doshi vmxnet3_free_pci_resources(adapter); 370239f9895aSRonak Doshi err_alloc_pci: 3703b0eb57cbSAndy King dma_free_coherent(&adapter->pdev->dev, 3704b0eb57cbSAndy King sizeof(struct Vmxnet3_DriverShared), 3705d1a890faSShreyas Bhatewara adapter->shared, adapter->shared_pa); 3706d1a890faSShreyas Bhatewara err_alloc_shared: 3707b0eb57cbSAndy King dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa, 3708bf7bec46SChristophe JAILLET sizeof(struct vmxnet3_adapter), DMA_TO_DEVICE); 370961aeeceaShpreg@vmware.com err_set_mask: 3710d1a890faSShreyas Bhatewara free_netdev(netdev); 3711d1a890faSShreyas Bhatewara return err; 3712d1a890faSShreyas Bhatewara } 3713d1a890faSShreyas Bhatewara 3714d1a890faSShreyas Bhatewara 37153a4751a3SBill Pemberton static void 3716d1a890faSShreyas Bhatewara vmxnet3_remove_device(struct pci_dev *pdev) 3717d1a890faSShreyas Bhatewara { 3718d1a890faSShreyas Bhatewara struct net_device *netdev = pci_get_drvdata(pdev); 3719d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 372009c5088eSShreyas Bhatewara int size = 0; 372139f9895aSRonak Doshi int num_rx_queues, rx_queues; 372239f9895aSRonak Doshi unsigned long flags; 372309c5088eSShreyas Bhatewara 372409c5088eSShreyas Bhatewara #ifdef VMXNET3_RSS 372509c5088eSShreyas Bhatewara if (enable_mq) 372609c5088eSShreyas Bhatewara num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES, 372709c5088eSShreyas Bhatewara (int)num_online_cpus()); 372809c5088eSShreyas Bhatewara else 372909c5088eSShreyas Bhatewara #endif 373009c5088eSShreyas Bhatewara num_rx_queues = 1; 373115ccf2f4SRonak Doshi if (!VMXNET3_VERSION_GE_6(adapter)) { 3732eebb02b1SShreyas Bhatewara num_rx_queues = rounddown_pow_of_two(num_rx_queues); 373315ccf2f4SRonak Doshi } 373439f9895aSRonak Doshi if (VMXNET3_VERSION_GE_6(adapter)) { 373539f9895aSRonak Doshi spin_lock_irqsave(&adapter->cmd_lock, flags); 373639f9895aSRonak Doshi VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 373739f9895aSRonak Doshi VMXNET3_CMD_GET_MAX_QUEUES_CONF); 373839f9895aSRonak Doshi rx_queues = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 373939f9895aSRonak Doshi spin_unlock_irqrestore(&adapter->cmd_lock, flags); 374039f9895aSRonak Doshi if (rx_queues > 0) 374139f9895aSRonak Doshi rx_queues = (rx_queues >> 8) & 0xff; 374239f9895aSRonak Doshi else 374339f9895aSRonak Doshi rx_queues = min(num_rx_queues, VMXNET3_DEVICE_DEFAULT_RX_QUEUES); 374439f9895aSRonak Doshi num_rx_queues = min(num_rx_queues, rx_queues); 374539f9895aSRonak Doshi } else { 374639f9895aSRonak Doshi num_rx_queues = min(num_rx_queues, 374739f9895aSRonak Doshi VMXNET3_DEVICE_DEFAULT_RX_QUEUES); 374839f9895aSRonak Doshi } 3749d1a890faSShreyas Bhatewara 375023f333a2STejun Heo cancel_work_sync(&adapter->work); 3751d1a890faSShreyas Bhatewara 3752d1a890faSShreyas Bhatewara unregister_netdev(netdev); 3753d1a890faSShreyas Bhatewara 3754d1a890faSShreyas Bhatewara vmxnet3_free_intr_resources(adapter); 3755d1a890faSShreyas Bhatewara vmxnet3_free_pci_resources(adapter); 37564edef40eSShrikrishna Khare if (VMXNET3_VERSION_GE_3(adapter)) { 37574edef40eSShrikrishna Khare dma_free_coherent(&adapter->pdev->dev, 37584edef40eSShrikrishna Khare sizeof(struct Vmxnet3_CoalesceScheme), 37594edef40eSShrikrishna Khare adapter->coal_conf, adapter->coal_conf_pa); 37604edef40eSShrikrishna Khare } 376109c5088eSShreyas Bhatewara #ifdef VMXNET3_RSS 3762b0eb57cbSAndy King dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf), 3763b0eb57cbSAndy King adapter->rss_conf, adapter->rss_conf_pa); 376409c5088eSShreyas Bhatewara #endif 3765b0eb57cbSAndy King dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf), 3766b0eb57cbSAndy King adapter->pm_conf, adapter->pm_conf_pa); 376709c5088eSShreyas Bhatewara 376809c5088eSShreyas Bhatewara size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues; 376909c5088eSShreyas Bhatewara size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues; 3770b0eb57cbSAndy King dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start, 377109c5088eSShreyas Bhatewara adapter->queue_desc_pa); 3772b0eb57cbSAndy King dma_free_coherent(&adapter->pdev->dev, 3773b0eb57cbSAndy King sizeof(struct Vmxnet3_DriverShared), 3774d1a890faSShreyas Bhatewara adapter->shared, adapter->shared_pa); 3775b0eb57cbSAndy King dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa, 3776bf7bec46SChristophe JAILLET sizeof(struct vmxnet3_adapter), DMA_TO_DEVICE); 3777d1a890faSShreyas Bhatewara free_netdev(netdev); 3778d1a890faSShreyas Bhatewara } 3779d1a890faSShreyas Bhatewara 3780e9ba47bfSShreyas Bhatewara static void vmxnet3_shutdown_device(struct pci_dev *pdev) 3781e9ba47bfSShreyas Bhatewara { 3782e9ba47bfSShreyas Bhatewara struct net_device *netdev = pci_get_drvdata(pdev); 3783e9ba47bfSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3784e9ba47bfSShreyas Bhatewara unsigned long flags; 3785e9ba47bfSShreyas Bhatewara 3786e9ba47bfSShreyas Bhatewara /* Reset_work may be in the middle of resetting the device, wait for its 3787e9ba47bfSShreyas Bhatewara * completion. 3788e9ba47bfSShreyas Bhatewara */ 3789e9ba47bfSShreyas Bhatewara while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 379093c65d13SYueHaibing usleep_range(1000, 2000); 3791e9ba47bfSShreyas Bhatewara 3792e9ba47bfSShreyas Bhatewara if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, 3793e9ba47bfSShreyas Bhatewara &adapter->state)) { 3794e9ba47bfSShreyas Bhatewara clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3795e9ba47bfSShreyas Bhatewara return; 3796e9ba47bfSShreyas Bhatewara } 3797e9ba47bfSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 3798e9ba47bfSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3799e9ba47bfSShreyas Bhatewara VMXNET3_CMD_QUIESCE_DEV); 3800e9ba47bfSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3801e9ba47bfSShreyas Bhatewara vmxnet3_disable_all_intrs(adapter); 3802e9ba47bfSShreyas Bhatewara 3803e9ba47bfSShreyas Bhatewara clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3804e9ba47bfSShreyas Bhatewara } 3805e9ba47bfSShreyas Bhatewara 3806d1a890faSShreyas Bhatewara 3807d1a890faSShreyas Bhatewara #ifdef CONFIG_PM 3808d1a890faSShreyas Bhatewara 3809d1a890faSShreyas Bhatewara static int 3810d1a890faSShreyas Bhatewara vmxnet3_suspend(struct device *device) 3811d1a890faSShreyas Bhatewara { 3812d1a890faSShreyas Bhatewara struct pci_dev *pdev = to_pci_dev(device); 3813d1a890faSShreyas Bhatewara struct net_device *netdev = pci_get_drvdata(pdev); 3814d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3815d1a890faSShreyas Bhatewara struct Vmxnet3_PMConf *pmConf; 3816d1a890faSShreyas Bhatewara struct ethhdr *ehdr; 3817d1a890faSShreyas Bhatewara struct arphdr *ahdr; 3818d1a890faSShreyas Bhatewara u8 *arpreq; 3819d1a890faSShreyas Bhatewara struct in_device *in_dev; 3820d1a890faSShreyas Bhatewara struct in_ifaddr *ifa; 382183d0feffSShreyas Bhatewara unsigned long flags; 3822d1a890faSShreyas Bhatewara int i = 0; 3823d1a890faSShreyas Bhatewara 3824d1a890faSShreyas Bhatewara if (!netif_running(netdev)) 3825d1a890faSShreyas Bhatewara return 0; 3826d1a890faSShreyas Bhatewara 382751956cd6SShreyas Bhatewara for (i = 0; i < adapter->num_rx_queues; i++) 382851956cd6SShreyas Bhatewara napi_disable(&adapter->rx_queue[i].napi); 382951956cd6SShreyas Bhatewara 3830d1a890faSShreyas Bhatewara vmxnet3_disable_all_intrs(adapter); 3831d1a890faSShreyas Bhatewara vmxnet3_free_irqs(adapter); 3832d1a890faSShreyas Bhatewara vmxnet3_free_intr_resources(adapter); 3833d1a890faSShreyas Bhatewara 3834d1a890faSShreyas Bhatewara netif_device_detach(netdev); 3835d1a890faSShreyas Bhatewara 3836d1a890faSShreyas Bhatewara /* Create wake-up filters. */ 3837d1a890faSShreyas Bhatewara pmConf = adapter->pm_conf; 3838d1a890faSShreyas Bhatewara memset(pmConf, 0, sizeof(*pmConf)); 3839d1a890faSShreyas Bhatewara 3840d1a890faSShreyas Bhatewara if (adapter->wol & WAKE_UCAST) { 3841d1a890faSShreyas Bhatewara pmConf->filters[i].patternSize = ETH_ALEN; 3842d1a890faSShreyas Bhatewara pmConf->filters[i].maskSize = 1; 3843d1a890faSShreyas Bhatewara memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN); 3844d1a890faSShreyas Bhatewara pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */ 3845d1a890faSShreyas Bhatewara 38463843e515SHarvey Harrison pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER; 3847d1a890faSShreyas Bhatewara i++; 3848d1a890faSShreyas Bhatewara } 3849d1a890faSShreyas Bhatewara 3850d1a890faSShreyas Bhatewara if (adapter->wol & WAKE_ARP) { 38512638eb8bSFlorian Westphal rcu_read_lock(); 3852d1a890faSShreyas Bhatewara 38532638eb8bSFlorian Westphal in_dev = __in_dev_get_rcu(netdev); 38542638eb8bSFlorian Westphal if (!in_dev) { 38552638eb8bSFlorian Westphal rcu_read_unlock(); 3856d1a890faSShreyas Bhatewara goto skip_arp; 38572638eb8bSFlorian Westphal } 38582638eb8bSFlorian Westphal 38592638eb8bSFlorian Westphal ifa = rcu_dereference(in_dev->ifa_list); 38602638eb8bSFlorian Westphal if (!ifa) { 38612638eb8bSFlorian Westphal rcu_read_unlock(); 38622638eb8bSFlorian Westphal goto skip_arp; 38632638eb8bSFlorian Westphal } 3864d1a890faSShreyas Bhatewara 3865d1a890faSShreyas Bhatewara pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/ 3866d1a890faSShreyas Bhatewara sizeof(struct arphdr) + /* ARP header */ 3867d1a890faSShreyas Bhatewara 2 * ETH_ALEN + /* 2 Ethernet addresses*/ 3868d1a890faSShreyas Bhatewara 2 * sizeof(u32); /*2 IPv4 addresses */ 3869d1a890faSShreyas Bhatewara pmConf->filters[i].maskSize = 3870d1a890faSShreyas Bhatewara (pmConf->filters[i].patternSize - 1) / 8 + 1; 3871d1a890faSShreyas Bhatewara 3872d1a890faSShreyas Bhatewara /* ETH_P_ARP in Ethernet header. */ 3873d1a890faSShreyas Bhatewara ehdr = (struct ethhdr *)pmConf->filters[i].pattern; 3874d1a890faSShreyas Bhatewara ehdr->h_proto = htons(ETH_P_ARP); 3875d1a890faSShreyas Bhatewara 3876d1a890faSShreyas Bhatewara /* ARPOP_REQUEST in ARP header. */ 3877d1a890faSShreyas Bhatewara ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN]; 3878d1a890faSShreyas Bhatewara ahdr->ar_op = htons(ARPOP_REQUEST); 3879d1a890faSShreyas Bhatewara arpreq = (u8 *)(ahdr + 1); 3880d1a890faSShreyas Bhatewara 3881d1a890faSShreyas Bhatewara /* The Unicast IPv4 address in 'tip' field. */ 3882d1a890faSShreyas Bhatewara arpreq += 2 * ETH_ALEN + sizeof(u32); 38832638eb8bSFlorian Westphal *(__be32 *)arpreq = ifa->ifa_address; 38842638eb8bSFlorian Westphal 38852638eb8bSFlorian Westphal rcu_read_unlock(); 3886d1a890faSShreyas Bhatewara 3887d1a890faSShreyas Bhatewara /* The mask for the relevant bits. */ 3888d1a890faSShreyas Bhatewara pmConf->filters[i].mask[0] = 0x00; 3889d1a890faSShreyas Bhatewara pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */ 3890d1a890faSShreyas Bhatewara pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */ 3891d1a890faSShreyas Bhatewara pmConf->filters[i].mask[3] = 0x00; 3892d1a890faSShreyas Bhatewara pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */ 3893d1a890faSShreyas Bhatewara pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */ 3894d1a890faSShreyas Bhatewara 38953843e515SHarvey Harrison pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER; 3896d1a890faSShreyas Bhatewara i++; 3897d1a890faSShreyas Bhatewara } 3898d1a890faSShreyas Bhatewara 3899d1a890faSShreyas Bhatewara skip_arp: 3900d1a890faSShreyas Bhatewara if (adapter->wol & WAKE_MAGIC) 39013843e515SHarvey Harrison pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC; 3902d1a890faSShreyas Bhatewara 3903d1a890faSShreyas Bhatewara pmConf->numFilters = i; 3904d1a890faSShreyas Bhatewara 3905115924b6SShreyas Bhatewara adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1); 3906115924b6SShreyas Bhatewara adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof( 3907115924b6SShreyas Bhatewara *pmConf)); 3908b0eb57cbSAndy King adapter->shared->devRead.pmConfDesc.confPA = 3909b0eb57cbSAndy King cpu_to_le64(adapter->pm_conf_pa); 3910d1a890faSShreyas Bhatewara 391183d0feffSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 3912d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3913d1a890faSShreyas Bhatewara VMXNET3_CMD_UPDATE_PMCFG); 391483d0feffSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3915d1a890faSShreyas Bhatewara 3916d1a890faSShreyas Bhatewara pci_save_state(pdev); 3917d1a890faSShreyas Bhatewara pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND), 3918d1a890faSShreyas Bhatewara adapter->wol); 3919d1a890faSShreyas Bhatewara pci_disable_device(pdev); 3920d1a890faSShreyas Bhatewara pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND)); 3921d1a890faSShreyas Bhatewara 3922d1a890faSShreyas Bhatewara return 0; 3923d1a890faSShreyas Bhatewara } 3924d1a890faSShreyas Bhatewara 3925d1a890faSShreyas Bhatewara 3926d1a890faSShreyas Bhatewara static int 3927d1a890faSShreyas Bhatewara vmxnet3_resume(struct device *device) 3928d1a890faSShreyas Bhatewara { 39295ec82c1eSShrikrishna Khare int err; 393083d0feffSShreyas Bhatewara unsigned long flags; 3931d1a890faSShreyas Bhatewara struct pci_dev *pdev = to_pci_dev(device); 3932d1a890faSShreyas Bhatewara struct net_device *netdev = pci_get_drvdata(pdev); 3933d1a890faSShreyas Bhatewara struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3934d1a890faSShreyas Bhatewara 3935d1a890faSShreyas Bhatewara if (!netif_running(netdev)) 3936d1a890faSShreyas Bhatewara return 0; 3937d1a890faSShreyas Bhatewara 3938d1a890faSShreyas Bhatewara pci_set_power_state(pdev, PCI_D0); 3939d1a890faSShreyas Bhatewara pci_restore_state(pdev); 3940d1a890faSShreyas Bhatewara err = pci_enable_device_mem(pdev); 3941d1a890faSShreyas Bhatewara if (err != 0) 3942d1a890faSShreyas Bhatewara return err; 3943d1a890faSShreyas Bhatewara 3944d1a890faSShreyas Bhatewara pci_enable_wake(pdev, PCI_D0, 0); 3945d1a890faSShreyas Bhatewara 39465ec82c1eSShrikrishna Khare vmxnet3_alloc_intr_resources(adapter); 39475ec82c1eSShrikrishna Khare 39485ec82c1eSShrikrishna Khare /* During hibernate and suspend, device has to be reinitialized as the 39495ec82c1eSShrikrishna Khare * device state need not be preserved. 39505ec82c1eSShrikrishna Khare */ 39515ec82c1eSShrikrishna Khare 39525ec82c1eSShrikrishna Khare /* Need not check adapter state as other reset tasks cannot run during 39535ec82c1eSShrikrishna Khare * device resume. 39545ec82c1eSShrikrishna Khare */ 395583d0feffSShreyas Bhatewara spin_lock_irqsave(&adapter->cmd_lock, flags); 3956d1a890faSShreyas Bhatewara VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 39575ec82c1eSShrikrishna Khare VMXNET3_CMD_QUIESCE_DEV); 395883d0feffSShreyas Bhatewara spin_unlock_irqrestore(&adapter->cmd_lock, flags); 39595ec82c1eSShrikrishna Khare vmxnet3_tq_cleanup_all(adapter); 39605ec82c1eSShrikrishna Khare vmxnet3_rq_cleanup_all(adapter); 39615ec82c1eSShrikrishna Khare 39625ec82c1eSShrikrishna Khare vmxnet3_reset_dev(adapter); 39635ec82c1eSShrikrishna Khare err = vmxnet3_activate_dev(adapter); 39645ec82c1eSShrikrishna Khare if (err != 0) { 39655ec82c1eSShrikrishna Khare netdev_err(netdev, 39665ec82c1eSShrikrishna Khare "failed to re-activate on resume, error: %d", err); 39675ec82c1eSShrikrishna Khare vmxnet3_force_close(adapter); 39685ec82c1eSShrikrishna Khare return err; 39695ec82c1eSShrikrishna Khare } 39705ec82c1eSShrikrishna Khare netif_device_attach(netdev); 3971d1a890faSShreyas Bhatewara 3972d1a890faSShreyas Bhatewara return 0; 3973d1a890faSShreyas Bhatewara } 3974d1a890faSShreyas Bhatewara 397547145210SAlexey Dobriyan static const struct dev_pm_ops vmxnet3_pm_ops = { 3976d1a890faSShreyas Bhatewara .suspend = vmxnet3_suspend, 3977d1a890faSShreyas Bhatewara .resume = vmxnet3_resume, 39785ec82c1eSShrikrishna Khare .freeze = vmxnet3_suspend, 39795ec82c1eSShrikrishna Khare .restore = vmxnet3_resume, 3980d1a890faSShreyas Bhatewara }; 3981d1a890faSShreyas Bhatewara #endif 3982d1a890faSShreyas Bhatewara 3983d1a890faSShreyas Bhatewara static struct pci_driver vmxnet3_driver = { 3984d1a890faSShreyas Bhatewara .name = vmxnet3_driver_name, 3985d1a890faSShreyas Bhatewara .id_table = vmxnet3_pciid_table, 3986d1a890faSShreyas Bhatewara .probe = vmxnet3_probe_device, 39873a4751a3SBill Pemberton .remove = vmxnet3_remove_device, 3988e9ba47bfSShreyas Bhatewara .shutdown = vmxnet3_shutdown_device, 3989d1a890faSShreyas Bhatewara #ifdef CONFIG_PM 3990d1a890faSShreyas Bhatewara .driver.pm = &vmxnet3_pm_ops, 3991d1a890faSShreyas Bhatewara #endif 3992d1a890faSShreyas Bhatewara }; 3993d1a890faSShreyas Bhatewara 3994d1a890faSShreyas Bhatewara 3995d1a890faSShreyas Bhatewara static int __init 3996d1a890faSShreyas Bhatewara vmxnet3_init_module(void) 3997d1a890faSShreyas Bhatewara { 3998204a6e65SStephen Hemminger pr_info("%s - version %s\n", VMXNET3_DRIVER_DESC, 3999d1a890faSShreyas Bhatewara VMXNET3_DRIVER_VERSION_REPORT); 4000d1a890faSShreyas Bhatewara return pci_register_driver(&vmxnet3_driver); 4001d1a890faSShreyas Bhatewara } 4002d1a890faSShreyas Bhatewara 4003d1a890faSShreyas Bhatewara module_init(vmxnet3_init_module); 4004d1a890faSShreyas Bhatewara 4005d1a890faSShreyas Bhatewara 4006d1a890faSShreyas Bhatewara static void 4007d1a890faSShreyas Bhatewara vmxnet3_exit_module(void) 4008d1a890faSShreyas Bhatewara { 4009d1a890faSShreyas Bhatewara pci_unregister_driver(&vmxnet3_driver); 4010d1a890faSShreyas Bhatewara } 4011d1a890faSShreyas Bhatewara 4012d1a890faSShreyas Bhatewara module_exit(vmxnet3_exit_module); 4013d1a890faSShreyas Bhatewara 4014d1a890faSShreyas Bhatewara MODULE_AUTHOR("VMware, Inc."); 4015d1a890faSShreyas Bhatewara MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC); 4016d1a890faSShreyas Bhatewara MODULE_LICENSE("GPL v2"); 4017d1a890faSShreyas Bhatewara MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING); 4018