1 /* 2 * Linux driver for VMware's vmxnet3 ethernet NIC. 3 * 4 * Copyright (C) 2008-2016, VMware, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; version 2 of the License and no later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 13 * NON INFRINGEMENT. See the GNU General Public License for more 14 * details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * The full GNU General Public License is included in this distribution in 21 * the file called "COPYING". 22 * 23 * Maintained by: pv-drivers@vmware.com 24 * 25 */ 26 27 #ifndef _VMXNET3_DEFS_H_ 28 #define _VMXNET3_DEFS_H_ 29 30 #include "upt1_defs.h" 31 32 /* all registers are 32 bit wide */ 33 /* BAR 1 */ 34 enum { 35 VMXNET3_REG_VRRS = 0x0, /* Vmxnet3 Revision Report Selection */ 36 VMXNET3_REG_UVRS = 0x8, /* UPT Version Report Selection */ 37 VMXNET3_REG_DSAL = 0x10, /* Driver Shared Address Low */ 38 VMXNET3_REG_DSAH = 0x18, /* Driver Shared Address High */ 39 VMXNET3_REG_CMD = 0x20, /* Command */ 40 VMXNET3_REG_MACL = 0x28, /* MAC Address Low */ 41 VMXNET3_REG_MACH = 0x30, /* MAC Address High */ 42 VMXNET3_REG_ICR = 0x38, /* Interrupt Cause Register */ 43 VMXNET3_REG_ECR = 0x40 /* Event Cause Register */ 44 }; 45 46 /* BAR 0 */ 47 enum { 48 VMXNET3_REG_IMR = 0x0, /* Interrupt Mask Register */ 49 VMXNET3_REG_TXPROD = 0x600, /* Tx Producer Index */ 50 VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */ 51 VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */ 52 }; 53 54 #define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */ 55 #define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */ 56 57 #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */ 58 #define VMXNET3_REG_ALIGN_MASK 0x7 59 60 /* I/O Mapped access to registers */ 61 #define VMXNET3_IO_TYPE_PT 0 62 #define VMXNET3_IO_TYPE_VD 1 63 #define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF)) 64 #define VMXNET3_IO_TYPE(addr) ((addr) >> 24) 65 #define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF) 66 67 enum { 68 VMXNET3_CMD_FIRST_SET = 0xCAFE0000, 69 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET, 70 VMXNET3_CMD_QUIESCE_DEV, 71 VMXNET3_CMD_RESET_DEV, 72 VMXNET3_CMD_UPDATE_RX_MODE, 73 VMXNET3_CMD_UPDATE_MAC_FILTERS, 74 VMXNET3_CMD_UPDATE_VLAN_FILTERS, 75 VMXNET3_CMD_UPDATE_RSSIDT, 76 VMXNET3_CMD_UPDATE_IML, 77 VMXNET3_CMD_UPDATE_PMCFG, 78 VMXNET3_CMD_UPDATE_FEATURE, 79 VMXNET3_CMD_RESERVED1, 80 VMXNET3_CMD_LOAD_PLUGIN, 81 VMXNET3_CMD_RESERVED2, 82 VMXNET3_CMD_RESERVED3, 83 VMXNET3_CMD_SET_COALESCE, 84 VMXNET3_CMD_REGISTER_MEMREGS, 85 86 VMXNET3_CMD_FIRST_GET = 0xF00D0000, 87 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET, 88 VMXNET3_CMD_GET_STATS, 89 VMXNET3_CMD_GET_LINK, 90 VMXNET3_CMD_GET_PERM_MAC_LO, 91 VMXNET3_CMD_GET_PERM_MAC_HI, 92 VMXNET3_CMD_GET_DID_LO, 93 VMXNET3_CMD_GET_DID_HI, 94 VMXNET3_CMD_GET_DEV_EXTRA_INFO, 95 VMXNET3_CMD_GET_CONF_INTR, 96 VMXNET3_CMD_GET_RESERVED1, 97 VMXNET3_CMD_GET_TXDATA_DESC_SIZE, 98 VMXNET3_CMD_GET_COALESCE, 99 }; 100 101 /* 102 * Little Endian layout of bitfields - 103 * Byte 0 : 7.....len.....0 104 * Byte 1 : rsvd gen 13.len.8 105 * Byte 2 : 5.msscof.0 ext1 dtype 106 * Byte 3 : 13...msscof...6 107 * 108 * Big Endian layout of bitfields - 109 * Byte 0: 13...msscof...6 110 * Byte 1 : 5.msscof.0 ext1 dtype 111 * Byte 2 : rsvd gen 13.len.8 112 * Byte 3 : 7.....len.....0 113 * 114 * Thus, le32_to_cpu on the dword will allow the big endian driver to read 115 * the bit fields correctly. And cpu_to_le32 will convert bitfields 116 * bit fields written by big endian driver to format required by device. 117 */ 118 119 struct Vmxnet3_TxDesc { 120 __le64 addr; 121 122 #ifdef __BIG_ENDIAN_BITFIELD 123 u32 msscof:14; /* MSS, checksum offset, flags */ 124 u32 ext1:1; 125 u32 dtype:1; /* descriptor type */ 126 u32 rsvd:1; 127 u32 gen:1; /* generation bit */ 128 u32 len:14; 129 #else 130 u32 len:14; 131 u32 gen:1; /* generation bit */ 132 u32 rsvd:1; 133 u32 dtype:1; /* descriptor type */ 134 u32 ext1:1; 135 u32 msscof:14; /* MSS, checksum offset, flags */ 136 #endif /* __BIG_ENDIAN_BITFIELD */ 137 138 #ifdef __BIG_ENDIAN_BITFIELD 139 u32 tci:16; /* Tag to Insert */ 140 u32 ti:1; /* VLAN Tag Insertion */ 141 u32 ext2:1; 142 u32 cq:1; /* completion request */ 143 u32 eop:1; /* End Of Packet */ 144 u32 om:2; /* offload mode */ 145 u32 hlen:10; /* header len */ 146 #else 147 u32 hlen:10; /* header len */ 148 u32 om:2; /* offload mode */ 149 u32 eop:1; /* End Of Packet */ 150 u32 cq:1; /* completion request */ 151 u32 ext2:1; 152 u32 ti:1; /* VLAN Tag Insertion */ 153 u32 tci:16; /* Tag to Insert */ 154 #endif /* __BIG_ENDIAN_BITFIELD */ 155 }; 156 157 /* TxDesc.OM values */ 158 #define VMXNET3_OM_NONE 0 159 #define VMXNET3_OM_CSUM 2 160 #define VMXNET3_OM_TSO 3 161 162 /* fields in TxDesc we access w/o using bit fields */ 163 #define VMXNET3_TXD_EOP_SHIFT 12 164 #define VMXNET3_TXD_CQ_SHIFT 13 165 #define VMXNET3_TXD_GEN_SHIFT 14 166 #define VMXNET3_TXD_EOP_DWORD_SHIFT 3 167 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2 168 169 #define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT) 170 #define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT) 171 #define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT) 172 173 #define VMXNET3_HDR_COPY_SIZE 128 174 175 176 struct Vmxnet3_TxDataDesc { 177 u8 data[VMXNET3_HDR_COPY_SIZE]; 178 }; 179 180 typedef u8 Vmxnet3_RxDataDesc; 181 182 #define VMXNET3_TCD_GEN_SHIFT 31 183 #define VMXNET3_TCD_GEN_SIZE 1 184 #define VMXNET3_TCD_TXIDX_SHIFT 0 185 #define VMXNET3_TCD_TXIDX_SIZE 12 186 #define VMXNET3_TCD_GEN_DWORD_SHIFT 3 187 188 struct Vmxnet3_TxCompDesc { 189 u32 txdIdx:12; /* Index of the EOP TxDesc */ 190 u32 ext1:20; 191 192 __le32 ext2; 193 __le32 ext3; 194 195 u32 rsvd:24; 196 u32 type:7; /* completion type */ 197 u32 gen:1; /* generation bit */ 198 }; 199 200 struct Vmxnet3_RxDesc { 201 __le64 addr; 202 203 #ifdef __BIG_ENDIAN_BITFIELD 204 u32 gen:1; /* Generation bit */ 205 u32 rsvd:15; 206 u32 dtype:1; /* Descriptor type */ 207 u32 btype:1; /* Buffer Type */ 208 u32 len:14; 209 #else 210 u32 len:14; 211 u32 btype:1; /* Buffer Type */ 212 u32 dtype:1; /* Descriptor type */ 213 u32 rsvd:15; 214 u32 gen:1; /* Generation bit */ 215 #endif 216 u32 ext1; 217 }; 218 219 /* values of RXD.BTYPE */ 220 #define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */ 221 #define VMXNET3_RXD_BTYPE_BODY 1 /* body only */ 222 223 /* fields in RxDesc we access w/o using bit fields */ 224 #define VMXNET3_RXD_BTYPE_SHIFT 14 225 #define VMXNET3_RXD_GEN_SHIFT 31 226 227 struct Vmxnet3_RxCompDesc { 228 #ifdef __BIG_ENDIAN_BITFIELD 229 u32 ext2:1; 230 u32 cnc:1; /* Checksum Not Calculated */ 231 u32 rssType:4; /* RSS hash type used */ 232 u32 rqID:10; /* rx queue/ring ID */ 233 u32 sop:1; /* Start of Packet */ 234 u32 eop:1; /* End of Packet */ 235 u32 ext1:2; 236 u32 rxdIdx:12; /* Index of the RxDesc */ 237 #else 238 u32 rxdIdx:12; /* Index of the RxDesc */ 239 u32 ext1:2; 240 u32 eop:1; /* End of Packet */ 241 u32 sop:1; /* Start of Packet */ 242 u32 rqID:10; /* rx queue/ring ID */ 243 u32 rssType:4; /* RSS hash type used */ 244 u32 cnc:1; /* Checksum Not Calculated */ 245 u32 ext2:1; 246 #endif /* __BIG_ENDIAN_BITFIELD */ 247 248 __le32 rssHash; /* RSS hash value */ 249 250 #ifdef __BIG_ENDIAN_BITFIELD 251 u32 tci:16; /* Tag stripped */ 252 u32 ts:1; /* Tag is stripped */ 253 u32 err:1; /* Error */ 254 u32 len:14; /* data length */ 255 #else 256 u32 len:14; /* data length */ 257 u32 err:1; /* Error */ 258 u32 ts:1; /* Tag is stripped */ 259 u32 tci:16; /* Tag stripped */ 260 #endif /* __BIG_ENDIAN_BITFIELD */ 261 262 263 #ifdef __BIG_ENDIAN_BITFIELD 264 u32 gen:1; /* generation bit */ 265 u32 type:7; /* completion type */ 266 u32 fcs:1; /* Frame CRC correct */ 267 u32 frg:1; /* IP Fragment */ 268 u32 v4:1; /* IPv4 */ 269 u32 v6:1; /* IPv6 */ 270 u32 ipc:1; /* IP Checksum Correct */ 271 u32 tcp:1; /* TCP packet */ 272 u32 udp:1; /* UDP packet */ 273 u32 tuc:1; /* TCP/UDP Checksum Correct */ 274 u32 csum:16; 275 #else 276 u32 csum:16; 277 u32 tuc:1; /* TCP/UDP Checksum Correct */ 278 u32 udp:1; /* UDP packet */ 279 u32 tcp:1; /* TCP packet */ 280 u32 ipc:1; /* IP Checksum Correct */ 281 u32 v6:1; /* IPv6 */ 282 u32 v4:1; /* IPv4 */ 283 u32 frg:1; /* IP Fragment */ 284 u32 fcs:1; /* Frame CRC correct */ 285 u32 type:7; /* completion type */ 286 u32 gen:1; /* generation bit */ 287 #endif /* __BIG_ENDIAN_BITFIELD */ 288 }; 289 290 struct Vmxnet3_RxCompDescExt { 291 __le32 dword1; 292 u8 segCnt; /* Number of aggregated packets */ 293 u8 dupAckCnt; /* Number of duplicate Acks */ 294 __le16 tsDelta; /* TCP timestamp difference */ 295 __le32 dword2; 296 #ifdef __BIG_ENDIAN_BITFIELD 297 u32 gen:1; /* generation bit */ 298 u32 type:7; /* completion type */ 299 u32 fcs:1; /* Frame CRC correct */ 300 u32 frg:1; /* IP Fragment */ 301 u32 v4:1; /* IPv4 */ 302 u32 v6:1; /* IPv6 */ 303 u32 ipc:1; /* IP Checksum Correct */ 304 u32 tcp:1; /* TCP packet */ 305 u32 udp:1; /* UDP packet */ 306 u32 tuc:1; /* TCP/UDP Checksum Correct */ 307 u32 mss:16; 308 #else 309 u32 mss:16; 310 u32 tuc:1; /* TCP/UDP Checksum Correct */ 311 u32 udp:1; /* UDP packet */ 312 u32 tcp:1; /* TCP packet */ 313 u32 ipc:1; /* IP Checksum Correct */ 314 u32 v6:1; /* IPv6 */ 315 u32 v4:1; /* IPv4 */ 316 u32 frg:1; /* IP Fragment */ 317 u32 fcs:1; /* Frame CRC correct */ 318 u32 type:7; /* completion type */ 319 u32 gen:1; /* generation bit */ 320 #endif /* __BIG_ENDIAN_BITFIELD */ 321 }; 322 323 324 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */ 325 #define VMXNET3_RCD_TUC_SHIFT 16 326 #define VMXNET3_RCD_IPC_SHIFT 19 327 328 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */ 329 #define VMXNET3_RCD_TYPE_SHIFT 56 330 #define VMXNET3_RCD_GEN_SHIFT 63 331 332 /* csum OK for TCP/UDP pkts over IP */ 333 #define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \ 334 1 << VMXNET3_RCD_IPC_SHIFT) 335 #define VMXNET3_TXD_GEN_SIZE 1 336 #define VMXNET3_TXD_EOP_SIZE 1 337 338 /* value of RxCompDesc.rssType */ 339 enum { 340 VMXNET3_RCD_RSS_TYPE_NONE = 0, 341 VMXNET3_RCD_RSS_TYPE_IPV4 = 1, 342 VMXNET3_RCD_RSS_TYPE_TCPIPV4 = 2, 343 VMXNET3_RCD_RSS_TYPE_IPV6 = 3, 344 VMXNET3_RCD_RSS_TYPE_TCPIPV6 = 4, 345 }; 346 347 348 /* a union for accessing all cmd/completion descriptors */ 349 union Vmxnet3_GenericDesc { 350 __le64 qword[2]; 351 __le32 dword[4]; 352 __le16 word[8]; 353 struct Vmxnet3_TxDesc txd; 354 struct Vmxnet3_RxDesc rxd; 355 struct Vmxnet3_TxCompDesc tcd; 356 struct Vmxnet3_RxCompDesc rcd; 357 struct Vmxnet3_RxCompDescExt rcdExt; 358 }; 359 360 #define VMXNET3_INIT_GEN 1 361 362 /* Max size of a single tx buffer */ 363 #define VMXNET3_MAX_TX_BUF_SIZE (1 << 14) 364 365 /* # of tx desc needed for a tx buffer size */ 366 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \ 367 VMXNET3_MAX_TX_BUF_SIZE) 368 369 /* max # of tx descs for a non-tso pkt */ 370 #define VMXNET3_MAX_TXD_PER_PKT 16 371 372 /* Max size of a single rx buffer */ 373 #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1) 374 /* Minimum size of a type 0 buffer */ 375 #define VMXNET3_MIN_T0_BUF_SIZE 128 376 #define VMXNET3_MAX_CSUM_OFFSET 1024 377 378 /* Ring base address alignment */ 379 #define VMXNET3_RING_BA_ALIGN 512 380 #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1) 381 382 /* Ring size must be a multiple of 32 */ 383 #define VMXNET3_RING_SIZE_ALIGN 32 384 #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1) 385 386 /* Tx Data Ring buffer size must be a multiple of 64 */ 387 #define VMXNET3_TXDATA_DESC_SIZE_ALIGN 64 388 #define VMXNET3_TXDATA_DESC_SIZE_MASK (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1) 389 390 /* Rx Data Ring buffer size must be a multiple of 64 */ 391 #define VMXNET3_RXDATA_DESC_SIZE_ALIGN 64 392 #define VMXNET3_RXDATA_DESC_SIZE_MASK (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1) 393 394 /* Max ring size */ 395 #define VMXNET3_TX_RING_MAX_SIZE 4096 396 #define VMXNET3_TC_RING_MAX_SIZE 4096 397 #define VMXNET3_RX_RING_MAX_SIZE 4096 398 #define VMXNET3_RX_RING2_MAX_SIZE 4096 399 #define VMXNET3_RC_RING_MAX_SIZE 8192 400 401 #define VMXNET3_TXDATA_DESC_MIN_SIZE 128 402 #define VMXNET3_TXDATA_DESC_MAX_SIZE 2048 403 404 #define VMXNET3_RXDATA_DESC_MAX_SIZE 2048 405 406 /* a list of reasons for queue stop */ 407 408 enum { 409 VMXNET3_ERR_NOEOP = 0x80000000, /* cannot find the EOP desc of a pkt */ 410 VMXNET3_ERR_TXD_REUSE = 0x80000001, /* reuse TxDesc before tx completion */ 411 VMXNET3_ERR_BIG_PKT = 0x80000002, /* too many TxDesc for a pkt */ 412 VMXNET3_ERR_DESC_NOT_SPT = 0x80000003, /* descriptor type not supported */ 413 VMXNET3_ERR_SMALL_BUF = 0x80000004, /* type 0 buffer too small */ 414 VMXNET3_ERR_STRESS = 0x80000005, /* stress option firing in vmkernel */ 415 VMXNET3_ERR_SWITCH = 0x80000006, /* mode switch failure */ 416 VMXNET3_ERR_TXD_INVALID = 0x80000007, /* invalid TxDesc */ 417 }; 418 419 /* completion descriptor types */ 420 #define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */ 421 #define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */ 422 #define VMXNET3_CDTYPE_RXCOMP_LRO 4 /* Rx Completion Descriptor for LRO */ 423 424 enum { 425 VMXNET3_GOS_BITS_UNK = 0, /* unknown */ 426 VMXNET3_GOS_BITS_32 = 1, 427 VMXNET3_GOS_BITS_64 = 2, 428 }; 429 430 #define VMXNET3_GOS_TYPE_LINUX 1 431 432 433 struct Vmxnet3_GOSInfo { 434 #ifdef __BIG_ENDIAN_BITFIELD 435 u32 gosMisc:10; /* other info about gos */ 436 u32 gosVer:16; /* gos version */ 437 u32 gosType:4; /* which guest */ 438 u32 gosBits:2; /* 32-bit or 64-bit? */ 439 #else 440 u32 gosBits:2; /* 32-bit or 64-bit? */ 441 u32 gosType:4; /* which guest */ 442 u32 gosVer:16; /* gos version */ 443 u32 gosMisc:10; /* other info about gos */ 444 #endif /* __BIG_ENDIAN_BITFIELD */ 445 }; 446 447 struct Vmxnet3_DriverInfo { 448 __le32 version; 449 struct Vmxnet3_GOSInfo gos; 450 __le32 vmxnet3RevSpt; 451 __le32 uptVerSpt; 452 }; 453 454 455 #define VMXNET3_REV1_MAGIC 3133079265u 456 457 /* 458 * QueueDescPA must be 128 bytes aligned. It points to an array of 459 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc. 460 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by 461 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively. 462 */ 463 #define VMXNET3_QUEUE_DESC_ALIGN 128 464 465 466 struct Vmxnet3_MiscConf { 467 struct Vmxnet3_DriverInfo driverInfo; 468 __le64 uptFeatures; 469 __le64 ddPA; /* driver data PA */ 470 __le64 queueDescPA; /* queue descriptor table PA */ 471 __le32 ddLen; /* driver data len */ 472 __le32 queueDescLen; /* queue desc. table len in bytes */ 473 __le32 mtu; 474 __le16 maxNumRxSG; 475 u8 numTxQueues; 476 u8 numRxQueues; 477 __le32 reserved[4]; 478 }; 479 480 481 struct Vmxnet3_TxQueueConf { 482 __le64 txRingBasePA; 483 __le64 dataRingBasePA; 484 __le64 compRingBasePA; 485 __le64 ddPA; /* driver data */ 486 __le64 reserved; 487 __le32 txRingSize; /* # of tx desc */ 488 __le32 dataRingSize; /* # of data desc */ 489 __le32 compRingSize; /* # of comp desc */ 490 __le32 ddLen; /* size of driver data */ 491 u8 intrIdx; 492 u8 _pad1[1]; 493 __le16 txDataRingDescSize; 494 u8 _pad2[4]; 495 }; 496 497 498 struct Vmxnet3_RxQueueConf { 499 __le64 rxRingBasePA[2]; 500 __le64 compRingBasePA; 501 __le64 ddPA; /* driver data */ 502 __le64 rxDataRingBasePA; 503 __le32 rxRingSize[2]; /* # of rx desc */ 504 __le32 compRingSize; /* # of rx comp desc */ 505 __le32 ddLen; /* size of driver data */ 506 u8 intrIdx; 507 u8 _pad1[1]; 508 __le16 rxDataRingDescSize; /* size of rx data ring buffer */ 509 u8 _pad2[4]; 510 }; 511 512 513 enum vmxnet3_intr_mask_mode { 514 VMXNET3_IMM_AUTO = 0, 515 VMXNET3_IMM_ACTIVE = 1, 516 VMXNET3_IMM_LAZY = 2 517 }; 518 519 enum vmxnet3_intr_type { 520 VMXNET3_IT_AUTO = 0, 521 VMXNET3_IT_INTX = 1, 522 VMXNET3_IT_MSI = 2, 523 VMXNET3_IT_MSIX = 3 524 }; 525 526 #define VMXNET3_MAX_TX_QUEUES 8 527 #define VMXNET3_MAX_RX_QUEUES 16 528 /* addition 1 for events */ 529 #define VMXNET3_MAX_INTRS 25 530 531 /* value of intrCtrl */ 532 #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */ 533 534 535 struct Vmxnet3_IntrConf { 536 bool autoMask; 537 u8 numIntrs; /* # of interrupts */ 538 u8 eventIntrIdx; 539 u8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for 540 * each intr */ 541 __le32 intrCtrl; 542 __le32 reserved[2]; 543 }; 544 545 /* one bit per VLAN ID, the size is in the units of u32 */ 546 #define VMXNET3_VFT_SIZE (4096 / (sizeof(u32) * 8)) 547 548 549 struct Vmxnet3_QueueStatus { 550 bool stopped; 551 u8 _pad[3]; 552 __le32 error; 553 }; 554 555 556 struct Vmxnet3_TxQueueCtrl { 557 __le32 txNumDeferred; 558 __le32 txThreshold; 559 __le64 reserved; 560 }; 561 562 563 struct Vmxnet3_RxQueueCtrl { 564 bool updateRxProd; 565 u8 _pad[7]; 566 __le64 reserved; 567 }; 568 569 enum { 570 VMXNET3_RXM_UCAST = 0x01, /* unicast only */ 571 VMXNET3_RXM_MCAST = 0x02, /* multicast passing the filters */ 572 VMXNET3_RXM_BCAST = 0x04, /* broadcast only */ 573 VMXNET3_RXM_ALL_MULTI = 0x08, /* all multicast */ 574 VMXNET3_RXM_PROMISC = 0x10 /* promiscuous */ 575 }; 576 577 struct Vmxnet3_RxFilterConf { 578 __le32 rxMode; /* VMXNET3_RXM_xxx */ 579 __le16 mfTableLen; /* size of the multicast filter table */ 580 __le16 _pad1; 581 __le64 mfTablePA; /* PA of the multicast filters table */ 582 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */ 583 }; 584 585 586 #define VMXNET3_PM_MAX_FILTERS 6 587 #define VMXNET3_PM_MAX_PATTERN_SIZE 128 588 #define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8) 589 590 #define VMXNET3_PM_WAKEUP_MAGIC cpu_to_le16(0x01) /* wake up on magic pkts */ 591 #define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02) /* wake up on pkts matching 592 * filters */ 593 594 595 struct Vmxnet3_PM_PktFilter { 596 u8 maskSize; 597 u8 patternSize; 598 u8 mask[VMXNET3_PM_MAX_MASK_SIZE]; 599 u8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE]; 600 u8 pad[6]; 601 }; 602 603 604 struct Vmxnet3_PMConf { 605 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */ 606 u8 numFilters; 607 u8 pad[5]; 608 struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS]; 609 }; 610 611 612 struct Vmxnet3_VariableLenConfDesc { 613 __le32 confVer; 614 __le32 confLen; 615 __le64 confPA; 616 }; 617 618 619 struct Vmxnet3_TxQueueDesc { 620 struct Vmxnet3_TxQueueCtrl ctrl; 621 struct Vmxnet3_TxQueueConf conf; 622 623 /* Driver read after a GET command */ 624 struct Vmxnet3_QueueStatus status; 625 struct UPT1_TxStats stats; 626 u8 _pad[88]; /* 128 aligned */ 627 }; 628 629 630 struct Vmxnet3_RxQueueDesc { 631 struct Vmxnet3_RxQueueCtrl ctrl; 632 struct Vmxnet3_RxQueueConf conf; 633 /* Driver read after a GET commad */ 634 struct Vmxnet3_QueueStatus status; 635 struct UPT1_RxStats stats; 636 u8 __pad[88]; /* 128 aligned */ 637 }; 638 639 struct Vmxnet3_SetPolling { 640 u8 enablePolling; 641 }; 642 643 #define VMXNET3_COAL_STATIC_MAX_DEPTH 128 644 #define VMXNET3_COAL_RBC_MIN_RATE 100 645 #define VMXNET3_COAL_RBC_MAX_RATE 100000 646 647 enum Vmxnet3_CoalesceMode { 648 VMXNET3_COALESCE_DISABLED = 0, 649 VMXNET3_COALESCE_ADAPT = 1, 650 VMXNET3_COALESCE_STATIC = 2, 651 VMXNET3_COALESCE_RBC = 3 652 }; 653 654 struct Vmxnet3_CoalesceRbc { 655 u32 rbc_rate; 656 }; 657 658 struct Vmxnet3_CoalesceStatic { 659 u32 tx_depth; 660 u32 tx_comp_depth; 661 u32 rx_depth; 662 }; 663 664 struct Vmxnet3_CoalesceScheme { 665 enum Vmxnet3_CoalesceMode coalMode; 666 union { 667 struct Vmxnet3_CoalesceRbc coalRbc; 668 struct Vmxnet3_CoalesceStatic coalStatic; 669 } coalPara; 670 }; 671 672 struct Vmxnet3_MemoryRegion { 673 __le64 startPA; 674 __le32 length; 675 __le16 txQueueBits; 676 __le16 rxQueueBits; 677 }; 678 679 #define MAX_MEMORY_REGION_PER_QUEUE 16 680 #define MAX_MEMORY_REGION_PER_DEVICE 256 681 682 struct Vmxnet3_MemRegs { 683 __le16 numRegs; 684 __le16 pad[3]; 685 struct Vmxnet3_MemoryRegion memRegs[1]; 686 }; 687 688 /* If the command data <= 16 bytes, use the shared memory directly. 689 * otherwise, use variable length configuration descriptor. 690 */ 691 union Vmxnet3_CmdInfo { 692 struct Vmxnet3_VariableLenConfDesc varConf; 693 struct Vmxnet3_SetPolling setPolling; 694 __le64 data[2]; 695 }; 696 697 struct Vmxnet3_DSDevRead { 698 /* read-only region for device, read by dev in response to a SET cmd */ 699 struct Vmxnet3_MiscConf misc; 700 struct Vmxnet3_IntrConf intrConf; 701 struct Vmxnet3_RxFilterConf rxFilterConf; 702 struct Vmxnet3_VariableLenConfDesc rssConfDesc; 703 struct Vmxnet3_VariableLenConfDesc pmConfDesc; 704 struct Vmxnet3_VariableLenConfDesc pluginConfDesc; 705 }; 706 707 /* All structures in DriverShared are padded to multiples of 8 bytes */ 708 struct Vmxnet3_DriverShared { 709 __le32 magic; 710 /* make devRead start at 64bit boundaries */ 711 __le32 pad; 712 struct Vmxnet3_DSDevRead devRead; 713 __le32 ecr; 714 __le32 reserved; 715 union { 716 __le32 reserved1[4]; 717 union Vmxnet3_CmdInfo cmdInfo; /* only valid in the context of 718 * executing the relevant 719 * command 720 */ 721 } cu; 722 }; 723 724 725 #define VMXNET3_ECR_RQERR (1 << 0) 726 #define VMXNET3_ECR_TQERR (1 << 1) 727 #define VMXNET3_ECR_LINK (1 << 2) 728 #define VMXNET3_ECR_DIC (1 << 3) 729 #define VMXNET3_ECR_DEBUG (1 << 4) 730 731 /* flip the gen bit of a ring */ 732 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1) 733 734 /* only use this if moving the idx won't affect the gen bit */ 735 #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \ 736 do {\ 737 (idx)++;\ 738 if (unlikely((idx) == (ring_size))) {\ 739 (idx) = 0;\ 740 } \ 741 } while (0) 742 743 #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \ 744 (vfTable[vid >> 5] |= (1 << (vid & 31))) 745 #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \ 746 (vfTable[vid >> 5] &= ~(1 << (vid & 31))) 747 748 #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \ 749 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0) 750 751 #define VMXNET3_MAX_MTU 9000 752 #define VMXNET3_MIN_MTU 60 753 754 #define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */ 755 #define VMXNET3_LINK_DOWN 0 756 757 #endif /* _VMXNET3_DEFS_H_ */ 758