1 /*************************************************************************** 2 * 3 * Copyright (C) 2007-2010 SMSC 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 18 * 19 *****************************************************************************/ 20 21 #include <linux/module.h> 22 #include <linux/kmod.h> 23 #include <linux/init.h> 24 #include <linux/netdevice.h> 25 #include <linux/etherdevice.h> 26 #include <linux/ethtool.h> 27 #include <linux/mii.h> 28 #include <linux/usb.h> 29 #include <linux/crc32.h> 30 #include <linux/usb/usbnet.h> 31 #include <linux/slab.h> 32 #include "smsc75xx.h" 33 34 #define SMSC_CHIPNAME "smsc75xx" 35 #define SMSC_DRIVER_VERSION "1.0.0" 36 #define HS_USB_PKT_SIZE (512) 37 #define FS_USB_PKT_SIZE (64) 38 #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE) 39 #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE) 40 #define DEFAULT_BULK_IN_DELAY (0x00002000) 41 #define MAX_SINGLE_PACKET_SIZE (9000) 42 #define LAN75XX_EEPROM_MAGIC (0x7500) 43 #define EEPROM_MAC_OFFSET (0x01) 44 #define DEFAULT_TX_CSUM_ENABLE (true) 45 #define DEFAULT_RX_CSUM_ENABLE (true) 46 #define DEFAULT_TSO_ENABLE (true) 47 #define SMSC75XX_INTERNAL_PHY_ID (1) 48 #define SMSC75XX_TX_OVERHEAD (8) 49 #define MAX_RX_FIFO_SIZE (20 * 1024) 50 #define MAX_TX_FIFO_SIZE (12 * 1024) 51 #define USB_VENDOR_ID_SMSC (0x0424) 52 #define USB_PRODUCT_ID_LAN7500 (0x7500) 53 #define USB_PRODUCT_ID_LAN7505 (0x7505) 54 #define RXW_PADDING 2 55 #define SUPPORTED_WAKE (WAKE_MAGIC) 56 57 #define check_warn(ret, fmt, args...) \ 58 ({ if (ret < 0) netdev_warn(dev->net, fmt, ##args); }) 59 60 #define check_warn_return(ret, fmt, args...) \ 61 ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); return ret; } }) 62 63 #define check_warn_goto_done(ret, fmt, args...) \ 64 ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); goto done; } }) 65 66 struct smsc75xx_priv { 67 struct usbnet *dev; 68 u32 rfe_ctl; 69 u32 wolopts; 70 u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN]; 71 struct mutex dataport_mutex; 72 spinlock_t rfe_ctl_lock; 73 struct work_struct set_multicast; 74 }; 75 76 struct usb_context { 77 struct usb_ctrlrequest req; 78 struct usbnet *dev; 79 }; 80 81 static bool turbo_mode = true; 82 module_param(turbo_mode, bool, 0644); 83 MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction"); 84 85 static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index, 86 u32 *data) 87 { 88 u32 *buf = kmalloc(4, GFP_KERNEL); 89 int ret; 90 91 BUG_ON(!dev); 92 93 if (!buf) 94 return -ENOMEM; 95 96 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), 97 USB_VENDOR_REQUEST_READ_REGISTER, 98 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 99 00, index, buf, 4, USB_CTRL_GET_TIMEOUT); 100 101 if (unlikely(ret < 0)) 102 netdev_warn(dev->net, 103 "Failed to read reg index 0x%08x: %d", index, ret); 104 105 le32_to_cpus(buf); 106 *data = *buf; 107 kfree(buf); 108 109 return ret; 110 } 111 112 static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index, 113 u32 data) 114 { 115 u32 *buf = kmalloc(4, GFP_KERNEL); 116 int ret; 117 118 BUG_ON(!dev); 119 120 if (!buf) 121 return -ENOMEM; 122 123 *buf = data; 124 cpu_to_le32s(buf); 125 126 ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), 127 USB_VENDOR_REQUEST_WRITE_REGISTER, 128 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 129 00, index, buf, 4, USB_CTRL_SET_TIMEOUT); 130 131 if (unlikely(ret < 0)) 132 netdev_warn(dev->net, 133 "Failed to write reg index 0x%08x: %d", index, ret); 134 135 kfree(buf); 136 137 return ret; 138 } 139 140 static int smsc75xx_set_feature(struct usbnet *dev, u32 feature) 141 { 142 if (WARN_ON_ONCE(!dev)) 143 return -EINVAL; 144 145 cpu_to_le32s(&feature); 146 147 return usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), 148 USB_REQ_SET_FEATURE, USB_RECIP_DEVICE, feature, 0, NULL, 0, 149 USB_CTRL_SET_TIMEOUT); 150 } 151 152 static int smsc75xx_clear_feature(struct usbnet *dev, u32 feature) 153 { 154 if (WARN_ON_ONCE(!dev)) 155 return -EINVAL; 156 157 cpu_to_le32s(&feature); 158 159 return usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), 160 USB_REQ_CLEAR_FEATURE, USB_RECIP_DEVICE, feature, 0, NULL, 0, 161 USB_CTRL_SET_TIMEOUT); 162 } 163 164 /* Loop until the read is completed with timeout 165 * called with phy_mutex held */ 166 static int smsc75xx_phy_wait_not_busy(struct usbnet *dev) 167 { 168 unsigned long start_time = jiffies; 169 u32 val; 170 int ret; 171 172 do { 173 ret = smsc75xx_read_reg(dev, MII_ACCESS, &val); 174 check_warn_return(ret, "Error reading MII_ACCESS"); 175 176 if (!(val & MII_ACCESS_BUSY)) 177 return 0; 178 } while (!time_after(jiffies, start_time + HZ)); 179 180 return -EIO; 181 } 182 183 static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx) 184 { 185 struct usbnet *dev = netdev_priv(netdev); 186 u32 val, addr; 187 int ret; 188 189 mutex_lock(&dev->phy_mutex); 190 191 /* confirm MII not busy */ 192 ret = smsc75xx_phy_wait_not_busy(dev); 193 check_warn_goto_done(ret, "MII is busy in smsc75xx_mdio_read"); 194 195 /* set the address, index & direction (read from PHY) */ 196 phy_id &= dev->mii.phy_id_mask; 197 idx &= dev->mii.reg_num_mask; 198 addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR) 199 | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR) 200 | MII_ACCESS_READ | MII_ACCESS_BUSY; 201 ret = smsc75xx_write_reg(dev, MII_ACCESS, addr); 202 check_warn_goto_done(ret, "Error writing MII_ACCESS"); 203 204 ret = smsc75xx_phy_wait_not_busy(dev); 205 check_warn_goto_done(ret, "Timed out reading MII reg %02X", idx); 206 207 ret = smsc75xx_read_reg(dev, MII_DATA, &val); 208 check_warn_goto_done(ret, "Error reading MII_DATA"); 209 210 ret = (u16)(val & 0xFFFF); 211 212 done: 213 mutex_unlock(&dev->phy_mutex); 214 return ret; 215 } 216 217 static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx, 218 int regval) 219 { 220 struct usbnet *dev = netdev_priv(netdev); 221 u32 val, addr; 222 int ret; 223 224 mutex_lock(&dev->phy_mutex); 225 226 /* confirm MII not busy */ 227 ret = smsc75xx_phy_wait_not_busy(dev); 228 check_warn_goto_done(ret, "MII is busy in smsc75xx_mdio_write"); 229 230 val = regval; 231 ret = smsc75xx_write_reg(dev, MII_DATA, val); 232 check_warn_goto_done(ret, "Error writing MII_DATA"); 233 234 /* set the address, index & direction (write to PHY) */ 235 phy_id &= dev->mii.phy_id_mask; 236 idx &= dev->mii.reg_num_mask; 237 addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR) 238 | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR) 239 | MII_ACCESS_WRITE | MII_ACCESS_BUSY; 240 ret = smsc75xx_write_reg(dev, MII_ACCESS, addr); 241 check_warn_goto_done(ret, "Error writing MII_ACCESS"); 242 243 ret = smsc75xx_phy_wait_not_busy(dev); 244 check_warn_goto_done(ret, "Timed out writing MII reg %02X", idx); 245 246 done: 247 mutex_unlock(&dev->phy_mutex); 248 } 249 250 static int smsc75xx_wait_eeprom(struct usbnet *dev) 251 { 252 unsigned long start_time = jiffies; 253 u32 val; 254 int ret; 255 256 do { 257 ret = smsc75xx_read_reg(dev, E2P_CMD, &val); 258 check_warn_return(ret, "Error reading E2P_CMD"); 259 260 if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT)) 261 break; 262 udelay(40); 263 } while (!time_after(jiffies, start_time + HZ)); 264 265 if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) { 266 netdev_warn(dev->net, "EEPROM read operation timeout"); 267 return -EIO; 268 } 269 270 return 0; 271 } 272 273 static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev) 274 { 275 unsigned long start_time = jiffies; 276 u32 val; 277 int ret; 278 279 do { 280 ret = smsc75xx_read_reg(dev, E2P_CMD, &val); 281 check_warn_return(ret, "Error reading E2P_CMD"); 282 283 if (!(val & E2P_CMD_BUSY)) 284 return 0; 285 286 udelay(40); 287 } while (!time_after(jiffies, start_time + HZ)); 288 289 netdev_warn(dev->net, "EEPROM is busy"); 290 return -EIO; 291 } 292 293 static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length, 294 u8 *data) 295 { 296 u32 val; 297 int i, ret; 298 299 BUG_ON(!dev); 300 BUG_ON(!data); 301 302 ret = smsc75xx_eeprom_confirm_not_busy(dev); 303 if (ret) 304 return ret; 305 306 for (i = 0; i < length; i++) { 307 val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR); 308 ret = smsc75xx_write_reg(dev, E2P_CMD, val); 309 check_warn_return(ret, "Error writing E2P_CMD"); 310 311 ret = smsc75xx_wait_eeprom(dev); 312 if (ret < 0) 313 return ret; 314 315 ret = smsc75xx_read_reg(dev, E2P_DATA, &val); 316 check_warn_return(ret, "Error reading E2P_DATA"); 317 318 data[i] = val & 0xFF; 319 offset++; 320 } 321 322 return 0; 323 } 324 325 static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length, 326 u8 *data) 327 { 328 u32 val; 329 int i, ret; 330 331 BUG_ON(!dev); 332 BUG_ON(!data); 333 334 ret = smsc75xx_eeprom_confirm_not_busy(dev); 335 if (ret) 336 return ret; 337 338 /* Issue write/erase enable command */ 339 val = E2P_CMD_BUSY | E2P_CMD_EWEN; 340 ret = smsc75xx_write_reg(dev, E2P_CMD, val); 341 check_warn_return(ret, "Error writing E2P_CMD"); 342 343 ret = smsc75xx_wait_eeprom(dev); 344 if (ret < 0) 345 return ret; 346 347 for (i = 0; i < length; i++) { 348 349 /* Fill data register */ 350 val = data[i]; 351 ret = smsc75xx_write_reg(dev, E2P_DATA, val); 352 check_warn_return(ret, "Error writing E2P_DATA"); 353 354 /* Send "write" command */ 355 val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR); 356 ret = smsc75xx_write_reg(dev, E2P_CMD, val); 357 check_warn_return(ret, "Error writing E2P_CMD"); 358 359 ret = smsc75xx_wait_eeprom(dev); 360 if (ret < 0) 361 return ret; 362 363 offset++; 364 } 365 366 return 0; 367 } 368 369 static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev) 370 { 371 int i, ret; 372 373 for (i = 0; i < 100; i++) { 374 u32 dp_sel; 375 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel); 376 check_warn_return(ret, "Error reading DP_SEL"); 377 378 if (dp_sel & DP_SEL_DPRDY) 379 return 0; 380 381 udelay(40); 382 } 383 384 netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out"); 385 386 return -EIO; 387 } 388 389 static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr, 390 u32 length, u32 *buf) 391 { 392 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]); 393 u32 dp_sel; 394 int i, ret; 395 396 mutex_lock(&pdata->dataport_mutex); 397 398 ret = smsc75xx_dataport_wait_not_busy(dev); 399 check_warn_goto_done(ret, "smsc75xx_dataport_write busy on entry"); 400 401 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel); 402 check_warn_goto_done(ret, "Error reading DP_SEL"); 403 404 dp_sel &= ~DP_SEL_RSEL; 405 dp_sel |= ram_select; 406 ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel); 407 check_warn_goto_done(ret, "Error writing DP_SEL"); 408 409 for (i = 0; i < length; i++) { 410 ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i); 411 check_warn_goto_done(ret, "Error writing DP_ADDR"); 412 413 ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]); 414 check_warn_goto_done(ret, "Error writing DP_DATA"); 415 416 ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE); 417 check_warn_goto_done(ret, "Error writing DP_CMD"); 418 419 ret = smsc75xx_dataport_wait_not_busy(dev); 420 check_warn_goto_done(ret, "smsc75xx_dataport_write timeout"); 421 } 422 423 done: 424 mutex_unlock(&pdata->dataport_mutex); 425 return ret; 426 } 427 428 /* returns hash bit number for given MAC address */ 429 static u32 smsc75xx_hash(char addr[ETH_ALEN]) 430 { 431 return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff; 432 } 433 434 static void smsc75xx_deferred_multicast_write(struct work_struct *param) 435 { 436 struct smsc75xx_priv *pdata = 437 container_of(param, struct smsc75xx_priv, set_multicast); 438 struct usbnet *dev = pdata->dev; 439 int ret; 440 441 netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x", 442 pdata->rfe_ctl); 443 444 smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN, 445 DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table); 446 447 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl); 448 check_warn(ret, "Error writing RFE_CRL"); 449 } 450 451 static void smsc75xx_set_multicast(struct net_device *netdev) 452 { 453 struct usbnet *dev = netdev_priv(netdev); 454 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]); 455 unsigned long flags; 456 int i; 457 458 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags); 459 460 pdata->rfe_ctl &= 461 ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF); 462 pdata->rfe_ctl |= RFE_CTL_AB; 463 464 for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++) 465 pdata->multicast_hash_table[i] = 0; 466 467 if (dev->net->flags & IFF_PROMISC) { 468 netif_dbg(dev, drv, dev->net, "promiscuous mode enabled"); 469 pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU; 470 } else if (dev->net->flags & IFF_ALLMULTI) { 471 netif_dbg(dev, drv, dev->net, "receive all multicast enabled"); 472 pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF; 473 } else if (!netdev_mc_empty(dev->net)) { 474 struct netdev_hw_addr *ha; 475 476 netif_dbg(dev, drv, dev->net, "receive multicast hash filter"); 477 478 pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF; 479 480 netdev_for_each_mc_addr(ha, netdev) { 481 u32 bitnum = smsc75xx_hash(ha->addr); 482 pdata->multicast_hash_table[bitnum / 32] |= 483 (1 << (bitnum % 32)); 484 } 485 } else { 486 netif_dbg(dev, drv, dev->net, "receive own packets only"); 487 pdata->rfe_ctl |= RFE_CTL_DPF; 488 } 489 490 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags); 491 492 /* defer register writes to a sleepable context */ 493 schedule_work(&pdata->set_multicast); 494 } 495 496 static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex, 497 u16 lcladv, u16 rmtadv) 498 { 499 u32 flow = 0, fct_flow = 0; 500 int ret; 501 502 if (duplex == DUPLEX_FULL) { 503 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); 504 505 if (cap & FLOW_CTRL_TX) { 506 flow = (FLOW_TX_FCEN | 0xFFFF); 507 /* set fct_flow thresholds to 20% and 80% */ 508 fct_flow = (8 << 8) | 32; 509 } 510 511 if (cap & FLOW_CTRL_RX) 512 flow |= FLOW_RX_FCEN; 513 514 netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s", 515 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"), 516 (cap & FLOW_CTRL_TX ? "enabled" : "disabled")); 517 } else { 518 netif_dbg(dev, link, dev->net, "half duplex"); 519 } 520 521 ret = smsc75xx_write_reg(dev, FLOW, flow); 522 check_warn_return(ret, "Error writing FLOW"); 523 524 ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow); 525 check_warn_return(ret, "Error writing FCT_FLOW"); 526 527 return 0; 528 } 529 530 static int smsc75xx_link_reset(struct usbnet *dev) 531 { 532 struct mii_if_info *mii = &dev->mii; 533 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 534 u16 lcladv, rmtadv; 535 int ret; 536 537 /* write to clear phy interrupt status */ 538 smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC, 539 PHY_INT_SRC_CLEAR_ALL); 540 541 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL); 542 check_warn_return(ret, "Error writing INT_STS"); 543 544 mii_check_media(mii, 1, 1); 545 mii_ethtool_gset(&dev->mii, &ecmd); 546 lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE); 547 rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA); 548 549 netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x" 550 " rmtadv: %04x", ethtool_cmd_speed(&ecmd), 551 ecmd.duplex, lcladv, rmtadv); 552 553 return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv); 554 } 555 556 static void smsc75xx_status(struct usbnet *dev, struct urb *urb) 557 { 558 u32 intdata; 559 560 if (urb->actual_length != 4) { 561 netdev_warn(dev->net, 562 "unexpected urb length %d", urb->actual_length); 563 return; 564 } 565 566 memcpy(&intdata, urb->transfer_buffer, 4); 567 le32_to_cpus(&intdata); 568 569 netif_dbg(dev, link, dev->net, "intdata: 0x%08X", intdata); 570 571 if (intdata & INT_ENP_PHY_INT) 572 usbnet_defer_kevent(dev, EVENT_LINK_RESET); 573 else 574 netdev_warn(dev->net, 575 "unexpected interrupt, intdata=0x%08X", intdata); 576 } 577 578 static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net) 579 { 580 return MAX_EEPROM_SIZE; 581 } 582 583 static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev, 584 struct ethtool_eeprom *ee, u8 *data) 585 { 586 struct usbnet *dev = netdev_priv(netdev); 587 588 ee->magic = LAN75XX_EEPROM_MAGIC; 589 590 return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data); 591 } 592 593 static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev, 594 struct ethtool_eeprom *ee, u8 *data) 595 { 596 struct usbnet *dev = netdev_priv(netdev); 597 598 if (ee->magic != LAN75XX_EEPROM_MAGIC) { 599 netdev_warn(dev->net, 600 "EEPROM: magic value mismatch: 0x%x", ee->magic); 601 return -EINVAL; 602 } 603 604 return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data); 605 } 606 607 static void smsc75xx_ethtool_get_wol(struct net_device *net, 608 struct ethtool_wolinfo *wolinfo) 609 { 610 struct usbnet *dev = netdev_priv(net); 611 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]); 612 613 wolinfo->supported = SUPPORTED_WAKE; 614 wolinfo->wolopts = pdata->wolopts; 615 } 616 617 static int smsc75xx_ethtool_set_wol(struct net_device *net, 618 struct ethtool_wolinfo *wolinfo) 619 { 620 struct usbnet *dev = netdev_priv(net); 621 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]); 622 623 pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE; 624 return 0; 625 } 626 627 static const struct ethtool_ops smsc75xx_ethtool_ops = { 628 .get_link = usbnet_get_link, 629 .nway_reset = usbnet_nway_reset, 630 .get_drvinfo = usbnet_get_drvinfo, 631 .get_msglevel = usbnet_get_msglevel, 632 .set_msglevel = usbnet_set_msglevel, 633 .get_settings = usbnet_get_settings, 634 .set_settings = usbnet_set_settings, 635 .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len, 636 .get_eeprom = smsc75xx_ethtool_get_eeprom, 637 .set_eeprom = smsc75xx_ethtool_set_eeprom, 638 .get_wol = smsc75xx_ethtool_get_wol, 639 .set_wol = smsc75xx_ethtool_set_wol, 640 }; 641 642 static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 643 { 644 struct usbnet *dev = netdev_priv(netdev); 645 646 if (!netif_running(netdev)) 647 return -EINVAL; 648 649 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); 650 } 651 652 static void smsc75xx_init_mac_address(struct usbnet *dev) 653 { 654 /* try reading mac address from EEPROM */ 655 if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, 656 dev->net->dev_addr) == 0) { 657 if (is_valid_ether_addr(dev->net->dev_addr)) { 658 /* eeprom values are valid so use them */ 659 netif_dbg(dev, ifup, dev->net, 660 "MAC address read from EEPROM"); 661 return; 662 } 663 } 664 665 /* no eeprom, or eeprom values are invalid. generate random MAC */ 666 eth_hw_addr_random(dev->net); 667 netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr"); 668 } 669 670 static int smsc75xx_set_mac_address(struct usbnet *dev) 671 { 672 u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 | 673 dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24; 674 u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8; 675 676 int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi); 677 check_warn_return(ret, "Failed to write RX_ADDRH: %d", ret); 678 679 ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo); 680 check_warn_return(ret, "Failed to write RX_ADDRL: %d", ret); 681 682 addr_hi |= ADDR_FILTX_FB_VALID; 683 ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi); 684 check_warn_return(ret, "Failed to write ADDR_FILTX: %d", ret); 685 686 ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo); 687 check_warn_return(ret, "Failed to write ADDR_FILTX+4: %d", ret); 688 689 return 0; 690 } 691 692 static int smsc75xx_phy_initialize(struct usbnet *dev) 693 { 694 int bmcr, ret, timeout = 0; 695 696 /* Initialize MII structure */ 697 dev->mii.dev = dev->net; 698 dev->mii.mdio_read = smsc75xx_mdio_read; 699 dev->mii.mdio_write = smsc75xx_mdio_write; 700 dev->mii.phy_id_mask = 0x1f; 701 dev->mii.reg_num_mask = 0x1f; 702 dev->mii.supports_gmii = 1; 703 dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID; 704 705 /* reset phy and wait for reset to complete */ 706 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); 707 708 do { 709 msleep(10); 710 bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR); 711 check_warn_return(bmcr, "Error reading MII_BMCR"); 712 timeout++; 713 } while ((bmcr & BMCR_RESET) && (timeout < 100)); 714 715 if (timeout >= 100) { 716 netdev_warn(dev->net, "timeout on PHY Reset"); 717 return -EIO; 718 } 719 720 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 721 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP | 722 ADVERTISE_PAUSE_ASYM); 723 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000, 724 ADVERTISE_1000FULL); 725 726 /* read and write to clear phy interrupt status */ 727 ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC); 728 check_warn_return(ret, "Error reading PHY_INT_SRC"); 729 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff); 730 731 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK, 732 PHY_INT_MASK_DEFAULT); 733 mii_nway_restart(&dev->mii); 734 735 netif_dbg(dev, ifup, dev->net, "phy initialised successfully"); 736 return 0; 737 } 738 739 static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size) 740 { 741 int ret = 0; 742 u32 buf; 743 bool rxenabled; 744 745 ret = smsc75xx_read_reg(dev, MAC_RX, &buf); 746 check_warn_return(ret, "Failed to read MAC_RX: %d", ret); 747 748 rxenabled = ((buf & MAC_RX_RXEN) != 0); 749 750 if (rxenabled) { 751 buf &= ~MAC_RX_RXEN; 752 ret = smsc75xx_write_reg(dev, MAC_RX, buf); 753 check_warn_return(ret, "Failed to write MAC_RX: %d", ret); 754 } 755 756 /* add 4 to size for FCS */ 757 buf &= ~MAC_RX_MAX_SIZE; 758 buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE); 759 760 ret = smsc75xx_write_reg(dev, MAC_RX, buf); 761 check_warn_return(ret, "Failed to write MAC_RX: %d", ret); 762 763 if (rxenabled) { 764 buf |= MAC_RX_RXEN; 765 ret = smsc75xx_write_reg(dev, MAC_RX, buf); 766 check_warn_return(ret, "Failed to write MAC_RX: %d", ret); 767 } 768 769 return 0; 770 } 771 772 static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu) 773 { 774 struct usbnet *dev = netdev_priv(netdev); 775 776 int ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu); 777 check_warn_return(ret, "Failed to set mac rx frame length"); 778 779 return usbnet_change_mtu(netdev, new_mtu); 780 } 781 782 /* Enable or disable Rx checksum offload engine */ 783 static int smsc75xx_set_features(struct net_device *netdev, 784 netdev_features_t features) 785 { 786 struct usbnet *dev = netdev_priv(netdev); 787 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]); 788 unsigned long flags; 789 int ret; 790 791 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags); 792 793 if (features & NETIF_F_RXCSUM) 794 pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM; 795 else 796 pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM); 797 798 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags); 799 /* it's racing here! */ 800 801 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl); 802 check_warn_return(ret, "Error writing RFE_CTL"); 803 804 return 0; 805 } 806 807 static int smsc75xx_wait_ready(struct usbnet *dev) 808 { 809 int timeout = 0; 810 811 do { 812 u32 buf; 813 int ret = smsc75xx_read_reg(dev, PMT_CTL, &buf); 814 check_warn_return(ret, "Failed to read PMT_CTL: %d", ret); 815 816 if (buf & PMT_CTL_DEV_RDY) 817 return 0; 818 819 msleep(10); 820 timeout++; 821 } while (timeout < 100); 822 823 netdev_warn(dev->net, "timeout waiting for device ready"); 824 return -EIO; 825 } 826 827 static int smsc75xx_reset(struct usbnet *dev) 828 { 829 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]); 830 u32 buf; 831 int ret = 0, timeout; 832 833 netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset"); 834 835 ret = smsc75xx_wait_ready(dev); 836 check_warn_return(ret, "device not ready in smsc75xx_reset"); 837 838 ret = smsc75xx_read_reg(dev, HW_CFG, &buf); 839 check_warn_return(ret, "Failed to read HW_CFG: %d", ret); 840 841 buf |= HW_CFG_LRST; 842 843 ret = smsc75xx_write_reg(dev, HW_CFG, buf); 844 check_warn_return(ret, "Failed to write HW_CFG: %d", ret); 845 846 timeout = 0; 847 do { 848 msleep(10); 849 ret = smsc75xx_read_reg(dev, HW_CFG, &buf); 850 check_warn_return(ret, "Failed to read HW_CFG: %d", ret); 851 timeout++; 852 } while ((buf & HW_CFG_LRST) && (timeout < 100)); 853 854 if (timeout >= 100) { 855 netdev_warn(dev->net, "timeout on completion of Lite Reset"); 856 return -EIO; 857 } 858 859 netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY"); 860 861 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf); 862 check_warn_return(ret, "Failed to read PMT_CTL: %d", ret); 863 864 buf |= PMT_CTL_PHY_RST; 865 866 ret = smsc75xx_write_reg(dev, PMT_CTL, buf); 867 check_warn_return(ret, "Failed to write PMT_CTL: %d", ret); 868 869 timeout = 0; 870 do { 871 msleep(10); 872 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf); 873 check_warn_return(ret, "Failed to read PMT_CTL: %d", ret); 874 timeout++; 875 } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100)); 876 877 if (timeout >= 100) { 878 netdev_warn(dev->net, "timeout waiting for PHY Reset"); 879 return -EIO; 880 } 881 882 netif_dbg(dev, ifup, dev->net, "PHY reset complete"); 883 884 smsc75xx_init_mac_address(dev); 885 886 ret = smsc75xx_set_mac_address(dev); 887 check_warn_return(ret, "Failed to set mac address"); 888 889 netif_dbg(dev, ifup, dev->net, "MAC Address: %pM", dev->net->dev_addr); 890 891 ret = smsc75xx_read_reg(dev, HW_CFG, &buf); 892 check_warn_return(ret, "Failed to read HW_CFG: %d", ret); 893 894 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x", buf); 895 896 buf |= HW_CFG_BIR; 897 898 ret = smsc75xx_write_reg(dev, HW_CFG, buf); 899 check_warn_return(ret, "Failed to write HW_CFG: %d", ret); 900 901 ret = smsc75xx_read_reg(dev, HW_CFG, &buf); 902 check_warn_return(ret, "Failed to read HW_CFG: %d", ret); 903 904 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after " 905 "writing HW_CFG_BIR: 0x%08x", buf); 906 907 if (!turbo_mode) { 908 buf = 0; 909 dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE; 910 } else if (dev->udev->speed == USB_SPEED_HIGH) { 911 buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE; 912 dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE; 913 } else { 914 buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE; 915 dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE; 916 } 917 918 netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld", 919 (ulong)dev->rx_urb_size); 920 921 ret = smsc75xx_write_reg(dev, BURST_CAP, buf); 922 check_warn_return(ret, "Failed to write BURST_CAP: %d", ret); 923 924 ret = smsc75xx_read_reg(dev, BURST_CAP, &buf); 925 check_warn_return(ret, "Failed to read BURST_CAP: %d", ret); 926 927 netif_dbg(dev, ifup, dev->net, 928 "Read Value from BURST_CAP after writing: 0x%08x", buf); 929 930 ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY); 931 check_warn_return(ret, "Failed to write BULK_IN_DLY: %d", ret); 932 933 ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf); 934 check_warn_return(ret, "Failed to read BULK_IN_DLY: %d", ret); 935 936 netif_dbg(dev, ifup, dev->net, 937 "Read Value from BULK_IN_DLY after writing: 0x%08x", buf); 938 939 if (turbo_mode) { 940 ret = smsc75xx_read_reg(dev, HW_CFG, &buf); 941 check_warn_return(ret, "Failed to read HW_CFG: %d", ret); 942 943 netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x", buf); 944 945 buf |= (HW_CFG_MEF | HW_CFG_BCE); 946 947 ret = smsc75xx_write_reg(dev, HW_CFG, buf); 948 check_warn_return(ret, "Failed to write HW_CFG: %d", ret); 949 950 ret = smsc75xx_read_reg(dev, HW_CFG, &buf); 951 check_warn_return(ret, "Failed to read HW_CFG: %d", ret); 952 953 netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x", buf); 954 } 955 956 /* set FIFO sizes */ 957 buf = (MAX_RX_FIFO_SIZE - 512) / 512; 958 ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf); 959 check_warn_return(ret, "Failed to write FCT_RX_FIFO_END: %d", ret); 960 961 netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x", buf); 962 963 buf = (MAX_TX_FIFO_SIZE - 512) / 512; 964 ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf); 965 check_warn_return(ret, "Failed to write FCT_TX_FIFO_END: %d", ret); 966 967 netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x", buf); 968 969 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL); 970 check_warn_return(ret, "Failed to write INT_STS: %d", ret); 971 972 ret = smsc75xx_read_reg(dev, ID_REV, &buf); 973 check_warn_return(ret, "Failed to read ID_REV: %d", ret); 974 975 netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x", buf); 976 977 ret = smsc75xx_read_reg(dev, E2P_CMD, &buf); 978 check_warn_return(ret, "Failed to read E2P_CMD: %d", ret); 979 980 /* only set default GPIO/LED settings if no EEPROM is detected */ 981 if (!(buf & E2P_CMD_LOADED)) { 982 ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf); 983 check_warn_return(ret, "Failed to read LED_GPIO_CFG: %d", ret); 984 985 buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL); 986 buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL; 987 988 ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf); 989 check_warn_return(ret, "Failed to write LED_GPIO_CFG: %d", ret); 990 } 991 992 ret = smsc75xx_write_reg(dev, FLOW, 0); 993 check_warn_return(ret, "Failed to write FLOW: %d", ret); 994 995 ret = smsc75xx_write_reg(dev, FCT_FLOW, 0); 996 check_warn_return(ret, "Failed to write FCT_FLOW: %d", ret); 997 998 /* Don't need rfe_ctl_lock during initialisation */ 999 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl); 1000 check_warn_return(ret, "Failed to read RFE_CTL: %d", ret); 1001 1002 pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF; 1003 1004 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl); 1005 check_warn_return(ret, "Failed to write RFE_CTL: %d", ret); 1006 1007 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl); 1008 check_warn_return(ret, "Failed to read RFE_CTL: %d", ret); 1009 1010 netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x", pdata->rfe_ctl); 1011 1012 /* Enable or disable checksum offload engines */ 1013 smsc75xx_set_features(dev->net, dev->net->features); 1014 1015 smsc75xx_set_multicast(dev->net); 1016 1017 ret = smsc75xx_phy_initialize(dev); 1018 check_warn_return(ret, "Failed to initialize PHY: %d", ret); 1019 1020 ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf); 1021 check_warn_return(ret, "Failed to read INT_EP_CTL: %d", ret); 1022 1023 /* enable PHY interrupts */ 1024 buf |= INT_ENP_PHY_INT; 1025 1026 ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf); 1027 check_warn_return(ret, "Failed to write INT_EP_CTL: %d", ret); 1028 1029 /* allow mac to detect speed and duplex from phy */ 1030 ret = smsc75xx_read_reg(dev, MAC_CR, &buf); 1031 check_warn_return(ret, "Failed to read MAC_CR: %d", ret); 1032 1033 buf |= (MAC_CR_ADD | MAC_CR_ASD); 1034 ret = smsc75xx_write_reg(dev, MAC_CR, buf); 1035 check_warn_return(ret, "Failed to write MAC_CR: %d", ret); 1036 1037 ret = smsc75xx_read_reg(dev, MAC_TX, &buf); 1038 check_warn_return(ret, "Failed to read MAC_TX: %d", ret); 1039 1040 buf |= MAC_TX_TXEN; 1041 1042 ret = smsc75xx_write_reg(dev, MAC_TX, buf); 1043 check_warn_return(ret, "Failed to write MAC_TX: %d", ret); 1044 1045 netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x", buf); 1046 1047 ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf); 1048 check_warn_return(ret, "Failed to read FCT_TX_CTL: %d", ret); 1049 1050 buf |= FCT_TX_CTL_EN; 1051 1052 ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf); 1053 check_warn_return(ret, "Failed to write FCT_TX_CTL: %d", ret); 1054 1055 netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x", buf); 1056 1057 ret = smsc75xx_set_rx_max_frame_length(dev, 1514); 1058 check_warn_return(ret, "Failed to set max rx frame length"); 1059 1060 ret = smsc75xx_read_reg(dev, MAC_RX, &buf); 1061 check_warn_return(ret, "Failed to read MAC_RX: %d", ret); 1062 1063 buf |= MAC_RX_RXEN; 1064 1065 ret = smsc75xx_write_reg(dev, MAC_RX, buf); 1066 check_warn_return(ret, "Failed to write MAC_RX: %d", ret); 1067 1068 netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x", buf); 1069 1070 ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf); 1071 check_warn_return(ret, "Failed to read FCT_RX_CTL: %d", ret); 1072 1073 buf |= FCT_RX_CTL_EN; 1074 1075 ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf); 1076 check_warn_return(ret, "Failed to write FCT_RX_CTL: %d", ret); 1077 1078 netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x", buf); 1079 1080 netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0"); 1081 return 0; 1082 } 1083 1084 static const struct net_device_ops smsc75xx_netdev_ops = { 1085 .ndo_open = usbnet_open, 1086 .ndo_stop = usbnet_stop, 1087 .ndo_start_xmit = usbnet_start_xmit, 1088 .ndo_tx_timeout = usbnet_tx_timeout, 1089 .ndo_change_mtu = smsc75xx_change_mtu, 1090 .ndo_set_mac_address = eth_mac_addr, 1091 .ndo_validate_addr = eth_validate_addr, 1092 .ndo_do_ioctl = smsc75xx_ioctl, 1093 .ndo_set_rx_mode = smsc75xx_set_multicast, 1094 .ndo_set_features = smsc75xx_set_features, 1095 }; 1096 1097 static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf) 1098 { 1099 struct smsc75xx_priv *pdata = NULL; 1100 int ret; 1101 1102 printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n"); 1103 1104 ret = usbnet_get_endpoints(dev, intf); 1105 check_warn_return(ret, "usbnet_get_endpoints failed: %d", ret); 1106 1107 dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv), 1108 GFP_KERNEL); 1109 1110 pdata = (struct smsc75xx_priv *)(dev->data[0]); 1111 if (!pdata) { 1112 netdev_warn(dev->net, "Unable to allocate smsc75xx_priv"); 1113 return -ENOMEM; 1114 } 1115 1116 pdata->dev = dev; 1117 1118 spin_lock_init(&pdata->rfe_ctl_lock); 1119 mutex_init(&pdata->dataport_mutex); 1120 1121 INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write); 1122 1123 if (DEFAULT_TX_CSUM_ENABLE) { 1124 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1125 if (DEFAULT_TSO_ENABLE) 1126 dev->net->features |= NETIF_F_SG | 1127 NETIF_F_TSO | NETIF_F_TSO6; 1128 } 1129 if (DEFAULT_RX_CSUM_ENABLE) 1130 dev->net->features |= NETIF_F_RXCSUM; 1131 1132 dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1133 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_RXCSUM; 1134 1135 /* Init all registers */ 1136 ret = smsc75xx_reset(dev); 1137 1138 dev->net->netdev_ops = &smsc75xx_netdev_ops; 1139 dev->net->ethtool_ops = &smsc75xx_ethtool_ops; 1140 dev->net->flags |= IFF_MULTICAST; 1141 dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD; 1142 dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len; 1143 return 0; 1144 } 1145 1146 static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf) 1147 { 1148 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]); 1149 if (pdata) { 1150 netif_dbg(dev, ifdown, dev->net, "free pdata"); 1151 kfree(pdata); 1152 pdata = NULL; 1153 dev->data[0] = 0; 1154 } 1155 } 1156 1157 static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message) 1158 { 1159 struct usbnet *dev = usb_get_intfdata(intf); 1160 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]); 1161 int ret; 1162 u32 val; 1163 1164 ret = usbnet_suspend(intf, message); 1165 check_warn_return(ret, "usbnet_suspend error"); 1166 1167 /* if no wol options set, enter lowest power SUSPEND2 mode */ 1168 if (!(pdata->wolopts & SUPPORTED_WAKE)) { 1169 netdev_info(dev->net, "entering SUSPEND2 mode"); 1170 1171 /* disable energy detect (link up) & wake up events */ 1172 ret = smsc75xx_read_reg(dev, WUCSR, &val); 1173 check_warn_return(ret, "Error reading WUCSR"); 1174 1175 val &= ~(WUCSR_MPEN | WUCSR_WUEN); 1176 1177 ret = smsc75xx_write_reg(dev, WUCSR, val); 1178 check_warn_return(ret, "Error writing WUCSR"); 1179 1180 ret = smsc75xx_read_reg(dev, PMT_CTL, &val); 1181 check_warn_return(ret, "Error reading PMT_CTL"); 1182 1183 val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN); 1184 1185 ret = smsc75xx_write_reg(dev, PMT_CTL, val); 1186 check_warn_return(ret, "Error writing PMT_CTL"); 1187 1188 /* enter suspend2 mode */ 1189 ret = smsc75xx_read_reg(dev, PMT_CTL, &val); 1190 check_warn_return(ret, "Error reading PMT_CTL"); 1191 1192 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST); 1193 val |= PMT_CTL_SUS_MODE_2; 1194 1195 ret = smsc75xx_write_reg(dev, PMT_CTL, val); 1196 check_warn_return(ret, "Error writing PMT_CTL"); 1197 1198 return 0; 1199 } 1200 1201 if (pdata->wolopts & WAKE_MAGIC) { 1202 /* clear any pending magic packet status */ 1203 ret = smsc75xx_read_reg(dev, WUCSR, &val); 1204 check_warn_return(ret, "Error reading WUCSR"); 1205 1206 val |= WUCSR_MPR; 1207 1208 ret = smsc75xx_write_reg(dev, WUCSR, val); 1209 check_warn_return(ret, "Error writing WUCSR"); 1210 } 1211 1212 /* enable/disable magic packup wake */ 1213 ret = smsc75xx_read_reg(dev, WUCSR, &val); 1214 check_warn_return(ret, "Error reading WUCSR"); 1215 1216 if (pdata->wolopts & WAKE_MAGIC) { 1217 netdev_info(dev->net, "enabling magic packet wakeup"); 1218 val |= WUCSR_MPEN; 1219 } else { 1220 netdev_info(dev->net, "disabling magic packet wakeup"); 1221 val &= ~WUCSR_MPEN; 1222 } 1223 1224 ret = smsc75xx_write_reg(dev, WUCSR, val); 1225 check_warn_return(ret, "Error writing WUCSR"); 1226 1227 /* enable wol wakeup source */ 1228 ret = smsc75xx_read_reg(dev, PMT_CTL, &val); 1229 check_warn_return(ret, "Error reading PMT_CTL"); 1230 1231 val |= PMT_CTL_WOL_EN; 1232 1233 ret = smsc75xx_write_reg(dev, PMT_CTL, val); 1234 check_warn_return(ret, "Error writing PMT_CTL"); 1235 1236 /* enable receiver */ 1237 ret = smsc75xx_read_reg(dev, MAC_RX, &val); 1238 check_warn_return(ret, "Failed to read MAC_RX: %d", ret); 1239 1240 val |= MAC_RX_RXEN; 1241 1242 ret = smsc75xx_write_reg(dev, MAC_RX, val); 1243 check_warn_return(ret, "Failed to write MAC_RX: %d", ret); 1244 1245 /* some wol options are enabled, so enter SUSPEND0 */ 1246 netdev_info(dev->net, "entering SUSPEND0 mode"); 1247 1248 ret = smsc75xx_read_reg(dev, PMT_CTL, &val); 1249 check_warn_return(ret, "Error reading PMT_CTL"); 1250 1251 val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST)); 1252 val |= PMT_CTL_SUS_MODE_0; 1253 1254 ret = smsc75xx_write_reg(dev, PMT_CTL, val); 1255 check_warn_return(ret, "Error writing PMT_CTL"); 1256 1257 /* clear wol status */ 1258 val &= ~PMT_CTL_WUPS; 1259 val |= PMT_CTL_WUPS_WOL; 1260 ret = smsc75xx_write_reg(dev, PMT_CTL, val); 1261 check_warn_return(ret, "Error writing PMT_CTL"); 1262 1263 /* read back PMT_CTL */ 1264 ret = smsc75xx_read_reg(dev, PMT_CTL, &val); 1265 check_warn_return(ret, "Error reading PMT_CTL"); 1266 1267 smsc75xx_set_feature(dev, USB_DEVICE_REMOTE_WAKEUP); 1268 1269 return 0; 1270 } 1271 1272 static int smsc75xx_resume(struct usb_interface *intf) 1273 { 1274 struct usbnet *dev = usb_get_intfdata(intf); 1275 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]); 1276 int ret; 1277 u32 val; 1278 1279 if (pdata->wolopts & WAKE_MAGIC) { 1280 netdev_info(dev->net, "resuming from SUSPEND0"); 1281 1282 smsc75xx_clear_feature(dev, USB_DEVICE_REMOTE_WAKEUP); 1283 1284 /* Disable magic packup wake */ 1285 ret = smsc75xx_read_reg(dev, WUCSR, &val); 1286 check_warn_return(ret, "Error reading WUCSR"); 1287 1288 val &= ~WUCSR_MPEN; 1289 1290 ret = smsc75xx_write_reg(dev, WUCSR, val); 1291 check_warn_return(ret, "Error writing WUCSR"); 1292 1293 /* clear wake-up status */ 1294 ret = smsc75xx_read_reg(dev, PMT_CTL, &val); 1295 check_warn_return(ret, "Error reading PMT_CTL"); 1296 1297 val &= ~PMT_CTL_WOL_EN; 1298 val |= PMT_CTL_WUPS; 1299 1300 ret = smsc75xx_write_reg(dev, PMT_CTL, val); 1301 check_warn_return(ret, "Error writing PMT_CTL"); 1302 } else { 1303 netdev_info(dev->net, "resuming from SUSPEND2"); 1304 1305 ret = smsc75xx_read_reg(dev, PMT_CTL, &val); 1306 check_warn_return(ret, "Error reading PMT_CTL"); 1307 1308 val |= PMT_CTL_PHY_PWRUP; 1309 1310 ret = smsc75xx_write_reg(dev, PMT_CTL, val); 1311 check_warn_return(ret, "Error writing PMT_CTL"); 1312 } 1313 1314 ret = smsc75xx_wait_ready(dev); 1315 check_warn_return(ret, "device not ready in smsc75xx_resume"); 1316 1317 return usbnet_resume(intf); 1318 } 1319 1320 static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb, 1321 u32 rx_cmd_a, u32 rx_cmd_b) 1322 { 1323 if (!(dev->net->features & NETIF_F_RXCSUM) || 1324 unlikely(rx_cmd_a & RX_CMD_A_LCSM)) { 1325 skb->ip_summed = CHECKSUM_NONE; 1326 } else { 1327 skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT)); 1328 skb->ip_summed = CHECKSUM_COMPLETE; 1329 } 1330 } 1331 1332 static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb) 1333 { 1334 while (skb->len > 0) { 1335 u32 rx_cmd_a, rx_cmd_b, align_count, size; 1336 struct sk_buff *ax_skb; 1337 unsigned char *packet; 1338 1339 memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a)); 1340 le32_to_cpus(&rx_cmd_a); 1341 skb_pull(skb, 4); 1342 1343 memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b)); 1344 le32_to_cpus(&rx_cmd_b); 1345 skb_pull(skb, 4 + RXW_PADDING); 1346 1347 packet = skb->data; 1348 1349 /* get the packet length */ 1350 size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING; 1351 align_count = (4 - ((size + RXW_PADDING) % 4)) % 4; 1352 1353 if (unlikely(rx_cmd_a & RX_CMD_A_RED)) { 1354 netif_dbg(dev, rx_err, dev->net, 1355 "Error rx_cmd_a=0x%08x", rx_cmd_a); 1356 dev->net->stats.rx_errors++; 1357 dev->net->stats.rx_dropped++; 1358 1359 if (rx_cmd_a & RX_CMD_A_FCS) 1360 dev->net->stats.rx_crc_errors++; 1361 else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT)) 1362 dev->net->stats.rx_frame_errors++; 1363 } else { 1364 /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */ 1365 if (unlikely(size > (ETH_FRAME_LEN + 12))) { 1366 netif_dbg(dev, rx_err, dev->net, 1367 "size err rx_cmd_a=0x%08x", rx_cmd_a); 1368 return 0; 1369 } 1370 1371 /* last frame in this batch */ 1372 if (skb->len == size) { 1373 smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a, 1374 rx_cmd_b); 1375 1376 skb_trim(skb, skb->len - 4); /* remove fcs */ 1377 skb->truesize = size + sizeof(struct sk_buff); 1378 1379 return 1; 1380 } 1381 1382 ax_skb = skb_clone(skb, GFP_ATOMIC); 1383 if (unlikely(!ax_skb)) { 1384 netdev_warn(dev->net, "Error allocating skb"); 1385 return 0; 1386 } 1387 1388 ax_skb->len = size; 1389 ax_skb->data = packet; 1390 skb_set_tail_pointer(ax_skb, size); 1391 1392 smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a, 1393 rx_cmd_b); 1394 1395 skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */ 1396 ax_skb->truesize = size + sizeof(struct sk_buff); 1397 1398 usbnet_skb_return(dev, ax_skb); 1399 } 1400 1401 skb_pull(skb, size); 1402 1403 /* padding bytes before the next frame starts */ 1404 if (skb->len) 1405 skb_pull(skb, align_count); 1406 } 1407 1408 if (unlikely(skb->len < 0)) { 1409 netdev_warn(dev->net, "invalid rx length<0 %d", skb->len); 1410 return 0; 1411 } 1412 1413 return 1; 1414 } 1415 1416 static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev, 1417 struct sk_buff *skb, gfp_t flags) 1418 { 1419 u32 tx_cmd_a, tx_cmd_b; 1420 1421 skb_linearize(skb); 1422 1423 if (skb_headroom(skb) < SMSC75XX_TX_OVERHEAD) { 1424 struct sk_buff *skb2 = 1425 skb_copy_expand(skb, SMSC75XX_TX_OVERHEAD, 0, flags); 1426 dev_kfree_skb_any(skb); 1427 skb = skb2; 1428 if (!skb) 1429 return NULL; 1430 } 1431 1432 tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS; 1433 1434 if (skb->ip_summed == CHECKSUM_PARTIAL) 1435 tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE; 1436 1437 if (skb_is_gso(skb)) { 1438 u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN); 1439 tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS; 1440 1441 tx_cmd_a |= TX_CMD_A_LSO; 1442 } else { 1443 tx_cmd_b = 0; 1444 } 1445 1446 skb_push(skb, 4); 1447 cpu_to_le32s(&tx_cmd_b); 1448 memcpy(skb->data, &tx_cmd_b, 4); 1449 1450 skb_push(skb, 4); 1451 cpu_to_le32s(&tx_cmd_a); 1452 memcpy(skb->data, &tx_cmd_a, 4); 1453 1454 return skb; 1455 } 1456 1457 static const struct driver_info smsc75xx_info = { 1458 .description = "smsc75xx USB 2.0 Gigabit Ethernet", 1459 .bind = smsc75xx_bind, 1460 .unbind = smsc75xx_unbind, 1461 .link_reset = smsc75xx_link_reset, 1462 .reset = smsc75xx_reset, 1463 .rx_fixup = smsc75xx_rx_fixup, 1464 .tx_fixup = smsc75xx_tx_fixup, 1465 .status = smsc75xx_status, 1466 .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR, 1467 }; 1468 1469 static const struct usb_device_id products[] = { 1470 { 1471 /* SMSC7500 USB Gigabit Ethernet Device */ 1472 USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500), 1473 .driver_info = (unsigned long) &smsc75xx_info, 1474 }, 1475 { 1476 /* SMSC7500 USB Gigabit Ethernet Device */ 1477 USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505), 1478 .driver_info = (unsigned long) &smsc75xx_info, 1479 }, 1480 { }, /* END */ 1481 }; 1482 MODULE_DEVICE_TABLE(usb, products); 1483 1484 static struct usb_driver smsc75xx_driver = { 1485 .name = SMSC_CHIPNAME, 1486 .id_table = products, 1487 .probe = usbnet_probe, 1488 .suspend = smsc75xx_suspend, 1489 .resume = smsc75xx_resume, 1490 .reset_resume = smsc75xx_resume, 1491 .disconnect = usbnet_disconnect, 1492 .disable_hub_initiated_lpm = 1, 1493 }; 1494 1495 module_usb_driver(smsc75xx_driver); 1496 1497 MODULE_AUTHOR("Nancy Lin"); 1498 MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>"); 1499 MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices"); 1500 MODULE_LICENSE("GPL"); 1501