1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 4 */ 5 6 #include <linux/signal.h> 7 #include <linux/slab.h> 8 #include <linux/module.h> 9 #include <linux/netdevice.h> 10 #include <linux/etherdevice.h> 11 #include <linux/mii.h> 12 #include <linux/ethtool.h> 13 #include <linux/usb.h> 14 #include <linux/crc32.h> 15 #include <linux/if_vlan.h> 16 #include <linux/uaccess.h> 17 #include <linux/list.h> 18 #include <linux/ip.h> 19 #include <linux/ipv6.h> 20 #include <net/ip6_checksum.h> 21 #include <uapi/linux/mdio.h> 22 #include <linux/mdio.h> 23 #include <linux/usb/cdc.h> 24 #include <linux/suspend.h> 25 #include <linux/acpi.h> 26 27 /* Information for net-next */ 28 #define NETNEXT_VERSION "09" 29 30 /* Information for net */ 31 #define NET_VERSION "9" 32 33 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION 34 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 35 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 36 #define MODULENAME "r8152" 37 38 #define R8152_PHY_ID 32 39 40 #define PLA_IDR 0xc000 41 #define PLA_RCR 0xc010 42 #define PLA_RMS 0xc016 43 #define PLA_RXFIFO_CTRL0 0xc0a0 44 #define PLA_RXFIFO_CTRL1 0xc0a4 45 #define PLA_RXFIFO_CTRL2 0xc0a8 46 #define PLA_DMY_REG0 0xc0b0 47 #define PLA_FMC 0xc0b4 48 #define PLA_CFG_WOL 0xc0b6 49 #define PLA_TEREDO_CFG 0xc0bc 50 #define PLA_TEREDO_WAKE_BASE 0xc0c4 51 #define PLA_MAR 0xcd00 52 #define PLA_BACKUP 0xd000 53 #define PAL_BDC_CR 0xd1a0 54 #define PLA_TEREDO_TIMER 0xd2cc 55 #define PLA_REALWOW_TIMER 0xd2e8 56 #define PLA_EFUSE_DATA 0xdd00 57 #define PLA_EFUSE_CMD 0xdd02 58 #define PLA_LEDSEL 0xdd90 59 #define PLA_LED_FEATURE 0xdd92 60 #define PLA_PHYAR 0xde00 61 #define PLA_BOOT_CTRL 0xe004 62 #define PLA_GPHY_INTR_IMR 0xe022 63 #define PLA_EEE_CR 0xe040 64 #define PLA_EEEP_CR 0xe080 65 #define PLA_MAC_PWR_CTRL 0xe0c0 66 #define PLA_MAC_PWR_CTRL2 0xe0ca 67 #define PLA_MAC_PWR_CTRL3 0xe0cc 68 #define PLA_MAC_PWR_CTRL4 0xe0ce 69 #define PLA_WDT6_CTRL 0xe428 70 #define PLA_TCR0 0xe610 71 #define PLA_TCR1 0xe612 72 #define PLA_MTPS 0xe615 73 #define PLA_TXFIFO_CTRL 0xe618 74 #define PLA_RSTTALLY 0xe800 75 #define PLA_CR 0xe813 76 #define PLA_CRWECR 0xe81c 77 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 78 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 79 #define PLA_CONFIG5 0xe822 80 #define PLA_PHY_PWR 0xe84c 81 #define PLA_OOB_CTRL 0xe84f 82 #define PLA_CPCR 0xe854 83 #define PLA_MISC_0 0xe858 84 #define PLA_MISC_1 0xe85a 85 #define PLA_OCP_GPHY_BASE 0xe86c 86 #define PLA_TALLYCNT 0xe890 87 #define PLA_SFF_STS_7 0xe8de 88 #define PLA_PHYSTATUS 0xe908 89 #define PLA_BP_BA 0xfc26 90 #define PLA_BP_0 0xfc28 91 #define PLA_BP_1 0xfc2a 92 #define PLA_BP_2 0xfc2c 93 #define PLA_BP_3 0xfc2e 94 #define PLA_BP_4 0xfc30 95 #define PLA_BP_5 0xfc32 96 #define PLA_BP_6 0xfc34 97 #define PLA_BP_7 0xfc36 98 #define PLA_BP_EN 0xfc38 99 100 #define USB_USB2PHY 0xb41e 101 #define USB_SSPHYLINK2 0xb428 102 #define USB_U2P3_CTRL 0xb460 103 #define USB_CSR_DUMMY1 0xb464 104 #define USB_CSR_DUMMY2 0xb466 105 #define USB_DEV_STAT 0xb808 106 #define USB_CONNECT_TIMER 0xcbf8 107 #define USB_MSC_TIMER 0xcbfc 108 #define USB_BURST_SIZE 0xcfc0 109 #define USB_LPM_CONFIG 0xcfd8 110 #define USB_USB_CTRL 0xd406 111 #define USB_PHY_CTRL 0xd408 112 #define USB_TX_AGG 0xd40a 113 #define USB_RX_BUF_TH 0xd40c 114 #define USB_USB_TIMER 0xd428 115 #define USB_RX_EARLY_TIMEOUT 0xd42c 116 #define USB_RX_EARLY_SIZE 0xd42e 117 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ 118 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ 119 #define USB_TX_DMA 0xd434 120 #define USB_UPT_RXDMA_OWN 0xd437 121 #define USB_TOLERANCE 0xd490 122 #define USB_LPM_CTRL 0xd41a 123 #define USB_BMU_RESET 0xd4b0 124 #define USB_U1U2_TIMER 0xd4da 125 #define USB_UPS_CTRL 0xd800 126 #define USB_POWER_CUT 0xd80a 127 #define USB_MISC_0 0xd81a 128 #define USB_MISC_1 0xd81f 129 #define USB_AFE_CTRL2 0xd824 130 #define USB_UPS_CFG 0xd842 131 #define USB_UPS_FLAGS 0xd848 132 #define USB_WDT11_CTRL 0xe43c 133 #define USB_BP_BA 0xfc26 134 #define USB_BP_0 0xfc28 135 #define USB_BP_1 0xfc2a 136 #define USB_BP_2 0xfc2c 137 #define USB_BP_3 0xfc2e 138 #define USB_BP_4 0xfc30 139 #define USB_BP_5 0xfc32 140 #define USB_BP_6 0xfc34 141 #define USB_BP_7 0xfc36 142 #define USB_BP_EN 0xfc38 143 #define USB_BP_8 0xfc38 144 #define USB_BP_9 0xfc3a 145 #define USB_BP_10 0xfc3c 146 #define USB_BP_11 0xfc3e 147 #define USB_BP_12 0xfc40 148 #define USB_BP_13 0xfc42 149 #define USB_BP_14 0xfc44 150 #define USB_BP_15 0xfc46 151 #define USB_BP2_EN 0xfc48 152 153 /* OCP Registers */ 154 #define OCP_ALDPS_CONFIG 0x2010 155 #define OCP_EEE_CONFIG1 0x2080 156 #define OCP_EEE_CONFIG2 0x2092 157 #define OCP_EEE_CONFIG3 0x2094 158 #define OCP_BASE_MII 0xa400 159 #define OCP_EEE_AR 0xa41a 160 #define OCP_EEE_DATA 0xa41c 161 #define OCP_PHY_STATUS 0xa420 162 #define OCP_NCTL_CFG 0xa42c 163 #define OCP_POWER_CFG 0xa430 164 #define OCP_EEE_CFG 0xa432 165 #define OCP_SRAM_ADDR 0xa436 166 #define OCP_SRAM_DATA 0xa438 167 #define OCP_DOWN_SPEED 0xa442 168 #define OCP_EEE_ABLE 0xa5c4 169 #define OCP_EEE_ADV 0xa5d0 170 #define OCP_EEE_LPABLE 0xa5d2 171 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ 172 #define OCP_PHY_PATCH_STAT 0xb800 173 #define OCP_PHY_PATCH_CMD 0xb820 174 #define OCP_ADC_IOFFSET 0xbcfc 175 #define OCP_ADC_CFG 0xbc06 176 #define OCP_SYSCLK_CFG 0xc416 177 178 /* SRAM Register */ 179 #define SRAM_GREEN_CFG 0x8011 180 #define SRAM_LPF_CFG 0x8012 181 #define SRAM_10M_AMP1 0x8080 182 #define SRAM_10M_AMP2 0x8082 183 #define SRAM_IMPEDANCE 0x8084 184 185 /* PLA_RCR */ 186 #define RCR_AAP 0x00000001 187 #define RCR_APM 0x00000002 188 #define RCR_AM 0x00000004 189 #define RCR_AB 0x00000008 190 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 191 192 /* PLA_RXFIFO_CTRL0 */ 193 #define RXFIFO_THR1_NORMAL 0x00080002 194 #define RXFIFO_THR1_OOB 0x01800003 195 196 /* PLA_RXFIFO_CTRL1 */ 197 #define RXFIFO_THR2_FULL 0x00000060 198 #define RXFIFO_THR2_HIGH 0x00000038 199 #define RXFIFO_THR2_OOB 0x0000004a 200 #define RXFIFO_THR2_NORMAL 0x00a0 201 202 /* PLA_RXFIFO_CTRL2 */ 203 #define RXFIFO_THR3_FULL 0x00000078 204 #define RXFIFO_THR3_HIGH 0x00000048 205 #define RXFIFO_THR3_OOB 0x0000005a 206 #define RXFIFO_THR3_NORMAL 0x0110 207 208 /* PLA_TXFIFO_CTRL */ 209 #define TXFIFO_THR_NORMAL 0x00400008 210 #define TXFIFO_THR_NORMAL2 0x01000008 211 212 /* PLA_DMY_REG0 */ 213 #define ECM_ALDPS 0x0002 214 215 /* PLA_FMC */ 216 #define FMC_FCR_MCU_EN 0x0001 217 218 /* PLA_EEEP_CR */ 219 #define EEEP_CR_EEEP_TX 0x0002 220 221 /* PLA_WDT6_CTRL */ 222 #define WDT6_SET_MODE 0x0010 223 224 /* PLA_TCR0 */ 225 #define TCR0_TX_EMPTY 0x0800 226 #define TCR0_AUTO_FIFO 0x0080 227 228 /* PLA_TCR1 */ 229 #define VERSION_MASK 0x7cf0 230 231 /* PLA_MTPS */ 232 #define MTPS_JUMBO (12 * 1024 / 64) 233 #define MTPS_DEFAULT (6 * 1024 / 64) 234 235 /* PLA_RSTTALLY */ 236 #define TALLY_RESET 0x0001 237 238 /* PLA_CR */ 239 #define CR_RST 0x10 240 #define CR_RE 0x08 241 #define CR_TE 0x04 242 243 /* PLA_CRWECR */ 244 #define CRWECR_NORAML 0x00 245 #define CRWECR_CONFIG 0xc0 246 247 /* PLA_OOB_CTRL */ 248 #define NOW_IS_OOB 0x80 249 #define TXFIFO_EMPTY 0x20 250 #define RXFIFO_EMPTY 0x10 251 #define LINK_LIST_READY 0x02 252 #define DIS_MCU_CLROOB 0x01 253 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 254 255 /* PLA_MISC_1 */ 256 #define RXDY_GATED_EN 0x0008 257 258 /* PLA_SFF_STS_7 */ 259 #define RE_INIT_LL 0x8000 260 #define MCU_BORW_EN 0x4000 261 262 /* PLA_CPCR */ 263 #define CPCR_RX_VLAN 0x0040 264 265 /* PLA_CFG_WOL */ 266 #define MAGIC_EN 0x0001 267 268 /* PLA_TEREDO_CFG */ 269 #define TEREDO_SEL 0x8000 270 #define TEREDO_WAKE_MASK 0x7f00 271 #define TEREDO_RS_EVENT_MASK 0x00fe 272 #define OOB_TEREDO_EN 0x0001 273 274 /* PAL_BDC_CR */ 275 #define ALDPS_PROXY_MODE 0x0001 276 277 /* PLA_EFUSE_CMD */ 278 #define EFUSE_READ_CMD BIT(15) 279 #define EFUSE_DATA_BIT16 BIT(7) 280 281 /* PLA_CONFIG34 */ 282 #define LINK_ON_WAKE_EN 0x0010 283 #define LINK_OFF_WAKE_EN 0x0008 284 285 /* PLA_CONFIG5 */ 286 #define BWF_EN 0x0040 287 #define MWF_EN 0x0020 288 #define UWF_EN 0x0010 289 #define LAN_WAKE_EN 0x0002 290 291 /* PLA_LED_FEATURE */ 292 #define LED_MODE_MASK 0x0700 293 294 /* PLA_PHY_PWR */ 295 #define TX_10M_IDLE_EN 0x0080 296 #define PFM_PWM_SWITCH 0x0040 297 298 /* PLA_MAC_PWR_CTRL */ 299 #define D3_CLK_GATED_EN 0x00004000 300 #define MCU_CLK_RATIO 0x07010f07 301 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 302 #define ALDPS_SPDWN_RATIO 0x0f87 303 304 /* PLA_MAC_PWR_CTRL2 */ 305 #define EEE_SPDWN_RATIO 0x8007 306 #define MAC_CLK_SPDWN_EN BIT(15) 307 308 /* PLA_MAC_PWR_CTRL3 */ 309 #define PKT_AVAIL_SPDWN_EN 0x0100 310 #define SUSPEND_SPDWN_EN 0x0004 311 #define U1U2_SPDWN_EN 0x0002 312 #define L1_SPDWN_EN 0x0001 313 314 /* PLA_MAC_PWR_CTRL4 */ 315 #define PWRSAVE_SPDWN_EN 0x1000 316 #define RXDV_SPDWN_EN 0x0800 317 #define TX10MIDLE_EN 0x0100 318 #define TP100_SPDWN_EN 0x0020 319 #define TP500_SPDWN_EN 0x0010 320 #define TP1000_SPDWN_EN 0x0008 321 #define EEE_SPDWN_EN 0x0001 322 323 /* PLA_GPHY_INTR_IMR */ 324 #define GPHY_STS_MSK 0x0001 325 #define SPEED_DOWN_MSK 0x0002 326 #define SPDWN_RXDV_MSK 0x0004 327 #define SPDWN_LINKCHG_MSK 0x0008 328 329 /* PLA_PHYAR */ 330 #define PHYAR_FLAG 0x80000000 331 332 /* PLA_EEE_CR */ 333 #define EEE_RX_EN 0x0001 334 #define EEE_TX_EN 0x0002 335 336 /* PLA_BOOT_CTRL */ 337 #define AUTOLOAD_DONE 0x0002 338 339 /* USB_USB2PHY */ 340 #define USB2PHY_SUSPEND 0x0001 341 #define USB2PHY_L1 0x0002 342 343 /* USB_SSPHYLINK2 */ 344 #define pwd_dn_scale_mask 0x3ffe 345 #define pwd_dn_scale(x) ((x) << 1) 346 347 /* USB_CSR_DUMMY1 */ 348 #define DYNAMIC_BURST 0x0001 349 350 /* USB_CSR_DUMMY2 */ 351 #define EP4_FULL_FC 0x0001 352 353 /* USB_DEV_STAT */ 354 #define STAT_SPEED_MASK 0x0006 355 #define STAT_SPEED_HIGH 0x0000 356 #define STAT_SPEED_FULL 0x0002 357 358 /* USB_LPM_CONFIG */ 359 #define LPM_U1U2_EN BIT(0) 360 361 /* USB_TX_AGG */ 362 #define TX_AGG_MAX_THRESHOLD 0x03 363 364 /* USB_RX_BUF_TH */ 365 #define RX_THR_SUPPER 0x0c350180 366 #define RX_THR_HIGH 0x7a120180 367 #define RX_THR_SLOW 0xffff0180 368 #define RX_THR_B 0x00010001 369 370 /* USB_TX_DMA */ 371 #define TEST_MODE_DISABLE 0x00000001 372 #define TX_SIZE_ADJUST1 0x00000100 373 374 /* USB_BMU_RESET */ 375 #define BMU_RESET_EP_IN 0x01 376 #define BMU_RESET_EP_OUT 0x02 377 378 /* USB_UPT_RXDMA_OWN */ 379 #define OWN_UPDATE BIT(0) 380 #define OWN_CLEAR BIT(1) 381 382 /* USB_UPS_CTRL */ 383 #define POWER_CUT 0x0100 384 385 /* USB_PM_CTRL_STATUS */ 386 #define RESUME_INDICATE 0x0001 387 388 /* USB_USB_CTRL */ 389 #define RX_AGG_DISABLE 0x0010 390 #define RX_ZERO_EN 0x0080 391 392 /* USB_U2P3_CTRL */ 393 #define U2P3_ENABLE 0x0001 394 395 /* USB_POWER_CUT */ 396 #define PWR_EN 0x0001 397 #define PHASE2_EN 0x0008 398 #define UPS_EN BIT(4) 399 #define USP_PREWAKE BIT(5) 400 401 /* USB_MISC_0 */ 402 #define PCUT_STATUS 0x0001 403 404 /* USB_RX_EARLY_TIMEOUT */ 405 #define COALESCE_SUPER 85000U 406 #define COALESCE_HIGH 250000U 407 #define COALESCE_SLOW 524280U 408 409 /* USB_WDT11_CTRL */ 410 #define TIMER11_EN 0x0001 411 412 /* USB_LPM_CTRL */ 413 /* bit 4 ~ 5: fifo empty boundary */ 414 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 415 /* bit 2 ~ 3: LMP timer */ 416 #define LPM_TIMER_MASK 0x0c 417 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 418 #define LPM_TIMER_500US 0x0c /* 500 us */ 419 #define ROK_EXIT_LPM 0x02 420 421 /* USB_AFE_CTRL2 */ 422 #define SEN_VAL_MASK 0xf800 423 #define SEN_VAL_NORMAL 0xa000 424 #define SEL_RXIDLE 0x0100 425 426 /* USB_UPS_CFG */ 427 #define SAW_CNT_1MS_MASK 0x0fff 428 429 /* USB_UPS_FLAGS */ 430 #define UPS_FLAGS_R_TUNE BIT(0) 431 #define UPS_FLAGS_EN_10M_CKDIV BIT(1) 432 #define UPS_FLAGS_250M_CKDIV BIT(2) 433 #define UPS_FLAGS_EN_ALDPS BIT(3) 434 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) 435 #define UPS_FLAGS_SPEED_MASK (0xf << 16) 436 #define ups_flags_speed(x) ((x) << 16) 437 #define UPS_FLAGS_EN_EEE BIT(20) 438 #define UPS_FLAGS_EN_500M_EEE BIT(21) 439 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22) 440 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) 441 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) 442 #define UPS_FLAGS_EN_GREEN BIT(26) 443 #define UPS_FLAGS_EN_FLOW_CTR BIT(27) 444 445 enum spd_duplex { 446 NWAY_10M_HALF = 1, 447 NWAY_10M_FULL, 448 NWAY_100M_HALF, 449 NWAY_100M_FULL, 450 NWAY_1000M_FULL, 451 FORCE_10M_HALF, 452 FORCE_10M_FULL, 453 FORCE_100M_HALF, 454 FORCE_100M_FULL, 455 }; 456 457 /* OCP_ALDPS_CONFIG */ 458 #define ENPWRSAVE 0x8000 459 #define ENPDNPS 0x0200 460 #define LINKENA 0x0100 461 #define DIS_SDSAVE 0x0010 462 463 /* OCP_PHY_STATUS */ 464 #define PHY_STAT_MASK 0x0007 465 #define PHY_STAT_EXT_INIT 2 466 #define PHY_STAT_LAN_ON 3 467 #define PHY_STAT_PWRDN 5 468 469 /* OCP_NCTL_CFG */ 470 #define PGA_RETURN_EN BIT(1) 471 472 /* OCP_POWER_CFG */ 473 #define EEE_CLKDIV_EN 0x8000 474 #define EN_ALDPS 0x0004 475 #define EN_10M_PLLOFF 0x0001 476 477 /* OCP_EEE_CONFIG1 */ 478 #define RG_TXLPI_MSK_HFDUP 0x8000 479 #define RG_MATCLR_EN 0x4000 480 #define EEE_10_CAP 0x2000 481 #define EEE_NWAY_EN 0x1000 482 #define TX_QUIET_EN 0x0200 483 #define RX_QUIET_EN 0x0100 484 #define sd_rise_time_mask 0x0070 485 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 486 #define RG_RXLPI_MSK_HFDUP 0x0008 487 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 488 489 /* OCP_EEE_CONFIG2 */ 490 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 491 #define RG_DACQUIET_EN 0x0400 492 #define RG_LDVQUIET_EN 0x0200 493 #define RG_CKRSEL 0x0020 494 #define RG_EEEPRG_EN 0x0010 495 496 /* OCP_EEE_CONFIG3 */ 497 #define fast_snr_mask 0xff80 498 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 499 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 500 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 501 502 /* OCP_EEE_AR */ 503 /* bit[15:14] function */ 504 #define FUN_ADDR 0x0000 505 #define FUN_DATA 0x4000 506 /* bit[4:0] device addr */ 507 508 /* OCP_EEE_CFG */ 509 #define CTAP_SHORT_EN 0x0040 510 #define EEE10_EN 0x0010 511 512 /* OCP_DOWN_SPEED */ 513 #define EN_EEE_CMODE BIT(14) 514 #define EN_EEE_1000 BIT(13) 515 #define EN_EEE_100 BIT(12) 516 #define EN_10M_CLKDIV BIT(11) 517 #define EN_10M_BGOFF 0x0080 518 519 /* OCP_PHY_STATE */ 520 #define TXDIS_STATE 0x01 521 #define ABD_STATE 0x02 522 523 /* OCP_PHY_PATCH_STAT */ 524 #define PATCH_READY BIT(6) 525 526 /* OCP_PHY_PATCH_CMD */ 527 #define PATCH_REQUEST BIT(4) 528 529 /* OCP_ADC_CFG */ 530 #define CKADSEL_L 0x0100 531 #define ADC_EN 0x0080 532 #define EN_EMI_L 0x0040 533 534 /* OCP_SYSCLK_CFG */ 535 #define clk_div_expo(x) (min(x, 5) << 8) 536 537 /* SRAM_GREEN_CFG */ 538 #define GREEN_ETH_EN BIT(15) 539 #define R_TUNE_EN BIT(11) 540 541 /* SRAM_LPF_CFG */ 542 #define LPF_AUTO_TUNE 0x8000 543 544 /* SRAM_10M_AMP1 */ 545 #define GDAC_IB_UPALL 0x0008 546 547 /* SRAM_10M_AMP2 */ 548 #define AMP_DN 0x0200 549 550 /* SRAM_IMPEDANCE */ 551 #define RX_DRIVING_MASK 0x6000 552 553 /* MAC PASSTHRU */ 554 #define AD_MASK 0xfee0 555 #define BND_MASK 0x0004 556 #define BD_MASK 0x0001 557 #define EFUSE 0xcfdb 558 #define PASS_THRU_MASK 0x1 559 560 enum rtl_register_content { 561 _1000bps = 0x10, 562 _100bps = 0x08, 563 _10bps = 0x04, 564 LINK_STATUS = 0x02, 565 FULL_DUP = 0x01, 566 }; 567 568 #define RTL8152_MAX_TX 4 569 #define RTL8152_MAX_RX 10 570 #define INTBUFSIZE 2 571 #define TX_ALIGN 4 572 #define RX_ALIGN 8 573 574 #define INTR_LINK 0x0004 575 576 #define RTL8152_REQT_READ 0xc0 577 #define RTL8152_REQT_WRITE 0x40 578 #define RTL8152_REQ_GET_REGS 0x05 579 #define RTL8152_REQ_SET_REGS 0x05 580 581 #define BYTE_EN_DWORD 0xff 582 #define BYTE_EN_WORD 0x33 583 #define BYTE_EN_BYTE 0x11 584 #define BYTE_EN_SIX_BYTES 0x3f 585 #define BYTE_EN_START_MASK 0x0f 586 #define BYTE_EN_END_MASK 0xf0 587 588 #define RTL8153_MAX_PACKET 9216 /* 9K */ 589 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \ 590 ETH_FCS_LEN) 591 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 592 #define RTL8153_RMS RTL8153_MAX_PACKET 593 #define RTL8152_TX_TIMEOUT (5 * HZ) 594 #define RTL8152_NAPI_WEIGHT 64 595 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \ 596 sizeof(struct rx_desc) + RX_ALIGN) 597 598 /* rtl8152 flags */ 599 enum rtl8152_flags { 600 RTL8152_UNPLUG = 0, 601 RTL8152_SET_RX_MODE, 602 WORK_ENABLE, 603 RTL8152_LINK_CHG, 604 SELECTIVE_SUSPEND, 605 PHY_RESET, 606 SCHEDULE_NAPI, 607 GREEN_ETHERNET, 608 DELL_TB_RX_AGG_BUG, 609 }; 610 611 /* Define these values to match your device */ 612 #define VENDOR_ID_REALTEK 0x0bda 613 #define VENDOR_ID_MICROSOFT 0x045e 614 #define VENDOR_ID_SAMSUNG 0x04e8 615 #define VENDOR_ID_LENOVO 0x17ef 616 #define VENDOR_ID_LINKSYS 0x13b1 617 #define VENDOR_ID_NVIDIA 0x0955 618 #define VENDOR_ID_TPLINK 0x2357 619 620 #define MCU_TYPE_PLA 0x0100 621 #define MCU_TYPE_USB 0x0000 622 623 struct tally_counter { 624 __le64 tx_packets; 625 __le64 rx_packets; 626 __le64 tx_errors; 627 __le32 rx_errors; 628 __le16 rx_missed; 629 __le16 align_errors; 630 __le32 tx_one_collision; 631 __le32 tx_multi_collision; 632 __le64 rx_unicast; 633 __le64 rx_broadcast; 634 __le32 rx_multicast; 635 __le16 tx_aborted; 636 __le16 tx_underrun; 637 }; 638 639 struct rx_desc { 640 __le32 opts1; 641 #define RX_LEN_MASK 0x7fff 642 643 __le32 opts2; 644 #define RD_UDP_CS BIT(23) 645 #define RD_TCP_CS BIT(22) 646 #define RD_IPV6_CS BIT(20) 647 #define RD_IPV4_CS BIT(19) 648 649 __le32 opts3; 650 #define IPF BIT(23) /* IP checksum fail */ 651 #define UDPF BIT(22) /* UDP checksum fail */ 652 #define TCPF BIT(21) /* TCP checksum fail */ 653 #define RX_VLAN_TAG BIT(16) 654 655 __le32 opts4; 656 __le32 opts5; 657 __le32 opts6; 658 }; 659 660 struct tx_desc { 661 __le32 opts1; 662 #define TX_FS BIT(31) /* First segment of a packet */ 663 #define TX_LS BIT(30) /* Final segment of a packet */ 664 #define GTSENDV4 BIT(28) 665 #define GTSENDV6 BIT(27) 666 #define GTTCPHO_SHIFT 18 667 #define GTTCPHO_MAX 0x7fU 668 #define TX_LEN_MAX 0x3ffffU 669 670 __le32 opts2; 671 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 672 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 673 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 674 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 675 #define MSS_SHIFT 17 676 #define MSS_MAX 0x7ffU 677 #define TCPHO_SHIFT 17 678 #define TCPHO_MAX 0x7ffU 679 #define TX_VLAN_TAG BIT(16) 680 }; 681 682 struct r8152; 683 684 struct rx_agg { 685 struct list_head list; 686 struct urb *urb; 687 struct r8152 *context; 688 void *buffer; 689 void *head; 690 }; 691 692 struct tx_agg { 693 struct list_head list; 694 struct urb *urb; 695 struct r8152 *context; 696 void *buffer; 697 void *head; 698 u32 skb_num; 699 u32 skb_len; 700 }; 701 702 struct r8152 { 703 unsigned long flags; 704 struct usb_device *udev; 705 struct napi_struct napi; 706 struct usb_interface *intf; 707 struct net_device *netdev; 708 struct urb *intr_urb; 709 struct tx_agg tx_info[RTL8152_MAX_TX]; 710 struct rx_agg rx_info[RTL8152_MAX_RX]; 711 struct list_head rx_done, tx_free; 712 struct sk_buff_head tx_queue, rx_queue; 713 spinlock_t rx_lock, tx_lock; 714 struct delayed_work schedule, hw_phy_work; 715 struct mii_if_info mii; 716 struct mutex control; /* use for hw setting */ 717 #ifdef CONFIG_PM_SLEEP 718 struct notifier_block pm_notifier; 719 #endif 720 721 struct rtl_ops { 722 void (*init)(struct r8152 *); 723 int (*enable)(struct r8152 *); 724 void (*disable)(struct r8152 *); 725 void (*up)(struct r8152 *); 726 void (*down)(struct r8152 *); 727 void (*unload)(struct r8152 *); 728 int (*eee_get)(struct r8152 *, struct ethtool_eee *); 729 int (*eee_set)(struct r8152 *, struct ethtool_eee *); 730 bool (*in_nway)(struct r8152 *); 731 void (*hw_phy_cfg)(struct r8152 *); 732 void (*autosuspend_en)(struct r8152 *tp, bool enable); 733 } rtl_ops; 734 735 int intr_interval; 736 u32 saved_wolopts; 737 u32 msg_enable; 738 u32 tx_qlen; 739 u32 coalesce; 740 u16 ocp_base; 741 u16 speed; 742 u8 *intr_buff; 743 u8 version; 744 u8 duplex; 745 u8 autoneg; 746 }; 747 748 enum rtl_version { 749 RTL_VER_UNKNOWN = 0, 750 RTL_VER_01, 751 RTL_VER_02, 752 RTL_VER_03, 753 RTL_VER_04, 754 RTL_VER_05, 755 RTL_VER_06, 756 RTL_VER_07, 757 RTL_VER_08, 758 RTL_VER_09, 759 RTL_VER_MAX 760 }; 761 762 enum tx_csum_stat { 763 TX_CSUM_SUCCESS = 0, 764 TX_CSUM_TSO, 765 TX_CSUM_NONE 766 }; 767 768 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 769 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 770 */ 771 static const int multicast_filter_limit = 32; 772 static unsigned int agg_buf_sz = 16384; 773 774 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ 775 VLAN_ETH_HLEN - ETH_FCS_LEN) 776 777 static 778 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 779 { 780 int ret; 781 void *tmp; 782 783 tmp = kmalloc(size, GFP_KERNEL); 784 if (!tmp) 785 return -ENOMEM; 786 787 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 788 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 789 value, index, tmp, size, 500); 790 791 memcpy(data, tmp, size); 792 kfree(tmp); 793 794 return ret; 795 } 796 797 static 798 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 799 { 800 int ret; 801 void *tmp; 802 803 tmp = kmemdup(data, size, GFP_KERNEL); 804 if (!tmp) 805 return -ENOMEM; 806 807 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 808 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 809 value, index, tmp, size, 500); 810 811 kfree(tmp); 812 813 return ret; 814 } 815 816 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 817 void *data, u16 type) 818 { 819 u16 limit = 64; 820 int ret = 0; 821 822 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 823 return -ENODEV; 824 825 /* both size and indix must be 4 bytes align */ 826 if ((size & 3) || !size || (index & 3) || !data) 827 return -EPERM; 828 829 if ((u32)index + (u32)size > 0xffff) 830 return -EPERM; 831 832 while (size) { 833 if (size > limit) { 834 ret = get_registers(tp, index, type, limit, data); 835 if (ret < 0) 836 break; 837 838 index += limit; 839 data += limit; 840 size -= limit; 841 } else { 842 ret = get_registers(tp, index, type, size, data); 843 if (ret < 0) 844 break; 845 846 index += size; 847 data += size; 848 size = 0; 849 break; 850 } 851 } 852 853 if (ret == -ENODEV) 854 set_bit(RTL8152_UNPLUG, &tp->flags); 855 856 return ret; 857 } 858 859 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 860 u16 size, void *data, u16 type) 861 { 862 int ret; 863 u16 byteen_start, byteen_end, byen; 864 u16 limit = 512; 865 866 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 867 return -ENODEV; 868 869 /* both size and indix must be 4 bytes align */ 870 if ((size & 3) || !size || (index & 3) || !data) 871 return -EPERM; 872 873 if ((u32)index + (u32)size > 0xffff) 874 return -EPERM; 875 876 byteen_start = byteen & BYTE_EN_START_MASK; 877 byteen_end = byteen & BYTE_EN_END_MASK; 878 879 byen = byteen_start | (byteen_start << 4); 880 ret = set_registers(tp, index, type | byen, 4, data); 881 if (ret < 0) 882 goto error1; 883 884 index += 4; 885 data += 4; 886 size -= 4; 887 888 if (size) { 889 size -= 4; 890 891 while (size) { 892 if (size > limit) { 893 ret = set_registers(tp, index, 894 type | BYTE_EN_DWORD, 895 limit, data); 896 if (ret < 0) 897 goto error1; 898 899 index += limit; 900 data += limit; 901 size -= limit; 902 } else { 903 ret = set_registers(tp, index, 904 type | BYTE_EN_DWORD, 905 size, data); 906 if (ret < 0) 907 goto error1; 908 909 index += size; 910 data += size; 911 size = 0; 912 break; 913 } 914 } 915 916 byen = byteen_end | (byteen_end >> 4); 917 ret = set_registers(tp, index, type | byen, 4, data); 918 if (ret < 0) 919 goto error1; 920 } 921 922 error1: 923 if (ret == -ENODEV) 924 set_bit(RTL8152_UNPLUG, &tp->flags); 925 926 return ret; 927 } 928 929 static inline 930 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 931 { 932 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 933 } 934 935 static inline 936 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 937 { 938 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 939 } 940 941 static inline 942 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 943 { 944 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 945 } 946 947 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 948 { 949 __le32 data; 950 951 generic_ocp_read(tp, index, sizeof(data), &data, type); 952 953 return __le32_to_cpu(data); 954 } 955 956 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 957 { 958 __le32 tmp = __cpu_to_le32(data); 959 960 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 961 } 962 963 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 964 { 965 u32 data; 966 __le32 tmp; 967 u16 byen = BYTE_EN_WORD; 968 u8 shift = index & 2; 969 970 index &= ~3; 971 byen <<= shift; 972 973 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen); 974 975 data = __le32_to_cpu(tmp); 976 data >>= (shift * 8); 977 data &= 0xffff; 978 979 return (u16)data; 980 } 981 982 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 983 { 984 u32 mask = 0xffff; 985 __le32 tmp; 986 u16 byen = BYTE_EN_WORD; 987 u8 shift = index & 2; 988 989 data &= mask; 990 991 if (index & 2) { 992 byen <<= shift; 993 mask <<= (shift * 8); 994 data <<= (shift * 8); 995 index &= ~3; 996 } 997 998 tmp = __cpu_to_le32(data); 999 1000 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1001 } 1002 1003 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 1004 { 1005 u32 data; 1006 __le32 tmp; 1007 u8 shift = index & 3; 1008 1009 index &= ~3; 1010 1011 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 1012 1013 data = __le32_to_cpu(tmp); 1014 data >>= (shift * 8); 1015 data &= 0xff; 1016 1017 return (u8)data; 1018 } 1019 1020 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 1021 { 1022 u32 mask = 0xff; 1023 __le32 tmp; 1024 u16 byen = BYTE_EN_BYTE; 1025 u8 shift = index & 3; 1026 1027 data &= mask; 1028 1029 if (index & 3) { 1030 byen <<= shift; 1031 mask <<= (shift * 8); 1032 data <<= (shift * 8); 1033 index &= ~3; 1034 } 1035 1036 tmp = __cpu_to_le32(data); 1037 1038 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1039 } 1040 1041 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 1042 { 1043 u16 ocp_base, ocp_index; 1044 1045 ocp_base = addr & 0xf000; 1046 if (ocp_base != tp->ocp_base) { 1047 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1048 tp->ocp_base = ocp_base; 1049 } 1050 1051 ocp_index = (addr & 0x0fff) | 0xb000; 1052 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 1053 } 1054 1055 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 1056 { 1057 u16 ocp_base, ocp_index; 1058 1059 ocp_base = addr & 0xf000; 1060 if (ocp_base != tp->ocp_base) { 1061 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1062 tp->ocp_base = ocp_base; 1063 } 1064 1065 ocp_index = (addr & 0x0fff) | 0xb000; 1066 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 1067 } 1068 1069 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 1070 { 1071 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 1072 } 1073 1074 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 1075 { 1076 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 1077 } 1078 1079 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 1080 { 1081 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1082 ocp_reg_write(tp, OCP_SRAM_DATA, data); 1083 } 1084 1085 static u16 sram_read(struct r8152 *tp, u16 addr) 1086 { 1087 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1088 return ocp_reg_read(tp, OCP_SRAM_DATA); 1089 } 1090 1091 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 1092 { 1093 struct r8152 *tp = netdev_priv(netdev); 1094 int ret; 1095 1096 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1097 return -ENODEV; 1098 1099 if (phy_id != R8152_PHY_ID) 1100 return -EINVAL; 1101 1102 ret = r8152_mdio_read(tp, reg); 1103 1104 return ret; 1105 } 1106 1107 static 1108 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 1109 { 1110 struct r8152 *tp = netdev_priv(netdev); 1111 1112 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1113 return; 1114 1115 if (phy_id != R8152_PHY_ID) 1116 return; 1117 1118 r8152_mdio_write(tp, reg, val); 1119 } 1120 1121 static int 1122 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 1123 1124 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1125 { 1126 struct r8152 *tp = netdev_priv(netdev); 1127 struct sockaddr *addr = p; 1128 int ret = -EADDRNOTAVAIL; 1129 1130 if (!is_valid_ether_addr(addr->sa_data)) 1131 goto out1; 1132 1133 ret = usb_autopm_get_interface(tp->intf); 1134 if (ret < 0) 1135 goto out1; 1136 1137 mutex_lock(&tp->control); 1138 1139 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1140 1141 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1142 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1143 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1144 1145 mutex_unlock(&tp->control); 1146 1147 usb_autopm_put_interface(tp->intf); 1148 out1: 1149 return ret; 1150 } 1151 1152 /* Devices containing proper chips can support a persistent 1153 * host system provided MAC address. 1154 * Examples of this are Dell TB15 and Dell WD15 docks 1155 */ 1156 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) 1157 { 1158 acpi_status status; 1159 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1160 union acpi_object *obj; 1161 int ret = -EINVAL; 1162 u32 ocp_data; 1163 unsigned char buf[6]; 1164 1165 /* test for -AD variant of RTL8153 */ 1166 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 1167 if ((ocp_data & AD_MASK) == 0x1000) { 1168 /* test for MAC address pass-through bit */ 1169 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); 1170 if ((ocp_data & PASS_THRU_MASK) != 1) { 1171 netif_dbg(tp, probe, tp->netdev, 1172 "No efuse for RTL8153-AD MAC pass through\n"); 1173 return -ENODEV; 1174 } 1175 } else { 1176 /* test for RTL8153-BND and RTL8153-BD */ 1177 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); 1178 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) { 1179 netif_dbg(tp, probe, tp->netdev, 1180 "Invalid variant for MAC pass through\n"); 1181 return -ENODEV; 1182 } 1183 } 1184 1185 /* returns _AUXMAC_#AABBCCDDEEFF# */ 1186 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer); 1187 obj = (union acpi_object *)buffer.pointer; 1188 if (!ACPI_SUCCESS(status)) 1189 return -ENODEV; 1190 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) { 1191 netif_warn(tp, probe, tp->netdev, 1192 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", 1193 obj->type, obj->string.length); 1194 goto amacout; 1195 } 1196 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || 1197 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { 1198 netif_warn(tp, probe, tp->netdev, 1199 "Invalid header when reading pass-thru MAC addr\n"); 1200 goto amacout; 1201 } 1202 ret = hex2bin(buf, obj->string.pointer + 9, 6); 1203 if (!(ret == 0 && is_valid_ether_addr(buf))) { 1204 netif_warn(tp, probe, tp->netdev, 1205 "Invalid MAC for pass-thru MAC addr: %d, %pM\n", 1206 ret, buf); 1207 ret = -EINVAL; 1208 goto amacout; 1209 } 1210 memcpy(sa->sa_data, buf, 6); 1211 netif_info(tp, probe, tp->netdev, 1212 "Using pass-thru MAC addr %pM\n", sa->sa_data); 1213 1214 amacout: 1215 kfree(obj); 1216 return ret; 1217 } 1218 1219 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa) 1220 { 1221 struct net_device *dev = tp->netdev; 1222 int ret; 1223 1224 sa->sa_family = dev->type; 1225 1226 if (tp->version == RTL_VER_01) { 1227 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data); 1228 } else { 1229 /* if device doesn't support MAC pass through this will 1230 * be expected to be non-zero 1231 */ 1232 ret = vendor_mac_passthru_addr_read(tp, sa); 1233 if (ret < 0) 1234 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa->sa_data); 1235 } 1236 1237 if (ret < 0) { 1238 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1239 } else if (!is_valid_ether_addr(sa->sa_data)) { 1240 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1241 sa->sa_data); 1242 eth_hw_addr_random(dev); 1243 ether_addr_copy(sa->sa_data, dev->dev_addr); 1244 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1245 sa->sa_data); 1246 return 0; 1247 } 1248 1249 return ret; 1250 } 1251 1252 static int set_ethernet_addr(struct r8152 *tp) 1253 { 1254 struct net_device *dev = tp->netdev; 1255 struct sockaddr sa; 1256 int ret; 1257 1258 ret = determine_ethernet_addr(tp, &sa); 1259 if (ret < 0) 1260 return ret; 1261 1262 if (tp->version == RTL_VER_01) 1263 ether_addr_copy(dev->dev_addr, sa.sa_data); 1264 else 1265 ret = rtl8152_set_mac_address(dev, &sa); 1266 1267 return ret; 1268 } 1269 1270 static void read_bulk_callback(struct urb *urb) 1271 { 1272 struct net_device *netdev; 1273 int status = urb->status; 1274 struct rx_agg *agg; 1275 struct r8152 *tp; 1276 unsigned long flags; 1277 1278 agg = urb->context; 1279 if (!agg) 1280 return; 1281 1282 tp = agg->context; 1283 if (!tp) 1284 return; 1285 1286 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1287 return; 1288 1289 if (!test_bit(WORK_ENABLE, &tp->flags)) 1290 return; 1291 1292 netdev = tp->netdev; 1293 1294 /* When link down, the driver would cancel all bulks. */ 1295 /* This avoid the re-submitting bulk */ 1296 if (!netif_carrier_ok(netdev)) 1297 return; 1298 1299 usb_mark_last_busy(tp->udev); 1300 1301 switch (status) { 1302 case 0: 1303 if (urb->actual_length < ETH_ZLEN) 1304 break; 1305 1306 spin_lock_irqsave(&tp->rx_lock, flags); 1307 list_add_tail(&agg->list, &tp->rx_done); 1308 spin_unlock_irqrestore(&tp->rx_lock, flags); 1309 napi_schedule(&tp->napi); 1310 return; 1311 case -ESHUTDOWN: 1312 set_bit(RTL8152_UNPLUG, &tp->flags); 1313 netif_device_detach(tp->netdev); 1314 return; 1315 case -ENOENT: 1316 return; /* the urb is in unlink state */ 1317 case -ETIME: 1318 if (net_ratelimit()) 1319 netdev_warn(netdev, "maybe reset is needed?\n"); 1320 break; 1321 default: 1322 if (net_ratelimit()) 1323 netdev_warn(netdev, "Rx status %d\n", status); 1324 break; 1325 } 1326 1327 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1328 } 1329 1330 static void write_bulk_callback(struct urb *urb) 1331 { 1332 struct net_device_stats *stats; 1333 struct net_device *netdev; 1334 struct tx_agg *agg; 1335 struct r8152 *tp; 1336 unsigned long flags; 1337 int status = urb->status; 1338 1339 agg = urb->context; 1340 if (!agg) 1341 return; 1342 1343 tp = agg->context; 1344 if (!tp) 1345 return; 1346 1347 netdev = tp->netdev; 1348 stats = &netdev->stats; 1349 if (status) { 1350 if (net_ratelimit()) 1351 netdev_warn(netdev, "Tx status %d\n", status); 1352 stats->tx_errors += agg->skb_num; 1353 } else { 1354 stats->tx_packets += agg->skb_num; 1355 stats->tx_bytes += agg->skb_len; 1356 } 1357 1358 spin_lock_irqsave(&tp->tx_lock, flags); 1359 list_add_tail(&agg->list, &tp->tx_free); 1360 spin_unlock_irqrestore(&tp->tx_lock, flags); 1361 1362 usb_autopm_put_interface_async(tp->intf); 1363 1364 if (!netif_carrier_ok(netdev)) 1365 return; 1366 1367 if (!test_bit(WORK_ENABLE, &tp->flags)) 1368 return; 1369 1370 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1371 return; 1372 1373 if (!skb_queue_empty(&tp->tx_queue)) 1374 napi_schedule(&tp->napi); 1375 } 1376 1377 static void intr_callback(struct urb *urb) 1378 { 1379 struct r8152 *tp; 1380 __le16 *d; 1381 int status = urb->status; 1382 int res; 1383 1384 tp = urb->context; 1385 if (!tp) 1386 return; 1387 1388 if (!test_bit(WORK_ENABLE, &tp->flags)) 1389 return; 1390 1391 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1392 return; 1393 1394 switch (status) { 1395 case 0: /* success */ 1396 break; 1397 case -ECONNRESET: /* unlink */ 1398 case -ESHUTDOWN: 1399 netif_device_detach(tp->netdev); 1400 /* fall through */ 1401 case -ENOENT: 1402 case -EPROTO: 1403 netif_info(tp, intr, tp->netdev, 1404 "Stop submitting intr, status %d\n", status); 1405 return; 1406 case -EOVERFLOW: 1407 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1408 goto resubmit; 1409 /* -EPIPE: should clear the halt */ 1410 default: 1411 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1412 goto resubmit; 1413 } 1414 1415 d = urb->transfer_buffer; 1416 if (INTR_LINK & __le16_to_cpu(d[0])) { 1417 if (!netif_carrier_ok(tp->netdev)) { 1418 set_bit(RTL8152_LINK_CHG, &tp->flags); 1419 schedule_delayed_work(&tp->schedule, 0); 1420 } 1421 } else { 1422 if (netif_carrier_ok(tp->netdev)) { 1423 netif_stop_queue(tp->netdev); 1424 set_bit(RTL8152_LINK_CHG, &tp->flags); 1425 schedule_delayed_work(&tp->schedule, 0); 1426 } 1427 } 1428 1429 resubmit: 1430 res = usb_submit_urb(urb, GFP_ATOMIC); 1431 if (res == -ENODEV) { 1432 set_bit(RTL8152_UNPLUG, &tp->flags); 1433 netif_device_detach(tp->netdev); 1434 } else if (res) { 1435 netif_err(tp, intr, tp->netdev, 1436 "can't resubmit intr, status %d\n", res); 1437 } 1438 } 1439 1440 static inline void *rx_agg_align(void *data) 1441 { 1442 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1443 } 1444 1445 static inline void *tx_agg_align(void *data) 1446 { 1447 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1448 } 1449 1450 static void free_all_mem(struct r8152 *tp) 1451 { 1452 int i; 1453 1454 for (i = 0; i < RTL8152_MAX_RX; i++) { 1455 usb_free_urb(tp->rx_info[i].urb); 1456 tp->rx_info[i].urb = NULL; 1457 1458 kfree(tp->rx_info[i].buffer); 1459 tp->rx_info[i].buffer = NULL; 1460 tp->rx_info[i].head = NULL; 1461 } 1462 1463 for (i = 0; i < RTL8152_MAX_TX; i++) { 1464 usb_free_urb(tp->tx_info[i].urb); 1465 tp->tx_info[i].urb = NULL; 1466 1467 kfree(tp->tx_info[i].buffer); 1468 tp->tx_info[i].buffer = NULL; 1469 tp->tx_info[i].head = NULL; 1470 } 1471 1472 usb_free_urb(tp->intr_urb); 1473 tp->intr_urb = NULL; 1474 1475 kfree(tp->intr_buff); 1476 tp->intr_buff = NULL; 1477 } 1478 1479 static int alloc_all_mem(struct r8152 *tp) 1480 { 1481 struct net_device *netdev = tp->netdev; 1482 struct usb_interface *intf = tp->intf; 1483 struct usb_host_interface *alt = intf->cur_altsetting; 1484 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1485 struct urb *urb; 1486 int node, i; 1487 u8 *buf; 1488 1489 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1490 1491 spin_lock_init(&tp->rx_lock); 1492 spin_lock_init(&tp->tx_lock); 1493 INIT_LIST_HEAD(&tp->tx_free); 1494 INIT_LIST_HEAD(&tp->rx_done); 1495 skb_queue_head_init(&tp->tx_queue); 1496 skb_queue_head_init(&tp->rx_queue); 1497 1498 for (i = 0; i < RTL8152_MAX_RX; i++) { 1499 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1500 if (!buf) 1501 goto err1; 1502 1503 if (buf != rx_agg_align(buf)) { 1504 kfree(buf); 1505 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, 1506 node); 1507 if (!buf) 1508 goto err1; 1509 } 1510 1511 urb = usb_alloc_urb(0, GFP_KERNEL); 1512 if (!urb) { 1513 kfree(buf); 1514 goto err1; 1515 } 1516 1517 INIT_LIST_HEAD(&tp->rx_info[i].list); 1518 tp->rx_info[i].context = tp; 1519 tp->rx_info[i].urb = urb; 1520 tp->rx_info[i].buffer = buf; 1521 tp->rx_info[i].head = rx_agg_align(buf); 1522 } 1523 1524 for (i = 0; i < RTL8152_MAX_TX; i++) { 1525 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1526 if (!buf) 1527 goto err1; 1528 1529 if (buf != tx_agg_align(buf)) { 1530 kfree(buf); 1531 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 1532 node); 1533 if (!buf) 1534 goto err1; 1535 } 1536 1537 urb = usb_alloc_urb(0, GFP_KERNEL); 1538 if (!urb) { 1539 kfree(buf); 1540 goto err1; 1541 } 1542 1543 INIT_LIST_HEAD(&tp->tx_info[i].list); 1544 tp->tx_info[i].context = tp; 1545 tp->tx_info[i].urb = urb; 1546 tp->tx_info[i].buffer = buf; 1547 tp->tx_info[i].head = tx_agg_align(buf); 1548 1549 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1550 } 1551 1552 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1553 if (!tp->intr_urb) 1554 goto err1; 1555 1556 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1557 if (!tp->intr_buff) 1558 goto err1; 1559 1560 tp->intr_interval = (int)ep_intr->desc.bInterval; 1561 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1562 tp->intr_buff, INTBUFSIZE, intr_callback, 1563 tp, tp->intr_interval); 1564 1565 return 0; 1566 1567 err1: 1568 free_all_mem(tp); 1569 return -ENOMEM; 1570 } 1571 1572 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1573 { 1574 struct tx_agg *agg = NULL; 1575 unsigned long flags; 1576 1577 if (list_empty(&tp->tx_free)) 1578 return NULL; 1579 1580 spin_lock_irqsave(&tp->tx_lock, flags); 1581 if (!list_empty(&tp->tx_free)) { 1582 struct list_head *cursor; 1583 1584 cursor = tp->tx_free.next; 1585 list_del_init(cursor); 1586 agg = list_entry(cursor, struct tx_agg, list); 1587 } 1588 spin_unlock_irqrestore(&tp->tx_lock, flags); 1589 1590 return agg; 1591 } 1592 1593 /* r8152_csum_workaround() 1594 * The hw limites the value the transport offset. When the offset is out of the 1595 * range, calculate the checksum by sw. 1596 */ 1597 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1598 struct sk_buff_head *list) 1599 { 1600 if (skb_shinfo(skb)->gso_size) { 1601 netdev_features_t features = tp->netdev->features; 1602 struct sk_buff_head seg_list; 1603 struct sk_buff *segs, *nskb; 1604 1605 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 1606 segs = skb_gso_segment(skb, features); 1607 if (IS_ERR(segs) || !segs) 1608 goto drop; 1609 1610 __skb_queue_head_init(&seg_list); 1611 1612 do { 1613 nskb = segs; 1614 segs = segs->next; 1615 nskb->next = NULL; 1616 __skb_queue_tail(&seg_list, nskb); 1617 } while (segs); 1618 1619 skb_queue_splice(&seg_list, list); 1620 dev_kfree_skb(skb); 1621 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1622 if (skb_checksum_help(skb) < 0) 1623 goto drop; 1624 1625 __skb_queue_head(list, skb); 1626 } else { 1627 struct net_device_stats *stats; 1628 1629 drop: 1630 stats = &tp->netdev->stats; 1631 stats->tx_dropped++; 1632 dev_kfree_skb(skb); 1633 } 1634 } 1635 1636 /* msdn_giant_send_check() 1637 * According to the document of microsoft, the TCP Pseudo Header excludes the 1638 * packet length for IPv6 TCP large packets. 1639 */ 1640 static int msdn_giant_send_check(struct sk_buff *skb) 1641 { 1642 const struct ipv6hdr *ipv6h; 1643 struct tcphdr *th; 1644 int ret; 1645 1646 ret = skb_cow_head(skb, 0); 1647 if (ret) 1648 return ret; 1649 1650 ipv6h = ipv6_hdr(skb); 1651 th = tcp_hdr(skb); 1652 1653 th->check = 0; 1654 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1655 1656 return ret; 1657 } 1658 1659 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 1660 { 1661 if (skb_vlan_tag_present(skb)) { 1662 u32 opts2; 1663 1664 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); 1665 desc->opts2 |= cpu_to_le32(opts2); 1666 } 1667 } 1668 1669 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 1670 { 1671 u32 opts2 = le32_to_cpu(desc->opts2); 1672 1673 if (opts2 & RX_VLAN_TAG) 1674 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1675 swab16(opts2 & 0xffff)); 1676 } 1677 1678 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1679 struct sk_buff *skb, u32 len, u32 transport_offset) 1680 { 1681 u32 mss = skb_shinfo(skb)->gso_size; 1682 u32 opts1, opts2 = 0; 1683 int ret = TX_CSUM_SUCCESS; 1684 1685 WARN_ON_ONCE(len > TX_LEN_MAX); 1686 1687 opts1 = len | TX_FS | TX_LS; 1688 1689 if (mss) { 1690 if (transport_offset > GTTCPHO_MAX) { 1691 netif_warn(tp, tx_err, tp->netdev, 1692 "Invalid transport offset 0x%x for TSO\n", 1693 transport_offset); 1694 ret = TX_CSUM_TSO; 1695 goto unavailable; 1696 } 1697 1698 switch (vlan_get_protocol(skb)) { 1699 case htons(ETH_P_IP): 1700 opts1 |= GTSENDV4; 1701 break; 1702 1703 case htons(ETH_P_IPV6): 1704 if (msdn_giant_send_check(skb)) { 1705 ret = TX_CSUM_TSO; 1706 goto unavailable; 1707 } 1708 opts1 |= GTSENDV6; 1709 break; 1710 1711 default: 1712 WARN_ON_ONCE(1); 1713 break; 1714 } 1715 1716 opts1 |= transport_offset << GTTCPHO_SHIFT; 1717 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1718 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1719 u8 ip_protocol; 1720 1721 if (transport_offset > TCPHO_MAX) { 1722 netif_warn(tp, tx_err, tp->netdev, 1723 "Invalid transport offset 0x%x\n", 1724 transport_offset); 1725 ret = TX_CSUM_NONE; 1726 goto unavailable; 1727 } 1728 1729 switch (vlan_get_protocol(skb)) { 1730 case htons(ETH_P_IP): 1731 opts2 |= IPV4_CS; 1732 ip_protocol = ip_hdr(skb)->protocol; 1733 break; 1734 1735 case htons(ETH_P_IPV6): 1736 opts2 |= IPV6_CS; 1737 ip_protocol = ipv6_hdr(skb)->nexthdr; 1738 break; 1739 1740 default: 1741 ip_protocol = IPPROTO_RAW; 1742 break; 1743 } 1744 1745 if (ip_protocol == IPPROTO_TCP) 1746 opts2 |= TCP_CS; 1747 else if (ip_protocol == IPPROTO_UDP) 1748 opts2 |= UDP_CS; 1749 else 1750 WARN_ON_ONCE(1); 1751 1752 opts2 |= transport_offset << TCPHO_SHIFT; 1753 } 1754 1755 desc->opts2 = cpu_to_le32(opts2); 1756 desc->opts1 = cpu_to_le32(opts1); 1757 1758 unavailable: 1759 return ret; 1760 } 1761 1762 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1763 { 1764 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1765 int remain, ret; 1766 u8 *tx_data; 1767 1768 __skb_queue_head_init(&skb_head); 1769 spin_lock(&tx_queue->lock); 1770 skb_queue_splice_init(tx_queue, &skb_head); 1771 spin_unlock(&tx_queue->lock); 1772 1773 tx_data = agg->head; 1774 agg->skb_num = 0; 1775 agg->skb_len = 0; 1776 remain = agg_buf_sz; 1777 1778 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1779 struct tx_desc *tx_desc; 1780 struct sk_buff *skb; 1781 unsigned int len; 1782 u32 offset; 1783 1784 skb = __skb_dequeue(&skb_head); 1785 if (!skb) 1786 break; 1787 1788 len = skb->len + sizeof(*tx_desc); 1789 1790 if (len > remain) { 1791 __skb_queue_head(&skb_head, skb); 1792 break; 1793 } 1794 1795 tx_data = tx_agg_align(tx_data); 1796 tx_desc = (struct tx_desc *)tx_data; 1797 1798 offset = (u32)skb_transport_offset(skb); 1799 1800 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1801 r8152_csum_workaround(tp, skb, &skb_head); 1802 continue; 1803 } 1804 1805 rtl_tx_vlan_tag(tx_desc, skb); 1806 1807 tx_data += sizeof(*tx_desc); 1808 1809 len = skb->len; 1810 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1811 struct net_device_stats *stats = &tp->netdev->stats; 1812 1813 stats->tx_dropped++; 1814 dev_kfree_skb_any(skb); 1815 tx_data -= sizeof(*tx_desc); 1816 continue; 1817 } 1818 1819 tx_data += len; 1820 agg->skb_len += len; 1821 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1; 1822 1823 dev_kfree_skb_any(skb); 1824 1825 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1826 1827 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags)) 1828 break; 1829 } 1830 1831 if (!skb_queue_empty(&skb_head)) { 1832 spin_lock(&tx_queue->lock); 1833 skb_queue_splice(&skb_head, tx_queue); 1834 spin_unlock(&tx_queue->lock); 1835 } 1836 1837 netif_tx_lock(tp->netdev); 1838 1839 if (netif_queue_stopped(tp->netdev) && 1840 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1841 netif_wake_queue(tp->netdev); 1842 1843 netif_tx_unlock(tp->netdev); 1844 1845 ret = usb_autopm_get_interface_async(tp->intf); 1846 if (ret < 0) 1847 goto out_tx_fill; 1848 1849 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1850 agg->head, (int)(tx_data - (u8 *)agg->head), 1851 (usb_complete_t)write_bulk_callback, agg); 1852 1853 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1854 if (ret < 0) 1855 usb_autopm_put_interface_async(tp->intf); 1856 1857 out_tx_fill: 1858 return ret; 1859 } 1860 1861 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1862 { 1863 u8 checksum = CHECKSUM_NONE; 1864 u32 opts2, opts3; 1865 1866 if (!(tp->netdev->features & NETIF_F_RXCSUM)) 1867 goto return_result; 1868 1869 opts2 = le32_to_cpu(rx_desc->opts2); 1870 opts3 = le32_to_cpu(rx_desc->opts3); 1871 1872 if (opts2 & RD_IPV4_CS) { 1873 if (opts3 & IPF) 1874 checksum = CHECKSUM_NONE; 1875 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1876 checksum = CHECKSUM_UNNECESSARY; 1877 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1878 checksum = CHECKSUM_UNNECESSARY; 1879 } else if (opts2 & RD_IPV6_CS) { 1880 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1881 checksum = CHECKSUM_UNNECESSARY; 1882 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1883 checksum = CHECKSUM_UNNECESSARY; 1884 } 1885 1886 return_result: 1887 return checksum; 1888 } 1889 1890 static int rx_bottom(struct r8152 *tp, int budget) 1891 { 1892 unsigned long flags; 1893 struct list_head *cursor, *next, rx_queue; 1894 int ret = 0, work_done = 0; 1895 struct napi_struct *napi = &tp->napi; 1896 1897 if (!skb_queue_empty(&tp->rx_queue)) { 1898 while (work_done < budget) { 1899 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); 1900 struct net_device *netdev = tp->netdev; 1901 struct net_device_stats *stats = &netdev->stats; 1902 unsigned int pkt_len; 1903 1904 if (!skb) 1905 break; 1906 1907 pkt_len = skb->len; 1908 napi_gro_receive(napi, skb); 1909 work_done++; 1910 stats->rx_packets++; 1911 stats->rx_bytes += pkt_len; 1912 } 1913 } 1914 1915 if (list_empty(&tp->rx_done)) 1916 goto out1; 1917 1918 INIT_LIST_HEAD(&rx_queue); 1919 spin_lock_irqsave(&tp->rx_lock, flags); 1920 list_splice_init(&tp->rx_done, &rx_queue); 1921 spin_unlock_irqrestore(&tp->rx_lock, flags); 1922 1923 list_for_each_safe(cursor, next, &rx_queue) { 1924 struct rx_desc *rx_desc; 1925 struct rx_agg *agg; 1926 int len_used = 0; 1927 struct urb *urb; 1928 u8 *rx_data; 1929 1930 list_del_init(cursor); 1931 1932 agg = list_entry(cursor, struct rx_agg, list); 1933 urb = agg->urb; 1934 if (urb->actual_length < ETH_ZLEN) 1935 goto submit; 1936 1937 rx_desc = agg->head; 1938 rx_data = agg->head; 1939 len_used += sizeof(struct rx_desc); 1940 1941 while (urb->actual_length > len_used) { 1942 struct net_device *netdev = tp->netdev; 1943 struct net_device_stats *stats = &netdev->stats; 1944 unsigned int pkt_len; 1945 struct sk_buff *skb; 1946 1947 /* limite the skb numbers for rx_queue */ 1948 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000)) 1949 break; 1950 1951 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1952 if (pkt_len < ETH_ZLEN) 1953 break; 1954 1955 len_used += pkt_len; 1956 if (urb->actual_length < len_used) 1957 break; 1958 1959 pkt_len -= ETH_FCS_LEN; 1960 rx_data += sizeof(struct rx_desc); 1961 1962 skb = napi_alloc_skb(napi, pkt_len); 1963 if (!skb) { 1964 stats->rx_dropped++; 1965 goto find_next_rx; 1966 } 1967 1968 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 1969 memcpy(skb->data, rx_data, pkt_len); 1970 skb_put(skb, pkt_len); 1971 skb->protocol = eth_type_trans(skb, netdev); 1972 rtl_rx_vlan_tag(rx_desc, skb); 1973 if (work_done < budget) { 1974 napi_gro_receive(napi, skb); 1975 work_done++; 1976 stats->rx_packets++; 1977 stats->rx_bytes += pkt_len; 1978 } else { 1979 __skb_queue_tail(&tp->rx_queue, skb); 1980 } 1981 1982 find_next_rx: 1983 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN); 1984 rx_desc = (struct rx_desc *)rx_data; 1985 len_used = (int)(rx_data - (u8 *)agg->head); 1986 len_used += sizeof(struct rx_desc); 1987 } 1988 1989 submit: 1990 if (!ret) { 1991 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1992 } else { 1993 urb->actual_length = 0; 1994 list_add_tail(&agg->list, next); 1995 } 1996 } 1997 1998 if (!list_empty(&rx_queue)) { 1999 spin_lock_irqsave(&tp->rx_lock, flags); 2000 list_splice_tail(&rx_queue, &tp->rx_done); 2001 spin_unlock_irqrestore(&tp->rx_lock, flags); 2002 } 2003 2004 out1: 2005 return work_done; 2006 } 2007 2008 static void tx_bottom(struct r8152 *tp) 2009 { 2010 int res; 2011 2012 do { 2013 struct tx_agg *agg; 2014 2015 if (skb_queue_empty(&tp->tx_queue)) 2016 break; 2017 2018 agg = r8152_get_tx_agg(tp); 2019 if (!agg) 2020 break; 2021 2022 res = r8152_tx_agg_fill(tp, agg); 2023 if (res) { 2024 struct net_device *netdev = tp->netdev; 2025 2026 if (res == -ENODEV) { 2027 set_bit(RTL8152_UNPLUG, &tp->flags); 2028 netif_device_detach(netdev); 2029 } else { 2030 struct net_device_stats *stats = &netdev->stats; 2031 unsigned long flags; 2032 2033 netif_warn(tp, tx_err, netdev, 2034 "failed tx_urb %d\n", res); 2035 stats->tx_dropped += agg->skb_num; 2036 2037 spin_lock_irqsave(&tp->tx_lock, flags); 2038 list_add_tail(&agg->list, &tp->tx_free); 2039 spin_unlock_irqrestore(&tp->tx_lock, flags); 2040 } 2041 } 2042 } while (res == 0); 2043 } 2044 2045 static void bottom_half(struct r8152 *tp) 2046 { 2047 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2048 return; 2049 2050 if (!test_bit(WORK_ENABLE, &tp->flags)) 2051 return; 2052 2053 /* When link down, the driver would cancel all bulks. */ 2054 /* This avoid the re-submitting bulk */ 2055 if (!netif_carrier_ok(tp->netdev)) 2056 return; 2057 2058 clear_bit(SCHEDULE_NAPI, &tp->flags); 2059 2060 tx_bottom(tp); 2061 } 2062 2063 static int r8152_poll(struct napi_struct *napi, int budget) 2064 { 2065 struct r8152 *tp = container_of(napi, struct r8152, napi); 2066 int work_done; 2067 2068 work_done = rx_bottom(tp, budget); 2069 bottom_half(tp); 2070 2071 if (work_done < budget) { 2072 if (!napi_complete_done(napi, work_done)) 2073 goto out; 2074 if (!list_empty(&tp->rx_done)) 2075 napi_schedule(napi); 2076 else if (!skb_queue_empty(&tp->tx_queue) && 2077 !list_empty(&tp->tx_free)) 2078 napi_schedule(napi); 2079 } 2080 2081 out: 2082 return work_done; 2083 } 2084 2085 static 2086 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 2087 { 2088 int ret; 2089 2090 /* The rx would be stopped, so skip submitting */ 2091 if (test_bit(RTL8152_UNPLUG, &tp->flags) || 2092 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) 2093 return 0; 2094 2095 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 2096 agg->head, agg_buf_sz, 2097 (usb_complete_t)read_bulk_callback, agg); 2098 2099 ret = usb_submit_urb(agg->urb, mem_flags); 2100 if (ret == -ENODEV) { 2101 set_bit(RTL8152_UNPLUG, &tp->flags); 2102 netif_device_detach(tp->netdev); 2103 } else if (ret) { 2104 struct urb *urb = agg->urb; 2105 unsigned long flags; 2106 2107 urb->actual_length = 0; 2108 spin_lock_irqsave(&tp->rx_lock, flags); 2109 list_add_tail(&agg->list, &tp->rx_done); 2110 spin_unlock_irqrestore(&tp->rx_lock, flags); 2111 2112 netif_err(tp, rx_err, tp->netdev, 2113 "Couldn't submit rx[%p], ret = %d\n", agg, ret); 2114 2115 napi_schedule(&tp->napi); 2116 } 2117 2118 return ret; 2119 } 2120 2121 static void rtl_drop_queued_tx(struct r8152 *tp) 2122 { 2123 struct net_device_stats *stats = &tp->netdev->stats; 2124 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 2125 struct sk_buff *skb; 2126 2127 if (skb_queue_empty(tx_queue)) 2128 return; 2129 2130 __skb_queue_head_init(&skb_head); 2131 spin_lock_bh(&tx_queue->lock); 2132 skb_queue_splice_init(tx_queue, &skb_head); 2133 spin_unlock_bh(&tx_queue->lock); 2134 2135 while ((skb = __skb_dequeue(&skb_head))) { 2136 dev_kfree_skb(skb); 2137 stats->tx_dropped++; 2138 } 2139 } 2140 2141 static void rtl8152_tx_timeout(struct net_device *netdev) 2142 { 2143 struct r8152 *tp = netdev_priv(netdev); 2144 2145 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 2146 2147 usb_queue_reset_device(tp->intf); 2148 } 2149 2150 static void rtl8152_set_rx_mode(struct net_device *netdev) 2151 { 2152 struct r8152 *tp = netdev_priv(netdev); 2153 2154 if (netif_carrier_ok(netdev)) { 2155 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2156 schedule_delayed_work(&tp->schedule, 0); 2157 } 2158 } 2159 2160 static void _rtl8152_set_rx_mode(struct net_device *netdev) 2161 { 2162 struct r8152 *tp = netdev_priv(netdev); 2163 u32 mc_filter[2]; /* Multicast hash filter */ 2164 __le32 tmp[2]; 2165 u32 ocp_data; 2166 2167 netif_stop_queue(netdev); 2168 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2169 ocp_data &= ~RCR_ACPT_ALL; 2170 ocp_data |= RCR_AB | RCR_APM; 2171 2172 if (netdev->flags & IFF_PROMISC) { 2173 /* Unconditionally log net taps. */ 2174 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 2175 ocp_data |= RCR_AM | RCR_AAP; 2176 mc_filter[1] = 0xffffffff; 2177 mc_filter[0] = 0xffffffff; 2178 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 2179 (netdev->flags & IFF_ALLMULTI)) { 2180 /* Too many to filter perfectly -- accept all multicasts. */ 2181 ocp_data |= RCR_AM; 2182 mc_filter[1] = 0xffffffff; 2183 mc_filter[0] = 0xffffffff; 2184 } else { 2185 struct netdev_hw_addr *ha; 2186 2187 mc_filter[1] = 0; 2188 mc_filter[0] = 0; 2189 netdev_for_each_mc_addr(ha, netdev) { 2190 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2191 2192 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2193 ocp_data |= RCR_AM; 2194 } 2195 } 2196 2197 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 2198 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 2199 2200 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 2201 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2202 netif_wake_queue(netdev); 2203 } 2204 2205 static netdev_features_t 2206 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 2207 netdev_features_t features) 2208 { 2209 u32 mss = skb_shinfo(skb)->gso_size; 2210 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 2211 int offset = skb_transport_offset(skb); 2212 2213 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) 2214 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2215 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 2216 features &= ~NETIF_F_GSO_MASK; 2217 2218 return features; 2219 } 2220 2221 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 2222 struct net_device *netdev) 2223 { 2224 struct r8152 *tp = netdev_priv(netdev); 2225 2226 skb_tx_timestamp(skb); 2227 2228 skb_queue_tail(&tp->tx_queue, skb); 2229 2230 if (!list_empty(&tp->tx_free)) { 2231 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2232 set_bit(SCHEDULE_NAPI, &tp->flags); 2233 schedule_delayed_work(&tp->schedule, 0); 2234 } else { 2235 usb_mark_last_busy(tp->udev); 2236 napi_schedule(&tp->napi); 2237 } 2238 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 2239 netif_stop_queue(netdev); 2240 } 2241 2242 return NETDEV_TX_OK; 2243 } 2244 2245 static void r8152b_reset_packet_filter(struct r8152 *tp) 2246 { 2247 u32 ocp_data; 2248 2249 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 2250 ocp_data &= ~FMC_FCR_MCU_EN; 2251 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2252 ocp_data |= FMC_FCR_MCU_EN; 2253 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2254 } 2255 2256 static void rtl8152_nic_reset(struct r8152 *tp) 2257 { 2258 int i; 2259 2260 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 2261 2262 for (i = 0; i < 1000; i++) { 2263 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 2264 break; 2265 usleep_range(100, 400); 2266 } 2267 } 2268 2269 static void set_tx_qlen(struct r8152 *tp) 2270 { 2271 struct net_device *netdev = tp->netdev; 2272 2273 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN + 2274 sizeof(struct tx_desc)); 2275 } 2276 2277 static inline u8 rtl8152_get_speed(struct r8152 *tp) 2278 { 2279 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 2280 } 2281 2282 static void rtl_set_eee_plus(struct r8152 *tp) 2283 { 2284 u32 ocp_data; 2285 u8 speed; 2286 2287 speed = rtl8152_get_speed(tp); 2288 if (speed & _10bps) { 2289 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2290 ocp_data |= EEEP_CR_EEEP_TX; 2291 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2292 } else { 2293 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2294 ocp_data &= ~EEEP_CR_EEEP_TX; 2295 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2296 } 2297 } 2298 2299 static void rxdy_gated_en(struct r8152 *tp, bool enable) 2300 { 2301 u32 ocp_data; 2302 2303 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 2304 if (enable) 2305 ocp_data |= RXDY_GATED_EN; 2306 else 2307 ocp_data &= ~RXDY_GATED_EN; 2308 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 2309 } 2310 2311 static int rtl_start_rx(struct r8152 *tp) 2312 { 2313 int i, ret = 0; 2314 2315 INIT_LIST_HEAD(&tp->rx_done); 2316 for (i = 0; i < RTL8152_MAX_RX; i++) { 2317 INIT_LIST_HEAD(&tp->rx_info[i].list); 2318 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 2319 if (ret) 2320 break; 2321 } 2322 2323 if (ret && ++i < RTL8152_MAX_RX) { 2324 struct list_head rx_queue; 2325 unsigned long flags; 2326 2327 INIT_LIST_HEAD(&rx_queue); 2328 2329 do { 2330 struct rx_agg *agg = &tp->rx_info[i++]; 2331 struct urb *urb = agg->urb; 2332 2333 urb->actual_length = 0; 2334 list_add_tail(&agg->list, &rx_queue); 2335 } while (i < RTL8152_MAX_RX); 2336 2337 spin_lock_irqsave(&tp->rx_lock, flags); 2338 list_splice_tail(&rx_queue, &tp->rx_done); 2339 spin_unlock_irqrestore(&tp->rx_lock, flags); 2340 } 2341 2342 return ret; 2343 } 2344 2345 static int rtl_stop_rx(struct r8152 *tp) 2346 { 2347 int i; 2348 2349 for (i = 0; i < RTL8152_MAX_RX; i++) 2350 usb_kill_urb(tp->rx_info[i].urb); 2351 2352 while (!skb_queue_empty(&tp->rx_queue)) 2353 dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); 2354 2355 return 0; 2356 } 2357 2358 static int rtl_enable(struct r8152 *tp) 2359 { 2360 u32 ocp_data; 2361 2362 r8152b_reset_packet_filter(tp); 2363 2364 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2365 ocp_data |= CR_RE | CR_TE; 2366 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2367 2368 rxdy_gated_en(tp, false); 2369 2370 return 0; 2371 } 2372 2373 static int rtl8152_enable(struct r8152 *tp) 2374 { 2375 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2376 return -ENODEV; 2377 2378 set_tx_qlen(tp); 2379 rtl_set_eee_plus(tp); 2380 2381 return rtl_enable(tp); 2382 } 2383 2384 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) 2385 { 2386 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, 2387 OWN_UPDATE | OWN_CLEAR); 2388 } 2389 2390 static void r8153_set_rx_early_timeout(struct r8152 *tp) 2391 { 2392 u32 ocp_data = tp->coalesce / 8; 2393 2394 switch (tp->version) { 2395 case RTL_VER_03: 2396 case RTL_VER_04: 2397 case RTL_VER_05: 2398 case RTL_VER_06: 2399 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2400 ocp_data); 2401 break; 2402 2403 case RTL_VER_08: 2404 case RTL_VER_09: 2405 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout 2406 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns. 2407 */ 2408 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2409 128 / 8); 2410 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, 2411 ocp_data); 2412 r8153b_rx_agg_chg_indicate(tp); 2413 break; 2414 2415 default: 2416 break; 2417 } 2418 } 2419 2420 static void r8153_set_rx_early_size(struct r8152 *tp) 2421 { 2422 u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu); 2423 2424 switch (tp->version) { 2425 case RTL_VER_03: 2426 case RTL_VER_04: 2427 case RTL_VER_05: 2428 case RTL_VER_06: 2429 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2430 ocp_data / 4); 2431 break; 2432 case RTL_VER_08: 2433 case RTL_VER_09: 2434 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2435 ocp_data / 8); 2436 r8153b_rx_agg_chg_indicate(tp); 2437 break; 2438 default: 2439 WARN_ON_ONCE(1); 2440 break; 2441 } 2442 } 2443 2444 static int rtl8153_enable(struct r8152 *tp) 2445 { 2446 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2447 return -ENODEV; 2448 2449 set_tx_qlen(tp); 2450 rtl_set_eee_plus(tp); 2451 r8153_set_rx_early_timeout(tp); 2452 r8153_set_rx_early_size(tp); 2453 2454 return rtl_enable(tp); 2455 } 2456 2457 static void rtl_disable(struct r8152 *tp) 2458 { 2459 u32 ocp_data; 2460 int i; 2461 2462 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2463 rtl_drop_queued_tx(tp); 2464 return; 2465 } 2466 2467 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2468 ocp_data &= ~RCR_ACPT_ALL; 2469 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2470 2471 rtl_drop_queued_tx(tp); 2472 2473 for (i = 0; i < RTL8152_MAX_TX; i++) 2474 usb_kill_urb(tp->tx_info[i].urb); 2475 2476 rxdy_gated_en(tp, true); 2477 2478 for (i = 0; i < 1000; i++) { 2479 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2480 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2481 break; 2482 usleep_range(1000, 2000); 2483 } 2484 2485 for (i = 0; i < 1000; i++) { 2486 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2487 break; 2488 usleep_range(1000, 2000); 2489 } 2490 2491 rtl_stop_rx(tp); 2492 2493 rtl8152_nic_reset(tp); 2494 } 2495 2496 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2497 { 2498 u32 ocp_data; 2499 2500 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2501 if (enable) 2502 ocp_data |= POWER_CUT; 2503 else 2504 ocp_data &= ~POWER_CUT; 2505 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2506 2507 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2508 ocp_data &= ~RESUME_INDICATE; 2509 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2510 } 2511 2512 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 2513 { 2514 u32 ocp_data; 2515 2516 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2517 if (enable) 2518 ocp_data |= CPCR_RX_VLAN; 2519 else 2520 ocp_data &= ~CPCR_RX_VLAN; 2521 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2522 } 2523 2524 static int rtl8152_set_features(struct net_device *dev, 2525 netdev_features_t features) 2526 { 2527 netdev_features_t changed = features ^ dev->features; 2528 struct r8152 *tp = netdev_priv(dev); 2529 int ret; 2530 2531 ret = usb_autopm_get_interface(tp->intf); 2532 if (ret < 0) 2533 goto out; 2534 2535 mutex_lock(&tp->control); 2536 2537 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 2538 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2539 rtl_rx_vlan_en(tp, true); 2540 else 2541 rtl_rx_vlan_en(tp, false); 2542 } 2543 2544 mutex_unlock(&tp->control); 2545 2546 usb_autopm_put_interface(tp->intf); 2547 2548 out: 2549 return ret; 2550 } 2551 2552 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2553 2554 static u32 __rtl_get_wol(struct r8152 *tp) 2555 { 2556 u32 ocp_data; 2557 u32 wolopts = 0; 2558 2559 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2560 if (ocp_data & LINK_ON_WAKE_EN) 2561 wolopts |= WAKE_PHY; 2562 2563 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2564 if (ocp_data & UWF_EN) 2565 wolopts |= WAKE_UCAST; 2566 if (ocp_data & BWF_EN) 2567 wolopts |= WAKE_BCAST; 2568 if (ocp_data & MWF_EN) 2569 wolopts |= WAKE_MCAST; 2570 2571 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2572 if (ocp_data & MAGIC_EN) 2573 wolopts |= WAKE_MAGIC; 2574 2575 return wolopts; 2576 } 2577 2578 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2579 { 2580 u32 ocp_data; 2581 2582 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2583 2584 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2585 ocp_data &= ~LINK_ON_WAKE_EN; 2586 if (wolopts & WAKE_PHY) 2587 ocp_data |= LINK_ON_WAKE_EN; 2588 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2589 2590 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2591 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); 2592 if (wolopts & WAKE_UCAST) 2593 ocp_data |= UWF_EN; 2594 if (wolopts & WAKE_BCAST) 2595 ocp_data |= BWF_EN; 2596 if (wolopts & WAKE_MCAST) 2597 ocp_data |= MWF_EN; 2598 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2599 2600 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2601 2602 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2603 ocp_data &= ~MAGIC_EN; 2604 if (wolopts & WAKE_MAGIC) 2605 ocp_data |= MAGIC_EN; 2606 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2607 2608 if (wolopts & WAKE_ANY) 2609 device_set_wakeup_enable(&tp->udev->dev, true); 2610 else 2611 device_set_wakeup_enable(&tp->udev->dev, false); 2612 } 2613 2614 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable) 2615 { 2616 /* MAC clock speed down */ 2617 if (enable) { 2618 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 2619 ALDPS_SPDWN_RATIO); 2620 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 2621 EEE_SPDWN_RATIO); 2622 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 2623 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | 2624 U1U2_SPDWN_EN | L1_SPDWN_EN); 2625 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 2626 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | 2627 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN | 2628 TP1000_SPDWN_EN); 2629 } else { 2630 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); 2631 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); 2632 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); 2633 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); 2634 } 2635 } 2636 2637 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2638 { 2639 u8 u1u2[8]; 2640 2641 if (enable) 2642 memset(u1u2, 0xff, sizeof(u1u2)); 2643 else 2644 memset(u1u2, 0x00, sizeof(u1u2)); 2645 2646 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2647 } 2648 2649 static void r8153b_u1u2en(struct r8152 *tp, bool enable) 2650 { 2651 u32 ocp_data; 2652 2653 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); 2654 if (enable) 2655 ocp_data |= LPM_U1U2_EN; 2656 else 2657 ocp_data &= ~LPM_U1U2_EN; 2658 2659 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); 2660 } 2661 2662 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2663 { 2664 u32 ocp_data; 2665 2666 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2667 if (enable) 2668 ocp_data |= U2P3_ENABLE; 2669 else 2670 ocp_data &= ~U2P3_ENABLE; 2671 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2672 } 2673 2674 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear) 2675 { 2676 u32 ocp_data; 2677 2678 ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS); 2679 ocp_data &= ~clear; 2680 ocp_data |= set; 2681 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data); 2682 } 2683 2684 static void r8153b_green_en(struct r8152 *tp, bool enable) 2685 { 2686 u16 data; 2687 2688 if (enable) { 2689 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ 2690 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ 2691 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ 2692 } else { 2693 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ 2694 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ 2695 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ 2696 } 2697 2698 data = sram_read(tp, SRAM_GREEN_CFG); 2699 data |= GREEN_ETH_EN; 2700 sram_write(tp, SRAM_GREEN_CFG, data); 2701 2702 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0); 2703 } 2704 2705 static u16 r8153_phy_status(struct r8152 *tp, u16 desired) 2706 { 2707 u16 data; 2708 int i; 2709 2710 for (i = 0; i < 500; i++) { 2711 data = ocp_reg_read(tp, OCP_PHY_STATUS); 2712 data &= PHY_STAT_MASK; 2713 if (desired) { 2714 if (data == desired) 2715 break; 2716 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN || 2717 data == PHY_STAT_EXT_INIT) { 2718 break; 2719 } 2720 2721 msleep(20); 2722 } 2723 2724 return data; 2725 } 2726 2727 static void r8153b_ups_en(struct r8152 *tp, bool enable) 2728 { 2729 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); 2730 2731 if (enable) { 2732 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; 2733 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2734 2735 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 2736 ocp_data |= BIT(0); 2737 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 2738 } else { 2739 u16 data; 2740 2741 ocp_data &= ~(UPS_EN | USP_PREWAKE); 2742 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2743 2744 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 2745 ocp_data &= ~BIT(0); 2746 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 2747 2748 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2749 ocp_data &= ~PCUT_STATUS; 2750 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2751 2752 data = r8153_phy_status(tp, 0); 2753 2754 switch (data) { 2755 case PHY_STAT_PWRDN: 2756 case PHY_STAT_EXT_INIT: 2757 r8153b_green_en(tp, 2758 test_bit(GREEN_ETHERNET, &tp->flags)); 2759 2760 data = r8152_mdio_read(tp, MII_BMCR); 2761 data &= ~BMCR_PDOWN; 2762 data |= BMCR_RESET; 2763 r8152_mdio_write(tp, MII_BMCR, data); 2764 2765 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 2766 /* fall through */ 2767 2768 default: 2769 if (data != PHY_STAT_LAN_ON) 2770 netif_warn(tp, link, tp->netdev, 2771 "PHY not ready"); 2772 break; 2773 } 2774 } 2775 } 2776 2777 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2778 { 2779 u32 ocp_data; 2780 2781 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2782 if (enable) 2783 ocp_data |= PWR_EN | PHASE2_EN; 2784 else 2785 ocp_data &= ~(PWR_EN | PHASE2_EN); 2786 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2787 2788 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2789 ocp_data &= ~PCUT_STATUS; 2790 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2791 } 2792 2793 static void r8153b_power_cut_en(struct r8152 *tp, bool enable) 2794 { 2795 u32 ocp_data; 2796 2797 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2798 if (enable) 2799 ocp_data |= PWR_EN | PHASE2_EN; 2800 else 2801 ocp_data &= ~PWR_EN; 2802 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2803 2804 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2805 ocp_data &= ~PCUT_STATUS; 2806 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2807 } 2808 2809 static void r8153b_queue_wake(struct r8152 *tp, bool enable) 2810 { 2811 u32 ocp_data; 2812 2813 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a); 2814 if (enable) 2815 ocp_data |= BIT(0); 2816 else 2817 ocp_data &= ~BIT(0); 2818 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data); 2819 2820 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c); 2821 ocp_data &= ~BIT(0); 2822 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data); 2823 } 2824 2825 static bool rtl_can_wakeup(struct r8152 *tp) 2826 { 2827 struct usb_device *udev = tp->udev; 2828 2829 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); 2830 } 2831 2832 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 2833 { 2834 if (enable) { 2835 u32 ocp_data; 2836 2837 __rtl_set_wol(tp, WAKE_ANY); 2838 2839 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2840 2841 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2842 ocp_data |= LINK_OFF_WAKE_EN; 2843 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2844 2845 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2846 } else { 2847 u32 ocp_data; 2848 2849 __rtl_set_wol(tp, tp->saved_wolopts); 2850 2851 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2852 2853 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2854 ocp_data &= ~LINK_OFF_WAKE_EN; 2855 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2856 2857 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2858 } 2859 } 2860 2861 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) 2862 { 2863 if (enable) { 2864 r8153_u1u2en(tp, false); 2865 r8153_u2p3en(tp, false); 2866 r8153_mac_clk_spd(tp, true); 2867 rtl_runtime_suspend_enable(tp, true); 2868 } else { 2869 rtl_runtime_suspend_enable(tp, false); 2870 r8153_mac_clk_spd(tp, false); 2871 2872 switch (tp->version) { 2873 case RTL_VER_03: 2874 case RTL_VER_04: 2875 break; 2876 case RTL_VER_05: 2877 case RTL_VER_06: 2878 default: 2879 r8153_u2p3en(tp, true); 2880 break; 2881 } 2882 2883 r8153_u1u2en(tp, true); 2884 } 2885 } 2886 2887 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable) 2888 { 2889 if (enable) { 2890 r8153b_queue_wake(tp, true); 2891 r8153b_u1u2en(tp, false); 2892 r8153_u2p3en(tp, false); 2893 rtl_runtime_suspend_enable(tp, true); 2894 r8153b_ups_en(tp, true); 2895 } else { 2896 r8153b_ups_en(tp, false); 2897 r8153b_queue_wake(tp, false); 2898 rtl_runtime_suspend_enable(tp, false); 2899 r8153_u2p3en(tp, true); 2900 r8153b_u1u2en(tp, true); 2901 } 2902 } 2903 2904 static void r8153_teredo_off(struct r8152 *tp) 2905 { 2906 u32 ocp_data; 2907 2908 switch (tp->version) { 2909 case RTL_VER_01: 2910 case RTL_VER_02: 2911 case RTL_VER_03: 2912 case RTL_VER_04: 2913 case RTL_VER_05: 2914 case RTL_VER_06: 2915 case RTL_VER_07: 2916 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2917 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | 2918 OOB_TEREDO_EN); 2919 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2920 break; 2921 2922 case RTL_VER_08: 2923 case RTL_VER_09: 2924 /* The bit 0 ~ 7 are relative with teredo settings. They are 2925 * W1C (write 1 to clear), so set all 1 to disable it. 2926 */ 2927 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); 2928 break; 2929 2930 default: 2931 break; 2932 } 2933 2934 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 2935 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 2936 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 2937 } 2938 2939 static void rtl_reset_bmu(struct r8152 *tp) 2940 { 2941 u32 ocp_data; 2942 2943 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); 2944 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 2945 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2946 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 2947 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2948 } 2949 2950 static void r8152_aldps_en(struct r8152 *tp, bool enable) 2951 { 2952 if (enable) { 2953 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 2954 LINKENA | DIS_SDSAVE); 2955 } else { 2956 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | 2957 DIS_SDSAVE); 2958 msleep(20); 2959 } 2960 } 2961 2962 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 2963 { 2964 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 2965 ocp_reg_write(tp, OCP_EEE_DATA, reg); 2966 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 2967 } 2968 2969 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 2970 { 2971 u16 data; 2972 2973 r8152_mmd_indirect(tp, dev, reg); 2974 data = ocp_reg_read(tp, OCP_EEE_DATA); 2975 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 2976 2977 return data; 2978 } 2979 2980 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 2981 { 2982 r8152_mmd_indirect(tp, dev, reg); 2983 ocp_reg_write(tp, OCP_EEE_DATA, data); 2984 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 2985 } 2986 2987 static void r8152_eee_en(struct r8152 *tp, bool enable) 2988 { 2989 u16 config1, config2, config3; 2990 u32 ocp_data; 2991 2992 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 2993 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 2994 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 2995 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 2996 2997 if (enable) { 2998 ocp_data |= EEE_RX_EN | EEE_TX_EN; 2999 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 3000 config1 |= sd_rise_time(1); 3001 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 3002 config3 |= fast_snr(42); 3003 } else { 3004 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3005 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 3006 RX_QUIET_EN); 3007 config1 |= sd_rise_time(7); 3008 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 3009 config3 |= fast_snr(511); 3010 } 3011 3012 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3013 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 3014 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 3015 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 3016 } 3017 3018 static void r8152b_enable_eee(struct r8152 *tp) 3019 { 3020 r8152_eee_en(tp, true); 3021 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); 3022 } 3023 3024 static void r8152b_enable_fc(struct r8152 *tp) 3025 { 3026 u16 anar; 3027 3028 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3029 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 3030 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3031 } 3032 3033 static void rtl8152_disable(struct r8152 *tp) 3034 { 3035 r8152_aldps_en(tp, false); 3036 rtl_disable(tp); 3037 r8152_aldps_en(tp, true); 3038 } 3039 3040 static void r8152b_hw_phy_cfg(struct r8152 *tp) 3041 { 3042 r8152b_enable_eee(tp); 3043 r8152_aldps_en(tp, true); 3044 r8152b_enable_fc(tp); 3045 3046 set_bit(PHY_RESET, &tp->flags); 3047 } 3048 3049 static void r8152b_exit_oob(struct r8152 *tp) 3050 { 3051 u32 ocp_data; 3052 int i; 3053 3054 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3055 ocp_data &= ~RCR_ACPT_ALL; 3056 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3057 3058 rxdy_gated_en(tp, true); 3059 r8153_teredo_off(tp); 3060 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3061 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 3062 3063 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3064 ocp_data &= ~NOW_IS_OOB; 3065 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3066 3067 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3068 ocp_data &= ~MCU_BORW_EN; 3069 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3070 3071 for (i = 0; i < 1000; i++) { 3072 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3073 if (ocp_data & LINK_LIST_READY) 3074 break; 3075 usleep_range(1000, 2000); 3076 } 3077 3078 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3079 ocp_data |= RE_INIT_LL; 3080 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3081 3082 for (i = 0; i < 1000; i++) { 3083 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3084 if (ocp_data & LINK_LIST_READY) 3085 break; 3086 usleep_range(1000, 2000); 3087 } 3088 3089 rtl8152_nic_reset(tp); 3090 3091 /* rx share fifo credit full threshold */ 3092 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3093 3094 if (tp->udev->speed == USB_SPEED_FULL || 3095 tp->udev->speed == USB_SPEED_LOW) { 3096 /* rx share fifo credit near full threshold */ 3097 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3098 RXFIFO_THR2_FULL); 3099 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3100 RXFIFO_THR3_FULL); 3101 } else { 3102 /* rx share fifo credit near full threshold */ 3103 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3104 RXFIFO_THR2_HIGH); 3105 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3106 RXFIFO_THR3_HIGH); 3107 } 3108 3109 /* TX share fifo free credit full threshold */ 3110 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 3111 3112 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 3113 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 3114 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 3115 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 3116 3117 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3118 3119 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3120 3121 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3122 ocp_data |= TCR0_AUTO_FIFO; 3123 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3124 } 3125 3126 static void r8152b_enter_oob(struct r8152 *tp) 3127 { 3128 u32 ocp_data; 3129 int i; 3130 3131 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3132 ocp_data &= ~NOW_IS_OOB; 3133 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3134 3135 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 3136 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 3137 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 3138 3139 rtl_disable(tp); 3140 3141 for (i = 0; i < 1000; i++) { 3142 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3143 if (ocp_data & LINK_LIST_READY) 3144 break; 3145 usleep_range(1000, 2000); 3146 } 3147 3148 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3149 ocp_data |= RE_INIT_LL; 3150 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3151 3152 for (i = 0; i < 1000; i++) { 3153 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3154 if (ocp_data & LINK_LIST_READY) 3155 break; 3156 usleep_range(1000, 2000); 3157 } 3158 3159 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3160 3161 rtl_rx_vlan_en(tp, true); 3162 3163 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 3164 ocp_data |= ALDPS_PROXY_MODE; 3165 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 3166 3167 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3168 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3169 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3170 3171 rxdy_gated_en(tp, false); 3172 3173 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3174 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3175 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3176 } 3177 3178 static int r8153_patch_request(struct r8152 *tp, bool request) 3179 { 3180 u16 data; 3181 int i; 3182 3183 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD); 3184 if (request) 3185 data |= PATCH_REQUEST; 3186 else 3187 data &= ~PATCH_REQUEST; 3188 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); 3189 3190 for (i = 0; request && i < 5000; i++) { 3191 usleep_range(1000, 2000); 3192 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY) 3193 break; 3194 } 3195 3196 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) { 3197 netif_err(tp, drv, tp->netdev, "patch request fail\n"); 3198 r8153_patch_request(tp, false); 3199 return -ETIME; 3200 } else { 3201 return 0; 3202 } 3203 } 3204 3205 static void r8153_aldps_en(struct r8152 *tp, bool enable) 3206 { 3207 u16 data; 3208 3209 data = ocp_reg_read(tp, OCP_POWER_CFG); 3210 if (enable) { 3211 data |= EN_ALDPS; 3212 ocp_reg_write(tp, OCP_POWER_CFG, data); 3213 } else { 3214 int i; 3215 3216 data &= ~EN_ALDPS; 3217 ocp_reg_write(tp, OCP_POWER_CFG, data); 3218 for (i = 0; i < 20; i++) { 3219 usleep_range(1000, 2000); 3220 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) 3221 break; 3222 } 3223 } 3224 } 3225 3226 static void r8153b_aldps_en(struct r8152 *tp, bool enable) 3227 { 3228 r8153_aldps_en(tp, enable); 3229 3230 if (enable) 3231 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0); 3232 else 3233 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS); 3234 } 3235 3236 static void r8153_eee_en(struct r8152 *tp, bool enable) 3237 { 3238 u32 ocp_data; 3239 u16 config; 3240 3241 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3242 config = ocp_reg_read(tp, OCP_EEE_CFG); 3243 3244 if (enable) { 3245 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3246 config |= EEE10_EN; 3247 } else { 3248 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3249 config &= ~EEE10_EN; 3250 } 3251 3252 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3253 ocp_reg_write(tp, OCP_EEE_CFG, config); 3254 } 3255 3256 static void r8153b_eee_en(struct r8152 *tp, bool enable) 3257 { 3258 r8153_eee_en(tp, enable); 3259 3260 if (enable) 3261 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0); 3262 else 3263 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE); 3264 } 3265 3266 static void r8153b_enable_fc(struct r8152 *tp) 3267 { 3268 r8152b_enable_fc(tp); 3269 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0); 3270 } 3271 3272 static void r8153_hw_phy_cfg(struct r8152 *tp) 3273 { 3274 u32 ocp_data; 3275 u16 data; 3276 3277 /* disable ALDPS before updating the PHY parameters */ 3278 r8153_aldps_en(tp, false); 3279 3280 /* disable EEE before updating the PHY parameters */ 3281 r8153_eee_en(tp, false); 3282 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3283 3284 if (tp->version == RTL_VER_03) { 3285 data = ocp_reg_read(tp, OCP_EEE_CFG); 3286 data &= ~CTAP_SHORT_EN; 3287 ocp_reg_write(tp, OCP_EEE_CFG, data); 3288 } 3289 3290 data = ocp_reg_read(tp, OCP_POWER_CFG); 3291 data |= EEE_CLKDIV_EN; 3292 ocp_reg_write(tp, OCP_POWER_CFG, data); 3293 3294 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3295 data |= EN_10M_BGOFF; 3296 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3297 data = ocp_reg_read(tp, OCP_POWER_CFG); 3298 data |= EN_10M_PLLOFF; 3299 ocp_reg_write(tp, OCP_POWER_CFG, data); 3300 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 3301 3302 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3303 ocp_data |= PFM_PWM_SWITCH; 3304 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3305 3306 /* Enable LPF corner auto tune */ 3307 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 3308 3309 /* Adjust 10M Amplitude */ 3310 sram_write(tp, SRAM_10M_AMP1, 0x00af); 3311 sram_write(tp, SRAM_10M_AMP2, 0x0208); 3312 3313 r8153_eee_en(tp, true); 3314 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3315 3316 r8153_aldps_en(tp, true); 3317 r8152b_enable_fc(tp); 3318 3319 switch (tp->version) { 3320 case RTL_VER_03: 3321 case RTL_VER_04: 3322 break; 3323 case RTL_VER_05: 3324 case RTL_VER_06: 3325 default: 3326 r8153_u2p3en(tp, true); 3327 break; 3328 } 3329 3330 set_bit(PHY_RESET, &tp->flags); 3331 } 3332 3333 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) 3334 { 3335 u32 ocp_data; 3336 3337 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr); 3338 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD); 3339 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */ 3340 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA); 3341 3342 return ocp_data; 3343 } 3344 3345 static void r8153b_hw_phy_cfg(struct r8152 *tp) 3346 { 3347 u32 ocp_data, ups_flags = 0; 3348 u16 data; 3349 3350 /* disable ALDPS before updating the PHY parameters */ 3351 r8153b_aldps_en(tp, false); 3352 3353 /* disable EEE before updating the PHY parameters */ 3354 r8153b_eee_en(tp, false); 3355 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3356 3357 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); 3358 3359 data = sram_read(tp, SRAM_GREEN_CFG); 3360 data |= R_TUNE_EN; 3361 sram_write(tp, SRAM_GREEN_CFG, data); 3362 data = ocp_reg_read(tp, OCP_NCTL_CFG); 3363 data |= PGA_RETURN_EN; 3364 ocp_reg_write(tp, OCP_NCTL_CFG, data); 3365 3366 /* ADC Bias Calibration: 3367 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake 3368 * bit (bit3) to rebuild the real 16-bit data. Write the data to the 3369 * ADC ioffset. 3370 */ 3371 ocp_data = r8152_efuse_read(tp, 0x7d); 3372 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); 3373 if (data != 0xffff) 3374 ocp_reg_write(tp, OCP_ADC_IOFFSET, data); 3375 3376 /* ups mode tx-link-pulse timing adjustment: 3377 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] 3378 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt 3379 */ 3380 ocp_data = ocp_reg_read(tp, 0xc426); 3381 ocp_data &= 0x3fff; 3382 if (ocp_data) { 3383 u32 swr_cnt_1ms_ini; 3384 3385 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; 3386 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); 3387 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; 3388 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); 3389 } 3390 3391 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3392 ocp_data |= PFM_PWM_SWITCH; 3393 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3394 3395 /* Advnace EEE */ 3396 if (!r8153_patch_request(tp, true)) { 3397 data = ocp_reg_read(tp, OCP_POWER_CFG); 3398 data |= EEE_CLKDIV_EN; 3399 ocp_reg_write(tp, OCP_POWER_CFG, data); 3400 3401 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3402 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV; 3403 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3404 3405 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); 3406 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5)); 3407 3408 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV | 3409 UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN | 3410 UPS_FLAGS_EEE_PLLOFF_GIGA; 3411 3412 r8153_patch_request(tp, false); 3413 } 3414 3415 r8153b_ups_flags_w1w0(tp, ups_flags, 0); 3416 3417 r8153b_eee_en(tp, true); 3418 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3419 3420 r8153b_aldps_en(tp, true); 3421 r8153b_enable_fc(tp); 3422 r8153_u2p3en(tp, true); 3423 3424 set_bit(PHY_RESET, &tp->flags); 3425 } 3426 3427 static void r8153_first_init(struct r8152 *tp) 3428 { 3429 u32 ocp_data; 3430 int i; 3431 3432 r8153_mac_clk_spd(tp, false); 3433 rxdy_gated_en(tp, true); 3434 r8153_teredo_off(tp); 3435 3436 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3437 ocp_data &= ~RCR_ACPT_ALL; 3438 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3439 3440 rtl8152_nic_reset(tp); 3441 rtl_reset_bmu(tp); 3442 3443 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3444 ocp_data &= ~NOW_IS_OOB; 3445 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3446 3447 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3448 ocp_data &= ~MCU_BORW_EN; 3449 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3450 3451 for (i = 0; i < 1000; i++) { 3452 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3453 if (ocp_data & LINK_LIST_READY) 3454 break; 3455 usleep_range(1000, 2000); 3456 } 3457 3458 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3459 ocp_data |= RE_INIT_LL; 3460 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3461 3462 for (i = 0; i < 1000; i++) { 3463 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3464 if (ocp_data & LINK_LIST_READY) 3465 break; 3466 usleep_range(1000, 2000); 3467 } 3468 3469 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3470 3471 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3472 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3473 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 3474 3475 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3476 ocp_data |= TCR0_AUTO_FIFO; 3477 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3478 3479 rtl8152_nic_reset(tp); 3480 3481 /* rx share fifo credit full threshold */ 3482 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3483 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 3484 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 3485 /* TX share fifo free credit full threshold */ 3486 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 3487 } 3488 3489 static void r8153_enter_oob(struct r8152 *tp) 3490 { 3491 u32 ocp_data; 3492 int i; 3493 3494 r8153_mac_clk_spd(tp, true); 3495 3496 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3497 ocp_data &= ~NOW_IS_OOB; 3498 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3499 3500 rtl_disable(tp); 3501 rtl_reset_bmu(tp); 3502 3503 for (i = 0; i < 1000; i++) { 3504 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3505 if (ocp_data & LINK_LIST_READY) 3506 break; 3507 usleep_range(1000, 2000); 3508 } 3509 3510 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3511 ocp_data |= RE_INIT_LL; 3512 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3513 3514 for (i = 0; i < 1000; i++) { 3515 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3516 if (ocp_data & LINK_LIST_READY) 3517 break; 3518 usleep_range(1000, 2000); 3519 } 3520 3521 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3522 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3523 3524 switch (tp->version) { 3525 case RTL_VER_03: 3526 case RTL_VER_04: 3527 case RTL_VER_05: 3528 case RTL_VER_06: 3529 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 3530 ocp_data &= ~TEREDO_WAKE_MASK; 3531 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 3532 break; 3533 3534 case RTL_VER_08: 3535 case RTL_VER_09: 3536 /* Clear teredo wake event. bit[15:8] is the teredo wakeup 3537 * type. Set it to zero. bits[7:0] are the W1C bits about 3538 * the events. Set them to all 1 to clear them. 3539 */ 3540 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); 3541 break; 3542 3543 default: 3544 break; 3545 } 3546 3547 rtl_rx_vlan_en(tp, true); 3548 3549 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 3550 ocp_data |= ALDPS_PROXY_MODE; 3551 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 3552 3553 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3554 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3555 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3556 3557 rxdy_gated_en(tp, false); 3558 3559 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3560 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3561 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3562 } 3563 3564 static void rtl8153_disable(struct r8152 *tp) 3565 { 3566 r8153_aldps_en(tp, false); 3567 rtl_disable(tp); 3568 rtl_reset_bmu(tp); 3569 r8153_aldps_en(tp, true); 3570 } 3571 3572 static void rtl8153b_disable(struct r8152 *tp) 3573 { 3574 r8153b_aldps_en(tp, false); 3575 rtl_disable(tp); 3576 rtl_reset_bmu(tp); 3577 r8153b_aldps_en(tp, true); 3578 } 3579 3580 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 3581 { 3582 u16 bmcr, anar, gbcr; 3583 enum spd_duplex speed_duplex; 3584 int ret = 0; 3585 3586 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3587 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 3588 ADVERTISE_100HALF | ADVERTISE_100FULL); 3589 if (tp->mii.supports_gmii) { 3590 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 3591 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 3592 } else { 3593 gbcr = 0; 3594 } 3595 3596 if (autoneg == AUTONEG_DISABLE) { 3597 if (speed == SPEED_10) { 3598 bmcr = 0; 3599 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3600 speed_duplex = FORCE_10M_HALF; 3601 } else if (speed == SPEED_100) { 3602 bmcr = BMCR_SPEED100; 3603 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3604 speed_duplex = FORCE_100M_HALF; 3605 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3606 bmcr = BMCR_SPEED1000; 3607 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3608 speed_duplex = NWAY_1000M_FULL; 3609 } else { 3610 ret = -EINVAL; 3611 goto out; 3612 } 3613 3614 if (duplex == DUPLEX_FULL) { 3615 bmcr |= BMCR_FULLDPLX; 3616 if (speed != SPEED_1000) 3617 speed_duplex++; 3618 } 3619 } else { 3620 if (speed == SPEED_10) { 3621 if (duplex == DUPLEX_FULL) { 3622 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3623 speed_duplex = NWAY_10M_FULL; 3624 } else { 3625 anar |= ADVERTISE_10HALF; 3626 speed_duplex = NWAY_10M_HALF; 3627 } 3628 } else if (speed == SPEED_100) { 3629 if (duplex == DUPLEX_FULL) { 3630 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3631 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3632 speed_duplex = NWAY_100M_FULL; 3633 } else { 3634 anar |= ADVERTISE_10HALF; 3635 anar |= ADVERTISE_100HALF; 3636 speed_duplex = NWAY_100M_HALF; 3637 } 3638 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3639 if (duplex == DUPLEX_FULL) { 3640 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3641 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3642 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3643 } else { 3644 anar |= ADVERTISE_10HALF; 3645 anar |= ADVERTISE_100HALF; 3646 gbcr |= ADVERTISE_1000HALF; 3647 } 3648 speed_duplex = NWAY_1000M_FULL; 3649 } else { 3650 ret = -EINVAL; 3651 goto out; 3652 } 3653 3654 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 3655 } 3656 3657 if (test_and_clear_bit(PHY_RESET, &tp->flags)) 3658 bmcr |= BMCR_RESET; 3659 3660 if (tp->mii.supports_gmii) 3661 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 3662 3663 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3664 r8152_mdio_write(tp, MII_BMCR, bmcr); 3665 3666 switch (tp->version) { 3667 case RTL_VER_08: 3668 case RTL_VER_09: 3669 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex), 3670 UPS_FLAGS_SPEED_MASK); 3671 break; 3672 3673 default: 3674 break; 3675 } 3676 3677 if (bmcr & BMCR_RESET) { 3678 int i; 3679 3680 for (i = 0; i < 50; i++) { 3681 msleep(20); 3682 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 3683 break; 3684 } 3685 } 3686 3687 out: 3688 return ret; 3689 } 3690 3691 static void rtl8152_up(struct r8152 *tp) 3692 { 3693 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3694 return; 3695 3696 r8152_aldps_en(tp, false); 3697 r8152b_exit_oob(tp); 3698 r8152_aldps_en(tp, true); 3699 } 3700 3701 static void rtl8152_down(struct r8152 *tp) 3702 { 3703 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3704 rtl_drop_queued_tx(tp); 3705 return; 3706 } 3707 3708 r8152_power_cut_en(tp, false); 3709 r8152_aldps_en(tp, false); 3710 r8152b_enter_oob(tp); 3711 r8152_aldps_en(tp, true); 3712 } 3713 3714 static void rtl8153_up(struct r8152 *tp) 3715 { 3716 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3717 return; 3718 3719 r8153_u1u2en(tp, false); 3720 r8153_u2p3en(tp, false); 3721 r8153_aldps_en(tp, false); 3722 r8153_first_init(tp); 3723 r8153_aldps_en(tp, true); 3724 3725 switch (tp->version) { 3726 case RTL_VER_03: 3727 case RTL_VER_04: 3728 break; 3729 case RTL_VER_05: 3730 case RTL_VER_06: 3731 default: 3732 r8153_u2p3en(tp, true); 3733 break; 3734 } 3735 3736 r8153_u1u2en(tp, true); 3737 } 3738 3739 static void rtl8153_down(struct r8152 *tp) 3740 { 3741 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3742 rtl_drop_queued_tx(tp); 3743 return; 3744 } 3745 3746 r8153_u1u2en(tp, false); 3747 r8153_u2p3en(tp, false); 3748 r8153_power_cut_en(tp, false); 3749 r8153_aldps_en(tp, false); 3750 r8153_enter_oob(tp); 3751 r8153_aldps_en(tp, true); 3752 } 3753 3754 static void rtl8153b_up(struct r8152 *tp) 3755 { 3756 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3757 return; 3758 3759 r8153b_u1u2en(tp, false); 3760 r8153_u2p3en(tp, false); 3761 r8153b_aldps_en(tp, false); 3762 3763 r8153_first_init(tp); 3764 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); 3765 3766 r8153b_aldps_en(tp, true); 3767 r8153_u2p3en(tp, true); 3768 r8153b_u1u2en(tp, true); 3769 } 3770 3771 static void rtl8153b_down(struct r8152 *tp) 3772 { 3773 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3774 rtl_drop_queued_tx(tp); 3775 return; 3776 } 3777 3778 r8153b_u1u2en(tp, false); 3779 r8153_u2p3en(tp, false); 3780 r8153b_power_cut_en(tp, false); 3781 r8153b_aldps_en(tp, false); 3782 r8153_enter_oob(tp); 3783 r8153b_aldps_en(tp, true); 3784 } 3785 3786 static bool rtl8152_in_nway(struct r8152 *tp) 3787 { 3788 u16 nway_state; 3789 3790 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); 3791 tp->ocp_base = 0x2000; 3792 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ 3793 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); 3794 3795 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ 3796 if (nway_state & 0xc000) 3797 return false; 3798 else 3799 return true; 3800 } 3801 3802 static bool rtl8153_in_nway(struct r8152 *tp) 3803 { 3804 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; 3805 3806 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) 3807 return false; 3808 else 3809 return true; 3810 } 3811 3812 static void set_carrier(struct r8152 *tp) 3813 { 3814 struct net_device *netdev = tp->netdev; 3815 struct napi_struct *napi = &tp->napi; 3816 u8 speed; 3817 3818 speed = rtl8152_get_speed(tp); 3819 3820 if (speed & LINK_STATUS) { 3821 if (!netif_carrier_ok(netdev)) { 3822 tp->rtl_ops.enable(tp); 3823 netif_stop_queue(netdev); 3824 napi_disable(napi); 3825 netif_carrier_on(netdev); 3826 rtl_start_rx(tp); 3827 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 3828 _rtl8152_set_rx_mode(netdev); 3829 napi_enable(&tp->napi); 3830 netif_wake_queue(netdev); 3831 netif_info(tp, link, netdev, "carrier on\n"); 3832 } else if (netif_queue_stopped(netdev) && 3833 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) { 3834 netif_wake_queue(netdev); 3835 } 3836 } else { 3837 if (netif_carrier_ok(netdev)) { 3838 netif_carrier_off(netdev); 3839 napi_disable(napi); 3840 tp->rtl_ops.disable(tp); 3841 napi_enable(napi); 3842 netif_info(tp, link, netdev, "carrier off\n"); 3843 } 3844 } 3845 } 3846 3847 static void rtl_work_func_t(struct work_struct *work) 3848 { 3849 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 3850 3851 /* If the device is unplugged or !netif_running(), the workqueue 3852 * doesn't need to wake the device, and could return directly. 3853 */ 3854 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) 3855 return; 3856 3857 if (usb_autopm_get_interface(tp->intf) < 0) 3858 return; 3859 3860 if (!test_bit(WORK_ENABLE, &tp->flags)) 3861 goto out1; 3862 3863 if (!mutex_trylock(&tp->control)) { 3864 schedule_delayed_work(&tp->schedule, 0); 3865 goto out1; 3866 } 3867 3868 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) 3869 set_carrier(tp); 3870 3871 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) 3872 _rtl8152_set_rx_mode(tp->netdev); 3873 3874 /* don't schedule napi before linking */ 3875 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) && 3876 netif_carrier_ok(tp->netdev)) 3877 napi_schedule(&tp->napi); 3878 3879 mutex_unlock(&tp->control); 3880 3881 out1: 3882 usb_autopm_put_interface(tp->intf); 3883 } 3884 3885 static void rtl_hw_phy_work_func_t(struct work_struct *work) 3886 { 3887 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); 3888 3889 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3890 return; 3891 3892 if (usb_autopm_get_interface(tp->intf) < 0) 3893 return; 3894 3895 mutex_lock(&tp->control); 3896 3897 tp->rtl_ops.hw_phy_cfg(tp); 3898 3899 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex); 3900 3901 mutex_unlock(&tp->control); 3902 3903 usb_autopm_put_interface(tp->intf); 3904 } 3905 3906 #ifdef CONFIG_PM_SLEEP 3907 static int rtl_notifier(struct notifier_block *nb, unsigned long action, 3908 void *data) 3909 { 3910 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); 3911 3912 switch (action) { 3913 case PM_HIBERNATION_PREPARE: 3914 case PM_SUSPEND_PREPARE: 3915 usb_autopm_get_interface(tp->intf); 3916 break; 3917 3918 case PM_POST_HIBERNATION: 3919 case PM_POST_SUSPEND: 3920 usb_autopm_put_interface(tp->intf); 3921 break; 3922 3923 case PM_POST_RESTORE: 3924 case PM_RESTORE_PREPARE: 3925 default: 3926 break; 3927 } 3928 3929 return NOTIFY_DONE; 3930 } 3931 #endif 3932 3933 static int rtl8152_open(struct net_device *netdev) 3934 { 3935 struct r8152 *tp = netdev_priv(netdev); 3936 int res = 0; 3937 3938 res = alloc_all_mem(tp); 3939 if (res) 3940 goto out; 3941 3942 res = usb_autopm_get_interface(tp->intf); 3943 if (res < 0) 3944 goto out_free; 3945 3946 mutex_lock(&tp->control); 3947 3948 tp->rtl_ops.up(tp); 3949 3950 netif_carrier_off(netdev); 3951 netif_start_queue(netdev); 3952 set_bit(WORK_ENABLE, &tp->flags); 3953 3954 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3955 if (res) { 3956 if (res == -ENODEV) 3957 netif_device_detach(tp->netdev); 3958 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 3959 res); 3960 goto out_unlock; 3961 } 3962 napi_enable(&tp->napi); 3963 3964 mutex_unlock(&tp->control); 3965 3966 usb_autopm_put_interface(tp->intf); 3967 #ifdef CONFIG_PM_SLEEP 3968 tp->pm_notifier.notifier_call = rtl_notifier; 3969 register_pm_notifier(&tp->pm_notifier); 3970 #endif 3971 return 0; 3972 3973 out_unlock: 3974 mutex_unlock(&tp->control); 3975 usb_autopm_put_interface(tp->intf); 3976 out_free: 3977 free_all_mem(tp); 3978 out: 3979 return res; 3980 } 3981 3982 static int rtl8152_close(struct net_device *netdev) 3983 { 3984 struct r8152 *tp = netdev_priv(netdev); 3985 int res = 0; 3986 3987 #ifdef CONFIG_PM_SLEEP 3988 unregister_pm_notifier(&tp->pm_notifier); 3989 #endif 3990 if (!test_bit(RTL8152_UNPLUG, &tp->flags)) 3991 napi_disable(&tp->napi); 3992 clear_bit(WORK_ENABLE, &tp->flags); 3993 usb_kill_urb(tp->intr_urb); 3994 cancel_delayed_work_sync(&tp->schedule); 3995 netif_stop_queue(netdev); 3996 3997 res = usb_autopm_get_interface(tp->intf); 3998 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { 3999 rtl_drop_queued_tx(tp); 4000 rtl_stop_rx(tp); 4001 } else { 4002 mutex_lock(&tp->control); 4003 4004 tp->rtl_ops.down(tp); 4005 4006 mutex_unlock(&tp->control); 4007 4008 usb_autopm_put_interface(tp->intf); 4009 } 4010 4011 free_all_mem(tp); 4012 4013 return res; 4014 } 4015 4016 static void rtl_tally_reset(struct r8152 *tp) 4017 { 4018 u32 ocp_data; 4019 4020 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 4021 ocp_data |= TALLY_RESET; 4022 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 4023 } 4024 4025 static void r8152b_init(struct r8152 *tp) 4026 { 4027 u32 ocp_data; 4028 u16 data; 4029 4030 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4031 return; 4032 4033 data = r8152_mdio_read(tp, MII_BMCR); 4034 if (data & BMCR_PDOWN) { 4035 data &= ~BMCR_PDOWN; 4036 r8152_mdio_write(tp, MII_BMCR, data); 4037 } 4038 4039 r8152_aldps_en(tp, false); 4040 4041 if (tp->version == RTL_VER_01) { 4042 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4043 ocp_data &= ~LED_MODE_MASK; 4044 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4045 } 4046 4047 r8152_power_cut_en(tp, false); 4048 4049 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 4050 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 4051 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 4052 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 4053 ocp_data &= ~MCU_CLK_RATIO_MASK; 4054 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 4055 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 4056 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 4057 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 4058 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 4059 4060 rtl_tally_reset(tp); 4061 4062 /* enable rx aggregation */ 4063 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4064 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4065 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4066 } 4067 4068 static void r8153_init(struct r8152 *tp) 4069 { 4070 u32 ocp_data; 4071 u16 data; 4072 int i; 4073 4074 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4075 return; 4076 4077 r8153_u1u2en(tp, false); 4078 4079 for (i = 0; i < 500; i++) { 4080 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4081 AUTOLOAD_DONE) 4082 break; 4083 msleep(20); 4084 } 4085 4086 data = r8153_phy_status(tp, 0); 4087 4088 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 4089 tp->version == RTL_VER_05) 4090 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 4091 4092 data = r8152_mdio_read(tp, MII_BMCR); 4093 if (data & BMCR_PDOWN) { 4094 data &= ~BMCR_PDOWN; 4095 r8152_mdio_write(tp, MII_BMCR, data); 4096 } 4097 4098 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4099 4100 r8153_u2p3en(tp, false); 4101 4102 if (tp->version == RTL_VER_04) { 4103 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 4104 ocp_data &= ~pwd_dn_scale_mask; 4105 ocp_data |= pwd_dn_scale(96); 4106 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 4107 4108 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 4109 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 4110 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 4111 } else if (tp->version == RTL_VER_05) { 4112 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 4113 ocp_data &= ~ECM_ALDPS; 4114 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 4115 4116 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4117 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4118 ocp_data &= ~DYNAMIC_BURST; 4119 else 4120 ocp_data |= DYNAMIC_BURST; 4121 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4122 } else if (tp->version == RTL_VER_06) { 4123 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4124 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4125 ocp_data &= ~DYNAMIC_BURST; 4126 else 4127 ocp_data |= DYNAMIC_BURST; 4128 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4129 } 4130 4131 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 4132 ocp_data |= EP4_FULL_FC; 4133 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 4134 4135 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 4136 ocp_data &= ~TIMER11_EN; 4137 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 4138 4139 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4140 ocp_data &= ~LED_MODE_MASK; 4141 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4142 4143 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 4144 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) 4145 ocp_data |= LPM_TIMER_500MS; 4146 else 4147 ocp_data |= LPM_TIMER_500US; 4148 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 4149 4150 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 4151 ocp_data &= ~SEN_VAL_MASK; 4152 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 4153 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 4154 4155 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 4156 4157 r8153_power_cut_en(tp, false); 4158 r8153_u1u2en(tp, true); 4159 r8153_mac_clk_spd(tp, false); 4160 usb_enable_lpm(tp->udev); 4161 4162 /* rx aggregation */ 4163 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4164 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4165 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags)) 4166 ocp_data |= RX_AGG_DISABLE; 4167 4168 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4169 4170 rtl_tally_reset(tp); 4171 4172 switch (tp->udev->speed) { 4173 case USB_SPEED_SUPER: 4174 case USB_SPEED_SUPER_PLUS: 4175 tp->coalesce = COALESCE_SUPER; 4176 break; 4177 case USB_SPEED_HIGH: 4178 tp->coalesce = COALESCE_HIGH; 4179 break; 4180 default: 4181 tp->coalesce = COALESCE_SLOW; 4182 break; 4183 } 4184 } 4185 4186 static void r8153b_init(struct r8152 *tp) 4187 { 4188 u32 ocp_data; 4189 u16 data; 4190 int i; 4191 4192 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4193 return; 4194 4195 r8153b_u1u2en(tp, false); 4196 4197 for (i = 0; i < 500; i++) { 4198 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4199 AUTOLOAD_DONE) 4200 break; 4201 msleep(20); 4202 } 4203 4204 data = r8153_phy_status(tp, 0); 4205 4206 data = r8152_mdio_read(tp, MII_BMCR); 4207 if (data & BMCR_PDOWN) { 4208 data &= ~BMCR_PDOWN; 4209 r8152_mdio_write(tp, MII_BMCR, data); 4210 } 4211 4212 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4213 4214 r8153_u2p3en(tp, false); 4215 4216 /* MSC timer = 0xfff * 8ms = 32760 ms */ 4217 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 4218 4219 /* U1/U2/L1 idle timer. 500 us */ 4220 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 4221 4222 r8153b_power_cut_en(tp, false); 4223 r8153b_ups_en(tp, false); 4224 r8153b_queue_wake(tp, false); 4225 rtl_runtime_suspend_enable(tp, false); 4226 r8153b_u1u2en(tp, true); 4227 usb_enable_lpm(tp->udev); 4228 4229 /* MAC clock speed down */ 4230 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); 4231 ocp_data |= MAC_CLK_SPDWN_EN; 4232 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); 4233 4234 set_bit(GREEN_ETHERNET, &tp->flags); 4235 4236 /* rx aggregation */ 4237 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4238 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4239 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4240 4241 rtl_tally_reset(tp); 4242 4243 tp->coalesce = 15000; /* 15 us */ 4244 } 4245 4246 static int rtl8152_pre_reset(struct usb_interface *intf) 4247 { 4248 struct r8152 *tp = usb_get_intfdata(intf); 4249 struct net_device *netdev; 4250 4251 if (!tp) 4252 return 0; 4253 4254 netdev = tp->netdev; 4255 if (!netif_running(netdev)) 4256 return 0; 4257 4258 netif_stop_queue(netdev); 4259 napi_disable(&tp->napi); 4260 clear_bit(WORK_ENABLE, &tp->flags); 4261 usb_kill_urb(tp->intr_urb); 4262 cancel_delayed_work_sync(&tp->schedule); 4263 if (netif_carrier_ok(netdev)) { 4264 mutex_lock(&tp->control); 4265 tp->rtl_ops.disable(tp); 4266 mutex_unlock(&tp->control); 4267 } 4268 4269 return 0; 4270 } 4271 4272 static int rtl8152_post_reset(struct usb_interface *intf) 4273 { 4274 struct r8152 *tp = usb_get_intfdata(intf); 4275 struct net_device *netdev; 4276 struct sockaddr sa; 4277 4278 if (!tp) 4279 return 0; 4280 4281 /* reset the MAC adddress in case of policy change */ 4282 if (determine_ethernet_addr(tp, &sa) >= 0) { 4283 rtnl_lock(); 4284 dev_set_mac_address (tp->netdev, &sa, NULL); 4285 rtnl_unlock(); 4286 } 4287 4288 netdev = tp->netdev; 4289 if (!netif_running(netdev)) 4290 return 0; 4291 4292 set_bit(WORK_ENABLE, &tp->flags); 4293 if (netif_carrier_ok(netdev)) { 4294 mutex_lock(&tp->control); 4295 tp->rtl_ops.enable(tp); 4296 rtl_start_rx(tp); 4297 _rtl8152_set_rx_mode(netdev); 4298 mutex_unlock(&tp->control); 4299 } 4300 4301 napi_enable(&tp->napi); 4302 netif_wake_queue(netdev); 4303 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 4304 4305 if (!list_empty(&tp->rx_done)) 4306 napi_schedule(&tp->napi); 4307 4308 return 0; 4309 } 4310 4311 static bool delay_autosuspend(struct r8152 *tp) 4312 { 4313 bool sw_linking = !!netif_carrier_ok(tp->netdev); 4314 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); 4315 4316 /* This means a linking change occurs and the driver doesn't detect it, 4317 * yet. If the driver has disabled tx/rx and hw is linking on, the 4318 * device wouldn't wake up by receiving any packet. 4319 */ 4320 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) 4321 return true; 4322 4323 /* If the linking down is occurred by nway, the device may miss the 4324 * linking change event. And it wouldn't wake when linking on. 4325 */ 4326 if (!sw_linking && tp->rtl_ops.in_nway(tp)) 4327 return true; 4328 else if (!skb_queue_empty(&tp->tx_queue)) 4329 return true; 4330 else 4331 return false; 4332 } 4333 4334 static int rtl8152_runtime_resume(struct r8152 *tp) 4335 { 4336 struct net_device *netdev = tp->netdev; 4337 4338 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4339 struct napi_struct *napi = &tp->napi; 4340 4341 tp->rtl_ops.autosuspend_en(tp, false); 4342 napi_disable(napi); 4343 set_bit(WORK_ENABLE, &tp->flags); 4344 4345 if (netif_carrier_ok(netdev)) { 4346 if (rtl8152_get_speed(tp) & LINK_STATUS) { 4347 rtl_start_rx(tp); 4348 } else { 4349 netif_carrier_off(netdev); 4350 tp->rtl_ops.disable(tp); 4351 netif_info(tp, link, netdev, "linking down\n"); 4352 } 4353 } 4354 4355 napi_enable(napi); 4356 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4357 smp_mb__after_atomic(); 4358 4359 if (!list_empty(&tp->rx_done)) 4360 napi_schedule(&tp->napi); 4361 4362 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4363 } else { 4364 if (netdev->flags & IFF_UP) 4365 tp->rtl_ops.autosuspend_en(tp, false); 4366 4367 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4368 } 4369 4370 return 0; 4371 } 4372 4373 static int rtl8152_system_resume(struct r8152 *tp) 4374 { 4375 struct net_device *netdev = tp->netdev; 4376 4377 netif_device_attach(netdev); 4378 4379 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4380 tp->rtl_ops.up(tp); 4381 netif_carrier_off(netdev); 4382 set_bit(WORK_ENABLE, &tp->flags); 4383 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4384 } 4385 4386 return 0; 4387 } 4388 4389 static int rtl8152_runtime_suspend(struct r8152 *tp) 4390 { 4391 struct net_device *netdev = tp->netdev; 4392 int ret = 0; 4393 4394 set_bit(SELECTIVE_SUSPEND, &tp->flags); 4395 smp_mb__after_atomic(); 4396 4397 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4398 u32 rcr = 0; 4399 4400 if (netif_carrier_ok(netdev)) { 4401 u32 ocp_data; 4402 4403 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 4404 ocp_data = rcr & ~RCR_ACPT_ALL; 4405 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 4406 rxdy_gated_en(tp, true); 4407 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 4408 PLA_OOB_CTRL); 4409 if (!(ocp_data & RXFIFO_EMPTY)) { 4410 rxdy_gated_en(tp, false); 4411 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4412 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4413 smp_mb__after_atomic(); 4414 ret = -EBUSY; 4415 goto out1; 4416 } 4417 } 4418 4419 clear_bit(WORK_ENABLE, &tp->flags); 4420 usb_kill_urb(tp->intr_urb); 4421 4422 tp->rtl_ops.autosuspend_en(tp, true); 4423 4424 if (netif_carrier_ok(netdev)) { 4425 struct napi_struct *napi = &tp->napi; 4426 4427 napi_disable(napi); 4428 rtl_stop_rx(tp); 4429 rxdy_gated_en(tp, false); 4430 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4431 napi_enable(napi); 4432 } 4433 4434 if (delay_autosuspend(tp)) { 4435 rtl8152_runtime_resume(tp); 4436 ret = -EBUSY; 4437 } 4438 } 4439 4440 out1: 4441 return ret; 4442 } 4443 4444 static int rtl8152_system_suspend(struct r8152 *tp) 4445 { 4446 struct net_device *netdev = tp->netdev; 4447 4448 netif_device_detach(netdev); 4449 4450 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4451 struct napi_struct *napi = &tp->napi; 4452 4453 clear_bit(WORK_ENABLE, &tp->flags); 4454 usb_kill_urb(tp->intr_urb); 4455 napi_disable(napi); 4456 cancel_delayed_work_sync(&tp->schedule); 4457 tp->rtl_ops.down(tp); 4458 napi_enable(napi); 4459 } 4460 4461 return 0; 4462 } 4463 4464 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 4465 { 4466 struct r8152 *tp = usb_get_intfdata(intf); 4467 int ret; 4468 4469 mutex_lock(&tp->control); 4470 4471 if (PMSG_IS_AUTO(message)) 4472 ret = rtl8152_runtime_suspend(tp); 4473 else 4474 ret = rtl8152_system_suspend(tp); 4475 4476 mutex_unlock(&tp->control); 4477 4478 return ret; 4479 } 4480 4481 static int rtl8152_resume(struct usb_interface *intf) 4482 { 4483 struct r8152 *tp = usb_get_intfdata(intf); 4484 int ret; 4485 4486 mutex_lock(&tp->control); 4487 4488 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) 4489 ret = rtl8152_runtime_resume(tp); 4490 else 4491 ret = rtl8152_system_resume(tp); 4492 4493 mutex_unlock(&tp->control); 4494 4495 return ret; 4496 } 4497 4498 static int rtl8152_reset_resume(struct usb_interface *intf) 4499 { 4500 struct r8152 *tp = usb_get_intfdata(intf); 4501 4502 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4503 mutex_lock(&tp->control); 4504 tp->rtl_ops.init(tp); 4505 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 4506 mutex_unlock(&tp->control); 4507 return rtl8152_resume(intf); 4508 } 4509 4510 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4511 { 4512 struct r8152 *tp = netdev_priv(dev); 4513 4514 if (usb_autopm_get_interface(tp->intf) < 0) 4515 return; 4516 4517 if (!rtl_can_wakeup(tp)) { 4518 wol->supported = 0; 4519 wol->wolopts = 0; 4520 } else { 4521 mutex_lock(&tp->control); 4522 wol->supported = WAKE_ANY; 4523 wol->wolopts = __rtl_get_wol(tp); 4524 mutex_unlock(&tp->control); 4525 } 4526 4527 usb_autopm_put_interface(tp->intf); 4528 } 4529 4530 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4531 { 4532 struct r8152 *tp = netdev_priv(dev); 4533 int ret; 4534 4535 if (!rtl_can_wakeup(tp)) 4536 return -EOPNOTSUPP; 4537 4538 if (wol->wolopts & ~WAKE_ANY) 4539 return -EINVAL; 4540 4541 ret = usb_autopm_get_interface(tp->intf); 4542 if (ret < 0) 4543 goto out_set_wol; 4544 4545 mutex_lock(&tp->control); 4546 4547 __rtl_set_wol(tp, wol->wolopts); 4548 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 4549 4550 mutex_unlock(&tp->control); 4551 4552 usb_autopm_put_interface(tp->intf); 4553 4554 out_set_wol: 4555 return ret; 4556 } 4557 4558 static u32 rtl8152_get_msglevel(struct net_device *dev) 4559 { 4560 struct r8152 *tp = netdev_priv(dev); 4561 4562 return tp->msg_enable; 4563 } 4564 4565 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 4566 { 4567 struct r8152 *tp = netdev_priv(dev); 4568 4569 tp->msg_enable = value; 4570 } 4571 4572 static void rtl8152_get_drvinfo(struct net_device *netdev, 4573 struct ethtool_drvinfo *info) 4574 { 4575 struct r8152 *tp = netdev_priv(netdev); 4576 4577 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 4578 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 4579 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 4580 } 4581 4582 static 4583 int rtl8152_get_link_ksettings(struct net_device *netdev, 4584 struct ethtool_link_ksettings *cmd) 4585 { 4586 struct r8152 *tp = netdev_priv(netdev); 4587 int ret; 4588 4589 if (!tp->mii.mdio_read) 4590 return -EOPNOTSUPP; 4591 4592 ret = usb_autopm_get_interface(tp->intf); 4593 if (ret < 0) 4594 goto out; 4595 4596 mutex_lock(&tp->control); 4597 4598 mii_ethtool_get_link_ksettings(&tp->mii, cmd); 4599 4600 mutex_unlock(&tp->control); 4601 4602 usb_autopm_put_interface(tp->intf); 4603 4604 out: 4605 return ret; 4606 } 4607 4608 static int rtl8152_set_link_ksettings(struct net_device *dev, 4609 const struct ethtool_link_ksettings *cmd) 4610 { 4611 struct r8152 *tp = netdev_priv(dev); 4612 int ret; 4613 4614 ret = usb_autopm_get_interface(tp->intf); 4615 if (ret < 0) 4616 goto out; 4617 4618 mutex_lock(&tp->control); 4619 4620 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, 4621 cmd->base.duplex); 4622 if (!ret) { 4623 tp->autoneg = cmd->base.autoneg; 4624 tp->speed = cmd->base.speed; 4625 tp->duplex = cmd->base.duplex; 4626 } 4627 4628 mutex_unlock(&tp->control); 4629 4630 usb_autopm_put_interface(tp->intf); 4631 4632 out: 4633 return ret; 4634 } 4635 4636 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 4637 "tx_packets", 4638 "rx_packets", 4639 "tx_errors", 4640 "rx_errors", 4641 "rx_missed", 4642 "align_errors", 4643 "tx_single_collisions", 4644 "tx_multi_collisions", 4645 "rx_unicast", 4646 "rx_broadcast", 4647 "rx_multicast", 4648 "tx_aborted", 4649 "tx_underrun", 4650 }; 4651 4652 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 4653 { 4654 switch (sset) { 4655 case ETH_SS_STATS: 4656 return ARRAY_SIZE(rtl8152_gstrings); 4657 default: 4658 return -EOPNOTSUPP; 4659 } 4660 } 4661 4662 static void rtl8152_get_ethtool_stats(struct net_device *dev, 4663 struct ethtool_stats *stats, u64 *data) 4664 { 4665 struct r8152 *tp = netdev_priv(dev); 4666 struct tally_counter tally; 4667 4668 if (usb_autopm_get_interface(tp->intf) < 0) 4669 return; 4670 4671 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 4672 4673 usb_autopm_put_interface(tp->intf); 4674 4675 data[0] = le64_to_cpu(tally.tx_packets); 4676 data[1] = le64_to_cpu(tally.rx_packets); 4677 data[2] = le64_to_cpu(tally.tx_errors); 4678 data[3] = le32_to_cpu(tally.rx_errors); 4679 data[4] = le16_to_cpu(tally.rx_missed); 4680 data[5] = le16_to_cpu(tally.align_errors); 4681 data[6] = le32_to_cpu(tally.tx_one_collision); 4682 data[7] = le32_to_cpu(tally.tx_multi_collision); 4683 data[8] = le64_to_cpu(tally.rx_unicast); 4684 data[9] = le64_to_cpu(tally.rx_broadcast); 4685 data[10] = le32_to_cpu(tally.rx_multicast); 4686 data[11] = le16_to_cpu(tally.tx_aborted); 4687 data[12] = le16_to_cpu(tally.tx_underrun); 4688 } 4689 4690 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4691 { 4692 switch (stringset) { 4693 case ETH_SS_STATS: 4694 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 4695 break; 4696 } 4697 } 4698 4699 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 4700 { 4701 u32 ocp_data, lp, adv, supported = 0; 4702 u16 val; 4703 4704 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 4705 supported = mmd_eee_cap_to_ethtool_sup_t(val); 4706 4707 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 4708 adv = mmd_eee_adv_to_ethtool_adv_t(val); 4709 4710 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 4711 lp = mmd_eee_adv_to_ethtool_adv_t(val); 4712 4713 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 4714 ocp_data &= EEE_RX_EN | EEE_TX_EN; 4715 4716 eee->eee_enabled = !!ocp_data; 4717 eee->eee_active = !!(supported & adv & lp); 4718 eee->supported = supported; 4719 eee->advertised = adv; 4720 eee->lp_advertised = lp; 4721 4722 return 0; 4723 } 4724 4725 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4726 { 4727 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4728 4729 r8152_eee_en(tp, eee->eee_enabled); 4730 4731 if (!eee->eee_enabled) 4732 val = 0; 4733 4734 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); 4735 4736 return 0; 4737 } 4738 4739 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 4740 { 4741 u32 ocp_data, lp, adv, supported = 0; 4742 u16 val; 4743 4744 val = ocp_reg_read(tp, OCP_EEE_ABLE); 4745 supported = mmd_eee_cap_to_ethtool_sup_t(val); 4746 4747 val = ocp_reg_read(tp, OCP_EEE_ADV); 4748 adv = mmd_eee_adv_to_ethtool_adv_t(val); 4749 4750 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 4751 lp = mmd_eee_adv_to_ethtool_adv_t(val); 4752 4753 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 4754 ocp_data &= EEE_RX_EN | EEE_TX_EN; 4755 4756 eee->eee_enabled = !!ocp_data; 4757 eee->eee_active = !!(supported & adv & lp); 4758 eee->supported = supported; 4759 eee->advertised = adv; 4760 eee->lp_advertised = lp; 4761 4762 return 0; 4763 } 4764 4765 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4766 { 4767 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4768 4769 r8153_eee_en(tp, eee->eee_enabled); 4770 4771 if (!eee->eee_enabled) 4772 val = 0; 4773 4774 ocp_reg_write(tp, OCP_EEE_ADV, val); 4775 4776 return 0; 4777 } 4778 4779 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4780 { 4781 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4782 4783 r8153b_eee_en(tp, eee->eee_enabled); 4784 4785 if (!eee->eee_enabled) 4786 val = 0; 4787 4788 ocp_reg_write(tp, OCP_EEE_ADV, val); 4789 4790 return 0; 4791 } 4792 4793 static int 4794 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) 4795 { 4796 struct r8152 *tp = netdev_priv(net); 4797 int ret; 4798 4799 ret = usb_autopm_get_interface(tp->intf); 4800 if (ret < 0) 4801 goto out; 4802 4803 mutex_lock(&tp->control); 4804 4805 ret = tp->rtl_ops.eee_get(tp, edata); 4806 4807 mutex_unlock(&tp->control); 4808 4809 usb_autopm_put_interface(tp->intf); 4810 4811 out: 4812 return ret; 4813 } 4814 4815 static int 4816 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) 4817 { 4818 struct r8152 *tp = netdev_priv(net); 4819 int ret; 4820 4821 ret = usb_autopm_get_interface(tp->intf); 4822 if (ret < 0) 4823 goto out; 4824 4825 mutex_lock(&tp->control); 4826 4827 ret = tp->rtl_ops.eee_set(tp, edata); 4828 if (!ret) 4829 ret = mii_nway_restart(&tp->mii); 4830 4831 mutex_unlock(&tp->control); 4832 4833 usb_autopm_put_interface(tp->intf); 4834 4835 out: 4836 return ret; 4837 } 4838 4839 static int rtl8152_nway_reset(struct net_device *dev) 4840 { 4841 struct r8152 *tp = netdev_priv(dev); 4842 int ret; 4843 4844 ret = usb_autopm_get_interface(tp->intf); 4845 if (ret < 0) 4846 goto out; 4847 4848 mutex_lock(&tp->control); 4849 4850 ret = mii_nway_restart(&tp->mii); 4851 4852 mutex_unlock(&tp->control); 4853 4854 usb_autopm_put_interface(tp->intf); 4855 4856 out: 4857 return ret; 4858 } 4859 4860 static int rtl8152_get_coalesce(struct net_device *netdev, 4861 struct ethtool_coalesce *coalesce) 4862 { 4863 struct r8152 *tp = netdev_priv(netdev); 4864 4865 switch (tp->version) { 4866 case RTL_VER_01: 4867 case RTL_VER_02: 4868 case RTL_VER_07: 4869 return -EOPNOTSUPP; 4870 default: 4871 break; 4872 } 4873 4874 coalesce->rx_coalesce_usecs = tp->coalesce; 4875 4876 return 0; 4877 } 4878 4879 static int rtl8152_set_coalesce(struct net_device *netdev, 4880 struct ethtool_coalesce *coalesce) 4881 { 4882 struct r8152 *tp = netdev_priv(netdev); 4883 int ret; 4884 4885 switch (tp->version) { 4886 case RTL_VER_01: 4887 case RTL_VER_02: 4888 case RTL_VER_07: 4889 return -EOPNOTSUPP; 4890 default: 4891 break; 4892 } 4893 4894 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) 4895 return -EINVAL; 4896 4897 ret = usb_autopm_get_interface(tp->intf); 4898 if (ret < 0) 4899 return ret; 4900 4901 mutex_lock(&tp->control); 4902 4903 if (tp->coalesce != coalesce->rx_coalesce_usecs) { 4904 tp->coalesce = coalesce->rx_coalesce_usecs; 4905 4906 if (netif_running(tp->netdev) && netif_carrier_ok(netdev)) 4907 r8153_set_rx_early_timeout(tp); 4908 } 4909 4910 mutex_unlock(&tp->control); 4911 4912 usb_autopm_put_interface(tp->intf); 4913 4914 return ret; 4915 } 4916 4917 static const struct ethtool_ops ops = { 4918 .get_drvinfo = rtl8152_get_drvinfo, 4919 .get_link = ethtool_op_get_link, 4920 .nway_reset = rtl8152_nway_reset, 4921 .get_msglevel = rtl8152_get_msglevel, 4922 .set_msglevel = rtl8152_set_msglevel, 4923 .get_wol = rtl8152_get_wol, 4924 .set_wol = rtl8152_set_wol, 4925 .get_strings = rtl8152_get_strings, 4926 .get_sset_count = rtl8152_get_sset_count, 4927 .get_ethtool_stats = rtl8152_get_ethtool_stats, 4928 .get_coalesce = rtl8152_get_coalesce, 4929 .set_coalesce = rtl8152_set_coalesce, 4930 .get_eee = rtl_ethtool_get_eee, 4931 .set_eee = rtl_ethtool_set_eee, 4932 .get_link_ksettings = rtl8152_get_link_ksettings, 4933 .set_link_ksettings = rtl8152_set_link_ksettings, 4934 }; 4935 4936 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 4937 { 4938 struct r8152 *tp = netdev_priv(netdev); 4939 struct mii_ioctl_data *data = if_mii(rq); 4940 int res; 4941 4942 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4943 return -ENODEV; 4944 4945 res = usb_autopm_get_interface(tp->intf); 4946 if (res < 0) 4947 goto out; 4948 4949 switch (cmd) { 4950 case SIOCGMIIPHY: 4951 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 4952 break; 4953 4954 case SIOCGMIIREG: 4955 mutex_lock(&tp->control); 4956 data->val_out = r8152_mdio_read(tp, data->reg_num); 4957 mutex_unlock(&tp->control); 4958 break; 4959 4960 case SIOCSMIIREG: 4961 if (!capable(CAP_NET_ADMIN)) { 4962 res = -EPERM; 4963 break; 4964 } 4965 mutex_lock(&tp->control); 4966 r8152_mdio_write(tp, data->reg_num, data->val_in); 4967 mutex_unlock(&tp->control); 4968 break; 4969 4970 default: 4971 res = -EOPNOTSUPP; 4972 } 4973 4974 usb_autopm_put_interface(tp->intf); 4975 4976 out: 4977 return res; 4978 } 4979 4980 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 4981 { 4982 struct r8152 *tp = netdev_priv(dev); 4983 int ret; 4984 4985 switch (tp->version) { 4986 case RTL_VER_01: 4987 case RTL_VER_02: 4988 case RTL_VER_07: 4989 dev->mtu = new_mtu; 4990 return 0; 4991 default: 4992 break; 4993 } 4994 4995 ret = usb_autopm_get_interface(tp->intf); 4996 if (ret < 0) 4997 return ret; 4998 4999 mutex_lock(&tp->control); 5000 5001 dev->mtu = new_mtu; 5002 5003 if (netif_running(dev)) { 5004 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 5005 5006 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms); 5007 5008 if (netif_carrier_ok(dev)) 5009 r8153_set_rx_early_size(tp); 5010 } 5011 5012 mutex_unlock(&tp->control); 5013 5014 usb_autopm_put_interface(tp->intf); 5015 5016 return ret; 5017 } 5018 5019 static const struct net_device_ops rtl8152_netdev_ops = { 5020 .ndo_open = rtl8152_open, 5021 .ndo_stop = rtl8152_close, 5022 .ndo_do_ioctl = rtl8152_ioctl, 5023 .ndo_start_xmit = rtl8152_start_xmit, 5024 .ndo_tx_timeout = rtl8152_tx_timeout, 5025 .ndo_set_features = rtl8152_set_features, 5026 .ndo_set_rx_mode = rtl8152_set_rx_mode, 5027 .ndo_set_mac_address = rtl8152_set_mac_address, 5028 .ndo_change_mtu = rtl8152_change_mtu, 5029 .ndo_validate_addr = eth_validate_addr, 5030 .ndo_features_check = rtl8152_features_check, 5031 }; 5032 5033 static void rtl8152_unload(struct r8152 *tp) 5034 { 5035 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5036 return; 5037 5038 if (tp->version != RTL_VER_01) 5039 r8152_power_cut_en(tp, true); 5040 } 5041 5042 static void rtl8153_unload(struct r8152 *tp) 5043 { 5044 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5045 return; 5046 5047 r8153_power_cut_en(tp, false); 5048 } 5049 5050 static void rtl8153b_unload(struct r8152 *tp) 5051 { 5052 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5053 return; 5054 5055 r8153b_power_cut_en(tp, false); 5056 } 5057 5058 static int rtl_ops_init(struct r8152 *tp) 5059 { 5060 struct rtl_ops *ops = &tp->rtl_ops; 5061 int ret = 0; 5062 5063 switch (tp->version) { 5064 case RTL_VER_01: 5065 case RTL_VER_02: 5066 case RTL_VER_07: 5067 ops->init = r8152b_init; 5068 ops->enable = rtl8152_enable; 5069 ops->disable = rtl8152_disable; 5070 ops->up = rtl8152_up; 5071 ops->down = rtl8152_down; 5072 ops->unload = rtl8152_unload; 5073 ops->eee_get = r8152_get_eee; 5074 ops->eee_set = r8152_set_eee; 5075 ops->in_nway = rtl8152_in_nway; 5076 ops->hw_phy_cfg = r8152b_hw_phy_cfg; 5077 ops->autosuspend_en = rtl_runtime_suspend_enable; 5078 break; 5079 5080 case RTL_VER_03: 5081 case RTL_VER_04: 5082 case RTL_VER_05: 5083 case RTL_VER_06: 5084 ops->init = r8153_init; 5085 ops->enable = rtl8153_enable; 5086 ops->disable = rtl8153_disable; 5087 ops->up = rtl8153_up; 5088 ops->down = rtl8153_down; 5089 ops->unload = rtl8153_unload; 5090 ops->eee_get = r8153_get_eee; 5091 ops->eee_set = r8153_set_eee; 5092 ops->in_nway = rtl8153_in_nway; 5093 ops->hw_phy_cfg = r8153_hw_phy_cfg; 5094 ops->autosuspend_en = rtl8153_runtime_enable; 5095 break; 5096 5097 case RTL_VER_08: 5098 case RTL_VER_09: 5099 ops->init = r8153b_init; 5100 ops->enable = rtl8153_enable; 5101 ops->disable = rtl8153b_disable; 5102 ops->up = rtl8153b_up; 5103 ops->down = rtl8153b_down; 5104 ops->unload = rtl8153b_unload; 5105 ops->eee_get = r8153_get_eee; 5106 ops->eee_set = r8153b_set_eee; 5107 ops->in_nway = rtl8153_in_nway; 5108 ops->hw_phy_cfg = r8153b_hw_phy_cfg; 5109 ops->autosuspend_en = rtl8153b_runtime_enable; 5110 break; 5111 5112 default: 5113 ret = -ENODEV; 5114 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 5115 break; 5116 } 5117 5118 return ret; 5119 } 5120 5121 static u8 rtl_get_version(struct usb_interface *intf) 5122 { 5123 struct usb_device *udev = interface_to_usbdev(intf); 5124 u32 ocp_data = 0; 5125 __le32 *tmp; 5126 u8 version; 5127 int ret; 5128 5129 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); 5130 if (!tmp) 5131 return 0; 5132 5133 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 5134 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 5135 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500); 5136 if (ret > 0) 5137 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK; 5138 5139 kfree(tmp); 5140 5141 switch (ocp_data) { 5142 case 0x4c00: 5143 version = RTL_VER_01; 5144 break; 5145 case 0x4c10: 5146 version = RTL_VER_02; 5147 break; 5148 case 0x5c00: 5149 version = RTL_VER_03; 5150 break; 5151 case 0x5c10: 5152 version = RTL_VER_04; 5153 break; 5154 case 0x5c20: 5155 version = RTL_VER_05; 5156 break; 5157 case 0x5c30: 5158 version = RTL_VER_06; 5159 break; 5160 case 0x4800: 5161 version = RTL_VER_07; 5162 break; 5163 case 0x6000: 5164 version = RTL_VER_08; 5165 break; 5166 case 0x6010: 5167 version = RTL_VER_09; 5168 break; 5169 default: 5170 version = RTL_VER_UNKNOWN; 5171 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); 5172 break; 5173 } 5174 5175 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); 5176 5177 return version; 5178 } 5179 5180 static int rtl8152_probe(struct usb_interface *intf, 5181 const struct usb_device_id *id) 5182 { 5183 struct usb_device *udev = interface_to_usbdev(intf); 5184 u8 version = rtl_get_version(intf); 5185 struct r8152 *tp; 5186 struct net_device *netdev; 5187 int ret; 5188 5189 if (version == RTL_VER_UNKNOWN) 5190 return -ENODEV; 5191 5192 if (udev->actconfig->desc.bConfigurationValue != 1) { 5193 usb_driver_set_configuration(udev, 1); 5194 return -ENODEV; 5195 } 5196 5197 usb_reset_device(udev); 5198 netdev = alloc_etherdev(sizeof(struct r8152)); 5199 if (!netdev) { 5200 dev_err(&intf->dev, "Out of memory\n"); 5201 return -ENOMEM; 5202 } 5203 5204 SET_NETDEV_DEV(netdev, &intf->dev); 5205 tp = netdev_priv(netdev); 5206 tp->msg_enable = 0x7FFF; 5207 5208 tp->udev = udev; 5209 tp->netdev = netdev; 5210 tp->intf = intf; 5211 tp->version = version; 5212 5213 switch (version) { 5214 case RTL_VER_01: 5215 case RTL_VER_02: 5216 case RTL_VER_07: 5217 tp->mii.supports_gmii = 0; 5218 break; 5219 default: 5220 tp->mii.supports_gmii = 1; 5221 break; 5222 } 5223 5224 ret = rtl_ops_init(tp); 5225 if (ret) 5226 goto out; 5227 5228 mutex_init(&tp->control); 5229 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 5230 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); 5231 5232 netdev->netdev_ops = &rtl8152_netdev_ops; 5233 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 5234 5235 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5236 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 5237 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 5238 NETIF_F_HW_VLAN_CTAG_TX; 5239 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5240 NETIF_F_TSO | NETIF_F_FRAGLIST | 5241 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 5242 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; 5243 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 5244 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 5245 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 5246 5247 if (tp->version == RTL_VER_01) { 5248 netdev->features &= ~NETIF_F_RXCSUM; 5249 netdev->hw_features &= ~NETIF_F_RXCSUM; 5250 } 5251 5252 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial && 5253 (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) { 5254 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation"); 5255 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags); 5256 } 5257 5258 netdev->ethtool_ops = &ops; 5259 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 5260 5261 /* MTU range: 68 - 1500 or 9194 */ 5262 netdev->min_mtu = ETH_MIN_MTU; 5263 switch (tp->version) { 5264 case RTL_VER_01: 5265 case RTL_VER_02: 5266 netdev->max_mtu = ETH_DATA_LEN; 5267 break; 5268 default: 5269 netdev->max_mtu = RTL8153_MAX_MTU; 5270 break; 5271 } 5272 5273 tp->mii.dev = netdev; 5274 tp->mii.mdio_read = read_mii_word; 5275 tp->mii.mdio_write = write_mii_word; 5276 tp->mii.phy_id_mask = 0x3f; 5277 tp->mii.reg_num_mask = 0x1f; 5278 tp->mii.phy_id = R8152_PHY_ID; 5279 5280 tp->autoneg = AUTONEG_ENABLE; 5281 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100; 5282 tp->duplex = DUPLEX_FULL; 5283 5284 intf->needs_remote_wakeup = 1; 5285 5286 tp->rtl_ops.init(tp); 5287 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 5288 set_ethernet_addr(tp); 5289 5290 usb_set_intfdata(intf, tp); 5291 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); 5292 5293 ret = register_netdev(netdev); 5294 if (ret != 0) { 5295 netif_err(tp, probe, netdev, "couldn't register the device\n"); 5296 goto out1; 5297 } 5298 5299 if (!rtl_can_wakeup(tp)) 5300 __rtl_set_wol(tp, 0); 5301 5302 tp->saved_wolopts = __rtl_get_wol(tp); 5303 if (tp->saved_wolopts) 5304 device_set_wakeup_enable(&udev->dev, true); 5305 else 5306 device_set_wakeup_enable(&udev->dev, false); 5307 5308 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 5309 5310 return 0; 5311 5312 out1: 5313 netif_napi_del(&tp->napi); 5314 usb_set_intfdata(intf, NULL); 5315 out: 5316 free_netdev(netdev); 5317 return ret; 5318 } 5319 5320 static void rtl8152_disconnect(struct usb_interface *intf) 5321 { 5322 struct r8152 *tp = usb_get_intfdata(intf); 5323 5324 usb_set_intfdata(intf, NULL); 5325 if (tp) { 5326 struct usb_device *udev = tp->udev; 5327 5328 if (udev->state == USB_STATE_NOTATTACHED) 5329 set_bit(RTL8152_UNPLUG, &tp->flags); 5330 5331 netif_napi_del(&tp->napi); 5332 unregister_netdev(tp->netdev); 5333 cancel_delayed_work_sync(&tp->hw_phy_work); 5334 tp->rtl_ops.unload(tp); 5335 free_netdev(tp->netdev); 5336 } 5337 } 5338 5339 #define REALTEK_USB_DEVICE(vend, prod) \ 5340 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ 5341 USB_DEVICE_ID_MATCH_INT_CLASS, \ 5342 .idVendor = (vend), \ 5343 .idProduct = (prod), \ 5344 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ 5345 }, \ 5346 { \ 5347 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ 5348 USB_DEVICE_ID_MATCH_DEVICE, \ 5349 .idVendor = (vend), \ 5350 .idProduct = (prod), \ 5351 .bInterfaceClass = USB_CLASS_COMM, \ 5352 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ 5353 .bInterfaceProtocol = USB_CDC_PROTO_NONE 5354 5355 /* table of devices that work with this driver */ 5356 static const struct usb_device_id rtl8152_table[] = { 5357 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)}, 5358 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, 5359 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, 5360 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)}, 5361 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)}, 5362 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, 5363 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, 5364 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)}, 5365 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)}, 5366 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, 5367 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)}, 5368 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)}, 5369 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)}, 5370 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, 5371 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)}, 5372 {} 5373 }; 5374 5375 MODULE_DEVICE_TABLE(usb, rtl8152_table); 5376 5377 static struct usb_driver rtl8152_driver = { 5378 .name = MODULENAME, 5379 .id_table = rtl8152_table, 5380 .probe = rtl8152_probe, 5381 .disconnect = rtl8152_disconnect, 5382 .suspend = rtl8152_suspend, 5383 .resume = rtl8152_resume, 5384 .reset_resume = rtl8152_reset_resume, 5385 .pre_reset = rtl8152_pre_reset, 5386 .post_reset = rtl8152_post_reset, 5387 .supports_autosuspend = 1, 5388 .disable_hub_initiated_lpm = 1, 5389 }; 5390 5391 module_usb_driver(rtl8152_driver); 5392 5393 MODULE_AUTHOR(DRIVER_AUTHOR); 5394 MODULE_DESCRIPTION(DRIVER_DESC); 5395 MODULE_LICENSE("GPL"); 5396 MODULE_VERSION(DRIVER_VERSION); 5397