1 /* 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2 as published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/signal.h> 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/usb.h> 18 #include <linux/crc32.h> 19 #include <linux/if_vlan.h> 20 #include <linux/uaccess.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include <net/ip6_checksum.h> 25 #include <uapi/linux/mdio.h> 26 #include <linux/mdio.h> 27 #include <linux/usb/cdc.h> 28 #include <linux/suspend.h> 29 #include <linux/acpi.h> 30 31 /* Information for net-next */ 32 #define NETNEXT_VERSION "09" 33 34 /* Information for net */ 35 #define NET_VERSION "9" 36 37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION 38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 40 #define MODULENAME "r8152" 41 42 #define R8152_PHY_ID 32 43 44 #define PLA_IDR 0xc000 45 #define PLA_RCR 0xc010 46 #define PLA_RMS 0xc016 47 #define PLA_RXFIFO_CTRL0 0xc0a0 48 #define PLA_RXFIFO_CTRL1 0xc0a4 49 #define PLA_RXFIFO_CTRL2 0xc0a8 50 #define PLA_DMY_REG0 0xc0b0 51 #define PLA_FMC 0xc0b4 52 #define PLA_CFG_WOL 0xc0b6 53 #define PLA_TEREDO_CFG 0xc0bc 54 #define PLA_TEREDO_WAKE_BASE 0xc0c4 55 #define PLA_MAR 0xcd00 56 #define PLA_BACKUP 0xd000 57 #define PAL_BDC_CR 0xd1a0 58 #define PLA_TEREDO_TIMER 0xd2cc 59 #define PLA_REALWOW_TIMER 0xd2e8 60 #define PLA_EFUSE_DATA 0xdd00 61 #define PLA_EFUSE_CMD 0xdd02 62 #define PLA_LEDSEL 0xdd90 63 #define PLA_LED_FEATURE 0xdd92 64 #define PLA_PHYAR 0xde00 65 #define PLA_BOOT_CTRL 0xe004 66 #define PLA_GPHY_INTR_IMR 0xe022 67 #define PLA_EEE_CR 0xe040 68 #define PLA_EEEP_CR 0xe080 69 #define PLA_MAC_PWR_CTRL 0xe0c0 70 #define PLA_MAC_PWR_CTRL2 0xe0ca 71 #define PLA_MAC_PWR_CTRL3 0xe0cc 72 #define PLA_MAC_PWR_CTRL4 0xe0ce 73 #define PLA_WDT6_CTRL 0xe428 74 #define PLA_TCR0 0xe610 75 #define PLA_TCR1 0xe612 76 #define PLA_MTPS 0xe615 77 #define PLA_TXFIFO_CTRL 0xe618 78 #define PLA_RSTTALLY 0xe800 79 #define PLA_CR 0xe813 80 #define PLA_CRWECR 0xe81c 81 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 82 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 83 #define PLA_CONFIG5 0xe822 84 #define PLA_PHY_PWR 0xe84c 85 #define PLA_OOB_CTRL 0xe84f 86 #define PLA_CPCR 0xe854 87 #define PLA_MISC_0 0xe858 88 #define PLA_MISC_1 0xe85a 89 #define PLA_OCP_GPHY_BASE 0xe86c 90 #define PLA_TALLYCNT 0xe890 91 #define PLA_SFF_STS_7 0xe8de 92 #define PLA_PHYSTATUS 0xe908 93 #define PLA_BP_BA 0xfc26 94 #define PLA_BP_0 0xfc28 95 #define PLA_BP_1 0xfc2a 96 #define PLA_BP_2 0xfc2c 97 #define PLA_BP_3 0xfc2e 98 #define PLA_BP_4 0xfc30 99 #define PLA_BP_5 0xfc32 100 #define PLA_BP_6 0xfc34 101 #define PLA_BP_7 0xfc36 102 #define PLA_BP_EN 0xfc38 103 104 #define USB_USB2PHY 0xb41e 105 #define USB_SSPHYLINK2 0xb428 106 #define USB_U2P3_CTRL 0xb460 107 #define USB_CSR_DUMMY1 0xb464 108 #define USB_CSR_DUMMY2 0xb466 109 #define USB_DEV_STAT 0xb808 110 #define USB_CONNECT_TIMER 0xcbf8 111 #define USB_MSC_TIMER 0xcbfc 112 #define USB_BURST_SIZE 0xcfc0 113 #define USB_LPM_CONFIG 0xcfd8 114 #define USB_USB_CTRL 0xd406 115 #define USB_PHY_CTRL 0xd408 116 #define USB_TX_AGG 0xd40a 117 #define USB_RX_BUF_TH 0xd40c 118 #define USB_USB_TIMER 0xd428 119 #define USB_RX_EARLY_TIMEOUT 0xd42c 120 #define USB_RX_EARLY_SIZE 0xd42e 121 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ 122 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ 123 #define USB_TX_DMA 0xd434 124 #define USB_UPT_RXDMA_OWN 0xd437 125 #define USB_TOLERANCE 0xd490 126 #define USB_LPM_CTRL 0xd41a 127 #define USB_BMU_RESET 0xd4b0 128 #define USB_U1U2_TIMER 0xd4da 129 #define USB_UPS_CTRL 0xd800 130 #define USB_POWER_CUT 0xd80a 131 #define USB_MISC_0 0xd81a 132 #define USB_AFE_CTRL2 0xd824 133 #define USB_UPS_CFG 0xd842 134 #define USB_UPS_FLAGS 0xd848 135 #define USB_WDT11_CTRL 0xe43c 136 #define USB_BP_BA 0xfc26 137 #define USB_BP_0 0xfc28 138 #define USB_BP_1 0xfc2a 139 #define USB_BP_2 0xfc2c 140 #define USB_BP_3 0xfc2e 141 #define USB_BP_4 0xfc30 142 #define USB_BP_5 0xfc32 143 #define USB_BP_6 0xfc34 144 #define USB_BP_7 0xfc36 145 #define USB_BP_EN 0xfc38 146 #define USB_BP_8 0xfc38 147 #define USB_BP_9 0xfc3a 148 #define USB_BP_10 0xfc3c 149 #define USB_BP_11 0xfc3e 150 #define USB_BP_12 0xfc40 151 #define USB_BP_13 0xfc42 152 #define USB_BP_14 0xfc44 153 #define USB_BP_15 0xfc46 154 #define USB_BP2_EN 0xfc48 155 156 /* OCP Registers */ 157 #define OCP_ALDPS_CONFIG 0x2010 158 #define OCP_EEE_CONFIG1 0x2080 159 #define OCP_EEE_CONFIG2 0x2092 160 #define OCP_EEE_CONFIG3 0x2094 161 #define OCP_BASE_MII 0xa400 162 #define OCP_EEE_AR 0xa41a 163 #define OCP_EEE_DATA 0xa41c 164 #define OCP_PHY_STATUS 0xa420 165 #define OCP_NCTL_CFG 0xa42c 166 #define OCP_POWER_CFG 0xa430 167 #define OCP_EEE_CFG 0xa432 168 #define OCP_SRAM_ADDR 0xa436 169 #define OCP_SRAM_DATA 0xa438 170 #define OCP_DOWN_SPEED 0xa442 171 #define OCP_EEE_ABLE 0xa5c4 172 #define OCP_EEE_ADV 0xa5d0 173 #define OCP_EEE_LPABLE 0xa5d2 174 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ 175 #define OCP_PHY_PATCH_STAT 0xb800 176 #define OCP_PHY_PATCH_CMD 0xb820 177 #define OCP_ADC_IOFFSET 0xbcfc 178 #define OCP_ADC_CFG 0xbc06 179 #define OCP_SYSCLK_CFG 0xc416 180 181 /* SRAM Register */ 182 #define SRAM_GREEN_CFG 0x8011 183 #define SRAM_LPF_CFG 0x8012 184 #define SRAM_10M_AMP1 0x8080 185 #define SRAM_10M_AMP2 0x8082 186 #define SRAM_IMPEDANCE 0x8084 187 188 /* PLA_RCR */ 189 #define RCR_AAP 0x00000001 190 #define RCR_APM 0x00000002 191 #define RCR_AM 0x00000004 192 #define RCR_AB 0x00000008 193 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 194 195 /* PLA_RXFIFO_CTRL0 */ 196 #define RXFIFO_THR1_NORMAL 0x00080002 197 #define RXFIFO_THR1_OOB 0x01800003 198 199 /* PLA_RXFIFO_CTRL1 */ 200 #define RXFIFO_THR2_FULL 0x00000060 201 #define RXFIFO_THR2_HIGH 0x00000038 202 #define RXFIFO_THR2_OOB 0x0000004a 203 #define RXFIFO_THR2_NORMAL 0x00a0 204 205 /* PLA_RXFIFO_CTRL2 */ 206 #define RXFIFO_THR3_FULL 0x00000078 207 #define RXFIFO_THR3_HIGH 0x00000048 208 #define RXFIFO_THR3_OOB 0x0000005a 209 #define RXFIFO_THR3_NORMAL 0x0110 210 211 /* PLA_TXFIFO_CTRL */ 212 #define TXFIFO_THR_NORMAL 0x00400008 213 #define TXFIFO_THR_NORMAL2 0x01000008 214 215 /* PLA_DMY_REG0 */ 216 #define ECM_ALDPS 0x0002 217 218 /* PLA_FMC */ 219 #define FMC_FCR_MCU_EN 0x0001 220 221 /* PLA_EEEP_CR */ 222 #define EEEP_CR_EEEP_TX 0x0002 223 224 /* PLA_WDT6_CTRL */ 225 #define WDT6_SET_MODE 0x0010 226 227 /* PLA_TCR0 */ 228 #define TCR0_TX_EMPTY 0x0800 229 #define TCR0_AUTO_FIFO 0x0080 230 231 /* PLA_TCR1 */ 232 #define VERSION_MASK 0x7cf0 233 234 /* PLA_MTPS */ 235 #define MTPS_JUMBO (12 * 1024 / 64) 236 #define MTPS_DEFAULT (6 * 1024 / 64) 237 238 /* PLA_RSTTALLY */ 239 #define TALLY_RESET 0x0001 240 241 /* PLA_CR */ 242 #define CR_RST 0x10 243 #define CR_RE 0x08 244 #define CR_TE 0x04 245 246 /* PLA_CRWECR */ 247 #define CRWECR_NORAML 0x00 248 #define CRWECR_CONFIG 0xc0 249 250 /* PLA_OOB_CTRL */ 251 #define NOW_IS_OOB 0x80 252 #define TXFIFO_EMPTY 0x20 253 #define RXFIFO_EMPTY 0x10 254 #define LINK_LIST_READY 0x02 255 #define DIS_MCU_CLROOB 0x01 256 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 257 258 /* PLA_MISC_1 */ 259 #define RXDY_GATED_EN 0x0008 260 261 /* PLA_SFF_STS_7 */ 262 #define RE_INIT_LL 0x8000 263 #define MCU_BORW_EN 0x4000 264 265 /* PLA_CPCR */ 266 #define CPCR_RX_VLAN 0x0040 267 268 /* PLA_CFG_WOL */ 269 #define MAGIC_EN 0x0001 270 271 /* PLA_TEREDO_CFG */ 272 #define TEREDO_SEL 0x8000 273 #define TEREDO_WAKE_MASK 0x7f00 274 #define TEREDO_RS_EVENT_MASK 0x00fe 275 #define OOB_TEREDO_EN 0x0001 276 277 /* PAL_BDC_CR */ 278 #define ALDPS_PROXY_MODE 0x0001 279 280 /* PLA_EFUSE_CMD */ 281 #define EFUSE_READ_CMD BIT(15) 282 #define EFUSE_DATA_BIT16 BIT(7) 283 284 /* PLA_CONFIG34 */ 285 #define LINK_ON_WAKE_EN 0x0010 286 #define LINK_OFF_WAKE_EN 0x0008 287 288 /* PLA_CONFIG5 */ 289 #define BWF_EN 0x0040 290 #define MWF_EN 0x0020 291 #define UWF_EN 0x0010 292 #define LAN_WAKE_EN 0x0002 293 294 /* PLA_LED_FEATURE */ 295 #define LED_MODE_MASK 0x0700 296 297 /* PLA_PHY_PWR */ 298 #define TX_10M_IDLE_EN 0x0080 299 #define PFM_PWM_SWITCH 0x0040 300 301 /* PLA_MAC_PWR_CTRL */ 302 #define D3_CLK_GATED_EN 0x00004000 303 #define MCU_CLK_RATIO 0x07010f07 304 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 305 #define ALDPS_SPDWN_RATIO 0x0f87 306 307 /* PLA_MAC_PWR_CTRL2 */ 308 #define EEE_SPDWN_RATIO 0x8007 309 #define MAC_CLK_SPDWN_EN BIT(15) 310 311 /* PLA_MAC_PWR_CTRL3 */ 312 #define PKT_AVAIL_SPDWN_EN 0x0100 313 #define SUSPEND_SPDWN_EN 0x0004 314 #define U1U2_SPDWN_EN 0x0002 315 #define L1_SPDWN_EN 0x0001 316 317 /* PLA_MAC_PWR_CTRL4 */ 318 #define PWRSAVE_SPDWN_EN 0x1000 319 #define RXDV_SPDWN_EN 0x0800 320 #define TX10MIDLE_EN 0x0100 321 #define TP100_SPDWN_EN 0x0020 322 #define TP500_SPDWN_EN 0x0010 323 #define TP1000_SPDWN_EN 0x0008 324 #define EEE_SPDWN_EN 0x0001 325 326 /* PLA_GPHY_INTR_IMR */ 327 #define GPHY_STS_MSK 0x0001 328 #define SPEED_DOWN_MSK 0x0002 329 #define SPDWN_RXDV_MSK 0x0004 330 #define SPDWN_LINKCHG_MSK 0x0008 331 332 /* PLA_PHYAR */ 333 #define PHYAR_FLAG 0x80000000 334 335 /* PLA_EEE_CR */ 336 #define EEE_RX_EN 0x0001 337 #define EEE_TX_EN 0x0002 338 339 /* PLA_BOOT_CTRL */ 340 #define AUTOLOAD_DONE 0x0002 341 342 /* USB_USB2PHY */ 343 #define USB2PHY_SUSPEND 0x0001 344 #define USB2PHY_L1 0x0002 345 346 /* USB_SSPHYLINK2 */ 347 #define pwd_dn_scale_mask 0x3ffe 348 #define pwd_dn_scale(x) ((x) << 1) 349 350 /* USB_CSR_DUMMY1 */ 351 #define DYNAMIC_BURST 0x0001 352 353 /* USB_CSR_DUMMY2 */ 354 #define EP4_FULL_FC 0x0001 355 356 /* USB_DEV_STAT */ 357 #define STAT_SPEED_MASK 0x0006 358 #define STAT_SPEED_HIGH 0x0000 359 #define STAT_SPEED_FULL 0x0002 360 361 /* USB_LPM_CONFIG */ 362 #define LPM_U1U2_EN BIT(0) 363 364 /* USB_TX_AGG */ 365 #define TX_AGG_MAX_THRESHOLD 0x03 366 367 /* USB_RX_BUF_TH */ 368 #define RX_THR_SUPPER 0x0c350180 369 #define RX_THR_HIGH 0x7a120180 370 #define RX_THR_SLOW 0xffff0180 371 #define RX_THR_B 0x00010001 372 373 /* USB_TX_DMA */ 374 #define TEST_MODE_DISABLE 0x00000001 375 #define TX_SIZE_ADJUST1 0x00000100 376 377 /* USB_BMU_RESET */ 378 #define BMU_RESET_EP_IN 0x01 379 #define BMU_RESET_EP_OUT 0x02 380 381 /* USB_UPT_RXDMA_OWN */ 382 #define OWN_UPDATE BIT(0) 383 #define OWN_CLEAR BIT(1) 384 385 /* USB_UPS_CTRL */ 386 #define POWER_CUT 0x0100 387 388 /* USB_PM_CTRL_STATUS */ 389 #define RESUME_INDICATE 0x0001 390 391 /* USB_USB_CTRL */ 392 #define RX_AGG_DISABLE 0x0010 393 #define RX_ZERO_EN 0x0080 394 395 /* USB_U2P3_CTRL */ 396 #define U2P3_ENABLE 0x0001 397 398 /* USB_POWER_CUT */ 399 #define PWR_EN 0x0001 400 #define PHASE2_EN 0x0008 401 #define UPS_EN BIT(4) 402 #define USP_PREWAKE BIT(5) 403 404 /* USB_MISC_0 */ 405 #define PCUT_STATUS 0x0001 406 407 /* USB_RX_EARLY_TIMEOUT */ 408 #define COALESCE_SUPER 85000U 409 #define COALESCE_HIGH 250000U 410 #define COALESCE_SLOW 524280U 411 412 /* USB_WDT11_CTRL */ 413 #define TIMER11_EN 0x0001 414 415 /* USB_LPM_CTRL */ 416 /* bit 4 ~ 5: fifo empty boundary */ 417 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 418 /* bit 2 ~ 3: LMP timer */ 419 #define LPM_TIMER_MASK 0x0c 420 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 421 #define LPM_TIMER_500US 0x0c /* 500 us */ 422 #define ROK_EXIT_LPM 0x02 423 424 /* USB_AFE_CTRL2 */ 425 #define SEN_VAL_MASK 0xf800 426 #define SEN_VAL_NORMAL 0xa000 427 #define SEL_RXIDLE 0x0100 428 429 /* USB_UPS_CFG */ 430 #define SAW_CNT_1MS_MASK 0x0fff 431 432 /* USB_UPS_FLAGS */ 433 #define UPS_FLAGS_R_TUNE BIT(0) 434 #define UPS_FLAGS_EN_10M_CKDIV BIT(1) 435 #define UPS_FLAGS_250M_CKDIV BIT(2) 436 #define UPS_FLAGS_EN_ALDPS BIT(3) 437 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) 438 #define UPS_FLAGS_SPEED_MASK (0xf << 16) 439 #define ups_flags_speed(x) ((x) << 16) 440 #define UPS_FLAGS_EN_EEE BIT(20) 441 #define UPS_FLAGS_EN_500M_EEE BIT(21) 442 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22) 443 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) 444 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) 445 #define UPS_FLAGS_EN_GREEN BIT(26) 446 #define UPS_FLAGS_EN_FLOW_CTR BIT(27) 447 448 enum spd_duplex { 449 NWAY_10M_HALF = 1, 450 NWAY_10M_FULL, 451 NWAY_100M_HALF, 452 NWAY_100M_FULL, 453 NWAY_1000M_FULL, 454 FORCE_10M_HALF, 455 FORCE_10M_FULL, 456 FORCE_100M_HALF, 457 FORCE_100M_FULL, 458 }; 459 460 /* OCP_ALDPS_CONFIG */ 461 #define ENPWRSAVE 0x8000 462 #define ENPDNPS 0x0200 463 #define LINKENA 0x0100 464 #define DIS_SDSAVE 0x0010 465 466 /* OCP_PHY_STATUS */ 467 #define PHY_STAT_MASK 0x0007 468 #define PHY_STAT_EXT_INIT 2 469 #define PHY_STAT_LAN_ON 3 470 #define PHY_STAT_PWRDN 5 471 472 /* OCP_NCTL_CFG */ 473 #define PGA_RETURN_EN BIT(1) 474 475 /* OCP_POWER_CFG */ 476 #define EEE_CLKDIV_EN 0x8000 477 #define EN_ALDPS 0x0004 478 #define EN_10M_PLLOFF 0x0001 479 480 /* OCP_EEE_CONFIG1 */ 481 #define RG_TXLPI_MSK_HFDUP 0x8000 482 #define RG_MATCLR_EN 0x4000 483 #define EEE_10_CAP 0x2000 484 #define EEE_NWAY_EN 0x1000 485 #define TX_QUIET_EN 0x0200 486 #define RX_QUIET_EN 0x0100 487 #define sd_rise_time_mask 0x0070 488 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 489 #define RG_RXLPI_MSK_HFDUP 0x0008 490 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 491 492 /* OCP_EEE_CONFIG2 */ 493 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 494 #define RG_DACQUIET_EN 0x0400 495 #define RG_LDVQUIET_EN 0x0200 496 #define RG_CKRSEL 0x0020 497 #define RG_EEEPRG_EN 0x0010 498 499 /* OCP_EEE_CONFIG3 */ 500 #define fast_snr_mask 0xff80 501 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 502 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 503 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 504 505 /* OCP_EEE_AR */ 506 /* bit[15:14] function */ 507 #define FUN_ADDR 0x0000 508 #define FUN_DATA 0x4000 509 /* bit[4:0] device addr */ 510 511 /* OCP_EEE_CFG */ 512 #define CTAP_SHORT_EN 0x0040 513 #define EEE10_EN 0x0010 514 515 /* OCP_DOWN_SPEED */ 516 #define EN_EEE_CMODE BIT(14) 517 #define EN_EEE_1000 BIT(13) 518 #define EN_EEE_100 BIT(12) 519 #define EN_10M_CLKDIV BIT(11) 520 #define EN_10M_BGOFF 0x0080 521 522 /* OCP_PHY_STATE */ 523 #define TXDIS_STATE 0x01 524 #define ABD_STATE 0x02 525 526 /* OCP_PHY_PATCH_STAT */ 527 #define PATCH_READY BIT(6) 528 529 /* OCP_PHY_PATCH_CMD */ 530 #define PATCH_REQUEST BIT(4) 531 532 /* OCP_ADC_CFG */ 533 #define CKADSEL_L 0x0100 534 #define ADC_EN 0x0080 535 #define EN_EMI_L 0x0040 536 537 /* OCP_SYSCLK_CFG */ 538 #define clk_div_expo(x) (min(x, 5) << 8) 539 540 /* SRAM_GREEN_CFG */ 541 #define GREEN_ETH_EN BIT(15) 542 #define R_TUNE_EN BIT(11) 543 544 /* SRAM_LPF_CFG */ 545 #define LPF_AUTO_TUNE 0x8000 546 547 /* SRAM_10M_AMP1 */ 548 #define GDAC_IB_UPALL 0x0008 549 550 /* SRAM_10M_AMP2 */ 551 #define AMP_DN 0x0200 552 553 /* SRAM_IMPEDANCE */ 554 #define RX_DRIVING_MASK 0x6000 555 556 /* MAC PASSTHRU */ 557 #define AD_MASK 0xfee0 558 #define EFUSE 0xcfdb 559 #define PASS_THRU_MASK 0x1 560 561 enum rtl_register_content { 562 _1000bps = 0x10, 563 _100bps = 0x08, 564 _10bps = 0x04, 565 LINK_STATUS = 0x02, 566 FULL_DUP = 0x01, 567 }; 568 569 #define RTL8152_MAX_TX 4 570 #define RTL8152_MAX_RX 10 571 #define INTBUFSIZE 2 572 #define TX_ALIGN 4 573 #define RX_ALIGN 8 574 575 #define INTR_LINK 0x0004 576 577 #define RTL8152_REQT_READ 0xc0 578 #define RTL8152_REQT_WRITE 0x40 579 #define RTL8152_REQ_GET_REGS 0x05 580 #define RTL8152_REQ_SET_REGS 0x05 581 582 #define BYTE_EN_DWORD 0xff 583 #define BYTE_EN_WORD 0x33 584 #define BYTE_EN_BYTE 0x11 585 #define BYTE_EN_SIX_BYTES 0x3f 586 #define BYTE_EN_START_MASK 0x0f 587 #define BYTE_EN_END_MASK 0xf0 588 589 #define RTL8153_MAX_PACKET 9216 /* 9K */ 590 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \ 591 ETH_FCS_LEN) 592 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 593 #define RTL8153_RMS RTL8153_MAX_PACKET 594 #define RTL8152_TX_TIMEOUT (5 * HZ) 595 #define RTL8152_NAPI_WEIGHT 64 596 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \ 597 sizeof(struct rx_desc) + RX_ALIGN) 598 599 /* rtl8152 flags */ 600 enum rtl8152_flags { 601 RTL8152_UNPLUG = 0, 602 RTL8152_SET_RX_MODE, 603 WORK_ENABLE, 604 RTL8152_LINK_CHG, 605 SELECTIVE_SUSPEND, 606 PHY_RESET, 607 SCHEDULE_NAPI, 608 GREEN_ETHERNET, 609 DELL_TB_RX_AGG_BUG, 610 }; 611 612 /* Define these values to match your device */ 613 #define VENDOR_ID_REALTEK 0x0bda 614 #define VENDOR_ID_MICROSOFT 0x045e 615 #define VENDOR_ID_SAMSUNG 0x04e8 616 #define VENDOR_ID_LENOVO 0x17ef 617 #define VENDOR_ID_LINKSYS 0x13b1 618 #define VENDOR_ID_NVIDIA 0x0955 619 #define VENDOR_ID_TPLINK 0x2357 620 621 #define MCU_TYPE_PLA 0x0100 622 #define MCU_TYPE_USB 0x0000 623 624 struct tally_counter { 625 __le64 tx_packets; 626 __le64 rx_packets; 627 __le64 tx_errors; 628 __le32 rx_errors; 629 __le16 rx_missed; 630 __le16 align_errors; 631 __le32 tx_one_collision; 632 __le32 tx_multi_collision; 633 __le64 rx_unicast; 634 __le64 rx_broadcast; 635 __le32 rx_multicast; 636 __le16 tx_aborted; 637 __le16 tx_underrun; 638 }; 639 640 struct rx_desc { 641 __le32 opts1; 642 #define RX_LEN_MASK 0x7fff 643 644 __le32 opts2; 645 #define RD_UDP_CS BIT(23) 646 #define RD_TCP_CS BIT(22) 647 #define RD_IPV6_CS BIT(20) 648 #define RD_IPV4_CS BIT(19) 649 650 __le32 opts3; 651 #define IPF BIT(23) /* IP checksum fail */ 652 #define UDPF BIT(22) /* UDP checksum fail */ 653 #define TCPF BIT(21) /* TCP checksum fail */ 654 #define RX_VLAN_TAG BIT(16) 655 656 __le32 opts4; 657 __le32 opts5; 658 __le32 opts6; 659 }; 660 661 struct tx_desc { 662 __le32 opts1; 663 #define TX_FS BIT(31) /* First segment of a packet */ 664 #define TX_LS BIT(30) /* Final segment of a packet */ 665 #define GTSENDV4 BIT(28) 666 #define GTSENDV6 BIT(27) 667 #define GTTCPHO_SHIFT 18 668 #define GTTCPHO_MAX 0x7fU 669 #define TX_LEN_MAX 0x3ffffU 670 671 __le32 opts2; 672 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 673 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 674 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 675 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 676 #define MSS_SHIFT 17 677 #define MSS_MAX 0x7ffU 678 #define TCPHO_SHIFT 17 679 #define TCPHO_MAX 0x7ffU 680 #define TX_VLAN_TAG BIT(16) 681 }; 682 683 struct r8152; 684 685 struct rx_agg { 686 struct list_head list; 687 struct urb *urb; 688 struct r8152 *context; 689 void *buffer; 690 void *head; 691 }; 692 693 struct tx_agg { 694 struct list_head list; 695 struct urb *urb; 696 struct r8152 *context; 697 void *buffer; 698 void *head; 699 u32 skb_num; 700 u32 skb_len; 701 }; 702 703 struct r8152 { 704 unsigned long flags; 705 struct usb_device *udev; 706 struct napi_struct napi; 707 struct usb_interface *intf; 708 struct net_device *netdev; 709 struct urb *intr_urb; 710 struct tx_agg tx_info[RTL8152_MAX_TX]; 711 struct rx_agg rx_info[RTL8152_MAX_RX]; 712 struct list_head rx_done, tx_free; 713 struct sk_buff_head tx_queue, rx_queue; 714 spinlock_t rx_lock, tx_lock; 715 struct delayed_work schedule, hw_phy_work; 716 struct mii_if_info mii; 717 struct mutex control; /* use for hw setting */ 718 #ifdef CONFIG_PM_SLEEP 719 struct notifier_block pm_notifier; 720 #endif 721 722 struct rtl_ops { 723 void (*init)(struct r8152 *); 724 int (*enable)(struct r8152 *); 725 void (*disable)(struct r8152 *); 726 void (*up)(struct r8152 *); 727 void (*down)(struct r8152 *); 728 void (*unload)(struct r8152 *); 729 int (*eee_get)(struct r8152 *, struct ethtool_eee *); 730 int (*eee_set)(struct r8152 *, struct ethtool_eee *); 731 bool (*in_nway)(struct r8152 *); 732 void (*hw_phy_cfg)(struct r8152 *); 733 void (*autosuspend_en)(struct r8152 *tp, bool enable); 734 } rtl_ops; 735 736 int intr_interval; 737 u32 saved_wolopts; 738 u32 msg_enable; 739 u32 tx_qlen; 740 u32 coalesce; 741 u16 ocp_base; 742 u16 speed; 743 u8 *intr_buff; 744 u8 version; 745 u8 duplex; 746 u8 autoneg; 747 }; 748 749 enum rtl_version { 750 RTL_VER_UNKNOWN = 0, 751 RTL_VER_01, 752 RTL_VER_02, 753 RTL_VER_03, 754 RTL_VER_04, 755 RTL_VER_05, 756 RTL_VER_06, 757 RTL_VER_07, 758 RTL_VER_08, 759 RTL_VER_09, 760 RTL_VER_MAX 761 }; 762 763 enum tx_csum_stat { 764 TX_CSUM_SUCCESS = 0, 765 TX_CSUM_TSO, 766 TX_CSUM_NONE 767 }; 768 769 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 770 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 771 */ 772 static const int multicast_filter_limit = 32; 773 static unsigned int agg_buf_sz = 16384; 774 775 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ 776 VLAN_ETH_HLEN - ETH_FCS_LEN) 777 778 static 779 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 780 { 781 int ret; 782 void *tmp; 783 784 tmp = kmalloc(size, GFP_KERNEL); 785 if (!tmp) 786 return -ENOMEM; 787 788 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 789 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 790 value, index, tmp, size, 500); 791 792 memcpy(data, tmp, size); 793 kfree(tmp); 794 795 return ret; 796 } 797 798 static 799 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 800 { 801 int ret; 802 void *tmp; 803 804 tmp = kmemdup(data, size, GFP_KERNEL); 805 if (!tmp) 806 return -ENOMEM; 807 808 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 809 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 810 value, index, tmp, size, 500); 811 812 kfree(tmp); 813 814 return ret; 815 } 816 817 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 818 void *data, u16 type) 819 { 820 u16 limit = 64; 821 int ret = 0; 822 823 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 824 return -ENODEV; 825 826 /* both size and indix must be 4 bytes align */ 827 if ((size & 3) || !size || (index & 3) || !data) 828 return -EPERM; 829 830 if ((u32)index + (u32)size > 0xffff) 831 return -EPERM; 832 833 while (size) { 834 if (size > limit) { 835 ret = get_registers(tp, index, type, limit, data); 836 if (ret < 0) 837 break; 838 839 index += limit; 840 data += limit; 841 size -= limit; 842 } else { 843 ret = get_registers(tp, index, type, size, data); 844 if (ret < 0) 845 break; 846 847 index += size; 848 data += size; 849 size = 0; 850 break; 851 } 852 } 853 854 if (ret == -ENODEV) 855 set_bit(RTL8152_UNPLUG, &tp->flags); 856 857 return ret; 858 } 859 860 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 861 u16 size, void *data, u16 type) 862 { 863 int ret; 864 u16 byteen_start, byteen_end, byen; 865 u16 limit = 512; 866 867 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 868 return -ENODEV; 869 870 /* both size and indix must be 4 bytes align */ 871 if ((size & 3) || !size || (index & 3) || !data) 872 return -EPERM; 873 874 if ((u32)index + (u32)size > 0xffff) 875 return -EPERM; 876 877 byteen_start = byteen & BYTE_EN_START_MASK; 878 byteen_end = byteen & BYTE_EN_END_MASK; 879 880 byen = byteen_start | (byteen_start << 4); 881 ret = set_registers(tp, index, type | byen, 4, data); 882 if (ret < 0) 883 goto error1; 884 885 index += 4; 886 data += 4; 887 size -= 4; 888 889 if (size) { 890 size -= 4; 891 892 while (size) { 893 if (size > limit) { 894 ret = set_registers(tp, index, 895 type | BYTE_EN_DWORD, 896 limit, data); 897 if (ret < 0) 898 goto error1; 899 900 index += limit; 901 data += limit; 902 size -= limit; 903 } else { 904 ret = set_registers(tp, index, 905 type | BYTE_EN_DWORD, 906 size, data); 907 if (ret < 0) 908 goto error1; 909 910 index += size; 911 data += size; 912 size = 0; 913 break; 914 } 915 } 916 917 byen = byteen_end | (byteen_end >> 4); 918 ret = set_registers(tp, index, type | byen, 4, data); 919 if (ret < 0) 920 goto error1; 921 } 922 923 error1: 924 if (ret == -ENODEV) 925 set_bit(RTL8152_UNPLUG, &tp->flags); 926 927 return ret; 928 } 929 930 static inline 931 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 932 { 933 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 934 } 935 936 static inline 937 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 938 { 939 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 940 } 941 942 static inline 943 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 944 { 945 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 946 } 947 948 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 949 { 950 __le32 data; 951 952 generic_ocp_read(tp, index, sizeof(data), &data, type); 953 954 return __le32_to_cpu(data); 955 } 956 957 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 958 { 959 __le32 tmp = __cpu_to_le32(data); 960 961 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 962 } 963 964 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 965 { 966 u32 data; 967 __le32 tmp; 968 u16 byen = BYTE_EN_WORD; 969 u8 shift = index & 2; 970 971 index &= ~3; 972 byen <<= shift; 973 974 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen); 975 976 data = __le32_to_cpu(tmp); 977 data >>= (shift * 8); 978 data &= 0xffff; 979 980 return (u16)data; 981 } 982 983 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 984 { 985 u32 mask = 0xffff; 986 __le32 tmp; 987 u16 byen = BYTE_EN_WORD; 988 u8 shift = index & 2; 989 990 data &= mask; 991 992 if (index & 2) { 993 byen <<= shift; 994 mask <<= (shift * 8); 995 data <<= (shift * 8); 996 index &= ~3; 997 } 998 999 tmp = __cpu_to_le32(data); 1000 1001 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1002 } 1003 1004 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 1005 { 1006 u32 data; 1007 __le32 tmp; 1008 u8 shift = index & 3; 1009 1010 index &= ~3; 1011 1012 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 1013 1014 data = __le32_to_cpu(tmp); 1015 data >>= (shift * 8); 1016 data &= 0xff; 1017 1018 return (u8)data; 1019 } 1020 1021 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 1022 { 1023 u32 mask = 0xff; 1024 __le32 tmp; 1025 u16 byen = BYTE_EN_BYTE; 1026 u8 shift = index & 3; 1027 1028 data &= mask; 1029 1030 if (index & 3) { 1031 byen <<= shift; 1032 mask <<= (shift * 8); 1033 data <<= (shift * 8); 1034 index &= ~3; 1035 } 1036 1037 tmp = __cpu_to_le32(data); 1038 1039 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1040 } 1041 1042 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 1043 { 1044 u16 ocp_base, ocp_index; 1045 1046 ocp_base = addr & 0xf000; 1047 if (ocp_base != tp->ocp_base) { 1048 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1049 tp->ocp_base = ocp_base; 1050 } 1051 1052 ocp_index = (addr & 0x0fff) | 0xb000; 1053 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 1054 } 1055 1056 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 1057 { 1058 u16 ocp_base, ocp_index; 1059 1060 ocp_base = addr & 0xf000; 1061 if (ocp_base != tp->ocp_base) { 1062 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1063 tp->ocp_base = ocp_base; 1064 } 1065 1066 ocp_index = (addr & 0x0fff) | 0xb000; 1067 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 1068 } 1069 1070 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 1071 { 1072 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 1073 } 1074 1075 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 1076 { 1077 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 1078 } 1079 1080 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 1081 { 1082 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1083 ocp_reg_write(tp, OCP_SRAM_DATA, data); 1084 } 1085 1086 static u16 sram_read(struct r8152 *tp, u16 addr) 1087 { 1088 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1089 return ocp_reg_read(tp, OCP_SRAM_DATA); 1090 } 1091 1092 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 1093 { 1094 struct r8152 *tp = netdev_priv(netdev); 1095 int ret; 1096 1097 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1098 return -ENODEV; 1099 1100 if (phy_id != R8152_PHY_ID) 1101 return -EINVAL; 1102 1103 ret = r8152_mdio_read(tp, reg); 1104 1105 return ret; 1106 } 1107 1108 static 1109 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 1110 { 1111 struct r8152 *tp = netdev_priv(netdev); 1112 1113 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1114 return; 1115 1116 if (phy_id != R8152_PHY_ID) 1117 return; 1118 1119 r8152_mdio_write(tp, reg, val); 1120 } 1121 1122 static int 1123 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 1124 1125 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1126 { 1127 struct r8152 *tp = netdev_priv(netdev); 1128 struct sockaddr *addr = p; 1129 int ret = -EADDRNOTAVAIL; 1130 1131 if (!is_valid_ether_addr(addr->sa_data)) 1132 goto out1; 1133 1134 ret = usb_autopm_get_interface(tp->intf); 1135 if (ret < 0) 1136 goto out1; 1137 1138 mutex_lock(&tp->control); 1139 1140 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1141 1142 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1143 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1144 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1145 1146 mutex_unlock(&tp->control); 1147 1148 usb_autopm_put_interface(tp->intf); 1149 out1: 1150 return ret; 1151 } 1152 1153 /* Devices containing RTL8153-AD can support a persistent 1154 * host system provided MAC address. 1155 * Examples of this are Dell TB15 and Dell WD15 docks 1156 */ 1157 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) 1158 { 1159 acpi_status status; 1160 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1161 union acpi_object *obj; 1162 int ret = -EINVAL; 1163 u32 ocp_data; 1164 unsigned char buf[6]; 1165 1166 /* test for -AD variant of RTL8153 */ 1167 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 1168 if ((ocp_data & AD_MASK) != 0x1000) 1169 return -ENODEV; 1170 1171 /* test for MAC address pass-through bit */ 1172 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); 1173 if ((ocp_data & PASS_THRU_MASK) != 1) 1174 return -ENODEV; 1175 1176 /* returns _AUXMAC_#AABBCCDDEEFF# */ 1177 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer); 1178 obj = (union acpi_object *)buffer.pointer; 1179 if (!ACPI_SUCCESS(status)) 1180 return -ENODEV; 1181 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) { 1182 netif_warn(tp, probe, tp->netdev, 1183 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", 1184 obj->type, obj->string.length); 1185 goto amacout; 1186 } 1187 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || 1188 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { 1189 netif_warn(tp, probe, tp->netdev, 1190 "Invalid header when reading pass-thru MAC addr\n"); 1191 goto amacout; 1192 } 1193 ret = hex2bin(buf, obj->string.pointer + 9, 6); 1194 if (!(ret == 0 && is_valid_ether_addr(buf))) { 1195 netif_warn(tp, probe, tp->netdev, 1196 "Invalid MAC for pass-thru MAC addr: %d, %pM\n", 1197 ret, buf); 1198 ret = -EINVAL; 1199 goto amacout; 1200 } 1201 memcpy(sa->sa_data, buf, 6); 1202 ether_addr_copy(tp->netdev->dev_addr, sa->sa_data); 1203 netif_info(tp, probe, tp->netdev, 1204 "Using pass-thru MAC addr %pM\n", sa->sa_data); 1205 1206 amacout: 1207 kfree(obj); 1208 return ret; 1209 } 1210 1211 static int set_ethernet_addr(struct r8152 *tp) 1212 { 1213 struct net_device *dev = tp->netdev; 1214 struct sockaddr sa; 1215 int ret; 1216 1217 if (tp->version == RTL_VER_01) { 1218 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); 1219 } else { 1220 /* if this is not an RTL8153-AD, no eFuse mac pass thru set, 1221 * or system doesn't provide valid _SB.AMAC this will be 1222 * be expected to non-zero 1223 */ 1224 ret = vendor_mac_passthru_addr_read(tp, &sa); 1225 if (ret < 0) 1226 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); 1227 } 1228 1229 if (ret < 0) { 1230 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1231 } else if (!is_valid_ether_addr(sa.sa_data)) { 1232 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1233 sa.sa_data); 1234 eth_hw_addr_random(dev); 1235 ether_addr_copy(sa.sa_data, dev->dev_addr); 1236 ret = rtl8152_set_mac_address(dev, &sa); 1237 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1238 sa.sa_data); 1239 } else { 1240 if (tp->version == RTL_VER_01) 1241 ether_addr_copy(dev->dev_addr, sa.sa_data); 1242 else 1243 ret = rtl8152_set_mac_address(dev, &sa); 1244 } 1245 1246 return ret; 1247 } 1248 1249 static void read_bulk_callback(struct urb *urb) 1250 { 1251 struct net_device *netdev; 1252 int status = urb->status; 1253 struct rx_agg *agg; 1254 struct r8152 *tp; 1255 unsigned long flags; 1256 1257 agg = urb->context; 1258 if (!agg) 1259 return; 1260 1261 tp = agg->context; 1262 if (!tp) 1263 return; 1264 1265 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1266 return; 1267 1268 if (!test_bit(WORK_ENABLE, &tp->flags)) 1269 return; 1270 1271 netdev = tp->netdev; 1272 1273 /* When link down, the driver would cancel all bulks. */ 1274 /* This avoid the re-submitting bulk */ 1275 if (!netif_carrier_ok(netdev)) 1276 return; 1277 1278 usb_mark_last_busy(tp->udev); 1279 1280 switch (status) { 1281 case 0: 1282 if (urb->actual_length < ETH_ZLEN) 1283 break; 1284 1285 spin_lock_irqsave(&tp->rx_lock, flags); 1286 list_add_tail(&agg->list, &tp->rx_done); 1287 spin_unlock_irqrestore(&tp->rx_lock, flags); 1288 napi_schedule(&tp->napi); 1289 return; 1290 case -ESHUTDOWN: 1291 set_bit(RTL8152_UNPLUG, &tp->flags); 1292 netif_device_detach(tp->netdev); 1293 return; 1294 case -ENOENT: 1295 return; /* the urb is in unlink state */ 1296 case -ETIME: 1297 if (net_ratelimit()) 1298 netdev_warn(netdev, "maybe reset is needed?\n"); 1299 break; 1300 default: 1301 if (net_ratelimit()) 1302 netdev_warn(netdev, "Rx status %d\n", status); 1303 break; 1304 } 1305 1306 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1307 } 1308 1309 static void write_bulk_callback(struct urb *urb) 1310 { 1311 struct net_device_stats *stats; 1312 struct net_device *netdev; 1313 struct tx_agg *agg; 1314 struct r8152 *tp; 1315 unsigned long flags; 1316 int status = urb->status; 1317 1318 agg = urb->context; 1319 if (!agg) 1320 return; 1321 1322 tp = agg->context; 1323 if (!tp) 1324 return; 1325 1326 netdev = tp->netdev; 1327 stats = &netdev->stats; 1328 if (status) { 1329 if (net_ratelimit()) 1330 netdev_warn(netdev, "Tx status %d\n", status); 1331 stats->tx_errors += agg->skb_num; 1332 } else { 1333 stats->tx_packets += agg->skb_num; 1334 stats->tx_bytes += agg->skb_len; 1335 } 1336 1337 spin_lock_irqsave(&tp->tx_lock, flags); 1338 list_add_tail(&agg->list, &tp->tx_free); 1339 spin_unlock_irqrestore(&tp->tx_lock, flags); 1340 1341 usb_autopm_put_interface_async(tp->intf); 1342 1343 if (!netif_carrier_ok(netdev)) 1344 return; 1345 1346 if (!test_bit(WORK_ENABLE, &tp->flags)) 1347 return; 1348 1349 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1350 return; 1351 1352 if (!skb_queue_empty(&tp->tx_queue)) 1353 napi_schedule(&tp->napi); 1354 } 1355 1356 static void intr_callback(struct urb *urb) 1357 { 1358 struct r8152 *tp; 1359 __le16 *d; 1360 int status = urb->status; 1361 int res; 1362 1363 tp = urb->context; 1364 if (!tp) 1365 return; 1366 1367 if (!test_bit(WORK_ENABLE, &tp->flags)) 1368 return; 1369 1370 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1371 return; 1372 1373 switch (status) { 1374 case 0: /* success */ 1375 break; 1376 case -ECONNRESET: /* unlink */ 1377 case -ESHUTDOWN: 1378 netif_device_detach(tp->netdev); 1379 /* fall through */ 1380 case -ENOENT: 1381 case -EPROTO: 1382 netif_info(tp, intr, tp->netdev, 1383 "Stop submitting intr, status %d\n", status); 1384 return; 1385 case -EOVERFLOW: 1386 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1387 goto resubmit; 1388 /* -EPIPE: should clear the halt */ 1389 default: 1390 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1391 goto resubmit; 1392 } 1393 1394 d = urb->transfer_buffer; 1395 if (INTR_LINK & __le16_to_cpu(d[0])) { 1396 if (!netif_carrier_ok(tp->netdev)) { 1397 set_bit(RTL8152_LINK_CHG, &tp->flags); 1398 schedule_delayed_work(&tp->schedule, 0); 1399 } 1400 } else { 1401 if (netif_carrier_ok(tp->netdev)) { 1402 netif_stop_queue(tp->netdev); 1403 set_bit(RTL8152_LINK_CHG, &tp->flags); 1404 schedule_delayed_work(&tp->schedule, 0); 1405 } 1406 } 1407 1408 resubmit: 1409 res = usb_submit_urb(urb, GFP_ATOMIC); 1410 if (res == -ENODEV) { 1411 set_bit(RTL8152_UNPLUG, &tp->flags); 1412 netif_device_detach(tp->netdev); 1413 } else if (res) { 1414 netif_err(tp, intr, tp->netdev, 1415 "can't resubmit intr, status %d\n", res); 1416 } 1417 } 1418 1419 static inline void *rx_agg_align(void *data) 1420 { 1421 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1422 } 1423 1424 static inline void *tx_agg_align(void *data) 1425 { 1426 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1427 } 1428 1429 static void free_all_mem(struct r8152 *tp) 1430 { 1431 int i; 1432 1433 for (i = 0; i < RTL8152_MAX_RX; i++) { 1434 usb_free_urb(tp->rx_info[i].urb); 1435 tp->rx_info[i].urb = NULL; 1436 1437 kfree(tp->rx_info[i].buffer); 1438 tp->rx_info[i].buffer = NULL; 1439 tp->rx_info[i].head = NULL; 1440 } 1441 1442 for (i = 0; i < RTL8152_MAX_TX; i++) { 1443 usb_free_urb(tp->tx_info[i].urb); 1444 tp->tx_info[i].urb = NULL; 1445 1446 kfree(tp->tx_info[i].buffer); 1447 tp->tx_info[i].buffer = NULL; 1448 tp->tx_info[i].head = NULL; 1449 } 1450 1451 usb_free_urb(tp->intr_urb); 1452 tp->intr_urb = NULL; 1453 1454 kfree(tp->intr_buff); 1455 tp->intr_buff = NULL; 1456 } 1457 1458 static int alloc_all_mem(struct r8152 *tp) 1459 { 1460 struct net_device *netdev = tp->netdev; 1461 struct usb_interface *intf = tp->intf; 1462 struct usb_host_interface *alt = intf->cur_altsetting; 1463 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1464 struct urb *urb; 1465 int node, i; 1466 u8 *buf; 1467 1468 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1469 1470 spin_lock_init(&tp->rx_lock); 1471 spin_lock_init(&tp->tx_lock); 1472 INIT_LIST_HEAD(&tp->tx_free); 1473 INIT_LIST_HEAD(&tp->rx_done); 1474 skb_queue_head_init(&tp->tx_queue); 1475 skb_queue_head_init(&tp->rx_queue); 1476 1477 for (i = 0; i < RTL8152_MAX_RX; i++) { 1478 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1479 if (!buf) 1480 goto err1; 1481 1482 if (buf != rx_agg_align(buf)) { 1483 kfree(buf); 1484 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, 1485 node); 1486 if (!buf) 1487 goto err1; 1488 } 1489 1490 urb = usb_alloc_urb(0, GFP_KERNEL); 1491 if (!urb) { 1492 kfree(buf); 1493 goto err1; 1494 } 1495 1496 INIT_LIST_HEAD(&tp->rx_info[i].list); 1497 tp->rx_info[i].context = tp; 1498 tp->rx_info[i].urb = urb; 1499 tp->rx_info[i].buffer = buf; 1500 tp->rx_info[i].head = rx_agg_align(buf); 1501 } 1502 1503 for (i = 0; i < RTL8152_MAX_TX; i++) { 1504 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1505 if (!buf) 1506 goto err1; 1507 1508 if (buf != tx_agg_align(buf)) { 1509 kfree(buf); 1510 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 1511 node); 1512 if (!buf) 1513 goto err1; 1514 } 1515 1516 urb = usb_alloc_urb(0, GFP_KERNEL); 1517 if (!urb) { 1518 kfree(buf); 1519 goto err1; 1520 } 1521 1522 INIT_LIST_HEAD(&tp->tx_info[i].list); 1523 tp->tx_info[i].context = tp; 1524 tp->tx_info[i].urb = urb; 1525 tp->tx_info[i].buffer = buf; 1526 tp->tx_info[i].head = tx_agg_align(buf); 1527 1528 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1529 } 1530 1531 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1532 if (!tp->intr_urb) 1533 goto err1; 1534 1535 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1536 if (!tp->intr_buff) 1537 goto err1; 1538 1539 tp->intr_interval = (int)ep_intr->desc.bInterval; 1540 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1541 tp->intr_buff, INTBUFSIZE, intr_callback, 1542 tp, tp->intr_interval); 1543 1544 return 0; 1545 1546 err1: 1547 free_all_mem(tp); 1548 return -ENOMEM; 1549 } 1550 1551 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1552 { 1553 struct tx_agg *agg = NULL; 1554 unsigned long flags; 1555 1556 if (list_empty(&tp->tx_free)) 1557 return NULL; 1558 1559 spin_lock_irqsave(&tp->tx_lock, flags); 1560 if (!list_empty(&tp->tx_free)) { 1561 struct list_head *cursor; 1562 1563 cursor = tp->tx_free.next; 1564 list_del_init(cursor); 1565 agg = list_entry(cursor, struct tx_agg, list); 1566 } 1567 spin_unlock_irqrestore(&tp->tx_lock, flags); 1568 1569 return agg; 1570 } 1571 1572 /* r8152_csum_workaround() 1573 * The hw limites the value the transport offset. When the offset is out of the 1574 * range, calculate the checksum by sw. 1575 */ 1576 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1577 struct sk_buff_head *list) 1578 { 1579 if (skb_shinfo(skb)->gso_size) { 1580 netdev_features_t features = tp->netdev->features; 1581 struct sk_buff_head seg_list; 1582 struct sk_buff *segs, *nskb; 1583 1584 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 1585 segs = skb_gso_segment(skb, features); 1586 if (IS_ERR(segs) || !segs) 1587 goto drop; 1588 1589 __skb_queue_head_init(&seg_list); 1590 1591 do { 1592 nskb = segs; 1593 segs = segs->next; 1594 nskb->next = NULL; 1595 __skb_queue_tail(&seg_list, nskb); 1596 } while (segs); 1597 1598 skb_queue_splice(&seg_list, list); 1599 dev_kfree_skb(skb); 1600 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1601 if (skb_checksum_help(skb) < 0) 1602 goto drop; 1603 1604 __skb_queue_head(list, skb); 1605 } else { 1606 struct net_device_stats *stats; 1607 1608 drop: 1609 stats = &tp->netdev->stats; 1610 stats->tx_dropped++; 1611 dev_kfree_skb(skb); 1612 } 1613 } 1614 1615 /* msdn_giant_send_check() 1616 * According to the document of microsoft, the TCP Pseudo Header excludes the 1617 * packet length for IPv6 TCP large packets. 1618 */ 1619 static int msdn_giant_send_check(struct sk_buff *skb) 1620 { 1621 const struct ipv6hdr *ipv6h; 1622 struct tcphdr *th; 1623 int ret; 1624 1625 ret = skb_cow_head(skb, 0); 1626 if (ret) 1627 return ret; 1628 1629 ipv6h = ipv6_hdr(skb); 1630 th = tcp_hdr(skb); 1631 1632 th->check = 0; 1633 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1634 1635 return ret; 1636 } 1637 1638 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 1639 { 1640 if (skb_vlan_tag_present(skb)) { 1641 u32 opts2; 1642 1643 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); 1644 desc->opts2 |= cpu_to_le32(opts2); 1645 } 1646 } 1647 1648 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 1649 { 1650 u32 opts2 = le32_to_cpu(desc->opts2); 1651 1652 if (opts2 & RX_VLAN_TAG) 1653 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1654 swab16(opts2 & 0xffff)); 1655 } 1656 1657 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1658 struct sk_buff *skb, u32 len, u32 transport_offset) 1659 { 1660 u32 mss = skb_shinfo(skb)->gso_size; 1661 u32 opts1, opts2 = 0; 1662 int ret = TX_CSUM_SUCCESS; 1663 1664 WARN_ON_ONCE(len > TX_LEN_MAX); 1665 1666 opts1 = len | TX_FS | TX_LS; 1667 1668 if (mss) { 1669 if (transport_offset > GTTCPHO_MAX) { 1670 netif_warn(tp, tx_err, tp->netdev, 1671 "Invalid transport offset 0x%x for TSO\n", 1672 transport_offset); 1673 ret = TX_CSUM_TSO; 1674 goto unavailable; 1675 } 1676 1677 switch (vlan_get_protocol(skb)) { 1678 case htons(ETH_P_IP): 1679 opts1 |= GTSENDV4; 1680 break; 1681 1682 case htons(ETH_P_IPV6): 1683 if (msdn_giant_send_check(skb)) { 1684 ret = TX_CSUM_TSO; 1685 goto unavailable; 1686 } 1687 opts1 |= GTSENDV6; 1688 break; 1689 1690 default: 1691 WARN_ON_ONCE(1); 1692 break; 1693 } 1694 1695 opts1 |= transport_offset << GTTCPHO_SHIFT; 1696 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1697 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1698 u8 ip_protocol; 1699 1700 if (transport_offset > TCPHO_MAX) { 1701 netif_warn(tp, tx_err, tp->netdev, 1702 "Invalid transport offset 0x%x\n", 1703 transport_offset); 1704 ret = TX_CSUM_NONE; 1705 goto unavailable; 1706 } 1707 1708 switch (vlan_get_protocol(skb)) { 1709 case htons(ETH_P_IP): 1710 opts2 |= IPV4_CS; 1711 ip_protocol = ip_hdr(skb)->protocol; 1712 break; 1713 1714 case htons(ETH_P_IPV6): 1715 opts2 |= IPV6_CS; 1716 ip_protocol = ipv6_hdr(skb)->nexthdr; 1717 break; 1718 1719 default: 1720 ip_protocol = IPPROTO_RAW; 1721 break; 1722 } 1723 1724 if (ip_protocol == IPPROTO_TCP) 1725 opts2 |= TCP_CS; 1726 else if (ip_protocol == IPPROTO_UDP) 1727 opts2 |= UDP_CS; 1728 else 1729 WARN_ON_ONCE(1); 1730 1731 opts2 |= transport_offset << TCPHO_SHIFT; 1732 } 1733 1734 desc->opts2 = cpu_to_le32(opts2); 1735 desc->opts1 = cpu_to_le32(opts1); 1736 1737 unavailable: 1738 return ret; 1739 } 1740 1741 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1742 { 1743 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1744 int remain, ret; 1745 u8 *tx_data; 1746 1747 __skb_queue_head_init(&skb_head); 1748 spin_lock(&tx_queue->lock); 1749 skb_queue_splice_init(tx_queue, &skb_head); 1750 spin_unlock(&tx_queue->lock); 1751 1752 tx_data = agg->head; 1753 agg->skb_num = 0; 1754 agg->skb_len = 0; 1755 remain = agg_buf_sz; 1756 1757 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1758 struct tx_desc *tx_desc; 1759 struct sk_buff *skb; 1760 unsigned int len; 1761 u32 offset; 1762 1763 skb = __skb_dequeue(&skb_head); 1764 if (!skb) 1765 break; 1766 1767 len = skb->len + sizeof(*tx_desc); 1768 1769 if (len > remain) { 1770 __skb_queue_head(&skb_head, skb); 1771 break; 1772 } 1773 1774 tx_data = tx_agg_align(tx_data); 1775 tx_desc = (struct tx_desc *)tx_data; 1776 1777 offset = (u32)skb_transport_offset(skb); 1778 1779 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1780 r8152_csum_workaround(tp, skb, &skb_head); 1781 continue; 1782 } 1783 1784 rtl_tx_vlan_tag(tx_desc, skb); 1785 1786 tx_data += sizeof(*tx_desc); 1787 1788 len = skb->len; 1789 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1790 struct net_device_stats *stats = &tp->netdev->stats; 1791 1792 stats->tx_dropped++; 1793 dev_kfree_skb_any(skb); 1794 tx_data -= sizeof(*tx_desc); 1795 continue; 1796 } 1797 1798 tx_data += len; 1799 agg->skb_len += len; 1800 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1; 1801 1802 dev_kfree_skb_any(skb); 1803 1804 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1805 1806 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags)) 1807 break; 1808 } 1809 1810 if (!skb_queue_empty(&skb_head)) { 1811 spin_lock(&tx_queue->lock); 1812 skb_queue_splice(&skb_head, tx_queue); 1813 spin_unlock(&tx_queue->lock); 1814 } 1815 1816 netif_tx_lock(tp->netdev); 1817 1818 if (netif_queue_stopped(tp->netdev) && 1819 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1820 netif_wake_queue(tp->netdev); 1821 1822 netif_tx_unlock(tp->netdev); 1823 1824 ret = usb_autopm_get_interface_async(tp->intf); 1825 if (ret < 0) 1826 goto out_tx_fill; 1827 1828 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1829 agg->head, (int)(tx_data - (u8 *)agg->head), 1830 (usb_complete_t)write_bulk_callback, agg); 1831 1832 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1833 if (ret < 0) 1834 usb_autopm_put_interface_async(tp->intf); 1835 1836 out_tx_fill: 1837 return ret; 1838 } 1839 1840 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1841 { 1842 u8 checksum = CHECKSUM_NONE; 1843 u32 opts2, opts3; 1844 1845 if (!(tp->netdev->features & NETIF_F_RXCSUM)) 1846 goto return_result; 1847 1848 opts2 = le32_to_cpu(rx_desc->opts2); 1849 opts3 = le32_to_cpu(rx_desc->opts3); 1850 1851 if (opts2 & RD_IPV4_CS) { 1852 if (opts3 & IPF) 1853 checksum = CHECKSUM_NONE; 1854 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1855 checksum = CHECKSUM_UNNECESSARY; 1856 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1857 checksum = CHECKSUM_UNNECESSARY; 1858 } else if (opts2 & RD_IPV6_CS) { 1859 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1860 checksum = CHECKSUM_UNNECESSARY; 1861 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1862 checksum = CHECKSUM_UNNECESSARY; 1863 } 1864 1865 return_result: 1866 return checksum; 1867 } 1868 1869 static int rx_bottom(struct r8152 *tp, int budget) 1870 { 1871 unsigned long flags; 1872 struct list_head *cursor, *next, rx_queue; 1873 int ret = 0, work_done = 0; 1874 struct napi_struct *napi = &tp->napi; 1875 1876 if (!skb_queue_empty(&tp->rx_queue)) { 1877 while (work_done < budget) { 1878 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); 1879 struct net_device *netdev = tp->netdev; 1880 struct net_device_stats *stats = &netdev->stats; 1881 unsigned int pkt_len; 1882 1883 if (!skb) 1884 break; 1885 1886 pkt_len = skb->len; 1887 napi_gro_receive(napi, skb); 1888 work_done++; 1889 stats->rx_packets++; 1890 stats->rx_bytes += pkt_len; 1891 } 1892 } 1893 1894 if (list_empty(&tp->rx_done)) 1895 goto out1; 1896 1897 INIT_LIST_HEAD(&rx_queue); 1898 spin_lock_irqsave(&tp->rx_lock, flags); 1899 list_splice_init(&tp->rx_done, &rx_queue); 1900 spin_unlock_irqrestore(&tp->rx_lock, flags); 1901 1902 list_for_each_safe(cursor, next, &rx_queue) { 1903 struct rx_desc *rx_desc; 1904 struct rx_agg *agg; 1905 int len_used = 0; 1906 struct urb *urb; 1907 u8 *rx_data; 1908 1909 list_del_init(cursor); 1910 1911 agg = list_entry(cursor, struct rx_agg, list); 1912 urb = agg->urb; 1913 if (urb->actual_length < ETH_ZLEN) 1914 goto submit; 1915 1916 rx_desc = agg->head; 1917 rx_data = agg->head; 1918 len_used += sizeof(struct rx_desc); 1919 1920 while (urb->actual_length > len_used) { 1921 struct net_device *netdev = tp->netdev; 1922 struct net_device_stats *stats = &netdev->stats; 1923 unsigned int pkt_len; 1924 struct sk_buff *skb; 1925 1926 /* limite the skb numbers for rx_queue */ 1927 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000)) 1928 break; 1929 1930 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1931 if (pkt_len < ETH_ZLEN) 1932 break; 1933 1934 len_used += pkt_len; 1935 if (urb->actual_length < len_used) 1936 break; 1937 1938 pkt_len -= ETH_FCS_LEN; 1939 rx_data += sizeof(struct rx_desc); 1940 1941 skb = napi_alloc_skb(napi, pkt_len); 1942 if (!skb) { 1943 stats->rx_dropped++; 1944 goto find_next_rx; 1945 } 1946 1947 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 1948 memcpy(skb->data, rx_data, pkt_len); 1949 skb_put(skb, pkt_len); 1950 skb->protocol = eth_type_trans(skb, netdev); 1951 rtl_rx_vlan_tag(rx_desc, skb); 1952 if (work_done < budget) { 1953 napi_gro_receive(napi, skb); 1954 work_done++; 1955 stats->rx_packets++; 1956 stats->rx_bytes += pkt_len; 1957 } else { 1958 __skb_queue_tail(&tp->rx_queue, skb); 1959 } 1960 1961 find_next_rx: 1962 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN); 1963 rx_desc = (struct rx_desc *)rx_data; 1964 len_used = (int)(rx_data - (u8 *)agg->head); 1965 len_used += sizeof(struct rx_desc); 1966 } 1967 1968 submit: 1969 if (!ret) { 1970 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1971 } else { 1972 urb->actual_length = 0; 1973 list_add_tail(&agg->list, next); 1974 } 1975 } 1976 1977 if (!list_empty(&rx_queue)) { 1978 spin_lock_irqsave(&tp->rx_lock, flags); 1979 list_splice_tail(&rx_queue, &tp->rx_done); 1980 spin_unlock_irqrestore(&tp->rx_lock, flags); 1981 } 1982 1983 out1: 1984 return work_done; 1985 } 1986 1987 static void tx_bottom(struct r8152 *tp) 1988 { 1989 int res; 1990 1991 do { 1992 struct tx_agg *agg; 1993 1994 if (skb_queue_empty(&tp->tx_queue)) 1995 break; 1996 1997 agg = r8152_get_tx_agg(tp); 1998 if (!agg) 1999 break; 2000 2001 res = r8152_tx_agg_fill(tp, agg); 2002 if (res) { 2003 struct net_device *netdev = tp->netdev; 2004 2005 if (res == -ENODEV) { 2006 set_bit(RTL8152_UNPLUG, &tp->flags); 2007 netif_device_detach(netdev); 2008 } else { 2009 struct net_device_stats *stats = &netdev->stats; 2010 unsigned long flags; 2011 2012 netif_warn(tp, tx_err, netdev, 2013 "failed tx_urb %d\n", res); 2014 stats->tx_dropped += agg->skb_num; 2015 2016 spin_lock_irqsave(&tp->tx_lock, flags); 2017 list_add_tail(&agg->list, &tp->tx_free); 2018 spin_unlock_irqrestore(&tp->tx_lock, flags); 2019 } 2020 } 2021 } while (res == 0); 2022 } 2023 2024 static void bottom_half(struct r8152 *tp) 2025 { 2026 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2027 return; 2028 2029 if (!test_bit(WORK_ENABLE, &tp->flags)) 2030 return; 2031 2032 /* When link down, the driver would cancel all bulks. */ 2033 /* This avoid the re-submitting bulk */ 2034 if (!netif_carrier_ok(tp->netdev)) 2035 return; 2036 2037 clear_bit(SCHEDULE_NAPI, &tp->flags); 2038 2039 tx_bottom(tp); 2040 } 2041 2042 static int r8152_poll(struct napi_struct *napi, int budget) 2043 { 2044 struct r8152 *tp = container_of(napi, struct r8152, napi); 2045 int work_done; 2046 2047 work_done = rx_bottom(tp, budget); 2048 bottom_half(tp); 2049 2050 if (work_done < budget) { 2051 if (!napi_complete_done(napi, work_done)) 2052 goto out; 2053 if (!list_empty(&tp->rx_done)) 2054 napi_schedule(napi); 2055 else if (!skb_queue_empty(&tp->tx_queue) && 2056 !list_empty(&tp->tx_free)) 2057 napi_schedule(napi); 2058 } 2059 2060 out: 2061 return work_done; 2062 } 2063 2064 static 2065 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 2066 { 2067 int ret; 2068 2069 /* The rx would be stopped, so skip submitting */ 2070 if (test_bit(RTL8152_UNPLUG, &tp->flags) || 2071 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) 2072 return 0; 2073 2074 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 2075 agg->head, agg_buf_sz, 2076 (usb_complete_t)read_bulk_callback, agg); 2077 2078 ret = usb_submit_urb(agg->urb, mem_flags); 2079 if (ret == -ENODEV) { 2080 set_bit(RTL8152_UNPLUG, &tp->flags); 2081 netif_device_detach(tp->netdev); 2082 } else if (ret) { 2083 struct urb *urb = agg->urb; 2084 unsigned long flags; 2085 2086 urb->actual_length = 0; 2087 spin_lock_irqsave(&tp->rx_lock, flags); 2088 list_add_tail(&agg->list, &tp->rx_done); 2089 spin_unlock_irqrestore(&tp->rx_lock, flags); 2090 2091 netif_err(tp, rx_err, tp->netdev, 2092 "Couldn't submit rx[%p], ret = %d\n", agg, ret); 2093 2094 napi_schedule(&tp->napi); 2095 } 2096 2097 return ret; 2098 } 2099 2100 static void rtl_drop_queued_tx(struct r8152 *tp) 2101 { 2102 struct net_device_stats *stats = &tp->netdev->stats; 2103 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 2104 struct sk_buff *skb; 2105 2106 if (skb_queue_empty(tx_queue)) 2107 return; 2108 2109 __skb_queue_head_init(&skb_head); 2110 spin_lock_bh(&tx_queue->lock); 2111 skb_queue_splice_init(tx_queue, &skb_head); 2112 spin_unlock_bh(&tx_queue->lock); 2113 2114 while ((skb = __skb_dequeue(&skb_head))) { 2115 dev_kfree_skb(skb); 2116 stats->tx_dropped++; 2117 } 2118 } 2119 2120 static void rtl8152_tx_timeout(struct net_device *netdev) 2121 { 2122 struct r8152 *tp = netdev_priv(netdev); 2123 2124 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 2125 2126 usb_queue_reset_device(tp->intf); 2127 } 2128 2129 static void rtl8152_set_rx_mode(struct net_device *netdev) 2130 { 2131 struct r8152 *tp = netdev_priv(netdev); 2132 2133 if (netif_carrier_ok(netdev)) { 2134 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2135 schedule_delayed_work(&tp->schedule, 0); 2136 } 2137 } 2138 2139 static void _rtl8152_set_rx_mode(struct net_device *netdev) 2140 { 2141 struct r8152 *tp = netdev_priv(netdev); 2142 u32 mc_filter[2]; /* Multicast hash filter */ 2143 __le32 tmp[2]; 2144 u32 ocp_data; 2145 2146 netif_stop_queue(netdev); 2147 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2148 ocp_data &= ~RCR_ACPT_ALL; 2149 ocp_data |= RCR_AB | RCR_APM; 2150 2151 if (netdev->flags & IFF_PROMISC) { 2152 /* Unconditionally log net taps. */ 2153 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 2154 ocp_data |= RCR_AM | RCR_AAP; 2155 mc_filter[1] = 0xffffffff; 2156 mc_filter[0] = 0xffffffff; 2157 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 2158 (netdev->flags & IFF_ALLMULTI)) { 2159 /* Too many to filter perfectly -- accept all multicasts. */ 2160 ocp_data |= RCR_AM; 2161 mc_filter[1] = 0xffffffff; 2162 mc_filter[0] = 0xffffffff; 2163 } else { 2164 struct netdev_hw_addr *ha; 2165 2166 mc_filter[1] = 0; 2167 mc_filter[0] = 0; 2168 netdev_for_each_mc_addr(ha, netdev) { 2169 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2170 2171 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2172 ocp_data |= RCR_AM; 2173 } 2174 } 2175 2176 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 2177 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 2178 2179 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 2180 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2181 netif_wake_queue(netdev); 2182 } 2183 2184 static netdev_features_t 2185 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 2186 netdev_features_t features) 2187 { 2188 u32 mss = skb_shinfo(skb)->gso_size; 2189 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 2190 int offset = skb_transport_offset(skb); 2191 2192 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) 2193 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2194 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 2195 features &= ~NETIF_F_GSO_MASK; 2196 2197 return features; 2198 } 2199 2200 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 2201 struct net_device *netdev) 2202 { 2203 struct r8152 *tp = netdev_priv(netdev); 2204 2205 skb_tx_timestamp(skb); 2206 2207 skb_queue_tail(&tp->tx_queue, skb); 2208 2209 if (!list_empty(&tp->tx_free)) { 2210 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2211 set_bit(SCHEDULE_NAPI, &tp->flags); 2212 schedule_delayed_work(&tp->schedule, 0); 2213 } else { 2214 usb_mark_last_busy(tp->udev); 2215 napi_schedule(&tp->napi); 2216 } 2217 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 2218 netif_stop_queue(netdev); 2219 } 2220 2221 return NETDEV_TX_OK; 2222 } 2223 2224 static void r8152b_reset_packet_filter(struct r8152 *tp) 2225 { 2226 u32 ocp_data; 2227 2228 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 2229 ocp_data &= ~FMC_FCR_MCU_EN; 2230 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2231 ocp_data |= FMC_FCR_MCU_EN; 2232 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2233 } 2234 2235 static void rtl8152_nic_reset(struct r8152 *tp) 2236 { 2237 int i; 2238 2239 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 2240 2241 for (i = 0; i < 1000; i++) { 2242 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 2243 break; 2244 usleep_range(100, 400); 2245 } 2246 } 2247 2248 static void set_tx_qlen(struct r8152 *tp) 2249 { 2250 struct net_device *netdev = tp->netdev; 2251 2252 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN + 2253 sizeof(struct tx_desc)); 2254 } 2255 2256 static inline u8 rtl8152_get_speed(struct r8152 *tp) 2257 { 2258 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 2259 } 2260 2261 static void rtl_set_eee_plus(struct r8152 *tp) 2262 { 2263 u32 ocp_data; 2264 u8 speed; 2265 2266 speed = rtl8152_get_speed(tp); 2267 if (speed & _10bps) { 2268 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2269 ocp_data |= EEEP_CR_EEEP_TX; 2270 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2271 } else { 2272 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2273 ocp_data &= ~EEEP_CR_EEEP_TX; 2274 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2275 } 2276 } 2277 2278 static void rxdy_gated_en(struct r8152 *tp, bool enable) 2279 { 2280 u32 ocp_data; 2281 2282 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 2283 if (enable) 2284 ocp_data |= RXDY_GATED_EN; 2285 else 2286 ocp_data &= ~RXDY_GATED_EN; 2287 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 2288 } 2289 2290 static int rtl_start_rx(struct r8152 *tp) 2291 { 2292 int i, ret = 0; 2293 2294 INIT_LIST_HEAD(&tp->rx_done); 2295 for (i = 0; i < RTL8152_MAX_RX; i++) { 2296 INIT_LIST_HEAD(&tp->rx_info[i].list); 2297 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 2298 if (ret) 2299 break; 2300 } 2301 2302 if (ret && ++i < RTL8152_MAX_RX) { 2303 struct list_head rx_queue; 2304 unsigned long flags; 2305 2306 INIT_LIST_HEAD(&rx_queue); 2307 2308 do { 2309 struct rx_agg *agg = &tp->rx_info[i++]; 2310 struct urb *urb = agg->urb; 2311 2312 urb->actual_length = 0; 2313 list_add_tail(&agg->list, &rx_queue); 2314 } while (i < RTL8152_MAX_RX); 2315 2316 spin_lock_irqsave(&tp->rx_lock, flags); 2317 list_splice_tail(&rx_queue, &tp->rx_done); 2318 spin_unlock_irqrestore(&tp->rx_lock, flags); 2319 } 2320 2321 return ret; 2322 } 2323 2324 static int rtl_stop_rx(struct r8152 *tp) 2325 { 2326 int i; 2327 2328 for (i = 0; i < RTL8152_MAX_RX; i++) 2329 usb_kill_urb(tp->rx_info[i].urb); 2330 2331 while (!skb_queue_empty(&tp->rx_queue)) 2332 dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); 2333 2334 return 0; 2335 } 2336 2337 static int rtl_enable(struct r8152 *tp) 2338 { 2339 u32 ocp_data; 2340 2341 r8152b_reset_packet_filter(tp); 2342 2343 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2344 ocp_data |= CR_RE | CR_TE; 2345 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2346 2347 rxdy_gated_en(tp, false); 2348 2349 return 0; 2350 } 2351 2352 static int rtl8152_enable(struct r8152 *tp) 2353 { 2354 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2355 return -ENODEV; 2356 2357 set_tx_qlen(tp); 2358 rtl_set_eee_plus(tp); 2359 2360 return rtl_enable(tp); 2361 } 2362 2363 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) 2364 { 2365 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, 2366 OWN_UPDATE | OWN_CLEAR); 2367 } 2368 2369 static void r8153_set_rx_early_timeout(struct r8152 *tp) 2370 { 2371 u32 ocp_data = tp->coalesce / 8; 2372 2373 switch (tp->version) { 2374 case RTL_VER_03: 2375 case RTL_VER_04: 2376 case RTL_VER_05: 2377 case RTL_VER_06: 2378 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2379 ocp_data); 2380 break; 2381 2382 case RTL_VER_08: 2383 case RTL_VER_09: 2384 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout 2385 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns. 2386 */ 2387 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2388 128 / 8); 2389 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, 2390 ocp_data); 2391 r8153b_rx_agg_chg_indicate(tp); 2392 break; 2393 2394 default: 2395 break; 2396 } 2397 } 2398 2399 static void r8153_set_rx_early_size(struct r8152 *tp) 2400 { 2401 u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu); 2402 2403 switch (tp->version) { 2404 case RTL_VER_03: 2405 case RTL_VER_04: 2406 case RTL_VER_05: 2407 case RTL_VER_06: 2408 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2409 ocp_data / 4); 2410 break; 2411 case RTL_VER_08: 2412 case RTL_VER_09: 2413 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2414 ocp_data / 8); 2415 r8153b_rx_agg_chg_indicate(tp); 2416 break; 2417 default: 2418 WARN_ON_ONCE(1); 2419 break; 2420 } 2421 } 2422 2423 static int rtl8153_enable(struct r8152 *tp) 2424 { 2425 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2426 return -ENODEV; 2427 2428 set_tx_qlen(tp); 2429 rtl_set_eee_plus(tp); 2430 r8153_set_rx_early_timeout(tp); 2431 r8153_set_rx_early_size(tp); 2432 2433 return rtl_enable(tp); 2434 } 2435 2436 static void rtl_disable(struct r8152 *tp) 2437 { 2438 u32 ocp_data; 2439 int i; 2440 2441 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2442 rtl_drop_queued_tx(tp); 2443 return; 2444 } 2445 2446 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2447 ocp_data &= ~RCR_ACPT_ALL; 2448 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2449 2450 rtl_drop_queued_tx(tp); 2451 2452 for (i = 0; i < RTL8152_MAX_TX; i++) 2453 usb_kill_urb(tp->tx_info[i].urb); 2454 2455 rxdy_gated_en(tp, true); 2456 2457 for (i = 0; i < 1000; i++) { 2458 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2459 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2460 break; 2461 usleep_range(1000, 2000); 2462 } 2463 2464 for (i = 0; i < 1000; i++) { 2465 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2466 break; 2467 usleep_range(1000, 2000); 2468 } 2469 2470 rtl_stop_rx(tp); 2471 2472 rtl8152_nic_reset(tp); 2473 } 2474 2475 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2476 { 2477 u32 ocp_data; 2478 2479 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2480 if (enable) 2481 ocp_data |= POWER_CUT; 2482 else 2483 ocp_data &= ~POWER_CUT; 2484 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2485 2486 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2487 ocp_data &= ~RESUME_INDICATE; 2488 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2489 } 2490 2491 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 2492 { 2493 u32 ocp_data; 2494 2495 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2496 if (enable) 2497 ocp_data |= CPCR_RX_VLAN; 2498 else 2499 ocp_data &= ~CPCR_RX_VLAN; 2500 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2501 } 2502 2503 static int rtl8152_set_features(struct net_device *dev, 2504 netdev_features_t features) 2505 { 2506 netdev_features_t changed = features ^ dev->features; 2507 struct r8152 *tp = netdev_priv(dev); 2508 int ret; 2509 2510 ret = usb_autopm_get_interface(tp->intf); 2511 if (ret < 0) 2512 goto out; 2513 2514 mutex_lock(&tp->control); 2515 2516 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 2517 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2518 rtl_rx_vlan_en(tp, true); 2519 else 2520 rtl_rx_vlan_en(tp, false); 2521 } 2522 2523 mutex_unlock(&tp->control); 2524 2525 usb_autopm_put_interface(tp->intf); 2526 2527 out: 2528 return ret; 2529 } 2530 2531 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2532 2533 static u32 __rtl_get_wol(struct r8152 *tp) 2534 { 2535 u32 ocp_data; 2536 u32 wolopts = 0; 2537 2538 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2539 if (ocp_data & LINK_ON_WAKE_EN) 2540 wolopts |= WAKE_PHY; 2541 2542 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2543 if (ocp_data & UWF_EN) 2544 wolopts |= WAKE_UCAST; 2545 if (ocp_data & BWF_EN) 2546 wolopts |= WAKE_BCAST; 2547 if (ocp_data & MWF_EN) 2548 wolopts |= WAKE_MCAST; 2549 2550 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2551 if (ocp_data & MAGIC_EN) 2552 wolopts |= WAKE_MAGIC; 2553 2554 return wolopts; 2555 } 2556 2557 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2558 { 2559 u32 ocp_data; 2560 2561 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2562 2563 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2564 ocp_data &= ~LINK_ON_WAKE_EN; 2565 if (wolopts & WAKE_PHY) 2566 ocp_data |= LINK_ON_WAKE_EN; 2567 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2568 2569 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2570 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); 2571 if (wolopts & WAKE_UCAST) 2572 ocp_data |= UWF_EN; 2573 if (wolopts & WAKE_BCAST) 2574 ocp_data |= BWF_EN; 2575 if (wolopts & WAKE_MCAST) 2576 ocp_data |= MWF_EN; 2577 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2578 2579 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2580 2581 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2582 ocp_data &= ~MAGIC_EN; 2583 if (wolopts & WAKE_MAGIC) 2584 ocp_data |= MAGIC_EN; 2585 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2586 2587 if (wolopts & WAKE_ANY) 2588 device_set_wakeup_enable(&tp->udev->dev, true); 2589 else 2590 device_set_wakeup_enable(&tp->udev->dev, false); 2591 } 2592 2593 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable) 2594 { 2595 /* MAC clock speed down */ 2596 if (enable) { 2597 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 2598 ALDPS_SPDWN_RATIO); 2599 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 2600 EEE_SPDWN_RATIO); 2601 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 2602 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | 2603 U1U2_SPDWN_EN | L1_SPDWN_EN); 2604 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 2605 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | 2606 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN | 2607 TP1000_SPDWN_EN); 2608 } else { 2609 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); 2610 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); 2611 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); 2612 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); 2613 } 2614 } 2615 2616 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2617 { 2618 u8 u1u2[8]; 2619 2620 if (enable) 2621 memset(u1u2, 0xff, sizeof(u1u2)); 2622 else 2623 memset(u1u2, 0x00, sizeof(u1u2)); 2624 2625 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2626 } 2627 2628 static void r8153b_u1u2en(struct r8152 *tp, bool enable) 2629 { 2630 u32 ocp_data; 2631 2632 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); 2633 if (enable) 2634 ocp_data |= LPM_U1U2_EN; 2635 else 2636 ocp_data &= ~LPM_U1U2_EN; 2637 2638 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); 2639 } 2640 2641 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2642 { 2643 u32 ocp_data; 2644 2645 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2646 if (enable) 2647 ocp_data |= U2P3_ENABLE; 2648 else 2649 ocp_data &= ~U2P3_ENABLE; 2650 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2651 } 2652 2653 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear) 2654 { 2655 u32 ocp_data; 2656 2657 ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS); 2658 ocp_data &= ~clear; 2659 ocp_data |= set; 2660 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data); 2661 } 2662 2663 static void r8153b_green_en(struct r8152 *tp, bool enable) 2664 { 2665 u16 data; 2666 2667 if (enable) { 2668 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ 2669 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ 2670 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ 2671 } else { 2672 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ 2673 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ 2674 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ 2675 } 2676 2677 data = sram_read(tp, SRAM_GREEN_CFG); 2678 data |= GREEN_ETH_EN; 2679 sram_write(tp, SRAM_GREEN_CFG, data); 2680 2681 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0); 2682 } 2683 2684 static u16 r8153_phy_status(struct r8152 *tp, u16 desired) 2685 { 2686 u16 data; 2687 int i; 2688 2689 for (i = 0; i < 500; i++) { 2690 data = ocp_reg_read(tp, OCP_PHY_STATUS); 2691 data &= PHY_STAT_MASK; 2692 if (desired) { 2693 if (data == desired) 2694 break; 2695 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN || 2696 data == PHY_STAT_EXT_INIT) { 2697 break; 2698 } 2699 2700 msleep(20); 2701 } 2702 2703 return data; 2704 } 2705 2706 static void r8153b_ups_en(struct r8152 *tp, bool enable) 2707 { 2708 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); 2709 2710 if (enable) { 2711 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; 2712 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2713 2714 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 2715 ocp_data |= BIT(0); 2716 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 2717 } else { 2718 u16 data; 2719 2720 ocp_data &= ~(UPS_EN | USP_PREWAKE); 2721 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2722 2723 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 2724 ocp_data &= ~BIT(0); 2725 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 2726 2727 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2728 ocp_data &= ~PCUT_STATUS; 2729 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2730 2731 data = r8153_phy_status(tp, 0); 2732 2733 switch (data) { 2734 case PHY_STAT_PWRDN: 2735 case PHY_STAT_EXT_INIT: 2736 r8153b_green_en(tp, 2737 test_bit(GREEN_ETHERNET, &tp->flags)); 2738 2739 data = r8152_mdio_read(tp, MII_BMCR); 2740 data &= ~BMCR_PDOWN; 2741 data |= BMCR_RESET; 2742 r8152_mdio_write(tp, MII_BMCR, data); 2743 2744 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 2745 /* fall through */ 2746 2747 default: 2748 if (data != PHY_STAT_LAN_ON) 2749 netif_warn(tp, link, tp->netdev, 2750 "PHY not ready"); 2751 break; 2752 } 2753 } 2754 } 2755 2756 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2757 { 2758 u32 ocp_data; 2759 2760 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2761 if (enable) 2762 ocp_data |= PWR_EN | PHASE2_EN; 2763 else 2764 ocp_data &= ~(PWR_EN | PHASE2_EN); 2765 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2766 2767 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2768 ocp_data &= ~PCUT_STATUS; 2769 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2770 } 2771 2772 static void r8153b_power_cut_en(struct r8152 *tp, bool enable) 2773 { 2774 u32 ocp_data; 2775 2776 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2777 if (enable) 2778 ocp_data |= PWR_EN | PHASE2_EN; 2779 else 2780 ocp_data &= ~PWR_EN; 2781 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2782 2783 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2784 ocp_data &= ~PCUT_STATUS; 2785 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2786 } 2787 2788 static void r8153b_queue_wake(struct r8152 *tp, bool enable) 2789 { 2790 u32 ocp_data; 2791 2792 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a); 2793 if (enable) 2794 ocp_data |= BIT(0); 2795 else 2796 ocp_data &= ~BIT(0); 2797 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data); 2798 2799 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c); 2800 ocp_data &= ~BIT(0); 2801 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data); 2802 } 2803 2804 static bool rtl_can_wakeup(struct r8152 *tp) 2805 { 2806 struct usb_device *udev = tp->udev; 2807 2808 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); 2809 } 2810 2811 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 2812 { 2813 if (enable) { 2814 u32 ocp_data; 2815 2816 __rtl_set_wol(tp, WAKE_ANY); 2817 2818 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2819 2820 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2821 ocp_data |= LINK_OFF_WAKE_EN; 2822 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2823 2824 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2825 } else { 2826 u32 ocp_data; 2827 2828 __rtl_set_wol(tp, tp->saved_wolopts); 2829 2830 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2831 2832 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2833 ocp_data &= ~LINK_OFF_WAKE_EN; 2834 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2835 2836 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2837 } 2838 } 2839 2840 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) 2841 { 2842 if (enable) { 2843 r8153_u1u2en(tp, false); 2844 r8153_u2p3en(tp, false); 2845 r8153_mac_clk_spd(tp, true); 2846 rtl_runtime_suspend_enable(tp, true); 2847 } else { 2848 rtl_runtime_suspend_enable(tp, false); 2849 r8153_mac_clk_spd(tp, false); 2850 2851 switch (tp->version) { 2852 case RTL_VER_03: 2853 case RTL_VER_04: 2854 break; 2855 case RTL_VER_05: 2856 case RTL_VER_06: 2857 default: 2858 r8153_u2p3en(tp, true); 2859 break; 2860 } 2861 2862 r8153_u1u2en(tp, true); 2863 } 2864 } 2865 2866 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable) 2867 { 2868 if (enable) { 2869 r8153b_queue_wake(tp, true); 2870 r8153b_u1u2en(tp, false); 2871 r8153_u2p3en(tp, false); 2872 rtl_runtime_suspend_enable(tp, true); 2873 r8153b_ups_en(tp, true); 2874 } else { 2875 r8153b_ups_en(tp, false); 2876 r8153b_queue_wake(tp, false); 2877 rtl_runtime_suspend_enable(tp, false); 2878 r8153_u2p3en(tp, true); 2879 r8153b_u1u2en(tp, true); 2880 } 2881 } 2882 2883 static void r8153_teredo_off(struct r8152 *tp) 2884 { 2885 u32 ocp_data; 2886 2887 switch (tp->version) { 2888 case RTL_VER_01: 2889 case RTL_VER_02: 2890 case RTL_VER_03: 2891 case RTL_VER_04: 2892 case RTL_VER_05: 2893 case RTL_VER_06: 2894 case RTL_VER_07: 2895 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2896 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | 2897 OOB_TEREDO_EN); 2898 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2899 break; 2900 2901 case RTL_VER_08: 2902 case RTL_VER_09: 2903 /* The bit 0 ~ 7 are relative with teredo settings. They are 2904 * W1C (write 1 to clear), so set all 1 to disable it. 2905 */ 2906 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); 2907 break; 2908 2909 default: 2910 break; 2911 } 2912 2913 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 2914 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 2915 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 2916 } 2917 2918 static void rtl_reset_bmu(struct r8152 *tp) 2919 { 2920 u32 ocp_data; 2921 2922 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); 2923 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 2924 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2925 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 2926 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2927 } 2928 2929 static void r8152_aldps_en(struct r8152 *tp, bool enable) 2930 { 2931 if (enable) { 2932 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 2933 LINKENA | DIS_SDSAVE); 2934 } else { 2935 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | 2936 DIS_SDSAVE); 2937 msleep(20); 2938 } 2939 } 2940 2941 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 2942 { 2943 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 2944 ocp_reg_write(tp, OCP_EEE_DATA, reg); 2945 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 2946 } 2947 2948 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 2949 { 2950 u16 data; 2951 2952 r8152_mmd_indirect(tp, dev, reg); 2953 data = ocp_reg_read(tp, OCP_EEE_DATA); 2954 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 2955 2956 return data; 2957 } 2958 2959 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 2960 { 2961 r8152_mmd_indirect(tp, dev, reg); 2962 ocp_reg_write(tp, OCP_EEE_DATA, data); 2963 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 2964 } 2965 2966 static void r8152_eee_en(struct r8152 *tp, bool enable) 2967 { 2968 u16 config1, config2, config3; 2969 u32 ocp_data; 2970 2971 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 2972 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 2973 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 2974 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 2975 2976 if (enable) { 2977 ocp_data |= EEE_RX_EN | EEE_TX_EN; 2978 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 2979 config1 |= sd_rise_time(1); 2980 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 2981 config3 |= fast_snr(42); 2982 } else { 2983 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 2984 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 2985 RX_QUIET_EN); 2986 config1 |= sd_rise_time(7); 2987 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 2988 config3 |= fast_snr(511); 2989 } 2990 2991 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 2992 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 2993 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 2994 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 2995 } 2996 2997 static void r8152b_enable_eee(struct r8152 *tp) 2998 { 2999 r8152_eee_en(tp, true); 3000 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); 3001 } 3002 3003 static void r8152b_enable_fc(struct r8152 *tp) 3004 { 3005 u16 anar; 3006 3007 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3008 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 3009 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3010 } 3011 3012 static void rtl8152_disable(struct r8152 *tp) 3013 { 3014 r8152_aldps_en(tp, false); 3015 rtl_disable(tp); 3016 r8152_aldps_en(tp, true); 3017 } 3018 3019 static void r8152b_hw_phy_cfg(struct r8152 *tp) 3020 { 3021 r8152b_enable_eee(tp); 3022 r8152_aldps_en(tp, true); 3023 r8152b_enable_fc(tp); 3024 3025 set_bit(PHY_RESET, &tp->flags); 3026 } 3027 3028 static void r8152b_exit_oob(struct r8152 *tp) 3029 { 3030 u32 ocp_data; 3031 int i; 3032 3033 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3034 ocp_data &= ~RCR_ACPT_ALL; 3035 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3036 3037 rxdy_gated_en(tp, true); 3038 r8153_teredo_off(tp); 3039 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3040 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 3041 3042 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3043 ocp_data &= ~NOW_IS_OOB; 3044 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3045 3046 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3047 ocp_data &= ~MCU_BORW_EN; 3048 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3049 3050 for (i = 0; i < 1000; i++) { 3051 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3052 if (ocp_data & LINK_LIST_READY) 3053 break; 3054 usleep_range(1000, 2000); 3055 } 3056 3057 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3058 ocp_data |= RE_INIT_LL; 3059 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3060 3061 for (i = 0; i < 1000; i++) { 3062 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3063 if (ocp_data & LINK_LIST_READY) 3064 break; 3065 usleep_range(1000, 2000); 3066 } 3067 3068 rtl8152_nic_reset(tp); 3069 3070 /* rx share fifo credit full threshold */ 3071 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3072 3073 if (tp->udev->speed == USB_SPEED_FULL || 3074 tp->udev->speed == USB_SPEED_LOW) { 3075 /* rx share fifo credit near full threshold */ 3076 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3077 RXFIFO_THR2_FULL); 3078 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3079 RXFIFO_THR3_FULL); 3080 } else { 3081 /* rx share fifo credit near full threshold */ 3082 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3083 RXFIFO_THR2_HIGH); 3084 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3085 RXFIFO_THR3_HIGH); 3086 } 3087 3088 /* TX share fifo free credit full threshold */ 3089 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 3090 3091 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 3092 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 3093 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 3094 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 3095 3096 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3097 3098 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3099 3100 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3101 ocp_data |= TCR0_AUTO_FIFO; 3102 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3103 } 3104 3105 static void r8152b_enter_oob(struct r8152 *tp) 3106 { 3107 u32 ocp_data; 3108 int i; 3109 3110 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3111 ocp_data &= ~NOW_IS_OOB; 3112 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3113 3114 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 3115 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 3116 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 3117 3118 rtl_disable(tp); 3119 3120 for (i = 0; i < 1000; i++) { 3121 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3122 if (ocp_data & LINK_LIST_READY) 3123 break; 3124 usleep_range(1000, 2000); 3125 } 3126 3127 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3128 ocp_data |= RE_INIT_LL; 3129 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3130 3131 for (i = 0; i < 1000; i++) { 3132 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3133 if (ocp_data & LINK_LIST_READY) 3134 break; 3135 usleep_range(1000, 2000); 3136 } 3137 3138 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3139 3140 rtl_rx_vlan_en(tp, true); 3141 3142 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 3143 ocp_data |= ALDPS_PROXY_MODE; 3144 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 3145 3146 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3147 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3148 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3149 3150 rxdy_gated_en(tp, false); 3151 3152 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3153 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3154 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3155 } 3156 3157 static int r8153_patch_request(struct r8152 *tp, bool request) 3158 { 3159 u16 data; 3160 int i; 3161 3162 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD); 3163 if (request) 3164 data |= PATCH_REQUEST; 3165 else 3166 data &= ~PATCH_REQUEST; 3167 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); 3168 3169 for (i = 0; request && i < 5000; i++) { 3170 usleep_range(1000, 2000); 3171 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY) 3172 break; 3173 } 3174 3175 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) { 3176 netif_err(tp, drv, tp->netdev, "patch request fail\n"); 3177 r8153_patch_request(tp, false); 3178 return -ETIME; 3179 } else { 3180 return 0; 3181 } 3182 } 3183 3184 static void r8153_aldps_en(struct r8152 *tp, bool enable) 3185 { 3186 u16 data; 3187 3188 data = ocp_reg_read(tp, OCP_POWER_CFG); 3189 if (enable) { 3190 data |= EN_ALDPS; 3191 ocp_reg_write(tp, OCP_POWER_CFG, data); 3192 } else { 3193 int i; 3194 3195 data &= ~EN_ALDPS; 3196 ocp_reg_write(tp, OCP_POWER_CFG, data); 3197 for (i = 0; i < 20; i++) { 3198 usleep_range(1000, 2000); 3199 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) 3200 break; 3201 } 3202 } 3203 } 3204 3205 static void r8153b_aldps_en(struct r8152 *tp, bool enable) 3206 { 3207 r8153_aldps_en(tp, enable); 3208 3209 if (enable) 3210 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0); 3211 else 3212 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS); 3213 } 3214 3215 static void r8153_eee_en(struct r8152 *tp, bool enable) 3216 { 3217 u32 ocp_data; 3218 u16 config; 3219 3220 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3221 config = ocp_reg_read(tp, OCP_EEE_CFG); 3222 3223 if (enable) { 3224 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3225 config |= EEE10_EN; 3226 } else { 3227 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3228 config &= ~EEE10_EN; 3229 } 3230 3231 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3232 ocp_reg_write(tp, OCP_EEE_CFG, config); 3233 } 3234 3235 static void r8153b_eee_en(struct r8152 *tp, bool enable) 3236 { 3237 r8153_eee_en(tp, enable); 3238 3239 if (enable) 3240 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0); 3241 else 3242 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE); 3243 } 3244 3245 static void r8153b_enable_fc(struct r8152 *tp) 3246 { 3247 r8152b_enable_fc(tp); 3248 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0); 3249 } 3250 3251 static void r8153_hw_phy_cfg(struct r8152 *tp) 3252 { 3253 u32 ocp_data; 3254 u16 data; 3255 3256 /* disable ALDPS before updating the PHY parameters */ 3257 r8153_aldps_en(tp, false); 3258 3259 /* disable EEE before updating the PHY parameters */ 3260 r8153_eee_en(tp, false); 3261 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3262 3263 if (tp->version == RTL_VER_03) { 3264 data = ocp_reg_read(tp, OCP_EEE_CFG); 3265 data &= ~CTAP_SHORT_EN; 3266 ocp_reg_write(tp, OCP_EEE_CFG, data); 3267 } 3268 3269 data = ocp_reg_read(tp, OCP_POWER_CFG); 3270 data |= EEE_CLKDIV_EN; 3271 ocp_reg_write(tp, OCP_POWER_CFG, data); 3272 3273 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3274 data |= EN_10M_BGOFF; 3275 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3276 data = ocp_reg_read(tp, OCP_POWER_CFG); 3277 data |= EN_10M_PLLOFF; 3278 ocp_reg_write(tp, OCP_POWER_CFG, data); 3279 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 3280 3281 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3282 ocp_data |= PFM_PWM_SWITCH; 3283 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3284 3285 /* Enable LPF corner auto tune */ 3286 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 3287 3288 /* Adjust 10M Amplitude */ 3289 sram_write(tp, SRAM_10M_AMP1, 0x00af); 3290 sram_write(tp, SRAM_10M_AMP2, 0x0208); 3291 3292 r8153_eee_en(tp, true); 3293 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3294 3295 r8153_aldps_en(tp, true); 3296 r8152b_enable_fc(tp); 3297 3298 switch (tp->version) { 3299 case RTL_VER_03: 3300 case RTL_VER_04: 3301 break; 3302 case RTL_VER_05: 3303 case RTL_VER_06: 3304 default: 3305 r8153_u2p3en(tp, true); 3306 break; 3307 } 3308 3309 set_bit(PHY_RESET, &tp->flags); 3310 } 3311 3312 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) 3313 { 3314 u32 ocp_data; 3315 3316 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr); 3317 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD); 3318 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */ 3319 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA); 3320 3321 return ocp_data; 3322 } 3323 3324 static void r8153b_hw_phy_cfg(struct r8152 *tp) 3325 { 3326 u32 ocp_data, ups_flags = 0; 3327 u16 data; 3328 3329 /* disable ALDPS before updating the PHY parameters */ 3330 r8153b_aldps_en(tp, false); 3331 3332 /* disable EEE before updating the PHY parameters */ 3333 r8153b_eee_en(tp, false); 3334 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3335 3336 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); 3337 3338 data = sram_read(tp, SRAM_GREEN_CFG); 3339 data |= R_TUNE_EN; 3340 sram_write(tp, SRAM_GREEN_CFG, data); 3341 data = ocp_reg_read(tp, OCP_NCTL_CFG); 3342 data |= PGA_RETURN_EN; 3343 ocp_reg_write(tp, OCP_NCTL_CFG, data); 3344 3345 /* ADC Bias Calibration: 3346 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake 3347 * bit (bit3) to rebuild the real 16-bit data. Write the data to the 3348 * ADC ioffset. 3349 */ 3350 ocp_data = r8152_efuse_read(tp, 0x7d); 3351 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); 3352 if (data != 0xffff) 3353 ocp_reg_write(tp, OCP_ADC_IOFFSET, data); 3354 3355 /* ups mode tx-link-pulse timing adjustment: 3356 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] 3357 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt 3358 */ 3359 ocp_data = ocp_reg_read(tp, 0xc426); 3360 ocp_data &= 0x3fff; 3361 if (ocp_data) { 3362 u32 swr_cnt_1ms_ini; 3363 3364 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; 3365 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); 3366 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; 3367 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); 3368 } 3369 3370 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3371 ocp_data |= PFM_PWM_SWITCH; 3372 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3373 3374 /* Advnace EEE */ 3375 if (!r8153_patch_request(tp, true)) { 3376 data = ocp_reg_read(tp, OCP_POWER_CFG); 3377 data |= EEE_CLKDIV_EN; 3378 ocp_reg_write(tp, OCP_POWER_CFG, data); 3379 3380 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3381 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV; 3382 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3383 3384 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); 3385 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5)); 3386 3387 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV | 3388 UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN | 3389 UPS_FLAGS_EEE_PLLOFF_GIGA; 3390 3391 r8153_patch_request(tp, false); 3392 } 3393 3394 r8153b_ups_flags_w1w0(tp, ups_flags, 0); 3395 3396 r8153b_eee_en(tp, true); 3397 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3398 3399 r8153b_aldps_en(tp, true); 3400 r8153b_enable_fc(tp); 3401 r8153_u2p3en(tp, true); 3402 3403 set_bit(PHY_RESET, &tp->flags); 3404 } 3405 3406 static void r8153_first_init(struct r8152 *tp) 3407 { 3408 u32 ocp_data; 3409 int i; 3410 3411 r8153_mac_clk_spd(tp, false); 3412 rxdy_gated_en(tp, true); 3413 r8153_teredo_off(tp); 3414 3415 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3416 ocp_data &= ~RCR_ACPT_ALL; 3417 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3418 3419 rtl8152_nic_reset(tp); 3420 rtl_reset_bmu(tp); 3421 3422 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3423 ocp_data &= ~NOW_IS_OOB; 3424 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3425 3426 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3427 ocp_data &= ~MCU_BORW_EN; 3428 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3429 3430 for (i = 0; i < 1000; i++) { 3431 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3432 if (ocp_data & LINK_LIST_READY) 3433 break; 3434 usleep_range(1000, 2000); 3435 } 3436 3437 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3438 ocp_data |= RE_INIT_LL; 3439 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3440 3441 for (i = 0; i < 1000; i++) { 3442 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3443 if (ocp_data & LINK_LIST_READY) 3444 break; 3445 usleep_range(1000, 2000); 3446 } 3447 3448 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3449 3450 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3451 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3452 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 3453 3454 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3455 ocp_data |= TCR0_AUTO_FIFO; 3456 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3457 3458 rtl8152_nic_reset(tp); 3459 3460 /* rx share fifo credit full threshold */ 3461 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3462 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 3463 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 3464 /* TX share fifo free credit full threshold */ 3465 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 3466 } 3467 3468 static void r8153_enter_oob(struct r8152 *tp) 3469 { 3470 u32 ocp_data; 3471 int i; 3472 3473 r8153_mac_clk_spd(tp, true); 3474 3475 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3476 ocp_data &= ~NOW_IS_OOB; 3477 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3478 3479 rtl_disable(tp); 3480 rtl_reset_bmu(tp); 3481 3482 for (i = 0; i < 1000; i++) { 3483 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3484 if (ocp_data & LINK_LIST_READY) 3485 break; 3486 usleep_range(1000, 2000); 3487 } 3488 3489 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3490 ocp_data |= RE_INIT_LL; 3491 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3492 3493 for (i = 0; i < 1000; i++) { 3494 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3495 if (ocp_data & LINK_LIST_READY) 3496 break; 3497 usleep_range(1000, 2000); 3498 } 3499 3500 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3501 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3502 3503 switch (tp->version) { 3504 case RTL_VER_03: 3505 case RTL_VER_04: 3506 case RTL_VER_05: 3507 case RTL_VER_06: 3508 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 3509 ocp_data &= ~TEREDO_WAKE_MASK; 3510 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 3511 break; 3512 3513 case RTL_VER_08: 3514 case RTL_VER_09: 3515 /* Clear teredo wake event. bit[15:8] is the teredo wakeup 3516 * type. Set it to zero. bits[7:0] are the W1C bits about 3517 * the events. Set them to all 1 to clear them. 3518 */ 3519 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); 3520 break; 3521 3522 default: 3523 break; 3524 } 3525 3526 rtl_rx_vlan_en(tp, true); 3527 3528 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 3529 ocp_data |= ALDPS_PROXY_MODE; 3530 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 3531 3532 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3533 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3534 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3535 3536 rxdy_gated_en(tp, false); 3537 3538 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3539 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3540 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3541 } 3542 3543 static void rtl8153_disable(struct r8152 *tp) 3544 { 3545 r8153_aldps_en(tp, false); 3546 rtl_disable(tp); 3547 rtl_reset_bmu(tp); 3548 r8153_aldps_en(tp, true); 3549 } 3550 3551 static void rtl8153b_disable(struct r8152 *tp) 3552 { 3553 r8153b_aldps_en(tp, false); 3554 rtl_disable(tp); 3555 rtl_reset_bmu(tp); 3556 r8153b_aldps_en(tp, true); 3557 } 3558 3559 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 3560 { 3561 u16 bmcr, anar, gbcr; 3562 enum spd_duplex speed_duplex; 3563 int ret = 0; 3564 3565 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3566 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 3567 ADVERTISE_100HALF | ADVERTISE_100FULL); 3568 if (tp->mii.supports_gmii) { 3569 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 3570 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 3571 } else { 3572 gbcr = 0; 3573 } 3574 3575 if (autoneg == AUTONEG_DISABLE) { 3576 if (speed == SPEED_10) { 3577 bmcr = 0; 3578 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3579 speed_duplex = FORCE_10M_HALF; 3580 } else if (speed == SPEED_100) { 3581 bmcr = BMCR_SPEED100; 3582 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3583 speed_duplex = FORCE_100M_HALF; 3584 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3585 bmcr = BMCR_SPEED1000; 3586 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3587 speed_duplex = NWAY_1000M_FULL; 3588 } else { 3589 ret = -EINVAL; 3590 goto out; 3591 } 3592 3593 if (duplex == DUPLEX_FULL) { 3594 bmcr |= BMCR_FULLDPLX; 3595 if (speed != SPEED_1000) 3596 speed_duplex++; 3597 } 3598 } else { 3599 if (speed == SPEED_10) { 3600 if (duplex == DUPLEX_FULL) { 3601 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3602 speed_duplex = NWAY_10M_FULL; 3603 } else { 3604 anar |= ADVERTISE_10HALF; 3605 speed_duplex = NWAY_10M_HALF; 3606 } 3607 } else if (speed == SPEED_100) { 3608 if (duplex == DUPLEX_FULL) { 3609 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3610 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3611 speed_duplex = NWAY_100M_FULL; 3612 } else { 3613 anar |= ADVERTISE_10HALF; 3614 anar |= ADVERTISE_100HALF; 3615 speed_duplex = NWAY_100M_HALF; 3616 } 3617 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3618 if (duplex == DUPLEX_FULL) { 3619 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3620 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3621 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3622 } else { 3623 anar |= ADVERTISE_10HALF; 3624 anar |= ADVERTISE_100HALF; 3625 gbcr |= ADVERTISE_1000HALF; 3626 } 3627 speed_duplex = NWAY_1000M_FULL; 3628 } else { 3629 ret = -EINVAL; 3630 goto out; 3631 } 3632 3633 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 3634 } 3635 3636 if (test_and_clear_bit(PHY_RESET, &tp->flags)) 3637 bmcr |= BMCR_RESET; 3638 3639 if (tp->mii.supports_gmii) 3640 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 3641 3642 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3643 r8152_mdio_write(tp, MII_BMCR, bmcr); 3644 3645 switch (tp->version) { 3646 case RTL_VER_08: 3647 case RTL_VER_09: 3648 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex), 3649 UPS_FLAGS_SPEED_MASK); 3650 break; 3651 3652 default: 3653 break; 3654 } 3655 3656 if (bmcr & BMCR_RESET) { 3657 int i; 3658 3659 for (i = 0; i < 50; i++) { 3660 msleep(20); 3661 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 3662 break; 3663 } 3664 } 3665 3666 out: 3667 return ret; 3668 } 3669 3670 static void rtl8152_up(struct r8152 *tp) 3671 { 3672 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3673 return; 3674 3675 r8152_aldps_en(tp, false); 3676 r8152b_exit_oob(tp); 3677 r8152_aldps_en(tp, true); 3678 } 3679 3680 static void rtl8152_down(struct r8152 *tp) 3681 { 3682 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3683 rtl_drop_queued_tx(tp); 3684 return; 3685 } 3686 3687 r8152_power_cut_en(tp, false); 3688 r8152_aldps_en(tp, false); 3689 r8152b_enter_oob(tp); 3690 r8152_aldps_en(tp, true); 3691 } 3692 3693 static void rtl8153_up(struct r8152 *tp) 3694 { 3695 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3696 return; 3697 3698 r8153_u1u2en(tp, false); 3699 r8153_u2p3en(tp, false); 3700 r8153_aldps_en(tp, false); 3701 r8153_first_init(tp); 3702 r8153_aldps_en(tp, true); 3703 3704 switch (tp->version) { 3705 case RTL_VER_03: 3706 case RTL_VER_04: 3707 break; 3708 case RTL_VER_05: 3709 case RTL_VER_06: 3710 default: 3711 r8153_u2p3en(tp, true); 3712 break; 3713 } 3714 3715 r8153_u1u2en(tp, true); 3716 } 3717 3718 static void rtl8153_down(struct r8152 *tp) 3719 { 3720 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3721 rtl_drop_queued_tx(tp); 3722 return; 3723 } 3724 3725 r8153_u1u2en(tp, false); 3726 r8153_u2p3en(tp, false); 3727 r8153_power_cut_en(tp, false); 3728 r8153_aldps_en(tp, false); 3729 r8153_enter_oob(tp); 3730 r8153_aldps_en(tp, true); 3731 } 3732 3733 static void rtl8153b_up(struct r8152 *tp) 3734 { 3735 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3736 return; 3737 3738 r8153b_u1u2en(tp, false); 3739 r8153_u2p3en(tp, false); 3740 r8153b_aldps_en(tp, false); 3741 3742 r8153_first_init(tp); 3743 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); 3744 3745 r8153b_aldps_en(tp, true); 3746 r8153_u2p3en(tp, true); 3747 r8153b_u1u2en(tp, true); 3748 } 3749 3750 static void rtl8153b_down(struct r8152 *tp) 3751 { 3752 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3753 rtl_drop_queued_tx(tp); 3754 return; 3755 } 3756 3757 r8153b_u1u2en(tp, false); 3758 r8153_u2p3en(tp, false); 3759 r8153b_power_cut_en(tp, false); 3760 r8153b_aldps_en(tp, false); 3761 r8153_enter_oob(tp); 3762 r8153b_aldps_en(tp, true); 3763 } 3764 3765 static bool rtl8152_in_nway(struct r8152 *tp) 3766 { 3767 u16 nway_state; 3768 3769 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); 3770 tp->ocp_base = 0x2000; 3771 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ 3772 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); 3773 3774 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ 3775 if (nway_state & 0xc000) 3776 return false; 3777 else 3778 return true; 3779 } 3780 3781 static bool rtl8153_in_nway(struct r8152 *tp) 3782 { 3783 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; 3784 3785 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) 3786 return false; 3787 else 3788 return true; 3789 } 3790 3791 static void set_carrier(struct r8152 *tp) 3792 { 3793 struct net_device *netdev = tp->netdev; 3794 struct napi_struct *napi = &tp->napi; 3795 u8 speed; 3796 3797 speed = rtl8152_get_speed(tp); 3798 3799 if (speed & LINK_STATUS) { 3800 if (!netif_carrier_ok(netdev)) { 3801 tp->rtl_ops.enable(tp); 3802 netif_stop_queue(netdev); 3803 napi_disable(napi); 3804 netif_carrier_on(netdev); 3805 rtl_start_rx(tp); 3806 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 3807 _rtl8152_set_rx_mode(netdev); 3808 napi_enable(&tp->napi); 3809 netif_wake_queue(netdev); 3810 netif_info(tp, link, netdev, "carrier on\n"); 3811 } else if (netif_queue_stopped(netdev) && 3812 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) { 3813 netif_wake_queue(netdev); 3814 } 3815 } else { 3816 if (netif_carrier_ok(netdev)) { 3817 netif_carrier_off(netdev); 3818 napi_disable(napi); 3819 tp->rtl_ops.disable(tp); 3820 napi_enable(napi); 3821 netif_info(tp, link, netdev, "carrier off\n"); 3822 } 3823 } 3824 } 3825 3826 static void rtl_work_func_t(struct work_struct *work) 3827 { 3828 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 3829 3830 /* If the device is unplugged or !netif_running(), the workqueue 3831 * doesn't need to wake the device, and could return directly. 3832 */ 3833 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) 3834 return; 3835 3836 if (usb_autopm_get_interface(tp->intf) < 0) 3837 return; 3838 3839 if (!test_bit(WORK_ENABLE, &tp->flags)) 3840 goto out1; 3841 3842 if (!mutex_trylock(&tp->control)) { 3843 schedule_delayed_work(&tp->schedule, 0); 3844 goto out1; 3845 } 3846 3847 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) 3848 set_carrier(tp); 3849 3850 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) 3851 _rtl8152_set_rx_mode(tp->netdev); 3852 3853 /* don't schedule napi before linking */ 3854 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) && 3855 netif_carrier_ok(tp->netdev)) 3856 napi_schedule(&tp->napi); 3857 3858 mutex_unlock(&tp->control); 3859 3860 out1: 3861 usb_autopm_put_interface(tp->intf); 3862 } 3863 3864 static void rtl_hw_phy_work_func_t(struct work_struct *work) 3865 { 3866 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); 3867 3868 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3869 return; 3870 3871 if (usb_autopm_get_interface(tp->intf) < 0) 3872 return; 3873 3874 mutex_lock(&tp->control); 3875 3876 tp->rtl_ops.hw_phy_cfg(tp); 3877 3878 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex); 3879 3880 mutex_unlock(&tp->control); 3881 3882 usb_autopm_put_interface(tp->intf); 3883 } 3884 3885 #ifdef CONFIG_PM_SLEEP 3886 static int rtl_notifier(struct notifier_block *nb, unsigned long action, 3887 void *data) 3888 { 3889 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); 3890 3891 switch (action) { 3892 case PM_HIBERNATION_PREPARE: 3893 case PM_SUSPEND_PREPARE: 3894 usb_autopm_get_interface(tp->intf); 3895 break; 3896 3897 case PM_POST_HIBERNATION: 3898 case PM_POST_SUSPEND: 3899 usb_autopm_put_interface(tp->intf); 3900 break; 3901 3902 case PM_POST_RESTORE: 3903 case PM_RESTORE_PREPARE: 3904 default: 3905 break; 3906 } 3907 3908 return NOTIFY_DONE; 3909 } 3910 #endif 3911 3912 static int rtl8152_open(struct net_device *netdev) 3913 { 3914 struct r8152 *tp = netdev_priv(netdev); 3915 int res = 0; 3916 3917 res = alloc_all_mem(tp); 3918 if (res) 3919 goto out; 3920 3921 res = usb_autopm_get_interface(tp->intf); 3922 if (res < 0) 3923 goto out_free; 3924 3925 mutex_lock(&tp->control); 3926 3927 tp->rtl_ops.up(tp); 3928 3929 netif_carrier_off(netdev); 3930 netif_start_queue(netdev); 3931 set_bit(WORK_ENABLE, &tp->flags); 3932 3933 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3934 if (res) { 3935 if (res == -ENODEV) 3936 netif_device_detach(tp->netdev); 3937 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 3938 res); 3939 goto out_unlock; 3940 } 3941 napi_enable(&tp->napi); 3942 3943 mutex_unlock(&tp->control); 3944 3945 usb_autopm_put_interface(tp->intf); 3946 #ifdef CONFIG_PM_SLEEP 3947 tp->pm_notifier.notifier_call = rtl_notifier; 3948 register_pm_notifier(&tp->pm_notifier); 3949 #endif 3950 return 0; 3951 3952 out_unlock: 3953 mutex_unlock(&tp->control); 3954 usb_autopm_put_interface(tp->intf); 3955 out_free: 3956 free_all_mem(tp); 3957 out: 3958 return res; 3959 } 3960 3961 static int rtl8152_close(struct net_device *netdev) 3962 { 3963 struct r8152 *tp = netdev_priv(netdev); 3964 int res = 0; 3965 3966 #ifdef CONFIG_PM_SLEEP 3967 unregister_pm_notifier(&tp->pm_notifier); 3968 #endif 3969 if (!test_bit(RTL8152_UNPLUG, &tp->flags)) 3970 napi_disable(&tp->napi); 3971 clear_bit(WORK_ENABLE, &tp->flags); 3972 usb_kill_urb(tp->intr_urb); 3973 cancel_delayed_work_sync(&tp->schedule); 3974 netif_stop_queue(netdev); 3975 3976 res = usb_autopm_get_interface(tp->intf); 3977 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { 3978 rtl_drop_queued_tx(tp); 3979 rtl_stop_rx(tp); 3980 } else { 3981 mutex_lock(&tp->control); 3982 3983 tp->rtl_ops.down(tp); 3984 3985 mutex_unlock(&tp->control); 3986 3987 usb_autopm_put_interface(tp->intf); 3988 } 3989 3990 free_all_mem(tp); 3991 3992 return res; 3993 } 3994 3995 static void rtl_tally_reset(struct r8152 *tp) 3996 { 3997 u32 ocp_data; 3998 3999 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 4000 ocp_data |= TALLY_RESET; 4001 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 4002 } 4003 4004 static void r8152b_init(struct r8152 *tp) 4005 { 4006 u32 ocp_data; 4007 u16 data; 4008 4009 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4010 return; 4011 4012 data = r8152_mdio_read(tp, MII_BMCR); 4013 if (data & BMCR_PDOWN) { 4014 data &= ~BMCR_PDOWN; 4015 r8152_mdio_write(tp, MII_BMCR, data); 4016 } 4017 4018 r8152_aldps_en(tp, false); 4019 4020 if (tp->version == RTL_VER_01) { 4021 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4022 ocp_data &= ~LED_MODE_MASK; 4023 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4024 } 4025 4026 r8152_power_cut_en(tp, false); 4027 4028 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 4029 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 4030 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 4031 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 4032 ocp_data &= ~MCU_CLK_RATIO_MASK; 4033 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 4034 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 4035 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 4036 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 4037 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 4038 4039 rtl_tally_reset(tp); 4040 4041 /* enable rx aggregation */ 4042 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4043 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4044 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4045 } 4046 4047 static void r8153_init(struct r8152 *tp) 4048 { 4049 u32 ocp_data; 4050 u16 data; 4051 int i; 4052 4053 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4054 return; 4055 4056 r8153_u1u2en(tp, false); 4057 4058 for (i = 0; i < 500; i++) { 4059 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4060 AUTOLOAD_DONE) 4061 break; 4062 msleep(20); 4063 } 4064 4065 data = r8153_phy_status(tp, 0); 4066 4067 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 4068 tp->version == RTL_VER_05) 4069 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 4070 4071 data = r8152_mdio_read(tp, MII_BMCR); 4072 if (data & BMCR_PDOWN) { 4073 data &= ~BMCR_PDOWN; 4074 r8152_mdio_write(tp, MII_BMCR, data); 4075 } 4076 4077 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4078 4079 r8153_u2p3en(tp, false); 4080 4081 if (tp->version == RTL_VER_04) { 4082 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 4083 ocp_data &= ~pwd_dn_scale_mask; 4084 ocp_data |= pwd_dn_scale(96); 4085 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 4086 4087 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 4088 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 4089 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 4090 } else if (tp->version == RTL_VER_05) { 4091 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 4092 ocp_data &= ~ECM_ALDPS; 4093 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 4094 4095 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4096 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4097 ocp_data &= ~DYNAMIC_BURST; 4098 else 4099 ocp_data |= DYNAMIC_BURST; 4100 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4101 } else if (tp->version == RTL_VER_06) { 4102 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4103 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4104 ocp_data &= ~DYNAMIC_BURST; 4105 else 4106 ocp_data |= DYNAMIC_BURST; 4107 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4108 } 4109 4110 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 4111 ocp_data |= EP4_FULL_FC; 4112 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 4113 4114 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 4115 ocp_data &= ~TIMER11_EN; 4116 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 4117 4118 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4119 ocp_data &= ~LED_MODE_MASK; 4120 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4121 4122 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 4123 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) 4124 ocp_data |= LPM_TIMER_500MS; 4125 else 4126 ocp_data |= LPM_TIMER_500US; 4127 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 4128 4129 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 4130 ocp_data &= ~SEN_VAL_MASK; 4131 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 4132 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 4133 4134 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 4135 4136 r8153_power_cut_en(tp, false); 4137 r8153_u1u2en(tp, true); 4138 r8153_mac_clk_spd(tp, false); 4139 usb_enable_lpm(tp->udev); 4140 4141 /* rx aggregation */ 4142 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4143 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4144 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags)) 4145 ocp_data |= RX_AGG_DISABLE; 4146 4147 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4148 4149 rtl_tally_reset(tp); 4150 4151 switch (tp->udev->speed) { 4152 case USB_SPEED_SUPER: 4153 case USB_SPEED_SUPER_PLUS: 4154 tp->coalesce = COALESCE_SUPER; 4155 break; 4156 case USB_SPEED_HIGH: 4157 tp->coalesce = COALESCE_HIGH; 4158 break; 4159 default: 4160 tp->coalesce = COALESCE_SLOW; 4161 break; 4162 } 4163 } 4164 4165 static void r8153b_init(struct r8152 *tp) 4166 { 4167 u32 ocp_data; 4168 u16 data; 4169 int i; 4170 4171 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4172 return; 4173 4174 r8153b_u1u2en(tp, false); 4175 4176 for (i = 0; i < 500; i++) { 4177 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4178 AUTOLOAD_DONE) 4179 break; 4180 msleep(20); 4181 } 4182 4183 data = r8153_phy_status(tp, 0); 4184 4185 data = r8152_mdio_read(tp, MII_BMCR); 4186 if (data & BMCR_PDOWN) { 4187 data &= ~BMCR_PDOWN; 4188 r8152_mdio_write(tp, MII_BMCR, data); 4189 } 4190 4191 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4192 4193 r8153_u2p3en(tp, false); 4194 4195 /* MSC timer = 0xfff * 8ms = 32760 ms */ 4196 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 4197 4198 /* U1/U2/L1 idle timer. 500 us */ 4199 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 4200 4201 r8153b_power_cut_en(tp, false); 4202 r8153b_ups_en(tp, false); 4203 r8153b_queue_wake(tp, false); 4204 rtl_runtime_suspend_enable(tp, false); 4205 r8153b_u1u2en(tp, true); 4206 usb_enable_lpm(tp->udev); 4207 4208 /* MAC clock speed down */ 4209 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); 4210 ocp_data |= MAC_CLK_SPDWN_EN; 4211 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); 4212 4213 set_bit(GREEN_ETHERNET, &tp->flags); 4214 4215 /* rx aggregation */ 4216 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4217 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4218 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4219 4220 rtl_tally_reset(tp); 4221 4222 tp->coalesce = 15000; /* 15 us */ 4223 } 4224 4225 static int rtl8152_pre_reset(struct usb_interface *intf) 4226 { 4227 struct r8152 *tp = usb_get_intfdata(intf); 4228 struct net_device *netdev; 4229 4230 if (!tp) 4231 return 0; 4232 4233 netdev = tp->netdev; 4234 if (!netif_running(netdev)) 4235 return 0; 4236 4237 netif_stop_queue(netdev); 4238 napi_disable(&tp->napi); 4239 clear_bit(WORK_ENABLE, &tp->flags); 4240 usb_kill_urb(tp->intr_urb); 4241 cancel_delayed_work_sync(&tp->schedule); 4242 if (netif_carrier_ok(netdev)) { 4243 mutex_lock(&tp->control); 4244 tp->rtl_ops.disable(tp); 4245 mutex_unlock(&tp->control); 4246 } 4247 4248 return 0; 4249 } 4250 4251 static int rtl8152_post_reset(struct usb_interface *intf) 4252 { 4253 struct r8152 *tp = usb_get_intfdata(intf); 4254 struct net_device *netdev; 4255 4256 if (!tp) 4257 return 0; 4258 4259 netdev = tp->netdev; 4260 if (!netif_running(netdev)) 4261 return 0; 4262 4263 set_bit(WORK_ENABLE, &tp->flags); 4264 if (netif_carrier_ok(netdev)) { 4265 mutex_lock(&tp->control); 4266 tp->rtl_ops.enable(tp); 4267 rtl_start_rx(tp); 4268 _rtl8152_set_rx_mode(netdev); 4269 mutex_unlock(&tp->control); 4270 } 4271 4272 napi_enable(&tp->napi); 4273 netif_wake_queue(netdev); 4274 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 4275 4276 if (!list_empty(&tp->rx_done)) 4277 napi_schedule(&tp->napi); 4278 4279 return 0; 4280 } 4281 4282 static bool delay_autosuspend(struct r8152 *tp) 4283 { 4284 bool sw_linking = !!netif_carrier_ok(tp->netdev); 4285 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); 4286 4287 /* This means a linking change occurs and the driver doesn't detect it, 4288 * yet. If the driver has disabled tx/rx and hw is linking on, the 4289 * device wouldn't wake up by receiving any packet. 4290 */ 4291 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) 4292 return true; 4293 4294 /* If the linking down is occurred by nway, the device may miss the 4295 * linking change event. And it wouldn't wake when linking on. 4296 */ 4297 if (!sw_linking && tp->rtl_ops.in_nway(tp)) 4298 return true; 4299 else if (!skb_queue_empty(&tp->tx_queue)) 4300 return true; 4301 else 4302 return false; 4303 } 4304 4305 static int rtl8152_runtime_resume(struct r8152 *tp) 4306 { 4307 struct net_device *netdev = tp->netdev; 4308 4309 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4310 struct napi_struct *napi = &tp->napi; 4311 4312 tp->rtl_ops.autosuspend_en(tp, false); 4313 napi_disable(napi); 4314 set_bit(WORK_ENABLE, &tp->flags); 4315 4316 if (netif_carrier_ok(netdev)) { 4317 if (rtl8152_get_speed(tp) & LINK_STATUS) { 4318 rtl_start_rx(tp); 4319 } else { 4320 netif_carrier_off(netdev); 4321 tp->rtl_ops.disable(tp); 4322 netif_info(tp, link, netdev, "linking down\n"); 4323 } 4324 } 4325 4326 napi_enable(napi); 4327 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4328 smp_mb__after_atomic(); 4329 4330 if (!list_empty(&tp->rx_done)) 4331 napi_schedule(&tp->napi); 4332 4333 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4334 } else { 4335 if (netdev->flags & IFF_UP) 4336 tp->rtl_ops.autosuspend_en(tp, false); 4337 4338 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4339 } 4340 4341 return 0; 4342 } 4343 4344 static int rtl8152_system_resume(struct r8152 *tp) 4345 { 4346 struct net_device *netdev = tp->netdev; 4347 4348 netif_device_attach(netdev); 4349 4350 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4351 tp->rtl_ops.up(tp); 4352 netif_carrier_off(netdev); 4353 set_bit(WORK_ENABLE, &tp->flags); 4354 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4355 } 4356 4357 return 0; 4358 } 4359 4360 static int rtl8152_runtime_suspend(struct r8152 *tp) 4361 { 4362 struct net_device *netdev = tp->netdev; 4363 int ret = 0; 4364 4365 set_bit(SELECTIVE_SUSPEND, &tp->flags); 4366 smp_mb__after_atomic(); 4367 4368 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4369 u32 rcr = 0; 4370 4371 if (netif_carrier_ok(netdev)) { 4372 u32 ocp_data; 4373 4374 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 4375 ocp_data = rcr & ~RCR_ACPT_ALL; 4376 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 4377 rxdy_gated_en(tp, true); 4378 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 4379 PLA_OOB_CTRL); 4380 if (!(ocp_data & RXFIFO_EMPTY)) { 4381 rxdy_gated_en(tp, false); 4382 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4383 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4384 smp_mb__after_atomic(); 4385 ret = -EBUSY; 4386 goto out1; 4387 } 4388 } 4389 4390 clear_bit(WORK_ENABLE, &tp->flags); 4391 usb_kill_urb(tp->intr_urb); 4392 4393 tp->rtl_ops.autosuspend_en(tp, true); 4394 4395 if (netif_carrier_ok(netdev)) { 4396 struct napi_struct *napi = &tp->napi; 4397 4398 napi_disable(napi); 4399 rtl_stop_rx(tp); 4400 rxdy_gated_en(tp, false); 4401 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4402 napi_enable(napi); 4403 } 4404 4405 if (delay_autosuspend(tp)) { 4406 rtl8152_runtime_resume(tp); 4407 ret = -EBUSY; 4408 } 4409 } 4410 4411 out1: 4412 return ret; 4413 } 4414 4415 static int rtl8152_system_suspend(struct r8152 *tp) 4416 { 4417 struct net_device *netdev = tp->netdev; 4418 4419 netif_device_detach(netdev); 4420 4421 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4422 struct napi_struct *napi = &tp->napi; 4423 4424 clear_bit(WORK_ENABLE, &tp->flags); 4425 usb_kill_urb(tp->intr_urb); 4426 napi_disable(napi); 4427 cancel_delayed_work_sync(&tp->schedule); 4428 tp->rtl_ops.down(tp); 4429 napi_enable(napi); 4430 } 4431 4432 return 0; 4433 } 4434 4435 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 4436 { 4437 struct r8152 *tp = usb_get_intfdata(intf); 4438 int ret; 4439 4440 mutex_lock(&tp->control); 4441 4442 if (PMSG_IS_AUTO(message)) 4443 ret = rtl8152_runtime_suspend(tp); 4444 else 4445 ret = rtl8152_system_suspend(tp); 4446 4447 mutex_unlock(&tp->control); 4448 4449 return ret; 4450 } 4451 4452 static int rtl8152_resume(struct usb_interface *intf) 4453 { 4454 struct r8152 *tp = usb_get_intfdata(intf); 4455 int ret; 4456 4457 mutex_lock(&tp->control); 4458 4459 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) 4460 ret = rtl8152_runtime_resume(tp); 4461 else 4462 ret = rtl8152_system_resume(tp); 4463 4464 mutex_unlock(&tp->control); 4465 4466 return ret; 4467 } 4468 4469 static int rtl8152_reset_resume(struct usb_interface *intf) 4470 { 4471 struct r8152 *tp = usb_get_intfdata(intf); 4472 4473 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4474 mutex_lock(&tp->control); 4475 tp->rtl_ops.init(tp); 4476 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 4477 mutex_unlock(&tp->control); 4478 return rtl8152_resume(intf); 4479 } 4480 4481 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4482 { 4483 struct r8152 *tp = netdev_priv(dev); 4484 4485 if (usb_autopm_get_interface(tp->intf) < 0) 4486 return; 4487 4488 if (!rtl_can_wakeup(tp)) { 4489 wol->supported = 0; 4490 wol->wolopts = 0; 4491 } else { 4492 mutex_lock(&tp->control); 4493 wol->supported = WAKE_ANY; 4494 wol->wolopts = __rtl_get_wol(tp); 4495 mutex_unlock(&tp->control); 4496 } 4497 4498 usb_autopm_put_interface(tp->intf); 4499 } 4500 4501 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4502 { 4503 struct r8152 *tp = netdev_priv(dev); 4504 int ret; 4505 4506 if (!rtl_can_wakeup(tp)) 4507 return -EOPNOTSUPP; 4508 4509 if (wol->wolopts & ~WAKE_ANY) 4510 return -EINVAL; 4511 4512 ret = usb_autopm_get_interface(tp->intf); 4513 if (ret < 0) 4514 goto out_set_wol; 4515 4516 mutex_lock(&tp->control); 4517 4518 __rtl_set_wol(tp, wol->wolopts); 4519 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 4520 4521 mutex_unlock(&tp->control); 4522 4523 usb_autopm_put_interface(tp->intf); 4524 4525 out_set_wol: 4526 return ret; 4527 } 4528 4529 static u32 rtl8152_get_msglevel(struct net_device *dev) 4530 { 4531 struct r8152 *tp = netdev_priv(dev); 4532 4533 return tp->msg_enable; 4534 } 4535 4536 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 4537 { 4538 struct r8152 *tp = netdev_priv(dev); 4539 4540 tp->msg_enable = value; 4541 } 4542 4543 static void rtl8152_get_drvinfo(struct net_device *netdev, 4544 struct ethtool_drvinfo *info) 4545 { 4546 struct r8152 *tp = netdev_priv(netdev); 4547 4548 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 4549 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 4550 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 4551 } 4552 4553 static 4554 int rtl8152_get_link_ksettings(struct net_device *netdev, 4555 struct ethtool_link_ksettings *cmd) 4556 { 4557 struct r8152 *tp = netdev_priv(netdev); 4558 int ret; 4559 4560 if (!tp->mii.mdio_read) 4561 return -EOPNOTSUPP; 4562 4563 ret = usb_autopm_get_interface(tp->intf); 4564 if (ret < 0) 4565 goto out; 4566 4567 mutex_lock(&tp->control); 4568 4569 mii_ethtool_get_link_ksettings(&tp->mii, cmd); 4570 4571 mutex_unlock(&tp->control); 4572 4573 usb_autopm_put_interface(tp->intf); 4574 4575 out: 4576 return ret; 4577 } 4578 4579 static int rtl8152_set_link_ksettings(struct net_device *dev, 4580 const struct ethtool_link_ksettings *cmd) 4581 { 4582 struct r8152 *tp = netdev_priv(dev); 4583 int ret; 4584 4585 ret = usb_autopm_get_interface(tp->intf); 4586 if (ret < 0) 4587 goto out; 4588 4589 mutex_lock(&tp->control); 4590 4591 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, 4592 cmd->base.duplex); 4593 if (!ret) { 4594 tp->autoneg = cmd->base.autoneg; 4595 tp->speed = cmd->base.speed; 4596 tp->duplex = cmd->base.duplex; 4597 } 4598 4599 mutex_unlock(&tp->control); 4600 4601 usb_autopm_put_interface(tp->intf); 4602 4603 out: 4604 return ret; 4605 } 4606 4607 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 4608 "tx_packets", 4609 "rx_packets", 4610 "tx_errors", 4611 "rx_errors", 4612 "rx_missed", 4613 "align_errors", 4614 "tx_single_collisions", 4615 "tx_multi_collisions", 4616 "rx_unicast", 4617 "rx_broadcast", 4618 "rx_multicast", 4619 "tx_aborted", 4620 "tx_underrun", 4621 }; 4622 4623 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 4624 { 4625 switch (sset) { 4626 case ETH_SS_STATS: 4627 return ARRAY_SIZE(rtl8152_gstrings); 4628 default: 4629 return -EOPNOTSUPP; 4630 } 4631 } 4632 4633 static void rtl8152_get_ethtool_stats(struct net_device *dev, 4634 struct ethtool_stats *stats, u64 *data) 4635 { 4636 struct r8152 *tp = netdev_priv(dev); 4637 struct tally_counter tally; 4638 4639 if (usb_autopm_get_interface(tp->intf) < 0) 4640 return; 4641 4642 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 4643 4644 usb_autopm_put_interface(tp->intf); 4645 4646 data[0] = le64_to_cpu(tally.tx_packets); 4647 data[1] = le64_to_cpu(tally.rx_packets); 4648 data[2] = le64_to_cpu(tally.tx_errors); 4649 data[3] = le32_to_cpu(tally.rx_errors); 4650 data[4] = le16_to_cpu(tally.rx_missed); 4651 data[5] = le16_to_cpu(tally.align_errors); 4652 data[6] = le32_to_cpu(tally.tx_one_collision); 4653 data[7] = le32_to_cpu(tally.tx_multi_collision); 4654 data[8] = le64_to_cpu(tally.rx_unicast); 4655 data[9] = le64_to_cpu(tally.rx_broadcast); 4656 data[10] = le32_to_cpu(tally.rx_multicast); 4657 data[11] = le16_to_cpu(tally.tx_aborted); 4658 data[12] = le16_to_cpu(tally.tx_underrun); 4659 } 4660 4661 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4662 { 4663 switch (stringset) { 4664 case ETH_SS_STATS: 4665 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 4666 break; 4667 } 4668 } 4669 4670 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 4671 { 4672 u32 ocp_data, lp, adv, supported = 0; 4673 u16 val; 4674 4675 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 4676 supported = mmd_eee_cap_to_ethtool_sup_t(val); 4677 4678 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 4679 adv = mmd_eee_adv_to_ethtool_adv_t(val); 4680 4681 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 4682 lp = mmd_eee_adv_to_ethtool_adv_t(val); 4683 4684 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 4685 ocp_data &= EEE_RX_EN | EEE_TX_EN; 4686 4687 eee->eee_enabled = !!ocp_data; 4688 eee->eee_active = !!(supported & adv & lp); 4689 eee->supported = supported; 4690 eee->advertised = adv; 4691 eee->lp_advertised = lp; 4692 4693 return 0; 4694 } 4695 4696 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4697 { 4698 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4699 4700 r8152_eee_en(tp, eee->eee_enabled); 4701 4702 if (!eee->eee_enabled) 4703 val = 0; 4704 4705 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); 4706 4707 return 0; 4708 } 4709 4710 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 4711 { 4712 u32 ocp_data, lp, adv, supported = 0; 4713 u16 val; 4714 4715 val = ocp_reg_read(tp, OCP_EEE_ABLE); 4716 supported = mmd_eee_cap_to_ethtool_sup_t(val); 4717 4718 val = ocp_reg_read(tp, OCP_EEE_ADV); 4719 adv = mmd_eee_adv_to_ethtool_adv_t(val); 4720 4721 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 4722 lp = mmd_eee_adv_to_ethtool_adv_t(val); 4723 4724 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 4725 ocp_data &= EEE_RX_EN | EEE_TX_EN; 4726 4727 eee->eee_enabled = !!ocp_data; 4728 eee->eee_active = !!(supported & adv & lp); 4729 eee->supported = supported; 4730 eee->advertised = adv; 4731 eee->lp_advertised = lp; 4732 4733 return 0; 4734 } 4735 4736 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4737 { 4738 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4739 4740 r8153_eee_en(tp, eee->eee_enabled); 4741 4742 if (!eee->eee_enabled) 4743 val = 0; 4744 4745 ocp_reg_write(tp, OCP_EEE_ADV, val); 4746 4747 return 0; 4748 } 4749 4750 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4751 { 4752 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4753 4754 r8153b_eee_en(tp, eee->eee_enabled); 4755 4756 if (!eee->eee_enabled) 4757 val = 0; 4758 4759 ocp_reg_write(tp, OCP_EEE_ADV, val); 4760 4761 return 0; 4762 } 4763 4764 static int 4765 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) 4766 { 4767 struct r8152 *tp = netdev_priv(net); 4768 int ret; 4769 4770 ret = usb_autopm_get_interface(tp->intf); 4771 if (ret < 0) 4772 goto out; 4773 4774 mutex_lock(&tp->control); 4775 4776 ret = tp->rtl_ops.eee_get(tp, edata); 4777 4778 mutex_unlock(&tp->control); 4779 4780 usb_autopm_put_interface(tp->intf); 4781 4782 out: 4783 return ret; 4784 } 4785 4786 static int 4787 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) 4788 { 4789 struct r8152 *tp = netdev_priv(net); 4790 int ret; 4791 4792 ret = usb_autopm_get_interface(tp->intf); 4793 if (ret < 0) 4794 goto out; 4795 4796 mutex_lock(&tp->control); 4797 4798 ret = tp->rtl_ops.eee_set(tp, edata); 4799 if (!ret) 4800 ret = mii_nway_restart(&tp->mii); 4801 4802 mutex_unlock(&tp->control); 4803 4804 usb_autopm_put_interface(tp->intf); 4805 4806 out: 4807 return ret; 4808 } 4809 4810 static int rtl8152_nway_reset(struct net_device *dev) 4811 { 4812 struct r8152 *tp = netdev_priv(dev); 4813 int ret; 4814 4815 ret = usb_autopm_get_interface(tp->intf); 4816 if (ret < 0) 4817 goto out; 4818 4819 mutex_lock(&tp->control); 4820 4821 ret = mii_nway_restart(&tp->mii); 4822 4823 mutex_unlock(&tp->control); 4824 4825 usb_autopm_put_interface(tp->intf); 4826 4827 out: 4828 return ret; 4829 } 4830 4831 static int rtl8152_get_coalesce(struct net_device *netdev, 4832 struct ethtool_coalesce *coalesce) 4833 { 4834 struct r8152 *tp = netdev_priv(netdev); 4835 4836 switch (tp->version) { 4837 case RTL_VER_01: 4838 case RTL_VER_02: 4839 case RTL_VER_07: 4840 return -EOPNOTSUPP; 4841 default: 4842 break; 4843 } 4844 4845 coalesce->rx_coalesce_usecs = tp->coalesce; 4846 4847 return 0; 4848 } 4849 4850 static int rtl8152_set_coalesce(struct net_device *netdev, 4851 struct ethtool_coalesce *coalesce) 4852 { 4853 struct r8152 *tp = netdev_priv(netdev); 4854 int ret; 4855 4856 switch (tp->version) { 4857 case RTL_VER_01: 4858 case RTL_VER_02: 4859 case RTL_VER_07: 4860 return -EOPNOTSUPP; 4861 default: 4862 break; 4863 } 4864 4865 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) 4866 return -EINVAL; 4867 4868 ret = usb_autopm_get_interface(tp->intf); 4869 if (ret < 0) 4870 return ret; 4871 4872 mutex_lock(&tp->control); 4873 4874 if (tp->coalesce != coalesce->rx_coalesce_usecs) { 4875 tp->coalesce = coalesce->rx_coalesce_usecs; 4876 4877 if (netif_running(tp->netdev) && netif_carrier_ok(netdev)) 4878 r8153_set_rx_early_timeout(tp); 4879 } 4880 4881 mutex_unlock(&tp->control); 4882 4883 usb_autopm_put_interface(tp->intf); 4884 4885 return ret; 4886 } 4887 4888 static const struct ethtool_ops ops = { 4889 .get_drvinfo = rtl8152_get_drvinfo, 4890 .get_link = ethtool_op_get_link, 4891 .nway_reset = rtl8152_nway_reset, 4892 .get_msglevel = rtl8152_get_msglevel, 4893 .set_msglevel = rtl8152_set_msglevel, 4894 .get_wol = rtl8152_get_wol, 4895 .set_wol = rtl8152_set_wol, 4896 .get_strings = rtl8152_get_strings, 4897 .get_sset_count = rtl8152_get_sset_count, 4898 .get_ethtool_stats = rtl8152_get_ethtool_stats, 4899 .get_coalesce = rtl8152_get_coalesce, 4900 .set_coalesce = rtl8152_set_coalesce, 4901 .get_eee = rtl_ethtool_get_eee, 4902 .set_eee = rtl_ethtool_set_eee, 4903 .get_link_ksettings = rtl8152_get_link_ksettings, 4904 .set_link_ksettings = rtl8152_set_link_ksettings, 4905 }; 4906 4907 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 4908 { 4909 struct r8152 *tp = netdev_priv(netdev); 4910 struct mii_ioctl_data *data = if_mii(rq); 4911 int res; 4912 4913 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4914 return -ENODEV; 4915 4916 res = usb_autopm_get_interface(tp->intf); 4917 if (res < 0) 4918 goto out; 4919 4920 switch (cmd) { 4921 case SIOCGMIIPHY: 4922 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 4923 break; 4924 4925 case SIOCGMIIREG: 4926 mutex_lock(&tp->control); 4927 data->val_out = r8152_mdio_read(tp, data->reg_num); 4928 mutex_unlock(&tp->control); 4929 break; 4930 4931 case SIOCSMIIREG: 4932 if (!capable(CAP_NET_ADMIN)) { 4933 res = -EPERM; 4934 break; 4935 } 4936 mutex_lock(&tp->control); 4937 r8152_mdio_write(tp, data->reg_num, data->val_in); 4938 mutex_unlock(&tp->control); 4939 break; 4940 4941 default: 4942 res = -EOPNOTSUPP; 4943 } 4944 4945 usb_autopm_put_interface(tp->intf); 4946 4947 out: 4948 return res; 4949 } 4950 4951 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 4952 { 4953 struct r8152 *tp = netdev_priv(dev); 4954 int ret; 4955 4956 switch (tp->version) { 4957 case RTL_VER_01: 4958 case RTL_VER_02: 4959 case RTL_VER_07: 4960 dev->mtu = new_mtu; 4961 return 0; 4962 default: 4963 break; 4964 } 4965 4966 ret = usb_autopm_get_interface(tp->intf); 4967 if (ret < 0) 4968 return ret; 4969 4970 mutex_lock(&tp->control); 4971 4972 dev->mtu = new_mtu; 4973 4974 if (netif_running(dev)) { 4975 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 4976 4977 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms); 4978 4979 if (netif_carrier_ok(dev)) 4980 r8153_set_rx_early_size(tp); 4981 } 4982 4983 mutex_unlock(&tp->control); 4984 4985 usb_autopm_put_interface(tp->intf); 4986 4987 return ret; 4988 } 4989 4990 static const struct net_device_ops rtl8152_netdev_ops = { 4991 .ndo_open = rtl8152_open, 4992 .ndo_stop = rtl8152_close, 4993 .ndo_do_ioctl = rtl8152_ioctl, 4994 .ndo_start_xmit = rtl8152_start_xmit, 4995 .ndo_tx_timeout = rtl8152_tx_timeout, 4996 .ndo_set_features = rtl8152_set_features, 4997 .ndo_set_rx_mode = rtl8152_set_rx_mode, 4998 .ndo_set_mac_address = rtl8152_set_mac_address, 4999 .ndo_change_mtu = rtl8152_change_mtu, 5000 .ndo_validate_addr = eth_validate_addr, 5001 .ndo_features_check = rtl8152_features_check, 5002 }; 5003 5004 static void rtl8152_unload(struct r8152 *tp) 5005 { 5006 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5007 return; 5008 5009 if (tp->version != RTL_VER_01) 5010 r8152_power_cut_en(tp, true); 5011 } 5012 5013 static void rtl8153_unload(struct r8152 *tp) 5014 { 5015 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5016 return; 5017 5018 r8153_power_cut_en(tp, false); 5019 } 5020 5021 static void rtl8153b_unload(struct r8152 *tp) 5022 { 5023 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5024 return; 5025 5026 r8153b_power_cut_en(tp, false); 5027 } 5028 5029 static int rtl_ops_init(struct r8152 *tp) 5030 { 5031 struct rtl_ops *ops = &tp->rtl_ops; 5032 int ret = 0; 5033 5034 switch (tp->version) { 5035 case RTL_VER_01: 5036 case RTL_VER_02: 5037 case RTL_VER_07: 5038 ops->init = r8152b_init; 5039 ops->enable = rtl8152_enable; 5040 ops->disable = rtl8152_disable; 5041 ops->up = rtl8152_up; 5042 ops->down = rtl8152_down; 5043 ops->unload = rtl8152_unload; 5044 ops->eee_get = r8152_get_eee; 5045 ops->eee_set = r8152_set_eee; 5046 ops->in_nway = rtl8152_in_nway; 5047 ops->hw_phy_cfg = r8152b_hw_phy_cfg; 5048 ops->autosuspend_en = rtl_runtime_suspend_enable; 5049 break; 5050 5051 case RTL_VER_03: 5052 case RTL_VER_04: 5053 case RTL_VER_05: 5054 case RTL_VER_06: 5055 ops->init = r8153_init; 5056 ops->enable = rtl8153_enable; 5057 ops->disable = rtl8153_disable; 5058 ops->up = rtl8153_up; 5059 ops->down = rtl8153_down; 5060 ops->unload = rtl8153_unload; 5061 ops->eee_get = r8153_get_eee; 5062 ops->eee_set = r8153_set_eee; 5063 ops->in_nway = rtl8153_in_nway; 5064 ops->hw_phy_cfg = r8153_hw_phy_cfg; 5065 ops->autosuspend_en = rtl8153_runtime_enable; 5066 break; 5067 5068 case RTL_VER_08: 5069 case RTL_VER_09: 5070 ops->init = r8153b_init; 5071 ops->enable = rtl8153_enable; 5072 ops->disable = rtl8153b_disable; 5073 ops->up = rtl8153b_up; 5074 ops->down = rtl8153b_down; 5075 ops->unload = rtl8153b_unload; 5076 ops->eee_get = r8153_get_eee; 5077 ops->eee_set = r8153b_set_eee; 5078 ops->in_nway = rtl8153_in_nway; 5079 ops->hw_phy_cfg = r8153b_hw_phy_cfg; 5080 ops->autosuspend_en = rtl8153b_runtime_enable; 5081 break; 5082 5083 default: 5084 ret = -ENODEV; 5085 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 5086 break; 5087 } 5088 5089 return ret; 5090 } 5091 5092 static u8 rtl_get_version(struct usb_interface *intf) 5093 { 5094 struct usb_device *udev = interface_to_usbdev(intf); 5095 u32 ocp_data = 0; 5096 __le32 *tmp; 5097 u8 version; 5098 int ret; 5099 5100 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); 5101 if (!tmp) 5102 return 0; 5103 5104 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 5105 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 5106 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500); 5107 if (ret > 0) 5108 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK; 5109 5110 kfree(tmp); 5111 5112 switch (ocp_data) { 5113 case 0x4c00: 5114 version = RTL_VER_01; 5115 break; 5116 case 0x4c10: 5117 version = RTL_VER_02; 5118 break; 5119 case 0x5c00: 5120 version = RTL_VER_03; 5121 break; 5122 case 0x5c10: 5123 version = RTL_VER_04; 5124 break; 5125 case 0x5c20: 5126 version = RTL_VER_05; 5127 break; 5128 case 0x5c30: 5129 version = RTL_VER_06; 5130 break; 5131 case 0x4800: 5132 version = RTL_VER_07; 5133 break; 5134 case 0x6000: 5135 version = RTL_VER_08; 5136 break; 5137 case 0x6010: 5138 version = RTL_VER_09; 5139 break; 5140 default: 5141 version = RTL_VER_UNKNOWN; 5142 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); 5143 break; 5144 } 5145 5146 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); 5147 5148 return version; 5149 } 5150 5151 static int rtl8152_probe(struct usb_interface *intf, 5152 const struct usb_device_id *id) 5153 { 5154 struct usb_device *udev = interface_to_usbdev(intf); 5155 u8 version = rtl_get_version(intf); 5156 struct r8152 *tp; 5157 struct net_device *netdev; 5158 int ret; 5159 5160 if (version == RTL_VER_UNKNOWN) 5161 return -ENODEV; 5162 5163 if (udev->actconfig->desc.bConfigurationValue != 1) { 5164 usb_driver_set_configuration(udev, 1); 5165 return -ENODEV; 5166 } 5167 5168 usb_reset_device(udev); 5169 netdev = alloc_etherdev(sizeof(struct r8152)); 5170 if (!netdev) { 5171 dev_err(&intf->dev, "Out of memory\n"); 5172 return -ENOMEM; 5173 } 5174 5175 SET_NETDEV_DEV(netdev, &intf->dev); 5176 tp = netdev_priv(netdev); 5177 tp->msg_enable = 0x7FFF; 5178 5179 tp->udev = udev; 5180 tp->netdev = netdev; 5181 tp->intf = intf; 5182 tp->version = version; 5183 5184 switch (version) { 5185 case RTL_VER_01: 5186 case RTL_VER_02: 5187 case RTL_VER_07: 5188 tp->mii.supports_gmii = 0; 5189 break; 5190 default: 5191 tp->mii.supports_gmii = 1; 5192 break; 5193 } 5194 5195 ret = rtl_ops_init(tp); 5196 if (ret) 5197 goto out; 5198 5199 mutex_init(&tp->control); 5200 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 5201 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); 5202 5203 netdev->netdev_ops = &rtl8152_netdev_ops; 5204 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 5205 5206 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5207 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 5208 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 5209 NETIF_F_HW_VLAN_CTAG_TX; 5210 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5211 NETIF_F_TSO | NETIF_F_FRAGLIST | 5212 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 5213 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; 5214 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 5215 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 5216 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 5217 5218 if (tp->version == RTL_VER_01) { 5219 netdev->features &= ~NETIF_F_RXCSUM; 5220 netdev->hw_features &= ~NETIF_F_RXCSUM; 5221 } 5222 5223 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial && 5224 (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) { 5225 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation"); 5226 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags); 5227 } 5228 5229 netdev->ethtool_ops = &ops; 5230 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 5231 5232 /* MTU range: 68 - 1500 or 9194 */ 5233 netdev->min_mtu = ETH_MIN_MTU; 5234 switch (tp->version) { 5235 case RTL_VER_01: 5236 case RTL_VER_02: 5237 netdev->max_mtu = ETH_DATA_LEN; 5238 break; 5239 default: 5240 netdev->max_mtu = RTL8153_MAX_MTU; 5241 break; 5242 } 5243 5244 tp->mii.dev = netdev; 5245 tp->mii.mdio_read = read_mii_word; 5246 tp->mii.mdio_write = write_mii_word; 5247 tp->mii.phy_id_mask = 0x3f; 5248 tp->mii.reg_num_mask = 0x1f; 5249 tp->mii.phy_id = R8152_PHY_ID; 5250 5251 tp->autoneg = AUTONEG_ENABLE; 5252 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100; 5253 tp->duplex = DUPLEX_FULL; 5254 5255 intf->needs_remote_wakeup = 1; 5256 5257 tp->rtl_ops.init(tp); 5258 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 5259 set_ethernet_addr(tp); 5260 5261 usb_set_intfdata(intf, tp); 5262 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); 5263 5264 ret = register_netdev(netdev); 5265 if (ret != 0) { 5266 netif_err(tp, probe, netdev, "couldn't register the device\n"); 5267 goto out1; 5268 } 5269 5270 if (!rtl_can_wakeup(tp)) 5271 __rtl_set_wol(tp, 0); 5272 5273 tp->saved_wolopts = __rtl_get_wol(tp); 5274 if (tp->saved_wolopts) 5275 device_set_wakeup_enable(&udev->dev, true); 5276 else 5277 device_set_wakeup_enable(&udev->dev, false); 5278 5279 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 5280 5281 return 0; 5282 5283 out1: 5284 netif_napi_del(&tp->napi); 5285 usb_set_intfdata(intf, NULL); 5286 out: 5287 free_netdev(netdev); 5288 return ret; 5289 } 5290 5291 static void rtl8152_disconnect(struct usb_interface *intf) 5292 { 5293 struct r8152 *tp = usb_get_intfdata(intf); 5294 5295 usb_set_intfdata(intf, NULL); 5296 if (tp) { 5297 struct usb_device *udev = tp->udev; 5298 5299 if (udev->state == USB_STATE_NOTATTACHED) 5300 set_bit(RTL8152_UNPLUG, &tp->flags); 5301 5302 netif_napi_del(&tp->napi); 5303 unregister_netdev(tp->netdev); 5304 cancel_delayed_work_sync(&tp->hw_phy_work); 5305 tp->rtl_ops.unload(tp); 5306 free_netdev(tp->netdev); 5307 } 5308 } 5309 5310 #define REALTEK_USB_DEVICE(vend, prod) \ 5311 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ 5312 USB_DEVICE_ID_MATCH_INT_CLASS, \ 5313 .idVendor = (vend), \ 5314 .idProduct = (prod), \ 5315 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ 5316 }, \ 5317 { \ 5318 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ 5319 USB_DEVICE_ID_MATCH_DEVICE, \ 5320 .idVendor = (vend), \ 5321 .idProduct = (prod), \ 5322 .bInterfaceClass = USB_CLASS_COMM, \ 5323 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ 5324 .bInterfaceProtocol = USB_CDC_PROTO_NONE 5325 5326 /* table of devices that work with this driver */ 5327 static const struct usb_device_id rtl8152_table[] = { 5328 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)}, 5329 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, 5330 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, 5331 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)}, 5332 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)}, 5333 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, 5334 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, 5335 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)}, 5336 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)}, 5337 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, 5338 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)}, 5339 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)}, 5340 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)}, 5341 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, 5342 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)}, 5343 {} 5344 }; 5345 5346 MODULE_DEVICE_TABLE(usb, rtl8152_table); 5347 5348 static struct usb_driver rtl8152_driver = { 5349 .name = MODULENAME, 5350 .id_table = rtl8152_table, 5351 .probe = rtl8152_probe, 5352 .disconnect = rtl8152_disconnect, 5353 .suspend = rtl8152_suspend, 5354 .resume = rtl8152_resume, 5355 .reset_resume = rtl8152_reset_resume, 5356 .pre_reset = rtl8152_pre_reset, 5357 .post_reset = rtl8152_post_reset, 5358 .supports_autosuspend = 1, 5359 .disable_hub_initiated_lpm = 1, 5360 }; 5361 5362 module_usb_driver(rtl8152_driver); 5363 5364 MODULE_AUTHOR(DRIVER_AUTHOR); 5365 MODULE_DESCRIPTION(DRIVER_DESC); 5366 MODULE_LICENSE("GPL"); 5367 MODULE_VERSION(DRIVER_VERSION); 5368