1 /* 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2 as published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/signal.h> 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/usb.h> 18 #include <linux/crc32.h> 19 #include <linux/if_vlan.h> 20 #include <linux/uaccess.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include <net/ip6_checksum.h> 25 #include <uapi/linux/mdio.h> 26 #include <linux/mdio.h> 27 #include <linux/usb/cdc.h> 28 #include <linux/suspend.h> 29 #include <linux/acpi.h> 30 31 /* Information for net-next */ 32 #define NETNEXT_VERSION "08" 33 34 /* Information for net */ 35 #define NET_VERSION "9" 36 37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION 38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 40 #define MODULENAME "r8152" 41 42 #define R8152_PHY_ID 32 43 44 #define PLA_IDR 0xc000 45 #define PLA_RCR 0xc010 46 #define PLA_RMS 0xc016 47 #define PLA_RXFIFO_CTRL0 0xc0a0 48 #define PLA_RXFIFO_CTRL1 0xc0a4 49 #define PLA_RXFIFO_CTRL2 0xc0a8 50 #define PLA_DMY_REG0 0xc0b0 51 #define PLA_FMC 0xc0b4 52 #define PLA_CFG_WOL 0xc0b6 53 #define PLA_TEREDO_CFG 0xc0bc 54 #define PLA_MAR 0xcd00 55 #define PLA_BACKUP 0xd000 56 #define PAL_BDC_CR 0xd1a0 57 #define PLA_TEREDO_TIMER 0xd2cc 58 #define PLA_REALWOW_TIMER 0xd2e8 59 #define PLA_LEDSEL 0xdd90 60 #define PLA_LED_FEATURE 0xdd92 61 #define PLA_PHYAR 0xde00 62 #define PLA_BOOT_CTRL 0xe004 63 #define PLA_GPHY_INTR_IMR 0xe022 64 #define PLA_EEE_CR 0xe040 65 #define PLA_EEEP_CR 0xe080 66 #define PLA_MAC_PWR_CTRL 0xe0c0 67 #define PLA_MAC_PWR_CTRL2 0xe0ca 68 #define PLA_MAC_PWR_CTRL3 0xe0cc 69 #define PLA_MAC_PWR_CTRL4 0xe0ce 70 #define PLA_WDT6_CTRL 0xe428 71 #define PLA_TCR0 0xe610 72 #define PLA_TCR1 0xe612 73 #define PLA_MTPS 0xe615 74 #define PLA_TXFIFO_CTRL 0xe618 75 #define PLA_RSTTALLY 0xe800 76 #define PLA_CR 0xe813 77 #define PLA_CRWECR 0xe81c 78 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 79 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 80 #define PLA_CONFIG5 0xe822 81 #define PLA_PHY_PWR 0xe84c 82 #define PLA_OOB_CTRL 0xe84f 83 #define PLA_CPCR 0xe854 84 #define PLA_MISC_0 0xe858 85 #define PLA_MISC_1 0xe85a 86 #define PLA_OCP_GPHY_BASE 0xe86c 87 #define PLA_TALLYCNT 0xe890 88 #define PLA_SFF_STS_7 0xe8de 89 #define PLA_PHYSTATUS 0xe908 90 #define PLA_BP_BA 0xfc26 91 #define PLA_BP_0 0xfc28 92 #define PLA_BP_1 0xfc2a 93 #define PLA_BP_2 0xfc2c 94 #define PLA_BP_3 0xfc2e 95 #define PLA_BP_4 0xfc30 96 #define PLA_BP_5 0xfc32 97 #define PLA_BP_6 0xfc34 98 #define PLA_BP_7 0xfc36 99 #define PLA_BP_EN 0xfc38 100 101 #define USB_USB2PHY 0xb41e 102 #define USB_SSPHYLINK2 0xb428 103 #define USB_U2P3_CTRL 0xb460 104 #define USB_CSR_DUMMY1 0xb464 105 #define USB_CSR_DUMMY2 0xb466 106 #define USB_DEV_STAT 0xb808 107 #define USB_CONNECT_TIMER 0xcbf8 108 #define USB_BURST_SIZE 0xcfc0 109 #define USB_USB_CTRL 0xd406 110 #define USB_PHY_CTRL 0xd408 111 #define USB_TX_AGG 0xd40a 112 #define USB_RX_BUF_TH 0xd40c 113 #define USB_USB_TIMER 0xd428 114 #define USB_RX_EARLY_TIMEOUT 0xd42c 115 #define USB_RX_EARLY_SIZE 0xd42e 116 #define USB_PM_CTRL_STATUS 0xd432 117 #define USB_TX_DMA 0xd434 118 #define USB_TOLERANCE 0xd490 119 #define USB_LPM_CTRL 0xd41a 120 #define USB_BMU_RESET 0xd4b0 121 #define USB_UPS_CTRL 0xd800 122 #define USB_MISC_0 0xd81a 123 #define USB_POWER_CUT 0xd80a 124 #define USB_AFE_CTRL2 0xd824 125 #define USB_WDT11_CTRL 0xe43c 126 #define USB_BP_BA 0xfc26 127 #define USB_BP_0 0xfc28 128 #define USB_BP_1 0xfc2a 129 #define USB_BP_2 0xfc2c 130 #define USB_BP_3 0xfc2e 131 #define USB_BP_4 0xfc30 132 #define USB_BP_5 0xfc32 133 #define USB_BP_6 0xfc34 134 #define USB_BP_7 0xfc36 135 #define USB_BP_EN 0xfc38 136 137 /* OCP Registers */ 138 #define OCP_ALDPS_CONFIG 0x2010 139 #define OCP_EEE_CONFIG1 0x2080 140 #define OCP_EEE_CONFIG2 0x2092 141 #define OCP_EEE_CONFIG3 0x2094 142 #define OCP_BASE_MII 0xa400 143 #define OCP_EEE_AR 0xa41a 144 #define OCP_EEE_DATA 0xa41c 145 #define OCP_PHY_STATUS 0xa420 146 #define OCP_POWER_CFG 0xa430 147 #define OCP_EEE_CFG 0xa432 148 #define OCP_SRAM_ADDR 0xa436 149 #define OCP_SRAM_DATA 0xa438 150 #define OCP_DOWN_SPEED 0xa442 151 #define OCP_EEE_ABLE 0xa5c4 152 #define OCP_EEE_ADV 0xa5d0 153 #define OCP_EEE_LPABLE 0xa5d2 154 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ 155 #define OCP_ADC_CFG 0xbc06 156 157 /* SRAM Register */ 158 #define SRAM_LPF_CFG 0x8012 159 #define SRAM_10M_AMP1 0x8080 160 #define SRAM_10M_AMP2 0x8082 161 #define SRAM_IMPEDANCE 0x8084 162 163 /* PLA_RCR */ 164 #define RCR_AAP 0x00000001 165 #define RCR_APM 0x00000002 166 #define RCR_AM 0x00000004 167 #define RCR_AB 0x00000008 168 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 169 170 /* PLA_RXFIFO_CTRL0 */ 171 #define RXFIFO_THR1_NORMAL 0x00080002 172 #define RXFIFO_THR1_OOB 0x01800003 173 174 /* PLA_RXFIFO_CTRL1 */ 175 #define RXFIFO_THR2_FULL 0x00000060 176 #define RXFIFO_THR2_HIGH 0x00000038 177 #define RXFIFO_THR2_OOB 0x0000004a 178 #define RXFIFO_THR2_NORMAL 0x00a0 179 180 /* PLA_RXFIFO_CTRL2 */ 181 #define RXFIFO_THR3_FULL 0x00000078 182 #define RXFIFO_THR3_HIGH 0x00000048 183 #define RXFIFO_THR3_OOB 0x0000005a 184 #define RXFIFO_THR3_NORMAL 0x0110 185 186 /* PLA_TXFIFO_CTRL */ 187 #define TXFIFO_THR_NORMAL 0x00400008 188 #define TXFIFO_THR_NORMAL2 0x01000008 189 190 /* PLA_DMY_REG0 */ 191 #define ECM_ALDPS 0x0002 192 193 /* PLA_FMC */ 194 #define FMC_FCR_MCU_EN 0x0001 195 196 /* PLA_EEEP_CR */ 197 #define EEEP_CR_EEEP_TX 0x0002 198 199 /* PLA_WDT6_CTRL */ 200 #define WDT6_SET_MODE 0x0010 201 202 /* PLA_TCR0 */ 203 #define TCR0_TX_EMPTY 0x0800 204 #define TCR0_AUTO_FIFO 0x0080 205 206 /* PLA_TCR1 */ 207 #define VERSION_MASK 0x7cf0 208 209 /* PLA_MTPS */ 210 #define MTPS_JUMBO (12 * 1024 / 64) 211 #define MTPS_DEFAULT (6 * 1024 / 64) 212 213 /* PLA_RSTTALLY */ 214 #define TALLY_RESET 0x0001 215 216 /* PLA_CR */ 217 #define CR_RST 0x10 218 #define CR_RE 0x08 219 #define CR_TE 0x04 220 221 /* PLA_CRWECR */ 222 #define CRWECR_NORAML 0x00 223 #define CRWECR_CONFIG 0xc0 224 225 /* PLA_OOB_CTRL */ 226 #define NOW_IS_OOB 0x80 227 #define TXFIFO_EMPTY 0x20 228 #define RXFIFO_EMPTY 0x10 229 #define LINK_LIST_READY 0x02 230 #define DIS_MCU_CLROOB 0x01 231 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 232 233 /* PLA_MISC_1 */ 234 #define RXDY_GATED_EN 0x0008 235 236 /* PLA_SFF_STS_7 */ 237 #define RE_INIT_LL 0x8000 238 #define MCU_BORW_EN 0x4000 239 240 /* PLA_CPCR */ 241 #define CPCR_RX_VLAN 0x0040 242 243 /* PLA_CFG_WOL */ 244 #define MAGIC_EN 0x0001 245 246 /* PLA_TEREDO_CFG */ 247 #define TEREDO_SEL 0x8000 248 #define TEREDO_WAKE_MASK 0x7f00 249 #define TEREDO_RS_EVENT_MASK 0x00fe 250 #define OOB_TEREDO_EN 0x0001 251 252 /* PAL_BDC_CR */ 253 #define ALDPS_PROXY_MODE 0x0001 254 255 /* PLA_CONFIG34 */ 256 #define LINK_ON_WAKE_EN 0x0010 257 #define LINK_OFF_WAKE_EN 0x0008 258 259 /* PLA_CONFIG5 */ 260 #define BWF_EN 0x0040 261 #define MWF_EN 0x0020 262 #define UWF_EN 0x0010 263 #define LAN_WAKE_EN 0x0002 264 265 /* PLA_LED_FEATURE */ 266 #define LED_MODE_MASK 0x0700 267 268 /* PLA_PHY_PWR */ 269 #define TX_10M_IDLE_EN 0x0080 270 #define PFM_PWM_SWITCH 0x0040 271 272 /* PLA_MAC_PWR_CTRL */ 273 #define D3_CLK_GATED_EN 0x00004000 274 #define MCU_CLK_RATIO 0x07010f07 275 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 276 #define ALDPS_SPDWN_RATIO 0x0f87 277 278 /* PLA_MAC_PWR_CTRL2 */ 279 #define EEE_SPDWN_RATIO 0x8007 280 281 /* PLA_MAC_PWR_CTRL3 */ 282 #define PKT_AVAIL_SPDWN_EN 0x0100 283 #define SUSPEND_SPDWN_EN 0x0004 284 #define U1U2_SPDWN_EN 0x0002 285 #define L1_SPDWN_EN 0x0001 286 287 /* PLA_MAC_PWR_CTRL4 */ 288 #define PWRSAVE_SPDWN_EN 0x1000 289 #define RXDV_SPDWN_EN 0x0800 290 #define TX10MIDLE_EN 0x0100 291 #define TP100_SPDWN_EN 0x0020 292 #define TP500_SPDWN_EN 0x0010 293 #define TP1000_SPDWN_EN 0x0008 294 #define EEE_SPDWN_EN 0x0001 295 296 /* PLA_GPHY_INTR_IMR */ 297 #define GPHY_STS_MSK 0x0001 298 #define SPEED_DOWN_MSK 0x0002 299 #define SPDWN_RXDV_MSK 0x0004 300 #define SPDWN_LINKCHG_MSK 0x0008 301 302 /* PLA_PHYAR */ 303 #define PHYAR_FLAG 0x80000000 304 305 /* PLA_EEE_CR */ 306 #define EEE_RX_EN 0x0001 307 #define EEE_TX_EN 0x0002 308 309 /* PLA_BOOT_CTRL */ 310 #define AUTOLOAD_DONE 0x0002 311 312 /* USB_USB2PHY */ 313 #define USB2PHY_SUSPEND 0x0001 314 #define USB2PHY_L1 0x0002 315 316 /* USB_SSPHYLINK2 */ 317 #define pwd_dn_scale_mask 0x3ffe 318 #define pwd_dn_scale(x) ((x) << 1) 319 320 /* USB_CSR_DUMMY1 */ 321 #define DYNAMIC_BURST 0x0001 322 323 /* USB_CSR_DUMMY2 */ 324 #define EP4_FULL_FC 0x0001 325 326 /* USB_DEV_STAT */ 327 #define STAT_SPEED_MASK 0x0006 328 #define STAT_SPEED_HIGH 0x0000 329 #define STAT_SPEED_FULL 0x0002 330 331 /* USB_TX_AGG */ 332 #define TX_AGG_MAX_THRESHOLD 0x03 333 334 /* USB_RX_BUF_TH */ 335 #define RX_THR_SUPPER 0x0c350180 336 #define RX_THR_HIGH 0x7a120180 337 #define RX_THR_SLOW 0xffff0180 338 339 /* USB_TX_DMA */ 340 #define TEST_MODE_DISABLE 0x00000001 341 #define TX_SIZE_ADJUST1 0x00000100 342 343 /* USB_BMU_RESET */ 344 #define BMU_RESET_EP_IN 0x01 345 #define BMU_RESET_EP_OUT 0x02 346 347 /* USB_UPS_CTRL */ 348 #define POWER_CUT 0x0100 349 350 /* USB_PM_CTRL_STATUS */ 351 #define RESUME_INDICATE 0x0001 352 353 /* USB_USB_CTRL */ 354 #define RX_AGG_DISABLE 0x0010 355 #define RX_ZERO_EN 0x0080 356 357 /* USB_U2P3_CTRL */ 358 #define U2P3_ENABLE 0x0001 359 360 /* USB_POWER_CUT */ 361 #define PWR_EN 0x0001 362 #define PHASE2_EN 0x0008 363 364 /* USB_MISC_0 */ 365 #define PCUT_STATUS 0x0001 366 367 /* USB_RX_EARLY_TIMEOUT */ 368 #define COALESCE_SUPER 85000U 369 #define COALESCE_HIGH 250000U 370 #define COALESCE_SLOW 524280U 371 372 /* USB_WDT11_CTRL */ 373 #define TIMER11_EN 0x0001 374 375 /* USB_LPM_CTRL */ 376 /* bit 4 ~ 5: fifo empty boundary */ 377 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 378 /* bit 2 ~ 3: LMP timer */ 379 #define LPM_TIMER_MASK 0x0c 380 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 381 #define LPM_TIMER_500US 0x0c /* 500 us */ 382 #define ROK_EXIT_LPM 0x02 383 384 /* USB_AFE_CTRL2 */ 385 #define SEN_VAL_MASK 0xf800 386 #define SEN_VAL_NORMAL 0xa000 387 #define SEL_RXIDLE 0x0100 388 389 /* OCP_ALDPS_CONFIG */ 390 #define ENPWRSAVE 0x8000 391 #define ENPDNPS 0x0200 392 #define LINKENA 0x0100 393 #define DIS_SDSAVE 0x0010 394 395 /* OCP_PHY_STATUS */ 396 #define PHY_STAT_MASK 0x0007 397 #define PHY_STAT_LAN_ON 3 398 #define PHY_STAT_PWRDN 5 399 400 /* OCP_POWER_CFG */ 401 #define EEE_CLKDIV_EN 0x8000 402 #define EN_ALDPS 0x0004 403 #define EN_10M_PLLOFF 0x0001 404 405 /* OCP_EEE_CONFIG1 */ 406 #define RG_TXLPI_MSK_HFDUP 0x8000 407 #define RG_MATCLR_EN 0x4000 408 #define EEE_10_CAP 0x2000 409 #define EEE_NWAY_EN 0x1000 410 #define TX_QUIET_EN 0x0200 411 #define RX_QUIET_EN 0x0100 412 #define sd_rise_time_mask 0x0070 413 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 414 #define RG_RXLPI_MSK_HFDUP 0x0008 415 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 416 417 /* OCP_EEE_CONFIG2 */ 418 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 419 #define RG_DACQUIET_EN 0x0400 420 #define RG_LDVQUIET_EN 0x0200 421 #define RG_CKRSEL 0x0020 422 #define RG_EEEPRG_EN 0x0010 423 424 /* OCP_EEE_CONFIG3 */ 425 #define fast_snr_mask 0xff80 426 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 427 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 428 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 429 430 /* OCP_EEE_AR */ 431 /* bit[15:14] function */ 432 #define FUN_ADDR 0x0000 433 #define FUN_DATA 0x4000 434 /* bit[4:0] device addr */ 435 436 /* OCP_EEE_CFG */ 437 #define CTAP_SHORT_EN 0x0040 438 #define EEE10_EN 0x0010 439 440 /* OCP_DOWN_SPEED */ 441 #define EN_10M_BGOFF 0x0080 442 443 /* OCP_PHY_STATE */ 444 #define TXDIS_STATE 0x01 445 #define ABD_STATE 0x02 446 447 /* OCP_ADC_CFG */ 448 #define CKADSEL_L 0x0100 449 #define ADC_EN 0x0080 450 #define EN_EMI_L 0x0040 451 452 /* SRAM_LPF_CFG */ 453 #define LPF_AUTO_TUNE 0x8000 454 455 /* SRAM_10M_AMP1 */ 456 #define GDAC_IB_UPALL 0x0008 457 458 /* SRAM_10M_AMP2 */ 459 #define AMP_DN 0x0200 460 461 /* SRAM_IMPEDANCE */ 462 #define RX_DRIVING_MASK 0x6000 463 464 /* MAC PASSTHRU */ 465 #define AD_MASK 0xfee0 466 #define EFUSE 0xcfdb 467 #define PASS_THRU_MASK 0x1 468 469 enum rtl_register_content { 470 _1000bps = 0x10, 471 _100bps = 0x08, 472 _10bps = 0x04, 473 LINK_STATUS = 0x02, 474 FULL_DUP = 0x01, 475 }; 476 477 #define RTL8152_MAX_TX 4 478 #define RTL8152_MAX_RX 10 479 #define INTBUFSIZE 2 480 #define CRC_SIZE 4 481 #define TX_ALIGN 4 482 #define RX_ALIGN 8 483 484 #define INTR_LINK 0x0004 485 486 #define RTL8152_REQT_READ 0xc0 487 #define RTL8152_REQT_WRITE 0x40 488 #define RTL8152_REQ_GET_REGS 0x05 489 #define RTL8152_REQ_SET_REGS 0x05 490 491 #define BYTE_EN_DWORD 0xff 492 #define BYTE_EN_WORD 0x33 493 #define BYTE_EN_BYTE 0x11 494 #define BYTE_EN_SIX_BYTES 0x3f 495 #define BYTE_EN_START_MASK 0x0f 496 #define BYTE_EN_END_MASK 0xf0 497 498 #define RTL8153_MAX_PACKET 9216 /* 9K */ 499 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN) 500 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) 501 #define RTL8153_RMS RTL8153_MAX_PACKET 502 #define RTL8152_TX_TIMEOUT (5 * HZ) 503 #define RTL8152_NAPI_WEIGHT 64 504 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + CRC_SIZE + \ 505 sizeof(struct rx_desc) + RX_ALIGN) 506 507 /* rtl8152 flags */ 508 enum rtl8152_flags { 509 RTL8152_UNPLUG = 0, 510 RTL8152_SET_RX_MODE, 511 WORK_ENABLE, 512 RTL8152_LINK_CHG, 513 SELECTIVE_SUSPEND, 514 PHY_RESET, 515 SCHEDULE_NAPI, 516 }; 517 518 /* Define these values to match your device */ 519 #define VENDOR_ID_REALTEK 0x0bda 520 #define VENDOR_ID_SAMSUNG 0x04e8 521 #define VENDOR_ID_LENOVO 0x17ef 522 #define VENDOR_ID_NVIDIA 0x0955 523 524 #define MCU_TYPE_PLA 0x0100 525 #define MCU_TYPE_USB 0x0000 526 527 struct tally_counter { 528 __le64 tx_packets; 529 __le64 rx_packets; 530 __le64 tx_errors; 531 __le32 rx_errors; 532 __le16 rx_missed; 533 __le16 align_errors; 534 __le32 tx_one_collision; 535 __le32 tx_multi_collision; 536 __le64 rx_unicast; 537 __le64 rx_broadcast; 538 __le32 rx_multicast; 539 __le16 tx_aborted; 540 __le16 tx_underrun; 541 }; 542 543 struct rx_desc { 544 __le32 opts1; 545 #define RX_LEN_MASK 0x7fff 546 547 __le32 opts2; 548 #define RD_UDP_CS BIT(23) 549 #define RD_TCP_CS BIT(22) 550 #define RD_IPV6_CS BIT(20) 551 #define RD_IPV4_CS BIT(19) 552 553 __le32 opts3; 554 #define IPF BIT(23) /* IP checksum fail */ 555 #define UDPF BIT(22) /* UDP checksum fail */ 556 #define TCPF BIT(21) /* TCP checksum fail */ 557 #define RX_VLAN_TAG BIT(16) 558 559 __le32 opts4; 560 __le32 opts5; 561 __le32 opts6; 562 }; 563 564 struct tx_desc { 565 __le32 opts1; 566 #define TX_FS BIT(31) /* First segment of a packet */ 567 #define TX_LS BIT(30) /* Final segment of a packet */ 568 #define GTSENDV4 BIT(28) 569 #define GTSENDV6 BIT(27) 570 #define GTTCPHO_SHIFT 18 571 #define GTTCPHO_MAX 0x7fU 572 #define TX_LEN_MAX 0x3ffffU 573 574 __le32 opts2; 575 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 576 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 577 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 578 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 579 #define MSS_SHIFT 17 580 #define MSS_MAX 0x7ffU 581 #define TCPHO_SHIFT 17 582 #define TCPHO_MAX 0x7ffU 583 #define TX_VLAN_TAG BIT(16) 584 }; 585 586 struct r8152; 587 588 struct rx_agg { 589 struct list_head list; 590 struct urb *urb; 591 struct r8152 *context; 592 void *buffer; 593 void *head; 594 }; 595 596 struct tx_agg { 597 struct list_head list; 598 struct urb *urb; 599 struct r8152 *context; 600 void *buffer; 601 void *head; 602 u32 skb_num; 603 u32 skb_len; 604 }; 605 606 struct r8152 { 607 unsigned long flags; 608 struct usb_device *udev; 609 struct napi_struct napi; 610 struct usb_interface *intf; 611 struct net_device *netdev; 612 struct urb *intr_urb; 613 struct tx_agg tx_info[RTL8152_MAX_TX]; 614 struct rx_agg rx_info[RTL8152_MAX_RX]; 615 struct list_head rx_done, tx_free; 616 struct sk_buff_head tx_queue, rx_queue; 617 spinlock_t rx_lock, tx_lock; 618 struct delayed_work schedule, hw_phy_work; 619 struct mii_if_info mii; 620 struct mutex control; /* use for hw setting */ 621 #ifdef CONFIG_PM_SLEEP 622 struct notifier_block pm_notifier; 623 #endif 624 625 struct rtl_ops { 626 void (*init)(struct r8152 *); 627 int (*enable)(struct r8152 *); 628 void (*disable)(struct r8152 *); 629 void (*up)(struct r8152 *); 630 void (*down)(struct r8152 *); 631 void (*unload)(struct r8152 *); 632 int (*eee_get)(struct r8152 *, struct ethtool_eee *); 633 int (*eee_set)(struct r8152 *, struct ethtool_eee *); 634 bool (*in_nway)(struct r8152 *); 635 void (*hw_phy_cfg)(struct r8152 *); 636 void (*autosuspend_en)(struct r8152 *tp, bool enable); 637 } rtl_ops; 638 639 int intr_interval; 640 u32 saved_wolopts; 641 u32 msg_enable; 642 u32 tx_qlen; 643 u32 coalesce; 644 u16 ocp_base; 645 u16 speed; 646 u8 *intr_buff; 647 u8 version; 648 u8 duplex; 649 u8 autoneg; 650 }; 651 652 enum rtl_version { 653 RTL_VER_UNKNOWN = 0, 654 RTL_VER_01, 655 RTL_VER_02, 656 RTL_VER_03, 657 RTL_VER_04, 658 RTL_VER_05, 659 RTL_VER_06, 660 RTL_VER_MAX 661 }; 662 663 enum tx_csum_stat { 664 TX_CSUM_SUCCESS = 0, 665 TX_CSUM_TSO, 666 TX_CSUM_NONE 667 }; 668 669 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 670 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 671 */ 672 static const int multicast_filter_limit = 32; 673 static unsigned int agg_buf_sz = 16384; 674 675 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ 676 VLAN_ETH_HLEN - VLAN_HLEN) 677 678 static 679 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 680 { 681 int ret; 682 void *tmp; 683 684 tmp = kmalloc(size, GFP_KERNEL); 685 if (!tmp) 686 return -ENOMEM; 687 688 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 689 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 690 value, index, tmp, size, 500); 691 692 memcpy(data, tmp, size); 693 kfree(tmp); 694 695 return ret; 696 } 697 698 static 699 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 700 { 701 int ret; 702 void *tmp; 703 704 tmp = kmemdup(data, size, GFP_KERNEL); 705 if (!tmp) 706 return -ENOMEM; 707 708 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 709 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 710 value, index, tmp, size, 500); 711 712 kfree(tmp); 713 714 return ret; 715 } 716 717 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 718 void *data, u16 type) 719 { 720 u16 limit = 64; 721 int ret = 0; 722 723 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 724 return -ENODEV; 725 726 /* both size and indix must be 4 bytes align */ 727 if ((size & 3) || !size || (index & 3) || !data) 728 return -EPERM; 729 730 if ((u32)index + (u32)size > 0xffff) 731 return -EPERM; 732 733 while (size) { 734 if (size > limit) { 735 ret = get_registers(tp, index, type, limit, data); 736 if (ret < 0) 737 break; 738 739 index += limit; 740 data += limit; 741 size -= limit; 742 } else { 743 ret = get_registers(tp, index, type, size, data); 744 if (ret < 0) 745 break; 746 747 index += size; 748 data += size; 749 size = 0; 750 break; 751 } 752 } 753 754 if (ret == -ENODEV) 755 set_bit(RTL8152_UNPLUG, &tp->flags); 756 757 return ret; 758 } 759 760 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 761 u16 size, void *data, u16 type) 762 { 763 int ret; 764 u16 byteen_start, byteen_end, byen; 765 u16 limit = 512; 766 767 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 768 return -ENODEV; 769 770 /* both size and indix must be 4 bytes align */ 771 if ((size & 3) || !size || (index & 3) || !data) 772 return -EPERM; 773 774 if ((u32)index + (u32)size > 0xffff) 775 return -EPERM; 776 777 byteen_start = byteen & BYTE_EN_START_MASK; 778 byteen_end = byteen & BYTE_EN_END_MASK; 779 780 byen = byteen_start | (byteen_start << 4); 781 ret = set_registers(tp, index, type | byen, 4, data); 782 if (ret < 0) 783 goto error1; 784 785 index += 4; 786 data += 4; 787 size -= 4; 788 789 if (size) { 790 size -= 4; 791 792 while (size) { 793 if (size > limit) { 794 ret = set_registers(tp, index, 795 type | BYTE_EN_DWORD, 796 limit, data); 797 if (ret < 0) 798 goto error1; 799 800 index += limit; 801 data += limit; 802 size -= limit; 803 } else { 804 ret = set_registers(tp, index, 805 type | BYTE_EN_DWORD, 806 size, data); 807 if (ret < 0) 808 goto error1; 809 810 index += size; 811 data += size; 812 size = 0; 813 break; 814 } 815 } 816 817 byen = byteen_end | (byteen_end >> 4); 818 ret = set_registers(tp, index, type | byen, 4, data); 819 if (ret < 0) 820 goto error1; 821 } 822 823 error1: 824 if (ret == -ENODEV) 825 set_bit(RTL8152_UNPLUG, &tp->flags); 826 827 return ret; 828 } 829 830 static inline 831 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 832 { 833 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 834 } 835 836 static inline 837 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 838 { 839 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 840 } 841 842 static inline 843 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 844 { 845 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); 846 } 847 848 static inline 849 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 850 { 851 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 852 } 853 854 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 855 { 856 __le32 data; 857 858 generic_ocp_read(tp, index, sizeof(data), &data, type); 859 860 return __le32_to_cpu(data); 861 } 862 863 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 864 { 865 __le32 tmp = __cpu_to_le32(data); 866 867 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 868 } 869 870 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 871 { 872 u32 data; 873 __le32 tmp; 874 u8 shift = index & 2; 875 876 index &= ~3; 877 878 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 879 880 data = __le32_to_cpu(tmp); 881 data >>= (shift * 8); 882 data &= 0xffff; 883 884 return (u16)data; 885 } 886 887 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 888 { 889 u32 mask = 0xffff; 890 __le32 tmp; 891 u16 byen = BYTE_EN_WORD; 892 u8 shift = index & 2; 893 894 data &= mask; 895 896 if (index & 2) { 897 byen <<= shift; 898 mask <<= (shift * 8); 899 data <<= (shift * 8); 900 index &= ~3; 901 } 902 903 tmp = __cpu_to_le32(data); 904 905 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 906 } 907 908 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 909 { 910 u32 data; 911 __le32 tmp; 912 u8 shift = index & 3; 913 914 index &= ~3; 915 916 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 917 918 data = __le32_to_cpu(tmp); 919 data >>= (shift * 8); 920 data &= 0xff; 921 922 return (u8)data; 923 } 924 925 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 926 { 927 u32 mask = 0xff; 928 __le32 tmp; 929 u16 byen = BYTE_EN_BYTE; 930 u8 shift = index & 3; 931 932 data &= mask; 933 934 if (index & 3) { 935 byen <<= shift; 936 mask <<= (shift * 8); 937 data <<= (shift * 8); 938 index &= ~3; 939 } 940 941 tmp = __cpu_to_le32(data); 942 943 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 944 } 945 946 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 947 { 948 u16 ocp_base, ocp_index; 949 950 ocp_base = addr & 0xf000; 951 if (ocp_base != tp->ocp_base) { 952 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 953 tp->ocp_base = ocp_base; 954 } 955 956 ocp_index = (addr & 0x0fff) | 0xb000; 957 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 958 } 959 960 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 961 { 962 u16 ocp_base, ocp_index; 963 964 ocp_base = addr & 0xf000; 965 if (ocp_base != tp->ocp_base) { 966 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 967 tp->ocp_base = ocp_base; 968 } 969 970 ocp_index = (addr & 0x0fff) | 0xb000; 971 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 972 } 973 974 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 975 { 976 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 977 } 978 979 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 980 { 981 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 982 } 983 984 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 985 { 986 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 987 ocp_reg_write(tp, OCP_SRAM_DATA, data); 988 } 989 990 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 991 { 992 struct r8152 *tp = netdev_priv(netdev); 993 int ret; 994 995 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 996 return -ENODEV; 997 998 if (phy_id != R8152_PHY_ID) 999 return -EINVAL; 1000 1001 ret = r8152_mdio_read(tp, reg); 1002 1003 return ret; 1004 } 1005 1006 static 1007 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 1008 { 1009 struct r8152 *tp = netdev_priv(netdev); 1010 1011 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1012 return; 1013 1014 if (phy_id != R8152_PHY_ID) 1015 return; 1016 1017 r8152_mdio_write(tp, reg, val); 1018 } 1019 1020 static int 1021 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 1022 1023 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1024 { 1025 struct r8152 *tp = netdev_priv(netdev); 1026 struct sockaddr *addr = p; 1027 int ret = -EADDRNOTAVAIL; 1028 1029 if (!is_valid_ether_addr(addr->sa_data)) 1030 goto out1; 1031 1032 ret = usb_autopm_get_interface(tp->intf); 1033 if (ret < 0) 1034 goto out1; 1035 1036 mutex_lock(&tp->control); 1037 1038 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1039 1040 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1041 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1042 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1043 1044 mutex_unlock(&tp->control); 1045 1046 usb_autopm_put_interface(tp->intf); 1047 out1: 1048 return ret; 1049 } 1050 1051 /* Devices containing RTL8153-AD can support a persistent 1052 * host system provided MAC address. 1053 * Examples of this are Dell TB15 and Dell WD15 docks 1054 */ 1055 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) 1056 { 1057 acpi_status status; 1058 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1059 union acpi_object *obj; 1060 int ret = -EINVAL; 1061 u32 ocp_data; 1062 unsigned char buf[6]; 1063 1064 /* test for -AD variant of RTL8153 */ 1065 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 1066 if ((ocp_data & AD_MASK) != 0x1000) 1067 return -ENODEV; 1068 1069 /* test for MAC address pass-through bit */ 1070 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); 1071 if ((ocp_data & PASS_THRU_MASK) != 1) 1072 return -ENODEV; 1073 1074 /* returns _AUXMAC_#AABBCCDDEEFF# */ 1075 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer); 1076 obj = (union acpi_object *)buffer.pointer; 1077 if (!ACPI_SUCCESS(status)) 1078 return -ENODEV; 1079 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) { 1080 netif_warn(tp, probe, tp->netdev, 1081 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", 1082 obj->type, obj->string.length); 1083 goto amacout; 1084 } 1085 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || 1086 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { 1087 netif_warn(tp, probe, tp->netdev, 1088 "Invalid header when reading pass-thru MAC addr\n"); 1089 goto amacout; 1090 } 1091 ret = hex2bin(buf, obj->string.pointer + 9, 6); 1092 if (!(ret == 0 && is_valid_ether_addr(buf))) { 1093 netif_warn(tp, probe, tp->netdev, 1094 "Invalid MAC for pass-thru MAC addr: %d, %pM\n", 1095 ret, buf); 1096 ret = -EINVAL; 1097 goto amacout; 1098 } 1099 memcpy(sa->sa_data, buf, 6); 1100 ether_addr_copy(tp->netdev->dev_addr, sa->sa_data); 1101 netif_info(tp, probe, tp->netdev, 1102 "Using pass-thru MAC addr %pM\n", sa->sa_data); 1103 1104 amacout: 1105 kfree(obj); 1106 return ret; 1107 } 1108 1109 static int set_ethernet_addr(struct r8152 *tp) 1110 { 1111 struct net_device *dev = tp->netdev; 1112 struct sockaddr sa; 1113 int ret; 1114 1115 if (tp->version == RTL_VER_01) { 1116 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); 1117 } else { 1118 /* if this is not an RTL8153-AD, no eFuse mac pass thru set, 1119 * or system doesn't provide valid _SB.AMAC this will be 1120 * be expected to non-zero 1121 */ 1122 ret = vendor_mac_passthru_addr_read(tp, &sa); 1123 if (ret < 0) 1124 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); 1125 } 1126 1127 if (ret < 0) { 1128 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1129 } else if (!is_valid_ether_addr(sa.sa_data)) { 1130 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1131 sa.sa_data); 1132 eth_hw_addr_random(dev); 1133 ether_addr_copy(sa.sa_data, dev->dev_addr); 1134 ret = rtl8152_set_mac_address(dev, &sa); 1135 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1136 sa.sa_data); 1137 } else { 1138 if (tp->version == RTL_VER_01) 1139 ether_addr_copy(dev->dev_addr, sa.sa_data); 1140 else 1141 ret = rtl8152_set_mac_address(dev, &sa); 1142 } 1143 1144 return ret; 1145 } 1146 1147 static void read_bulk_callback(struct urb *urb) 1148 { 1149 struct net_device *netdev; 1150 int status = urb->status; 1151 struct rx_agg *agg; 1152 struct r8152 *tp; 1153 1154 agg = urb->context; 1155 if (!agg) 1156 return; 1157 1158 tp = agg->context; 1159 if (!tp) 1160 return; 1161 1162 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1163 return; 1164 1165 if (!test_bit(WORK_ENABLE, &tp->flags)) 1166 return; 1167 1168 netdev = tp->netdev; 1169 1170 /* When link down, the driver would cancel all bulks. */ 1171 /* This avoid the re-submitting bulk */ 1172 if (!netif_carrier_ok(netdev)) 1173 return; 1174 1175 usb_mark_last_busy(tp->udev); 1176 1177 switch (status) { 1178 case 0: 1179 if (urb->actual_length < ETH_ZLEN) 1180 break; 1181 1182 spin_lock(&tp->rx_lock); 1183 list_add_tail(&agg->list, &tp->rx_done); 1184 spin_unlock(&tp->rx_lock); 1185 napi_schedule(&tp->napi); 1186 return; 1187 case -ESHUTDOWN: 1188 set_bit(RTL8152_UNPLUG, &tp->flags); 1189 netif_device_detach(tp->netdev); 1190 return; 1191 case -ENOENT: 1192 return; /* the urb is in unlink state */ 1193 case -ETIME: 1194 if (net_ratelimit()) 1195 netdev_warn(netdev, "maybe reset is needed?\n"); 1196 break; 1197 default: 1198 if (net_ratelimit()) 1199 netdev_warn(netdev, "Rx status %d\n", status); 1200 break; 1201 } 1202 1203 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1204 } 1205 1206 static void write_bulk_callback(struct urb *urb) 1207 { 1208 struct net_device_stats *stats; 1209 struct net_device *netdev; 1210 struct tx_agg *agg; 1211 struct r8152 *tp; 1212 int status = urb->status; 1213 1214 agg = urb->context; 1215 if (!agg) 1216 return; 1217 1218 tp = agg->context; 1219 if (!tp) 1220 return; 1221 1222 netdev = tp->netdev; 1223 stats = &netdev->stats; 1224 if (status) { 1225 if (net_ratelimit()) 1226 netdev_warn(netdev, "Tx status %d\n", status); 1227 stats->tx_errors += agg->skb_num; 1228 } else { 1229 stats->tx_packets += agg->skb_num; 1230 stats->tx_bytes += agg->skb_len; 1231 } 1232 1233 spin_lock(&tp->tx_lock); 1234 list_add_tail(&agg->list, &tp->tx_free); 1235 spin_unlock(&tp->tx_lock); 1236 1237 usb_autopm_put_interface_async(tp->intf); 1238 1239 if (!netif_carrier_ok(netdev)) 1240 return; 1241 1242 if (!test_bit(WORK_ENABLE, &tp->flags)) 1243 return; 1244 1245 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1246 return; 1247 1248 if (!skb_queue_empty(&tp->tx_queue)) 1249 napi_schedule(&tp->napi); 1250 } 1251 1252 static void intr_callback(struct urb *urb) 1253 { 1254 struct r8152 *tp; 1255 __le16 *d; 1256 int status = urb->status; 1257 int res; 1258 1259 tp = urb->context; 1260 if (!tp) 1261 return; 1262 1263 if (!test_bit(WORK_ENABLE, &tp->flags)) 1264 return; 1265 1266 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1267 return; 1268 1269 switch (status) { 1270 case 0: /* success */ 1271 break; 1272 case -ECONNRESET: /* unlink */ 1273 case -ESHUTDOWN: 1274 netif_device_detach(tp->netdev); 1275 case -ENOENT: 1276 case -EPROTO: 1277 netif_info(tp, intr, tp->netdev, 1278 "Stop submitting intr, status %d\n", status); 1279 return; 1280 case -EOVERFLOW: 1281 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1282 goto resubmit; 1283 /* -EPIPE: should clear the halt */ 1284 default: 1285 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1286 goto resubmit; 1287 } 1288 1289 d = urb->transfer_buffer; 1290 if (INTR_LINK & __le16_to_cpu(d[0])) { 1291 if (!netif_carrier_ok(tp->netdev)) { 1292 set_bit(RTL8152_LINK_CHG, &tp->flags); 1293 schedule_delayed_work(&tp->schedule, 0); 1294 } 1295 } else { 1296 if (netif_carrier_ok(tp->netdev)) { 1297 set_bit(RTL8152_LINK_CHG, &tp->flags); 1298 schedule_delayed_work(&tp->schedule, 0); 1299 } 1300 } 1301 1302 resubmit: 1303 res = usb_submit_urb(urb, GFP_ATOMIC); 1304 if (res == -ENODEV) { 1305 set_bit(RTL8152_UNPLUG, &tp->flags); 1306 netif_device_detach(tp->netdev); 1307 } else if (res) { 1308 netif_err(tp, intr, tp->netdev, 1309 "can't resubmit intr, status %d\n", res); 1310 } 1311 } 1312 1313 static inline void *rx_agg_align(void *data) 1314 { 1315 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1316 } 1317 1318 static inline void *tx_agg_align(void *data) 1319 { 1320 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1321 } 1322 1323 static void free_all_mem(struct r8152 *tp) 1324 { 1325 int i; 1326 1327 for (i = 0; i < RTL8152_MAX_RX; i++) { 1328 usb_free_urb(tp->rx_info[i].urb); 1329 tp->rx_info[i].urb = NULL; 1330 1331 kfree(tp->rx_info[i].buffer); 1332 tp->rx_info[i].buffer = NULL; 1333 tp->rx_info[i].head = NULL; 1334 } 1335 1336 for (i = 0; i < RTL8152_MAX_TX; i++) { 1337 usb_free_urb(tp->tx_info[i].urb); 1338 tp->tx_info[i].urb = NULL; 1339 1340 kfree(tp->tx_info[i].buffer); 1341 tp->tx_info[i].buffer = NULL; 1342 tp->tx_info[i].head = NULL; 1343 } 1344 1345 usb_free_urb(tp->intr_urb); 1346 tp->intr_urb = NULL; 1347 1348 kfree(tp->intr_buff); 1349 tp->intr_buff = NULL; 1350 } 1351 1352 static int alloc_all_mem(struct r8152 *tp) 1353 { 1354 struct net_device *netdev = tp->netdev; 1355 struct usb_interface *intf = tp->intf; 1356 struct usb_host_interface *alt = intf->cur_altsetting; 1357 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1358 struct urb *urb; 1359 int node, i; 1360 u8 *buf; 1361 1362 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1363 1364 spin_lock_init(&tp->rx_lock); 1365 spin_lock_init(&tp->tx_lock); 1366 INIT_LIST_HEAD(&tp->tx_free); 1367 INIT_LIST_HEAD(&tp->rx_done); 1368 skb_queue_head_init(&tp->tx_queue); 1369 skb_queue_head_init(&tp->rx_queue); 1370 1371 for (i = 0; i < RTL8152_MAX_RX; i++) { 1372 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1373 if (!buf) 1374 goto err1; 1375 1376 if (buf != rx_agg_align(buf)) { 1377 kfree(buf); 1378 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, 1379 node); 1380 if (!buf) 1381 goto err1; 1382 } 1383 1384 urb = usb_alloc_urb(0, GFP_KERNEL); 1385 if (!urb) { 1386 kfree(buf); 1387 goto err1; 1388 } 1389 1390 INIT_LIST_HEAD(&tp->rx_info[i].list); 1391 tp->rx_info[i].context = tp; 1392 tp->rx_info[i].urb = urb; 1393 tp->rx_info[i].buffer = buf; 1394 tp->rx_info[i].head = rx_agg_align(buf); 1395 } 1396 1397 for (i = 0; i < RTL8152_MAX_TX; i++) { 1398 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1399 if (!buf) 1400 goto err1; 1401 1402 if (buf != tx_agg_align(buf)) { 1403 kfree(buf); 1404 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 1405 node); 1406 if (!buf) 1407 goto err1; 1408 } 1409 1410 urb = usb_alloc_urb(0, GFP_KERNEL); 1411 if (!urb) { 1412 kfree(buf); 1413 goto err1; 1414 } 1415 1416 INIT_LIST_HEAD(&tp->tx_info[i].list); 1417 tp->tx_info[i].context = tp; 1418 tp->tx_info[i].urb = urb; 1419 tp->tx_info[i].buffer = buf; 1420 tp->tx_info[i].head = tx_agg_align(buf); 1421 1422 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1423 } 1424 1425 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1426 if (!tp->intr_urb) 1427 goto err1; 1428 1429 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1430 if (!tp->intr_buff) 1431 goto err1; 1432 1433 tp->intr_interval = (int)ep_intr->desc.bInterval; 1434 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1435 tp->intr_buff, INTBUFSIZE, intr_callback, 1436 tp, tp->intr_interval); 1437 1438 return 0; 1439 1440 err1: 1441 free_all_mem(tp); 1442 return -ENOMEM; 1443 } 1444 1445 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1446 { 1447 struct tx_agg *agg = NULL; 1448 unsigned long flags; 1449 1450 if (list_empty(&tp->tx_free)) 1451 return NULL; 1452 1453 spin_lock_irqsave(&tp->tx_lock, flags); 1454 if (!list_empty(&tp->tx_free)) { 1455 struct list_head *cursor; 1456 1457 cursor = tp->tx_free.next; 1458 list_del_init(cursor); 1459 agg = list_entry(cursor, struct tx_agg, list); 1460 } 1461 spin_unlock_irqrestore(&tp->tx_lock, flags); 1462 1463 return agg; 1464 } 1465 1466 /* r8152_csum_workaround() 1467 * The hw limites the value the transport offset. When the offset is out of the 1468 * range, calculate the checksum by sw. 1469 */ 1470 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1471 struct sk_buff_head *list) 1472 { 1473 if (skb_shinfo(skb)->gso_size) { 1474 netdev_features_t features = tp->netdev->features; 1475 struct sk_buff_head seg_list; 1476 struct sk_buff *segs, *nskb; 1477 1478 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 1479 segs = skb_gso_segment(skb, features); 1480 if (IS_ERR(segs) || !segs) 1481 goto drop; 1482 1483 __skb_queue_head_init(&seg_list); 1484 1485 do { 1486 nskb = segs; 1487 segs = segs->next; 1488 nskb->next = NULL; 1489 __skb_queue_tail(&seg_list, nskb); 1490 } while (segs); 1491 1492 skb_queue_splice(&seg_list, list); 1493 dev_kfree_skb(skb); 1494 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1495 if (skb_checksum_help(skb) < 0) 1496 goto drop; 1497 1498 __skb_queue_head(list, skb); 1499 } else { 1500 struct net_device_stats *stats; 1501 1502 drop: 1503 stats = &tp->netdev->stats; 1504 stats->tx_dropped++; 1505 dev_kfree_skb(skb); 1506 } 1507 } 1508 1509 /* msdn_giant_send_check() 1510 * According to the document of microsoft, the TCP Pseudo Header excludes the 1511 * packet length for IPv6 TCP large packets. 1512 */ 1513 static int msdn_giant_send_check(struct sk_buff *skb) 1514 { 1515 const struct ipv6hdr *ipv6h; 1516 struct tcphdr *th; 1517 int ret; 1518 1519 ret = skb_cow_head(skb, 0); 1520 if (ret) 1521 return ret; 1522 1523 ipv6h = ipv6_hdr(skb); 1524 th = tcp_hdr(skb); 1525 1526 th->check = 0; 1527 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1528 1529 return ret; 1530 } 1531 1532 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 1533 { 1534 if (skb_vlan_tag_present(skb)) { 1535 u32 opts2; 1536 1537 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); 1538 desc->opts2 |= cpu_to_le32(opts2); 1539 } 1540 } 1541 1542 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 1543 { 1544 u32 opts2 = le32_to_cpu(desc->opts2); 1545 1546 if (opts2 & RX_VLAN_TAG) 1547 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1548 swab16(opts2 & 0xffff)); 1549 } 1550 1551 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1552 struct sk_buff *skb, u32 len, u32 transport_offset) 1553 { 1554 u32 mss = skb_shinfo(skb)->gso_size; 1555 u32 opts1, opts2 = 0; 1556 int ret = TX_CSUM_SUCCESS; 1557 1558 WARN_ON_ONCE(len > TX_LEN_MAX); 1559 1560 opts1 = len | TX_FS | TX_LS; 1561 1562 if (mss) { 1563 if (transport_offset > GTTCPHO_MAX) { 1564 netif_warn(tp, tx_err, tp->netdev, 1565 "Invalid transport offset 0x%x for TSO\n", 1566 transport_offset); 1567 ret = TX_CSUM_TSO; 1568 goto unavailable; 1569 } 1570 1571 switch (vlan_get_protocol(skb)) { 1572 case htons(ETH_P_IP): 1573 opts1 |= GTSENDV4; 1574 break; 1575 1576 case htons(ETH_P_IPV6): 1577 if (msdn_giant_send_check(skb)) { 1578 ret = TX_CSUM_TSO; 1579 goto unavailable; 1580 } 1581 opts1 |= GTSENDV6; 1582 break; 1583 1584 default: 1585 WARN_ON_ONCE(1); 1586 break; 1587 } 1588 1589 opts1 |= transport_offset << GTTCPHO_SHIFT; 1590 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1591 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1592 u8 ip_protocol; 1593 1594 if (transport_offset > TCPHO_MAX) { 1595 netif_warn(tp, tx_err, tp->netdev, 1596 "Invalid transport offset 0x%x\n", 1597 transport_offset); 1598 ret = TX_CSUM_NONE; 1599 goto unavailable; 1600 } 1601 1602 switch (vlan_get_protocol(skb)) { 1603 case htons(ETH_P_IP): 1604 opts2 |= IPV4_CS; 1605 ip_protocol = ip_hdr(skb)->protocol; 1606 break; 1607 1608 case htons(ETH_P_IPV6): 1609 opts2 |= IPV6_CS; 1610 ip_protocol = ipv6_hdr(skb)->nexthdr; 1611 break; 1612 1613 default: 1614 ip_protocol = IPPROTO_RAW; 1615 break; 1616 } 1617 1618 if (ip_protocol == IPPROTO_TCP) 1619 opts2 |= TCP_CS; 1620 else if (ip_protocol == IPPROTO_UDP) 1621 opts2 |= UDP_CS; 1622 else 1623 WARN_ON_ONCE(1); 1624 1625 opts2 |= transport_offset << TCPHO_SHIFT; 1626 } 1627 1628 desc->opts2 = cpu_to_le32(opts2); 1629 desc->opts1 = cpu_to_le32(opts1); 1630 1631 unavailable: 1632 return ret; 1633 } 1634 1635 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1636 { 1637 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1638 int remain, ret; 1639 u8 *tx_data; 1640 1641 __skb_queue_head_init(&skb_head); 1642 spin_lock(&tx_queue->lock); 1643 skb_queue_splice_init(tx_queue, &skb_head); 1644 spin_unlock(&tx_queue->lock); 1645 1646 tx_data = agg->head; 1647 agg->skb_num = 0; 1648 agg->skb_len = 0; 1649 remain = agg_buf_sz; 1650 1651 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1652 struct tx_desc *tx_desc; 1653 struct sk_buff *skb; 1654 unsigned int len; 1655 u32 offset; 1656 1657 skb = __skb_dequeue(&skb_head); 1658 if (!skb) 1659 break; 1660 1661 len = skb->len + sizeof(*tx_desc); 1662 1663 if (len > remain) { 1664 __skb_queue_head(&skb_head, skb); 1665 break; 1666 } 1667 1668 tx_data = tx_agg_align(tx_data); 1669 tx_desc = (struct tx_desc *)tx_data; 1670 1671 offset = (u32)skb_transport_offset(skb); 1672 1673 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1674 r8152_csum_workaround(tp, skb, &skb_head); 1675 continue; 1676 } 1677 1678 rtl_tx_vlan_tag(tx_desc, skb); 1679 1680 tx_data += sizeof(*tx_desc); 1681 1682 len = skb->len; 1683 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1684 struct net_device_stats *stats = &tp->netdev->stats; 1685 1686 stats->tx_dropped++; 1687 dev_kfree_skb_any(skb); 1688 tx_data -= sizeof(*tx_desc); 1689 continue; 1690 } 1691 1692 tx_data += len; 1693 agg->skb_len += len; 1694 agg->skb_num++; 1695 1696 dev_kfree_skb_any(skb); 1697 1698 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1699 } 1700 1701 if (!skb_queue_empty(&skb_head)) { 1702 spin_lock(&tx_queue->lock); 1703 skb_queue_splice(&skb_head, tx_queue); 1704 spin_unlock(&tx_queue->lock); 1705 } 1706 1707 netif_tx_lock(tp->netdev); 1708 1709 if (netif_queue_stopped(tp->netdev) && 1710 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1711 netif_wake_queue(tp->netdev); 1712 1713 netif_tx_unlock(tp->netdev); 1714 1715 ret = usb_autopm_get_interface_async(tp->intf); 1716 if (ret < 0) 1717 goto out_tx_fill; 1718 1719 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1720 agg->head, (int)(tx_data - (u8 *)agg->head), 1721 (usb_complete_t)write_bulk_callback, agg); 1722 1723 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1724 if (ret < 0) 1725 usb_autopm_put_interface_async(tp->intf); 1726 1727 out_tx_fill: 1728 return ret; 1729 } 1730 1731 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1732 { 1733 u8 checksum = CHECKSUM_NONE; 1734 u32 opts2, opts3; 1735 1736 if (!(tp->netdev->features & NETIF_F_RXCSUM)) 1737 goto return_result; 1738 1739 opts2 = le32_to_cpu(rx_desc->opts2); 1740 opts3 = le32_to_cpu(rx_desc->opts3); 1741 1742 if (opts2 & RD_IPV4_CS) { 1743 if (opts3 & IPF) 1744 checksum = CHECKSUM_NONE; 1745 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) 1746 checksum = CHECKSUM_NONE; 1747 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) 1748 checksum = CHECKSUM_NONE; 1749 else 1750 checksum = CHECKSUM_UNNECESSARY; 1751 } else if (opts2 & RD_IPV6_CS) { 1752 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1753 checksum = CHECKSUM_UNNECESSARY; 1754 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1755 checksum = CHECKSUM_UNNECESSARY; 1756 } 1757 1758 return_result: 1759 return checksum; 1760 } 1761 1762 static int rx_bottom(struct r8152 *tp, int budget) 1763 { 1764 unsigned long flags; 1765 struct list_head *cursor, *next, rx_queue; 1766 int ret = 0, work_done = 0; 1767 1768 if (!skb_queue_empty(&tp->rx_queue)) { 1769 while (work_done < budget) { 1770 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); 1771 struct net_device *netdev = tp->netdev; 1772 struct net_device_stats *stats = &netdev->stats; 1773 unsigned int pkt_len; 1774 1775 if (!skb) 1776 break; 1777 1778 pkt_len = skb->len; 1779 napi_gro_receive(&tp->napi, skb); 1780 work_done++; 1781 stats->rx_packets++; 1782 stats->rx_bytes += pkt_len; 1783 } 1784 } 1785 1786 if (list_empty(&tp->rx_done)) 1787 goto out1; 1788 1789 INIT_LIST_HEAD(&rx_queue); 1790 spin_lock_irqsave(&tp->rx_lock, flags); 1791 list_splice_init(&tp->rx_done, &rx_queue); 1792 spin_unlock_irqrestore(&tp->rx_lock, flags); 1793 1794 list_for_each_safe(cursor, next, &rx_queue) { 1795 struct rx_desc *rx_desc; 1796 struct rx_agg *agg; 1797 int len_used = 0; 1798 struct urb *urb; 1799 u8 *rx_data; 1800 1801 list_del_init(cursor); 1802 1803 agg = list_entry(cursor, struct rx_agg, list); 1804 urb = agg->urb; 1805 if (urb->actual_length < ETH_ZLEN) 1806 goto submit; 1807 1808 rx_desc = agg->head; 1809 rx_data = agg->head; 1810 len_used += sizeof(struct rx_desc); 1811 1812 while (urb->actual_length > len_used) { 1813 struct net_device *netdev = tp->netdev; 1814 struct net_device_stats *stats = &netdev->stats; 1815 unsigned int pkt_len; 1816 struct sk_buff *skb; 1817 1818 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1819 if (pkt_len < ETH_ZLEN) 1820 break; 1821 1822 len_used += pkt_len; 1823 if (urb->actual_length < len_used) 1824 break; 1825 1826 pkt_len -= CRC_SIZE; 1827 rx_data += sizeof(struct rx_desc); 1828 1829 skb = napi_alloc_skb(&tp->napi, pkt_len); 1830 if (!skb) { 1831 stats->rx_dropped++; 1832 goto find_next_rx; 1833 } 1834 1835 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 1836 memcpy(skb->data, rx_data, pkt_len); 1837 skb_put(skb, pkt_len); 1838 skb->protocol = eth_type_trans(skb, netdev); 1839 rtl_rx_vlan_tag(rx_desc, skb); 1840 if (work_done < budget) { 1841 napi_gro_receive(&tp->napi, skb); 1842 work_done++; 1843 stats->rx_packets++; 1844 stats->rx_bytes += pkt_len; 1845 } else { 1846 __skb_queue_tail(&tp->rx_queue, skb); 1847 } 1848 1849 find_next_rx: 1850 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); 1851 rx_desc = (struct rx_desc *)rx_data; 1852 len_used = (int)(rx_data - (u8 *)agg->head); 1853 len_used += sizeof(struct rx_desc); 1854 } 1855 1856 submit: 1857 if (!ret) { 1858 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1859 } else { 1860 urb->actual_length = 0; 1861 list_add_tail(&agg->list, next); 1862 } 1863 } 1864 1865 if (!list_empty(&rx_queue)) { 1866 spin_lock_irqsave(&tp->rx_lock, flags); 1867 list_splice_tail(&rx_queue, &tp->rx_done); 1868 spin_unlock_irqrestore(&tp->rx_lock, flags); 1869 } 1870 1871 out1: 1872 return work_done; 1873 } 1874 1875 static void tx_bottom(struct r8152 *tp) 1876 { 1877 int res; 1878 1879 do { 1880 struct tx_agg *agg; 1881 1882 if (skb_queue_empty(&tp->tx_queue)) 1883 break; 1884 1885 agg = r8152_get_tx_agg(tp); 1886 if (!agg) 1887 break; 1888 1889 res = r8152_tx_agg_fill(tp, agg); 1890 if (res) { 1891 struct net_device *netdev = tp->netdev; 1892 1893 if (res == -ENODEV) { 1894 set_bit(RTL8152_UNPLUG, &tp->flags); 1895 netif_device_detach(netdev); 1896 } else { 1897 struct net_device_stats *stats = &netdev->stats; 1898 unsigned long flags; 1899 1900 netif_warn(tp, tx_err, netdev, 1901 "failed tx_urb %d\n", res); 1902 stats->tx_dropped += agg->skb_num; 1903 1904 spin_lock_irqsave(&tp->tx_lock, flags); 1905 list_add_tail(&agg->list, &tp->tx_free); 1906 spin_unlock_irqrestore(&tp->tx_lock, flags); 1907 } 1908 } 1909 } while (res == 0); 1910 } 1911 1912 static void bottom_half(struct r8152 *tp) 1913 { 1914 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1915 return; 1916 1917 if (!test_bit(WORK_ENABLE, &tp->flags)) 1918 return; 1919 1920 /* When link down, the driver would cancel all bulks. */ 1921 /* This avoid the re-submitting bulk */ 1922 if (!netif_carrier_ok(tp->netdev)) 1923 return; 1924 1925 clear_bit(SCHEDULE_NAPI, &tp->flags); 1926 1927 tx_bottom(tp); 1928 } 1929 1930 static int r8152_poll(struct napi_struct *napi, int budget) 1931 { 1932 struct r8152 *tp = container_of(napi, struct r8152, napi); 1933 int work_done; 1934 1935 work_done = rx_bottom(tp, budget); 1936 bottom_half(tp); 1937 1938 if (work_done < budget) { 1939 napi_complete(napi); 1940 if (!list_empty(&tp->rx_done)) 1941 napi_schedule(napi); 1942 else if (!skb_queue_empty(&tp->tx_queue) && 1943 !list_empty(&tp->tx_free)) 1944 napi_schedule(napi); 1945 } 1946 1947 return work_done; 1948 } 1949 1950 static 1951 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 1952 { 1953 int ret; 1954 1955 /* The rx would be stopped, so skip submitting */ 1956 if (test_bit(RTL8152_UNPLUG, &tp->flags) || 1957 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) 1958 return 0; 1959 1960 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 1961 agg->head, agg_buf_sz, 1962 (usb_complete_t)read_bulk_callback, agg); 1963 1964 ret = usb_submit_urb(agg->urb, mem_flags); 1965 if (ret == -ENODEV) { 1966 set_bit(RTL8152_UNPLUG, &tp->flags); 1967 netif_device_detach(tp->netdev); 1968 } else if (ret) { 1969 struct urb *urb = agg->urb; 1970 unsigned long flags; 1971 1972 urb->actual_length = 0; 1973 spin_lock_irqsave(&tp->rx_lock, flags); 1974 list_add_tail(&agg->list, &tp->rx_done); 1975 spin_unlock_irqrestore(&tp->rx_lock, flags); 1976 1977 netif_err(tp, rx_err, tp->netdev, 1978 "Couldn't submit rx[%p], ret = %d\n", agg, ret); 1979 1980 napi_schedule(&tp->napi); 1981 } 1982 1983 return ret; 1984 } 1985 1986 static void rtl_drop_queued_tx(struct r8152 *tp) 1987 { 1988 struct net_device_stats *stats = &tp->netdev->stats; 1989 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1990 struct sk_buff *skb; 1991 1992 if (skb_queue_empty(tx_queue)) 1993 return; 1994 1995 __skb_queue_head_init(&skb_head); 1996 spin_lock_bh(&tx_queue->lock); 1997 skb_queue_splice_init(tx_queue, &skb_head); 1998 spin_unlock_bh(&tx_queue->lock); 1999 2000 while ((skb = __skb_dequeue(&skb_head))) { 2001 dev_kfree_skb(skb); 2002 stats->tx_dropped++; 2003 } 2004 } 2005 2006 static void rtl8152_tx_timeout(struct net_device *netdev) 2007 { 2008 struct r8152 *tp = netdev_priv(netdev); 2009 2010 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 2011 2012 usb_queue_reset_device(tp->intf); 2013 } 2014 2015 static void rtl8152_set_rx_mode(struct net_device *netdev) 2016 { 2017 struct r8152 *tp = netdev_priv(netdev); 2018 2019 if (netif_carrier_ok(netdev)) { 2020 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2021 schedule_delayed_work(&tp->schedule, 0); 2022 } 2023 } 2024 2025 static void _rtl8152_set_rx_mode(struct net_device *netdev) 2026 { 2027 struct r8152 *tp = netdev_priv(netdev); 2028 u32 mc_filter[2]; /* Multicast hash filter */ 2029 __le32 tmp[2]; 2030 u32 ocp_data; 2031 2032 netif_stop_queue(netdev); 2033 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2034 ocp_data &= ~RCR_ACPT_ALL; 2035 ocp_data |= RCR_AB | RCR_APM; 2036 2037 if (netdev->flags & IFF_PROMISC) { 2038 /* Unconditionally log net taps. */ 2039 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 2040 ocp_data |= RCR_AM | RCR_AAP; 2041 mc_filter[1] = 0xffffffff; 2042 mc_filter[0] = 0xffffffff; 2043 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 2044 (netdev->flags & IFF_ALLMULTI)) { 2045 /* Too many to filter perfectly -- accept all multicasts. */ 2046 ocp_data |= RCR_AM; 2047 mc_filter[1] = 0xffffffff; 2048 mc_filter[0] = 0xffffffff; 2049 } else { 2050 struct netdev_hw_addr *ha; 2051 2052 mc_filter[1] = 0; 2053 mc_filter[0] = 0; 2054 netdev_for_each_mc_addr(ha, netdev) { 2055 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2056 2057 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2058 ocp_data |= RCR_AM; 2059 } 2060 } 2061 2062 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 2063 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 2064 2065 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 2066 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2067 netif_wake_queue(netdev); 2068 } 2069 2070 static netdev_features_t 2071 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 2072 netdev_features_t features) 2073 { 2074 u32 mss = skb_shinfo(skb)->gso_size; 2075 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 2076 int offset = skb_transport_offset(skb); 2077 2078 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) 2079 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2080 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 2081 features &= ~NETIF_F_GSO_MASK; 2082 2083 return features; 2084 } 2085 2086 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 2087 struct net_device *netdev) 2088 { 2089 struct r8152 *tp = netdev_priv(netdev); 2090 2091 skb_tx_timestamp(skb); 2092 2093 skb_queue_tail(&tp->tx_queue, skb); 2094 2095 if (!list_empty(&tp->tx_free)) { 2096 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2097 set_bit(SCHEDULE_NAPI, &tp->flags); 2098 schedule_delayed_work(&tp->schedule, 0); 2099 } else { 2100 usb_mark_last_busy(tp->udev); 2101 napi_schedule(&tp->napi); 2102 } 2103 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 2104 netif_stop_queue(netdev); 2105 } 2106 2107 return NETDEV_TX_OK; 2108 } 2109 2110 static void r8152b_reset_packet_filter(struct r8152 *tp) 2111 { 2112 u32 ocp_data; 2113 2114 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 2115 ocp_data &= ~FMC_FCR_MCU_EN; 2116 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2117 ocp_data |= FMC_FCR_MCU_EN; 2118 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2119 } 2120 2121 static void rtl8152_nic_reset(struct r8152 *tp) 2122 { 2123 int i; 2124 2125 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 2126 2127 for (i = 0; i < 1000; i++) { 2128 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 2129 break; 2130 usleep_range(100, 400); 2131 } 2132 } 2133 2134 static void set_tx_qlen(struct r8152 *tp) 2135 { 2136 struct net_device *netdev = tp->netdev; 2137 2138 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + 2139 sizeof(struct tx_desc)); 2140 } 2141 2142 static inline u8 rtl8152_get_speed(struct r8152 *tp) 2143 { 2144 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 2145 } 2146 2147 static void rtl_set_eee_plus(struct r8152 *tp) 2148 { 2149 u32 ocp_data; 2150 u8 speed; 2151 2152 speed = rtl8152_get_speed(tp); 2153 if (speed & _10bps) { 2154 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2155 ocp_data |= EEEP_CR_EEEP_TX; 2156 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2157 } else { 2158 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2159 ocp_data &= ~EEEP_CR_EEEP_TX; 2160 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2161 } 2162 } 2163 2164 static void rxdy_gated_en(struct r8152 *tp, bool enable) 2165 { 2166 u32 ocp_data; 2167 2168 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 2169 if (enable) 2170 ocp_data |= RXDY_GATED_EN; 2171 else 2172 ocp_data &= ~RXDY_GATED_EN; 2173 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 2174 } 2175 2176 static int rtl_start_rx(struct r8152 *tp) 2177 { 2178 int i, ret = 0; 2179 2180 INIT_LIST_HEAD(&tp->rx_done); 2181 for (i = 0; i < RTL8152_MAX_RX; i++) { 2182 INIT_LIST_HEAD(&tp->rx_info[i].list); 2183 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 2184 if (ret) 2185 break; 2186 } 2187 2188 if (ret && ++i < RTL8152_MAX_RX) { 2189 struct list_head rx_queue; 2190 unsigned long flags; 2191 2192 INIT_LIST_HEAD(&rx_queue); 2193 2194 do { 2195 struct rx_agg *agg = &tp->rx_info[i++]; 2196 struct urb *urb = agg->urb; 2197 2198 urb->actual_length = 0; 2199 list_add_tail(&agg->list, &rx_queue); 2200 } while (i < RTL8152_MAX_RX); 2201 2202 spin_lock_irqsave(&tp->rx_lock, flags); 2203 list_splice_tail(&rx_queue, &tp->rx_done); 2204 spin_unlock_irqrestore(&tp->rx_lock, flags); 2205 } 2206 2207 return ret; 2208 } 2209 2210 static int rtl_stop_rx(struct r8152 *tp) 2211 { 2212 int i; 2213 2214 for (i = 0; i < RTL8152_MAX_RX; i++) 2215 usb_kill_urb(tp->rx_info[i].urb); 2216 2217 while (!skb_queue_empty(&tp->rx_queue)) 2218 dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); 2219 2220 return 0; 2221 } 2222 2223 static int rtl_enable(struct r8152 *tp) 2224 { 2225 u32 ocp_data; 2226 2227 r8152b_reset_packet_filter(tp); 2228 2229 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2230 ocp_data |= CR_RE | CR_TE; 2231 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2232 2233 rxdy_gated_en(tp, false); 2234 2235 return 0; 2236 } 2237 2238 static int rtl8152_enable(struct r8152 *tp) 2239 { 2240 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2241 return -ENODEV; 2242 2243 set_tx_qlen(tp); 2244 rtl_set_eee_plus(tp); 2245 2246 return rtl_enable(tp); 2247 } 2248 2249 static void r8153_set_rx_early_timeout(struct r8152 *tp) 2250 { 2251 u32 ocp_data = tp->coalesce / 8; 2252 2253 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data); 2254 } 2255 2256 static void r8153_set_rx_early_size(struct r8152 *tp) 2257 { 2258 u32 ocp_data = (agg_buf_sz - rx_reserved_size(tp->netdev->mtu)) / 4; 2259 2260 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data); 2261 } 2262 2263 static int rtl8153_enable(struct r8152 *tp) 2264 { 2265 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2266 return -ENODEV; 2267 2268 usb_disable_lpm(tp->udev); 2269 set_tx_qlen(tp); 2270 rtl_set_eee_plus(tp); 2271 r8153_set_rx_early_timeout(tp); 2272 r8153_set_rx_early_size(tp); 2273 2274 return rtl_enable(tp); 2275 } 2276 2277 static void rtl_disable(struct r8152 *tp) 2278 { 2279 u32 ocp_data; 2280 int i; 2281 2282 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2283 rtl_drop_queued_tx(tp); 2284 return; 2285 } 2286 2287 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2288 ocp_data &= ~RCR_ACPT_ALL; 2289 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2290 2291 rtl_drop_queued_tx(tp); 2292 2293 for (i = 0; i < RTL8152_MAX_TX; i++) 2294 usb_kill_urb(tp->tx_info[i].urb); 2295 2296 rxdy_gated_en(tp, true); 2297 2298 for (i = 0; i < 1000; i++) { 2299 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2300 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2301 break; 2302 usleep_range(1000, 2000); 2303 } 2304 2305 for (i = 0; i < 1000; i++) { 2306 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2307 break; 2308 usleep_range(1000, 2000); 2309 } 2310 2311 rtl_stop_rx(tp); 2312 2313 rtl8152_nic_reset(tp); 2314 } 2315 2316 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2317 { 2318 u32 ocp_data; 2319 2320 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2321 if (enable) 2322 ocp_data |= POWER_CUT; 2323 else 2324 ocp_data &= ~POWER_CUT; 2325 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2326 2327 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2328 ocp_data &= ~RESUME_INDICATE; 2329 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2330 } 2331 2332 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 2333 { 2334 u32 ocp_data; 2335 2336 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2337 if (enable) 2338 ocp_data |= CPCR_RX_VLAN; 2339 else 2340 ocp_data &= ~CPCR_RX_VLAN; 2341 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2342 } 2343 2344 static int rtl8152_set_features(struct net_device *dev, 2345 netdev_features_t features) 2346 { 2347 netdev_features_t changed = features ^ dev->features; 2348 struct r8152 *tp = netdev_priv(dev); 2349 int ret; 2350 2351 ret = usb_autopm_get_interface(tp->intf); 2352 if (ret < 0) 2353 goto out; 2354 2355 mutex_lock(&tp->control); 2356 2357 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 2358 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2359 rtl_rx_vlan_en(tp, true); 2360 else 2361 rtl_rx_vlan_en(tp, false); 2362 } 2363 2364 mutex_unlock(&tp->control); 2365 2366 usb_autopm_put_interface(tp->intf); 2367 2368 out: 2369 return ret; 2370 } 2371 2372 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2373 2374 static u32 __rtl_get_wol(struct r8152 *tp) 2375 { 2376 u32 ocp_data; 2377 u32 wolopts = 0; 2378 2379 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2380 if (ocp_data & LINK_ON_WAKE_EN) 2381 wolopts |= WAKE_PHY; 2382 2383 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2384 if (ocp_data & UWF_EN) 2385 wolopts |= WAKE_UCAST; 2386 if (ocp_data & BWF_EN) 2387 wolopts |= WAKE_BCAST; 2388 if (ocp_data & MWF_EN) 2389 wolopts |= WAKE_MCAST; 2390 2391 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2392 if (ocp_data & MAGIC_EN) 2393 wolopts |= WAKE_MAGIC; 2394 2395 return wolopts; 2396 } 2397 2398 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2399 { 2400 u32 ocp_data; 2401 2402 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2403 2404 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2405 ocp_data &= ~LINK_ON_WAKE_EN; 2406 if (wolopts & WAKE_PHY) 2407 ocp_data |= LINK_ON_WAKE_EN; 2408 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2409 2410 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2411 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); 2412 if (wolopts & WAKE_UCAST) 2413 ocp_data |= UWF_EN; 2414 if (wolopts & WAKE_BCAST) 2415 ocp_data |= BWF_EN; 2416 if (wolopts & WAKE_MCAST) 2417 ocp_data |= MWF_EN; 2418 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2419 2420 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2421 2422 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2423 ocp_data &= ~MAGIC_EN; 2424 if (wolopts & WAKE_MAGIC) 2425 ocp_data |= MAGIC_EN; 2426 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2427 2428 if (wolopts & WAKE_ANY) 2429 device_set_wakeup_enable(&tp->udev->dev, true); 2430 else 2431 device_set_wakeup_enable(&tp->udev->dev, false); 2432 } 2433 2434 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2435 { 2436 u8 u1u2[8]; 2437 2438 if (enable) 2439 memset(u1u2, 0xff, sizeof(u1u2)); 2440 else 2441 memset(u1u2, 0x00, sizeof(u1u2)); 2442 2443 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2444 } 2445 2446 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2447 { 2448 u32 ocp_data; 2449 2450 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2451 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04) 2452 ocp_data |= U2P3_ENABLE; 2453 else 2454 ocp_data &= ~U2P3_ENABLE; 2455 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2456 } 2457 2458 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2459 { 2460 u32 ocp_data; 2461 2462 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2463 if (enable) 2464 ocp_data |= PWR_EN | PHASE2_EN; 2465 else 2466 ocp_data &= ~(PWR_EN | PHASE2_EN); 2467 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2468 2469 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2470 ocp_data &= ~PCUT_STATUS; 2471 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2472 } 2473 2474 static bool rtl_can_wakeup(struct r8152 *tp) 2475 { 2476 struct usb_device *udev = tp->udev; 2477 2478 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); 2479 } 2480 2481 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 2482 { 2483 if (enable) { 2484 u32 ocp_data; 2485 2486 __rtl_set_wol(tp, WAKE_ANY); 2487 2488 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2489 2490 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2491 ocp_data |= LINK_OFF_WAKE_EN; 2492 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2493 2494 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2495 } else { 2496 u32 ocp_data; 2497 2498 __rtl_set_wol(tp, tp->saved_wolopts); 2499 2500 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2501 2502 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2503 ocp_data &= ~LINK_OFF_WAKE_EN; 2504 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2505 2506 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2507 } 2508 } 2509 2510 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) 2511 { 2512 rtl_runtime_suspend_enable(tp, enable); 2513 2514 if (enable) { 2515 r8153_u1u2en(tp, false); 2516 r8153_u2p3en(tp, false); 2517 } else { 2518 r8153_u2p3en(tp, true); 2519 r8153_u1u2en(tp, true); 2520 } 2521 } 2522 2523 static void r8153_teredo_off(struct r8152 *tp) 2524 { 2525 u32 ocp_data; 2526 2527 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2528 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); 2529 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2530 2531 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 2532 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 2533 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 2534 } 2535 2536 static void rtl_reset_bmu(struct r8152 *tp) 2537 { 2538 u32 ocp_data; 2539 2540 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); 2541 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 2542 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2543 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 2544 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2545 } 2546 2547 static void r8152_aldps_en(struct r8152 *tp, bool enable) 2548 { 2549 if (enable) { 2550 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 2551 LINKENA | DIS_SDSAVE); 2552 } else { 2553 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | 2554 DIS_SDSAVE); 2555 msleep(20); 2556 } 2557 } 2558 2559 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 2560 { 2561 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 2562 ocp_reg_write(tp, OCP_EEE_DATA, reg); 2563 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 2564 } 2565 2566 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 2567 { 2568 u16 data; 2569 2570 r8152_mmd_indirect(tp, dev, reg); 2571 data = ocp_reg_read(tp, OCP_EEE_DATA); 2572 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 2573 2574 return data; 2575 } 2576 2577 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 2578 { 2579 r8152_mmd_indirect(tp, dev, reg); 2580 ocp_reg_write(tp, OCP_EEE_DATA, data); 2581 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 2582 } 2583 2584 static void r8152_eee_en(struct r8152 *tp, bool enable) 2585 { 2586 u16 config1, config2, config3; 2587 u32 ocp_data; 2588 2589 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 2590 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 2591 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 2592 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 2593 2594 if (enable) { 2595 ocp_data |= EEE_RX_EN | EEE_TX_EN; 2596 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 2597 config1 |= sd_rise_time(1); 2598 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 2599 config3 |= fast_snr(42); 2600 } else { 2601 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 2602 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 2603 RX_QUIET_EN); 2604 config1 |= sd_rise_time(7); 2605 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 2606 config3 |= fast_snr(511); 2607 } 2608 2609 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 2610 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 2611 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 2612 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 2613 } 2614 2615 static void r8152b_enable_eee(struct r8152 *tp) 2616 { 2617 r8152_eee_en(tp, true); 2618 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); 2619 } 2620 2621 static void r8152b_enable_fc(struct r8152 *tp) 2622 { 2623 u16 anar; 2624 2625 anar = r8152_mdio_read(tp, MII_ADVERTISE); 2626 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 2627 r8152_mdio_write(tp, MII_ADVERTISE, anar); 2628 } 2629 2630 static void rtl8152_disable(struct r8152 *tp) 2631 { 2632 r8152_aldps_en(tp, false); 2633 rtl_disable(tp); 2634 r8152_aldps_en(tp, true); 2635 } 2636 2637 static void r8152b_hw_phy_cfg(struct r8152 *tp) 2638 { 2639 r8152b_enable_eee(tp); 2640 r8152_aldps_en(tp, true); 2641 r8152b_enable_fc(tp); 2642 2643 set_bit(PHY_RESET, &tp->flags); 2644 } 2645 2646 static void r8152b_exit_oob(struct r8152 *tp) 2647 { 2648 u32 ocp_data; 2649 int i; 2650 2651 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2652 ocp_data &= ~RCR_ACPT_ALL; 2653 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2654 2655 rxdy_gated_en(tp, true); 2656 r8153_teredo_off(tp); 2657 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2658 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 2659 2660 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2661 ocp_data &= ~NOW_IS_OOB; 2662 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2663 2664 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2665 ocp_data &= ~MCU_BORW_EN; 2666 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2667 2668 for (i = 0; i < 1000; i++) { 2669 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2670 if (ocp_data & LINK_LIST_READY) 2671 break; 2672 usleep_range(1000, 2000); 2673 } 2674 2675 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2676 ocp_data |= RE_INIT_LL; 2677 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2678 2679 for (i = 0; i < 1000; i++) { 2680 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2681 if (ocp_data & LINK_LIST_READY) 2682 break; 2683 usleep_range(1000, 2000); 2684 } 2685 2686 rtl8152_nic_reset(tp); 2687 2688 /* rx share fifo credit full threshold */ 2689 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2690 2691 if (tp->udev->speed == USB_SPEED_FULL || 2692 tp->udev->speed == USB_SPEED_LOW) { 2693 /* rx share fifo credit near full threshold */ 2694 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2695 RXFIFO_THR2_FULL); 2696 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2697 RXFIFO_THR3_FULL); 2698 } else { 2699 /* rx share fifo credit near full threshold */ 2700 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2701 RXFIFO_THR2_HIGH); 2702 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2703 RXFIFO_THR3_HIGH); 2704 } 2705 2706 /* TX share fifo free credit full threshold */ 2707 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 2708 2709 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 2710 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 2711 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 2712 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 2713 2714 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 2715 2716 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2717 2718 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2719 ocp_data |= TCR0_AUTO_FIFO; 2720 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2721 } 2722 2723 static void r8152b_enter_oob(struct r8152 *tp) 2724 { 2725 u32 ocp_data; 2726 int i; 2727 2728 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2729 ocp_data &= ~NOW_IS_OOB; 2730 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2731 2732 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 2733 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 2734 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 2735 2736 rtl_disable(tp); 2737 2738 for (i = 0; i < 1000; i++) { 2739 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2740 if (ocp_data & LINK_LIST_READY) 2741 break; 2742 usleep_range(1000, 2000); 2743 } 2744 2745 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2746 ocp_data |= RE_INIT_LL; 2747 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2748 2749 for (i = 0; i < 1000; i++) { 2750 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2751 if (ocp_data & LINK_LIST_READY) 2752 break; 2753 usleep_range(1000, 2000); 2754 } 2755 2756 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2757 2758 rtl_rx_vlan_en(tp, true); 2759 2760 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2761 ocp_data |= ALDPS_PROXY_MODE; 2762 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2763 2764 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2765 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2766 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2767 2768 rxdy_gated_en(tp, false); 2769 2770 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2771 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2772 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2773 } 2774 2775 static void r8153_aldps_en(struct r8152 *tp, bool enable) 2776 { 2777 u16 data; 2778 2779 data = ocp_reg_read(tp, OCP_POWER_CFG); 2780 if (enable) { 2781 data |= EN_ALDPS; 2782 ocp_reg_write(tp, OCP_POWER_CFG, data); 2783 } else { 2784 data &= ~EN_ALDPS; 2785 ocp_reg_write(tp, OCP_POWER_CFG, data); 2786 msleep(20); 2787 } 2788 } 2789 2790 static void r8153_eee_en(struct r8152 *tp, bool enable) 2791 { 2792 u32 ocp_data; 2793 u16 config; 2794 2795 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 2796 config = ocp_reg_read(tp, OCP_EEE_CFG); 2797 2798 if (enable) { 2799 ocp_data |= EEE_RX_EN | EEE_TX_EN; 2800 config |= EEE10_EN; 2801 } else { 2802 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 2803 config &= ~EEE10_EN; 2804 } 2805 2806 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 2807 ocp_reg_write(tp, OCP_EEE_CFG, config); 2808 } 2809 2810 static void r8153_hw_phy_cfg(struct r8152 *tp) 2811 { 2812 u32 ocp_data; 2813 u16 data; 2814 2815 /* disable ALDPS before updating the PHY parameters */ 2816 r8153_aldps_en(tp, false); 2817 2818 /* disable EEE before updating the PHY parameters */ 2819 r8153_eee_en(tp, false); 2820 ocp_reg_write(tp, OCP_EEE_ADV, 0); 2821 2822 if (tp->version == RTL_VER_03) { 2823 data = ocp_reg_read(tp, OCP_EEE_CFG); 2824 data &= ~CTAP_SHORT_EN; 2825 ocp_reg_write(tp, OCP_EEE_CFG, data); 2826 } 2827 2828 data = ocp_reg_read(tp, OCP_POWER_CFG); 2829 data |= EEE_CLKDIV_EN; 2830 ocp_reg_write(tp, OCP_POWER_CFG, data); 2831 2832 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 2833 data |= EN_10M_BGOFF; 2834 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 2835 data = ocp_reg_read(tp, OCP_POWER_CFG); 2836 data |= EN_10M_PLLOFF; 2837 ocp_reg_write(tp, OCP_POWER_CFG, data); 2838 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 2839 2840 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 2841 ocp_data |= PFM_PWM_SWITCH; 2842 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 2843 2844 /* Enable LPF corner auto tune */ 2845 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 2846 2847 /* Adjust 10M Amplitude */ 2848 sram_write(tp, SRAM_10M_AMP1, 0x00af); 2849 sram_write(tp, SRAM_10M_AMP2, 0x0208); 2850 2851 r8153_eee_en(tp, true); 2852 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 2853 2854 r8153_aldps_en(tp, true); 2855 r8152b_enable_fc(tp); 2856 2857 set_bit(PHY_RESET, &tp->flags); 2858 } 2859 2860 static void r8153_first_init(struct r8152 *tp) 2861 { 2862 u32 ocp_data; 2863 int i; 2864 2865 rxdy_gated_en(tp, true); 2866 r8153_teredo_off(tp); 2867 2868 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2869 ocp_data &= ~RCR_ACPT_ALL; 2870 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2871 2872 rtl8152_nic_reset(tp); 2873 rtl_reset_bmu(tp); 2874 2875 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2876 ocp_data &= ~NOW_IS_OOB; 2877 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2878 2879 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2880 ocp_data &= ~MCU_BORW_EN; 2881 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2882 2883 for (i = 0; i < 1000; i++) { 2884 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2885 if (ocp_data & LINK_LIST_READY) 2886 break; 2887 usleep_range(1000, 2000); 2888 } 2889 2890 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2891 ocp_data |= RE_INIT_LL; 2892 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2893 2894 for (i = 0; i < 1000; i++) { 2895 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2896 if (ocp_data & LINK_LIST_READY) 2897 break; 2898 usleep_range(1000, 2000); 2899 } 2900 2901 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 2902 2903 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + CRC_SIZE; 2904 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 2905 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 2906 2907 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2908 ocp_data |= TCR0_AUTO_FIFO; 2909 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2910 2911 rtl8152_nic_reset(tp); 2912 2913 /* rx share fifo credit full threshold */ 2914 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2915 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 2916 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 2917 /* TX share fifo free credit full threshold */ 2918 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 2919 2920 /* rx aggregation */ 2921 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 2922 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 2923 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 2924 } 2925 2926 static void r8153_enter_oob(struct r8152 *tp) 2927 { 2928 u32 ocp_data; 2929 int i; 2930 2931 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2932 ocp_data &= ~NOW_IS_OOB; 2933 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2934 2935 rtl_disable(tp); 2936 rtl_reset_bmu(tp); 2937 2938 for (i = 0; i < 1000; i++) { 2939 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2940 if (ocp_data & LINK_LIST_READY) 2941 break; 2942 usleep_range(1000, 2000); 2943 } 2944 2945 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2946 ocp_data |= RE_INIT_LL; 2947 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2948 2949 for (i = 0; i < 1000; i++) { 2950 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2951 if (ocp_data & LINK_LIST_READY) 2952 break; 2953 usleep_range(1000, 2000); 2954 } 2955 2956 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + CRC_SIZE; 2957 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 2958 2959 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2960 ocp_data &= ~TEREDO_WAKE_MASK; 2961 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2962 2963 rtl_rx_vlan_en(tp, true); 2964 2965 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2966 ocp_data |= ALDPS_PROXY_MODE; 2967 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2968 2969 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2970 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2971 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2972 2973 rxdy_gated_en(tp, false); 2974 2975 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2976 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2977 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2978 } 2979 2980 static void rtl8153_disable(struct r8152 *tp) 2981 { 2982 r8153_aldps_en(tp, false); 2983 rtl_disable(tp); 2984 rtl_reset_bmu(tp); 2985 r8153_aldps_en(tp, true); 2986 usb_enable_lpm(tp->udev); 2987 } 2988 2989 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 2990 { 2991 u16 bmcr, anar, gbcr; 2992 int ret = 0; 2993 2994 anar = r8152_mdio_read(tp, MII_ADVERTISE); 2995 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 2996 ADVERTISE_100HALF | ADVERTISE_100FULL); 2997 if (tp->mii.supports_gmii) { 2998 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 2999 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 3000 } else { 3001 gbcr = 0; 3002 } 3003 3004 if (autoneg == AUTONEG_DISABLE) { 3005 if (speed == SPEED_10) { 3006 bmcr = 0; 3007 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3008 } else if (speed == SPEED_100) { 3009 bmcr = BMCR_SPEED100; 3010 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3011 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3012 bmcr = BMCR_SPEED1000; 3013 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3014 } else { 3015 ret = -EINVAL; 3016 goto out; 3017 } 3018 3019 if (duplex == DUPLEX_FULL) 3020 bmcr |= BMCR_FULLDPLX; 3021 } else { 3022 if (speed == SPEED_10) { 3023 if (duplex == DUPLEX_FULL) 3024 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3025 else 3026 anar |= ADVERTISE_10HALF; 3027 } else if (speed == SPEED_100) { 3028 if (duplex == DUPLEX_FULL) { 3029 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3030 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3031 } else { 3032 anar |= ADVERTISE_10HALF; 3033 anar |= ADVERTISE_100HALF; 3034 } 3035 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3036 if (duplex == DUPLEX_FULL) { 3037 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3038 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3039 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3040 } else { 3041 anar |= ADVERTISE_10HALF; 3042 anar |= ADVERTISE_100HALF; 3043 gbcr |= ADVERTISE_1000HALF; 3044 } 3045 } else { 3046 ret = -EINVAL; 3047 goto out; 3048 } 3049 3050 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 3051 } 3052 3053 if (test_and_clear_bit(PHY_RESET, &tp->flags)) 3054 bmcr |= BMCR_RESET; 3055 3056 if (tp->mii.supports_gmii) 3057 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 3058 3059 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3060 r8152_mdio_write(tp, MII_BMCR, bmcr); 3061 3062 if (bmcr & BMCR_RESET) { 3063 int i; 3064 3065 for (i = 0; i < 50; i++) { 3066 msleep(20); 3067 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 3068 break; 3069 } 3070 } 3071 3072 out: 3073 return ret; 3074 } 3075 3076 static void rtl8152_up(struct r8152 *tp) 3077 { 3078 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3079 return; 3080 3081 r8152_aldps_en(tp, false); 3082 r8152b_exit_oob(tp); 3083 r8152_aldps_en(tp, true); 3084 } 3085 3086 static void rtl8152_down(struct r8152 *tp) 3087 { 3088 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3089 rtl_drop_queued_tx(tp); 3090 return; 3091 } 3092 3093 r8152_power_cut_en(tp, false); 3094 r8152_aldps_en(tp, false); 3095 r8152b_enter_oob(tp); 3096 r8152_aldps_en(tp, true); 3097 } 3098 3099 static void rtl8153_up(struct r8152 *tp) 3100 { 3101 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3102 return; 3103 3104 r8153_u1u2en(tp, false); 3105 r8153_aldps_en(tp, false); 3106 r8153_first_init(tp); 3107 r8153_aldps_en(tp, true); 3108 r8153_u2p3en(tp, true); 3109 r8153_u1u2en(tp, true); 3110 usb_enable_lpm(tp->udev); 3111 } 3112 3113 static void rtl8153_down(struct r8152 *tp) 3114 { 3115 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3116 rtl_drop_queued_tx(tp); 3117 return; 3118 } 3119 3120 r8153_u1u2en(tp, false); 3121 r8153_u2p3en(tp, false); 3122 r8153_power_cut_en(tp, false); 3123 r8153_aldps_en(tp, false); 3124 r8153_enter_oob(tp); 3125 r8153_aldps_en(tp, true); 3126 } 3127 3128 static bool rtl8152_in_nway(struct r8152 *tp) 3129 { 3130 u16 nway_state; 3131 3132 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); 3133 tp->ocp_base = 0x2000; 3134 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ 3135 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); 3136 3137 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ 3138 if (nway_state & 0xc000) 3139 return false; 3140 else 3141 return true; 3142 } 3143 3144 static bool rtl8153_in_nway(struct r8152 *tp) 3145 { 3146 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; 3147 3148 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) 3149 return false; 3150 else 3151 return true; 3152 } 3153 3154 static void set_carrier(struct r8152 *tp) 3155 { 3156 struct net_device *netdev = tp->netdev; 3157 u8 speed; 3158 3159 speed = rtl8152_get_speed(tp); 3160 3161 if (speed & LINK_STATUS) { 3162 if (!netif_carrier_ok(netdev)) { 3163 tp->rtl_ops.enable(tp); 3164 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 3165 netif_stop_queue(netdev); 3166 napi_disable(&tp->napi); 3167 netif_carrier_on(netdev); 3168 rtl_start_rx(tp); 3169 napi_enable(&tp->napi); 3170 netif_wake_queue(netdev); 3171 netif_info(tp, link, netdev, "carrier on\n"); 3172 } 3173 } else { 3174 if (netif_carrier_ok(netdev)) { 3175 netif_carrier_off(netdev); 3176 napi_disable(&tp->napi); 3177 tp->rtl_ops.disable(tp); 3178 napi_enable(&tp->napi); 3179 netif_info(tp, link, netdev, "carrier off\n"); 3180 } 3181 } 3182 } 3183 3184 static void rtl_work_func_t(struct work_struct *work) 3185 { 3186 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 3187 3188 /* If the device is unplugged or !netif_running(), the workqueue 3189 * doesn't need to wake the device, and could return directly. 3190 */ 3191 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) 3192 return; 3193 3194 if (usb_autopm_get_interface(tp->intf) < 0) 3195 return; 3196 3197 if (!test_bit(WORK_ENABLE, &tp->flags)) 3198 goto out1; 3199 3200 if (!mutex_trylock(&tp->control)) { 3201 schedule_delayed_work(&tp->schedule, 0); 3202 goto out1; 3203 } 3204 3205 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) 3206 set_carrier(tp); 3207 3208 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) 3209 _rtl8152_set_rx_mode(tp->netdev); 3210 3211 /* don't schedule napi before linking */ 3212 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) && 3213 netif_carrier_ok(tp->netdev)) 3214 napi_schedule(&tp->napi); 3215 3216 mutex_unlock(&tp->control); 3217 3218 out1: 3219 usb_autopm_put_interface(tp->intf); 3220 } 3221 3222 static void rtl_hw_phy_work_func_t(struct work_struct *work) 3223 { 3224 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); 3225 3226 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3227 return; 3228 3229 if (usb_autopm_get_interface(tp->intf) < 0) 3230 return; 3231 3232 mutex_lock(&tp->control); 3233 3234 tp->rtl_ops.hw_phy_cfg(tp); 3235 3236 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex); 3237 3238 mutex_unlock(&tp->control); 3239 3240 usb_autopm_put_interface(tp->intf); 3241 } 3242 3243 #ifdef CONFIG_PM_SLEEP 3244 static int rtl_notifier(struct notifier_block *nb, unsigned long action, 3245 void *data) 3246 { 3247 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); 3248 3249 switch (action) { 3250 case PM_HIBERNATION_PREPARE: 3251 case PM_SUSPEND_PREPARE: 3252 usb_autopm_get_interface(tp->intf); 3253 break; 3254 3255 case PM_POST_HIBERNATION: 3256 case PM_POST_SUSPEND: 3257 usb_autopm_put_interface(tp->intf); 3258 break; 3259 3260 case PM_POST_RESTORE: 3261 case PM_RESTORE_PREPARE: 3262 default: 3263 break; 3264 } 3265 3266 return NOTIFY_DONE; 3267 } 3268 #endif 3269 3270 static int rtl8152_open(struct net_device *netdev) 3271 { 3272 struct r8152 *tp = netdev_priv(netdev); 3273 int res = 0; 3274 3275 res = alloc_all_mem(tp); 3276 if (res) 3277 goto out; 3278 3279 res = usb_autopm_get_interface(tp->intf); 3280 if (res < 0) 3281 goto out_free; 3282 3283 mutex_lock(&tp->control); 3284 3285 tp->rtl_ops.up(tp); 3286 3287 netif_carrier_off(netdev); 3288 netif_start_queue(netdev); 3289 set_bit(WORK_ENABLE, &tp->flags); 3290 3291 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3292 if (res) { 3293 if (res == -ENODEV) 3294 netif_device_detach(tp->netdev); 3295 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 3296 res); 3297 goto out_unlock; 3298 } 3299 napi_enable(&tp->napi); 3300 3301 mutex_unlock(&tp->control); 3302 3303 usb_autopm_put_interface(tp->intf); 3304 #ifdef CONFIG_PM_SLEEP 3305 tp->pm_notifier.notifier_call = rtl_notifier; 3306 register_pm_notifier(&tp->pm_notifier); 3307 #endif 3308 return 0; 3309 3310 out_unlock: 3311 mutex_unlock(&tp->control); 3312 usb_autopm_put_interface(tp->intf); 3313 out_free: 3314 free_all_mem(tp); 3315 out: 3316 return res; 3317 } 3318 3319 static int rtl8152_close(struct net_device *netdev) 3320 { 3321 struct r8152 *tp = netdev_priv(netdev); 3322 int res = 0; 3323 3324 #ifdef CONFIG_PM_SLEEP 3325 unregister_pm_notifier(&tp->pm_notifier); 3326 #endif 3327 napi_disable(&tp->napi); 3328 clear_bit(WORK_ENABLE, &tp->flags); 3329 usb_kill_urb(tp->intr_urb); 3330 cancel_delayed_work_sync(&tp->schedule); 3331 netif_stop_queue(netdev); 3332 3333 res = usb_autopm_get_interface(tp->intf); 3334 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { 3335 rtl_drop_queued_tx(tp); 3336 rtl_stop_rx(tp); 3337 } else { 3338 mutex_lock(&tp->control); 3339 3340 tp->rtl_ops.down(tp); 3341 3342 mutex_unlock(&tp->control); 3343 3344 usb_autopm_put_interface(tp->intf); 3345 } 3346 3347 free_all_mem(tp); 3348 3349 return res; 3350 } 3351 3352 static void rtl_tally_reset(struct r8152 *tp) 3353 { 3354 u32 ocp_data; 3355 3356 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 3357 ocp_data |= TALLY_RESET; 3358 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 3359 } 3360 3361 static void r8152b_init(struct r8152 *tp) 3362 { 3363 u32 ocp_data; 3364 u16 data; 3365 3366 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3367 return; 3368 3369 data = r8152_mdio_read(tp, MII_BMCR); 3370 if (data & BMCR_PDOWN) { 3371 data &= ~BMCR_PDOWN; 3372 r8152_mdio_write(tp, MII_BMCR, data); 3373 } 3374 3375 r8152_aldps_en(tp, false); 3376 3377 if (tp->version == RTL_VER_01) { 3378 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 3379 ocp_data &= ~LED_MODE_MASK; 3380 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 3381 } 3382 3383 r8152_power_cut_en(tp, false); 3384 3385 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3386 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 3387 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3388 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 3389 ocp_data &= ~MCU_CLK_RATIO_MASK; 3390 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 3391 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 3392 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 3393 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 3394 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 3395 3396 rtl_tally_reset(tp); 3397 3398 /* enable rx aggregation */ 3399 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 3400 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 3401 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 3402 } 3403 3404 static void r8153_init(struct r8152 *tp) 3405 { 3406 u32 ocp_data; 3407 u16 data; 3408 int i; 3409 3410 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3411 return; 3412 3413 r8153_u1u2en(tp, false); 3414 3415 for (i = 0; i < 500; i++) { 3416 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 3417 AUTOLOAD_DONE) 3418 break; 3419 msleep(20); 3420 } 3421 3422 for (i = 0; i < 500; i++) { 3423 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; 3424 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) 3425 break; 3426 msleep(20); 3427 } 3428 3429 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 3430 tp->version == RTL_VER_05) 3431 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 3432 3433 data = r8152_mdio_read(tp, MII_BMCR); 3434 if (data & BMCR_PDOWN) { 3435 data &= ~BMCR_PDOWN; 3436 r8152_mdio_write(tp, MII_BMCR, data); 3437 } 3438 3439 for (i = 0; i < 500; i++) { 3440 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; 3441 if (ocp_data == PHY_STAT_LAN_ON) 3442 break; 3443 msleep(20); 3444 } 3445 3446 usb_disable_lpm(tp->udev); 3447 r8153_u2p3en(tp, false); 3448 3449 if (tp->version == RTL_VER_04) { 3450 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 3451 ocp_data &= ~pwd_dn_scale_mask; 3452 ocp_data |= pwd_dn_scale(96); 3453 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 3454 3455 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 3456 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 3457 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 3458 } else if (tp->version == RTL_VER_05) { 3459 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 3460 ocp_data &= ~ECM_ALDPS; 3461 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 3462 3463 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 3464 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 3465 ocp_data &= ~DYNAMIC_BURST; 3466 else 3467 ocp_data |= DYNAMIC_BURST; 3468 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 3469 } else if (tp->version == RTL_VER_06) { 3470 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 3471 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 3472 ocp_data &= ~DYNAMIC_BURST; 3473 else 3474 ocp_data |= DYNAMIC_BURST; 3475 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 3476 } 3477 3478 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 3479 ocp_data |= EP4_FULL_FC; 3480 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 3481 3482 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 3483 ocp_data &= ~TIMER11_EN; 3484 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 3485 3486 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 3487 ocp_data &= ~LED_MODE_MASK; 3488 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 3489 3490 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 3491 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) 3492 ocp_data |= LPM_TIMER_500MS; 3493 else 3494 ocp_data |= LPM_TIMER_500US; 3495 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 3496 3497 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 3498 ocp_data &= ~SEN_VAL_MASK; 3499 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 3500 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 3501 3502 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 3503 3504 r8153_power_cut_en(tp, false); 3505 r8153_u1u2en(tp, true); 3506 3507 /* MAC clock speed down */ 3508 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); 3509 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); 3510 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); 3511 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); 3512 3513 rtl_tally_reset(tp); 3514 r8153_u2p3en(tp, true); 3515 } 3516 3517 static int rtl8152_pre_reset(struct usb_interface *intf) 3518 { 3519 struct r8152 *tp = usb_get_intfdata(intf); 3520 struct net_device *netdev; 3521 3522 if (!tp) 3523 return 0; 3524 3525 netdev = tp->netdev; 3526 if (!netif_running(netdev)) 3527 return 0; 3528 3529 netif_stop_queue(netdev); 3530 napi_disable(&tp->napi); 3531 clear_bit(WORK_ENABLE, &tp->flags); 3532 usb_kill_urb(tp->intr_urb); 3533 cancel_delayed_work_sync(&tp->schedule); 3534 if (netif_carrier_ok(netdev)) { 3535 mutex_lock(&tp->control); 3536 tp->rtl_ops.disable(tp); 3537 mutex_unlock(&tp->control); 3538 } 3539 3540 return 0; 3541 } 3542 3543 static int rtl8152_post_reset(struct usb_interface *intf) 3544 { 3545 struct r8152 *tp = usb_get_intfdata(intf); 3546 struct net_device *netdev; 3547 3548 if (!tp) 3549 return 0; 3550 3551 netdev = tp->netdev; 3552 if (!netif_running(netdev)) 3553 return 0; 3554 3555 set_bit(WORK_ENABLE, &tp->flags); 3556 if (netif_carrier_ok(netdev)) { 3557 mutex_lock(&tp->control); 3558 tp->rtl_ops.enable(tp); 3559 rtl_start_rx(tp); 3560 rtl8152_set_rx_mode(netdev); 3561 mutex_unlock(&tp->control); 3562 } 3563 3564 napi_enable(&tp->napi); 3565 netif_wake_queue(netdev); 3566 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3567 3568 if (!list_empty(&tp->rx_done)) 3569 napi_schedule(&tp->napi); 3570 3571 return 0; 3572 } 3573 3574 static bool delay_autosuspend(struct r8152 *tp) 3575 { 3576 bool sw_linking = !!netif_carrier_ok(tp->netdev); 3577 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); 3578 3579 /* This means a linking change occurs and the driver doesn't detect it, 3580 * yet. If the driver has disabled tx/rx and hw is linking on, the 3581 * device wouldn't wake up by receiving any packet. 3582 */ 3583 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) 3584 return true; 3585 3586 /* If the linking down is occurred by nway, the device may miss the 3587 * linking change event. And it wouldn't wake when linking on. 3588 */ 3589 if (!sw_linking && tp->rtl_ops.in_nway(tp)) 3590 return true; 3591 else if (!skb_queue_empty(&tp->tx_queue)) 3592 return true; 3593 else 3594 return false; 3595 } 3596 3597 static int rtl8152_runtime_suspend(struct r8152 *tp) 3598 { 3599 struct net_device *netdev = tp->netdev; 3600 int ret = 0; 3601 3602 set_bit(SELECTIVE_SUSPEND, &tp->flags); 3603 smp_mb__after_atomic(); 3604 3605 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 3606 u32 rcr = 0; 3607 3608 if (delay_autosuspend(tp)) { 3609 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3610 smp_mb__after_atomic(); 3611 ret = -EBUSY; 3612 goto out1; 3613 } 3614 3615 if (netif_carrier_ok(netdev)) { 3616 u32 ocp_data; 3617 3618 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3619 ocp_data = rcr & ~RCR_ACPT_ALL; 3620 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3621 rxdy_gated_en(tp, true); 3622 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 3623 PLA_OOB_CTRL); 3624 if (!(ocp_data & RXFIFO_EMPTY)) { 3625 rxdy_gated_en(tp, false); 3626 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 3627 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3628 smp_mb__after_atomic(); 3629 ret = -EBUSY; 3630 goto out1; 3631 } 3632 } 3633 3634 clear_bit(WORK_ENABLE, &tp->flags); 3635 usb_kill_urb(tp->intr_urb); 3636 3637 tp->rtl_ops.autosuspend_en(tp, true); 3638 3639 if (netif_carrier_ok(netdev)) { 3640 napi_disable(&tp->napi); 3641 rtl_stop_rx(tp); 3642 rxdy_gated_en(tp, false); 3643 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 3644 napi_enable(&tp->napi); 3645 } 3646 } 3647 3648 out1: 3649 return ret; 3650 } 3651 3652 static int rtl8152_system_suspend(struct r8152 *tp) 3653 { 3654 struct net_device *netdev = tp->netdev; 3655 int ret = 0; 3656 3657 netif_device_detach(netdev); 3658 3659 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 3660 clear_bit(WORK_ENABLE, &tp->flags); 3661 usb_kill_urb(tp->intr_urb); 3662 napi_disable(&tp->napi); 3663 cancel_delayed_work_sync(&tp->schedule); 3664 tp->rtl_ops.down(tp); 3665 napi_enable(&tp->napi); 3666 } 3667 3668 return ret; 3669 } 3670 3671 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 3672 { 3673 struct r8152 *tp = usb_get_intfdata(intf); 3674 int ret; 3675 3676 mutex_lock(&tp->control); 3677 3678 if (PMSG_IS_AUTO(message)) 3679 ret = rtl8152_runtime_suspend(tp); 3680 else 3681 ret = rtl8152_system_suspend(tp); 3682 3683 mutex_unlock(&tp->control); 3684 3685 return ret; 3686 } 3687 3688 static int rtl8152_resume(struct usb_interface *intf) 3689 { 3690 struct r8152 *tp = usb_get_intfdata(intf); 3691 3692 mutex_lock(&tp->control); 3693 3694 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3695 tp->rtl_ops.init(tp); 3696 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 3697 netif_device_attach(tp->netdev); 3698 } 3699 3700 if (netif_running(tp->netdev) && tp->netdev->flags & IFF_UP) { 3701 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3702 tp->rtl_ops.autosuspend_en(tp, false); 3703 napi_disable(&tp->napi); 3704 set_bit(WORK_ENABLE, &tp->flags); 3705 if (netif_carrier_ok(tp->netdev)) 3706 rtl_start_rx(tp); 3707 napi_enable(&tp->napi); 3708 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3709 smp_mb__after_atomic(); 3710 if (!list_empty(&tp->rx_done)) 3711 napi_schedule(&tp->napi); 3712 } else { 3713 tp->rtl_ops.up(tp); 3714 netif_carrier_off(tp->netdev); 3715 set_bit(WORK_ENABLE, &tp->flags); 3716 } 3717 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3718 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3719 if (tp->netdev->flags & IFF_UP) 3720 tp->rtl_ops.autosuspend_en(tp, false); 3721 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3722 } 3723 3724 mutex_unlock(&tp->control); 3725 3726 return 0; 3727 } 3728 3729 static int rtl8152_reset_resume(struct usb_interface *intf) 3730 { 3731 struct r8152 *tp = usb_get_intfdata(intf); 3732 3733 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3734 return rtl8152_resume(intf); 3735 } 3736 3737 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3738 { 3739 struct r8152 *tp = netdev_priv(dev); 3740 3741 if (usb_autopm_get_interface(tp->intf) < 0) 3742 return; 3743 3744 if (!rtl_can_wakeup(tp)) { 3745 wol->supported = 0; 3746 wol->wolopts = 0; 3747 } else { 3748 mutex_lock(&tp->control); 3749 wol->supported = WAKE_ANY; 3750 wol->wolopts = __rtl_get_wol(tp); 3751 mutex_unlock(&tp->control); 3752 } 3753 3754 usb_autopm_put_interface(tp->intf); 3755 } 3756 3757 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3758 { 3759 struct r8152 *tp = netdev_priv(dev); 3760 int ret; 3761 3762 if (!rtl_can_wakeup(tp)) 3763 return -EOPNOTSUPP; 3764 3765 ret = usb_autopm_get_interface(tp->intf); 3766 if (ret < 0) 3767 goto out_set_wol; 3768 3769 mutex_lock(&tp->control); 3770 3771 __rtl_set_wol(tp, wol->wolopts); 3772 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 3773 3774 mutex_unlock(&tp->control); 3775 3776 usb_autopm_put_interface(tp->intf); 3777 3778 out_set_wol: 3779 return ret; 3780 } 3781 3782 static u32 rtl8152_get_msglevel(struct net_device *dev) 3783 { 3784 struct r8152 *tp = netdev_priv(dev); 3785 3786 return tp->msg_enable; 3787 } 3788 3789 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 3790 { 3791 struct r8152 *tp = netdev_priv(dev); 3792 3793 tp->msg_enable = value; 3794 } 3795 3796 static void rtl8152_get_drvinfo(struct net_device *netdev, 3797 struct ethtool_drvinfo *info) 3798 { 3799 struct r8152 *tp = netdev_priv(netdev); 3800 3801 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 3802 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 3803 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 3804 } 3805 3806 static 3807 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) 3808 { 3809 struct r8152 *tp = netdev_priv(netdev); 3810 int ret; 3811 3812 if (!tp->mii.mdio_read) 3813 return -EOPNOTSUPP; 3814 3815 ret = usb_autopm_get_interface(tp->intf); 3816 if (ret < 0) 3817 goto out; 3818 3819 mutex_lock(&tp->control); 3820 3821 ret = mii_ethtool_gset(&tp->mii, cmd); 3822 3823 mutex_unlock(&tp->control); 3824 3825 usb_autopm_put_interface(tp->intf); 3826 3827 out: 3828 return ret; 3829 } 3830 3831 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 3832 { 3833 struct r8152 *tp = netdev_priv(dev); 3834 int ret; 3835 3836 ret = usb_autopm_get_interface(tp->intf); 3837 if (ret < 0) 3838 goto out; 3839 3840 mutex_lock(&tp->control); 3841 3842 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); 3843 if (!ret) { 3844 tp->autoneg = cmd->autoneg; 3845 tp->speed = cmd->speed; 3846 tp->duplex = cmd->duplex; 3847 } 3848 3849 mutex_unlock(&tp->control); 3850 3851 usb_autopm_put_interface(tp->intf); 3852 3853 out: 3854 return ret; 3855 } 3856 3857 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 3858 "tx_packets", 3859 "rx_packets", 3860 "tx_errors", 3861 "rx_errors", 3862 "rx_missed", 3863 "align_errors", 3864 "tx_single_collisions", 3865 "tx_multi_collisions", 3866 "rx_unicast", 3867 "rx_broadcast", 3868 "rx_multicast", 3869 "tx_aborted", 3870 "tx_underrun", 3871 }; 3872 3873 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 3874 { 3875 switch (sset) { 3876 case ETH_SS_STATS: 3877 return ARRAY_SIZE(rtl8152_gstrings); 3878 default: 3879 return -EOPNOTSUPP; 3880 } 3881 } 3882 3883 static void rtl8152_get_ethtool_stats(struct net_device *dev, 3884 struct ethtool_stats *stats, u64 *data) 3885 { 3886 struct r8152 *tp = netdev_priv(dev); 3887 struct tally_counter tally; 3888 3889 if (usb_autopm_get_interface(tp->intf) < 0) 3890 return; 3891 3892 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 3893 3894 usb_autopm_put_interface(tp->intf); 3895 3896 data[0] = le64_to_cpu(tally.tx_packets); 3897 data[1] = le64_to_cpu(tally.rx_packets); 3898 data[2] = le64_to_cpu(tally.tx_errors); 3899 data[3] = le32_to_cpu(tally.rx_errors); 3900 data[4] = le16_to_cpu(tally.rx_missed); 3901 data[5] = le16_to_cpu(tally.align_errors); 3902 data[6] = le32_to_cpu(tally.tx_one_collision); 3903 data[7] = le32_to_cpu(tally.tx_multi_collision); 3904 data[8] = le64_to_cpu(tally.rx_unicast); 3905 data[9] = le64_to_cpu(tally.rx_broadcast); 3906 data[10] = le32_to_cpu(tally.rx_multicast); 3907 data[11] = le16_to_cpu(tally.tx_aborted); 3908 data[12] = le16_to_cpu(tally.tx_underrun); 3909 } 3910 3911 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 3912 { 3913 switch (stringset) { 3914 case ETH_SS_STATS: 3915 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 3916 break; 3917 } 3918 } 3919 3920 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 3921 { 3922 u32 ocp_data, lp, adv, supported = 0; 3923 u16 val; 3924 3925 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 3926 supported = mmd_eee_cap_to_ethtool_sup_t(val); 3927 3928 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 3929 adv = mmd_eee_adv_to_ethtool_adv_t(val); 3930 3931 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 3932 lp = mmd_eee_adv_to_ethtool_adv_t(val); 3933 3934 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3935 ocp_data &= EEE_RX_EN | EEE_TX_EN; 3936 3937 eee->eee_enabled = !!ocp_data; 3938 eee->eee_active = !!(supported & adv & lp); 3939 eee->supported = supported; 3940 eee->advertised = adv; 3941 eee->lp_advertised = lp; 3942 3943 return 0; 3944 } 3945 3946 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 3947 { 3948 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 3949 3950 r8152_eee_en(tp, eee->eee_enabled); 3951 3952 if (!eee->eee_enabled) 3953 val = 0; 3954 3955 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); 3956 3957 return 0; 3958 } 3959 3960 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 3961 { 3962 u32 ocp_data, lp, adv, supported = 0; 3963 u16 val; 3964 3965 val = ocp_reg_read(tp, OCP_EEE_ABLE); 3966 supported = mmd_eee_cap_to_ethtool_sup_t(val); 3967 3968 val = ocp_reg_read(tp, OCP_EEE_ADV); 3969 adv = mmd_eee_adv_to_ethtool_adv_t(val); 3970 3971 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 3972 lp = mmd_eee_adv_to_ethtool_adv_t(val); 3973 3974 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3975 ocp_data &= EEE_RX_EN | EEE_TX_EN; 3976 3977 eee->eee_enabled = !!ocp_data; 3978 eee->eee_active = !!(supported & adv & lp); 3979 eee->supported = supported; 3980 eee->advertised = adv; 3981 eee->lp_advertised = lp; 3982 3983 return 0; 3984 } 3985 3986 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 3987 { 3988 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 3989 3990 r8153_eee_en(tp, eee->eee_enabled); 3991 3992 if (!eee->eee_enabled) 3993 val = 0; 3994 3995 ocp_reg_write(tp, OCP_EEE_ADV, val); 3996 3997 return 0; 3998 } 3999 4000 static int 4001 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) 4002 { 4003 struct r8152 *tp = netdev_priv(net); 4004 int ret; 4005 4006 ret = usb_autopm_get_interface(tp->intf); 4007 if (ret < 0) 4008 goto out; 4009 4010 mutex_lock(&tp->control); 4011 4012 ret = tp->rtl_ops.eee_get(tp, edata); 4013 4014 mutex_unlock(&tp->control); 4015 4016 usb_autopm_put_interface(tp->intf); 4017 4018 out: 4019 return ret; 4020 } 4021 4022 static int 4023 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) 4024 { 4025 struct r8152 *tp = netdev_priv(net); 4026 int ret; 4027 4028 ret = usb_autopm_get_interface(tp->intf); 4029 if (ret < 0) 4030 goto out; 4031 4032 mutex_lock(&tp->control); 4033 4034 ret = tp->rtl_ops.eee_set(tp, edata); 4035 if (!ret) 4036 ret = mii_nway_restart(&tp->mii); 4037 4038 mutex_unlock(&tp->control); 4039 4040 usb_autopm_put_interface(tp->intf); 4041 4042 out: 4043 return ret; 4044 } 4045 4046 static int rtl8152_nway_reset(struct net_device *dev) 4047 { 4048 struct r8152 *tp = netdev_priv(dev); 4049 int ret; 4050 4051 ret = usb_autopm_get_interface(tp->intf); 4052 if (ret < 0) 4053 goto out; 4054 4055 mutex_lock(&tp->control); 4056 4057 ret = mii_nway_restart(&tp->mii); 4058 4059 mutex_unlock(&tp->control); 4060 4061 usb_autopm_put_interface(tp->intf); 4062 4063 out: 4064 return ret; 4065 } 4066 4067 static int rtl8152_get_coalesce(struct net_device *netdev, 4068 struct ethtool_coalesce *coalesce) 4069 { 4070 struct r8152 *tp = netdev_priv(netdev); 4071 4072 switch (tp->version) { 4073 case RTL_VER_01: 4074 case RTL_VER_02: 4075 return -EOPNOTSUPP; 4076 default: 4077 break; 4078 } 4079 4080 coalesce->rx_coalesce_usecs = tp->coalesce; 4081 4082 return 0; 4083 } 4084 4085 static int rtl8152_set_coalesce(struct net_device *netdev, 4086 struct ethtool_coalesce *coalesce) 4087 { 4088 struct r8152 *tp = netdev_priv(netdev); 4089 int ret; 4090 4091 switch (tp->version) { 4092 case RTL_VER_01: 4093 case RTL_VER_02: 4094 return -EOPNOTSUPP; 4095 default: 4096 break; 4097 } 4098 4099 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) 4100 return -EINVAL; 4101 4102 ret = usb_autopm_get_interface(tp->intf); 4103 if (ret < 0) 4104 return ret; 4105 4106 mutex_lock(&tp->control); 4107 4108 if (tp->coalesce != coalesce->rx_coalesce_usecs) { 4109 tp->coalesce = coalesce->rx_coalesce_usecs; 4110 4111 if (netif_running(tp->netdev) && netif_carrier_ok(netdev)) 4112 r8153_set_rx_early_timeout(tp); 4113 } 4114 4115 mutex_unlock(&tp->control); 4116 4117 usb_autopm_put_interface(tp->intf); 4118 4119 return ret; 4120 } 4121 4122 static const struct ethtool_ops ops = { 4123 .get_drvinfo = rtl8152_get_drvinfo, 4124 .get_settings = rtl8152_get_settings, 4125 .set_settings = rtl8152_set_settings, 4126 .get_link = ethtool_op_get_link, 4127 .nway_reset = rtl8152_nway_reset, 4128 .get_msglevel = rtl8152_get_msglevel, 4129 .set_msglevel = rtl8152_set_msglevel, 4130 .get_wol = rtl8152_get_wol, 4131 .set_wol = rtl8152_set_wol, 4132 .get_strings = rtl8152_get_strings, 4133 .get_sset_count = rtl8152_get_sset_count, 4134 .get_ethtool_stats = rtl8152_get_ethtool_stats, 4135 .get_coalesce = rtl8152_get_coalesce, 4136 .set_coalesce = rtl8152_set_coalesce, 4137 .get_eee = rtl_ethtool_get_eee, 4138 .set_eee = rtl_ethtool_set_eee, 4139 }; 4140 4141 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 4142 { 4143 struct r8152 *tp = netdev_priv(netdev); 4144 struct mii_ioctl_data *data = if_mii(rq); 4145 int res; 4146 4147 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4148 return -ENODEV; 4149 4150 res = usb_autopm_get_interface(tp->intf); 4151 if (res < 0) 4152 goto out; 4153 4154 switch (cmd) { 4155 case SIOCGMIIPHY: 4156 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 4157 break; 4158 4159 case SIOCGMIIREG: 4160 mutex_lock(&tp->control); 4161 data->val_out = r8152_mdio_read(tp, data->reg_num); 4162 mutex_unlock(&tp->control); 4163 break; 4164 4165 case SIOCSMIIREG: 4166 if (!capable(CAP_NET_ADMIN)) { 4167 res = -EPERM; 4168 break; 4169 } 4170 mutex_lock(&tp->control); 4171 r8152_mdio_write(tp, data->reg_num, data->val_in); 4172 mutex_unlock(&tp->control); 4173 break; 4174 4175 default: 4176 res = -EOPNOTSUPP; 4177 } 4178 4179 usb_autopm_put_interface(tp->intf); 4180 4181 out: 4182 return res; 4183 } 4184 4185 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 4186 { 4187 struct r8152 *tp = netdev_priv(dev); 4188 int ret; 4189 4190 switch (tp->version) { 4191 case RTL_VER_01: 4192 case RTL_VER_02: 4193 dev->mtu = new_mtu; 4194 return 0; 4195 default: 4196 break; 4197 } 4198 4199 ret = usb_autopm_get_interface(tp->intf); 4200 if (ret < 0) 4201 return ret; 4202 4203 mutex_lock(&tp->control); 4204 4205 dev->mtu = new_mtu; 4206 4207 if (netif_running(dev)) { 4208 u32 rms = new_mtu + VLAN_ETH_HLEN + CRC_SIZE; 4209 4210 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms); 4211 4212 if (netif_carrier_ok(dev)) 4213 r8153_set_rx_early_size(tp); 4214 } 4215 4216 mutex_unlock(&tp->control); 4217 4218 usb_autopm_put_interface(tp->intf); 4219 4220 return ret; 4221 } 4222 4223 static const struct net_device_ops rtl8152_netdev_ops = { 4224 .ndo_open = rtl8152_open, 4225 .ndo_stop = rtl8152_close, 4226 .ndo_do_ioctl = rtl8152_ioctl, 4227 .ndo_start_xmit = rtl8152_start_xmit, 4228 .ndo_tx_timeout = rtl8152_tx_timeout, 4229 .ndo_set_features = rtl8152_set_features, 4230 .ndo_set_rx_mode = rtl8152_set_rx_mode, 4231 .ndo_set_mac_address = rtl8152_set_mac_address, 4232 .ndo_change_mtu = rtl8152_change_mtu, 4233 .ndo_validate_addr = eth_validate_addr, 4234 .ndo_features_check = rtl8152_features_check, 4235 }; 4236 4237 static void r8152b_get_version(struct r8152 *tp) 4238 { 4239 u32 ocp_data; 4240 u16 version; 4241 4242 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); 4243 version = (u16)(ocp_data & VERSION_MASK); 4244 4245 switch (version) { 4246 case 0x4c00: 4247 tp->version = RTL_VER_01; 4248 break; 4249 case 0x4c10: 4250 tp->version = RTL_VER_02; 4251 break; 4252 case 0x5c00: 4253 tp->version = RTL_VER_03; 4254 tp->mii.supports_gmii = 1; 4255 break; 4256 case 0x5c10: 4257 tp->version = RTL_VER_04; 4258 tp->mii.supports_gmii = 1; 4259 break; 4260 case 0x5c20: 4261 tp->version = RTL_VER_05; 4262 tp->mii.supports_gmii = 1; 4263 break; 4264 case 0x5c30: 4265 tp->version = RTL_VER_06; 4266 tp->mii.supports_gmii = 1; 4267 break; 4268 default: 4269 netif_info(tp, probe, tp->netdev, 4270 "Unknown version 0x%04x\n", version); 4271 break; 4272 } 4273 } 4274 4275 static void rtl8152_unload(struct r8152 *tp) 4276 { 4277 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4278 return; 4279 4280 if (tp->version != RTL_VER_01) 4281 r8152_power_cut_en(tp, true); 4282 } 4283 4284 static void rtl8153_unload(struct r8152 *tp) 4285 { 4286 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4287 return; 4288 4289 r8153_power_cut_en(tp, false); 4290 } 4291 4292 static int rtl_ops_init(struct r8152 *tp) 4293 { 4294 struct rtl_ops *ops = &tp->rtl_ops; 4295 int ret = 0; 4296 4297 switch (tp->version) { 4298 case RTL_VER_01: 4299 case RTL_VER_02: 4300 ops->init = r8152b_init; 4301 ops->enable = rtl8152_enable; 4302 ops->disable = rtl8152_disable; 4303 ops->up = rtl8152_up; 4304 ops->down = rtl8152_down; 4305 ops->unload = rtl8152_unload; 4306 ops->eee_get = r8152_get_eee; 4307 ops->eee_set = r8152_set_eee; 4308 ops->in_nway = rtl8152_in_nway; 4309 ops->hw_phy_cfg = r8152b_hw_phy_cfg; 4310 ops->autosuspend_en = rtl_runtime_suspend_enable; 4311 break; 4312 4313 case RTL_VER_03: 4314 case RTL_VER_04: 4315 case RTL_VER_05: 4316 case RTL_VER_06: 4317 ops->init = r8153_init; 4318 ops->enable = rtl8153_enable; 4319 ops->disable = rtl8153_disable; 4320 ops->up = rtl8153_up; 4321 ops->down = rtl8153_down; 4322 ops->unload = rtl8153_unload; 4323 ops->eee_get = r8153_get_eee; 4324 ops->eee_set = r8153_set_eee; 4325 ops->in_nway = rtl8153_in_nway; 4326 ops->hw_phy_cfg = r8153_hw_phy_cfg; 4327 ops->autosuspend_en = rtl8153_runtime_enable; 4328 break; 4329 4330 default: 4331 ret = -ENODEV; 4332 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 4333 break; 4334 } 4335 4336 return ret; 4337 } 4338 4339 static int rtl8152_probe(struct usb_interface *intf, 4340 const struct usb_device_id *id) 4341 { 4342 struct usb_device *udev = interface_to_usbdev(intf); 4343 struct r8152 *tp; 4344 struct net_device *netdev; 4345 int ret; 4346 4347 if (udev->actconfig->desc.bConfigurationValue != 1) { 4348 usb_driver_set_configuration(udev, 1); 4349 return -ENODEV; 4350 } 4351 4352 usb_reset_device(udev); 4353 netdev = alloc_etherdev(sizeof(struct r8152)); 4354 if (!netdev) { 4355 dev_err(&intf->dev, "Out of memory\n"); 4356 return -ENOMEM; 4357 } 4358 4359 SET_NETDEV_DEV(netdev, &intf->dev); 4360 tp = netdev_priv(netdev); 4361 tp->msg_enable = 0x7FFF; 4362 4363 tp->udev = udev; 4364 tp->netdev = netdev; 4365 tp->intf = intf; 4366 4367 r8152b_get_version(tp); 4368 ret = rtl_ops_init(tp); 4369 if (ret) 4370 goto out; 4371 4372 mutex_init(&tp->control); 4373 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 4374 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); 4375 4376 netdev->netdev_ops = &rtl8152_netdev_ops; 4377 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 4378 4379 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 4380 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 4381 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 4382 NETIF_F_HW_VLAN_CTAG_TX; 4383 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 4384 NETIF_F_TSO | NETIF_F_FRAGLIST | 4385 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 4386 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; 4387 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 4388 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 4389 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 4390 4391 if (tp->version == RTL_VER_01) { 4392 netdev->features &= ~NETIF_F_RXCSUM; 4393 netdev->hw_features &= ~NETIF_F_RXCSUM; 4394 } 4395 4396 netdev->ethtool_ops = &ops; 4397 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 4398 4399 /* MTU range: 68 - 1500 or 9194 */ 4400 netdev->min_mtu = ETH_MIN_MTU; 4401 switch (tp->version) { 4402 case RTL_VER_01: 4403 case RTL_VER_02: 4404 netdev->max_mtu = ETH_DATA_LEN; 4405 break; 4406 default: 4407 netdev->max_mtu = RTL8153_MAX_MTU; 4408 break; 4409 } 4410 4411 tp->mii.dev = netdev; 4412 tp->mii.mdio_read = read_mii_word; 4413 tp->mii.mdio_write = write_mii_word; 4414 tp->mii.phy_id_mask = 0x3f; 4415 tp->mii.reg_num_mask = 0x1f; 4416 tp->mii.phy_id = R8152_PHY_ID; 4417 4418 switch (udev->speed) { 4419 case USB_SPEED_SUPER: 4420 case USB_SPEED_SUPER_PLUS: 4421 tp->coalesce = COALESCE_SUPER; 4422 break; 4423 case USB_SPEED_HIGH: 4424 tp->coalesce = COALESCE_HIGH; 4425 break; 4426 default: 4427 tp->coalesce = COALESCE_SLOW; 4428 break; 4429 } 4430 4431 tp->autoneg = AUTONEG_ENABLE; 4432 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100; 4433 tp->duplex = DUPLEX_FULL; 4434 4435 intf->needs_remote_wakeup = 1; 4436 4437 tp->rtl_ops.init(tp); 4438 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 4439 set_ethernet_addr(tp); 4440 4441 usb_set_intfdata(intf, tp); 4442 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); 4443 4444 ret = register_netdev(netdev); 4445 if (ret != 0) { 4446 netif_err(tp, probe, netdev, "couldn't register the device\n"); 4447 goto out1; 4448 } 4449 4450 if (!rtl_can_wakeup(tp)) 4451 __rtl_set_wol(tp, 0); 4452 4453 tp->saved_wolopts = __rtl_get_wol(tp); 4454 if (tp->saved_wolopts) 4455 device_set_wakeup_enable(&udev->dev, true); 4456 else 4457 device_set_wakeup_enable(&udev->dev, false); 4458 4459 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 4460 4461 return 0; 4462 4463 out1: 4464 netif_napi_del(&tp->napi); 4465 usb_set_intfdata(intf, NULL); 4466 out: 4467 free_netdev(netdev); 4468 return ret; 4469 } 4470 4471 static void rtl8152_disconnect(struct usb_interface *intf) 4472 { 4473 struct r8152 *tp = usb_get_intfdata(intf); 4474 4475 usb_set_intfdata(intf, NULL); 4476 if (tp) { 4477 struct usb_device *udev = tp->udev; 4478 4479 if (udev->state == USB_STATE_NOTATTACHED) 4480 set_bit(RTL8152_UNPLUG, &tp->flags); 4481 4482 netif_napi_del(&tp->napi); 4483 unregister_netdev(tp->netdev); 4484 cancel_delayed_work_sync(&tp->hw_phy_work); 4485 tp->rtl_ops.unload(tp); 4486 free_netdev(tp->netdev); 4487 } 4488 } 4489 4490 #define REALTEK_USB_DEVICE(vend, prod) \ 4491 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ 4492 USB_DEVICE_ID_MATCH_INT_CLASS, \ 4493 .idVendor = (vend), \ 4494 .idProduct = (prod), \ 4495 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ 4496 }, \ 4497 { \ 4498 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ 4499 USB_DEVICE_ID_MATCH_DEVICE, \ 4500 .idVendor = (vend), \ 4501 .idProduct = (prod), \ 4502 .bInterfaceClass = USB_CLASS_COMM, \ 4503 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ 4504 .bInterfaceProtocol = USB_CDC_PROTO_NONE 4505 4506 /* table of devices that work with this driver */ 4507 static struct usb_device_id rtl8152_table[] = { 4508 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, 4509 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, 4510 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, 4511 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, 4512 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)}, 4513 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)}, 4514 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, 4515 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)}, 4516 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)}, 4517 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, 4518 {} 4519 }; 4520 4521 MODULE_DEVICE_TABLE(usb, rtl8152_table); 4522 4523 static struct usb_driver rtl8152_driver = { 4524 .name = MODULENAME, 4525 .id_table = rtl8152_table, 4526 .probe = rtl8152_probe, 4527 .disconnect = rtl8152_disconnect, 4528 .suspend = rtl8152_suspend, 4529 .resume = rtl8152_resume, 4530 .reset_resume = rtl8152_reset_resume, 4531 .pre_reset = rtl8152_pre_reset, 4532 .post_reset = rtl8152_post_reset, 4533 .supports_autosuspend = 1, 4534 .disable_hub_initiated_lpm = 1, 4535 }; 4536 4537 module_usb_driver(rtl8152_driver); 4538 4539 MODULE_AUTHOR(DRIVER_AUTHOR); 4540 MODULE_DESCRIPTION(DRIVER_DESC); 4541 MODULE_LICENSE("GPL"); 4542 MODULE_VERSION(DRIVER_VERSION); 4543