xref: /openbmc/linux/drivers/net/usb/r8152.c (revision dbe986bd)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4  */
5 
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
18 #include <linux/ip.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
29 #include <linux/usb/r8152.h>
30 
31 /* Information for net-next */
32 #define NETNEXT_VERSION		"12"
33 
34 /* Information for net */
35 #define NET_VERSION		"11"
36 
37 #define DRIVER_VERSION		"v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
41 
42 #define R8152_PHY_ID		32
43 
44 #define PLA_IDR			0xc000
45 #define PLA_RCR			0xc010
46 #define PLA_RCR1		0xc012
47 #define PLA_RMS			0xc016
48 #define PLA_RXFIFO_CTRL0	0xc0a0
49 #define PLA_RXFIFO_FULL		0xc0a2
50 #define PLA_RXFIFO_CTRL1	0xc0a4
51 #define PLA_RX_FIFO_FULL	0xc0a6
52 #define PLA_RXFIFO_CTRL2	0xc0a8
53 #define PLA_RX_FIFO_EMPTY	0xc0aa
54 #define PLA_DMY_REG0		0xc0b0
55 #define PLA_FMC			0xc0b4
56 #define PLA_CFG_WOL		0xc0b6
57 #define PLA_TEREDO_CFG		0xc0bc
58 #define PLA_TEREDO_WAKE_BASE	0xc0c4
59 #define PLA_MAR			0xcd00
60 #define PLA_BACKUP		0xd000
61 #define PLA_BDC_CR		0xd1a0
62 #define PLA_TEREDO_TIMER	0xd2cc
63 #define PLA_REALWOW_TIMER	0xd2e8
64 #define PLA_UPHY_TIMER		0xd388
65 #define PLA_SUSPEND_FLAG	0xd38a
66 #define PLA_INDICATE_FALG	0xd38c
67 #define PLA_MACDBG_PRE		0xd38c	/* RTL_VER_04 only */
68 #define PLA_MACDBG_POST		0xd38e	/* RTL_VER_04 only */
69 #define PLA_EXTRA_STATUS	0xd398
70 #define PLA_GPHY_CTRL		0xd3ae
71 #define PLA_POL_GPIO_CTRL	0xdc6a
72 #define PLA_EFUSE_DATA		0xdd00
73 #define PLA_EFUSE_CMD		0xdd02
74 #define PLA_LEDSEL		0xdd90
75 #define PLA_LED_FEATURE		0xdd92
76 #define PLA_PHYAR		0xde00
77 #define PLA_BOOT_CTRL		0xe004
78 #define PLA_LWAKE_CTRL_REG	0xe007
79 #define PLA_GPHY_INTR_IMR	0xe022
80 #define PLA_EEE_CR		0xe040
81 #define PLA_EEE_TXTWSYS		0xe04c
82 #define PLA_EEE_TXTWSYS_2P5G	0xe058
83 #define PLA_EEEP_CR		0xe080
84 #define PLA_MAC_PWR_CTRL	0xe0c0
85 #define PLA_MAC_PWR_CTRL2	0xe0ca
86 #define PLA_MAC_PWR_CTRL3	0xe0cc
87 #define PLA_MAC_PWR_CTRL4	0xe0ce
88 #define PLA_WDT6_CTRL		0xe428
89 #define PLA_TCR0		0xe610
90 #define PLA_TCR1		0xe612
91 #define PLA_MTPS		0xe615
92 #define PLA_TXFIFO_CTRL		0xe618
93 #define PLA_TXFIFO_FULL		0xe61a
94 #define PLA_RSTTALLY		0xe800
95 #define PLA_CR			0xe813
96 #define PLA_CRWECR		0xe81c
97 #define PLA_CONFIG12		0xe81e	/* CONFIG1, CONFIG2 */
98 #define PLA_CONFIG34		0xe820	/* CONFIG3, CONFIG4 */
99 #define PLA_CONFIG5		0xe822
100 #define PLA_PHY_PWR		0xe84c
101 #define PLA_OOB_CTRL		0xe84f
102 #define PLA_CPCR		0xe854
103 #define PLA_MISC_0		0xe858
104 #define PLA_MISC_1		0xe85a
105 #define PLA_OCP_GPHY_BASE	0xe86c
106 #define PLA_TALLYCNT		0xe890
107 #define PLA_SFF_STS_7		0xe8de
108 #define PLA_PHYSTATUS		0xe908
109 #define PLA_CONFIG6		0xe90a /* CONFIG6 */
110 #define PLA_USB_CFG		0xe952
111 #define PLA_BP_BA		0xfc26
112 #define PLA_BP_0		0xfc28
113 #define PLA_BP_1		0xfc2a
114 #define PLA_BP_2		0xfc2c
115 #define PLA_BP_3		0xfc2e
116 #define PLA_BP_4		0xfc30
117 #define PLA_BP_5		0xfc32
118 #define PLA_BP_6		0xfc34
119 #define PLA_BP_7		0xfc36
120 #define PLA_BP_EN		0xfc38
121 
122 #define USB_USB2PHY		0xb41e
123 #define USB_SSPHYLINK1		0xb426
124 #define USB_SSPHYLINK2		0xb428
125 #define USB_L1_CTRL		0xb45e
126 #define USB_U2P3_CTRL		0xb460
127 #define USB_CSR_DUMMY1		0xb464
128 #define USB_CSR_DUMMY2		0xb466
129 #define USB_DEV_STAT		0xb808
130 #define USB_CONNECT_TIMER	0xcbf8
131 #define USB_MSC_TIMER		0xcbfc
132 #define USB_BURST_SIZE		0xcfc0
133 #define USB_FW_FIX_EN0		0xcfca
134 #define USB_FW_FIX_EN1		0xcfcc
135 #define USB_LPM_CONFIG		0xcfd8
136 #define USB_ECM_OPTION		0xcfee
137 #define USB_CSTMR		0xcfef	/* RTL8153A */
138 #define USB_MISC_2		0xcfff
139 #define USB_ECM_OP		0xd26b
140 #define USB_GPHY_CTRL		0xd284
141 #define USB_SPEED_OPTION	0xd32a
142 #define USB_FW_CTRL		0xd334	/* RTL8153B */
143 #define USB_FC_TIMER		0xd340
144 #define USB_USB_CTRL		0xd406
145 #define USB_PHY_CTRL		0xd408
146 #define USB_TX_AGG		0xd40a
147 #define USB_RX_BUF_TH		0xd40c
148 #define USB_USB_TIMER		0xd428
149 #define USB_RX_EARLY_TIMEOUT	0xd42c
150 #define USB_RX_EARLY_SIZE	0xd42e
151 #define USB_PM_CTRL_STATUS	0xd432	/* RTL8153A */
152 #define USB_RX_EXTRA_AGGR_TMR	0xd432	/* RTL8153B */
153 #define USB_TX_DMA		0xd434
154 #define USB_UPT_RXDMA_OWN	0xd437
155 #define USB_UPHY3_MDCMDIO	0xd480
156 #define USB_TOLERANCE		0xd490
157 #define USB_LPM_CTRL		0xd41a
158 #define USB_BMU_RESET		0xd4b0
159 #define USB_BMU_CONFIG		0xd4b4
160 #define USB_U1U2_TIMER		0xd4da
161 #define USB_FW_TASK		0xd4e8	/* RTL8153B */
162 #define USB_RX_AGGR_NUM		0xd4ee
163 #define USB_UPS_CTRL		0xd800
164 #define USB_POWER_CUT		0xd80a
165 #define USB_MISC_0		0xd81a
166 #define USB_MISC_1		0xd81f
167 #define USB_AFE_CTRL2		0xd824
168 #define USB_UPHY_XTAL		0xd826
169 #define USB_UPS_CFG		0xd842
170 #define USB_UPS_FLAGS		0xd848
171 #define USB_WDT1_CTRL		0xe404
172 #define USB_WDT11_CTRL		0xe43c
173 #define USB_BP_BA		PLA_BP_BA
174 #define USB_BP_0		PLA_BP_0
175 #define USB_BP_1		PLA_BP_1
176 #define USB_BP_2		PLA_BP_2
177 #define USB_BP_3		PLA_BP_3
178 #define USB_BP_4		PLA_BP_4
179 #define USB_BP_5		PLA_BP_5
180 #define USB_BP_6		PLA_BP_6
181 #define USB_BP_7		PLA_BP_7
182 #define USB_BP_EN		PLA_BP_EN	/* RTL8153A */
183 #define USB_BP_8		0xfc38		/* RTL8153B */
184 #define USB_BP_9		0xfc3a
185 #define USB_BP_10		0xfc3c
186 #define USB_BP_11		0xfc3e
187 #define USB_BP_12		0xfc40
188 #define USB_BP_13		0xfc42
189 #define USB_BP_14		0xfc44
190 #define USB_BP_15		0xfc46
191 #define USB_BP2_EN		0xfc48
192 
193 /* OCP Registers */
194 #define OCP_ALDPS_CONFIG	0x2010
195 #define OCP_EEE_CONFIG1		0x2080
196 #define OCP_EEE_CONFIG2		0x2092
197 #define OCP_EEE_CONFIG3		0x2094
198 #define OCP_BASE_MII		0xa400
199 #define OCP_EEE_AR		0xa41a
200 #define OCP_EEE_DATA		0xa41c
201 #define OCP_PHY_STATUS		0xa420
202 #define OCP_NCTL_CFG		0xa42c
203 #define OCP_POWER_CFG		0xa430
204 #define OCP_EEE_CFG		0xa432
205 #define OCP_SRAM_ADDR		0xa436
206 #define OCP_SRAM_DATA		0xa438
207 #define OCP_DOWN_SPEED		0xa442
208 #define OCP_EEE_ABLE		0xa5c4
209 #define OCP_EEE_ADV		0xa5d0
210 #define OCP_EEE_LPABLE		0xa5d2
211 #define OCP_10GBT_CTRL		0xa5d4
212 #define OCP_10GBT_STAT		0xa5d6
213 #define OCP_EEE_ADV2		0xa6d4
214 #define OCP_PHY_STATE		0xa708		/* nway state for 8153 */
215 #define OCP_PHY_PATCH_STAT	0xb800
216 #define OCP_PHY_PATCH_CMD	0xb820
217 #define OCP_PHY_LOCK		0xb82e
218 #define OCP_ADC_IOFFSET		0xbcfc
219 #define OCP_ADC_CFG		0xbc06
220 #define OCP_SYSCLK_CFG		0xc416
221 
222 /* SRAM Register */
223 #define SRAM_GREEN_CFG		0x8011
224 #define SRAM_LPF_CFG		0x8012
225 #define SRAM_GPHY_FW_VER	0x801e
226 #define SRAM_10M_AMP1		0x8080
227 #define SRAM_10M_AMP2		0x8082
228 #define SRAM_IMPEDANCE		0x8084
229 #define SRAM_PHY_LOCK		0xb82e
230 
231 /* PLA_RCR */
232 #define RCR_AAP			0x00000001
233 #define RCR_APM			0x00000002
234 #define RCR_AM			0x00000004
235 #define RCR_AB			0x00000008
236 #define RCR_ACPT_ALL		(RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
237 #define SLOT_EN			BIT(11)
238 
239 /* PLA_RCR1 */
240 #define OUTER_VLAN		BIT(7)
241 #define INNER_VLAN		BIT(6)
242 
243 /* PLA_RXFIFO_CTRL0 */
244 #define RXFIFO_THR1_NORMAL	0x00080002
245 #define RXFIFO_THR1_OOB		0x01800003
246 
247 /* PLA_RXFIFO_FULL */
248 #define RXFIFO_FULL_MASK	0xfff
249 
250 /* PLA_RXFIFO_CTRL1 */
251 #define RXFIFO_THR2_FULL	0x00000060
252 #define RXFIFO_THR2_HIGH	0x00000038
253 #define RXFIFO_THR2_OOB		0x0000004a
254 #define RXFIFO_THR2_NORMAL	0x00a0
255 
256 /* PLA_RXFIFO_CTRL2 */
257 #define RXFIFO_THR3_FULL	0x00000078
258 #define RXFIFO_THR3_HIGH	0x00000048
259 #define RXFIFO_THR3_OOB		0x0000005a
260 #define RXFIFO_THR3_NORMAL	0x0110
261 
262 /* PLA_TXFIFO_CTRL */
263 #define TXFIFO_THR_NORMAL	0x00400008
264 #define TXFIFO_THR_NORMAL2	0x01000008
265 
266 /* PLA_DMY_REG0 */
267 #define ECM_ALDPS		0x0002
268 
269 /* PLA_FMC */
270 #define FMC_FCR_MCU_EN		0x0001
271 
272 /* PLA_EEEP_CR */
273 #define EEEP_CR_EEEP_TX		0x0002
274 
275 /* PLA_WDT6_CTRL */
276 #define WDT6_SET_MODE		0x0010
277 
278 /* PLA_TCR0 */
279 #define TCR0_TX_EMPTY		0x0800
280 #define TCR0_AUTO_FIFO		0x0080
281 
282 /* PLA_TCR1 */
283 #define VERSION_MASK		0x7cf0
284 #define IFG_MASK		(BIT(3) | BIT(9) | BIT(8))
285 #define IFG_144NS		BIT(9)
286 #define IFG_96NS		(BIT(9) | BIT(8))
287 
288 /* PLA_MTPS */
289 #define MTPS_JUMBO		(12 * 1024 / 64)
290 #define MTPS_DEFAULT		(6 * 1024 / 64)
291 
292 /* PLA_RSTTALLY */
293 #define TALLY_RESET		0x0001
294 
295 /* PLA_CR */
296 #define CR_RST			0x10
297 #define CR_RE			0x08
298 #define CR_TE			0x04
299 
300 /* PLA_CRWECR */
301 #define CRWECR_NORAML		0x00
302 #define CRWECR_CONFIG		0xc0
303 
304 /* PLA_OOB_CTRL */
305 #define NOW_IS_OOB		0x80
306 #define TXFIFO_EMPTY		0x20
307 #define RXFIFO_EMPTY		0x10
308 #define LINK_LIST_READY		0x02
309 #define DIS_MCU_CLROOB		0x01
310 #define FIFO_EMPTY		(TXFIFO_EMPTY | RXFIFO_EMPTY)
311 
312 /* PLA_MISC_1 */
313 #define RXDY_GATED_EN		0x0008
314 
315 /* PLA_SFF_STS_7 */
316 #define RE_INIT_LL		0x8000
317 #define MCU_BORW_EN		0x4000
318 
319 /* PLA_CPCR */
320 #define FLOW_CTRL_EN		BIT(0)
321 #define CPCR_RX_VLAN		0x0040
322 
323 /* PLA_CFG_WOL */
324 #define MAGIC_EN		0x0001
325 
326 /* PLA_TEREDO_CFG */
327 #define TEREDO_SEL		0x8000
328 #define TEREDO_WAKE_MASK	0x7f00
329 #define TEREDO_RS_EVENT_MASK	0x00fe
330 #define OOB_TEREDO_EN		0x0001
331 
332 /* PLA_BDC_CR */
333 #define ALDPS_PROXY_MODE	0x0001
334 
335 /* PLA_EFUSE_CMD */
336 #define EFUSE_READ_CMD		BIT(15)
337 #define EFUSE_DATA_BIT16	BIT(7)
338 
339 /* PLA_CONFIG34 */
340 #define LINK_ON_WAKE_EN		0x0010
341 #define LINK_OFF_WAKE_EN	0x0008
342 
343 /* PLA_CONFIG6 */
344 #define LANWAKE_CLR_EN		BIT(0)
345 
346 /* PLA_USB_CFG */
347 #define EN_XG_LIP		BIT(1)
348 #define EN_G_LIP		BIT(2)
349 
350 /* PLA_CONFIG5 */
351 #define BWF_EN			0x0040
352 #define MWF_EN			0x0020
353 #define UWF_EN			0x0010
354 #define LAN_WAKE_EN		0x0002
355 
356 /* PLA_LED_FEATURE */
357 #define LED_MODE_MASK		0x0700
358 
359 /* PLA_PHY_PWR */
360 #define TX_10M_IDLE_EN		0x0080
361 #define PFM_PWM_SWITCH		0x0040
362 #define TEST_IO_OFF		BIT(4)
363 
364 /* PLA_MAC_PWR_CTRL */
365 #define D3_CLK_GATED_EN		0x00004000
366 #define MCU_CLK_RATIO		0x07010f07
367 #define MCU_CLK_RATIO_MASK	0x0f0f0f0f
368 #define ALDPS_SPDWN_RATIO	0x0f87
369 
370 /* PLA_MAC_PWR_CTRL2 */
371 #define EEE_SPDWN_RATIO		0x8007
372 #define MAC_CLK_SPDWN_EN	BIT(15)
373 #define EEE_SPDWN_RATIO_MASK	0xff
374 
375 /* PLA_MAC_PWR_CTRL3 */
376 #define PLA_MCU_SPDWN_EN	BIT(14)
377 #define PKT_AVAIL_SPDWN_EN	0x0100
378 #define SUSPEND_SPDWN_EN	0x0004
379 #define U1U2_SPDWN_EN		0x0002
380 #define L1_SPDWN_EN		0x0001
381 
382 /* PLA_MAC_PWR_CTRL4 */
383 #define PWRSAVE_SPDWN_EN	0x1000
384 #define RXDV_SPDWN_EN		0x0800
385 #define TX10MIDLE_EN		0x0100
386 #define IDLE_SPDWN_EN		BIT(6)
387 #define TP100_SPDWN_EN		0x0020
388 #define TP500_SPDWN_EN		0x0010
389 #define TP1000_SPDWN_EN		0x0008
390 #define EEE_SPDWN_EN		0x0001
391 
392 /* PLA_GPHY_INTR_IMR */
393 #define GPHY_STS_MSK		0x0001
394 #define SPEED_DOWN_MSK		0x0002
395 #define SPDWN_RXDV_MSK		0x0004
396 #define SPDWN_LINKCHG_MSK	0x0008
397 
398 /* PLA_PHYAR */
399 #define PHYAR_FLAG		0x80000000
400 
401 /* PLA_EEE_CR */
402 #define EEE_RX_EN		0x0001
403 #define EEE_TX_EN		0x0002
404 
405 /* PLA_BOOT_CTRL */
406 #define AUTOLOAD_DONE		0x0002
407 
408 /* PLA_LWAKE_CTRL_REG */
409 #define LANWAKE_PIN		BIT(7)
410 
411 /* PLA_SUSPEND_FLAG */
412 #define LINK_CHG_EVENT		BIT(0)
413 
414 /* PLA_INDICATE_FALG */
415 #define UPCOMING_RUNTIME_D3	BIT(0)
416 
417 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
418 #define DEBUG_OE		BIT(0)
419 #define DEBUG_LTSSM		0x0082
420 
421 /* PLA_EXTRA_STATUS */
422 #define CUR_LINK_OK		BIT(15)
423 #define U3P3_CHECK_EN		BIT(7)	/* RTL_VER_05 only */
424 #define LINK_CHANGE_FLAG	BIT(8)
425 #define POLL_LINK_CHG		BIT(0)
426 
427 /* PLA_GPHY_CTRL */
428 #define GPHY_FLASH		BIT(1)
429 
430 /* PLA_POL_GPIO_CTRL */
431 #define DACK_DET_EN		BIT(15)
432 #define POL_GPHY_PATCH		BIT(4)
433 
434 /* USB_USB2PHY */
435 #define USB2PHY_SUSPEND		0x0001
436 #define USB2PHY_L1		0x0002
437 
438 /* USB_SSPHYLINK1 */
439 #define DELAY_PHY_PWR_CHG	BIT(1)
440 
441 /* USB_SSPHYLINK2 */
442 #define pwd_dn_scale_mask	0x3ffe
443 #define pwd_dn_scale(x)		((x) << 1)
444 
445 /* USB_CSR_DUMMY1 */
446 #define DYNAMIC_BURST		0x0001
447 
448 /* USB_CSR_DUMMY2 */
449 #define EP4_FULL_FC		0x0001
450 
451 /* USB_DEV_STAT */
452 #define STAT_SPEED_MASK		0x0006
453 #define STAT_SPEED_HIGH		0x0000
454 #define STAT_SPEED_FULL		0x0002
455 
456 /* USB_FW_FIX_EN0 */
457 #define FW_FIX_SUSPEND		BIT(14)
458 
459 /* USB_FW_FIX_EN1 */
460 #define FW_IP_RESET_EN		BIT(9)
461 
462 /* USB_LPM_CONFIG */
463 #define LPM_U1U2_EN		BIT(0)
464 
465 /* USB_TX_AGG */
466 #define TX_AGG_MAX_THRESHOLD	0x03
467 
468 /* USB_RX_BUF_TH */
469 #define RX_THR_SUPPER		0x0c350180
470 #define RX_THR_HIGH		0x7a120180
471 #define RX_THR_SLOW		0xffff0180
472 #define RX_THR_B		0x00010001
473 
474 /* USB_TX_DMA */
475 #define TEST_MODE_DISABLE	0x00000001
476 #define TX_SIZE_ADJUST1		0x00000100
477 
478 /* USB_BMU_RESET */
479 #define BMU_RESET_EP_IN		0x01
480 #define BMU_RESET_EP_OUT	0x02
481 
482 /* USB_BMU_CONFIG */
483 #define ACT_ODMA		BIT(1)
484 
485 /* USB_UPT_RXDMA_OWN */
486 #define OWN_UPDATE		BIT(0)
487 #define OWN_CLEAR		BIT(1)
488 
489 /* USB_FW_TASK */
490 #define FC_PATCH_TASK		BIT(1)
491 
492 /* USB_RX_AGGR_NUM */
493 #define RX_AGGR_NUM_MASK	0x1ff
494 
495 /* USB_UPS_CTRL */
496 #define POWER_CUT		0x0100
497 
498 /* USB_PM_CTRL_STATUS */
499 #define RESUME_INDICATE		0x0001
500 
501 /* USB_ECM_OPTION */
502 #define BYPASS_MAC_RESET	BIT(5)
503 
504 /* USB_CSTMR */
505 #define FORCE_SUPER		BIT(0)
506 
507 /* USB_MISC_2 */
508 #define UPS_FORCE_PWR_DOWN	BIT(0)
509 
510 /* USB_ECM_OP */
511 #define	EN_ALL_SPEED		BIT(0)
512 
513 /* USB_GPHY_CTRL */
514 #define GPHY_PATCH_DONE		BIT(2)
515 #define BYPASS_FLASH		BIT(5)
516 #define BACKUP_RESTRORE		BIT(6)
517 
518 /* USB_SPEED_OPTION */
519 #define RG_PWRDN_EN		BIT(8)
520 #define ALL_SPEED_OFF		BIT(9)
521 
522 /* USB_FW_CTRL */
523 #define FLOW_CTRL_PATCH_OPT	BIT(1)
524 #define AUTO_SPEEDUP		BIT(3)
525 #define FLOW_CTRL_PATCH_2	BIT(8)
526 
527 /* USB_FC_TIMER */
528 #define CTRL_TIMER_EN		BIT(15)
529 
530 /* USB_USB_CTRL */
531 #define CDC_ECM_EN		BIT(3)
532 #define RX_AGG_DISABLE		0x0010
533 #define RX_ZERO_EN		0x0080
534 
535 /* USB_U2P3_CTRL */
536 #define U2P3_ENABLE		0x0001
537 #define RX_DETECT8		BIT(3)
538 
539 /* USB_POWER_CUT */
540 #define PWR_EN			0x0001
541 #define PHASE2_EN		0x0008
542 #define UPS_EN			BIT(4)
543 #define USP_PREWAKE		BIT(5)
544 
545 /* USB_MISC_0 */
546 #define PCUT_STATUS		0x0001
547 
548 /* USB_RX_EARLY_TIMEOUT */
549 #define COALESCE_SUPER		 85000U
550 #define COALESCE_HIGH		250000U
551 #define COALESCE_SLOW		524280U
552 
553 /* USB_WDT1_CTRL */
554 #define WTD1_EN			BIT(0)
555 
556 /* USB_WDT11_CTRL */
557 #define TIMER11_EN		0x0001
558 
559 /* USB_LPM_CTRL */
560 /* bit 4 ~ 5: fifo empty boundary */
561 #define FIFO_EMPTY_1FB		0x30	/* 0x1fb * 64 = 32448 bytes */
562 /* bit 2 ~ 3: LMP timer */
563 #define LPM_TIMER_MASK		0x0c
564 #define LPM_TIMER_500MS		0x04	/* 500 ms */
565 #define LPM_TIMER_500US		0x0c	/* 500 us */
566 #define ROK_EXIT_LPM		0x02
567 
568 /* USB_AFE_CTRL2 */
569 #define SEN_VAL_MASK		0xf800
570 #define SEN_VAL_NORMAL		0xa000
571 #define SEL_RXIDLE		0x0100
572 
573 /* USB_UPHY_XTAL */
574 #define OOBS_POLLING		BIT(8)
575 
576 /* USB_UPS_CFG */
577 #define SAW_CNT_1MS_MASK	0x0fff
578 #define MID_REVERSE		BIT(5)	/* RTL8156A */
579 
580 /* USB_UPS_FLAGS */
581 #define UPS_FLAGS_R_TUNE		BIT(0)
582 #define UPS_FLAGS_EN_10M_CKDIV		BIT(1)
583 #define UPS_FLAGS_250M_CKDIV		BIT(2)
584 #define UPS_FLAGS_EN_ALDPS		BIT(3)
585 #define UPS_FLAGS_CTAP_SHORT_DIS	BIT(4)
586 #define UPS_FLAGS_SPEED_MASK		(0xf << 16)
587 #define ups_flags_speed(x)		((x) << 16)
588 #define UPS_FLAGS_EN_EEE		BIT(20)
589 #define UPS_FLAGS_EN_500M_EEE		BIT(21)
590 #define UPS_FLAGS_EN_EEE_CKDIV		BIT(22)
591 #define UPS_FLAGS_EEE_PLLOFF_100	BIT(23)
592 #define UPS_FLAGS_EEE_PLLOFF_GIGA	BIT(24)
593 #define UPS_FLAGS_EEE_CMOD_LV_EN	BIT(25)
594 #define UPS_FLAGS_EN_GREEN		BIT(26)
595 #define UPS_FLAGS_EN_FLOW_CTR		BIT(27)
596 
597 enum spd_duplex {
598 	NWAY_10M_HALF,
599 	NWAY_10M_FULL,
600 	NWAY_100M_HALF,
601 	NWAY_100M_FULL,
602 	NWAY_1000M_FULL,
603 	FORCE_10M_HALF,
604 	FORCE_10M_FULL,
605 	FORCE_100M_HALF,
606 	FORCE_100M_FULL,
607 	FORCE_1000M_FULL,
608 	NWAY_2500M_FULL,
609 };
610 
611 /* OCP_ALDPS_CONFIG */
612 #define ENPWRSAVE		0x8000
613 #define ENPDNPS			0x0200
614 #define LINKENA			0x0100
615 #define DIS_SDSAVE		0x0010
616 
617 /* OCP_PHY_STATUS */
618 #define PHY_STAT_MASK		0x0007
619 #define PHY_STAT_EXT_INIT	2
620 #define PHY_STAT_LAN_ON		3
621 #define PHY_STAT_PWRDN		5
622 
623 /* OCP_NCTL_CFG */
624 #define PGA_RETURN_EN		BIT(1)
625 
626 /* OCP_POWER_CFG */
627 #define EEE_CLKDIV_EN		0x8000
628 #define EN_ALDPS		0x0004
629 #define EN_10M_PLLOFF		0x0001
630 
631 /* OCP_EEE_CONFIG1 */
632 #define RG_TXLPI_MSK_HFDUP	0x8000
633 #define RG_MATCLR_EN		0x4000
634 #define EEE_10_CAP		0x2000
635 #define EEE_NWAY_EN		0x1000
636 #define TX_QUIET_EN		0x0200
637 #define RX_QUIET_EN		0x0100
638 #define sd_rise_time_mask	0x0070
639 #define sd_rise_time(x)		(min(x, 7) << 4)	/* bit 4 ~ 6 */
640 #define RG_RXLPI_MSK_HFDUP	0x0008
641 #define SDFALLTIME		0x0007	/* bit 0 ~ 2 */
642 
643 /* OCP_EEE_CONFIG2 */
644 #define RG_LPIHYS_NUM		0x7000	/* bit 12 ~ 15 */
645 #define RG_DACQUIET_EN		0x0400
646 #define RG_LDVQUIET_EN		0x0200
647 #define RG_CKRSEL		0x0020
648 #define RG_EEEPRG_EN		0x0010
649 
650 /* OCP_EEE_CONFIG3 */
651 #define fast_snr_mask		0xff80
652 #define fast_snr(x)		(min(x, 0x1ff) << 7)	/* bit 7 ~ 15 */
653 #define RG_LFS_SEL		0x0060	/* bit 6 ~ 5 */
654 #define MSK_PH			0x0006	/* bit 0 ~ 3 */
655 
656 /* OCP_EEE_AR */
657 /* bit[15:14] function */
658 #define FUN_ADDR		0x0000
659 #define FUN_DATA		0x4000
660 /* bit[4:0] device addr */
661 
662 /* OCP_EEE_CFG */
663 #define CTAP_SHORT_EN		0x0040
664 #define EEE10_EN		0x0010
665 
666 /* OCP_DOWN_SPEED */
667 #define EN_EEE_CMODE		BIT(14)
668 #define EN_EEE_1000		BIT(13)
669 #define EN_EEE_100		BIT(12)
670 #define EN_10M_CLKDIV		BIT(11)
671 #define EN_10M_BGOFF		0x0080
672 
673 /* OCP_10GBT_CTRL */
674 #define RTL_ADV2_5G_F_R		BIT(5)	/* Advertise 2.5GBASE-T fast-retrain */
675 
676 /* OCP_PHY_STATE */
677 #define TXDIS_STATE		0x01
678 #define ABD_STATE		0x02
679 
680 /* OCP_PHY_PATCH_STAT */
681 #define PATCH_READY		BIT(6)
682 
683 /* OCP_PHY_PATCH_CMD */
684 #define PATCH_REQUEST		BIT(4)
685 
686 /* OCP_PHY_LOCK */
687 #define PATCH_LOCK		BIT(0)
688 
689 /* OCP_ADC_CFG */
690 #define CKADSEL_L		0x0100
691 #define ADC_EN			0x0080
692 #define EN_EMI_L		0x0040
693 
694 /* OCP_SYSCLK_CFG */
695 #define sysclk_div_expo(x)	(min(x, 5) << 8)
696 #define clk_div_expo(x)		(min(x, 5) << 4)
697 
698 /* SRAM_GREEN_CFG */
699 #define GREEN_ETH_EN		BIT(15)
700 #define R_TUNE_EN		BIT(11)
701 
702 /* SRAM_LPF_CFG */
703 #define LPF_AUTO_TUNE		0x8000
704 
705 /* SRAM_10M_AMP1 */
706 #define GDAC_IB_UPALL		0x0008
707 
708 /* SRAM_10M_AMP2 */
709 #define AMP_DN			0x0200
710 
711 /* SRAM_IMPEDANCE */
712 #define RX_DRIVING_MASK		0x6000
713 
714 /* SRAM_PHY_LOCK */
715 #define PHY_PATCH_LOCK		0x0001
716 
717 /* MAC PASSTHRU */
718 #define AD_MASK			0xfee0
719 #define BND_MASK		0x0004
720 #define BD_MASK			0x0001
721 #define EFUSE			0xcfdb
722 #define PASS_THRU_MASK		0x1
723 
724 #define BP4_SUPER_ONLY		0x1578	/* RTL_VER_04 only */
725 
726 enum rtl_register_content {
727 	_2500bps	= BIT(10),
728 	_1250bps	= BIT(9),
729 	_500bps		= BIT(8),
730 	_tx_flow	= BIT(6),
731 	_rx_flow	= BIT(5),
732 	_1000bps	= 0x10,
733 	_100bps		= 0x08,
734 	_10bps		= 0x04,
735 	LINK_STATUS	= 0x02,
736 	FULL_DUP	= 0x01,
737 };
738 
739 #define is_speed_2500(_speed)	(((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
740 #define is_flow_control(_speed)	(((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
741 
742 #define RTL8152_MAX_TX		4
743 #define RTL8152_MAX_RX		10
744 #define INTBUFSIZE		2
745 #define TX_ALIGN		4
746 #define RX_ALIGN		8
747 
748 #define RTL8152_RX_MAX_PENDING	4096
749 #define RTL8152_RXFG_HEADSZ	256
750 
751 #define INTR_LINK		0x0004
752 
753 #define RTL8152_RMS		(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
754 #define RTL8153_RMS		RTL8153_MAX_PACKET
755 #define RTL8152_TX_TIMEOUT	(5 * HZ)
756 #define mtu_to_size(m)		((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
757 #define size_to_mtu(s)		((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
758 #define rx_reserved_size(x)	(mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
759 
760 /* rtl8152 flags */
761 enum rtl8152_flags {
762 	RTL8152_UNPLUG = 0,
763 	RTL8152_SET_RX_MODE,
764 	WORK_ENABLE,
765 	RTL8152_LINK_CHG,
766 	SELECTIVE_SUSPEND,
767 	PHY_RESET,
768 	SCHEDULE_TASKLET,
769 	GREEN_ETHERNET,
770 };
771 
772 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2	0x3082
773 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2		0xa387
774 
775 struct tally_counter {
776 	__le64	tx_packets;
777 	__le64	rx_packets;
778 	__le64	tx_errors;
779 	__le32	rx_errors;
780 	__le16	rx_missed;
781 	__le16	align_errors;
782 	__le32	tx_one_collision;
783 	__le32	tx_multi_collision;
784 	__le64	rx_unicast;
785 	__le64	rx_broadcast;
786 	__le32	rx_multicast;
787 	__le16	tx_aborted;
788 	__le16	tx_underrun;
789 };
790 
791 struct rx_desc {
792 	__le32 opts1;
793 #define RX_LEN_MASK			0x7fff
794 
795 	__le32 opts2;
796 #define RD_UDP_CS			BIT(23)
797 #define RD_TCP_CS			BIT(22)
798 #define RD_IPV6_CS			BIT(20)
799 #define RD_IPV4_CS			BIT(19)
800 
801 	__le32 opts3;
802 #define IPF				BIT(23) /* IP checksum fail */
803 #define UDPF				BIT(22) /* UDP checksum fail */
804 #define TCPF				BIT(21) /* TCP checksum fail */
805 #define RX_VLAN_TAG			BIT(16)
806 
807 	__le32 opts4;
808 	__le32 opts5;
809 	__le32 opts6;
810 };
811 
812 struct tx_desc {
813 	__le32 opts1;
814 #define TX_FS			BIT(31) /* First segment of a packet */
815 #define TX_LS			BIT(30) /* Final segment of a packet */
816 #define GTSENDV4		BIT(28)
817 #define GTSENDV6		BIT(27)
818 #define GTTCPHO_SHIFT		18
819 #define GTTCPHO_MAX		0x7fU
820 #define TX_LEN_MAX		0x3ffffU
821 
822 	__le32 opts2;
823 #define UDP_CS			BIT(31) /* Calculate UDP/IP checksum */
824 #define TCP_CS			BIT(30) /* Calculate TCP/IP checksum */
825 #define IPV4_CS			BIT(29) /* Calculate IPv4 checksum */
826 #define IPV6_CS			BIT(28) /* Calculate IPv6 checksum */
827 #define MSS_SHIFT		17
828 #define MSS_MAX			0x7ffU
829 #define TCPHO_SHIFT		17
830 #define TCPHO_MAX		0x7ffU
831 #define TX_VLAN_TAG		BIT(16)
832 };
833 
834 struct r8152;
835 
836 struct rx_agg {
837 	struct list_head list, info_list;
838 	struct urb *urb;
839 	struct r8152 *context;
840 	struct page *page;
841 	void *buffer;
842 };
843 
844 struct tx_agg {
845 	struct list_head list;
846 	struct urb *urb;
847 	struct r8152 *context;
848 	void *buffer;
849 	void *head;
850 	u32 skb_num;
851 	u32 skb_len;
852 };
853 
854 struct r8152 {
855 	unsigned long flags;
856 	struct usb_device *udev;
857 	struct napi_struct napi;
858 	struct usb_interface *intf;
859 	struct net_device *netdev;
860 	struct urb *intr_urb;
861 	struct tx_agg tx_info[RTL8152_MAX_TX];
862 	struct list_head rx_info, rx_used;
863 	struct list_head rx_done, tx_free;
864 	struct sk_buff_head tx_queue, rx_queue;
865 	spinlock_t rx_lock, tx_lock;
866 	struct delayed_work schedule, hw_phy_work;
867 	struct mii_if_info mii;
868 	struct mutex control;	/* use for hw setting */
869 #ifdef CONFIG_PM_SLEEP
870 	struct notifier_block pm_notifier;
871 #endif
872 	struct tasklet_struct tx_tl;
873 
874 	struct rtl_ops {
875 		void (*init)(struct r8152 *tp);
876 		int (*enable)(struct r8152 *tp);
877 		void (*disable)(struct r8152 *tp);
878 		void (*up)(struct r8152 *tp);
879 		void (*down)(struct r8152 *tp);
880 		void (*unload)(struct r8152 *tp);
881 		int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
882 		int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
883 		bool (*in_nway)(struct r8152 *tp);
884 		void (*hw_phy_cfg)(struct r8152 *tp);
885 		void (*autosuspend_en)(struct r8152 *tp, bool enable);
886 		void (*change_mtu)(struct r8152 *tp);
887 	} rtl_ops;
888 
889 	struct ups_info {
890 		u32 r_tune:1;
891 		u32 _10m_ckdiv:1;
892 		u32 _250m_ckdiv:1;
893 		u32 aldps:1;
894 		u32 lite_mode:2;
895 		u32 speed_duplex:4;
896 		u32 eee:1;
897 		u32 eee_lite:1;
898 		u32 eee_ckdiv:1;
899 		u32 eee_plloff_100:1;
900 		u32 eee_plloff_giga:1;
901 		u32 eee_cmod_lv:1;
902 		u32 green:1;
903 		u32 flow_control:1;
904 		u32 ctap_short_off:1;
905 	} ups_info;
906 
907 #define RTL_VER_SIZE		32
908 
909 	struct rtl_fw {
910 		const char *fw_name;
911 		const struct firmware *fw;
912 
913 		char version[RTL_VER_SIZE];
914 		int (*pre_fw)(struct r8152 *tp);
915 		int (*post_fw)(struct r8152 *tp);
916 
917 		bool retry;
918 	} rtl_fw;
919 
920 	atomic_t rx_count;
921 
922 	bool eee_en;
923 	int intr_interval;
924 	u32 saved_wolopts;
925 	u32 msg_enable;
926 	u32 tx_qlen;
927 	u32 coalesce;
928 	u32 advertising;
929 	u32 rx_buf_sz;
930 	u32 rx_copybreak;
931 	u32 rx_pending;
932 	u32 fc_pause_on, fc_pause_off;
933 
934 	unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out;
935 
936 	u32 support_2500full:1;
937 	u32 lenovo_macpassthru:1;
938 	u32 dell_tb_rx_agg_bug:1;
939 	u16 ocp_base;
940 	u16 speed;
941 	u16 eee_adv;
942 	u8 *intr_buff;
943 	u8 version;
944 	u8 duplex;
945 	u8 autoneg;
946 };
947 
948 /**
949  * struct fw_block - block type and total length
950  * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
951  *	RTL_FW_USB and so on.
952  * @length: total length of the current block.
953  */
954 struct fw_block {
955 	__le32 type;
956 	__le32 length;
957 } __packed;
958 
959 /**
960  * struct fw_header - header of the firmware file
961  * @checksum: checksum of sha256 which is calculated from the whole file
962  *	except the checksum field of the file. That is, calculate sha256
963  *	from the version field to the end of the file.
964  * @version: version of this firmware.
965  * @blocks: the first firmware block of the file
966  */
967 struct fw_header {
968 	u8 checksum[32];
969 	char version[RTL_VER_SIZE];
970 	struct fw_block blocks[];
971 } __packed;
972 
973 enum rtl8152_fw_flags {
974 	FW_FLAGS_USB = 0,
975 	FW_FLAGS_PLA,
976 	FW_FLAGS_START,
977 	FW_FLAGS_STOP,
978 	FW_FLAGS_NC,
979 	FW_FLAGS_NC1,
980 	FW_FLAGS_NC2,
981 	FW_FLAGS_UC2,
982 	FW_FLAGS_UC,
983 	FW_FLAGS_SPEED_UP,
984 	FW_FLAGS_VER,
985 };
986 
987 enum rtl8152_fw_fixup_cmd {
988 	FW_FIXUP_AND = 0,
989 	FW_FIXUP_OR,
990 	FW_FIXUP_NOT,
991 	FW_FIXUP_XOR,
992 };
993 
994 struct fw_phy_set {
995 	__le16 addr;
996 	__le16 data;
997 } __packed;
998 
999 struct fw_phy_speed_up {
1000 	struct fw_block blk_hdr;
1001 	__le16 fw_offset;
1002 	__le16 version;
1003 	__le16 fw_reg;
1004 	__le16 reserved;
1005 	char info[];
1006 } __packed;
1007 
1008 struct fw_phy_ver {
1009 	struct fw_block blk_hdr;
1010 	struct fw_phy_set ver;
1011 	__le32 reserved;
1012 } __packed;
1013 
1014 struct fw_phy_fixup {
1015 	struct fw_block blk_hdr;
1016 	struct fw_phy_set setting;
1017 	__le16 bit_cmd;
1018 	__le16 reserved;
1019 } __packed;
1020 
1021 struct fw_phy_union {
1022 	struct fw_block blk_hdr;
1023 	__le16 fw_offset;
1024 	__le16 fw_reg;
1025 	struct fw_phy_set pre_set[2];
1026 	struct fw_phy_set bp[8];
1027 	struct fw_phy_set bp_en;
1028 	u8 pre_num;
1029 	u8 bp_num;
1030 	char info[];
1031 } __packed;
1032 
1033 /**
1034  * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
1035  *	The layout of the firmware block is:
1036  *	<struct fw_mac> + <info> + <firmware data>.
1037  * @blk_hdr: firmware descriptor (type, length)
1038  * @fw_offset: offset of the firmware binary data. The start address of
1039  *	the data would be the address of struct fw_mac + @fw_offset.
1040  * @fw_reg: the register to load the firmware. Depends on chip.
1041  * @bp_ba_addr: the register to write break point base address. Depends on
1042  *	chip.
1043  * @bp_ba_value: break point base address. Depends on chip.
1044  * @bp_en_addr: the register to write break point enabled mask. Depends
1045  *	on chip.
1046  * @bp_en_value: break point enabled mask. Depends on the firmware.
1047  * @bp_start: the start register of break points. Depends on chip.
1048  * @bp_num: the break point number which needs to be set for this firmware.
1049  *	Depends on the firmware.
1050  * @bp: break points. Depends on firmware.
1051  * @reserved: reserved space (unused)
1052  * @fw_ver_reg: the register to store the fw version.
1053  * @fw_ver_data: the firmware version of the current type.
1054  * @info: additional information for debugging, and is followed by the
1055  *	binary data of firmware.
1056  */
1057 struct fw_mac {
1058 	struct fw_block blk_hdr;
1059 	__le16 fw_offset;
1060 	__le16 fw_reg;
1061 	__le16 bp_ba_addr;
1062 	__le16 bp_ba_value;
1063 	__le16 bp_en_addr;
1064 	__le16 bp_en_value;
1065 	__le16 bp_start;
1066 	__le16 bp_num;
1067 	__le16 bp[16]; /* any value determined by firmware */
1068 	__le32 reserved;
1069 	__le16 fw_ver_reg;
1070 	u8 fw_ver_data;
1071 	char info[];
1072 } __packed;
1073 
1074 /**
1075  * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
1076  *	This is used to set patch key when loading the firmware of PHY.
1077  * @blk_hdr: firmware descriptor (type, length)
1078  * @key_reg: the register to write the patch key.
1079  * @key_data: patch key.
1080  * @reserved: reserved space (unused)
1081  */
1082 struct fw_phy_patch_key {
1083 	struct fw_block blk_hdr;
1084 	__le16 key_reg;
1085 	__le16 key_data;
1086 	__le32 reserved;
1087 } __packed;
1088 
1089 /**
1090  * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
1091  *	The layout of the firmware block is:
1092  *	<struct fw_phy_nc> + <info> + <firmware data>.
1093  * @blk_hdr: firmware descriptor (type, length)
1094  * @fw_offset: offset of the firmware binary data. The start address of
1095  *	the data would be the address of struct fw_phy_nc + @fw_offset.
1096  * @fw_reg: the register to load the firmware. Depends on chip.
1097  * @ba_reg: the register to write the base address. Depends on chip.
1098  * @ba_data: base address. Depends on chip.
1099  * @patch_en_addr: the register of enabling patch mode. Depends on chip.
1100  * @patch_en_value: patch mode enabled mask. Depends on the firmware.
1101  * @mode_reg: the regitster of switching the mode.
1102  * @mode_pre: the mode needing to be set before loading the firmware.
1103  * @mode_post: the mode to be set when finishing to load the firmware.
1104  * @reserved: reserved space (unused)
1105  * @bp_start: the start register of break points. Depends on chip.
1106  * @bp_num: the break point number which needs to be set for this firmware.
1107  *	Depends on the firmware.
1108  * @bp: break points. Depends on firmware.
1109  * @info: additional information for debugging, and is followed by the
1110  *	binary data of firmware.
1111  */
1112 struct fw_phy_nc {
1113 	struct fw_block blk_hdr;
1114 	__le16 fw_offset;
1115 	__le16 fw_reg;
1116 	__le16 ba_reg;
1117 	__le16 ba_data;
1118 	__le16 patch_en_addr;
1119 	__le16 patch_en_value;
1120 	__le16 mode_reg;
1121 	__le16 mode_pre;
1122 	__le16 mode_post;
1123 	__le16 reserved;
1124 	__le16 bp_start;
1125 	__le16 bp_num;
1126 	__le16 bp[4];
1127 	char info[];
1128 } __packed;
1129 
1130 enum rtl_fw_type {
1131 	RTL_FW_END = 0,
1132 	RTL_FW_PLA,
1133 	RTL_FW_USB,
1134 	RTL_FW_PHY_START,
1135 	RTL_FW_PHY_STOP,
1136 	RTL_FW_PHY_NC,
1137 	RTL_FW_PHY_FIXUP,
1138 	RTL_FW_PHY_UNION_NC,
1139 	RTL_FW_PHY_UNION_NC1,
1140 	RTL_FW_PHY_UNION_NC2,
1141 	RTL_FW_PHY_UNION_UC2,
1142 	RTL_FW_PHY_UNION_UC,
1143 	RTL_FW_PHY_UNION_MISC,
1144 	RTL_FW_PHY_SPEED_UP,
1145 	RTL_FW_PHY_VER,
1146 };
1147 
1148 enum rtl_version {
1149 	RTL_VER_UNKNOWN = 0,
1150 	RTL_VER_01,
1151 	RTL_VER_02,
1152 	RTL_VER_03,
1153 	RTL_VER_04,
1154 	RTL_VER_05,
1155 	RTL_VER_06,
1156 	RTL_VER_07,
1157 	RTL_VER_08,
1158 	RTL_VER_09,
1159 
1160 	RTL_TEST_01,
1161 	RTL_VER_10,
1162 	RTL_VER_11,
1163 	RTL_VER_12,
1164 	RTL_VER_13,
1165 	RTL_VER_14,
1166 	RTL_VER_15,
1167 
1168 	RTL_VER_MAX
1169 };
1170 
1171 enum tx_csum_stat {
1172 	TX_CSUM_SUCCESS = 0,
1173 	TX_CSUM_TSO,
1174 	TX_CSUM_NONE
1175 };
1176 
1177 #define RTL_ADVERTISED_10_HALF			BIT(0)
1178 #define RTL_ADVERTISED_10_FULL			BIT(1)
1179 #define RTL_ADVERTISED_100_HALF			BIT(2)
1180 #define RTL_ADVERTISED_100_FULL			BIT(3)
1181 #define RTL_ADVERTISED_1000_HALF		BIT(4)
1182 #define RTL_ADVERTISED_1000_FULL		BIT(5)
1183 #define RTL_ADVERTISED_2500_FULL		BIT(6)
1184 
1185 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1186  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1187  */
1188 static const int multicast_filter_limit = 32;
1189 static unsigned int agg_buf_sz = 16384;
1190 
1191 #define RTL_LIMITED_TSO_SIZE	(size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc))
1192 
1193 static
1194 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1195 {
1196 	int ret;
1197 	void *tmp;
1198 
1199 	tmp = kmalloc(size, GFP_KERNEL);
1200 	if (!tmp)
1201 		return -ENOMEM;
1202 
1203 	ret = usb_control_msg(tp->udev, tp->pipe_ctrl_in,
1204 			      RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1205 			      value, index, tmp, size, 500);
1206 	if (ret < 0)
1207 		memset(data, 0xff, size);
1208 	else
1209 		memcpy(data, tmp, size);
1210 
1211 	kfree(tmp);
1212 
1213 	return ret;
1214 }
1215 
1216 static
1217 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1218 {
1219 	int ret;
1220 	void *tmp;
1221 
1222 	tmp = kmemdup(data, size, GFP_KERNEL);
1223 	if (!tmp)
1224 		return -ENOMEM;
1225 
1226 	ret = usb_control_msg(tp->udev, tp->pipe_ctrl_out,
1227 			      RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1228 			      value, index, tmp, size, 500);
1229 
1230 	kfree(tmp);
1231 
1232 	return ret;
1233 }
1234 
1235 static void rtl_set_unplug(struct r8152 *tp)
1236 {
1237 	if (tp->udev->state == USB_STATE_NOTATTACHED) {
1238 		set_bit(RTL8152_UNPLUG, &tp->flags);
1239 		smp_mb__after_atomic();
1240 	}
1241 }
1242 
1243 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1244 			    void *data, u16 type)
1245 {
1246 	u16 limit = 64;
1247 	int ret = 0;
1248 
1249 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1250 		return -ENODEV;
1251 
1252 	/* both size and indix must be 4 bytes align */
1253 	if ((size & 3) || !size || (index & 3) || !data)
1254 		return -EPERM;
1255 
1256 	if ((u32)index + (u32)size > 0xffff)
1257 		return -EPERM;
1258 
1259 	while (size) {
1260 		if (size > limit) {
1261 			ret = get_registers(tp, index, type, limit, data);
1262 			if (ret < 0)
1263 				break;
1264 
1265 			index += limit;
1266 			data += limit;
1267 			size -= limit;
1268 		} else {
1269 			ret = get_registers(tp, index, type, size, data);
1270 			if (ret < 0)
1271 				break;
1272 
1273 			index += size;
1274 			data += size;
1275 			size = 0;
1276 			break;
1277 		}
1278 	}
1279 
1280 	if (ret == -ENODEV)
1281 		rtl_set_unplug(tp);
1282 
1283 	return ret;
1284 }
1285 
1286 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1287 			     u16 size, void *data, u16 type)
1288 {
1289 	int ret;
1290 	u16 byteen_start, byteen_end, byen;
1291 	u16 limit = 512;
1292 
1293 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1294 		return -ENODEV;
1295 
1296 	/* both size and indix must be 4 bytes align */
1297 	if ((size & 3) || !size || (index & 3) || !data)
1298 		return -EPERM;
1299 
1300 	if ((u32)index + (u32)size > 0xffff)
1301 		return -EPERM;
1302 
1303 	byteen_start = byteen & BYTE_EN_START_MASK;
1304 	byteen_end = byteen & BYTE_EN_END_MASK;
1305 
1306 	byen = byteen_start | (byteen_start << 4);
1307 	ret = set_registers(tp, index, type | byen, 4, data);
1308 	if (ret < 0)
1309 		goto error1;
1310 
1311 	index += 4;
1312 	data += 4;
1313 	size -= 4;
1314 
1315 	if (size) {
1316 		size -= 4;
1317 
1318 		while (size) {
1319 			if (size > limit) {
1320 				ret = set_registers(tp, index,
1321 						    type | BYTE_EN_DWORD,
1322 						    limit, data);
1323 				if (ret < 0)
1324 					goto error1;
1325 
1326 				index += limit;
1327 				data += limit;
1328 				size -= limit;
1329 			} else {
1330 				ret = set_registers(tp, index,
1331 						    type | BYTE_EN_DWORD,
1332 						    size, data);
1333 				if (ret < 0)
1334 					goto error1;
1335 
1336 				index += size;
1337 				data += size;
1338 				size = 0;
1339 				break;
1340 			}
1341 		}
1342 
1343 		byen = byteen_end | (byteen_end >> 4);
1344 		ret = set_registers(tp, index, type | byen, 4, data);
1345 		if (ret < 0)
1346 			goto error1;
1347 	}
1348 
1349 error1:
1350 	if (ret == -ENODEV)
1351 		rtl_set_unplug(tp);
1352 
1353 	return ret;
1354 }
1355 
1356 static inline
1357 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1358 {
1359 	return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1360 }
1361 
1362 static inline
1363 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1364 {
1365 	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1366 }
1367 
1368 static inline
1369 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1370 {
1371 	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1372 }
1373 
1374 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1375 {
1376 	__le32 data;
1377 
1378 	generic_ocp_read(tp, index, sizeof(data), &data, type);
1379 
1380 	return __le32_to_cpu(data);
1381 }
1382 
1383 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1384 {
1385 	__le32 tmp = __cpu_to_le32(data);
1386 
1387 	generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1388 }
1389 
1390 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1391 {
1392 	u32 data;
1393 	__le32 tmp;
1394 	u16 byen = BYTE_EN_WORD;
1395 	u8 shift = index & 2;
1396 
1397 	index &= ~3;
1398 	byen <<= shift;
1399 
1400 	generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1401 
1402 	data = __le32_to_cpu(tmp);
1403 	data >>= (shift * 8);
1404 	data &= 0xffff;
1405 
1406 	return (u16)data;
1407 }
1408 
1409 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1410 {
1411 	u32 mask = 0xffff;
1412 	__le32 tmp;
1413 	u16 byen = BYTE_EN_WORD;
1414 	u8 shift = index & 2;
1415 
1416 	data &= mask;
1417 
1418 	if (index & 2) {
1419 		byen <<= shift;
1420 		mask <<= (shift * 8);
1421 		data <<= (shift * 8);
1422 		index &= ~3;
1423 	}
1424 
1425 	tmp = __cpu_to_le32(data);
1426 
1427 	generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1428 }
1429 
1430 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1431 {
1432 	u32 data;
1433 	__le32 tmp;
1434 	u8 shift = index & 3;
1435 
1436 	index &= ~3;
1437 
1438 	generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1439 
1440 	data = __le32_to_cpu(tmp);
1441 	data >>= (shift * 8);
1442 	data &= 0xff;
1443 
1444 	return (u8)data;
1445 }
1446 
1447 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1448 {
1449 	u32 mask = 0xff;
1450 	__le32 tmp;
1451 	u16 byen = BYTE_EN_BYTE;
1452 	u8 shift = index & 3;
1453 
1454 	data &= mask;
1455 
1456 	if (index & 3) {
1457 		byen <<= shift;
1458 		mask <<= (shift * 8);
1459 		data <<= (shift * 8);
1460 		index &= ~3;
1461 	}
1462 
1463 	tmp = __cpu_to_le32(data);
1464 
1465 	generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1466 }
1467 
1468 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1469 {
1470 	u16 ocp_base, ocp_index;
1471 
1472 	ocp_base = addr & 0xf000;
1473 	if (ocp_base != tp->ocp_base) {
1474 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1475 		tp->ocp_base = ocp_base;
1476 	}
1477 
1478 	ocp_index = (addr & 0x0fff) | 0xb000;
1479 	return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1480 }
1481 
1482 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1483 {
1484 	u16 ocp_base, ocp_index;
1485 
1486 	ocp_base = addr & 0xf000;
1487 	if (ocp_base != tp->ocp_base) {
1488 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1489 		tp->ocp_base = ocp_base;
1490 	}
1491 
1492 	ocp_index = (addr & 0x0fff) | 0xb000;
1493 	ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1494 }
1495 
1496 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1497 {
1498 	ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1499 }
1500 
1501 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1502 {
1503 	return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1504 }
1505 
1506 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1507 {
1508 	ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1509 	ocp_reg_write(tp, OCP_SRAM_DATA, data);
1510 }
1511 
1512 static u16 sram_read(struct r8152 *tp, u16 addr)
1513 {
1514 	ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1515 	return ocp_reg_read(tp, OCP_SRAM_DATA);
1516 }
1517 
1518 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1519 {
1520 	struct r8152 *tp = netdev_priv(netdev);
1521 	int ret;
1522 
1523 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1524 		return -ENODEV;
1525 
1526 	if (phy_id != R8152_PHY_ID)
1527 		return -EINVAL;
1528 
1529 	ret = r8152_mdio_read(tp, reg);
1530 
1531 	return ret;
1532 }
1533 
1534 static
1535 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1536 {
1537 	struct r8152 *tp = netdev_priv(netdev);
1538 
1539 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1540 		return;
1541 
1542 	if (phy_id != R8152_PHY_ID)
1543 		return;
1544 
1545 	r8152_mdio_write(tp, reg, val);
1546 }
1547 
1548 static int
1549 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1550 
1551 static int
1552 rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
1553 		  u32 advertising);
1554 
1555 static int __rtl8152_set_mac_address(struct net_device *netdev, void *p,
1556 				     bool in_resume)
1557 {
1558 	struct r8152 *tp = netdev_priv(netdev);
1559 	struct sockaddr *addr = p;
1560 	int ret = -EADDRNOTAVAIL;
1561 
1562 	if (!is_valid_ether_addr(addr->sa_data))
1563 		goto out1;
1564 
1565 	if (!in_resume) {
1566 		ret = usb_autopm_get_interface(tp->intf);
1567 		if (ret < 0)
1568 			goto out1;
1569 	}
1570 
1571 	mutex_lock(&tp->control);
1572 
1573 	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1574 
1575 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1576 	pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1577 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1578 
1579 	mutex_unlock(&tp->control);
1580 
1581 	if (!in_resume)
1582 		usb_autopm_put_interface(tp->intf);
1583 out1:
1584 	return ret;
1585 }
1586 
1587 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1588 {
1589 	return __rtl8152_set_mac_address(netdev, p, false);
1590 }
1591 
1592 /* Devices containing proper chips can support a persistent
1593  * host system provided MAC address.
1594  * Examples of this are Dell TB15 and Dell WD15 docks
1595  */
1596 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1597 {
1598 	acpi_status status;
1599 	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1600 	union acpi_object *obj;
1601 	int ret = -EINVAL;
1602 	u32 ocp_data;
1603 	unsigned char buf[6];
1604 	char *mac_obj_name;
1605 	acpi_object_type mac_obj_type;
1606 	int mac_strlen;
1607 
1608 	if (tp->lenovo_macpassthru) {
1609 		mac_obj_name = "\\MACA";
1610 		mac_obj_type = ACPI_TYPE_STRING;
1611 		mac_strlen = 0x16;
1612 	} else {
1613 		/* test for -AD variant of RTL8153 */
1614 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1615 		if ((ocp_data & AD_MASK) == 0x1000) {
1616 			/* test for MAC address pass-through bit */
1617 			ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1618 			if ((ocp_data & PASS_THRU_MASK) != 1) {
1619 				netif_dbg(tp, probe, tp->netdev,
1620 						"No efuse for RTL8153-AD MAC pass through\n");
1621 				return -ENODEV;
1622 			}
1623 		} else {
1624 			/* test for RTL8153-BND and RTL8153-BD */
1625 			ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1626 			if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1627 				netif_dbg(tp, probe, tp->netdev,
1628 						"Invalid variant for MAC pass through\n");
1629 				return -ENODEV;
1630 			}
1631 		}
1632 
1633 		mac_obj_name = "\\_SB.AMAC";
1634 		mac_obj_type = ACPI_TYPE_BUFFER;
1635 		mac_strlen = 0x17;
1636 	}
1637 
1638 	/* returns _AUXMAC_#AABBCCDDEEFF# */
1639 	status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1640 	obj = (union acpi_object *)buffer.pointer;
1641 	if (!ACPI_SUCCESS(status))
1642 		return -ENODEV;
1643 	if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1644 		netif_warn(tp, probe, tp->netdev,
1645 			   "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1646 			   obj->type, obj->string.length);
1647 		goto amacout;
1648 	}
1649 
1650 	if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1651 	    strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1652 		netif_warn(tp, probe, tp->netdev,
1653 			   "Invalid header when reading pass-thru MAC addr\n");
1654 		goto amacout;
1655 	}
1656 	ret = hex2bin(buf, obj->string.pointer + 9, 6);
1657 	if (!(ret == 0 && is_valid_ether_addr(buf))) {
1658 		netif_warn(tp, probe, tp->netdev,
1659 			   "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1660 			   ret, buf);
1661 		ret = -EINVAL;
1662 		goto amacout;
1663 	}
1664 	memcpy(sa->sa_data, buf, 6);
1665 	netif_info(tp, probe, tp->netdev,
1666 		   "Using pass-thru MAC addr %pM\n", sa->sa_data);
1667 
1668 amacout:
1669 	kfree(obj);
1670 	return ret;
1671 }
1672 
1673 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1674 {
1675 	struct net_device *dev = tp->netdev;
1676 	int ret;
1677 
1678 	sa->sa_family = dev->type;
1679 
1680 	ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1681 	if (ret < 0) {
1682 		if (tp->version == RTL_VER_01) {
1683 			ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1684 		} else {
1685 			/* if device doesn't support MAC pass through this will
1686 			 * be expected to be non-zero
1687 			 */
1688 			ret = vendor_mac_passthru_addr_read(tp, sa);
1689 			if (ret < 0)
1690 				ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1691 						   sa->sa_data);
1692 		}
1693 	}
1694 
1695 	if (ret < 0) {
1696 		netif_err(tp, probe, dev, "Get ether addr fail\n");
1697 	} else if (!is_valid_ether_addr(sa->sa_data)) {
1698 		netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1699 			  sa->sa_data);
1700 		eth_hw_addr_random(dev);
1701 		ether_addr_copy(sa->sa_data, dev->dev_addr);
1702 		netif_info(tp, probe, dev, "Random ether addr %pM\n",
1703 			   sa->sa_data);
1704 		return 0;
1705 	}
1706 
1707 	return ret;
1708 }
1709 
1710 static int set_ethernet_addr(struct r8152 *tp, bool in_resume)
1711 {
1712 	struct net_device *dev = tp->netdev;
1713 	struct sockaddr sa;
1714 	int ret;
1715 
1716 	ret = determine_ethernet_addr(tp, &sa);
1717 	if (ret < 0)
1718 		return ret;
1719 
1720 	if (tp->version == RTL_VER_01)
1721 		ether_addr_copy(dev->dev_addr, sa.sa_data);
1722 	else
1723 		ret = __rtl8152_set_mac_address(dev, &sa, in_resume);
1724 
1725 	return ret;
1726 }
1727 
1728 static void read_bulk_callback(struct urb *urb)
1729 {
1730 	struct net_device *netdev;
1731 	int status = urb->status;
1732 	struct rx_agg *agg;
1733 	struct r8152 *tp;
1734 	unsigned long flags;
1735 
1736 	agg = urb->context;
1737 	if (!agg)
1738 		return;
1739 
1740 	tp = agg->context;
1741 	if (!tp)
1742 		return;
1743 
1744 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1745 		return;
1746 
1747 	if (!test_bit(WORK_ENABLE, &tp->flags))
1748 		return;
1749 
1750 	netdev = tp->netdev;
1751 
1752 	/* When link down, the driver would cancel all bulks. */
1753 	/* This avoid the re-submitting bulk */
1754 	if (!netif_carrier_ok(netdev))
1755 		return;
1756 
1757 	usb_mark_last_busy(tp->udev);
1758 
1759 	switch (status) {
1760 	case 0:
1761 		if (urb->actual_length < ETH_ZLEN)
1762 			break;
1763 
1764 		spin_lock_irqsave(&tp->rx_lock, flags);
1765 		list_add_tail(&agg->list, &tp->rx_done);
1766 		spin_unlock_irqrestore(&tp->rx_lock, flags);
1767 		napi_schedule(&tp->napi);
1768 		return;
1769 	case -ESHUTDOWN:
1770 		rtl_set_unplug(tp);
1771 		netif_device_detach(tp->netdev);
1772 		return;
1773 	case -ENOENT:
1774 		return;	/* the urb is in unlink state */
1775 	case -ETIME:
1776 		if (net_ratelimit())
1777 			netdev_warn(netdev, "maybe reset is needed?\n");
1778 		break;
1779 	default:
1780 		if (net_ratelimit())
1781 			netdev_warn(netdev, "Rx status %d\n", status);
1782 		break;
1783 	}
1784 
1785 	r8152_submit_rx(tp, agg, GFP_ATOMIC);
1786 }
1787 
1788 static void write_bulk_callback(struct urb *urb)
1789 {
1790 	struct net_device_stats *stats;
1791 	struct net_device *netdev;
1792 	struct tx_agg *agg;
1793 	struct r8152 *tp;
1794 	unsigned long flags;
1795 	int status = urb->status;
1796 
1797 	agg = urb->context;
1798 	if (!agg)
1799 		return;
1800 
1801 	tp = agg->context;
1802 	if (!tp)
1803 		return;
1804 
1805 	netdev = tp->netdev;
1806 	stats = &netdev->stats;
1807 	if (status) {
1808 		if (net_ratelimit())
1809 			netdev_warn(netdev, "Tx status %d\n", status);
1810 		stats->tx_errors += agg->skb_num;
1811 	} else {
1812 		stats->tx_packets += agg->skb_num;
1813 		stats->tx_bytes += agg->skb_len;
1814 	}
1815 
1816 	spin_lock_irqsave(&tp->tx_lock, flags);
1817 	list_add_tail(&agg->list, &tp->tx_free);
1818 	spin_unlock_irqrestore(&tp->tx_lock, flags);
1819 
1820 	usb_autopm_put_interface_async(tp->intf);
1821 
1822 	if (!netif_carrier_ok(netdev))
1823 		return;
1824 
1825 	if (!test_bit(WORK_ENABLE, &tp->flags))
1826 		return;
1827 
1828 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1829 		return;
1830 
1831 	if (!skb_queue_empty(&tp->tx_queue))
1832 		tasklet_schedule(&tp->tx_tl);
1833 }
1834 
1835 static void intr_callback(struct urb *urb)
1836 {
1837 	struct r8152 *tp;
1838 	__le16 *d;
1839 	int status = urb->status;
1840 	int res;
1841 
1842 	tp = urb->context;
1843 	if (!tp)
1844 		return;
1845 
1846 	if (!test_bit(WORK_ENABLE, &tp->flags))
1847 		return;
1848 
1849 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1850 		return;
1851 
1852 	switch (status) {
1853 	case 0:			/* success */
1854 		break;
1855 	case -ECONNRESET:	/* unlink */
1856 	case -ESHUTDOWN:
1857 		netif_device_detach(tp->netdev);
1858 		fallthrough;
1859 	case -ENOENT:
1860 	case -EPROTO:
1861 		netif_info(tp, intr, tp->netdev,
1862 			   "Stop submitting intr, status %d\n", status);
1863 		return;
1864 	case -EOVERFLOW:
1865 		netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1866 		goto resubmit;
1867 	/* -EPIPE:  should clear the halt */
1868 	default:
1869 		netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1870 		goto resubmit;
1871 	}
1872 
1873 	d = urb->transfer_buffer;
1874 	if (INTR_LINK & __le16_to_cpu(d[0])) {
1875 		if (!netif_carrier_ok(tp->netdev)) {
1876 			set_bit(RTL8152_LINK_CHG, &tp->flags);
1877 			schedule_delayed_work(&tp->schedule, 0);
1878 		}
1879 	} else {
1880 		if (netif_carrier_ok(tp->netdev)) {
1881 			netif_stop_queue(tp->netdev);
1882 			set_bit(RTL8152_LINK_CHG, &tp->flags);
1883 			schedule_delayed_work(&tp->schedule, 0);
1884 		}
1885 	}
1886 
1887 resubmit:
1888 	res = usb_submit_urb(urb, GFP_ATOMIC);
1889 	if (res == -ENODEV) {
1890 		rtl_set_unplug(tp);
1891 		netif_device_detach(tp->netdev);
1892 	} else if (res) {
1893 		netif_err(tp, intr, tp->netdev,
1894 			  "can't resubmit intr, status %d\n", res);
1895 	}
1896 }
1897 
1898 static inline void *rx_agg_align(void *data)
1899 {
1900 	return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1901 }
1902 
1903 static inline void *tx_agg_align(void *data)
1904 {
1905 	return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1906 }
1907 
1908 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1909 {
1910 	list_del(&agg->info_list);
1911 
1912 	usb_free_urb(agg->urb);
1913 	put_page(agg->page);
1914 	kfree(agg);
1915 
1916 	atomic_dec(&tp->rx_count);
1917 }
1918 
1919 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1920 {
1921 	struct net_device *netdev = tp->netdev;
1922 	int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1923 	unsigned int order = get_order(tp->rx_buf_sz);
1924 	struct rx_agg *rx_agg;
1925 	unsigned long flags;
1926 
1927 	rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1928 	if (!rx_agg)
1929 		return NULL;
1930 
1931 	rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1932 	if (!rx_agg->page)
1933 		goto free_rx;
1934 
1935 	rx_agg->buffer = page_address(rx_agg->page);
1936 
1937 	rx_agg->urb = usb_alloc_urb(0, mflags);
1938 	if (!rx_agg->urb)
1939 		goto free_buf;
1940 
1941 	rx_agg->context = tp;
1942 
1943 	INIT_LIST_HEAD(&rx_agg->list);
1944 	INIT_LIST_HEAD(&rx_agg->info_list);
1945 	spin_lock_irqsave(&tp->rx_lock, flags);
1946 	list_add_tail(&rx_agg->info_list, &tp->rx_info);
1947 	spin_unlock_irqrestore(&tp->rx_lock, flags);
1948 
1949 	atomic_inc(&tp->rx_count);
1950 
1951 	return rx_agg;
1952 
1953 free_buf:
1954 	__free_pages(rx_agg->page, order);
1955 free_rx:
1956 	kfree(rx_agg);
1957 	return NULL;
1958 }
1959 
1960 static void free_all_mem(struct r8152 *tp)
1961 {
1962 	struct rx_agg *agg, *agg_next;
1963 	unsigned long flags;
1964 	int i;
1965 
1966 	spin_lock_irqsave(&tp->rx_lock, flags);
1967 
1968 	list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1969 		free_rx_agg(tp, agg);
1970 
1971 	spin_unlock_irqrestore(&tp->rx_lock, flags);
1972 
1973 	WARN_ON(atomic_read(&tp->rx_count));
1974 
1975 	for (i = 0; i < RTL8152_MAX_TX; i++) {
1976 		usb_free_urb(tp->tx_info[i].urb);
1977 		tp->tx_info[i].urb = NULL;
1978 
1979 		kfree(tp->tx_info[i].buffer);
1980 		tp->tx_info[i].buffer = NULL;
1981 		tp->tx_info[i].head = NULL;
1982 	}
1983 
1984 	usb_free_urb(tp->intr_urb);
1985 	tp->intr_urb = NULL;
1986 
1987 	kfree(tp->intr_buff);
1988 	tp->intr_buff = NULL;
1989 }
1990 
1991 static int alloc_all_mem(struct r8152 *tp)
1992 {
1993 	struct net_device *netdev = tp->netdev;
1994 	struct usb_interface *intf = tp->intf;
1995 	struct usb_host_interface *alt = intf->cur_altsetting;
1996 	struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1997 	int node, i;
1998 
1999 	node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
2000 
2001 	spin_lock_init(&tp->rx_lock);
2002 	spin_lock_init(&tp->tx_lock);
2003 	INIT_LIST_HEAD(&tp->rx_info);
2004 	INIT_LIST_HEAD(&tp->tx_free);
2005 	INIT_LIST_HEAD(&tp->rx_done);
2006 	skb_queue_head_init(&tp->tx_queue);
2007 	skb_queue_head_init(&tp->rx_queue);
2008 	atomic_set(&tp->rx_count, 0);
2009 
2010 	for (i = 0; i < RTL8152_MAX_RX; i++) {
2011 		if (!alloc_rx_agg(tp, GFP_KERNEL))
2012 			goto err1;
2013 	}
2014 
2015 	for (i = 0; i < RTL8152_MAX_TX; i++) {
2016 		struct urb *urb;
2017 		u8 *buf;
2018 
2019 		buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
2020 		if (!buf)
2021 			goto err1;
2022 
2023 		if (buf != tx_agg_align(buf)) {
2024 			kfree(buf);
2025 			buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
2026 					   node);
2027 			if (!buf)
2028 				goto err1;
2029 		}
2030 
2031 		urb = usb_alloc_urb(0, GFP_KERNEL);
2032 		if (!urb) {
2033 			kfree(buf);
2034 			goto err1;
2035 		}
2036 
2037 		INIT_LIST_HEAD(&tp->tx_info[i].list);
2038 		tp->tx_info[i].context = tp;
2039 		tp->tx_info[i].urb = urb;
2040 		tp->tx_info[i].buffer = buf;
2041 		tp->tx_info[i].head = tx_agg_align(buf);
2042 
2043 		list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
2044 	}
2045 
2046 	tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
2047 	if (!tp->intr_urb)
2048 		goto err1;
2049 
2050 	tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
2051 	if (!tp->intr_buff)
2052 		goto err1;
2053 
2054 	tp->intr_interval = (int)ep_intr->desc.bInterval;
2055 	usb_fill_int_urb(tp->intr_urb, tp->udev, tp->pipe_intr,
2056 			 tp->intr_buff, INTBUFSIZE, intr_callback,
2057 			 tp, tp->intr_interval);
2058 
2059 	return 0;
2060 
2061 err1:
2062 	free_all_mem(tp);
2063 	return -ENOMEM;
2064 }
2065 
2066 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
2067 {
2068 	struct tx_agg *agg = NULL;
2069 	unsigned long flags;
2070 
2071 	if (list_empty(&tp->tx_free))
2072 		return NULL;
2073 
2074 	spin_lock_irqsave(&tp->tx_lock, flags);
2075 	if (!list_empty(&tp->tx_free)) {
2076 		struct list_head *cursor;
2077 
2078 		cursor = tp->tx_free.next;
2079 		list_del_init(cursor);
2080 		agg = list_entry(cursor, struct tx_agg, list);
2081 	}
2082 	spin_unlock_irqrestore(&tp->tx_lock, flags);
2083 
2084 	return agg;
2085 }
2086 
2087 /* r8152_csum_workaround()
2088  * The hw limits the value of the transport offset. When the offset is out of
2089  * range, calculate the checksum by sw.
2090  */
2091 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
2092 				  struct sk_buff_head *list)
2093 {
2094 	if (skb_shinfo(skb)->gso_size) {
2095 		netdev_features_t features = tp->netdev->features;
2096 		struct sk_buff *segs, *seg, *next;
2097 		struct sk_buff_head seg_list;
2098 
2099 		features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
2100 		segs = skb_gso_segment(skb, features);
2101 		if (IS_ERR(segs) || !segs)
2102 			goto drop;
2103 
2104 		__skb_queue_head_init(&seg_list);
2105 
2106 		skb_list_walk_safe(segs, seg, next) {
2107 			skb_mark_not_on_list(seg);
2108 			__skb_queue_tail(&seg_list, seg);
2109 		}
2110 
2111 		skb_queue_splice(&seg_list, list);
2112 		dev_kfree_skb(skb);
2113 	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2114 		if (skb_checksum_help(skb) < 0)
2115 			goto drop;
2116 
2117 		__skb_queue_head(list, skb);
2118 	} else {
2119 		struct net_device_stats *stats;
2120 
2121 drop:
2122 		stats = &tp->netdev->stats;
2123 		stats->tx_dropped++;
2124 		dev_kfree_skb(skb);
2125 	}
2126 }
2127 
2128 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
2129 {
2130 	if (skb_vlan_tag_present(skb)) {
2131 		u32 opts2;
2132 
2133 		opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
2134 		desc->opts2 |= cpu_to_le32(opts2);
2135 	}
2136 }
2137 
2138 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
2139 {
2140 	u32 opts2 = le32_to_cpu(desc->opts2);
2141 
2142 	if (opts2 & RX_VLAN_TAG)
2143 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2144 				       swab16(opts2 & 0xffff));
2145 }
2146 
2147 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
2148 			 struct sk_buff *skb, u32 len, u32 transport_offset)
2149 {
2150 	u32 mss = skb_shinfo(skb)->gso_size;
2151 	u32 opts1, opts2 = 0;
2152 	int ret = TX_CSUM_SUCCESS;
2153 
2154 	WARN_ON_ONCE(len > TX_LEN_MAX);
2155 
2156 	opts1 = len | TX_FS | TX_LS;
2157 
2158 	if (mss) {
2159 		if (transport_offset > GTTCPHO_MAX) {
2160 			netif_warn(tp, tx_err, tp->netdev,
2161 				   "Invalid transport offset 0x%x for TSO\n",
2162 				   transport_offset);
2163 			ret = TX_CSUM_TSO;
2164 			goto unavailable;
2165 		}
2166 
2167 		switch (vlan_get_protocol(skb)) {
2168 		case htons(ETH_P_IP):
2169 			opts1 |= GTSENDV4;
2170 			break;
2171 
2172 		case htons(ETH_P_IPV6):
2173 			if (skb_cow_head(skb, 0)) {
2174 				ret = TX_CSUM_TSO;
2175 				goto unavailable;
2176 			}
2177 			tcp_v6_gso_csum_prep(skb);
2178 			opts1 |= GTSENDV6;
2179 			break;
2180 
2181 		default:
2182 			WARN_ON_ONCE(1);
2183 			break;
2184 		}
2185 
2186 		opts1 |= transport_offset << GTTCPHO_SHIFT;
2187 		opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2188 	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2189 		u8 ip_protocol;
2190 
2191 		if (transport_offset > TCPHO_MAX) {
2192 			netif_warn(tp, tx_err, tp->netdev,
2193 				   "Invalid transport offset 0x%x\n",
2194 				   transport_offset);
2195 			ret = TX_CSUM_NONE;
2196 			goto unavailable;
2197 		}
2198 
2199 		switch (vlan_get_protocol(skb)) {
2200 		case htons(ETH_P_IP):
2201 			opts2 |= IPV4_CS;
2202 			ip_protocol = ip_hdr(skb)->protocol;
2203 			break;
2204 
2205 		case htons(ETH_P_IPV6):
2206 			opts2 |= IPV6_CS;
2207 			ip_protocol = ipv6_hdr(skb)->nexthdr;
2208 			break;
2209 
2210 		default:
2211 			ip_protocol = IPPROTO_RAW;
2212 			break;
2213 		}
2214 
2215 		if (ip_protocol == IPPROTO_TCP)
2216 			opts2 |= TCP_CS;
2217 		else if (ip_protocol == IPPROTO_UDP)
2218 			opts2 |= UDP_CS;
2219 		else
2220 			WARN_ON_ONCE(1);
2221 
2222 		opts2 |= transport_offset << TCPHO_SHIFT;
2223 	}
2224 
2225 	desc->opts2 = cpu_to_le32(opts2);
2226 	desc->opts1 = cpu_to_le32(opts1);
2227 
2228 unavailable:
2229 	return ret;
2230 }
2231 
2232 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2233 {
2234 	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2235 	int remain, ret;
2236 	u8 *tx_data;
2237 
2238 	__skb_queue_head_init(&skb_head);
2239 	spin_lock(&tx_queue->lock);
2240 	skb_queue_splice_init(tx_queue, &skb_head);
2241 	spin_unlock(&tx_queue->lock);
2242 
2243 	tx_data = agg->head;
2244 	agg->skb_num = 0;
2245 	agg->skb_len = 0;
2246 	remain = agg_buf_sz;
2247 
2248 	while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2249 		struct tx_desc *tx_desc;
2250 		struct sk_buff *skb;
2251 		unsigned int len;
2252 		u32 offset;
2253 
2254 		skb = __skb_dequeue(&skb_head);
2255 		if (!skb)
2256 			break;
2257 
2258 		len = skb->len + sizeof(*tx_desc);
2259 
2260 		if (len > remain) {
2261 			__skb_queue_head(&skb_head, skb);
2262 			break;
2263 		}
2264 
2265 		tx_data = tx_agg_align(tx_data);
2266 		tx_desc = (struct tx_desc *)tx_data;
2267 
2268 		offset = (u32)skb_transport_offset(skb);
2269 
2270 		if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
2271 			r8152_csum_workaround(tp, skb, &skb_head);
2272 			continue;
2273 		}
2274 
2275 		rtl_tx_vlan_tag(tx_desc, skb);
2276 
2277 		tx_data += sizeof(*tx_desc);
2278 
2279 		len = skb->len;
2280 		if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2281 			struct net_device_stats *stats = &tp->netdev->stats;
2282 
2283 			stats->tx_dropped++;
2284 			dev_kfree_skb_any(skb);
2285 			tx_data -= sizeof(*tx_desc);
2286 			continue;
2287 		}
2288 
2289 		tx_data += len;
2290 		agg->skb_len += len;
2291 		agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2292 
2293 		dev_kfree_skb_any(skb);
2294 
2295 		remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2296 
2297 		if (tp->dell_tb_rx_agg_bug)
2298 			break;
2299 	}
2300 
2301 	if (!skb_queue_empty(&skb_head)) {
2302 		spin_lock(&tx_queue->lock);
2303 		skb_queue_splice(&skb_head, tx_queue);
2304 		spin_unlock(&tx_queue->lock);
2305 	}
2306 
2307 	netif_tx_lock(tp->netdev);
2308 
2309 	if (netif_queue_stopped(tp->netdev) &&
2310 	    skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2311 		netif_wake_queue(tp->netdev);
2312 
2313 	netif_tx_unlock(tp->netdev);
2314 
2315 	ret = usb_autopm_get_interface_async(tp->intf);
2316 	if (ret < 0)
2317 		goto out_tx_fill;
2318 
2319 	usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_out,
2320 			  agg->head, (int)(tx_data - (u8 *)agg->head),
2321 			  (usb_complete_t)write_bulk_callback, agg);
2322 
2323 	ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2324 	if (ret < 0)
2325 		usb_autopm_put_interface_async(tp->intf);
2326 
2327 out_tx_fill:
2328 	return ret;
2329 }
2330 
2331 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2332 {
2333 	u8 checksum = CHECKSUM_NONE;
2334 	u32 opts2, opts3;
2335 
2336 	if (!(tp->netdev->features & NETIF_F_RXCSUM))
2337 		goto return_result;
2338 
2339 	opts2 = le32_to_cpu(rx_desc->opts2);
2340 	opts3 = le32_to_cpu(rx_desc->opts3);
2341 
2342 	if (opts2 & RD_IPV4_CS) {
2343 		if (opts3 & IPF)
2344 			checksum = CHECKSUM_NONE;
2345 		else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2346 			checksum = CHECKSUM_UNNECESSARY;
2347 		else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2348 			checksum = CHECKSUM_UNNECESSARY;
2349 	} else if (opts2 & RD_IPV6_CS) {
2350 		if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2351 			checksum = CHECKSUM_UNNECESSARY;
2352 		else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2353 			checksum = CHECKSUM_UNNECESSARY;
2354 	}
2355 
2356 return_result:
2357 	return checksum;
2358 }
2359 
2360 static inline bool rx_count_exceed(struct r8152 *tp)
2361 {
2362 	return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2363 }
2364 
2365 static inline int agg_offset(struct rx_agg *agg, void *addr)
2366 {
2367 	return (int)(addr - agg->buffer);
2368 }
2369 
2370 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2371 {
2372 	struct rx_agg *agg, *agg_next, *agg_free = NULL;
2373 	unsigned long flags;
2374 
2375 	spin_lock_irqsave(&tp->rx_lock, flags);
2376 
2377 	list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2378 		if (page_count(agg->page) == 1) {
2379 			if (!agg_free) {
2380 				list_del_init(&agg->list);
2381 				agg_free = agg;
2382 				continue;
2383 			}
2384 			if (rx_count_exceed(tp)) {
2385 				list_del_init(&agg->list);
2386 				free_rx_agg(tp, agg);
2387 			}
2388 			break;
2389 		}
2390 	}
2391 
2392 	spin_unlock_irqrestore(&tp->rx_lock, flags);
2393 
2394 	if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2395 		agg_free = alloc_rx_agg(tp, mflags);
2396 
2397 	return agg_free;
2398 }
2399 
2400 static int rx_bottom(struct r8152 *tp, int budget)
2401 {
2402 	unsigned long flags;
2403 	struct list_head *cursor, *next, rx_queue;
2404 	int ret = 0, work_done = 0;
2405 	struct napi_struct *napi = &tp->napi;
2406 
2407 	if (!skb_queue_empty(&tp->rx_queue)) {
2408 		while (work_done < budget) {
2409 			struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2410 			struct net_device *netdev = tp->netdev;
2411 			struct net_device_stats *stats = &netdev->stats;
2412 			unsigned int pkt_len;
2413 
2414 			if (!skb)
2415 				break;
2416 
2417 			pkt_len = skb->len;
2418 			napi_gro_receive(napi, skb);
2419 			work_done++;
2420 			stats->rx_packets++;
2421 			stats->rx_bytes += pkt_len;
2422 		}
2423 	}
2424 
2425 	if (list_empty(&tp->rx_done))
2426 		goto out1;
2427 
2428 	INIT_LIST_HEAD(&rx_queue);
2429 	spin_lock_irqsave(&tp->rx_lock, flags);
2430 	list_splice_init(&tp->rx_done, &rx_queue);
2431 	spin_unlock_irqrestore(&tp->rx_lock, flags);
2432 
2433 	list_for_each_safe(cursor, next, &rx_queue) {
2434 		struct rx_desc *rx_desc;
2435 		struct rx_agg *agg, *agg_free;
2436 		int len_used = 0;
2437 		struct urb *urb;
2438 		u8 *rx_data;
2439 
2440 		list_del_init(cursor);
2441 
2442 		agg = list_entry(cursor, struct rx_agg, list);
2443 		urb = agg->urb;
2444 		if (urb->actual_length < ETH_ZLEN)
2445 			goto submit;
2446 
2447 		agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2448 
2449 		rx_desc = agg->buffer;
2450 		rx_data = agg->buffer;
2451 		len_used += sizeof(struct rx_desc);
2452 
2453 		while (urb->actual_length > len_used) {
2454 			struct net_device *netdev = tp->netdev;
2455 			struct net_device_stats *stats = &netdev->stats;
2456 			unsigned int pkt_len, rx_frag_head_sz;
2457 			struct sk_buff *skb;
2458 
2459 			/* limit the skb numbers for rx_queue */
2460 			if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2461 				break;
2462 
2463 			pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2464 			if (pkt_len < ETH_ZLEN)
2465 				break;
2466 
2467 			len_used += pkt_len;
2468 			if (urb->actual_length < len_used)
2469 				break;
2470 
2471 			pkt_len -= ETH_FCS_LEN;
2472 			rx_data += sizeof(struct rx_desc);
2473 
2474 			if (!agg_free || tp->rx_copybreak > pkt_len)
2475 				rx_frag_head_sz = pkt_len;
2476 			else
2477 				rx_frag_head_sz = tp->rx_copybreak;
2478 
2479 			skb = napi_alloc_skb(napi, rx_frag_head_sz);
2480 			if (!skb) {
2481 				stats->rx_dropped++;
2482 				goto find_next_rx;
2483 			}
2484 
2485 			skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2486 			memcpy(skb->data, rx_data, rx_frag_head_sz);
2487 			skb_put(skb, rx_frag_head_sz);
2488 			pkt_len -= rx_frag_head_sz;
2489 			rx_data += rx_frag_head_sz;
2490 			if (pkt_len) {
2491 				skb_add_rx_frag(skb, 0, agg->page,
2492 						agg_offset(agg, rx_data),
2493 						pkt_len,
2494 						SKB_DATA_ALIGN(pkt_len));
2495 				get_page(agg->page);
2496 			}
2497 
2498 			skb->protocol = eth_type_trans(skb, netdev);
2499 			rtl_rx_vlan_tag(rx_desc, skb);
2500 			if (work_done < budget) {
2501 				work_done++;
2502 				stats->rx_packets++;
2503 				stats->rx_bytes += skb->len;
2504 				napi_gro_receive(napi, skb);
2505 			} else {
2506 				__skb_queue_tail(&tp->rx_queue, skb);
2507 			}
2508 
2509 find_next_rx:
2510 			rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2511 			rx_desc = (struct rx_desc *)rx_data;
2512 			len_used = agg_offset(agg, rx_data);
2513 			len_used += sizeof(struct rx_desc);
2514 		}
2515 
2516 		WARN_ON(!agg_free && page_count(agg->page) > 1);
2517 
2518 		if (agg_free) {
2519 			spin_lock_irqsave(&tp->rx_lock, flags);
2520 			if (page_count(agg->page) == 1) {
2521 				list_add(&agg_free->list, &tp->rx_used);
2522 			} else {
2523 				list_add_tail(&agg->list, &tp->rx_used);
2524 				agg = agg_free;
2525 				urb = agg->urb;
2526 			}
2527 			spin_unlock_irqrestore(&tp->rx_lock, flags);
2528 		}
2529 
2530 submit:
2531 		if (!ret) {
2532 			ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2533 		} else {
2534 			urb->actual_length = 0;
2535 			list_add_tail(&agg->list, next);
2536 		}
2537 	}
2538 
2539 	if (!list_empty(&rx_queue)) {
2540 		spin_lock_irqsave(&tp->rx_lock, flags);
2541 		list_splice_tail(&rx_queue, &tp->rx_done);
2542 		spin_unlock_irqrestore(&tp->rx_lock, flags);
2543 	}
2544 
2545 out1:
2546 	return work_done;
2547 }
2548 
2549 static void tx_bottom(struct r8152 *tp)
2550 {
2551 	int res;
2552 
2553 	do {
2554 		struct net_device *netdev = tp->netdev;
2555 		struct tx_agg *agg;
2556 
2557 		if (skb_queue_empty(&tp->tx_queue))
2558 			break;
2559 
2560 		agg = r8152_get_tx_agg(tp);
2561 		if (!agg)
2562 			break;
2563 
2564 		res = r8152_tx_agg_fill(tp, agg);
2565 		if (!res)
2566 			continue;
2567 
2568 		if (res == -ENODEV) {
2569 			rtl_set_unplug(tp);
2570 			netif_device_detach(netdev);
2571 		} else {
2572 			struct net_device_stats *stats = &netdev->stats;
2573 			unsigned long flags;
2574 
2575 			netif_warn(tp, tx_err, netdev,
2576 				   "failed tx_urb %d\n", res);
2577 			stats->tx_dropped += agg->skb_num;
2578 
2579 			spin_lock_irqsave(&tp->tx_lock, flags);
2580 			list_add_tail(&agg->list, &tp->tx_free);
2581 			spin_unlock_irqrestore(&tp->tx_lock, flags);
2582 		}
2583 	} while (res == 0);
2584 }
2585 
2586 static void bottom_half(struct tasklet_struct *t)
2587 {
2588 	struct r8152 *tp = from_tasklet(tp, t, tx_tl);
2589 
2590 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
2591 		return;
2592 
2593 	if (!test_bit(WORK_ENABLE, &tp->flags))
2594 		return;
2595 
2596 	/* When link down, the driver would cancel all bulks. */
2597 	/* This avoid the re-submitting bulk */
2598 	if (!netif_carrier_ok(tp->netdev))
2599 		return;
2600 
2601 	clear_bit(SCHEDULE_TASKLET, &tp->flags);
2602 
2603 	tx_bottom(tp);
2604 }
2605 
2606 static int r8152_poll(struct napi_struct *napi, int budget)
2607 {
2608 	struct r8152 *tp = container_of(napi, struct r8152, napi);
2609 	int work_done;
2610 
2611 	work_done = rx_bottom(tp, budget);
2612 
2613 	if (work_done < budget) {
2614 		if (!napi_complete_done(napi, work_done))
2615 			goto out;
2616 		if (!list_empty(&tp->rx_done))
2617 			napi_schedule(napi);
2618 	}
2619 
2620 out:
2621 	return work_done;
2622 }
2623 
2624 static
2625 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2626 {
2627 	int ret;
2628 
2629 	/* The rx would be stopped, so skip submitting */
2630 	if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2631 	    !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2632 		return 0;
2633 
2634 	usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_in,
2635 			  agg->buffer, tp->rx_buf_sz,
2636 			  (usb_complete_t)read_bulk_callback, agg);
2637 
2638 	ret = usb_submit_urb(agg->urb, mem_flags);
2639 	if (ret == -ENODEV) {
2640 		rtl_set_unplug(tp);
2641 		netif_device_detach(tp->netdev);
2642 	} else if (ret) {
2643 		struct urb *urb = agg->urb;
2644 		unsigned long flags;
2645 
2646 		urb->actual_length = 0;
2647 		spin_lock_irqsave(&tp->rx_lock, flags);
2648 		list_add_tail(&agg->list, &tp->rx_done);
2649 		spin_unlock_irqrestore(&tp->rx_lock, flags);
2650 
2651 		netif_err(tp, rx_err, tp->netdev,
2652 			  "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2653 
2654 		napi_schedule(&tp->napi);
2655 	}
2656 
2657 	return ret;
2658 }
2659 
2660 static void rtl_drop_queued_tx(struct r8152 *tp)
2661 {
2662 	struct net_device_stats *stats = &tp->netdev->stats;
2663 	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2664 	struct sk_buff *skb;
2665 
2666 	if (skb_queue_empty(tx_queue))
2667 		return;
2668 
2669 	__skb_queue_head_init(&skb_head);
2670 	spin_lock_bh(&tx_queue->lock);
2671 	skb_queue_splice_init(tx_queue, &skb_head);
2672 	spin_unlock_bh(&tx_queue->lock);
2673 
2674 	while ((skb = __skb_dequeue(&skb_head))) {
2675 		dev_kfree_skb(skb);
2676 		stats->tx_dropped++;
2677 	}
2678 }
2679 
2680 static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2681 {
2682 	struct r8152 *tp = netdev_priv(netdev);
2683 
2684 	netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2685 
2686 	usb_queue_reset_device(tp->intf);
2687 }
2688 
2689 static void rtl8152_set_rx_mode(struct net_device *netdev)
2690 {
2691 	struct r8152 *tp = netdev_priv(netdev);
2692 
2693 	if (netif_carrier_ok(netdev)) {
2694 		set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2695 		schedule_delayed_work(&tp->schedule, 0);
2696 	}
2697 }
2698 
2699 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2700 {
2701 	struct r8152 *tp = netdev_priv(netdev);
2702 	u32 mc_filter[2];	/* Multicast hash filter */
2703 	__le32 tmp[2];
2704 	u32 ocp_data;
2705 
2706 	netif_stop_queue(netdev);
2707 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2708 	ocp_data &= ~RCR_ACPT_ALL;
2709 	ocp_data |= RCR_AB | RCR_APM;
2710 
2711 	if (netdev->flags & IFF_PROMISC) {
2712 		/* Unconditionally log net taps. */
2713 		netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2714 		ocp_data |= RCR_AM | RCR_AAP;
2715 		mc_filter[1] = 0xffffffff;
2716 		mc_filter[0] = 0xffffffff;
2717 	} else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2718 		   (netdev->flags & IFF_ALLMULTI)) {
2719 		/* Too many to filter perfectly -- accept all multicasts. */
2720 		ocp_data |= RCR_AM;
2721 		mc_filter[1] = 0xffffffff;
2722 		mc_filter[0] = 0xffffffff;
2723 	} else {
2724 		struct netdev_hw_addr *ha;
2725 
2726 		mc_filter[1] = 0;
2727 		mc_filter[0] = 0;
2728 		netdev_for_each_mc_addr(ha, netdev) {
2729 			int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2730 
2731 			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2732 			ocp_data |= RCR_AM;
2733 		}
2734 	}
2735 
2736 	tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2737 	tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2738 
2739 	pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2740 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2741 	netif_wake_queue(netdev);
2742 }
2743 
2744 static netdev_features_t
2745 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2746 		       netdev_features_t features)
2747 {
2748 	u32 mss = skb_shinfo(skb)->gso_size;
2749 	int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2750 	int offset = skb_transport_offset(skb);
2751 
2752 	if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2753 		features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2754 	else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2755 		features &= ~NETIF_F_GSO_MASK;
2756 
2757 	return features;
2758 }
2759 
2760 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2761 				      struct net_device *netdev)
2762 {
2763 	struct r8152 *tp = netdev_priv(netdev);
2764 
2765 	skb_tx_timestamp(skb);
2766 
2767 	skb_queue_tail(&tp->tx_queue, skb);
2768 
2769 	if (!list_empty(&tp->tx_free)) {
2770 		if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2771 			set_bit(SCHEDULE_TASKLET, &tp->flags);
2772 			schedule_delayed_work(&tp->schedule, 0);
2773 		} else {
2774 			usb_mark_last_busy(tp->udev);
2775 			tasklet_schedule(&tp->tx_tl);
2776 		}
2777 	} else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2778 		netif_stop_queue(netdev);
2779 	}
2780 
2781 	return NETDEV_TX_OK;
2782 }
2783 
2784 static void r8152b_reset_packet_filter(struct r8152 *tp)
2785 {
2786 	u32 ocp_data;
2787 
2788 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2789 	ocp_data &= ~FMC_FCR_MCU_EN;
2790 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2791 	ocp_data |= FMC_FCR_MCU_EN;
2792 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2793 }
2794 
2795 static void rtl8152_nic_reset(struct r8152 *tp)
2796 {
2797 	u32 ocp_data;
2798 	int i;
2799 
2800 	switch (tp->version) {
2801 	case RTL_TEST_01:
2802 	case RTL_VER_10:
2803 	case RTL_VER_11:
2804 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2805 		ocp_data &= ~CR_TE;
2806 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2807 
2808 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2809 		ocp_data &= ~BMU_RESET_EP_IN;
2810 		ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2811 
2812 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2813 		ocp_data |= CDC_ECM_EN;
2814 		ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2815 
2816 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2817 		ocp_data &= ~CR_RE;
2818 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2819 
2820 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2821 		ocp_data |= BMU_RESET_EP_IN;
2822 		ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2823 
2824 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2825 		ocp_data &= ~CDC_ECM_EN;
2826 		ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2827 		break;
2828 
2829 	default:
2830 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2831 
2832 		for (i = 0; i < 1000; i++) {
2833 			if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2834 				break;
2835 			usleep_range(100, 400);
2836 		}
2837 		break;
2838 	}
2839 }
2840 
2841 static void set_tx_qlen(struct r8152 *tp)
2842 {
2843 	tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));
2844 }
2845 
2846 static inline u16 rtl8152_get_speed(struct r8152 *tp)
2847 {
2848 	return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2849 }
2850 
2851 static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
2852 {
2853 	u32 ocp_data;
2854 
2855 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2856 	if (enable)
2857 		ocp_data |= EEEP_CR_EEEP_TX;
2858 	else
2859 		ocp_data &= ~EEEP_CR_EEEP_TX;
2860 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2861 }
2862 
2863 static void rtl_set_eee_plus(struct r8152 *tp)
2864 {
2865 	if (rtl8152_get_speed(tp) & _10bps)
2866 		rtl_eee_plus_en(tp, true);
2867 	else
2868 		rtl_eee_plus_en(tp, false);
2869 }
2870 
2871 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2872 {
2873 	u32 ocp_data;
2874 
2875 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2876 	if (enable)
2877 		ocp_data |= RXDY_GATED_EN;
2878 	else
2879 		ocp_data &= ~RXDY_GATED_EN;
2880 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2881 }
2882 
2883 static int rtl_start_rx(struct r8152 *tp)
2884 {
2885 	struct rx_agg *agg, *agg_next;
2886 	struct list_head tmp_list;
2887 	unsigned long flags;
2888 	int ret = 0, i = 0;
2889 
2890 	INIT_LIST_HEAD(&tmp_list);
2891 
2892 	spin_lock_irqsave(&tp->rx_lock, flags);
2893 
2894 	INIT_LIST_HEAD(&tp->rx_done);
2895 	INIT_LIST_HEAD(&tp->rx_used);
2896 
2897 	list_splice_init(&tp->rx_info, &tmp_list);
2898 
2899 	spin_unlock_irqrestore(&tp->rx_lock, flags);
2900 
2901 	list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2902 		INIT_LIST_HEAD(&agg->list);
2903 
2904 		/* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2905 		if (++i > RTL8152_MAX_RX) {
2906 			spin_lock_irqsave(&tp->rx_lock, flags);
2907 			list_add_tail(&agg->list, &tp->rx_used);
2908 			spin_unlock_irqrestore(&tp->rx_lock, flags);
2909 		} else if (unlikely(ret < 0)) {
2910 			spin_lock_irqsave(&tp->rx_lock, flags);
2911 			list_add_tail(&agg->list, &tp->rx_done);
2912 			spin_unlock_irqrestore(&tp->rx_lock, flags);
2913 		} else {
2914 			ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2915 		}
2916 	}
2917 
2918 	spin_lock_irqsave(&tp->rx_lock, flags);
2919 	WARN_ON(!list_empty(&tp->rx_info));
2920 	list_splice(&tmp_list, &tp->rx_info);
2921 	spin_unlock_irqrestore(&tp->rx_lock, flags);
2922 
2923 	return ret;
2924 }
2925 
2926 static int rtl_stop_rx(struct r8152 *tp)
2927 {
2928 	struct rx_agg *agg, *agg_next;
2929 	struct list_head tmp_list;
2930 	unsigned long flags;
2931 
2932 	INIT_LIST_HEAD(&tmp_list);
2933 
2934 	/* The usb_kill_urb() couldn't be used in atomic.
2935 	 * Therefore, move the list of rx_info to a tmp one.
2936 	 * Then, list_for_each_entry_safe could be used without
2937 	 * spin lock.
2938 	 */
2939 
2940 	spin_lock_irqsave(&tp->rx_lock, flags);
2941 	list_splice_init(&tp->rx_info, &tmp_list);
2942 	spin_unlock_irqrestore(&tp->rx_lock, flags);
2943 
2944 	list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2945 		/* At least RTL8152_MAX_RX rx_agg have the page_count being
2946 		 * equal to 1, so the other ones could be freed safely.
2947 		 */
2948 		if (page_count(agg->page) > 1)
2949 			free_rx_agg(tp, agg);
2950 		else
2951 			usb_kill_urb(agg->urb);
2952 	}
2953 
2954 	/* Move back the list of temp to the rx_info */
2955 	spin_lock_irqsave(&tp->rx_lock, flags);
2956 	WARN_ON(!list_empty(&tp->rx_info));
2957 	list_splice(&tmp_list, &tp->rx_info);
2958 	spin_unlock_irqrestore(&tp->rx_lock, flags);
2959 
2960 	while (!skb_queue_empty(&tp->rx_queue))
2961 		dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2962 
2963 	return 0;
2964 }
2965 
2966 static void rtl_set_ifg(struct r8152 *tp, u16 speed)
2967 {
2968 	u32 ocp_data;
2969 
2970 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
2971 	ocp_data &= ~IFG_MASK;
2972 	if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {
2973 		ocp_data |= IFG_144NS;
2974 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
2975 
2976 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
2977 		ocp_data &= ~TX10MIDLE_EN;
2978 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
2979 	} else {
2980 		ocp_data |= IFG_96NS;
2981 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
2982 
2983 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
2984 		ocp_data |= TX10MIDLE_EN;
2985 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
2986 	}
2987 }
2988 
2989 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2990 {
2991 	ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2992 		       OWN_UPDATE | OWN_CLEAR);
2993 }
2994 
2995 static int rtl_enable(struct r8152 *tp)
2996 {
2997 	u32 ocp_data;
2998 
2999 	r8152b_reset_packet_filter(tp);
3000 
3001 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
3002 	ocp_data |= CR_RE | CR_TE;
3003 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
3004 
3005 	switch (tp->version) {
3006 	case RTL_VER_08:
3007 	case RTL_VER_09:
3008 	case RTL_VER_14:
3009 		r8153b_rx_agg_chg_indicate(tp);
3010 		break;
3011 	default:
3012 		break;
3013 	}
3014 
3015 	rxdy_gated_en(tp, false);
3016 
3017 	return 0;
3018 }
3019 
3020 static int rtl8152_enable(struct r8152 *tp)
3021 {
3022 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
3023 		return -ENODEV;
3024 
3025 	set_tx_qlen(tp);
3026 	rtl_set_eee_plus(tp);
3027 
3028 	return rtl_enable(tp);
3029 }
3030 
3031 static void r8153_set_rx_early_timeout(struct r8152 *tp)
3032 {
3033 	u32 ocp_data = tp->coalesce / 8;
3034 
3035 	switch (tp->version) {
3036 	case RTL_VER_03:
3037 	case RTL_VER_04:
3038 	case RTL_VER_05:
3039 	case RTL_VER_06:
3040 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3041 			       ocp_data);
3042 		break;
3043 
3044 	case RTL_VER_08:
3045 	case RTL_VER_09:
3046 	case RTL_VER_14:
3047 		/* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
3048 		 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
3049 		 */
3050 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3051 			       128 / 8);
3052 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3053 			       ocp_data);
3054 		break;
3055 
3056 	case RTL_VER_10:
3057 	case RTL_VER_11:
3058 	case RTL_VER_12:
3059 	case RTL_VER_13:
3060 	case RTL_VER_15:
3061 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3062 			       640 / 8);
3063 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3064 			       ocp_data);
3065 		r8153b_rx_agg_chg_indicate(tp);
3066 		break;
3067 
3068 	default:
3069 		break;
3070 	}
3071 }
3072 
3073 static void r8153_set_rx_early_size(struct r8152 *tp)
3074 {
3075 	u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
3076 
3077 	switch (tp->version) {
3078 	case RTL_VER_03:
3079 	case RTL_VER_04:
3080 	case RTL_VER_05:
3081 	case RTL_VER_06:
3082 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3083 			       ocp_data / 4);
3084 		break;
3085 	case RTL_VER_08:
3086 	case RTL_VER_09:
3087 	case RTL_VER_14:
3088 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3089 			       ocp_data / 8);
3090 		break;
3091 	case RTL_TEST_01:
3092 	case RTL_VER_10:
3093 	case RTL_VER_11:
3094 	case RTL_VER_12:
3095 	case RTL_VER_13:
3096 	case RTL_VER_15:
3097 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3098 			       ocp_data / 8);
3099 		r8153b_rx_agg_chg_indicate(tp);
3100 		break;
3101 	default:
3102 		WARN_ON_ONCE(1);
3103 		break;
3104 	}
3105 }
3106 
3107 static int rtl8153_enable(struct r8152 *tp)
3108 {
3109 	u32 ocp_data;
3110 
3111 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
3112 		return -ENODEV;
3113 
3114 	set_tx_qlen(tp);
3115 	rtl_set_eee_plus(tp);
3116 	r8153_set_rx_early_timeout(tp);
3117 	r8153_set_rx_early_size(tp);
3118 
3119 	rtl_set_ifg(tp, rtl8152_get_speed(tp));
3120 
3121 	switch (tp->version) {
3122 	case RTL_VER_09:
3123 	case RTL_VER_14:
3124 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
3125 		ocp_data &= ~FC_PATCH_TASK;
3126 		ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3127 		usleep_range(1000, 2000);
3128 		ocp_data |= FC_PATCH_TASK;
3129 		ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3130 		break;
3131 	default:
3132 		break;
3133 	}
3134 
3135 	return rtl_enable(tp);
3136 }
3137 
3138 static void rtl_disable(struct r8152 *tp)
3139 {
3140 	u32 ocp_data;
3141 	int i;
3142 
3143 	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3144 		rtl_drop_queued_tx(tp);
3145 		return;
3146 	}
3147 
3148 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3149 	ocp_data &= ~RCR_ACPT_ALL;
3150 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3151 
3152 	rtl_drop_queued_tx(tp);
3153 
3154 	for (i = 0; i < RTL8152_MAX_TX; i++)
3155 		usb_kill_urb(tp->tx_info[i].urb);
3156 
3157 	rxdy_gated_en(tp, true);
3158 
3159 	for (i = 0; i < 1000; i++) {
3160 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3161 		if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
3162 			break;
3163 		usleep_range(1000, 2000);
3164 	}
3165 
3166 	for (i = 0; i < 1000; i++) {
3167 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
3168 			break;
3169 		usleep_range(1000, 2000);
3170 	}
3171 
3172 	rtl_stop_rx(tp);
3173 
3174 	rtl8152_nic_reset(tp);
3175 }
3176 
3177 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
3178 {
3179 	u32 ocp_data;
3180 
3181 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
3182 	if (enable)
3183 		ocp_data |= POWER_CUT;
3184 	else
3185 		ocp_data &= ~POWER_CUT;
3186 	ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
3187 
3188 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
3189 	ocp_data &= ~RESUME_INDICATE;
3190 	ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
3191 }
3192 
3193 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
3194 {
3195 	u32 ocp_data;
3196 
3197 	switch (tp->version) {
3198 	case RTL_VER_01:
3199 	case RTL_VER_02:
3200 	case RTL_VER_03:
3201 	case RTL_VER_04:
3202 	case RTL_VER_05:
3203 	case RTL_VER_06:
3204 	case RTL_VER_07:
3205 	case RTL_VER_08:
3206 	case RTL_VER_09:
3207 	case RTL_VER_14:
3208 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
3209 		if (enable)
3210 			ocp_data |= CPCR_RX_VLAN;
3211 		else
3212 			ocp_data &= ~CPCR_RX_VLAN;
3213 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
3214 		break;
3215 
3216 	case RTL_TEST_01:
3217 	case RTL_VER_10:
3218 	case RTL_VER_11:
3219 	case RTL_VER_12:
3220 	case RTL_VER_13:
3221 	case RTL_VER_15:
3222 	default:
3223 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
3224 		if (enable)
3225 			ocp_data |= OUTER_VLAN | INNER_VLAN;
3226 		else
3227 			ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
3228 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data);
3229 		break;
3230 	}
3231 }
3232 
3233 static int rtl8152_set_features(struct net_device *dev,
3234 				netdev_features_t features)
3235 {
3236 	netdev_features_t changed = features ^ dev->features;
3237 	struct r8152 *tp = netdev_priv(dev);
3238 	int ret;
3239 
3240 	ret = usb_autopm_get_interface(tp->intf);
3241 	if (ret < 0)
3242 		goto out;
3243 
3244 	mutex_lock(&tp->control);
3245 
3246 	if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
3247 		if (features & NETIF_F_HW_VLAN_CTAG_RX)
3248 			rtl_rx_vlan_en(tp, true);
3249 		else
3250 			rtl_rx_vlan_en(tp, false);
3251 	}
3252 
3253 	mutex_unlock(&tp->control);
3254 
3255 	usb_autopm_put_interface(tp->intf);
3256 
3257 out:
3258 	return ret;
3259 }
3260 
3261 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
3262 
3263 static u32 __rtl_get_wol(struct r8152 *tp)
3264 {
3265 	u32 ocp_data;
3266 	u32 wolopts = 0;
3267 
3268 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3269 	if (ocp_data & LINK_ON_WAKE_EN)
3270 		wolopts |= WAKE_PHY;
3271 
3272 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3273 	if (ocp_data & UWF_EN)
3274 		wolopts |= WAKE_UCAST;
3275 	if (ocp_data & BWF_EN)
3276 		wolopts |= WAKE_BCAST;
3277 	if (ocp_data & MWF_EN)
3278 		wolopts |= WAKE_MCAST;
3279 
3280 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3281 	if (ocp_data & MAGIC_EN)
3282 		wolopts |= WAKE_MAGIC;
3283 
3284 	return wolopts;
3285 }
3286 
3287 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3288 {
3289 	u32 ocp_data;
3290 
3291 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3292 
3293 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3294 	ocp_data &= ~LINK_ON_WAKE_EN;
3295 	if (wolopts & WAKE_PHY)
3296 		ocp_data |= LINK_ON_WAKE_EN;
3297 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3298 
3299 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3300 	ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3301 	if (wolopts & WAKE_UCAST)
3302 		ocp_data |= UWF_EN;
3303 	if (wolopts & WAKE_BCAST)
3304 		ocp_data |= BWF_EN;
3305 	if (wolopts & WAKE_MCAST)
3306 		ocp_data |= MWF_EN;
3307 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3308 
3309 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3310 
3311 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3312 	ocp_data &= ~MAGIC_EN;
3313 	if (wolopts & WAKE_MAGIC)
3314 		ocp_data |= MAGIC_EN;
3315 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3316 
3317 	if (wolopts & WAKE_ANY)
3318 		device_set_wakeup_enable(&tp->udev->dev, true);
3319 	else
3320 		device_set_wakeup_enable(&tp->udev->dev, false);
3321 }
3322 
3323 static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)
3324 {
3325 	u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3326 
3327 	/* MAC clock speed down */
3328 	if (enable)
3329 		ocp_data |= MAC_CLK_SPDWN_EN;
3330 	else
3331 		ocp_data &= ~MAC_CLK_SPDWN_EN;
3332 
3333 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3334 }
3335 
3336 static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)
3337 {
3338 	u32 ocp_data;
3339 
3340 	/* MAC clock speed down */
3341 	if (enable) {
3342 		/* aldps_spdwn_ratio, tp10_spdwn_ratio */
3343 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3344 			       0x0403);
3345 
3346 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3347 		ocp_data &= ~EEE_SPDWN_RATIO_MASK;
3348 		ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */
3349 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3350 	} else {
3351 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3352 		ocp_data &= ~MAC_CLK_SPDWN_EN;
3353 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3354 	}
3355 }
3356 
3357 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3358 {
3359 	u8 u1u2[8];
3360 
3361 	if (enable)
3362 		memset(u1u2, 0xff, sizeof(u1u2));
3363 	else
3364 		memset(u1u2, 0x00, sizeof(u1u2));
3365 
3366 	usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3367 }
3368 
3369 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3370 {
3371 	u32 ocp_data;
3372 
3373 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3374 	if (enable)
3375 		ocp_data |= LPM_U1U2_EN;
3376 	else
3377 		ocp_data &= ~LPM_U1U2_EN;
3378 
3379 	ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3380 }
3381 
3382 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3383 {
3384 	u32 ocp_data;
3385 
3386 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3387 	if (enable)
3388 		ocp_data |= U2P3_ENABLE;
3389 	else
3390 		ocp_data &= ~U2P3_ENABLE;
3391 	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3392 }
3393 
3394 static void r8153b_ups_flags(struct r8152 *tp)
3395 {
3396 	u32 ups_flags = 0;
3397 
3398 	if (tp->ups_info.green)
3399 		ups_flags |= UPS_FLAGS_EN_GREEN;
3400 
3401 	if (tp->ups_info.aldps)
3402 		ups_flags |= UPS_FLAGS_EN_ALDPS;
3403 
3404 	if (tp->ups_info.eee)
3405 		ups_flags |= UPS_FLAGS_EN_EEE;
3406 
3407 	if (tp->ups_info.flow_control)
3408 		ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3409 
3410 	if (tp->ups_info.eee_ckdiv)
3411 		ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3412 
3413 	if (tp->ups_info.eee_cmod_lv)
3414 		ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3415 
3416 	if (tp->ups_info.r_tune)
3417 		ups_flags |= UPS_FLAGS_R_TUNE;
3418 
3419 	if (tp->ups_info._10m_ckdiv)
3420 		ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3421 
3422 	if (tp->ups_info.eee_plloff_100)
3423 		ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3424 
3425 	if (tp->ups_info.eee_plloff_giga)
3426 		ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3427 
3428 	if (tp->ups_info._250m_ckdiv)
3429 		ups_flags |= UPS_FLAGS_250M_CKDIV;
3430 
3431 	if (tp->ups_info.ctap_short_off)
3432 		ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3433 
3434 	switch (tp->ups_info.speed_duplex) {
3435 	case NWAY_10M_HALF:
3436 		ups_flags |= ups_flags_speed(1);
3437 		break;
3438 	case NWAY_10M_FULL:
3439 		ups_flags |= ups_flags_speed(2);
3440 		break;
3441 	case NWAY_100M_HALF:
3442 		ups_flags |= ups_flags_speed(3);
3443 		break;
3444 	case NWAY_100M_FULL:
3445 		ups_flags |= ups_flags_speed(4);
3446 		break;
3447 	case NWAY_1000M_FULL:
3448 		ups_flags |= ups_flags_speed(5);
3449 		break;
3450 	case FORCE_10M_HALF:
3451 		ups_flags |= ups_flags_speed(6);
3452 		break;
3453 	case FORCE_10M_FULL:
3454 		ups_flags |= ups_flags_speed(7);
3455 		break;
3456 	case FORCE_100M_HALF:
3457 		ups_flags |= ups_flags_speed(8);
3458 		break;
3459 	case FORCE_100M_FULL:
3460 		ups_flags |= ups_flags_speed(9);
3461 		break;
3462 	default:
3463 		break;
3464 	}
3465 
3466 	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3467 }
3468 
3469 static void r8156_ups_flags(struct r8152 *tp)
3470 {
3471 	u32 ups_flags = 0;
3472 
3473 	if (tp->ups_info.green)
3474 		ups_flags |= UPS_FLAGS_EN_GREEN;
3475 
3476 	if (tp->ups_info.aldps)
3477 		ups_flags |= UPS_FLAGS_EN_ALDPS;
3478 
3479 	if (tp->ups_info.eee)
3480 		ups_flags |= UPS_FLAGS_EN_EEE;
3481 
3482 	if (tp->ups_info.flow_control)
3483 		ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3484 
3485 	if (tp->ups_info.eee_ckdiv)
3486 		ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3487 
3488 	if (tp->ups_info._10m_ckdiv)
3489 		ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3490 
3491 	if (tp->ups_info.eee_plloff_100)
3492 		ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3493 
3494 	if (tp->ups_info.eee_plloff_giga)
3495 		ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3496 
3497 	if (tp->ups_info._250m_ckdiv)
3498 		ups_flags |= UPS_FLAGS_250M_CKDIV;
3499 
3500 	switch (tp->ups_info.speed_duplex) {
3501 	case FORCE_10M_HALF:
3502 		ups_flags |= ups_flags_speed(0);
3503 		break;
3504 	case FORCE_10M_FULL:
3505 		ups_flags |= ups_flags_speed(1);
3506 		break;
3507 	case FORCE_100M_HALF:
3508 		ups_flags |= ups_flags_speed(2);
3509 		break;
3510 	case FORCE_100M_FULL:
3511 		ups_flags |= ups_flags_speed(3);
3512 		break;
3513 	case NWAY_10M_HALF:
3514 		ups_flags |= ups_flags_speed(4);
3515 		break;
3516 	case NWAY_10M_FULL:
3517 		ups_flags |= ups_flags_speed(5);
3518 		break;
3519 	case NWAY_100M_HALF:
3520 		ups_flags |= ups_flags_speed(6);
3521 		break;
3522 	case NWAY_100M_FULL:
3523 		ups_flags |= ups_flags_speed(7);
3524 		break;
3525 	case NWAY_1000M_FULL:
3526 		ups_flags |= ups_flags_speed(8);
3527 		break;
3528 	case NWAY_2500M_FULL:
3529 		ups_flags |= ups_flags_speed(9);
3530 		break;
3531 	default:
3532 		break;
3533 	}
3534 
3535 	switch (tp->ups_info.lite_mode) {
3536 	case 1:
3537 		ups_flags |= 0 << 5;
3538 		break;
3539 	case 2:
3540 		ups_flags |= 2 << 5;
3541 		break;
3542 	case 0:
3543 	default:
3544 		ups_flags |= 1 << 5;
3545 		break;
3546 	}
3547 
3548 	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3549 }
3550 
3551 static void rtl_green_en(struct r8152 *tp, bool enable)
3552 {
3553 	u16 data;
3554 
3555 	data = sram_read(tp, SRAM_GREEN_CFG);
3556 	if (enable)
3557 		data |= GREEN_ETH_EN;
3558 	else
3559 		data &= ~GREEN_ETH_EN;
3560 	sram_write(tp, SRAM_GREEN_CFG, data);
3561 
3562 	tp->ups_info.green = enable;
3563 }
3564 
3565 static void r8153b_green_en(struct r8152 *tp, bool enable)
3566 {
3567 	if (enable) {
3568 		sram_write(tp, 0x8045, 0);	/* 10M abiq&ldvbias */
3569 		sram_write(tp, 0x804d, 0x1222);	/* 100M short abiq&ldvbias */
3570 		sram_write(tp, 0x805d, 0x0022);	/* 1000M short abiq&ldvbias */
3571 	} else {
3572 		sram_write(tp, 0x8045, 0x2444);	/* 10M abiq&ldvbias */
3573 		sram_write(tp, 0x804d, 0x2444);	/* 100M short abiq&ldvbias */
3574 		sram_write(tp, 0x805d, 0x2444);	/* 1000M short abiq&ldvbias */
3575 	}
3576 
3577 	rtl_green_en(tp, true);
3578 }
3579 
3580 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3581 {
3582 	u16 data;
3583 	int i;
3584 
3585 	for (i = 0; i < 500; i++) {
3586 		data = ocp_reg_read(tp, OCP_PHY_STATUS);
3587 		data &= PHY_STAT_MASK;
3588 		if (desired) {
3589 			if (data == desired)
3590 				break;
3591 		} else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3592 			   data == PHY_STAT_EXT_INIT) {
3593 			break;
3594 		}
3595 
3596 		msleep(20);
3597 		if (test_bit(RTL8152_UNPLUG, &tp->flags))
3598 			break;
3599 	}
3600 
3601 	return data;
3602 }
3603 
3604 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3605 {
3606 	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3607 
3608 	if (enable) {
3609 		r8153b_ups_flags(tp);
3610 
3611 		ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3612 		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3613 
3614 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3615 		ocp_data |= UPS_FORCE_PWR_DOWN;
3616 		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3617 	} else {
3618 		ocp_data &= ~(UPS_EN | USP_PREWAKE);
3619 		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3620 
3621 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3622 		ocp_data &= ~UPS_FORCE_PWR_DOWN;
3623 		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3624 
3625 		if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3626 			int i;
3627 
3628 			for (i = 0; i < 500; i++) {
3629 				if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3630 				    AUTOLOAD_DONE)
3631 					break;
3632 				msleep(20);
3633 			}
3634 
3635 			tp->rtl_ops.hw_phy_cfg(tp);
3636 
3637 			rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3638 					  tp->duplex, tp->advertising);
3639 		}
3640 	}
3641 }
3642 
3643 static void r8153c_ups_en(struct r8152 *tp, bool enable)
3644 {
3645 	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3646 
3647 	if (enable) {
3648 		r8153b_ups_flags(tp);
3649 
3650 		ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3651 		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3652 
3653 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3654 		ocp_data |= UPS_FORCE_PWR_DOWN;
3655 		ocp_data &= ~BIT(7);
3656 		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3657 	} else {
3658 		ocp_data &= ~(UPS_EN | USP_PREWAKE);
3659 		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3660 
3661 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3662 		ocp_data &= ~UPS_FORCE_PWR_DOWN;
3663 		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3664 
3665 		if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3666 			int i;
3667 
3668 			for (i = 0; i < 500; i++) {
3669 				if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3670 				    AUTOLOAD_DONE)
3671 					break;
3672 				msleep(20);
3673 			}
3674 
3675 			tp->rtl_ops.hw_phy_cfg(tp);
3676 
3677 			rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3678 					  tp->duplex, tp->advertising);
3679 		}
3680 
3681 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3682 
3683 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3684 		ocp_data |= BIT(8);
3685 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3686 
3687 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3688 	}
3689 }
3690 
3691 static void r8156_ups_en(struct r8152 *tp, bool enable)
3692 {
3693 	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3694 
3695 	if (enable) {
3696 		r8156_ups_flags(tp);
3697 
3698 		ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3699 		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3700 
3701 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3702 		ocp_data |= UPS_FORCE_PWR_DOWN;
3703 		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3704 
3705 		switch (tp->version) {
3706 		case RTL_VER_13:
3707 		case RTL_VER_15:
3708 			ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
3709 			ocp_data &= ~OOBS_POLLING;
3710 			ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);
3711 			break;
3712 		default:
3713 			break;
3714 		}
3715 	} else {
3716 		ocp_data &= ~(UPS_EN | USP_PREWAKE);
3717 		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3718 
3719 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3720 		ocp_data &= ~UPS_FORCE_PWR_DOWN;
3721 		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3722 
3723 		if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3724 			tp->rtl_ops.hw_phy_cfg(tp);
3725 
3726 			rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3727 					  tp->duplex, tp->advertising);
3728 		}
3729 	}
3730 }
3731 
3732 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3733 {
3734 	u32 ocp_data;
3735 
3736 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3737 	if (enable)
3738 		ocp_data |= PWR_EN | PHASE2_EN;
3739 	else
3740 		ocp_data &= ~(PWR_EN | PHASE2_EN);
3741 	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3742 
3743 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3744 	ocp_data &= ~PCUT_STATUS;
3745 	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3746 }
3747 
3748 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3749 {
3750 	u32 ocp_data;
3751 
3752 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3753 	if (enable)
3754 		ocp_data |= PWR_EN | PHASE2_EN;
3755 	else
3756 		ocp_data &= ~PWR_EN;
3757 	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3758 
3759 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3760 	ocp_data &= ~PCUT_STATUS;
3761 	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3762 }
3763 
3764 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3765 {
3766 	u32 ocp_data;
3767 
3768 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3769 	if (enable)
3770 		ocp_data |= UPCOMING_RUNTIME_D3;
3771 	else
3772 		ocp_data &= ~UPCOMING_RUNTIME_D3;
3773 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3774 
3775 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3776 	ocp_data &= ~LINK_CHG_EVENT;
3777 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3778 
3779 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3780 	ocp_data &= ~LINK_CHANGE_FLAG;
3781 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3782 }
3783 
3784 static bool rtl_can_wakeup(struct r8152 *tp)
3785 {
3786 	struct usb_device *udev = tp->udev;
3787 
3788 	return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3789 }
3790 
3791 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3792 {
3793 	if (enable) {
3794 		u32 ocp_data;
3795 
3796 		__rtl_set_wol(tp, WAKE_ANY);
3797 
3798 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3799 
3800 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3801 		ocp_data |= LINK_OFF_WAKE_EN;
3802 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3803 
3804 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3805 	} else {
3806 		u32 ocp_data;
3807 
3808 		__rtl_set_wol(tp, tp->saved_wolopts);
3809 
3810 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3811 
3812 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3813 		ocp_data &= ~LINK_OFF_WAKE_EN;
3814 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3815 
3816 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3817 	}
3818 }
3819 
3820 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3821 {
3822 	if (enable) {
3823 		r8153_u1u2en(tp, false);
3824 		r8153_u2p3en(tp, false);
3825 		rtl_runtime_suspend_enable(tp, true);
3826 	} else {
3827 		rtl_runtime_suspend_enable(tp, false);
3828 
3829 		switch (tp->version) {
3830 		case RTL_VER_03:
3831 		case RTL_VER_04:
3832 			break;
3833 		case RTL_VER_05:
3834 		case RTL_VER_06:
3835 		default:
3836 			r8153_u2p3en(tp, true);
3837 			break;
3838 		}
3839 
3840 		r8153_u1u2en(tp, true);
3841 	}
3842 }
3843 
3844 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3845 {
3846 	if (enable) {
3847 		r8153_queue_wake(tp, true);
3848 		r8153b_u1u2en(tp, false);
3849 		r8153_u2p3en(tp, false);
3850 		rtl_runtime_suspend_enable(tp, true);
3851 		r8153b_ups_en(tp, true);
3852 	} else {
3853 		r8153b_ups_en(tp, false);
3854 		r8153_queue_wake(tp, false);
3855 		rtl_runtime_suspend_enable(tp, false);
3856 		if (tp->udev->speed >= USB_SPEED_SUPER)
3857 			r8153b_u1u2en(tp, true);
3858 	}
3859 }
3860 
3861 static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)
3862 {
3863 	if (enable) {
3864 		r8153_queue_wake(tp, true);
3865 		r8153b_u1u2en(tp, false);
3866 		r8153_u2p3en(tp, false);
3867 		rtl_runtime_suspend_enable(tp, true);
3868 		r8153c_ups_en(tp, true);
3869 	} else {
3870 		r8153c_ups_en(tp, false);
3871 		r8153_queue_wake(tp, false);
3872 		rtl_runtime_suspend_enable(tp, false);
3873 		r8153b_u1u2en(tp, true);
3874 	}
3875 }
3876 
3877 static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)
3878 {
3879 	if (enable) {
3880 		r8153_queue_wake(tp, true);
3881 		r8153b_u1u2en(tp, false);
3882 		r8153_u2p3en(tp, false);
3883 		rtl_runtime_suspend_enable(tp, true);
3884 	} else {
3885 		r8153_queue_wake(tp, false);
3886 		rtl_runtime_suspend_enable(tp, false);
3887 		r8153_u2p3en(tp, true);
3888 		if (tp->udev->speed >= USB_SPEED_SUPER)
3889 			r8153b_u1u2en(tp, true);
3890 	}
3891 }
3892 
3893 static void r8153_teredo_off(struct r8152 *tp)
3894 {
3895 	u32 ocp_data;
3896 
3897 	switch (tp->version) {
3898 	case RTL_VER_01:
3899 	case RTL_VER_02:
3900 	case RTL_VER_03:
3901 	case RTL_VER_04:
3902 	case RTL_VER_05:
3903 	case RTL_VER_06:
3904 	case RTL_VER_07:
3905 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3906 		ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3907 			      OOB_TEREDO_EN);
3908 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3909 		break;
3910 
3911 	case RTL_VER_08:
3912 	case RTL_VER_09:
3913 	case RTL_TEST_01:
3914 	case RTL_VER_10:
3915 	case RTL_VER_11:
3916 	case RTL_VER_12:
3917 	case RTL_VER_13:
3918 	case RTL_VER_14:
3919 	case RTL_VER_15:
3920 	default:
3921 		/* The bit 0 ~ 7 are relative with teredo settings. They are
3922 		 * W1C (write 1 to clear), so set all 1 to disable it.
3923 		 */
3924 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3925 		break;
3926 	}
3927 
3928 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3929 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3930 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3931 }
3932 
3933 static void rtl_reset_bmu(struct r8152 *tp)
3934 {
3935 	u32 ocp_data;
3936 
3937 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3938 	ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3939 	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3940 	ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3941 	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3942 }
3943 
3944 /* Clear the bp to stop the firmware before loading a new one */
3945 static void rtl_clear_bp(struct r8152 *tp, u16 type)
3946 {
3947 	switch (tp->version) {
3948 	case RTL_VER_01:
3949 	case RTL_VER_02:
3950 	case RTL_VER_07:
3951 		break;
3952 	case RTL_VER_03:
3953 	case RTL_VER_04:
3954 	case RTL_VER_05:
3955 	case RTL_VER_06:
3956 		ocp_write_byte(tp, type, PLA_BP_EN, 0);
3957 		break;
3958 	case RTL_VER_08:
3959 	case RTL_VER_09:
3960 	case RTL_VER_10:
3961 	case RTL_VER_11:
3962 	case RTL_VER_12:
3963 	case RTL_VER_13:
3964 	case RTL_VER_14:
3965 	case RTL_VER_15:
3966 	default:
3967 		if (type == MCU_TYPE_USB) {
3968 			ocp_write_byte(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
3969 
3970 			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
3971 			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
3972 			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
3973 			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
3974 			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
3975 			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
3976 			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
3977 			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
3978 		} else {
3979 			ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
3980 		}
3981 		break;
3982 	}
3983 
3984 	ocp_write_word(tp, type, PLA_BP_0, 0);
3985 	ocp_write_word(tp, type, PLA_BP_1, 0);
3986 	ocp_write_word(tp, type, PLA_BP_2, 0);
3987 	ocp_write_word(tp, type, PLA_BP_3, 0);
3988 	ocp_write_word(tp, type, PLA_BP_4, 0);
3989 	ocp_write_word(tp, type, PLA_BP_5, 0);
3990 	ocp_write_word(tp, type, PLA_BP_6, 0);
3991 	ocp_write_word(tp, type, PLA_BP_7, 0);
3992 
3993 	/* wait 3 ms to make sure the firmware is stopped */
3994 	usleep_range(3000, 6000);
3995 	ocp_write_word(tp, type, PLA_BP_BA, 0);
3996 }
3997 
3998 static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
3999 {
4000 	u16 data, check;
4001 	int i;
4002 
4003 	data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
4004 	if (request) {
4005 		data |= PATCH_REQUEST;
4006 		check = 0;
4007 	} else {
4008 		data &= ~PATCH_REQUEST;
4009 		check = PATCH_READY;
4010 	}
4011 	ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
4012 
4013 	for (i = 0; wait && i < 5000; i++) {
4014 		u32 ocp_data;
4015 
4016 		usleep_range(1000, 2000);
4017 		ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
4018 		if ((ocp_data & PATCH_READY) ^ check)
4019 			break;
4020 	}
4021 
4022 	if (request && wait &&
4023 	    !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
4024 		dev_err(&tp->intf->dev, "PHY patch request fail\n");
4025 		rtl_phy_patch_request(tp, false, false);
4026 		return -ETIME;
4027 	} else {
4028 		return 0;
4029 	}
4030 }
4031 
4032 static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)
4033 {
4034 	if (patch_key && key_addr) {
4035 		sram_write(tp, key_addr, patch_key);
4036 		sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
4037 	} else if (key_addr) {
4038 		u16 data;
4039 
4040 		sram_write(tp, 0x0000, 0x0000);
4041 
4042 		data = ocp_reg_read(tp, OCP_PHY_LOCK);
4043 		data &= ~PATCH_LOCK;
4044 		ocp_reg_write(tp, OCP_PHY_LOCK, data);
4045 
4046 		sram_write(tp, key_addr, 0x0000);
4047 	} else {
4048 		WARN_ON_ONCE(1);
4049 	}
4050 }
4051 
4052 static int
4053 rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)
4054 {
4055 	if (rtl_phy_patch_request(tp, true, wait))
4056 		return -ETIME;
4057 
4058 	rtl_patch_key_set(tp, key_addr, patch_key);
4059 
4060 	return 0;
4061 }
4062 
4063 static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)
4064 {
4065 	rtl_patch_key_set(tp, key_addr, 0);
4066 
4067 	rtl_phy_patch_request(tp, false, wait);
4068 
4069 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
4070 
4071 	return 0;
4072 }
4073 
4074 static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy)
4075 {
4076 	u16 fw_offset;
4077 	u32 length;
4078 	bool rc = false;
4079 
4080 	switch (tp->version) {
4081 	case RTL_VER_01:
4082 	case RTL_VER_02:
4083 	case RTL_VER_03:
4084 	case RTL_VER_04:
4085 	case RTL_VER_05:
4086 	case RTL_VER_06:
4087 	case RTL_VER_07:
4088 	case RTL_VER_08:
4089 	case RTL_VER_09:
4090 	case RTL_VER_10:
4091 	case RTL_VER_11:
4092 	case RTL_VER_12:
4093 	case RTL_VER_14:
4094 		goto out;
4095 	case RTL_VER_13:
4096 	case RTL_VER_15:
4097 	default:
4098 		break;
4099 	}
4100 
4101 	fw_offset = __le16_to_cpu(phy->fw_offset);
4102 	length = __le32_to_cpu(phy->blk_hdr.length);
4103 	if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4104 		dev_err(&tp->intf->dev, "invalid fw_offset\n");
4105 		goto out;
4106 	}
4107 
4108 	length -= fw_offset;
4109 	if (length & 3) {
4110 		dev_err(&tp->intf->dev, "invalid block length\n");
4111 		goto out;
4112 	}
4113 
4114 	if (__le16_to_cpu(phy->fw_reg) != 0x9A00) {
4115 		dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4116 		goto out;
4117 	}
4118 
4119 	rc = true;
4120 out:
4121 	return rc;
4122 }
4123 
4124 static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver)
4125 {
4126 	bool rc = false;
4127 
4128 	switch (tp->version) {
4129 	case RTL_VER_10:
4130 	case RTL_VER_11:
4131 	case RTL_VER_12:
4132 	case RTL_VER_13:
4133 	case RTL_VER_15:
4134 		break;
4135 	default:
4136 		goto out;
4137 	}
4138 
4139 	if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) {
4140 		dev_err(&tp->intf->dev, "invalid block length\n");
4141 		goto out;
4142 	}
4143 
4144 	if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) {
4145 		dev_err(&tp->intf->dev, "invalid phy ver addr\n");
4146 		goto out;
4147 	}
4148 
4149 	rc = true;
4150 out:
4151 	return rc;
4152 }
4153 
4154 static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix)
4155 {
4156 	bool rc = false;
4157 
4158 	switch (tp->version) {
4159 	case RTL_VER_10:
4160 	case RTL_VER_11:
4161 	case RTL_VER_12:
4162 	case RTL_VER_13:
4163 	case RTL_VER_15:
4164 		break;
4165 	default:
4166 		goto out;
4167 	}
4168 
4169 	if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) {
4170 		dev_err(&tp->intf->dev, "invalid block length\n");
4171 		goto out;
4172 	}
4173 
4174 	if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD ||
4175 	    __le16_to_cpu(fix->setting.data) != BIT(7)) {
4176 		dev_err(&tp->intf->dev, "invalid phy fixup\n");
4177 		goto out;
4178 	}
4179 
4180 	rc = true;
4181 out:
4182 	return rc;
4183 }
4184 
4185 static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy)
4186 {
4187 	u16 fw_offset;
4188 	u32 length;
4189 	bool rc = false;
4190 
4191 	switch (tp->version) {
4192 	case RTL_VER_10:
4193 	case RTL_VER_11:
4194 	case RTL_VER_12:
4195 	case RTL_VER_13:
4196 	case RTL_VER_15:
4197 		break;
4198 	default:
4199 		goto out;
4200 	}
4201 
4202 	fw_offset = __le16_to_cpu(phy->fw_offset);
4203 	length = __le32_to_cpu(phy->blk_hdr.length);
4204 	if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4205 		dev_err(&tp->intf->dev, "invalid fw_offset\n");
4206 		goto out;
4207 	}
4208 
4209 	length -= fw_offset;
4210 	if (length & 1) {
4211 		dev_err(&tp->intf->dev, "invalid block length\n");
4212 		goto out;
4213 	}
4214 
4215 	if (phy->pre_num > 2) {
4216 		dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num);
4217 		goto out;
4218 	}
4219 
4220 	if (phy->bp_num > 8) {
4221 		dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num);
4222 		goto out;
4223 	}
4224 
4225 	rc = true;
4226 out:
4227 	return rc;
4228 }
4229 
4230 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
4231 {
4232 	u32 length;
4233 	u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
4234 	bool rc = false;
4235 
4236 	switch (tp->version) {
4237 	case RTL_VER_04:
4238 	case RTL_VER_05:
4239 	case RTL_VER_06:
4240 		fw_reg = 0xa014;
4241 		ba_reg = 0xa012;
4242 		patch_en_addr = 0xa01a;
4243 		mode_reg = 0xb820;
4244 		bp_start = 0xa000;
4245 		break;
4246 	default:
4247 		goto out;
4248 	}
4249 
4250 	fw_offset = __le16_to_cpu(phy->fw_offset);
4251 	if (fw_offset < sizeof(*phy)) {
4252 		dev_err(&tp->intf->dev, "fw_offset too small\n");
4253 		goto out;
4254 	}
4255 
4256 	length = __le32_to_cpu(phy->blk_hdr.length);
4257 	if (length < fw_offset) {
4258 		dev_err(&tp->intf->dev, "invalid fw_offset\n");
4259 		goto out;
4260 	}
4261 
4262 	length -= __le16_to_cpu(phy->fw_offset);
4263 	if (!length || (length & 1)) {
4264 		dev_err(&tp->intf->dev, "invalid block length\n");
4265 		goto out;
4266 	}
4267 
4268 	if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
4269 		dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4270 		goto out;
4271 	}
4272 
4273 	if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
4274 		dev_err(&tp->intf->dev, "invalid base address register\n");
4275 		goto out;
4276 	}
4277 
4278 	if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
4279 		dev_err(&tp->intf->dev,
4280 			"invalid patch mode enabled register\n");
4281 		goto out;
4282 	}
4283 
4284 	if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
4285 		dev_err(&tp->intf->dev,
4286 			"invalid register to switch the mode\n");
4287 		goto out;
4288 	}
4289 
4290 	if (__le16_to_cpu(phy->bp_start) != bp_start) {
4291 		dev_err(&tp->intf->dev,
4292 			"invalid start register of break point\n");
4293 		goto out;
4294 	}
4295 
4296 	if (__le16_to_cpu(phy->bp_num) > 4) {
4297 		dev_err(&tp->intf->dev, "invalid break point number\n");
4298 		goto out;
4299 	}
4300 
4301 	rc = true;
4302 out:
4303 	return rc;
4304 }
4305 
4306 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
4307 {
4308 	u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
4309 	bool rc = false;
4310 	u32 length, type;
4311 	int i, max_bp;
4312 
4313 	type = __le32_to_cpu(mac->blk_hdr.type);
4314 	if (type == RTL_FW_PLA) {
4315 		switch (tp->version) {
4316 		case RTL_VER_01:
4317 		case RTL_VER_02:
4318 		case RTL_VER_07:
4319 			fw_reg = 0xf800;
4320 			bp_ba_addr = PLA_BP_BA;
4321 			bp_en_addr = 0;
4322 			bp_start = PLA_BP_0;
4323 			max_bp = 8;
4324 			break;
4325 		case RTL_VER_03:
4326 		case RTL_VER_04:
4327 		case RTL_VER_05:
4328 		case RTL_VER_06:
4329 		case RTL_VER_08:
4330 		case RTL_VER_09:
4331 		case RTL_VER_11:
4332 		case RTL_VER_12:
4333 		case RTL_VER_13:
4334 		case RTL_VER_14:
4335 		case RTL_VER_15:
4336 			fw_reg = 0xf800;
4337 			bp_ba_addr = PLA_BP_BA;
4338 			bp_en_addr = PLA_BP_EN;
4339 			bp_start = PLA_BP_0;
4340 			max_bp = 8;
4341 			break;
4342 		default:
4343 			goto out;
4344 		}
4345 	} else if (type == RTL_FW_USB) {
4346 		switch (tp->version) {
4347 		case RTL_VER_03:
4348 		case RTL_VER_04:
4349 		case RTL_VER_05:
4350 		case RTL_VER_06:
4351 			fw_reg = 0xf800;
4352 			bp_ba_addr = USB_BP_BA;
4353 			bp_en_addr = USB_BP_EN;
4354 			bp_start = USB_BP_0;
4355 			max_bp = 8;
4356 			break;
4357 		case RTL_VER_08:
4358 		case RTL_VER_09:
4359 		case RTL_VER_11:
4360 		case RTL_VER_12:
4361 		case RTL_VER_13:
4362 		case RTL_VER_14:
4363 		case RTL_VER_15:
4364 			fw_reg = 0xe600;
4365 			bp_ba_addr = USB_BP_BA;
4366 			bp_en_addr = USB_BP2_EN;
4367 			bp_start = USB_BP_0;
4368 			max_bp = 16;
4369 			break;
4370 		case RTL_VER_01:
4371 		case RTL_VER_02:
4372 		case RTL_VER_07:
4373 		default:
4374 			goto out;
4375 		}
4376 	} else {
4377 		goto out;
4378 	}
4379 
4380 	fw_offset = __le16_to_cpu(mac->fw_offset);
4381 	if (fw_offset < sizeof(*mac)) {
4382 		dev_err(&tp->intf->dev, "fw_offset too small\n");
4383 		goto out;
4384 	}
4385 
4386 	length = __le32_to_cpu(mac->blk_hdr.length);
4387 	if (length < fw_offset) {
4388 		dev_err(&tp->intf->dev, "invalid fw_offset\n");
4389 		goto out;
4390 	}
4391 
4392 	length -= fw_offset;
4393 	if (length < 4 || (length & 3)) {
4394 		dev_err(&tp->intf->dev, "invalid block length\n");
4395 		goto out;
4396 	}
4397 
4398 	if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
4399 		dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4400 		goto out;
4401 	}
4402 
4403 	if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
4404 		dev_err(&tp->intf->dev, "invalid base address register\n");
4405 		goto out;
4406 	}
4407 
4408 	if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
4409 		dev_err(&tp->intf->dev, "invalid enabled mask register\n");
4410 		goto out;
4411 	}
4412 
4413 	if (__le16_to_cpu(mac->bp_start) != bp_start) {
4414 		dev_err(&tp->intf->dev,
4415 			"invalid start register of break point\n");
4416 		goto out;
4417 	}
4418 
4419 	if (__le16_to_cpu(mac->bp_num) > max_bp) {
4420 		dev_err(&tp->intf->dev, "invalid break point number\n");
4421 		goto out;
4422 	}
4423 
4424 	for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
4425 		if (mac->bp[i]) {
4426 			dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
4427 			goto out;
4428 		}
4429 	}
4430 
4431 	rc = true;
4432 out:
4433 	return rc;
4434 }
4435 
4436 /* Verify the checksum for the firmware file. It is calculated from the version
4437  * field to the end of the file. Compare the result with the checksum field to
4438  * make sure the file is correct.
4439  */
4440 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
4441 				       struct fw_header *fw_hdr, size_t size)
4442 {
4443 	unsigned char checksum[sizeof(fw_hdr->checksum)];
4444 	struct crypto_shash *alg;
4445 	struct shash_desc *sdesc;
4446 	size_t len;
4447 	long rc;
4448 
4449 	alg = crypto_alloc_shash("sha256", 0, 0);
4450 	if (IS_ERR(alg)) {
4451 		rc = PTR_ERR(alg);
4452 		goto out;
4453 	}
4454 
4455 	if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
4456 		rc = -EFAULT;
4457 		dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
4458 			crypto_shash_digestsize(alg));
4459 		goto free_shash;
4460 	}
4461 
4462 	len = sizeof(*sdesc) + crypto_shash_descsize(alg);
4463 	sdesc = kmalloc(len, GFP_KERNEL);
4464 	if (!sdesc) {
4465 		rc = -ENOMEM;
4466 		goto free_shash;
4467 	}
4468 	sdesc->tfm = alg;
4469 
4470 	len = size - sizeof(fw_hdr->checksum);
4471 	rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
4472 	kfree(sdesc);
4473 	if (rc)
4474 		goto free_shash;
4475 
4476 	if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
4477 		dev_err(&tp->intf->dev, "checksum fail\n");
4478 		rc = -EFAULT;
4479 	}
4480 
4481 free_shash:
4482 	crypto_free_shash(alg);
4483 out:
4484 	return rc;
4485 }
4486 
4487 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
4488 {
4489 	const struct firmware *fw = rtl_fw->fw;
4490 	struct fw_header *fw_hdr = (struct fw_header *)fw->data;
4491 	unsigned long fw_flags = 0;
4492 	long ret = -EFAULT;
4493 	int i;
4494 
4495 	if (fw->size < sizeof(*fw_hdr)) {
4496 		dev_err(&tp->intf->dev, "file too small\n");
4497 		goto fail;
4498 	}
4499 
4500 	ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
4501 	if (ret)
4502 		goto fail;
4503 
4504 	ret = -EFAULT;
4505 
4506 	for (i = sizeof(*fw_hdr); i < fw->size;) {
4507 		struct fw_block *block = (struct fw_block *)&fw->data[i];
4508 		u32 type;
4509 
4510 		if ((i + sizeof(*block)) > fw->size)
4511 			goto fail;
4512 
4513 		type = __le32_to_cpu(block->type);
4514 		switch (type) {
4515 		case RTL_FW_END:
4516 			if (__le32_to_cpu(block->length) != sizeof(*block))
4517 				goto fail;
4518 			goto fw_end;
4519 		case RTL_FW_PLA:
4520 			if (test_bit(FW_FLAGS_PLA, &fw_flags)) {
4521 				dev_err(&tp->intf->dev,
4522 					"multiple PLA firmware encountered");
4523 				goto fail;
4524 			}
4525 
4526 			if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4527 				dev_err(&tp->intf->dev,
4528 					"check PLA firmware failed\n");
4529 				goto fail;
4530 			}
4531 			__set_bit(FW_FLAGS_PLA, &fw_flags);
4532 			break;
4533 		case RTL_FW_USB:
4534 			if (test_bit(FW_FLAGS_USB, &fw_flags)) {
4535 				dev_err(&tp->intf->dev,
4536 					"multiple USB firmware encountered");
4537 				goto fail;
4538 			}
4539 
4540 			if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4541 				dev_err(&tp->intf->dev,
4542 					"check USB firmware failed\n");
4543 				goto fail;
4544 			}
4545 			__set_bit(FW_FLAGS_USB, &fw_flags);
4546 			break;
4547 		case RTL_FW_PHY_START:
4548 			if (test_bit(FW_FLAGS_START, &fw_flags) ||
4549 			    test_bit(FW_FLAGS_NC, &fw_flags) ||
4550 			    test_bit(FW_FLAGS_NC1, &fw_flags) ||
4551 			    test_bit(FW_FLAGS_NC2, &fw_flags) ||
4552 			    test_bit(FW_FLAGS_UC2, &fw_flags) ||
4553 			    test_bit(FW_FLAGS_UC, &fw_flags) ||
4554 			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
4555 				dev_err(&tp->intf->dev,
4556 					"check PHY_START fail\n");
4557 				goto fail;
4558 			}
4559 
4560 			if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) {
4561 				dev_err(&tp->intf->dev,
4562 					"Invalid length for PHY_START\n");
4563 				goto fail;
4564 			}
4565 			__set_bit(FW_FLAGS_START, &fw_flags);
4566 			break;
4567 		case RTL_FW_PHY_STOP:
4568 			if (test_bit(FW_FLAGS_STOP, &fw_flags) ||
4569 			    !test_bit(FW_FLAGS_START, &fw_flags)) {
4570 				dev_err(&tp->intf->dev,
4571 					"Check PHY_STOP fail\n");
4572 				goto fail;
4573 			}
4574 
4575 			if (__le32_to_cpu(block->length) != sizeof(*block)) {
4576 				dev_err(&tp->intf->dev,
4577 					"Invalid length for PHY_STOP\n");
4578 				goto fail;
4579 			}
4580 			__set_bit(FW_FLAGS_STOP, &fw_flags);
4581 			break;
4582 		case RTL_FW_PHY_NC:
4583 			if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4584 			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
4585 				dev_err(&tp->intf->dev,
4586 					"check PHY_NC fail\n");
4587 				goto fail;
4588 			}
4589 
4590 			if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4591 				dev_err(&tp->intf->dev,
4592 					"multiple PHY NC encountered\n");
4593 				goto fail;
4594 			}
4595 
4596 			if (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) {
4597 				dev_err(&tp->intf->dev,
4598 					"check PHY NC firmware failed\n");
4599 				goto fail;
4600 			}
4601 			__set_bit(FW_FLAGS_NC, &fw_flags);
4602 			break;
4603 		case RTL_FW_PHY_UNION_NC:
4604 			if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4605 			    test_bit(FW_FLAGS_NC1, &fw_flags) ||
4606 			    test_bit(FW_FLAGS_NC2, &fw_flags) ||
4607 			    test_bit(FW_FLAGS_UC2, &fw_flags) ||
4608 			    test_bit(FW_FLAGS_UC, &fw_flags) ||
4609 			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
4610 				dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n");
4611 				goto fail;
4612 			}
4613 
4614 			if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4615 				dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n");
4616 				goto fail;
4617 			}
4618 
4619 			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4620 				dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n");
4621 				goto fail;
4622 			}
4623 			__set_bit(FW_FLAGS_NC, &fw_flags);
4624 			break;
4625 		case RTL_FW_PHY_UNION_NC1:
4626 			if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4627 			    test_bit(FW_FLAGS_NC2, &fw_flags) ||
4628 			    test_bit(FW_FLAGS_UC2, &fw_flags) ||
4629 			    test_bit(FW_FLAGS_UC, &fw_flags) ||
4630 			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
4631 				dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n");
4632 				goto fail;
4633 			}
4634 
4635 			if (test_bit(FW_FLAGS_NC1, &fw_flags)) {
4636 				dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n");
4637 				goto fail;
4638 			}
4639 
4640 			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4641 				dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n");
4642 				goto fail;
4643 			}
4644 			__set_bit(FW_FLAGS_NC1, &fw_flags);
4645 			break;
4646 		case RTL_FW_PHY_UNION_NC2:
4647 			if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4648 			    test_bit(FW_FLAGS_UC2, &fw_flags) ||
4649 			    test_bit(FW_FLAGS_UC, &fw_flags) ||
4650 			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
4651 				dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n");
4652 				goto fail;
4653 			}
4654 
4655 			if (test_bit(FW_FLAGS_NC2, &fw_flags)) {
4656 				dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n");
4657 				goto fail;
4658 			}
4659 
4660 			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4661 				dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n");
4662 				goto fail;
4663 			}
4664 			__set_bit(FW_FLAGS_NC2, &fw_flags);
4665 			break;
4666 		case RTL_FW_PHY_UNION_UC2:
4667 			if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4668 			    test_bit(FW_FLAGS_UC, &fw_flags) ||
4669 			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
4670 				dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n");
4671 				goto fail;
4672 			}
4673 
4674 			if (test_bit(FW_FLAGS_UC2, &fw_flags)) {
4675 				dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n");
4676 				goto fail;
4677 			}
4678 
4679 			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4680 				dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n");
4681 				goto fail;
4682 			}
4683 			__set_bit(FW_FLAGS_UC2, &fw_flags);
4684 			break;
4685 		case RTL_FW_PHY_UNION_UC:
4686 			if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4687 			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
4688 				dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n");
4689 				goto fail;
4690 			}
4691 
4692 			if (test_bit(FW_FLAGS_UC, &fw_flags)) {
4693 				dev_err(&tp->intf->dev, "multiple PHY UC encountered\n");
4694 				goto fail;
4695 			}
4696 
4697 			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4698 				dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n");
4699 				goto fail;
4700 			}
4701 			__set_bit(FW_FLAGS_UC, &fw_flags);
4702 			break;
4703 		case RTL_FW_PHY_UNION_MISC:
4704 			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4705 				dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n");
4706 				goto fail;
4707 			}
4708 			break;
4709 		case RTL_FW_PHY_FIXUP:
4710 			if (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) {
4711 				dev_err(&tp->intf->dev, "check PHY fixup failed\n");
4712 				goto fail;
4713 			}
4714 			break;
4715 		case RTL_FW_PHY_SPEED_UP:
4716 			if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) {
4717 				dev_err(&tp->intf->dev, "multiple PHY firmware encountered");
4718 				goto fail;
4719 			}
4720 
4721 			if (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) {
4722 				dev_err(&tp->intf->dev, "check PHY speed up failed\n");
4723 				goto fail;
4724 			}
4725 			__set_bit(FW_FLAGS_SPEED_UP, &fw_flags);
4726 			break;
4727 		case RTL_FW_PHY_VER:
4728 			if (test_bit(FW_FLAGS_START, &fw_flags) ||
4729 			    test_bit(FW_FLAGS_NC, &fw_flags) ||
4730 			    test_bit(FW_FLAGS_NC1, &fw_flags) ||
4731 			    test_bit(FW_FLAGS_NC2, &fw_flags) ||
4732 			    test_bit(FW_FLAGS_UC2, &fw_flags) ||
4733 			    test_bit(FW_FLAGS_UC, &fw_flags) ||
4734 			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
4735 				dev_err(&tp->intf->dev, "Invalid order to set PHY version\n");
4736 				goto fail;
4737 			}
4738 
4739 			if (test_bit(FW_FLAGS_VER, &fw_flags)) {
4740 				dev_err(&tp->intf->dev, "multiple PHY version encountered");
4741 				goto fail;
4742 			}
4743 
4744 			if (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) {
4745 				dev_err(&tp->intf->dev, "check PHY version failed\n");
4746 				goto fail;
4747 			}
4748 			__set_bit(FW_FLAGS_VER, &fw_flags);
4749 			break;
4750 		default:
4751 			dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
4752 				 type);
4753 			break;
4754 		}
4755 
4756 		/* next block */
4757 		i += ALIGN(__le32_to_cpu(block->length), 8);
4758 	}
4759 
4760 fw_end:
4761 	if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) {
4762 		dev_err(&tp->intf->dev, "without PHY_STOP\n");
4763 		goto fail;
4764 	}
4765 
4766 	return 0;
4767 fail:
4768 	return ret;
4769 }
4770 
4771 static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)
4772 {
4773 	u32 len;
4774 	u8 *data;
4775 
4776 	if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) {
4777 		dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4778 		return;
4779 	}
4780 
4781 	len = __le32_to_cpu(phy->blk_hdr.length);
4782 	len -= __le16_to_cpu(phy->fw_offset);
4783 	data = (u8 *)phy + __le16_to_cpu(phy->fw_offset);
4784 
4785 	if (rtl_phy_patch_request(tp, true, wait))
4786 		return;
4787 
4788 	while (len) {
4789 		u32 ocp_data, size;
4790 		int i;
4791 
4792 		if (len < 2048)
4793 			size = len;
4794 		else
4795 			size = 2048;
4796 
4797 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);
4798 		ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;
4799 		ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data);
4800 
4801 		generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB);
4802 
4803 		data += size;
4804 		len -= size;
4805 
4806 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);
4807 		ocp_data |= POL_GPHY_PATCH;
4808 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data);
4809 
4810 		for (i = 0; i < 1000; i++) {
4811 			if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))
4812 				break;
4813 		}
4814 
4815 		if (i == 1000) {
4816 			dev_err(&tp->intf->dev, "ram code speedup mode timeout\n");
4817 			break;
4818 		}
4819 	}
4820 
4821 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
4822 	rtl_phy_patch_request(tp, false, wait);
4823 
4824 	if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version))
4825 		dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4826 	else
4827 		dev_err(&tp->intf->dev, "ram code speedup mode fail\n");
4828 }
4829 
4830 static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver)
4831 {
4832 	u16 ver_addr, ver;
4833 
4834 	ver_addr = __le16_to_cpu(phy_ver->ver.addr);
4835 	ver = __le16_to_cpu(phy_ver->ver.data);
4836 
4837 	if (sram_read(tp, ver_addr) >= ver) {
4838 		dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4839 		return 0;
4840 	}
4841 
4842 	sram_write(tp, ver_addr, ver);
4843 
4844 	dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver);
4845 
4846 	return ver;
4847 }
4848 
4849 static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix)
4850 {
4851 	u16 addr, data;
4852 
4853 	addr = __le16_to_cpu(fix->setting.addr);
4854 	data = ocp_reg_read(tp, addr);
4855 
4856 	switch (__le16_to_cpu(fix->bit_cmd)) {
4857 	case FW_FIXUP_AND:
4858 		data &= __le16_to_cpu(fix->setting.data);
4859 		break;
4860 	case FW_FIXUP_OR:
4861 		data |= __le16_to_cpu(fix->setting.data);
4862 		break;
4863 	case FW_FIXUP_NOT:
4864 		data &= ~__le16_to_cpu(fix->setting.data);
4865 		break;
4866 	case FW_FIXUP_XOR:
4867 		data ^= __le16_to_cpu(fix->setting.data);
4868 		break;
4869 	default:
4870 		return;
4871 	}
4872 
4873 	ocp_reg_write(tp, addr, data);
4874 
4875 	dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data);
4876 }
4877 
4878 static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy)
4879 {
4880 	__le16 *data;
4881 	u32 length;
4882 	int i, num;
4883 
4884 	num = phy->pre_num;
4885 	for (i = 0; i < num; i++)
4886 		sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr),
4887 			   __le16_to_cpu(phy->pre_set[i].data));
4888 
4889 	length = __le32_to_cpu(phy->blk_hdr.length);
4890 	length -= __le16_to_cpu(phy->fw_offset);
4891 	num = length / 2;
4892 	data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
4893 
4894 	ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
4895 	for (i = 0; i < num; i++)
4896 		ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
4897 
4898 	num = phy->bp_num;
4899 	for (i = 0; i < num; i++)
4900 		sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data));
4901 
4902 	if (phy->bp_num && phy->bp_en.addr)
4903 		sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data));
4904 
4905 	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4906 }
4907 
4908 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
4909 {
4910 	u16 mode_reg, bp_index;
4911 	u32 length, i, num;
4912 	__le16 *data;
4913 
4914 	mode_reg = __le16_to_cpu(phy->mode_reg);
4915 	sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
4916 	sram_write(tp, __le16_to_cpu(phy->ba_reg),
4917 		   __le16_to_cpu(phy->ba_data));
4918 
4919 	length = __le32_to_cpu(phy->blk_hdr.length);
4920 	length -= __le16_to_cpu(phy->fw_offset);
4921 	num = length / 2;
4922 	data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
4923 
4924 	ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
4925 	for (i = 0; i < num; i++)
4926 		ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
4927 
4928 	sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
4929 		   __le16_to_cpu(phy->patch_en_value));
4930 
4931 	bp_index = __le16_to_cpu(phy->bp_start);
4932 	num = __le16_to_cpu(phy->bp_num);
4933 	for (i = 0; i < num; i++) {
4934 		sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
4935 		bp_index += 2;
4936 	}
4937 
4938 	sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
4939 
4940 	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4941 }
4942 
4943 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
4944 {
4945 	u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
4946 	u32 length;
4947 	u8 *data;
4948 	int i;
4949 
4950 	switch (__le32_to_cpu(mac->blk_hdr.type)) {
4951 	case RTL_FW_PLA:
4952 		type = MCU_TYPE_PLA;
4953 		break;
4954 	case RTL_FW_USB:
4955 		type = MCU_TYPE_USB;
4956 		break;
4957 	default:
4958 		return;
4959 	}
4960 
4961 	fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
4962 	if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) {
4963 		dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB");
4964 		return;
4965 	}
4966 
4967 	rtl_clear_bp(tp, type);
4968 
4969 	/* Enable backup/restore of MACDBG. This is required after clearing PLA
4970 	 * break points and before applying the PLA firmware.
4971 	 */
4972 	if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
4973 	    !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
4974 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
4975 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
4976 	}
4977 
4978 	length = __le32_to_cpu(mac->blk_hdr.length);
4979 	length -= __le16_to_cpu(mac->fw_offset);
4980 
4981 	data = (u8 *)mac;
4982 	data += __le16_to_cpu(mac->fw_offset);
4983 
4984 	generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
4985 			  type);
4986 
4987 	ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
4988 		       __le16_to_cpu(mac->bp_ba_value));
4989 
4990 	bp_index = __le16_to_cpu(mac->bp_start);
4991 	bp_num = __le16_to_cpu(mac->bp_num);
4992 	for (i = 0; i < bp_num; i++) {
4993 		ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
4994 		bp_index += 2;
4995 	}
4996 
4997 	bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
4998 	if (bp_en_addr)
4999 		ocp_write_word(tp, type, bp_en_addr,
5000 			       __le16_to_cpu(mac->bp_en_value));
5001 
5002 	if (fw_ver_reg)
5003 		ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
5004 			       mac->fw_ver_data);
5005 
5006 	dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
5007 }
5008 
5009 static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)
5010 {
5011 	struct rtl_fw *rtl_fw = &tp->rtl_fw;
5012 	const struct firmware *fw;
5013 	struct fw_header *fw_hdr;
5014 	struct fw_phy_patch_key *key;
5015 	u16 key_addr = 0;
5016 	int i, patch_phy = 1;
5017 
5018 	if (IS_ERR_OR_NULL(rtl_fw->fw))
5019 		return;
5020 
5021 	fw = rtl_fw->fw;
5022 	fw_hdr = (struct fw_header *)fw->data;
5023 
5024 	if (rtl_fw->pre_fw)
5025 		rtl_fw->pre_fw(tp);
5026 
5027 	for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
5028 		struct fw_block *block = (struct fw_block *)&fw->data[i];
5029 
5030 		switch (__le32_to_cpu(block->type)) {
5031 		case RTL_FW_END:
5032 			goto post_fw;
5033 		case RTL_FW_PLA:
5034 		case RTL_FW_USB:
5035 			rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
5036 			break;
5037 		case RTL_FW_PHY_START:
5038 			if (!patch_phy)
5039 				break;
5040 			key = (struct fw_phy_patch_key *)block;
5041 			key_addr = __le16_to_cpu(key->key_reg);
5042 			rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut);
5043 			break;
5044 		case RTL_FW_PHY_STOP:
5045 			if (!patch_phy)
5046 				break;
5047 			WARN_ON(!key_addr);
5048 			rtl_post_ram_code(tp, key_addr, !power_cut);
5049 			break;
5050 		case RTL_FW_PHY_NC:
5051 			rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
5052 			break;
5053 		case RTL_FW_PHY_VER:
5054 			patch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block);
5055 			break;
5056 		case RTL_FW_PHY_UNION_NC:
5057 		case RTL_FW_PHY_UNION_NC1:
5058 		case RTL_FW_PHY_UNION_NC2:
5059 		case RTL_FW_PHY_UNION_UC2:
5060 		case RTL_FW_PHY_UNION_UC:
5061 		case RTL_FW_PHY_UNION_MISC:
5062 			if (patch_phy)
5063 				rtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block);
5064 			break;
5065 		case RTL_FW_PHY_FIXUP:
5066 			if (patch_phy)
5067 				rtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block);
5068 			break;
5069 		case RTL_FW_PHY_SPEED_UP:
5070 			rtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut);
5071 			break;
5072 		default:
5073 			break;
5074 		}
5075 
5076 		i += ALIGN(__le32_to_cpu(block->length), 8);
5077 	}
5078 
5079 post_fw:
5080 	if (rtl_fw->post_fw)
5081 		rtl_fw->post_fw(tp);
5082 
5083 	strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
5084 	dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
5085 }
5086 
5087 static void rtl8152_release_firmware(struct r8152 *tp)
5088 {
5089 	struct rtl_fw *rtl_fw = &tp->rtl_fw;
5090 
5091 	if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
5092 		release_firmware(rtl_fw->fw);
5093 		rtl_fw->fw = NULL;
5094 	}
5095 }
5096 
5097 static int rtl8152_request_firmware(struct r8152 *tp)
5098 {
5099 	struct rtl_fw *rtl_fw = &tp->rtl_fw;
5100 	long rc;
5101 
5102 	if (rtl_fw->fw || !rtl_fw->fw_name) {
5103 		dev_info(&tp->intf->dev, "skip request firmware\n");
5104 		rc = 0;
5105 		goto result;
5106 	}
5107 
5108 	rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
5109 	if (rc < 0)
5110 		goto result;
5111 
5112 	rc = rtl8152_check_firmware(tp, rtl_fw);
5113 	if (rc < 0)
5114 		release_firmware(rtl_fw->fw);
5115 
5116 result:
5117 	if (rc) {
5118 		rtl_fw->fw = ERR_PTR(rc);
5119 
5120 		dev_warn(&tp->intf->dev,
5121 			 "unable to load firmware patch %s (%ld)\n",
5122 			 rtl_fw->fw_name, rc);
5123 	}
5124 
5125 	return rc;
5126 }
5127 
5128 static void r8152_aldps_en(struct r8152 *tp, bool enable)
5129 {
5130 	if (enable) {
5131 		ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
5132 						    LINKENA | DIS_SDSAVE);
5133 	} else {
5134 		ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
5135 						    DIS_SDSAVE);
5136 		msleep(20);
5137 	}
5138 }
5139 
5140 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
5141 {
5142 	ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
5143 	ocp_reg_write(tp, OCP_EEE_DATA, reg);
5144 	ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
5145 }
5146 
5147 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
5148 {
5149 	u16 data;
5150 
5151 	r8152_mmd_indirect(tp, dev, reg);
5152 	data = ocp_reg_read(tp, OCP_EEE_DATA);
5153 	ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5154 
5155 	return data;
5156 }
5157 
5158 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
5159 {
5160 	r8152_mmd_indirect(tp, dev, reg);
5161 	ocp_reg_write(tp, OCP_EEE_DATA, data);
5162 	ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5163 }
5164 
5165 static void r8152_eee_en(struct r8152 *tp, bool enable)
5166 {
5167 	u16 config1, config2, config3;
5168 	u32 ocp_data;
5169 
5170 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5171 	config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
5172 	config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
5173 	config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
5174 
5175 	if (enable) {
5176 		ocp_data |= EEE_RX_EN | EEE_TX_EN;
5177 		config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
5178 		config1 |= sd_rise_time(1);
5179 		config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
5180 		config3 |= fast_snr(42);
5181 	} else {
5182 		ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5183 		config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
5184 			     RX_QUIET_EN);
5185 		config1 |= sd_rise_time(7);
5186 		config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
5187 		config3 |= fast_snr(511);
5188 	}
5189 
5190 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5191 	ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
5192 	ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
5193 	ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
5194 }
5195 
5196 static void r8153_eee_en(struct r8152 *tp, bool enable)
5197 {
5198 	u32 ocp_data;
5199 	u16 config;
5200 
5201 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5202 	config = ocp_reg_read(tp, OCP_EEE_CFG);
5203 
5204 	if (enable) {
5205 		ocp_data |= EEE_RX_EN | EEE_TX_EN;
5206 		config |= EEE10_EN;
5207 	} else {
5208 		ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5209 		config &= ~EEE10_EN;
5210 	}
5211 
5212 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5213 	ocp_reg_write(tp, OCP_EEE_CFG, config);
5214 
5215 	tp->ups_info.eee = enable;
5216 }
5217 
5218 static void r8156_eee_en(struct r8152 *tp, bool enable)
5219 {
5220 	u16 config;
5221 
5222 	r8153_eee_en(tp, enable);
5223 
5224 	config = ocp_reg_read(tp, OCP_EEE_ADV2);
5225 
5226 	if (enable)
5227 		config |= MDIO_EEE_2_5GT;
5228 	else
5229 		config &= ~MDIO_EEE_2_5GT;
5230 
5231 	ocp_reg_write(tp, OCP_EEE_ADV2, config);
5232 }
5233 
5234 static void rtl_eee_enable(struct r8152 *tp, bool enable)
5235 {
5236 	switch (tp->version) {
5237 	case RTL_VER_01:
5238 	case RTL_VER_02:
5239 	case RTL_VER_07:
5240 		if (enable) {
5241 			r8152_eee_en(tp, true);
5242 			r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
5243 					tp->eee_adv);
5244 		} else {
5245 			r8152_eee_en(tp, false);
5246 			r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
5247 		}
5248 		break;
5249 	case RTL_VER_03:
5250 	case RTL_VER_04:
5251 	case RTL_VER_05:
5252 	case RTL_VER_06:
5253 	case RTL_VER_08:
5254 	case RTL_VER_09:
5255 	case RTL_VER_14:
5256 		if (enable) {
5257 			r8153_eee_en(tp, true);
5258 			ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5259 		} else {
5260 			r8153_eee_en(tp, false);
5261 			ocp_reg_write(tp, OCP_EEE_ADV, 0);
5262 		}
5263 		break;
5264 	case RTL_VER_10:
5265 	case RTL_VER_11:
5266 	case RTL_VER_12:
5267 	case RTL_VER_13:
5268 	case RTL_VER_15:
5269 		if (enable) {
5270 			r8156_eee_en(tp, true);
5271 			ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5272 		} else {
5273 			r8156_eee_en(tp, false);
5274 			ocp_reg_write(tp, OCP_EEE_ADV, 0);
5275 		}
5276 		break;
5277 	default:
5278 		break;
5279 	}
5280 }
5281 
5282 static void r8152b_enable_fc(struct r8152 *tp)
5283 {
5284 	u16 anar;
5285 
5286 	anar = r8152_mdio_read(tp, MII_ADVERTISE);
5287 	anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
5288 	r8152_mdio_write(tp, MII_ADVERTISE, anar);
5289 
5290 	tp->ups_info.flow_control = true;
5291 }
5292 
5293 static void rtl8152_disable(struct r8152 *tp)
5294 {
5295 	r8152_aldps_en(tp, false);
5296 	rtl_disable(tp);
5297 	r8152_aldps_en(tp, true);
5298 }
5299 
5300 static void r8152b_hw_phy_cfg(struct r8152 *tp)
5301 {
5302 	rtl8152_apply_firmware(tp, false);
5303 	rtl_eee_enable(tp, tp->eee_en);
5304 	r8152_aldps_en(tp, true);
5305 	r8152b_enable_fc(tp);
5306 
5307 	set_bit(PHY_RESET, &tp->flags);
5308 }
5309 
5310 static void wait_oob_link_list_ready(struct r8152 *tp)
5311 {
5312 	u32 ocp_data;
5313 	int i;
5314 
5315 	for (i = 0; i < 1000; i++) {
5316 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5317 		if (ocp_data & LINK_LIST_READY)
5318 			break;
5319 		usleep_range(1000, 2000);
5320 	}
5321 }
5322 
5323 static void r8156b_wait_loading_flash(struct r8152 *tp)
5324 {
5325 	if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&
5326 	    !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {
5327 		int i;
5328 
5329 		for (i = 0; i < 100; i++) {
5330 			if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)
5331 				break;
5332 			usleep_range(1000, 2000);
5333 		}
5334 	}
5335 }
5336 
5337 static void r8152b_exit_oob(struct r8152 *tp)
5338 {
5339 	u32 ocp_data;
5340 
5341 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5342 	ocp_data &= ~RCR_ACPT_ALL;
5343 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5344 
5345 	rxdy_gated_en(tp, true);
5346 	r8153_teredo_off(tp);
5347 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
5348 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
5349 
5350 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5351 	ocp_data &= ~NOW_IS_OOB;
5352 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5353 
5354 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5355 	ocp_data &= ~MCU_BORW_EN;
5356 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5357 
5358 	wait_oob_link_list_ready(tp);
5359 
5360 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5361 	ocp_data |= RE_INIT_LL;
5362 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5363 
5364 	wait_oob_link_list_ready(tp);
5365 
5366 	rtl8152_nic_reset(tp);
5367 
5368 	/* rx share fifo credit full threshold */
5369 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5370 
5371 	if (tp->udev->speed == USB_SPEED_FULL ||
5372 	    tp->udev->speed == USB_SPEED_LOW) {
5373 		/* rx share fifo credit near full threshold */
5374 		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5375 				RXFIFO_THR2_FULL);
5376 		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5377 				RXFIFO_THR3_FULL);
5378 	} else {
5379 		/* rx share fifo credit near full threshold */
5380 		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5381 				RXFIFO_THR2_HIGH);
5382 		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5383 				RXFIFO_THR3_HIGH);
5384 	}
5385 
5386 	/* TX share fifo free credit full threshold */
5387 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5388 
5389 	ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
5390 	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
5391 	ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
5392 			TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
5393 
5394 	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5395 
5396 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5397 
5398 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5399 	ocp_data |= TCR0_AUTO_FIFO;
5400 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5401 }
5402 
5403 static void r8152b_enter_oob(struct r8152 *tp)
5404 {
5405 	u32 ocp_data;
5406 
5407 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5408 	ocp_data &= ~NOW_IS_OOB;
5409 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5410 
5411 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
5412 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
5413 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
5414 
5415 	rtl_disable(tp);
5416 
5417 	wait_oob_link_list_ready(tp);
5418 
5419 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5420 	ocp_data |= RE_INIT_LL;
5421 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5422 
5423 	wait_oob_link_list_ready(tp);
5424 
5425 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5426 
5427 	rtl_rx_vlan_en(tp, true);
5428 
5429 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5430 	ocp_data |= ALDPS_PROXY_MODE;
5431 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
5432 
5433 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5434 	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5435 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5436 
5437 	rxdy_gated_en(tp, false);
5438 
5439 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5440 	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5441 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5442 }
5443 
5444 static int r8153_pre_firmware_1(struct r8152 *tp)
5445 {
5446 	int i;
5447 
5448 	/* Wait till the WTD timer is ready. It would take at most 104 ms. */
5449 	for (i = 0; i < 104; i++) {
5450 		u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
5451 
5452 		if (!(ocp_data & WTD1_EN))
5453 			break;
5454 		usleep_range(1000, 2000);
5455 	}
5456 
5457 	return 0;
5458 }
5459 
5460 static int r8153_post_firmware_1(struct r8152 *tp)
5461 {
5462 	/* set USB_BP_4 to support USB_SPEED_SUPER only */
5463 	if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
5464 		ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
5465 
5466 	/* reset UPHY timer to 36 ms */
5467 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5468 
5469 	return 0;
5470 }
5471 
5472 static int r8153_pre_firmware_2(struct r8152 *tp)
5473 {
5474 	u32 ocp_data;
5475 
5476 	r8153_pre_firmware_1(tp);
5477 
5478 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5479 	ocp_data &= ~FW_FIX_SUSPEND;
5480 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5481 
5482 	return 0;
5483 }
5484 
5485 static int r8153_post_firmware_2(struct r8152 *tp)
5486 {
5487 	u32 ocp_data;
5488 
5489 	/* enable bp0 if support USB_SPEED_SUPER only */
5490 	if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
5491 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5492 		ocp_data |= BIT(0);
5493 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5494 	}
5495 
5496 	/* reset UPHY timer to 36 ms */
5497 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5498 
5499 	/* enable U3P3 check, set the counter to 4 */
5500 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
5501 
5502 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5503 	ocp_data |= FW_FIX_SUSPEND;
5504 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5505 
5506 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5507 	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5508 	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5509 
5510 	return 0;
5511 }
5512 
5513 static int r8153_post_firmware_3(struct r8152 *tp)
5514 {
5515 	u32 ocp_data;
5516 
5517 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5518 	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5519 	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5520 
5521 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5522 	ocp_data |= FW_IP_RESET_EN;
5523 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5524 
5525 	return 0;
5526 }
5527 
5528 static int r8153b_pre_firmware_1(struct r8152 *tp)
5529 {
5530 	/* enable fc timer and set timer to 1 second. */
5531 	ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
5532 		       CTRL_TIMER_EN | (1000 / 8));
5533 
5534 	return 0;
5535 }
5536 
5537 static int r8153b_post_firmware_1(struct r8152 *tp)
5538 {
5539 	u32 ocp_data;
5540 
5541 	/* enable bp0 for RTL8153-BND */
5542 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
5543 	if (ocp_data & BND_MASK) {
5544 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5545 		ocp_data |= BIT(0);
5546 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5547 	}
5548 
5549 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5550 	ocp_data |= FLOW_CTRL_PATCH_OPT;
5551 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5552 
5553 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5554 	ocp_data |= FC_PATCH_TASK;
5555 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5556 
5557 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5558 	ocp_data |= FW_IP_RESET_EN;
5559 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5560 
5561 	return 0;
5562 }
5563 
5564 static int r8153c_post_firmware_1(struct r8152 *tp)
5565 {
5566 	u32 ocp_data;
5567 
5568 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5569 	ocp_data |= FLOW_CTRL_PATCH_2;
5570 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5571 
5572 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5573 	ocp_data |= FC_PATCH_TASK;
5574 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5575 
5576 	return 0;
5577 }
5578 
5579 static int r8156a_post_firmware_1(struct r8152 *tp)
5580 {
5581 	u32 ocp_data;
5582 
5583 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5584 	ocp_data |= FW_IP_RESET_EN;
5585 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5586 
5587 	/* Modify U3PHY parameter for compatibility issue */
5588 	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e);
5589 	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9);
5590 
5591 	return 0;
5592 }
5593 
5594 static void r8153_aldps_en(struct r8152 *tp, bool enable)
5595 {
5596 	u16 data;
5597 
5598 	data = ocp_reg_read(tp, OCP_POWER_CFG);
5599 	if (enable) {
5600 		data |= EN_ALDPS;
5601 		ocp_reg_write(tp, OCP_POWER_CFG, data);
5602 	} else {
5603 		int i;
5604 
5605 		data &= ~EN_ALDPS;
5606 		ocp_reg_write(tp, OCP_POWER_CFG, data);
5607 		for (i = 0; i < 20; i++) {
5608 			usleep_range(1000, 2000);
5609 			if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
5610 				break;
5611 		}
5612 	}
5613 
5614 	tp->ups_info.aldps = enable;
5615 }
5616 
5617 static void r8153_hw_phy_cfg(struct r8152 *tp)
5618 {
5619 	u32 ocp_data;
5620 	u16 data;
5621 
5622 	/* disable ALDPS before updating the PHY parameters */
5623 	r8153_aldps_en(tp, false);
5624 
5625 	/* disable EEE before updating the PHY parameters */
5626 	rtl_eee_enable(tp, false);
5627 
5628 	rtl8152_apply_firmware(tp, false);
5629 
5630 	if (tp->version == RTL_VER_03) {
5631 		data = ocp_reg_read(tp, OCP_EEE_CFG);
5632 		data &= ~CTAP_SHORT_EN;
5633 		ocp_reg_write(tp, OCP_EEE_CFG, data);
5634 	}
5635 
5636 	data = ocp_reg_read(tp, OCP_POWER_CFG);
5637 	data |= EEE_CLKDIV_EN;
5638 	ocp_reg_write(tp, OCP_POWER_CFG, data);
5639 
5640 	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5641 	data |= EN_10M_BGOFF;
5642 	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5643 	data = ocp_reg_read(tp, OCP_POWER_CFG);
5644 	data |= EN_10M_PLLOFF;
5645 	ocp_reg_write(tp, OCP_POWER_CFG, data);
5646 	sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
5647 
5648 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5649 	ocp_data |= PFM_PWM_SWITCH;
5650 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5651 
5652 	/* Enable LPF corner auto tune */
5653 	sram_write(tp, SRAM_LPF_CFG, 0xf70f);
5654 
5655 	/* Adjust 10M Amplitude */
5656 	sram_write(tp, SRAM_10M_AMP1, 0x00af);
5657 	sram_write(tp, SRAM_10M_AMP2, 0x0208);
5658 
5659 	if (tp->eee_en)
5660 		rtl_eee_enable(tp, true);
5661 
5662 	r8153_aldps_en(tp, true);
5663 	r8152b_enable_fc(tp);
5664 
5665 	switch (tp->version) {
5666 	case RTL_VER_03:
5667 	case RTL_VER_04:
5668 		break;
5669 	case RTL_VER_05:
5670 	case RTL_VER_06:
5671 	default:
5672 		r8153_u2p3en(tp, true);
5673 		break;
5674 	}
5675 
5676 	set_bit(PHY_RESET, &tp->flags);
5677 }
5678 
5679 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
5680 {
5681 	u32 ocp_data;
5682 
5683 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
5684 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
5685 	ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;	/* data of bit16 */
5686 	ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
5687 
5688 	return ocp_data;
5689 }
5690 
5691 static void r8153b_hw_phy_cfg(struct r8152 *tp)
5692 {
5693 	u32 ocp_data;
5694 	u16 data;
5695 
5696 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
5697 	if (ocp_data & PCUT_STATUS) {
5698 		ocp_data &= ~PCUT_STATUS;
5699 		ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
5700 	}
5701 
5702 	/* disable ALDPS before updating the PHY parameters */
5703 	r8153_aldps_en(tp, false);
5704 
5705 	/* disable EEE before updating the PHY parameters */
5706 	rtl_eee_enable(tp, false);
5707 
5708 	/* U1/U2/L1 idle timer. 500 us */
5709 	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5710 
5711 	data = r8153_phy_status(tp, 0);
5712 
5713 	switch (data) {
5714 	case PHY_STAT_PWRDN:
5715 	case PHY_STAT_EXT_INIT:
5716 		rtl8152_apply_firmware(tp, true);
5717 
5718 		data = r8152_mdio_read(tp, MII_BMCR);
5719 		data &= ~BMCR_PDOWN;
5720 		r8152_mdio_write(tp, MII_BMCR, data);
5721 		break;
5722 	case PHY_STAT_LAN_ON:
5723 	default:
5724 		rtl8152_apply_firmware(tp, false);
5725 		break;
5726 	}
5727 
5728 	r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
5729 
5730 	data = sram_read(tp, SRAM_GREEN_CFG);
5731 	data |= R_TUNE_EN;
5732 	sram_write(tp, SRAM_GREEN_CFG, data);
5733 	data = ocp_reg_read(tp, OCP_NCTL_CFG);
5734 	data |= PGA_RETURN_EN;
5735 	ocp_reg_write(tp, OCP_NCTL_CFG, data);
5736 
5737 	/* ADC Bias Calibration:
5738 	 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
5739 	 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
5740 	 * ADC ioffset.
5741 	 */
5742 	ocp_data = r8152_efuse_read(tp, 0x7d);
5743 	data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
5744 	if (data != 0xffff)
5745 		ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
5746 
5747 	/* ups mode tx-link-pulse timing adjustment:
5748 	 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
5749 	 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
5750 	 */
5751 	ocp_data = ocp_reg_read(tp, 0xc426);
5752 	ocp_data &= 0x3fff;
5753 	if (ocp_data) {
5754 		u32 swr_cnt_1ms_ini;
5755 
5756 		swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
5757 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
5758 		ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
5759 		ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
5760 	}
5761 
5762 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5763 	ocp_data |= PFM_PWM_SWITCH;
5764 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5765 
5766 	/* Advnace EEE */
5767 	if (!rtl_phy_patch_request(tp, true, true)) {
5768 		data = ocp_reg_read(tp, OCP_POWER_CFG);
5769 		data |= EEE_CLKDIV_EN;
5770 		ocp_reg_write(tp, OCP_POWER_CFG, data);
5771 		tp->ups_info.eee_ckdiv = true;
5772 
5773 		data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5774 		data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
5775 		ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5776 		tp->ups_info.eee_cmod_lv = true;
5777 		tp->ups_info._10m_ckdiv = true;
5778 		tp->ups_info.eee_plloff_giga = true;
5779 
5780 		ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
5781 		ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
5782 		tp->ups_info._250m_ckdiv = true;
5783 
5784 		rtl_phy_patch_request(tp, false, true);
5785 	}
5786 
5787 	if (tp->eee_en)
5788 		rtl_eee_enable(tp, true);
5789 
5790 	r8153_aldps_en(tp, true);
5791 	r8152b_enable_fc(tp);
5792 
5793 	set_bit(PHY_RESET, &tp->flags);
5794 }
5795 
5796 static void r8153c_hw_phy_cfg(struct r8152 *tp)
5797 {
5798 	r8153b_hw_phy_cfg(tp);
5799 
5800 	tp->ups_info.r_tune = true;
5801 }
5802 
5803 static void rtl8153_change_mtu(struct r8152 *tp)
5804 {
5805 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
5806 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
5807 }
5808 
5809 static void r8153_first_init(struct r8152 *tp)
5810 {
5811 	u32 ocp_data;
5812 
5813 	rxdy_gated_en(tp, true);
5814 	r8153_teredo_off(tp);
5815 
5816 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5817 	ocp_data &= ~RCR_ACPT_ALL;
5818 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5819 
5820 	rtl8152_nic_reset(tp);
5821 	rtl_reset_bmu(tp);
5822 
5823 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5824 	ocp_data &= ~NOW_IS_OOB;
5825 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5826 
5827 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5828 	ocp_data &= ~MCU_BORW_EN;
5829 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5830 
5831 	wait_oob_link_list_ready(tp);
5832 
5833 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5834 	ocp_data |= RE_INIT_LL;
5835 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5836 
5837 	wait_oob_link_list_ready(tp);
5838 
5839 	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5840 
5841 	rtl8153_change_mtu(tp);
5842 
5843 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5844 	ocp_data |= TCR0_AUTO_FIFO;
5845 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5846 
5847 	rtl8152_nic_reset(tp);
5848 
5849 	/* rx share fifo credit full threshold */
5850 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5851 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
5852 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
5853 	/* TX share fifo free credit full threshold */
5854 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5855 }
5856 
5857 static void r8153_enter_oob(struct r8152 *tp)
5858 {
5859 	u32 ocp_data;
5860 
5861 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5862 	ocp_data &= ~NOW_IS_OOB;
5863 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5864 
5865 	rtl_disable(tp);
5866 	rtl_reset_bmu(tp);
5867 
5868 	wait_oob_link_list_ready(tp);
5869 
5870 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5871 	ocp_data |= RE_INIT_LL;
5872 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5873 
5874 	wait_oob_link_list_ready(tp);
5875 
5876 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
5877 
5878 	switch (tp->version) {
5879 	case RTL_VER_03:
5880 	case RTL_VER_04:
5881 	case RTL_VER_05:
5882 	case RTL_VER_06:
5883 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
5884 		ocp_data &= ~TEREDO_WAKE_MASK;
5885 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
5886 		break;
5887 
5888 	case RTL_VER_08:
5889 	case RTL_VER_09:
5890 	case RTL_VER_14:
5891 		/* Clear teredo wake event. bit[15:8] is the teredo wakeup
5892 		 * type. Set it to zero. bits[7:0] are the W1C bits about
5893 		 * the events. Set them to all 1 to clear them.
5894 		 */
5895 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
5896 		break;
5897 
5898 	default:
5899 		break;
5900 	}
5901 
5902 	rtl_rx_vlan_en(tp, true);
5903 
5904 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5905 	ocp_data |= ALDPS_PROXY_MODE;
5906 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
5907 
5908 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5909 	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5910 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5911 
5912 	rxdy_gated_en(tp, false);
5913 
5914 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5915 	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5916 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5917 }
5918 
5919 static void rtl8153_disable(struct r8152 *tp)
5920 {
5921 	r8153_aldps_en(tp, false);
5922 	rtl_disable(tp);
5923 	rtl_reset_bmu(tp);
5924 	r8153_aldps_en(tp, true);
5925 }
5926 
5927 static int rtl8156_enable(struct r8152 *tp)
5928 {
5929 	u32 ocp_data;
5930 	u16 speed;
5931 
5932 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
5933 		return -ENODEV;
5934 
5935 	set_tx_qlen(tp);
5936 	rtl_set_eee_plus(tp);
5937 	r8153_set_rx_early_timeout(tp);
5938 	r8153_set_rx_early_size(tp);
5939 
5940 	speed = rtl8152_get_speed(tp);
5941 	rtl_set_ifg(tp, speed);
5942 
5943 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
5944 	if (speed & _2500bps)
5945 		ocp_data &= ~IDLE_SPDWN_EN;
5946 	else
5947 		ocp_data |= IDLE_SPDWN_EN;
5948 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
5949 
5950 	if (speed & _1000bps)
5951 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11);
5952 	else if (speed & _500bps)
5953 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d);
5954 
5955 	if (tp->udev->speed == USB_SPEED_HIGH) {
5956 		/* USB 0xb45e[3:0] l1_nyet_hird */
5957 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
5958 		ocp_data &= ~0xf;
5959 		if (is_flow_control(speed))
5960 			ocp_data |= 0xf;
5961 		else
5962 			ocp_data |= 0x1;
5963 		ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
5964 	}
5965 
5966 	return rtl_enable(tp);
5967 }
5968 
5969 static int rtl8156b_enable(struct r8152 *tp)
5970 {
5971 	u32 ocp_data;
5972 	u16 speed;
5973 
5974 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
5975 		return -ENODEV;
5976 
5977 	set_tx_qlen(tp);
5978 	rtl_set_eee_plus(tp);
5979 
5980 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);
5981 	ocp_data &= ~RX_AGGR_NUM_MASK;
5982 	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data);
5983 
5984 	r8153_set_rx_early_timeout(tp);
5985 	r8153_set_rx_early_size(tp);
5986 
5987 	speed = rtl8152_get_speed(tp);
5988 	rtl_set_ifg(tp, speed);
5989 
5990 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
5991 	if (speed & _2500bps)
5992 		ocp_data &= ~IDLE_SPDWN_EN;
5993 	else
5994 		ocp_data |= IDLE_SPDWN_EN;
5995 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
5996 
5997 	if (tp->udev->speed == USB_SPEED_HIGH) {
5998 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
5999 		ocp_data &= ~0xf;
6000 		if (is_flow_control(speed))
6001 			ocp_data |= 0xf;
6002 		else
6003 			ocp_data |= 0x1;
6004 		ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
6005 	}
6006 
6007 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6008 	ocp_data &= ~FC_PATCH_TASK;
6009 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6010 	usleep_range(1000, 2000);
6011 	ocp_data |= FC_PATCH_TASK;
6012 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6013 
6014 	return rtl_enable(tp);
6015 }
6016 
6017 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
6018 			     u32 advertising)
6019 {
6020 	u16 bmcr;
6021 	int ret = 0;
6022 
6023 	if (autoneg == AUTONEG_DISABLE) {
6024 		if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
6025 			return -EINVAL;
6026 
6027 		switch (speed) {
6028 		case SPEED_10:
6029 			bmcr = BMCR_SPEED10;
6030 			if (duplex == DUPLEX_FULL) {
6031 				bmcr |= BMCR_FULLDPLX;
6032 				tp->ups_info.speed_duplex = FORCE_10M_FULL;
6033 			} else {
6034 				tp->ups_info.speed_duplex = FORCE_10M_HALF;
6035 			}
6036 			break;
6037 		case SPEED_100:
6038 			bmcr = BMCR_SPEED100;
6039 			if (duplex == DUPLEX_FULL) {
6040 				bmcr |= BMCR_FULLDPLX;
6041 				tp->ups_info.speed_duplex = FORCE_100M_FULL;
6042 			} else {
6043 				tp->ups_info.speed_duplex = FORCE_100M_HALF;
6044 			}
6045 			break;
6046 		case SPEED_1000:
6047 			if (tp->mii.supports_gmii) {
6048 				bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
6049 				tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6050 				break;
6051 			}
6052 			fallthrough;
6053 		default:
6054 			ret = -EINVAL;
6055 			goto out;
6056 		}
6057 
6058 		if (duplex == DUPLEX_FULL)
6059 			tp->mii.full_duplex = 1;
6060 		else
6061 			tp->mii.full_duplex = 0;
6062 
6063 		tp->mii.force_media = 1;
6064 	} else {
6065 		u16 orig, new1;
6066 		u32 support;
6067 
6068 		support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6069 			  RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6070 
6071 		if (tp->mii.supports_gmii) {
6072 			support |= RTL_ADVERTISED_1000_FULL;
6073 
6074 			if (tp->support_2500full)
6075 				support |= RTL_ADVERTISED_2500_FULL;
6076 		}
6077 
6078 		if (!(advertising & support))
6079 			return -EINVAL;
6080 
6081 		orig = r8152_mdio_read(tp, MII_ADVERTISE);
6082 		new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
6083 				ADVERTISE_100HALF | ADVERTISE_100FULL);
6084 		if (advertising & RTL_ADVERTISED_10_HALF) {
6085 			new1 |= ADVERTISE_10HALF;
6086 			tp->ups_info.speed_duplex = NWAY_10M_HALF;
6087 		}
6088 		if (advertising & RTL_ADVERTISED_10_FULL) {
6089 			new1 |= ADVERTISE_10FULL;
6090 			tp->ups_info.speed_duplex = NWAY_10M_FULL;
6091 		}
6092 
6093 		if (advertising & RTL_ADVERTISED_100_HALF) {
6094 			new1 |= ADVERTISE_100HALF;
6095 			tp->ups_info.speed_duplex = NWAY_100M_HALF;
6096 		}
6097 		if (advertising & RTL_ADVERTISED_100_FULL) {
6098 			new1 |= ADVERTISE_100FULL;
6099 			tp->ups_info.speed_duplex = NWAY_100M_FULL;
6100 		}
6101 
6102 		if (orig != new1) {
6103 			r8152_mdio_write(tp, MII_ADVERTISE, new1);
6104 			tp->mii.advertising = new1;
6105 		}
6106 
6107 		if (tp->mii.supports_gmii) {
6108 			orig = r8152_mdio_read(tp, MII_CTRL1000);
6109 			new1 = orig & ~(ADVERTISE_1000FULL |
6110 					ADVERTISE_1000HALF);
6111 
6112 			if (advertising & RTL_ADVERTISED_1000_FULL) {
6113 				new1 |= ADVERTISE_1000FULL;
6114 				tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6115 			}
6116 
6117 			if (orig != new1)
6118 				r8152_mdio_write(tp, MII_CTRL1000, new1);
6119 		}
6120 
6121 		if (tp->support_2500full) {
6122 			orig = ocp_reg_read(tp, OCP_10GBT_CTRL);
6123 			new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;
6124 
6125 			if (advertising & RTL_ADVERTISED_2500_FULL) {
6126 				new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;
6127 				tp->ups_info.speed_duplex = NWAY_2500M_FULL;
6128 			}
6129 
6130 			if (orig != new1)
6131 				ocp_reg_write(tp, OCP_10GBT_CTRL, new1);
6132 		}
6133 
6134 		bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
6135 
6136 		tp->mii.force_media = 0;
6137 	}
6138 
6139 	if (test_and_clear_bit(PHY_RESET, &tp->flags))
6140 		bmcr |= BMCR_RESET;
6141 
6142 	r8152_mdio_write(tp, MII_BMCR, bmcr);
6143 
6144 	if (bmcr & BMCR_RESET) {
6145 		int i;
6146 
6147 		for (i = 0; i < 50; i++) {
6148 			msleep(20);
6149 			if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
6150 				break;
6151 		}
6152 	}
6153 
6154 out:
6155 	return ret;
6156 }
6157 
6158 static void rtl8152_up(struct r8152 *tp)
6159 {
6160 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
6161 		return;
6162 
6163 	r8152_aldps_en(tp, false);
6164 	r8152b_exit_oob(tp);
6165 	r8152_aldps_en(tp, true);
6166 }
6167 
6168 static void rtl8152_down(struct r8152 *tp)
6169 {
6170 	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6171 		rtl_drop_queued_tx(tp);
6172 		return;
6173 	}
6174 
6175 	r8152_power_cut_en(tp, false);
6176 	r8152_aldps_en(tp, false);
6177 	r8152b_enter_oob(tp);
6178 	r8152_aldps_en(tp, true);
6179 }
6180 
6181 static void rtl8153_up(struct r8152 *tp)
6182 {
6183 	u32 ocp_data;
6184 
6185 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
6186 		return;
6187 
6188 	r8153_u1u2en(tp, false);
6189 	r8153_u2p3en(tp, false);
6190 	r8153_aldps_en(tp, false);
6191 	r8153_first_init(tp);
6192 
6193 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6194 	ocp_data |= LANWAKE_CLR_EN;
6195 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6196 
6197 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6198 	ocp_data &= ~LANWAKE_PIN;
6199 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
6200 
6201 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
6202 	ocp_data &= ~DELAY_PHY_PWR_CHG;
6203 	ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
6204 
6205 	r8153_aldps_en(tp, true);
6206 
6207 	switch (tp->version) {
6208 	case RTL_VER_03:
6209 	case RTL_VER_04:
6210 		break;
6211 	case RTL_VER_05:
6212 	case RTL_VER_06:
6213 	default:
6214 		r8153_u2p3en(tp, true);
6215 		break;
6216 	}
6217 
6218 	r8153_u1u2en(tp, true);
6219 }
6220 
6221 static void rtl8153_down(struct r8152 *tp)
6222 {
6223 	u32 ocp_data;
6224 
6225 	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6226 		rtl_drop_queued_tx(tp);
6227 		return;
6228 	}
6229 
6230 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6231 	ocp_data &= ~LANWAKE_CLR_EN;
6232 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6233 
6234 	r8153_u1u2en(tp, false);
6235 	r8153_u2p3en(tp, false);
6236 	r8153_power_cut_en(tp, false);
6237 	r8153_aldps_en(tp, false);
6238 	r8153_enter_oob(tp);
6239 	r8153_aldps_en(tp, true);
6240 }
6241 
6242 static void rtl8153b_up(struct r8152 *tp)
6243 {
6244 	u32 ocp_data;
6245 
6246 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
6247 		return;
6248 
6249 	r8153b_u1u2en(tp, false);
6250 	r8153_u2p3en(tp, false);
6251 	r8153_aldps_en(tp, false);
6252 
6253 	r8153_first_init(tp);
6254 	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6255 
6256 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6257 	ocp_data &= ~PLA_MCU_SPDWN_EN;
6258 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6259 
6260 	r8153_aldps_en(tp, true);
6261 
6262 	if (tp->udev->speed >= USB_SPEED_SUPER)
6263 		r8153b_u1u2en(tp, true);
6264 }
6265 
6266 static void rtl8153b_down(struct r8152 *tp)
6267 {
6268 	u32 ocp_data;
6269 
6270 	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6271 		rtl_drop_queued_tx(tp);
6272 		return;
6273 	}
6274 
6275 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6276 	ocp_data |= PLA_MCU_SPDWN_EN;
6277 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6278 
6279 	r8153b_u1u2en(tp, false);
6280 	r8153_u2p3en(tp, false);
6281 	r8153b_power_cut_en(tp, false);
6282 	r8153_aldps_en(tp, false);
6283 	r8153_enter_oob(tp);
6284 	r8153_aldps_en(tp, true);
6285 }
6286 
6287 static void rtl8153c_change_mtu(struct r8152 *tp)
6288 {
6289 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
6290 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64);
6291 
6292 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6293 
6294 	/* Adjust the tx fifo free credit full threshold, otherwise
6295 	 * the fifo would be too small to send a jumbo frame packet.
6296 	 */
6297 	if (tp->netdev->mtu < 8000)
6298 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8);
6299 	else
6300 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8);
6301 }
6302 
6303 static void rtl8153c_up(struct r8152 *tp)
6304 {
6305 	u32 ocp_data;
6306 
6307 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
6308 		return;
6309 
6310 	r8153b_u1u2en(tp, false);
6311 	r8153_u2p3en(tp, false);
6312 	r8153_aldps_en(tp, false);
6313 
6314 	rxdy_gated_en(tp, true);
6315 	r8153_teredo_off(tp);
6316 
6317 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6318 	ocp_data &= ~RCR_ACPT_ALL;
6319 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6320 
6321 	rtl8152_nic_reset(tp);
6322 	rtl_reset_bmu(tp);
6323 
6324 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6325 	ocp_data &= ~NOW_IS_OOB;
6326 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6327 
6328 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6329 	ocp_data &= ~MCU_BORW_EN;
6330 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6331 
6332 	wait_oob_link_list_ready(tp);
6333 
6334 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6335 	ocp_data |= RE_INIT_LL;
6336 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6337 
6338 	wait_oob_link_list_ready(tp);
6339 
6340 	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6341 
6342 	rtl8153c_change_mtu(tp);
6343 
6344 	rtl8152_nic_reset(tp);
6345 
6346 	/* rx share fifo credit full threshold */
6347 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02);
6348 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08);
6349 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
6350 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
6351 
6352 	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6353 
6354 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
6355 
6356 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
6357 	ocp_data |= BIT(8);
6358 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
6359 
6360 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
6361 
6362 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6363 	ocp_data &= ~PLA_MCU_SPDWN_EN;
6364 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6365 
6366 	r8153_aldps_en(tp, true);
6367 	r8153b_u1u2en(tp, true);
6368 }
6369 
6370 static inline u32 fc_pause_on_auto(struct r8152 *tp)
6371 {
6372 	return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);
6373 }
6374 
6375 static inline u32 fc_pause_off_auto(struct r8152 *tp)
6376 {
6377 	return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);
6378 }
6379 
6380 static void r8156_fc_parameter(struct r8152 *tp)
6381 {
6382 	u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);
6383 	u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);
6384 
6385 	switch (tp->version) {
6386 	case RTL_VER_10:
6387 	case RTL_VER_11:
6388 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 8);
6389 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 8);
6390 		break;
6391 	case RTL_VER_12:
6392 	case RTL_VER_13:
6393 	case RTL_VER_15:
6394 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16);
6395 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16);
6396 		break;
6397 	default:
6398 		break;
6399 	}
6400 }
6401 
6402 static void rtl8156_change_mtu(struct r8152 *tp)
6403 {
6404 	u32 rx_max_size = mtu_to_size(tp->netdev->mtu);
6405 
6406 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size);
6407 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
6408 	r8156_fc_parameter(tp);
6409 
6410 	/* TX share fifo free credit full threshold */
6411 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6412 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,
6413 		       ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);
6414 }
6415 
6416 static void rtl8156_up(struct r8152 *tp)
6417 {
6418 	u32 ocp_data;
6419 
6420 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
6421 		return;
6422 
6423 	r8153b_u1u2en(tp, false);
6424 	r8153_u2p3en(tp, false);
6425 	r8153_aldps_en(tp, false);
6426 
6427 	rxdy_gated_en(tp, true);
6428 	r8153_teredo_off(tp);
6429 
6430 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6431 	ocp_data &= ~RCR_ACPT_ALL;
6432 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6433 
6434 	rtl8152_nic_reset(tp);
6435 	rtl_reset_bmu(tp);
6436 
6437 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6438 	ocp_data &= ~NOW_IS_OOB;
6439 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6440 
6441 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6442 	ocp_data &= ~MCU_BORW_EN;
6443 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6444 
6445 	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6446 
6447 	rtl8156_change_mtu(tp);
6448 
6449 	switch (tp->version) {
6450 	case RTL_TEST_01:
6451 	case RTL_VER_10:
6452 	case RTL_VER_11:
6453 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
6454 		ocp_data |= ACT_ODMA;
6455 		ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
6456 		break;
6457 	default:
6458 		break;
6459 	}
6460 
6461 	/* share FIFO settings */
6462 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);
6463 	ocp_data &= ~RXFIFO_FULL_MASK;
6464 	ocp_data |= 0x08;
6465 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data);
6466 
6467 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6468 	ocp_data &= ~PLA_MCU_SPDWN_EN;
6469 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6470 
6471 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);
6472 	ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);
6473 	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data);
6474 
6475 	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400);
6476 
6477 	if (tp->saved_wolopts != __rtl_get_wol(tp)) {
6478 		netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n");
6479 		__rtl_set_wol(tp, tp->saved_wolopts);
6480 	}
6481 
6482 	r8153_aldps_en(tp, true);
6483 	r8153_u2p3en(tp, true);
6484 
6485 	if (tp->udev->speed >= USB_SPEED_SUPER)
6486 		r8153b_u1u2en(tp, true);
6487 }
6488 
6489 static void rtl8156_down(struct r8152 *tp)
6490 {
6491 	u32 ocp_data;
6492 
6493 	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6494 		rtl_drop_queued_tx(tp);
6495 		return;
6496 	}
6497 
6498 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6499 	ocp_data |= PLA_MCU_SPDWN_EN;
6500 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6501 
6502 	r8153b_u1u2en(tp, false);
6503 	r8153_u2p3en(tp, false);
6504 	r8153b_power_cut_en(tp, false);
6505 	r8153_aldps_en(tp, false);
6506 
6507 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6508 	ocp_data &= ~NOW_IS_OOB;
6509 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6510 
6511 	rtl_disable(tp);
6512 	rtl_reset_bmu(tp);
6513 
6514 	/* Clear teredo wake event. bit[15:8] is the teredo wakeup
6515 	 * type. Set it to zero. bits[7:0] are the W1C bits about
6516 	 * the events. Set them to all 1 to clear them.
6517 	 */
6518 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
6519 
6520 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6521 	ocp_data |= NOW_IS_OOB;
6522 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6523 
6524 	rtl_rx_vlan_en(tp, true);
6525 	rxdy_gated_en(tp, false);
6526 
6527 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6528 	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6529 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6530 
6531 	r8153_aldps_en(tp, true);
6532 }
6533 
6534 static bool rtl8152_in_nway(struct r8152 *tp)
6535 {
6536 	u16 nway_state;
6537 
6538 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
6539 	tp->ocp_base = 0x2000;
6540 	ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);		/* phy state */
6541 	nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
6542 
6543 	/* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
6544 	if (nway_state & 0xc000)
6545 		return false;
6546 	else
6547 		return true;
6548 }
6549 
6550 static bool rtl8153_in_nway(struct r8152 *tp)
6551 {
6552 	u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
6553 
6554 	if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
6555 		return false;
6556 	else
6557 		return true;
6558 }
6559 
6560 static void set_carrier(struct r8152 *tp)
6561 {
6562 	struct net_device *netdev = tp->netdev;
6563 	struct napi_struct *napi = &tp->napi;
6564 	u16 speed;
6565 
6566 	speed = rtl8152_get_speed(tp);
6567 
6568 	if (speed & LINK_STATUS) {
6569 		if (!netif_carrier_ok(netdev)) {
6570 			tp->rtl_ops.enable(tp);
6571 			netif_stop_queue(netdev);
6572 			napi_disable(napi);
6573 			netif_carrier_on(netdev);
6574 			rtl_start_rx(tp);
6575 			clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6576 			_rtl8152_set_rx_mode(netdev);
6577 			napi_enable(napi);
6578 			netif_wake_queue(netdev);
6579 			netif_info(tp, link, netdev, "carrier on\n");
6580 		} else if (netif_queue_stopped(netdev) &&
6581 			   skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
6582 			netif_wake_queue(netdev);
6583 		}
6584 	} else {
6585 		if (netif_carrier_ok(netdev)) {
6586 			netif_carrier_off(netdev);
6587 			tasklet_disable(&tp->tx_tl);
6588 			napi_disable(napi);
6589 			tp->rtl_ops.disable(tp);
6590 			napi_enable(napi);
6591 			tasklet_enable(&tp->tx_tl);
6592 			netif_info(tp, link, netdev, "carrier off\n");
6593 		}
6594 	}
6595 }
6596 
6597 static void rtl_work_func_t(struct work_struct *work)
6598 {
6599 	struct r8152 *tp = container_of(work, struct r8152, schedule.work);
6600 
6601 	/* If the device is unplugged or !netif_running(), the workqueue
6602 	 * doesn't need to wake the device, and could return directly.
6603 	 */
6604 	if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
6605 		return;
6606 
6607 	if (usb_autopm_get_interface(tp->intf) < 0)
6608 		return;
6609 
6610 	if (!test_bit(WORK_ENABLE, &tp->flags))
6611 		goto out1;
6612 
6613 	if (!mutex_trylock(&tp->control)) {
6614 		schedule_delayed_work(&tp->schedule, 0);
6615 		goto out1;
6616 	}
6617 
6618 	if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
6619 		set_carrier(tp);
6620 
6621 	if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
6622 		_rtl8152_set_rx_mode(tp->netdev);
6623 
6624 	/* don't schedule tasket before linking */
6625 	if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
6626 	    netif_carrier_ok(tp->netdev))
6627 		tasklet_schedule(&tp->tx_tl);
6628 
6629 	mutex_unlock(&tp->control);
6630 
6631 out1:
6632 	usb_autopm_put_interface(tp->intf);
6633 }
6634 
6635 static void rtl_hw_phy_work_func_t(struct work_struct *work)
6636 {
6637 	struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
6638 
6639 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
6640 		return;
6641 
6642 	if (usb_autopm_get_interface(tp->intf) < 0)
6643 		return;
6644 
6645 	mutex_lock(&tp->control);
6646 
6647 	if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
6648 		tp->rtl_fw.retry = false;
6649 		tp->rtl_fw.fw = NULL;
6650 
6651 		/* Delay execution in case request_firmware() is not ready yet.
6652 		 */
6653 		queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
6654 		goto ignore_once;
6655 	}
6656 
6657 	tp->rtl_ops.hw_phy_cfg(tp);
6658 
6659 	rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
6660 			  tp->advertising);
6661 
6662 ignore_once:
6663 	mutex_unlock(&tp->control);
6664 
6665 	usb_autopm_put_interface(tp->intf);
6666 }
6667 
6668 #ifdef CONFIG_PM_SLEEP
6669 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
6670 			void *data)
6671 {
6672 	struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
6673 
6674 	switch (action) {
6675 	case PM_HIBERNATION_PREPARE:
6676 	case PM_SUSPEND_PREPARE:
6677 		usb_autopm_get_interface(tp->intf);
6678 		break;
6679 
6680 	case PM_POST_HIBERNATION:
6681 	case PM_POST_SUSPEND:
6682 		usb_autopm_put_interface(tp->intf);
6683 		break;
6684 
6685 	case PM_POST_RESTORE:
6686 	case PM_RESTORE_PREPARE:
6687 	default:
6688 		break;
6689 	}
6690 
6691 	return NOTIFY_DONE;
6692 }
6693 #endif
6694 
6695 static int rtl8152_open(struct net_device *netdev)
6696 {
6697 	struct r8152 *tp = netdev_priv(netdev);
6698 	int res = 0;
6699 
6700 	if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
6701 		cancel_delayed_work_sync(&tp->hw_phy_work);
6702 		rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
6703 	}
6704 
6705 	res = alloc_all_mem(tp);
6706 	if (res)
6707 		goto out;
6708 
6709 	res = usb_autopm_get_interface(tp->intf);
6710 	if (res < 0)
6711 		goto out_free;
6712 
6713 	mutex_lock(&tp->control);
6714 
6715 	tp->rtl_ops.up(tp);
6716 
6717 	netif_carrier_off(netdev);
6718 	netif_start_queue(netdev);
6719 	set_bit(WORK_ENABLE, &tp->flags);
6720 
6721 	res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
6722 	if (res) {
6723 		if (res == -ENODEV)
6724 			netif_device_detach(tp->netdev);
6725 		netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
6726 			   res);
6727 		goto out_unlock;
6728 	}
6729 	napi_enable(&tp->napi);
6730 	tasklet_enable(&tp->tx_tl);
6731 
6732 	mutex_unlock(&tp->control);
6733 
6734 	usb_autopm_put_interface(tp->intf);
6735 #ifdef CONFIG_PM_SLEEP
6736 	tp->pm_notifier.notifier_call = rtl_notifier;
6737 	register_pm_notifier(&tp->pm_notifier);
6738 #endif
6739 	return 0;
6740 
6741 out_unlock:
6742 	mutex_unlock(&tp->control);
6743 	usb_autopm_put_interface(tp->intf);
6744 out_free:
6745 	free_all_mem(tp);
6746 out:
6747 	return res;
6748 }
6749 
6750 static int rtl8152_close(struct net_device *netdev)
6751 {
6752 	struct r8152 *tp = netdev_priv(netdev);
6753 	int res = 0;
6754 
6755 #ifdef CONFIG_PM_SLEEP
6756 	unregister_pm_notifier(&tp->pm_notifier);
6757 #endif
6758 	tasklet_disable(&tp->tx_tl);
6759 	clear_bit(WORK_ENABLE, &tp->flags);
6760 	usb_kill_urb(tp->intr_urb);
6761 	cancel_delayed_work_sync(&tp->schedule);
6762 	napi_disable(&tp->napi);
6763 	netif_stop_queue(netdev);
6764 
6765 	res = usb_autopm_get_interface(tp->intf);
6766 	if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
6767 		rtl_drop_queued_tx(tp);
6768 		rtl_stop_rx(tp);
6769 	} else {
6770 		mutex_lock(&tp->control);
6771 
6772 		tp->rtl_ops.down(tp);
6773 
6774 		mutex_unlock(&tp->control);
6775 	}
6776 
6777 	if (!res)
6778 		usb_autopm_put_interface(tp->intf);
6779 
6780 	free_all_mem(tp);
6781 
6782 	return res;
6783 }
6784 
6785 static void rtl_tally_reset(struct r8152 *tp)
6786 {
6787 	u32 ocp_data;
6788 
6789 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
6790 	ocp_data |= TALLY_RESET;
6791 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
6792 }
6793 
6794 static void r8152b_init(struct r8152 *tp)
6795 {
6796 	u32 ocp_data;
6797 	u16 data;
6798 
6799 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
6800 		return;
6801 
6802 	data = r8152_mdio_read(tp, MII_BMCR);
6803 	if (data & BMCR_PDOWN) {
6804 		data &= ~BMCR_PDOWN;
6805 		r8152_mdio_write(tp, MII_BMCR, data);
6806 	}
6807 
6808 	r8152_aldps_en(tp, false);
6809 
6810 	if (tp->version == RTL_VER_01) {
6811 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
6812 		ocp_data &= ~LED_MODE_MASK;
6813 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
6814 	}
6815 
6816 	r8152_power_cut_en(tp, false);
6817 
6818 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
6819 	ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
6820 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
6821 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
6822 	ocp_data &= ~MCU_CLK_RATIO_MASK;
6823 	ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
6824 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
6825 	ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
6826 		   SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
6827 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
6828 
6829 	rtl_tally_reset(tp);
6830 
6831 	/* enable rx aggregation */
6832 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
6833 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
6834 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
6835 }
6836 
6837 static void r8153_init(struct r8152 *tp)
6838 {
6839 	u32 ocp_data;
6840 	u16 data;
6841 	int i;
6842 
6843 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
6844 		return;
6845 
6846 	r8153_u1u2en(tp, false);
6847 
6848 	for (i = 0; i < 500; i++) {
6849 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
6850 		    AUTOLOAD_DONE)
6851 			break;
6852 
6853 		msleep(20);
6854 		if (test_bit(RTL8152_UNPLUG, &tp->flags))
6855 			break;
6856 	}
6857 
6858 	data = r8153_phy_status(tp, 0);
6859 
6860 	if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
6861 	    tp->version == RTL_VER_05)
6862 		ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
6863 
6864 	data = r8152_mdio_read(tp, MII_BMCR);
6865 	if (data & BMCR_PDOWN) {
6866 		data &= ~BMCR_PDOWN;
6867 		r8152_mdio_write(tp, MII_BMCR, data);
6868 	}
6869 
6870 	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
6871 
6872 	r8153_u2p3en(tp, false);
6873 
6874 	if (tp->version == RTL_VER_04) {
6875 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
6876 		ocp_data &= ~pwd_dn_scale_mask;
6877 		ocp_data |= pwd_dn_scale(96);
6878 		ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
6879 
6880 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
6881 		ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
6882 		ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
6883 	} else if (tp->version == RTL_VER_05) {
6884 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
6885 		ocp_data &= ~ECM_ALDPS;
6886 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
6887 
6888 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
6889 		if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
6890 			ocp_data &= ~DYNAMIC_BURST;
6891 		else
6892 			ocp_data |= DYNAMIC_BURST;
6893 		ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
6894 	} else if (tp->version == RTL_VER_06) {
6895 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
6896 		if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
6897 			ocp_data &= ~DYNAMIC_BURST;
6898 		else
6899 			ocp_data |= DYNAMIC_BURST;
6900 		ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
6901 
6902 		r8153_queue_wake(tp, false);
6903 
6904 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
6905 		if (rtl8152_get_speed(tp) & LINK_STATUS)
6906 			ocp_data |= CUR_LINK_OK;
6907 		else
6908 			ocp_data &= ~CUR_LINK_OK;
6909 		ocp_data |= POLL_LINK_CHG;
6910 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
6911 	}
6912 
6913 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
6914 	ocp_data |= EP4_FULL_FC;
6915 	ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
6916 
6917 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
6918 	ocp_data &= ~TIMER11_EN;
6919 	ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
6920 
6921 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
6922 	ocp_data &= ~LED_MODE_MASK;
6923 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
6924 
6925 	ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
6926 	if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
6927 		ocp_data |= LPM_TIMER_500MS;
6928 	else
6929 		ocp_data |= LPM_TIMER_500US;
6930 	ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
6931 
6932 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
6933 	ocp_data &= ~SEN_VAL_MASK;
6934 	ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
6935 	ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
6936 
6937 	ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
6938 
6939 	r8153_power_cut_en(tp, false);
6940 	rtl_runtime_suspend_enable(tp, false);
6941 	r8153_mac_clk_speed_down(tp, false);
6942 	r8153_u1u2en(tp, true);
6943 	usb_enable_lpm(tp->udev);
6944 
6945 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6946 	ocp_data |= LANWAKE_CLR_EN;
6947 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6948 
6949 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6950 	ocp_data &= ~LANWAKE_PIN;
6951 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
6952 
6953 	/* rx aggregation */
6954 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
6955 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
6956 	if (tp->dell_tb_rx_agg_bug)
6957 		ocp_data |= RX_AGG_DISABLE;
6958 
6959 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
6960 
6961 	rtl_tally_reset(tp);
6962 
6963 	switch (tp->udev->speed) {
6964 	case USB_SPEED_SUPER:
6965 	case USB_SPEED_SUPER_PLUS:
6966 		tp->coalesce = COALESCE_SUPER;
6967 		break;
6968 	case USB_SPEED_HIGH:
6969 		tp->coalesce = COALESCE_HIGH;
6970 		break;
6971 	default:
6972 		tp->coalesce = COALESCE_SLOW;
6973 		break;
6974 	}
6975 }
6976 
6977 static void r8153b_init(struct r8152 *tp)
6978 {
6979 	u32 ocp_data;
6980 	u16 data;
6981 	int i;
6982 
6983 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
6984 		return;
6985 
6986 	r8153b_u1u2en(tp, false);
6987 
6988 	for (i = 0; i < 500; i++) {
6989 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
6990 		    AUTOLOAD_DONE)
6991 			break;
6992 
6993 		msleep(20);
6994 		if (test_bit(RTL8152_UNPLUG, &tp->flags))
6995 			break;
6996 	}
6997 
6998 	data = r8153_phy_status(tp, 0);
6999 
7000 	data = r8152_mdio_read(tp, MII_BMCR);
7001 	if (data & BMCR_PDOWN) {
7002 		data &= ~BMCR_PDOWN;
7003 		r8152_mdio_write(tp, MII_BMCR, data);
7004 	}
7005 
7006 	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7007 
7008 	r8153_u2p3en(tp, false);
7009 
7010 	/* MSC timer = 0xfff * 8ms = 32760 ms */
7011 	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7012 
7013 	r8153b_power_cut_en(tp, false);
7014 	r8153b_ups_en(tp, false);
7015 	r8153_queue_wake(tp, false);
7016 	rtl_runtime_suspend_enable(tp, false);
7017 
7018 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7019 	if (rtl8152_get_speed(tp) & LINK_STATUS)
7020 		ocp_data |= CUR_LINK_OK;
7021 	else
7022 		ocp_data &= ~CUR_LINK_OK;
7023 	ocp_data |= POLL_LINK_CHG;
7024 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7025 
7026 	if (tp->udev->speed >= USB_SPEED_SUPER)
7027 		r8153b_u1u2en(tp, true);
7028 
7029 	usb_enable_lpm(tp->udev);
7030 
7031 	/* MAC clock speed down */
7032 	r8153_mac_clk_speed_down(tp, true);
7033 
7034 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7035 	ocp_data &= ~PLA_MCU_SPDWN_EN;
7036 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
7037 
7038 	if (tp->version == RTL_VER_09) {
7039 		/* Disable Test IO for 32QFN */
7040 		if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
7041 			ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7042 			ocp_data |= TEST_IO_OFF;
7043 			ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7044 		}
7045 	}
7046 
7047 	set_bit(GREEN_ETHERNET, &tp->flags);
7048 
7049 	/* rx aggregation */
7050 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7051 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7052 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7053 
7054 	rtl_tally_reset(tp);
7055 
7056 	tp->coalesce = 15000;	/* 15 us */
7057 }
7058 
7059 static void r8153c_init(struct r8152 *tp)
7060 {
7061 	u32 ocp_data;
7062 	u16 data;
7063 	int i;
7064 
7065 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
7066 		return;
7067 
7068 	r8153b_u1u2en(tp, false);
7069 
7070 	/* Disable spi_en */
7071 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
7072 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
7073 	ocp_data &= ~BIT(3);
7074 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
7075 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0);
7076 	ocp_data |= BIT(1);
7077 	ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data);
7078 
7079 	for (i = 0; i < 500; i++) {
7080 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7081 		    AUTOLOAD_DONE)
7082 			break;
7083 
7084 		msleep(20);
7085 		if (test_bit(RTL8152_UNPLUG, &tp->flags))
7086 			return;
7087 	}
7088 
7089 	data = r8153_phy_status(tp, 0);
7090 
7091 	data = r8152_mdio_read(tp, MII_BMCR);
7092 	if (data & BMCR_PDOWN) {
7093 		data &= ~BMCR_PDOWN;
7094 		r8152_mdio_write(tp, MII_BMCR, data);
7095 	}
7096 
7097 	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7098 
7099 	r8153_u2p3en(tp, false);
7100 
7101 	/* MSC timer = 0xfff * 8ms = 32760 ms */
7102 	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7103 
7104 	r8153b_power_cut_en(tp, false);
7105 	r8153c_ups_en(tp, false);
7106 	r8153_queue_wake(tp, false);
7107 	rtl_runtime_suspend_enable(tp, false);
7108 
7109 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7110 	if (rtl8152_get_speed(tp) & LINK_STATUS)
7111 		ocp_data |= CUR_LINK_OK;
7112 	else
7113 		ocp_data &= ~CUR_LINK_OK;
7114 
7115 	ocp_data |= POLL_LINK_CHG;
7116 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7117 
7118 	r8153b_u1u2en(tp, true);
7119 
7120 	usb_enable_lpm(tp->udev);
7121 
7122 	/* MAC clock speed down */
7123 	r8153_mac_clk_speed_down(tp, true);
7124 
7125 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
7126 	ocp_data &= ~BIT(7);
7127 	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
7128 
7129 	set_bit(GREEN_ETHERNET, &tp->flags);
7130 
7131 	/* rx aggregation */
7132 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7133 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7134 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7135 
7136 	rtl_tally_reset(tp);
7137 
7138 	tp->coalesce = 15000;	/* 15 us */
7139 }
7140 
7141 static void r8156_hw_phy_cfg(struct r8152 *tp)
7142 {
7143 	u32 ocp_data;
7144 	u16 data;
7145 
7146 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7147 	if (ocp_data & PCUT_STATUS) {
7148 		ocp_data &= ~PCUT_STATUS;
7149 		ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7150 	}
7151 
7152 	data = r8153_phy_status(tp, 0);
7153 	switch (data) {
7154 	case PHY_STAT_EXT_INIT:
7155 		rtl8152_apply_firmware(tp, true);
7156 
7157 		data = ocp_reg_read(tp, 0xa468);
7158 		data &= ~(BIT(3) | BIT(1));
7159 		ocp_reg_write(tp, 0xa468, data);
7160 		break;
7161 	case PHY_STAT_LAN_ON:
7162 	case PHY_STAT_PWRDN:
7163 	default:
7164 		rtl8152_apply_firmware(tp, false);
7165 		break;
7166 	}
7167 
7168 	/* disable ALDPS before updating the PHY parameters */
7169 	r8153_aldps_en(tp, false);
7170 
7171 	/* disable EEE before updating the PHY parameters */
7172 	rtl_eee_enable(tp, false);
7173 
7174 	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7175 	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7176 
7177 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7178 	ocp_data |= PFM_PWM_SWITCH;
7179 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7180 
7181 	switch (tp->version) {
7182 	case RTL_VER_10:
7183 		data = ocp_reg_read(tp, 0xad40);
7184 		data &= ~0x3ff;
7185 		data |= BIT(7) | BIT(2);
7186 		ocp_reg_write(tp, 0xad40, data);
7187 
7188 		data = ocp_reg_read(tp, 0xad4e);
7189 		data |= BIT(4);
7190 		ocp_reg_write(tp, 0xad4e, data);
7191 		data = ocp_reg_read(tp, 0xad16);
7192 		data &= ~0x3ff;
7193 		data |= 0x6;
7194 		ocp_reg_write(tp, 0xad16, data);
7195 		data = ocp_reg_read(tp, 0xad32);
7196 		data &= ~0x3f;
7197 		data |= 6;
7198 		ocp_reg_write(tp, 0xad32, data);
7199 		data = ocp_reg_read(tp, 0xac08);
7200 		data &= ~(BIT(12) | BIT(8));
7201 		ocp_reg_write(tp, 0xac08, data);
7202 		data = ocp_reg_read(tp, 0xac8a);
7203 		data |= BIT(12) | BIT(13) | BIT(14);
7204 		data &= ~BIT(15);
7205 		ocp_reg_write(tp, 0xac8a, data);
7206 		data = ocp_reg_read(tp, 0xad18);
7207 		data |= BIT(10);
7208 		ocp_reg_write(tp, 0xad18, data);
7209 		data = ocp_reg_read(tp, 0xad1a);
7210 		data |= 0x3ff;
7211 		ocp_reg_write(tp, 0xad1a, data);
7212 		data = ocp_reg_read(tp, 0xad1c);
7213 		data |= 0x3ff;
7214 		ocp_reg_write(tp, 0xad1c, data);
7215 
7216 		data = sram_read(tp, 0x80ea);
7217 		data &= ~0xff00;
7218 		data |= 0xc400;
7219 		sram_write(tp, 0x80ea, data);
7220 		data = sram_read(tp, 0x80eb);
7221 		data &= ~0x0700;
7222 		data |= 0x0300;
7223 		sram_write(tp, 0x80eb, data);
7224 		data = sram_read(tp, 0x80f8);
7225 		data &= ~0xff00;
7226 		data |= 0x1c00;
7227 		sram_write(tp, 0x80f8, data);
7228 		data = sram_read(tp, 0x80f1);
7229 		data &= ~0xff00;
7230 		data |= 0x3000;
7231 		sram_write(tp, 0x80f1, data);
7232 
7233 		data = sram_read(tp, 0x80fe);
7234 		data &= ~0xff00;
7235 		data |= 0xa500;
7236 		sram_write(tp, 0x80fe, data);
7237 		data = sram_read(tp, 0x8102);
7238 		data &= ~0xff00;
7239 		data |= 0x5000;
7240 		sram_write(tp, 0x8102, data);
7241 		data = sram_read(tp, 0x8015);
7242 		data &= ~0xff00;
7243 		data |= 0x3300;
7244 		sram_write(tp, 0x8015, data);
7245 		data = sram_read(tp, 0x8100);
7246 		data &= ~0xff00;
7247 		data |= 0x7000;
7248 		sram_write(tp, 0x8100, data);
7249 		data = sram_read(tp, 0x8014);
7250 		data &= ~0xff00;
7251 		data |= 0xf000;
7252 		sram_write(tp, 0x8014, data);
7253 		data = sram_read(tp, 0x8016);
7254 		data &= ~0xff00;
7255 		data |= 0x6500;
7256 		sram_write(tp, 0x8016, data);
7257 		data = sram_read(tp, 0x80dc);
7258 		data &= ~0xff00;
7259 		data |= 0xed00;
7260 		sram_write(tp, 0x80dc, data);
7261 		data = sram_read(tp, 0x80df);
7262 		data |= BIT(8);
7263 		sram_write(tp, 0x80df, data);
7264 		data = sram_read(tp, 0x80e1);
7265 		data &= ~BIT(8);
7266 		sram_write(tp, 0x80e1, data);
7267 
7268 		data = ocp_reg_read(tp, 0xbf06);
7269 		data &= ~0x003f;
7270 		data |= 0x0038;
7271 		ocp_reg_write(tp, 0xbf06, data);
7272 
7273 		sram_write(tp, 0x819f, 0xddb6);
7274 
7275 		ocp_reg_write(tp, 0xbc34, 0x5555);
7276 		data = ocp_reg_read(tp, 0xbf0a);
7277 		data &= ~0x0e00;
7278 		data |= 0x0a00;
7279 		ocp_reg_write(tp, 0xbf0a, data);
7280 
7281 		data = ocp_reg_read(tp, 0xbd2c);
7282 		data &= ~BIT(13);
7283 		ocp_reg_write(tp, 0xbd2c, data);
7284 		break;
7285 	case RTL_VER_11:
7286 		data = ocp_reg_read(tp, 0xad16);
7287 		data |= 0x3ff;
7288 		ocp_reg_write(tp, 0xad16, data);
7289 		data = ocp_reg_read(tp, 0xad32);
7290 		data &= ~0x3f;
7291 		data |= 6;
7292 		ocp_reg_write(tp, 0xad32, data);
7293 		data = ocp_reg_read(tp, 0xac08);
7294 		data &= ~(BIT(12) | BIT(8));
7295 		ocp_reg_write(tp, 0xac08, data);
7296 		data = ocp_reg_read(tp, 0xacc0);
7297 		data &= ~0x3;
7298 		data |= BIT(1);
7299 		ocp_reg_write(tp, 0xacc0, data);
7300 		data = ocp_reg_read(tp, 0xad40);
7301 		data &= ~0xe7;
7302 		data |= BIT(6) | BIT(2);
7303 		ocp_reg_write(tp, 0xad40, data);
7304 		data = ocp_reg_read(tp, 0xac14);
7305 		data &= ~BIT(7);
7306 		ocp_reg_write(tp, 0xac14, data);
7307 		data = ocp_reg_read(tp, 0xac80);
7308 		data &= ~(BIT(8) | BIT(9));
7309 		ocp_reg_write(tp, 0xac80, data);
7310 		data = ocp_reg_read(tp, 0xac5e);
7311 		data &= ~0x7;
7312 		data |= BIT(1);
7313 		ocp_reg_write(tp, 0xac5e, data);
7314 		ocp_reg_write(tp, 0xad4c, 0x00a8);
7315 		ocp_reg_write(tp, 0xac5c, 0x01ff);
7316 		data = ocp_reg_read(tp, 0xac8a);
7317 		data &= ~0xf0;
7318 		data |= BIT(4) | BIT(5);
7319 		ocp_reg_write(tp, 0xac8a, data);
7320 		ocp_reg_write(tp, 0xb87c, 0x8157);
7321 		data = ocp_reg_read(tp, 0xb87e);
7322 		data &= ~0xff00;
7323 		data |= 0x0500;
7324 		ocp_reg_write(tp, 0xb87e, data);
7325 		ocp_reg_write(tp, 0xb87c, 0x8159);
7326 		data = ocp_reg_read(tp, 0xb87e);
7327 		data &= ~0xff00;
7328 		data |= 0x0700;
7329 		ocp_reg_write(tp, 0xb87e, data);
7330 
7331 		/* AAGC */
7332 		ocp_reg_write(tp, 0xb87c, 0x80a2);
7333 		ocp_reg_write(tp, 0xb87e, 0x0153);
7334 		ocp_reg_write(tp, 0xb87c, 0x809c);
7335 		ocp_reg_write(tp, 0xb87e, 0x0153);
7336 
7337 		/* EEE parameter */
7338 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);
7339 
7340 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7341 		ocp_data |= EN_XG_LIP | EN_G_LIP;
7342 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7343 
7344 		sram_write(tp, 0x8257, 0x020f); /*  XG PLL */
7345 		sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */
7346 
7347 		if (rtl_phy_patch_request(tp, true, true))
7348 			return;
7349 
7350 		/* Advance EEE */
7351 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7352 		ocp_data |= EEE_SPDWN_EN;
7353 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
7354 
7355 		data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7356 		data &= ~(EN_EEE_100 | EN_EEE_1000);
7357 		data |= EN_10M_CLKDIV;
7358 		ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7359 		tp->ups_info._10m_ckdiv = true;
7360 		tp->ups_info.eee_plloff_100 = false;
7361 		tp->ups_info.eee_plloff_giga = false;
7362 
7363 		data = ocp_reg_read(tp, OCP_POWER_CFG);
7364 		data &= ~EEE_CLKDIV_EN;
7365 		ocp_reg_write(tp, OCP_POWER_CFG, data);
7366 		tp->ups_info.eee_ckdiv = false;
7367 
7368 		ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
7369 		ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));
7370 		tp->ups_info._250m_ckdiv = false;
7371 
7372 		rtl_phy_patch_request(tp, false, true);
7373 
7374 		/* enable ADC Ibias Cal */
7375 		data = ocp_reg_read(tp, 0xd068);
7376 		data |= BIT(13);
7377 		ocp_reg_write(tp, 0xd068, data);
7378 
7379 		/* enable Thermal Sensor */
7380 		data = sram_read(tp, 0x81a2);
7381 		data &= ~BIT(8);
7382 		sram_write(tp, 0x81a2, data);
7383 		data = ocp_reg_read(tp, 0xb54c);
7384 		data &= ~0xff00;
7385 		data |= 0xdb00;
7386 		ocp_reg_write(tp, 0xb54c, data);
7387 
7388 		/* Nway 2.5G Lite */
7389 		data = ocp_reg_read(tp, 0xa454);
7390 		data &= ~BIT(0);
7391 		ocp_reg_write(tp, 0xa454, data);
7392 
7393 		/* CS DSP solution */
7394 		data = ocp_reg_read(tp, OCP_10GBT_CTRL);
7395 		data |= RTL_ADV2_5G_F_R;
7396 		ocp_reg_write(tp, OCP_10GBT_CTRL, data);
7397 		data = ocp_reg_read(tp, 0xad4e);
7398 		data &= ~BIT(4);
7399 		ocp_reg_write(tp, 0xad4e, data);
7400 		data = ocp_reg_read(tp, 0xa86a);
7401 		data &= ~BIT(0);
7402 		ocp_reg_write(tp, 0xa86a, data);
7403 
7404 		/* MDI SWAP */
7405 		if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&
7406 		    (ocp_reg_read(tp, 0xd068) & BIT(1))) {
7407 			u16 swap_a, swap_b;
7408 
7409 			data = ocp_reg_read(tp, 0xd068);
7410 			data &= ~0x1f;
7411 			data |= 0x1; /* p0 */
7412 			ocp_reg_write(tp, 0xd068, data);
7413 			swap_a = ocp_reg_read(tp, 0xd06a);
7414 			data &= ~0x18;
7415 			data |= 0x18; /* p3 */
7416 			ocp_reg_write(tp, 0xd068, data);
7417 			swap_b = ocp_reg_read(tp, 0xd06a);
7418 			data &= ~0x18; /* p0 */
7419 			ocp_reg_write(tp, 0xd068, data);
7420 			ocp_reg_write(tp, 0xd06a,
7421 				      (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7422 			data |= 0x18; /* p3 */
7423 			ocp_reg_write(tp, 0xd068, data);
7424 			ocp_reg_write(tp, 0xd06a,
7425 				      (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7426 			data &= ~0x18;
7427 			data |= 0x08; /* p1 */
7428 			ocp_reg_write(tp, 0xd068, data);
7429 			swap_a = ocp_reg_read(tp, 0xd06a);
7430 			data &= ~0x18;
7431 			data |= 0x10; /* p2 */
7432 			ocp_reg_write(tp, 0xd068, data);
7433 			swap_b = ocp_reg_read(tp, 0xd06a);
7434 			data &= ~0x18;
7435 			data |= 0x08; /* p1 */
7436 			ocp_reg_write(tp, 0xd068, data);
7437 			ocp_reg_write(tp, 0xd06a,
7438 				      (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7439 			data &= ~0x18;
7440 			data |= 0x10; /* p2 */
7441 			ocp_reg_write(tp, 0xd068, data);
7442 			ocp_reg_write(tp, 0xd06a,
7443 				      (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7444 			swap_a = ocp_reg_read(tp, 0xbd5a);
7445 			swap_b = ocp_reg_read(tp, 0xbd5c);
7446 			ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) |
7447 				      ((swap_b & 0x1f) << 8) |
7448 				      ((swap_b >> 8) & 0x1f));
7449 			ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) |
7450 				      ((swap_a & 0x1f) << 8) |
7451 				      ((swap_a >> 8) & 0x1f));
7452 			swap_a = ocp_reg_read(tp, 0xbc18);
7453 			swap_b = ocp_reg_read(tp, 0xbc1a);
7454 			ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) |
7455 				      ((swap_b & 0x1f) << 8) |
7456 				      ((swap_b >> 8) & 0x1f));
7457 			ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) |
7458 				      ((swap_a & 0x1f) << 8) |
7459 				      ((swap_a >> 8) & 0x1f));
7460 		}
7461 		break;
7462 	default:
7463 		break;
7464 	}
7465 
7466 	rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7467 
7468 	data = ocp_reg_read(tp, 0xa428);
7469 	data &= ~BIT(9);
7470 	ocp_reg_write(tp, 0xa428, data);
7471 	data = ocp_reg_read(tp, 0xa5ea);
7472 	data &= ~BIT(0);
7473 	ocp_reg_write(tp, 0xa5ea, data);
7474 	tp->ups_info.lite_mode = 0;
7475 
7476 	if (tp->eee_en)
7477 		rtl_eee_enable(tp, true);
7478 
7479 	r8153_aldps_en(tp, true);
7480 	r8152b_enable_fc(tp);
7481 	r8153_u2p3en(tp, true);
7482 
7483 	set_bit(PHY_RESET, &tp->flags);
7484 }
7485 
7486 static void r8156b_hw_phy_cfg(struct r8152 *tp)
7487 {
7488 	u32 ocp_data;
7489 	u16 data;
7490 
7491 	switch (tp->version) {
7492 	case RTL_VER_12:
7493 		ocp_reg_write(tp, 0xbf86, 0x9000);
7494 		data = ocp_reg_read(tp, 0xc402);
7495 		data |= BIT(10);
7496 		ocp_reg_write(tp, 0xc402, data);
7497 		data &= ~BIT(10);
7498 		ocp_reg_write(tp, 0xc402, data);
7499 		ocp_reg_write(tp, 0xbd86, 0x1010);
7500 		ocp_reg_write(tp, 0xbd88, 0x1010);
7501 		data = ocp_reg_read(tp, 0xbd4e);
7502 		data &= ~(BIT(10) | BIT(11));
7503 		data |= BIT(11);
7504 		ocp_reg_write(tp, 0xbd4e, data);
7505 		data = ocp_reg_read(tp, 0xbf46);
7506 		data &= ~0xf00;
7507 		data |= 0x700;
7508 		ocp_reg_write(tp, 0xbf46, data);
7509 		break;
7510 	case RTL_VER_13:
7511 	case RTL_VER_15:
7512 		r8156b_wait_loading_flash(tp);
7513 		break;
7514 	default:
7515 		break;
7516 	}
7517 
7518 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7519 	if (ocp_data & PCUT_STATUS) {
7520 		ocp_data &= ~PCUT_STATUS;
7521 		ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7522 	}
7523 
7524 	data = r8153_phy_status(tp, 0);
7525 	switch (data) {
7526 	case PHY_STAT_EXT_INIT:
7527 		rtl8152_apply_firmware(tp, true);
7528 
7529 		data = ocp_reg_read(tp, 0xa466);
7530 		data &= ~BIT(0);
7531 		ocp_reg_write(tp, 0xa466, data);
7532 
7533 		data = ocp_reg_read(tp, 0xa468);
7534 		data &= ~(BIT(3) | BIT(1));
7535 		ocp_reg_write(tp, 0xa468, data);
7536 		break;
7537 	case PHY_STAT_LAN_ON:
7538 	case PHY_STAT_PWRDN:
7539 	default:
7540 		rtl8152_apply_firmware(tp, false);
7541 		break;
7542 	}
7543 
7544 	data = r8152_mdio_read(tp, MII_BMCR);
7545 	if (data & BMCR_PDOWN) {
7546 		data &= ~BMCR_PDOWN;
7547 		r8152_mdio_write(tp, MII_BMCR, data);
7548 	}
7549 
7550 	/* disable ALDPS before updating the PHY parameters */
7551 	r8153_aldps_en(tp, false);
7552 
7553 	/* disable EEE before updating the PHY parameters */
7554 	rtl_eee_enable(tp, false);
7555 
7556 	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7557 	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7558 
7559 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7560 	ocp_data |= PFM_PWM_SWITCH;
7561 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7562 
7563 	switch (tp->version) {
7564 	case RTL_VER_12:
7565 		data = ocp_reg_read(tp, 0xbc08);
7566 		data |= BIT(3) | BIT(2);
7567 		ocp_reg_write(tp, 0xbc08, data);
7568 
7569 		data = sram_read(tp, 0x8fff);
7570 		data &= ~0xff00;
7571 		data |= 0x0400;
7572 		sram_write(tp, 0x8fff, data);
7573 
7574 		data = ocp_reg_read(tp, 0xacda);
7575 		data |= 0xff00;
7576 		ocp_reg_write(tp, 0xacda, data);
7577 		data = ocp_reg_read(tp, 0xacde);
7578 		data |= 0xf000;
7579 		ocp_reg_write(tp, 0xacde, data);
7580 		ocp_reg_write(tp, 0xac8c, 0x0ffc);
7581 		ocp_reg_write(tp, 0xac46, 0xb7b4);
7582 		ocp_reg_write(tp, 0xac50, 0x0fbc);
7583 		ocp_reg_write(tp, 0xac3c, 0x9240);
7584 		ocp_reg_write(tp, 0xac4e, 0x0db4);
7585 		ocp_reg_write(tp, 0xacc6, 0x0707);
7586 		ocp_reg_write(tp, 0xacc8, 0xa0d3);
7587 		ocp_reg_write(tp, 0xad08, 0x0007);
7588 
7589 		ocp_reg_write(tp, 0xb87c, 0x8560);
7590 		ocp_reg_write(tp, 0xb87e, 0x19cc);
7591 		ocp_reg_write(tp, 0xb87c, 0x8562);
7592 		ocp_reg_write(tp, 0xb87e, 0x19cc);
7593 		ocp_reg_write(tp, 0xb87c, 0x8564);
7594 		ocp_reg_write(tp, 0xb87e, 0x19cc);
7595 		ocp_reg_write(tp, 0xb87c, 0x8566);
7596 		ocp_reg_write(tp, 0xb87e, 0x147d);
7597 		ocp_reg_write(tp, 0xb87c, 0x8568);
7598 		ocp_reg_write(tp, 0xb87e, 0x147d);
7599 		ocp_reg_write(tp, 0xb87c, 0x856a);
7600 		ocp_reg_write(tp, 0xb87e, 0x147d);
7601 		ocp_reg_write(tp, 0xb87c, 0x8ffe);
7602 		ocp_reg_write(tp, 0xb87e, 0x0907);
7603 		ocp_reg_write(tp, 0xb87c, 0x80d6);
7604 		ocp_reg_write(tp, 0xb87e, 0x2801);
7605 		ocp_reg_write(tp, 0xb87c, 0x80f2);
7606 		ocp_reg_write(tp, 0xb87e, 0x2801);
7607 		ocp_reg_write(tp, 0xb87c, 0x80f4);
7608 		ocp_reg_write(tp, 0xb87e, 0x6077);
7609 		ocp_reg_write(tp, 0xb506, 0x01e7);
7610 
7611 		ocp_reg_write(tp, 0xb87c, 0x8013);
7612 		ocp_reg_write(tp, 0xb87e, 0x0700);
7613 		ocp_reg_write(tp, 0xb87c, 0x8fb9);
7614 		ocp_reg_write(tp, 0xb87e, 0x2801);
7615 		ocp_reg_write(tp, 0xb87c, 0x8fba);
7616 		ocp_reg_write(tp, 0xb87e, 0x0100);
7617 		ocp_reg_write(tp, 0xb87c, 0x8fbc);
7618 		ocp_reg_write(tp, 0xb87e, 0x1900);
7619 		ocp_reg_write(tp, 0xb87c, 0x8fbe);
7620 		ocp_reg_write(tp, 0xb87e, 0xe100);
7621 		ocp_reg_write(tp, 0xb87c, 0x8fc0);
7622 		ocp_reg_write(tp, 0xb87e, 0x0800);
7623 		ocp_reg_write(tp, 0xb87c, 0x8fc2);
7624 		ocp_reg_write(tp, 0xb87e, 0xe500);
7625 		ocp_reg_write(tp, 0xb87c, 0x8fc4);
7626 		ocp_reg_write(tp, 0xb87e, 0x0f00);
7627 		ocp_reg_write(tp, 0xb87c, 0x8fc6);
7628 		ocp_reg_write(tp, 0xb87e, 0xf100);
7629 		ocp_reg_write(tp, 0xb87c, 0x8fc8);
7630 		ocp_reg_write(tp, 0xb87e, 0x0400);
7631 		ocp_reg_write(tp, 0xb87c, 0x8fca);
7632 		ocp_reg_write(tp, 0xb87e, 0xf300);
7633 		ocp_reg_write(tp, 0xb87c, 0x8fcc);
7634 		ocp_reg_write(tp, 0xb87e, 0xfd00);
7635 		ocp_reg_write(tp, 0xb87c, 0x8fce);
7636 		ocp_reg_write(tp, 0xb87e, 0xff00);
7637 		ocp_reg_write(tp, 0xb87c, 0x8fd0);
7638 		ocp_reg_write(tp, 0xb87e, 0xfb00);
7639 		ocp_reg_write(tp, 0xb87c, 0x8fd2);
7640 		ocp_reg_write(tp, 0xb87e, 0x0100);
7641 		ocp_reg_write(tp, 0xb87c, 0x8fd4);
7642 		ocp_reg_write(tp, 0xb87e, 0xf400);
7643 		ocp_reg_write(tp, 0xb87c, 0x8fd6);
7644 		ocp_reg_write(tp, 0xb87e, 0xff00);
7645 		ocp_reg_write(tp, 0xb87c, 0x8fd8);
7646 		ocp_reg_write(tp, 0xb87e, 0xf600);
7647 
7648 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7649 		ocp_data |= EN_XG_LIP | EN_G_LIP;
7650 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7651 		ocp_reg_write(tp, 0xb87c, 0x813d);
7652 		ocp_reg_write(tp, 0xb87e, 0x390e);
7653 		ocp_reg_write(tp, 0xb87c, 0x814f);
7654 		ocp_reg_write(tp, 0xb87e, 0x790e);
7655 		ocp_reg_write(tp, 0xb87c, 0x80b0);
7656 		ocp_reg_write(tp, 0xb87e, 0x0f31);
7657 		data = ocp_reg_read(tp, 0xbf4c);
7658 		data |= BIT(1);
7659 		ocp_reg_write(tp, 0xbf4c, data);
7660 		data = ocp_reg_read(tp, 0xbcca);
7661 		data |= BIT(9) | BIT(8);
7662 		ocp_reg_write(tp, 0xbcca, data);
7663 		ocp_reg_write(tp, 0xb87c, 0x8141);
7664 		ocp_reg_write(tp, 0xb87e, 0x320e);
7665 		ocp_reg_write(tp, 0xb87c, 0x8153);
7666 		ocp_reg_write(tp, 0xb87e, 0x720e);
7667 		ocp_reg_write(tp, 0xb87c, 0x8529);
7668 		ocp_reg_write(tp, 0xb87e, 0x050e);
7669 		data = ocp_reg_read(tp, OCP_EEE_CFG);
7670 		data &= ~CTAP_SHORT_EN;
7671 		ocp_reg_write(tp, OCP_EEE_CFG, data);
7672 
7673 		sram_write(tp, 0x816c, 0xc4a0);
7674 		sram_write(tp, 0x8170, 0xc4a0);
7675 		sram_write(tp, 0x8174, 0x04a0);
7676 		sram_write(tp, 0x8178, 0x04a0);
7677 		sram_write(tp, 0x817c, 0x0719);
7678 		sram_write(tp, 0x8ff4, 0x0400);
7679 		sram_write(tp, 0x8ff1, 0x0404);
7680 
7681 		ocp_reg_write(tp, 0xbf4a, 0x001b);
7682 		ocp_reg_write(tp, 0xb87c, 0x8033);
7683 		ocp_reg_write(tp, 0xb87e, 0x7c13);
7684 		ocp_reg_write(tp, 0xb87c, 0x8037);
7685 		ocp_reg_write(tp, 0xb87e, 0x7c13);
7686 		ocp_reg_write(tp, 0xb87c, 0x803b);
7687 		ocp_reg_write(tp, 0xb87e, 0xfc32);
7688 		ocp_reg_write(tp, 0xb87c, 0x803f);
7689 		ocp_reg_write(tp, 0xb87e, 0x7c13);
7690 		ocp_reg_write(tp, 0xb87c, 0x8043);
7691 		ocp_reg_write(tp, 0xb87e, 0x7c13);
7692 		ocp_reg_write(tp, 0xb87c, 0x8047);
7693 		ocp_reg_write(tp, 0xb87e, 0x7c13);
7694 
7695 		ocp_reg_write(tp, 0xb87c, 0x8145);
7696 		ocp_reg_write(tp, 0xb87e, 0x370e);
7697 		ocp_reg_write(tp, 0xb87c, 0x8157);
7698 		ocp_reg_write(tp, 0xb87e, 0x770e);
7699 		ocp_reg_write(tp, 0xb87c, 0x8169);
7700 		ocp_reg_write(tp, 0xb87e, 0x0d0a);
7701 		ocp_reg_write(tp, 0xb87c, 0x817b);
7702 		ocp_reg_write(tp, 0xb87e, 0x1d0a);
7703 
7704 		data = sram_read(tp, 0x8217);
7705 		data &= ~0xff00;
7706 		data |= 0x5000;
7707 		sram_write(tp, 0x8217, data);
7708 		data = sram_read(tp, 0x821a);
7709 		data &= ~0xff00;
7710 		data |= 0x5000;
7711 		sram_write(tp, 0x821a, data);
7712 		sram_write(tp, 0x80da, 0x0403);
7713 		data = sram_read(tp, 0x80dc);
7714 		data &= ~0xff00;
7715 		data |= 0x1000;
7716 		sram_write(tp, 0x80dc, data);
7717 		sram_write(tp, 0x80b3, 0x0384);
7718 		sram_write(tp, 0x80b7, 0x2007);
7719 		data = sram_read(tp, 0x80ba);
7720 		data &= ~0xff00;
7721 		data |= 0x6c00;
7722 		sram_write(tp, 0x80ba, data);
7723 		sram_write(tp, 0x80b5, 0xf009);
7724 		data = sram_read(tp, 0x80bd);
7725 		data &= ~0xff00;
7726 		data |= 0x9f00;
7727 		sram_write(tp, 0x80bd, data);
7728 		sram_write(tp, 0x80c7, 0xf083);
7729 		sram_write(tp, 0x80dd, 0x03f0);
7730 		data = sram_read(tp, 0x80df);
7731 		data &= ~0xff00;
7732 		data |= 0x1000;
7733 		sram_write(tp, 0x80df, data);
7734 		sram_write(tp, 0x80cb, 0x2007);
7735 		data = sram_read(tp, 0x80ce);
7736 		data &= ~0xff00;
7737 		data |= 0x6c00;
7738 		sram_write(tp, 0x80ce, data);
7739 		sram_write(tp, 0x80c9, 0x8009);
7740 		data = sram_read(tp, 0x80d1);
7741 		data &= ~0xff00;
7742 		data |= 0x8000;
7743 		sram_write(tp, 0x80d1, data);
7744 		sram_write(tp, 0x80a3, 0x200a);
7745 		sram_write(tp, 0x80a5, 0xf0ad);
7746 		sram_write(tp, 0x809f, 0x6073);
7747 		sram_write(tp, 0x80a1, 0x000b);
7748 		data = sram_read(tp, 0x80a9);
7749 		data &= ~0xff00;
7750 		data |= 0xc000;
7751 		sram_write(tp, 0x80a9, data);
7752 
7753 		if (rtl_phy_patch_request(tp, true, true))
7754 			return;
7755 
7756 		data = ocp_reg_read(tp, 0xb896);
7757 		data &= ~BIT(0);
7758 		ocp_reg_write(tp, 0xb896, data);
7759 		data = ocp_reg_read(tp, 0xb892);
7760 		data &= ~0xff00;
7761 		ocp_reg_write(tp, 0xb892, data);
7762 		ocp_reg_write(tp, 0xb88e, 0xc23e);
7763 		ocp_reg_write(tp, 0xb890, 0x0000);
7764 		ocp_reg_write(tp, 0xb88e, 0xc240);
7765 		ocp_reg_write(tp, 0xb890, 0x0103);
7766 		ocp_reg_write(tp, 0xb88e, 0xc242);
7767 		ocp_reg_write(tp, 0xb890, 0x0507);
7768 		ocp_reg_write(tp, 0xb88e, 0xc244);
7769 		ocp_reg_write(tp, 0xb890, 0x090b);
7770 		ocp_reg_write(tp, 0xb88e, 0xc246);
7771 		ocp_reg_write(tp, 0xb890, 0x0c0e);
7772 		ocp_reg_write(tp, 0xb88e, 0xc248);
7773 		ocp_reg_write(tp, 0xb890, 0x1012);
7774 		ocp_reg_write(tp, 0xb88e, 0xc24a);
7775 		ocp_reg_write(tp, 0xb890, 0x1416);
7776 		data = ocp_reg_read(tp, 0xb896);
7777 		data |= BIT(0);
7778 		ocp_reg_write(tp, 0xb896, data);
7779 
7780 		rtl_phy_patch_request(tp, false, true);
7781 
7782 		data = ocp_reg_read(tp, 0xa86a);
7783 		data |= BIT(0);
7784 		ocp_reg_write(tp, 0xa86a, data);
7785 		data = ocp_reg_read(tp, 0xa6f0);
7786 		data |= BIT(0);
7787 		ocp_reg_write(tp, 0xa6f0, data);
7788 
7789 		ocp_reg_write(tp, 0xbfa0, 0xd70d);
7790 		ocp_reg_write(tp, 0xbfa2, 0x4100);
7791 		ocp_reg_write(tp, 0xbfa4, 0xe868);
7792 		ocp_reg_write(tp, 0xbfa6, 0xdc59);
7793 		ocp_reg_write(tp, 0xb54c, 0x3c18);
7794 		data = ocp_reg_read(tp, 0xbfa4);
7795 		data &= ~BIT(5);
7796 		ocp_reg_write(tp, 0xbfa4, data);
7797 		data = sram_read(tp, 0x817d);
7798 		data |= BIT(12);
7799 		sram_write(tp, 0x817d, data);
7800 		break;
7801 	case RTL_VER_13:
7802 		/* 2.5G INRX */
7803 		data = ocp_reg_read(tp, 0xac46);
7804 		data &= ~0x00f0;
7805 		data |= 0x0090;
7806 		ocp_reg_write(tp, 0xac46, data);
7807 		data = ocp_reg_read(tp, 0xad30);
7808 		data &= ~0x0003;
7809 		data |= 0x0001;
7810 		ocp_reg_write(tp, 0xad30, data);
7811 		fallthrough;
7812 	case RTL_VER_15:
7813 		/* EEE parameter */
7814 		ocp_reg_write(tp, 0xb87c, 0x80f5);
7815 		ocp_reg_write(tp, 0xb87e, 0x760e);
7816 		ocp_reg_write(tp, 0xb87c, 0x8107);
7817 		ocp_reg_write(tp, 0xb87e, 0x360e);
7818 		ocp_reg_write(tp, 0xb87c, 0x8551);
7819 		data = ocp_reg_read(tp, 0xb87e);
7820 		data &= ~0xff00;
7821 		data |= 0x0800;
7822 		ocp_reg_write(tp, 0xb87e, data);
7823 
7824 		/* ADC_PGA parameter */
7825 		data = ocp_reg_read(tp, 0xbf00);
7826 		data &= ~0xe000;
7827 		data |= 0xa000;
7828 		ocp_reg_write(tp, 0xbf00, data);
7829 		data = ocp_reg_read(tp, 0xbf46);
7830 		data &= ~0x0f00;
7831 		data |= 0x0300;
7832 		ocp_reg_write(tp, 0xbf46, data);
7833 
7834 		/* Green Table-PGA, 1G full viterbi */
7835 		sram_write(tp, 0x8044, 0x2417);
7836 		sram_write(tp, 0x804a, 0x2417);
7837 		sram_write(tp, 0x8050, 0x2417);
7838 		sram_write(tp, 0x8056, 0x2417);
7839 		sram_write(tp, 0x805c, 0x2417);
7840 		sram_write(tp, 0x8062, 0x2417);
7841 		sram_write(tp, 0x8068, 0x2417);
7842 		sram_write(tp, 0x806e, 0x2417);
7843 		sram_write(tp, 0x8074, 0x2417);
7844 		sram_write(tp, 0x807a, 0x2417);
7845 
7846 		/* XG PLL */
7847 		data = ocp_reg_read(tp, 0xbf84);
7848 		data &= ~0xe000;
7849 		data |= 0xa000;
7850 		ocp_reg_write(tp, 0xbf84, data);
7851 		break;
7852 	default:
7853 		break;
7854 	}
7855 
7856 	if (rtl_phy_patch_request(tp, true, true))
7857 		return;
7858 
7859 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7860 	ocp_data |= EEE_SPDWN_EN;
7861 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
7862 
7863 	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7864 	data &= ~(EN_EEE_100 | EN_EEE_1000);
7865 	data |= EN_10M_CLKDIV;
7866 	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7867 	tp->ups_info._10m_ckdiv = true;
7868 	tp->ups_info.eee_plloff_100 = false;
7869 	tp->ups_info.eee_plloff_giga = false;
7870 
7871 	data = ocp_reg_read(tp, OCP_POWER_CFG);
7872 	data &= ~EEE_CLKDIV_EN;
7873 	ocp_reg_write(tp, OCP_POWER_CFG, data);
7874 	tp->ups_info.eee_ckdiv = false;
7875 
7876 	rtl_phy_patch_request(tp, false, true);
7877 
7878 	rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7879 
7880 	data = ocp_reg_read(tp, 0xa428);
7881 	data &= ~BIT(9);
7882 	ocp_reg_write(tp, 0xa428, data);
7883 	data = ocp_reg_read(tp, 0xa5ea);
7884 	data &= ~BIT(0);
7885 	ocp_reg_write(tp, 0xa5ea, data);
7886 	tp->ups_info.lite_mode = 0;
7887 
7888 	if (tp->eee_en)
7889 		rtl_eee_enable(tp, true);
7890 
7891 	r8153_aldps_en(tp, true);
7892 	r8152b_enable_fc(tp);
7893 	r8153_u2p3en(tp, true);
7894 
7895 	set_bit(PHY_RESET, &tp->flags);
7896 }
7897 
7898 static void r8156_init(struct r8152 *tp)
7899 {
7900 	u32 ocp_data;
7901 	u16 data;
7902 	int i;
7903 
7904 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
7905 		return;
7906 
7907 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
7908 	ocp_data &= ~EN_ALL_SPEED;
7909 	ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
7910 
7911 	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
7912 
7913 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
7914 	ocp_data |= BYPASS_MAC_RESET;
7915 	ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
7916 
7917 	r8153b_u1u2en(tp, false);
7918 
7919 	for (i = 0; i < 500; i++) {
7920 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7921 		    AUTOLOAD_DONE)
7922 			break;
7923 
7924 		msleep(20);
7925 		if (test_bit(RTL8152_UNPLUG, &tp->flags))
7926 			return;
7927 	}
7928 
7929 	data = r8153_phy_status(tp, 0);
7930 	if (data == PHY_STAT_EXT_INIT) {
7931 		data = ocp_reg_read(tp, 0xa468);
7932 		data &= ~(BIT(3) | BIT(1));
7933 		ocp_reg_write(tp, 0xa468, data);
7934 	}
7935 
7936 	data = r8152_mdio_read(tp, MII_BMCR);
7937 	if (data & BMCR_PDOWN) {
7938 		data &= ~BMCR_PDOWN;
7939 		r8152_mdio_write(tp, MII_BMCR, data);
7940 	}
7941 
7942 	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7943 	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7944 
7945 	r8153_u2p3en(tp, false);
7946 
7947 	/* MSC timer = 0xfff * 8ms = 32760 ms */
7948 	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7949 
7950 	/* U1/U2/L1 idle timer. 500 us */
7951 	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
7952 
7953 	r8153b_power_cut_en(tp, false);
7954 	r8156_ups_en(tp, false);
7955 	r8153_queue_wake(tp, false);
7956 	rtl_runtime_suspend_enable(tp, false);
7957 
7958 	if (tp->udev->speed >= USB_SPEED_SUPER)
7959 		r8153b_u1u2en(tp, true);
7960 
7961 	usb_enable_lpm(tp->udev);
7962 
7963 	r8156_mac_clk_spd(tp, true);
7964 
7965 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7966 	ocp_data &= ~PLA_MCU_SPDWN_EN;
7967 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
7968 
7969 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7970 	if (rtl8152_get_speed(tp) & LINK_STATUS)
7971 		ocp_data |= CUR_LINK_OK;
7972 	else
7973 		ocp_data &= ~CUR_LINK_OK;
7974 	ocp_data |= POLL_LINK_CHG;
7975 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7976 
7977 	set_bit(GREEN_ETHERNET, &tp->flags);
7978 
7979 	/* rx aggregation */
7980 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7981 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7982 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7983 
7984 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
7985 	ocp_data |= ACT_ODMA;
7986 	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
7987 
7988 	rtl_tally_reset(tp);
7989 
7990 	tp->coalesce = 15000;	/* 15 us */
7991 }
7992 
7993 static void r8156b_init(struct r8152 *tp)
7994 {
7995 	u32 ocp_data;
7996 	u16 data;
7997 	int i;
7998 
7999 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
8000 		return;
8001 
8002 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8003 	ocp_data &= ~EN_ALL_SPEED;
8004 	ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
8005 
8006 	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
8007 
8008 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8009 	ocp_data |= BYPASS_MAC_RESET;
8010 	ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
8011 
8012 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
8013 	ocp_data |= RX_DETECT8;
8014 	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
8015 
8016 	r8153b_u1u2en(tp, false);
8017 
8018 	switch (tp->version) {
8019 	case RTL_VER_13:
8020 	case RTL_VER_15:
8021 		r8156b_wait_loading_flash(tp);
8022 		break;
8023 	default:
8024 		break;
8025 	}
8026 
8027 	for (i = 0; i < 500; i++) {
8028 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8029 		    AUTOLOAD_DONE)
8030 			break;
8031 
8032 		msleep(20);
8033 		if (test_bit(RTL8152_UNPLUG, &tp->flags))
8034 			return;
8035 	}
8036 
8037 	data = r8153_phy_status(tp, 0);
8038 	if (data == PHY_STAT_EXT_INIT) {
8039 		data = ocp_reg_read(tp, 0xa468);
8040 		data &= ~(BIT(3) | BIT(1));
8041 		ocp_reg_write(tp, 0xa468, data);
8042 
8043 		data = ocp_reg_read(tp, 0xa466);
8044 		data &= ~BIT(0);
8045 		ocp_reg_write(tp, 0xa466, data);
8046 	}
8047 
8048 	data = r8152_mdio_read(tp, MII_BMCR);
8049 	if (data & BMCR_PDOWN) {
8050 		data &= ~BMCR_PDOWN;
8051 		r8152_mdio_write(tp, MII_BMCR, data);
8052 	}
8053 
8054 	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8055 
8056 	r8153_u2p3en(tp, false);
8057 
8058 	/* MSC timer = 0xfff * 8ms = 32760 ms */
8059 	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
8060 
8061 	/* U1/U2/L1 idle timer. 500 us */
8062 	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
8063 
8064 	r8153b_power_cut_en(tp, false);
8065 	r8156_ups_en(tp, false);
8066 	r8153_queue_wake(tp, false);
8067 	rtl_runtime_suspend_enable(tp, false);
8068 
8069 	if (tp->udev->speed >= USB_SPEED_SUPER)
8070 		r8153b_u1u2en(tp, true);
8071 
8072 	usb_enable_lpm(tp->udev);
8073 
8074 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);
8075 	ocp_data &= ~SLOT_EN;
8076 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8077 
8078 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
8079 	ocp_data |= FLOW_CTRL_EN;
8080 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
8081 
8082 	/* enable fc timer and set timer to 600 ms. */
8083 	ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
8084 		       CTRL_TIMER_EN | (600 / 8));
8085 
8086 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
8087 	if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))
8088 		ocp_data |= FLOW_CTRL_PATCH_2;
8089 	ocp_data &= ~AUTO_SPEEDUP;
8090 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
8091 
8092 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
8093 	ocp_data |= FC_PATCH_TASK;
8094 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
8095 
8096 	r8156_mac_clk_spd(tp, true);
8097 
8098 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8099 	ocp_data &= ~PLA_MCU_SPDWN_EN;
8100 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
8101 
8102 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8103 	if (rtl8152_get_speed(tp) & LINK_STATUS)
8104 		ocp_data |= CUR_LINK_OK;
8105 	else
8106 		ocp_data &= ~CUR_LINK_OK;
8107 	ocp_data |= POLL_LINK_CHG;
8108 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8109 
8110 	set_bit(GREEN_ETHERNET, &tp->flags);
8111 
8112 	/* rx aggregation */
8113 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8114 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8115 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8116 
8117 	rtl_tally_reset(tp);
8118 
8119 	tp->coalesce = 15000;	/* 15 us */
8120 }
8121 
8122 static bool rtl_check_vendor_ok(struct usb_interface *intf)
8123 {
8124 	struct usb_host_interface *alt = intf->cur_altsetting;
8125 	struct usb_endpoint_descriptor *in, *out, *intr;
8126 
8127 	if (usb_find_common_endpoints(alt, &in, &out, &intr, NULL) < 0) {
8128 		dev_err(&intf->dev, "Expected endpoints are not found\n");
8129 		return false;
8130 	}
8131 
8132 	/* Check Rx endpoint address */
8133 	if (usb_endpoint_num(in) != 1) {
8134 		dev_err(&intf->dev, "Invalid Rx endpoint address\n");
8135 		return false;
8136 	}
8137 
8138 	/* Check Tx endpoint address */
8139 	if (usb_endpoint_num(out) != 2) {
8140 		dev_err(&intf->dev, "Invalid Tx endpoint address\n");
8141 		return false;
8142 	}
8143 
8144 	/* Check interrupt endpoint address */
8145 	if (usb_endpoint_num(intr) != 3) {
8146 		dev_err(&intf->dev, "Invalid interrupt endpoint address\n");
8147 		return false;
8148 	}
8149 
8150 	return true;
8151 }
8152 
8153 static bool rtl_vendor_mode(struct usb_interface *intf)
8154 {
8155 	struct usb_host_interface *alt = intf->cur_altsetting;
8156 	struct usb_device *udev;
8157 	struct usb_host_config *c;
8158 	int i, num_configs;
8159 
8160 	if (alt->desc.bInterfaceClass == USB_CLASS_VENDOR_SPEC)
8161 		return rtl_check_vendor_ok(intf);
8162 
8163 	/* The vendor mode is not always config #1, so to find it out. */
8164 	udev = interface_to_usbdev(intf);
8165 	c = udev->config;
8166 	num_configs = udev->descriptor.bNumConfigurations;
8167 	if (num_configs < 2)
8168 		return false;
8169 
8170 	for (i = 0; i < num_configs; (i++, c++)) {
8171 		struct usb_interface_descriptor	*desc = NULL;
8172 
8173 		if (c->desc.bNumInterfaces > 0)
8174 			desc = &c->intf_cache[0]->altsetting->desc;
8175 		else
8176 			continue;
8177 
8178 		if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC) {
8179 			usb_driver_set_configuration(udev, c->desc.bConfigurationValue);
8180 			break;
8181 		}
8182 	}
8183 
8184 	if (i == num_configs)
8185 		dev_err(&intf->dev, "Unexpected Device\n");
8186 
8187 	return false;
8188 }
8189 
8190 static int rtl8152_pre_reset(struct usb_interface *intf)
8191 {
8192 	struct r8152 *tp = usb_get_intfdata(intf);
8193 	struct net_device *netdev;
8194 
8195 	if (!tp)
8196 		return 0;
8197 
8198 	netdev = tp->netdev;
8199 	if (!netif_running(netdev))
8200 		return 0;
8201 
8202 	netif_stop_queue(netdev);
8203 	tasklet_disable(&tp->tx_tl);
8204 	clear_bit(WORK_ENABLE, &tp->flags);
8205 	usb_kill_urb(tp->intr_urb);
8206 	cancel_delayed_work_sync(&tp->schedule);
8207 	napi_disable(&tp->napi);
8208 	if (netif_carrier_ok(netdev)) {
8209 		mutex_lock(&tp->control);
8210 		tp->rtl_ops.disable(tp);
8211 		mutex_unlock(&tp->control);
8212 	}
8213 
8214 	return 0;
8215 }
8216 
8217 static int rtl8152_post_reset(struct usb_interface *intf)
8218 {
8219 	struct r8152 *tp = usb_get_intfdata(intf);
8220 	struct net_device *netdev;
8221 	struct sockaddr sa;
8222 
8223 	if (!tp)
8224 		return 0;
8225 
8226 	/* reset the MAC address in case of policy change */
8227 	if (determine_ethernet_addr(tp, &sa) >= 0) {
8228 		rtnl_lock();
8229 		dev_set_mac_address (tp->netdev, &sa, NULL);
8230 		rtnl_unlock();
8231 	}
8232 
8233 	netdev = tp->netdev;
8234 	if (!netif_running(netdev))
8235 		return 0;
8236 
8237 	set_bit(WORK_ENABLE, &tp->flags);
8238 	if (netif_carrier_ok(netdev)) {
8239 		mutex_lock(&tp->control);
8240 		tp->rtl_ops.enable(tp);
8241 		rtl_start_rx(tp);
8242 		_rtl8152_set_rx_mode(netdev);
8243 		mutex_unlock(&tp->control);
8244 	}
8245 
8246 	napi_enable(&tp->napi);
8247 	tasklet_enable(&tp->tx_tl);
8248 	netif_wake_queue(netdev);
8249 	usb_submit_urb(tp->intr_urb, GFP_KERNEL);
8250 
8251 	if (!list_empty(&tp->rx_done))
8252 		napi_schedule(&tp->napi);
8253 
8254 	return 0;
8255 }
8256 
8257 static bool delay_autosuspend(struct r8152 *tp)
8258 {
8259 	bool sw_linking = !!netif_carrier_ok(tp->netdev);
8260 	bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
8261 
8262 	/* This means a linking change occurs and the driver doesn't detect it,
8263 	 * yet. If the driver has disabled tx/rx and hw is linking on, the
8264 	 * device wouldn't wake up by receiving any packet.
8265 	 */
8266 	if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
8267 		return true;
8268 
8269 	/* If the linking down is occurred by nway, the device may miss the
8270 	 * linking change event. And it wouldn't wake when linking on.
8271 	 */
8272 	if (!sw_linking && tp->rtl_ops.in_nway(tp))
8273 		return true;
8274 	else if (!skb_queue_empty(&tp->tx_queue))
8275 		return true;
8276 	else
8277 		return false;
8278 }
8279 
8280 static int rtl8152_runtime_resume(struct r8152 *tp)
8281 {
8282 	struct net_device *netdev = tp->netdev;
8283 
8284 	if (netif_running(netdev) && netdev->flags & IFF_UP) {
8285 		struct napi_struct *napi = &tp->napi;
8286 
8287 		tp->rtl_ops.autosuspend_en(tp, false);
8288 		napi_disable(napi);
8289 		set_bit(WORK_ENABLE, &tp->flags);
8290 
8291 		if (netif_carrier_ok(netdev)) {
8292 			if (rtl8152_get_speed(tp) & LINK_STATUS) {
8293 				rtl_start_rx(tp);
8294 			} else {
8295 				netif_carrier_off(netdev);
8296 				tp->rtl_ops.disable(tp);
8297 				netif_info(tp, link, netdev, "linking down\n");
8298 			}
8299 		}
8300 
8301 		napi_enable(napi);
8302 		clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8303 		smp_mb__after_atomic();
8304 
8305 		if (!list_empty(&tp->rx_done))
8306 			napi_schedule(&tp->napi);
8307 
8308 		usb_submit_urb(tp->intr_urb, GFP_NOIO);
8309 	} else {
8310 		if (netdev->flags & IFF_UP)
8311 			tp->rtl_ops.autosuspend_en(tp, false);
8312 
8313 		clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8314 	}
8315 
8316 	return 0;
8317 }
8318 
8319 static int rtl8152_system_resume(struct r8152 *tp)
8320 {
8321 	struct net_device *netdev = tp->netdev;
8322 
8323 	netif_device_attach(netdev);
8324 
8325 	if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
8326 		tp->rtl_ops.up(tp);
8327 		netif_carrier_off(netdev);
8328 		set_bit(WORK_ENABLE, &tp->flags);
8329 		usb_submit_urb(tp->intr_urb, GFP_NOIO);
8330 	}
8331 
8332 	return 0;
8333 }
8334 
8335 static int rtl8152_runtime_suspend(struct r8152 *tp)
8336 {
8337 	struct net_device *netdev = tp->netdev;
8338 	int ret = 0;
8339 
8340 	if (!tp->rtl_ops.autosuspend_en)
8341 		return -EBUSY;
8342 
8343 	set_bit(SELECTIVE_SUSPEND, &tp->flags);
8344 	smp_mb__after_atomic();
8345 
8346 	if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8347 		u32 rcr = 0;
8348 
8349 		if (netif_carrier_ok(netdev)) {
8350 			u32 ocp_data;
8351 
8352 			rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
8353 			ocp_data = rcr & ~RCR_ACPT_ALL;
8354 			ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8355 			rxdy_gated_en(tp, true);
8356 			ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
8357 						 PLA_OOB_CTRL);
8358 			if (!(ocp_data & RXFIFO_EMPTY)) {
8359 				rxdy_gated_en(tp, false);
8360 				ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8361 				clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8362 				smp_mb__after_atomic();
8363 				ret = -EBUSY;
8364 				goto out1;
8365 			}
8366 		}
8367 
8368 		clear_bit(WORK_ENABLE, &tp->flags);
8369 		usb_kill_urb(tp->intr_urb);
8370 
8371 		tp->rtl_ops.autosuspend_en(tp, true);
8372 
8373 		if (netif_carrier_ok(netdev)) {
8374 			struct napi_struct *napi = &tp->napi;
8375 
8376 			napi_disable(napi);
8377 			rtl_stop_rx(tp);
8378 			rxdy_gated_en(tp, false);
8379 			ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8380 			napi_enable(napi);
8381 		}
8382 
8383 		if (delay_autosuspend(tp)) {
8384 			rtl8152_runtime_resume(tp);
8385 			ret = -EBUSY;
8386 		}
8387 	}
8388 
8389 out1:
8390 	return ret;
8391 }
8392 
8393 static int rtl8152_system_suspend(struct r8152 *tp)
8394 {
8395 	struct net_device *netdev = tp->netdev;
8396 
8397 	netif_device_detach(netdev);
8398 
8399 	if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8400 		struct napi_struct *napi = &tp->napi;
8401 
8402 		clear_bit(WORK_ENABLE, &tp->flags);
8403 		usb_kill_urb(tp->intr_urb);
8404 		tasklet_disable(&tp->tx_tl);
8405 		napi_disable(napi);
8406 		cancel_delayed_work_sync(&tp->schedule);
8407 		tp->rtl_ops.down(tp);
8408 		napi_enable(napi);
8409 		tasklet_enable(&tp->tx_tl);
8410 	}
8411 
8412 	return 0;
8413 }
8414 
8415 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
8416 {
8417 	struct r8152 *tp = usb_get_intfdata(intf);
8418 	int ret;
8419 
8420 	mutex_lock(&tp->control);
8421 
8422 	if (PMSG_IS_AUTO(message))
8423 		ret = rtl8152_runtime_suspend(tp);
8424 	else
8425 		ret = rtl8152_system_suspend(tp);
8426 
8427 	mutex_unlock(&tp->control);
8428 
8429 	return ret;
8430 }
8431 
8432 static int rtl8152_resume(struct usb_interface *intf)
8433 {
8434 	struct r8152 *tp = usb_get_intfdata(intf);
8435 	int ret;
8436 
8437 	mutex_lock(&tp->control);
8438 
8439 	if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
8440 		ret = rtl8152_runtime_resume(tp);
8441 	else
8442 		ret = rtl8152_system_resume(tp);
8443 
8444 	mutex_unlock(&tp->control);
8445 
8446 	return ret;
8447 }
8448 
8449 static int rtl8152_reset_resume(struct usb_interface *intf)
8450 {
8451 	struct r8152 *tp = usb_get_intfdata(intf);
8452 
8453 	clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8454 	tp->rtl_ops.init(tp);
8455 	queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
8456 	set_ethernet_addr(tp, true);
8457 	return rtl8152_resume(intf);
8458 }
8459 
8460 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8461 {
8462 	struct r8152 *tp = netdev_priv(dev);
8463 
8464 	if (usb_autopm_get_interface(tp->intf) < 0)
8465 		return;
8466 
8467 	if (!rtl_can_wakeup(tp)) {
8468 		wol->supported = 0;
8469 		wol->wolopts = 0;
8470 	} else {
8471 		mutex_lock(&tp->control);
8472 		wol->supported = WAKE_ANY;
8473 		wol->wolopts = __rtl_get_wol(tp);
8474 		mutex_unlock(&tp->control);
8475 	}
8476 
8477 	usb_autopm_put_interface(tp->intf);
8478 }
8479 
8480 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8481 {
8482 	struct r8152 *tp = netdev_priv(dev);
8483 	int ret;
8484 
8485 	if (!rtl_can_wakeup(tp))
8486 		return -EOPNOTSUPP;
8487 
8488 	if (wol->wolopts & ~WAKE_ANY)
8489 		return -EINVAL;
8490 
8491 	ret = usb_autopm_get_interface(tp->intf);
8492 	if (ret < 0)
8493 		goto out_set_wol;
8494 
8495 	mutex_lock(&tp->control);
8496 
8497 	__rtl_set_wol(tp, wol->wolopts);
8498 	tp->saved_wolopts = wol->wolopts & WAKE_ANY;
8499 
8500 	mutex_unlock(&tp->control);
8501 
8502 	usb_autopm_put_interface(tp->intf);
8503 
8504 out_set_wol:
8505 	return ret;
8506 }
8507 
8508 static u32 rtl8152_get_msglevel(struct net_device *dev)
8509 {
8510 	struct r8152 *tp = netdev_priv(dev);
8511 
8512 	return tp->msg_enable;
8513 }
8514 
8515 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
8516 {
8517 	struct r8152 *tp = netdev_priv(dev);
8518 
8519 	tp->msg_enable = value;
8520 }
8521 
8522 static void rtl8152_get_drvinfo(struct net_device *netdev,
8523 				struct ethtool_drvinfo *info)
8524 {
8525 	struct r8152 *tp = netdev_priv(netdev);
8526 
8527 	strlcpy(info->driver, MODULENAME, sizeof(info->driver));
8528 	strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
8529 	usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
8530 	if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
8531 		strlcpy(info->fw_version, tp->rtl_fw.version,
8532 			sizeof(info->fw_version));
8533 }
8534 
8535 static
8536 int rtl8152_get_link_ksettings(struct net_device *netdev,
8537 			       struct ethtool_link_ksettings *cmd)
8538 {
8539 	struct r8152 *tp = netdev_priv(netdev);
8540 	int ret;
8541 
8542 	if (!tp->mii.mdio_read)
8543 		return -EOPNOTSUPP;
8544 
8545 	ret = usb_autopm_get_interface(tp->intf);
8546 	if (ret < 0)
8547 		goto out;
8548 
8549 	mutex_lock(&tp->control);
8550 
8551 	mii_ethtool_get_link_ksettings(&tp->mii, cmd);
8552 
8553 	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8554 			 cmd->link_modes.supported, tp->support_2500full);
8555 
8556 	if (tp->support_2500full) {
8557 		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8558 				 cmd->link_modes.advertising,
8559 				 ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);
8560 
8561 		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8562 				 cmd->link_modes.lp_advertising,
8563 				 ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);
8564 
8565 		if (is_speed_2500(rtl8152_get_speed(tp)))
8566 			cmd->base.speed = SPEED_2500;
8567 	}
8568 
8569 	mutex_unlock(&tp->control);
8570 
8571 	usb_autopm_put_interface(tp->intf);
8572 
8573 out:
8574 	return ret;
8575 }
8576 
8577 static int rtl8152_set_link_ksettings(struct net_device *dev,
8578 				      const struct ethtool_link_ksettings *cmd)
8579 {
8580 	struct r8152 *tp = netdev_priv(dev);
8581 	u32 advertising = 0;
8582 	int ret;
8583 
8584 	ret = usb_autopm_get_interface(tp->intf);
8585 	if (ret < 0)
8586 		goto out;
8587 
8588 	if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
8589 		     cmd->link_modes.advertising))
8590 		advertising |= RTL_ADVERTISED_10_HALF;
8591 
8592 	if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
8593 		     cmd->link_modes.advertising))
8594 		advertising |= RTL_ADVERTISED_10_FULL;
8595 
8596 	if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
8597 		     cmd->link_modes.advertising))
8598 		advertising |= RTL_ADVERTISED_100_HALF;
8599 
8600 	if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
8601 		     cmd->link_modes.advertising))
8602 		advertising |= RTL_ADVERTISED_100_FULL;
8603 
8604 	if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
8605 		     cmd->link_modes.advertising))
8606 		advertising |= RTL_ADVERTISED_1000_HALF;
8607 
8608 	if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
8609 		     cmd->link_modes.advertising))
8610 		advertising |= RTL_ADVERTISED_1000_FULL;
8611 
8612 	if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8613 		     cmd->link_modes.advertising))
8614 		advertising |= RTL_ADVERTISED_2500_FULL;
8615 
8616 	mutex_lock(&tp->control);
8617 
8618 	ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
8619 				cmd->base.duplex, advertising);
8620 	if (!ret) {
8621 		tp->autoneg = cmd->base.autoneg;
8622 		tp->speed = cmd->base.speed;
8623 		tp->duplex = cmd->base.duplex;
8624 		tp->advertising = advertising;
8625 	}
8626 
8627 	mutex_unlock(&tp->control);
8628 
8629 	usb_autopm_put_interface(tp->intf);
8630 
8631 out:
8632 	return ret;
8633 }
8634 
8635 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
8636 	"tx_packets",
8637 	"rx_packets",
8638 	"tx_errors",
8639 	"rx_errors",
8640 	"rx_missed",
8641 	"align_errors",
8642 	"tx_single_collisions",
8643 	"tx_multi_collisions",
8644 	"rx_unicast",
8645 	"rx_broadcast",
8646 	"rx_multicast",
8647 	"tx_aborted",
8648 	"tx_underrun",
8649 };
8650 
8651 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
8652 {
8653 	switch (sset) {
8654 	case ETH_SS_STATS:
8655 		return ARRAY_SIZE(rtl8152_gstrings);
8656 	default:
8657 		return -EOPNOTSUPP;
8658 	}
8659 }
8660 
8661 static void rtl8152_get_ethtool_stats(struct net_device *dev,
8662 				      struct ethtool_stats *stats, u64 *data)
8663 {
8664 	struct r8152 *tp = netdev_priv(dev);
8665 	struct tally_counter tally;
8666 
8667 	if (usb_autopm_get_interface(tp->intf) < 0)
8668 		return;
8669 
8670 	generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
8671 
8672 	usb_autopm_put_interface(tp->intf);
8673 
8674 	data[0] = le64_to_cpu(tally.tx_packets);
8675 	data[1] = le64_to_cpu(tally.rx_packets);
8676 	data[2] = le64_to_cpu(tally.tx_errors);
8677 	data[3] = le32_to_cpu(tally.rx_errors);
8678 	data[4] = le16_to_cpu(tally.rx_missed);
8679 	data[5] = le16_to_cpu(tally.align_errors);
8680 	data[6] = le32_to_cpu(tally.tx_one_collision);
8681 	data[7] = le32_to_cpu(tally.tx_multi_collision);
8682 	data[8] = le64_to_cpu(tally.rx_unicast);
8683 	data[9] = le64_to_cpu(tally.rx_broadcast);
8684 	data[10] = le32_to_cpu(tally.rx_multicast);
8685 	data[11] = le16_to_cpu(tally.tx_aborted);
8686 	data[12] = le16_to_cpu(tally.tx_underrun);
8687 }
8688 
8689 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
8690 {
8691 	switch (stringset) {
8692 	case ETH_SS_STATS:
8693 		memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
8694 		break;
8695 	}
8696 }
8697 
8698 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8699 {
8700 	u32 lp, adv, supported = 0;
8701 	u16 val;
8702 
8703 	val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
8704 	supported = mmd_eee_cap_to_ethtool_sup_t(val);
8705 
8706 	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
8707 	adv = mmd_eee_adv_to_ethtool_adv_t(val);
8708 
8709 	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
8710 	lp = mmd_eee_adv_to_ethtool_adv_t(val);
8711 
8712 	eee->eee_enabled = tp->eee_en;
8713 	eee->eee_active = !!(supported & adv & lp);
8714 	eee->supported = supported;
8715 	eee->advertised = tp->eee_adv;
8716 	eee->lp_advertised = lp;
8717 
8718 	return 0;
8719 }
8720 
8721 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
8722 {
8723 	u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
8724 
8725 	tp->eee_en = eee->eee_enabled;
8726 	tp->eee_adv = val;
8727 
8728 	rtl_eee_enable(tp, tp->eee_en);
8729 
8730 	return 0;
8731 }
8732 
8733 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8734 {
8735 	u32 lp, adv, supported = 0;
8736 	u16 val;
8737 
8738 	val = ocp_reg_read(tp, OCP_EEE_ABLE);
8739 	supported = mmd_eee_cap_to_ethtool_sup_t(val);
8740 
8741 	val = ocp_reg_read(tp, OCP_EEE_ADV);
8742 	adv = mmd_eee_adv_to_ethtool_adv_t(val);
8743 
8744 	val = ocp_reg_read(tp, OCP_EEE_LPABLE);
8745 	lp = mmd_eee_adv_to_ethtool_adv_t(val);
8746 
8747 	eee->eee_enabled = tp->eee_en;
8748 	eee->eee_active = !!(supported & adv & lp);
8749 	eee->supported = supported;
8750 	eee->advertised = tp->eee_adv;
8751 	eee->lp_advertised = lp;
8752 
8753 	return 0;
8754 }
8755 
8756 static int
8757 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
8758 {
8759 	struct r8152 *tp = netdev_priv(net);
8760 	int ret;
8761 
8762 	if (!tp->rtl_ops.eee_get) {
8763 		ret = -EOPNOTSUPP;
8764 		goto out;
8765 	}
8766 
8767 	ret = usb_autopm_get_interface(tp->intf);
8768 	if (ret < 0)
8769 		goto out;
8770 
8771 	mutex_lock(&tp->control);
8772 
8773 	ret = tp->rtl_ops.eee_get(tp, edata);
8774 
8775 	mutex_unlock(&tp->control);
8776 
8777 	usb_autopm_put_interface(tp->intf);
8778 
8779 out:
8780 	return ret;
8781 }
8782 
8783 static int
8784 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
8785 {
8786 	struct r8152 *tp = netdev_priv(net);
8787 	int ret;
8788 
8789 	if (!tp->rtl_ops.eee_set) {
8790 		ret = -EOPNOTSUPP;
8791 		goto out;
8792 	}
8793 
8794 	ret = usb_autopm_get_interface(tp->intf);
8795 	if (ret < 0)
8796 		goto out;
8797 
8798 	mutex_lock(&tp->control);
8799 
8800 	ret = tp->rtl_ops.eee_set(tp, edata);
8801 	if (!ret)
8802 		ret = mii_nway_restart(&tp->mii);
8803 
8804 	mutex_unlock(&tp->control);
8805 
8806 	usb_autopm_put_interface(tp->intf);
8807 
8808 out:
8809 	return ret;
8810 }
8811 
8812 static int rtl8152_nway_reset(struct net_device *dev)
8813 {
8814 	struct r8152 *tp = netdev_priv(dev);
8815 	int ret;
8816 
8817 	ret = usb_autopm_get_interface(tp->intf);
8818 	if (ret < 0)
8819 		goto out;
8820 
8821 	mutex_lock(&tp->control);
8822 
8823 	ret = mii_nway_restart(&tp->mii);
8824 
8825 	mutex_unlock(&tp->control);
8826 
8827 	usb_autopm_put_interface(tp->intf);
8828 
8829 out:
8830 	return ret;
8831 }
8832 
8833 static int rtl8152_get_coalesce(struct net_device *netdev,
8834 				struct ethtool_coalesce *coalesce)
8835 {
8836 	struct r8152 *tp = netdev_priv(netdev);
8837 
8838 	switch (tp->version) {
8839 	case RTL_VER_01:
8840 	case RTL_VER_02:
8841 	case RTL_VER_07:
8842 		return -EOPNOTSUPP;
8843 	default:
8844 		break;
8845 	}
8846 
8847 	coalesce->rx_coalesce_usecs = tp->coalesce;
8848 
8849 	return 0;
8850 }
8851 
8852 static int rtl8152_set_coalesce(struct net_device *netdev,
8853 				struct ethtool_coalesce *coalesce)
8854 {
8855 	struct r8152 *tp = netdev_priv(netdev);
8856 	int ret;
8857 
8858 	switch (tp->version) {
8859 	case RTL_VER_01:
8860 	case RTL_VER_02:
8861 	case RTL_VER_07:
8862 		return -EOPNOTSUPP;
8863 	default:
8864 		break;
8865 	}
8866 
8867 	if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
8868 		return -EINVAL;
8869 
8870 	ret = usb_autopm_get_interface(tp->intf);
8871 	if (ret < 0)
8872 		return ret;
8873 
8874 	mutex_lock(&tp->control);
8875 
8876 	if (tp->coalesce != coalesce->rx_coalesce_usecs) {
8877 		tp->coalesce = coalesce->rx_coalesce_usecs;
8878 
8879 		if (netif_running(netdev) && netif_carrier_ok(netdev)) {
8880 			netif_stop_queue(netdev);
8881 			napi_disable(&tp->napi);
8882 			tp->rtl_ops.disable(tp);
8883 			tp->rtl_ops.enable(tp);
8884 			rtl_start_rx(tp);
8885 			clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
8886 			_rtl8152_set_rx_mode(netdev);
8887 			napi_enable(&tp->napi);
8888 			netif_wake_queue(netdev);
8889 		}
8890 	}
8891 
8892 	mutex_unlock(&tp->control);
8893 
8894 	usb_autopm_put_interface(tp->intf);
8895 
8896 	return ret;
8897 }
8898 
8899 static int rtl8152_get_tunable(struct net_device *netdev,
8900 			       const struct ethtool_tunable *tunable, void *d)
8901 {
8902 	struct r8152 *tp = netdev_priv(netdev);
8903 
8904 	switch (tunable->id) {
8905 	case ETHTOOL_RX_COPYBREAK:
8906 		*(u32 *)d = tp->rx_copybreak;
8907 		break;
8908 	default:
8909 		return -EOPNOTSUPP;
8910 	}
8911 
8912 	return 0;
8913 }
8914 
8915 static int rtl8152_set_tunable(struct net_device *netdev,
8916 			       const struct ethtool_tunable *tunable,
8917 			       const void *d)
8918 {
8919 	struct r8152 *tp = netdev_priv(netdev);
8920 	u32 val;
8921 
8922 	switch (tunable->id) {
8923 	case ETHTOOL_RX_COPYBREAK:
8924 		val = *(u32 *)d;
8925 		if (val < ETH_ZLEN) {
8926 			netif_err(tp, rx_err, netdev,
8927 				  "Invalid rx copy break value\n");
8928 			return -EINVAL;
8929 		}
8930 
8931 		if (tp->rx_copybreak != val) {
8932 			if (netdev->flags & IFF_UP) {
8933 				mutex_lock(&tp->control);
8934 				napi_disable(&tp->napi);
8935 				tp->rx_copybreak = val;
8936 				napi_enable(&tp->napi);
8937 				mutex_unlock(&tp->control);
8938 			} else {
8939 				tp->rx_copybreak = val;
8940 			}
8941 		}
8942 		break;
8943 	default:
8944 		return -EOPNOTSUPP;
8945 	}
8946 
8947 	return 0;
8948 }
8949 
8950 static void rtl8152_get_ringparam(struct net_device *netdev,
8951 				  struct ethtool_ringparam *ring)
8952 {
8953 	struct r8152 *tp = netdev_priv(netdev);
8954 
8955 	ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
8956 	ring->rx_pending = tp->rx_pending;
8957 }
8958 
8959 static int rtl8152_set_ringparam(struct net_device *netdev,
8960 				 struct ethtool_ringparam *ring)
8961 {
8962 	struct r8152 *tp = netdev_priv(netdev);
8963 
8964 	if (ring->rx_pending < (RTL8152_MAX_RX * 2))
8965 		return -EINVAL;
8966 
8967 	if (tp->rx_pending != ring->rx_pending) {
8968 		if (netdev->flags & IFF_UP) {
8969 			mutex_lock(&tp->control);
8970 			napi_disable(&tp->napi);
8971 			tp->rx_pending = ring->rx_pending;
8972 			napi_enable(&tp->napi);
8973 			mutex_unlock(&tp->control);
8974 		} else {
8975 			tp->rx_pending = ring->rx_pending;
8976 		}
8977 	}
8978 
8979 	return 0;
8980 }
8981 
8982 static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
8983 {
8984 	struct r8152 *tp = netdev_priv(netdev);
8985 	u16 bmcr, lcladv, rmtadv;
8986 	u8 cap;
8987 
8988 	if (usb_autopm_get_interface(tp->intf) < 0)
8989 		return;
8990 
8991 	mutex_lock(&tp->control);
8992 
8993 	bmcr = r8152_mdio_read(tp, MII_BMCR);
8994 	lcladv = r8152_mdio_read(tp, MII_ADVERTISE);
8995 	rmtadv = r8152_mdio_read(tp, MII_LPA);
8996 
8997 	mutex_unlock(&tp->control);
8998 
8999 	usb_autopm_put_interface(tp->intf);
9000 
9001 	if (!(bmcr & BMCR_ANENABLE)) {
9002 		pause->autoneg = 0;
9003 		pause->rx_pause = 0;
9004 		pause->tx_pause = 0;
9005 		return;
9006 	}
9007 
9008 	pause->autoneg = 1;
9009 
9010 	cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
9011 
9012 	if (cap & FLOW_CTRL_RX)
9013 		pause->rx_pause = 1;
9014 
9015 	if (cap & FLOW_CTRL_TX)
9016 		pause->tx_pause = 1;
9017 }
9018 
9019 static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9020 {
9021 	struct r8152 *tp = netdev_priv(netdev);
9022 	u16 old, new1;
9023 	u8 cap = 0;
9024 	int ret;
9025 
9026 	ret = usb_autopm_get_interface(tp->intf);
9027 	if (ret < 0)
9028 		return ret;
9029 
9030 	mutex_lock(&tp->control);
9031 
9032 	if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) {
9033 		ret = -EINVAL;
9034 		goto out;
9035 	}
9036 
9037 	if (pause->rx_pause)
9038 		cap |= FLOW_CTRL_RX;
9039 
9040 	if (pause->tx_pause)
9041 		cap |= FLOW_CTRL_TX;
9042 
9043 	old = r8152_mdio_read(tp, MII_ADVERTISE);
9044 	new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap);
9045 	if (old != new1)
9046 		r8152_mdio_write(tp, MII_ADVERTISE, new1);
9047 
9048 out:
9049 	mutex_unlock(&tp->control);
9050 	usb_autopm_put_interface(tp->intf);
9051 
9052 	return ret;
9053 }
9054 
9055 static const struct ethtool_ops ops = {
9056 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS,
9057 	.get_drvinfo = rtl8152_get_drvinfo,
9058 	.get_link = ethtool_op_get_link,
9059 	.nway_reset = rtl8152_nway_reset,
9060 	.get_msglevel = rtl8152_get_msglevel,
9061 	.set_msglevel = rtl8152_set_msglevel,
9062 	.get_wol = rtl8152_get_wol,
9063 	.set_wol = rtl8152_set_wol,
9064 	.get_strings = rtl8152_get_strings,
9065 	.get_sset_count = rtl8152_get_sset_count,
9066 	.get_ethtool_stats = rtl8152_get_ethtool_stats,
9067 	.get_coalesce = rtl8152_get_coalesce,
9068 	.set_coalesce = rtl8152_set_coalesce,
9069 	.get_eee = rtl_ethtool_get_eee,
9070 	.set_eee = rtl_ethtool_set_eee,
9071 	.get_link_ksettings = rtl8152_get_link_ksettings,
9072 	.set_link_ksettings = rtl8152_set_link_ksettings,
9073 	.get_tunable = rtl8152_get_tunable,
9074 	.set_tunable = rtl8152_set_tunable,
9075 	.get_ringparam = rtl8152_get_ringparam,
9076 	.set_ringparam = rtl8152_set_ringparam,
9077 	.get_pauseparam = rtl8152_get_pauseparam,
9078 	.set_pauseparam = rtl8152_set_pauseparam,
9079 };
9080 
9081 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
9082 {
9083 	struct r8152 *tp = netdev_priv(netdev);
9084 	struct mii_ioctl_data *data = if_mii(rq);
9085 	int res;
9086 
9087 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
9088 		return -ENODEV;
9089 
9090 	res = usb_autopm_get_interface(tp->intf);
9091 	if (res < 0)
9092 		goto out;
9093 
9094 	switch (cmd) {
9095 	case SIOCGMIIPHY:
9096 		data->phy_id = R8152_PHY_ID; /* Internal PHY */
9097 		break;
9098 
9099 	case SIOCGMIIREG:
9100 		mutex_lock(&tp->control);
9101 		data->val_out = r8152_mdio_read(tp, data->reg_num);
9102 		mutex_unlock(&tp->control);
9103 		break;
9104 
9105 	case SIOCSMIIREG:
9106 		if (!capable(CAP_NET_ADMIN)) {
9107 			res = -EPERM;
9108 			break;
9109 		}
9110 		mutex_lock(&tp->control);
9111 		r8152_mdio_write(tp, data->reg_num, data->val_in);
9112 		mutex_unlock(&tp->control);
9113 		break;
9114 
9115 	default:
9116 		res = -EOPNOTSUPP;
9117 	}
9118 
9119 	usb_autopm_put_interface(tp->intf);
9120 
9121 out:
9122 	return res;
9123 }
9124 
9125 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
9126 {
9127 	struct r8152 *tp = netdev_priv(dev);
9128 	int ret;
9129 
9130 	switch (tp->version) {
9131 	case RTL_VER_01:
9132 	case RTL_VER_02:
9133 	case RTL_VER_07:
9134 		dev->mtu = new_mtu;
9135 		return 0;
9136 	default:
9137 		break;
9138 	}
9139 
9140 	ret = usb_autopm_get_interface(tp->intf);
9141 	if (ret < 0)
9142 		return ret;
9143 
9144 	mutex_lock(&tp->control);
9145 
9146 	dev->mtu = new_mtu;
9147 
9148 	if (netif_running(dev)) {
9149 		if (tp->rtl_ops.change_mtu)
9150 			tp->rtl_ops.change_mtu(tp);
9151 
9152 		if (netif_carrier_ok(dev)) {
9153 			netif_stop_queue(dev);
9154 			napi_disable(&tp->napi);
9155 			tasklet_disable(&tp->tx_tl);
9156 			tp->rtl_ops.disable(tp);
9157 			tp->rtl_ops.enable(tp);
9158 			rtl_start_rx(tp);
9159 			tasklet_enable(&tp->tx_tl);
9160 			napi_enable(&tp->napi);
9161 			rtl8152_set_rx_mode(dev);
9162 			netif_wake_queue(dev);
9163 		}
9164 	}
9165 
9166 	mutex_unlock(&tp->control);
9167 
9168 	usb_autopm_put_interface(tp->intf);
9169 
9170 	return ret;
9171 }
9172 
9173 static const struct net_device_ops rtl8152_netdev_ops = {
9174 	.ndo_open		= rtl8152_open,
9175 	.ndo_stop		= rtl8152_close,
9176 	.ndo_do_ioctl		= rtl8152_ioctl,
9177 	.ndo_start_xmit		= rtl8152_start_xmit,
9178 	.ndo_tx_timeout		= rtl8152_tx_timeout,
9179 	.ndo_set_features	= rtl8152_set_features,
9180 	.ndo_set_rx_mode	= rtl8152_set_rx_mode,
9181 	.ndo_set_mac_address	= rtl8152_set_mac_address,
9182 	.ndo_change_mtu		= rtl8152_change_mtu,
9183 	.ndo_validate_addr	= eth_validate_addr,
9184 	.ndo_features_check	= rtl8152_features_check,
9185 };
9186 
9187 static void rtl8152_unload(struct r8152 *tp)
9188 {
9189 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
9190 		return;
9191 
9192 	if (tp->version != RTL_VER_01)
9193 		r8152_power_cut_en(tp, true);
9194 }
9195 
9196 static void rtl8153_unload(struct r8152 *tp)
9197 {
9198 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
9199 		return;
9200 
9201 	r8153_power_cut_en(tp, false);
9202 }
9203 
9204 static void rtl8153b_unload(struct r8152 *tp)
9205 {
9206 	if (test_bit(RTL8152_UNPLUG, &tp->flags))
9207 		return;
9208 
9209 	r8153b_power_cut_en(tp, false);
9210 }
9211 
9212 static int rtl_ops_init(struct r8152 *tp)
9213 {
9214 	struct rtl_ops *ops = &tp->rtl_ops;
9215 	int ret = 0;
9216 
9217 	switch (tp->version) {
9218 	case RTL_VER_01:
9219 	case RTL_VER_02:
9220 	case RTL_VER_07:
9221 		ops->init		= r8152b_init;
9222 		ops->enable		= rtl8152_enable;
9223 		ops->disable		= rtl8152_disable;
9224 		ops->up			= rtl8152_up;
9225 		ops->down		= rtl8152_down;
9226 		ops->unload		= rtl8152_unload;
9227 		ops->eee_get		= r8152_get_eee;
9228 		ops->eee_set		= r8152_set_eee;
9229 		ops->in_nway		= rtl8152_in_nway;
9230 		ops->hw_phy_cfg		= r8152b_hw_phy_cfg;
9231 		ops->autosuspend_en	= rtl_runtime_suspend_enable;
9232 		tp->rx_buf_sz		= 16 * 1024;
9233 		tp->eee_en		= true;
9234 		tp->eee_adv		= MDIO_EEE_100TX;
9235 		break;
9236 
9237 	case RTL_VER_03:
9238 	case RTL_VER_04:
9239 	case RTL_VER_05:
9240 	case RTL_VER_06:
9241 		ops->init		= r8153_init;
9242 		ops->enable		= rtl8153_enable;
9243 		ops->disable		= rtl8153_disable;
9244 		ops->up			= rtl8153_up;
9245 		ops->down		= rtl8153_down;
9246 		ops->unload		= rtl8153_unload;
9247 		ops->eee_get		= r8153_get_eee;
9248 		ops->eee_set		= r8152_set_eee;
9249 		ops->in_nway		= rtl8153_in_nway;
9250 		ops->hw_phy_cfg		= r8153_hw_phy_cfg;
9251 		ops->autosuspend_en	= rtl8153_runtime_enable;
9252 		ops->change_mtu		= rtl8153_change_mtu;
9253 		if (tp->udev->speed < USB_SPEED_SUPER)
9254 			tp->rx_buf_sz	= 16 * 1024;
9255 		else
9256 			tp->rx_buf_sz	= 32 * 1024;
9257 		tp->eee_en		= true;
9258 		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
9259 		break;
9260 
9261 	case RTL_VER_08:
9262 	case RTL_VER_09:
9263 		ops->init		= r8153b_init;
9264 		ops->enable		= rtl8153_enable;
9265 		ops->disable		= rtl8153_disable;
9266 		ops->up			= rtl8153b_up;
9267 		ops->down		= rtl8153b_down;
9268 		ops->unload		= rtl8153b_unload;
9269 		ops->eee_get		= r8153_get_eee;
9270 		ops->eee_set		= r8152_set_eee;
9271 		ops->in_nway		= rtl8153_in_nway;
9272 		ops->hw_phy_cfg		= r8153b_hw_phy_cfg;
9273 		ops->autosuspend_en	= rtl8153b_runtime_enable;
9274 		ops->change_mtu		= rtl8153_change_mtu;
9275 		tp->rx_buf_sz		= 32 * 1024;
9276 		tp->eee_en		= true;
9277 		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
9278 		break;
9279 
9280 	case RTL_VER_11:
9281 		tp->eee_en		= true;
9282 		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
9283 		fallthrough;
9284 	case RTL_VER_10:
9285 		ops->init		= r8156_init;
9286 		ops->enable		= rtl8156_enable;
9287 		ops->disable		= rtl8153_disable;
9288 		ops->up			= rtl8156_up;
9289 		ops->down		= rtl8156_down;
9290 		ops->unload		= rtl8153_unload;
9291 		ops->eee_get		= r8153_get_eee;
9292 		ops->eee_set		= r8152_set_eee;
9293 		ops->in_nway		= rtl8153_in_nway;
9294 		ops->hw_phy_cfg		= r8156_hw_phy_cfg;
9295 		ops->autosuspend_en	= rtl8156_runtime_enable;
9296 		ops->change_mtu		= rtl8156_change_mtu;
9297 		tp->rx_buf_sz		= 48 * 1024;
9298 		tp->support_2500full	= 1;
9299 		break;
9300 
9301 	case RTL_VER_12:
9302 	case RTL_VER_13:
9303 		tp->support_2500full	= 1;
9304 		fallthrough;
9305 	case RTL_VER_15:
9306 		tp->eee_en		= true;
9307 		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
9308 		ops->init		= r8156b_init;
9309 		ops->enable		= rtl8156b_enable;
9310 		ops->disable		= rtl8153_disable;
9311 		ops->up			= rtl8156_up;
9312 		ops->down		= rtl8156_down;
9313 		ops->unload		= rtl8153_unload;
9314 		ops->eee_get		= r8153_get_eee;
9315 		ops->eee_set		= r8152_set_eee;
9316 		ops->in_nway		= rtl8153_in_nway;
9317 		ops->hw_phy_cfg		= r8156b_hw_phy_cfg;
9318 		ops->autosuspend_en	= rtl8156_runtime_enable;
9319 		ops->change_mtu		= rtl8156_change_mtu;
9320 		tp->rx_buf_sz		= 48 * 1024;
9321 		break;
9322 
9323 	case RTL_VER_14:
9324 		ops->init		= r8153c_init;
9325 		ops->enable		= rtl8153_enable;
9326 		ops->disable		= rtl8153_disable;
9327 		ops->up			= rtl8153c_up;
9328 		ops->down		= rtl8153b_down;
9329 		ops->unload		= rtl8153_unload;
9330 		ops->eee_get		= r8153_get_eee;
9331 		ops->eee_set		= r8152_set_eee;
9332 		ops->in_nway		= rtl8153_in_nway;
9333 		ops->hw_phy_cfg		= r8153c_hw_phy_cfg;
9334 		ops->autosuspend_en	= rtl8153c_runtime_enable;
9335 		ops->change_mtu		= rtl8153c_change_mtu;
9336 		tp->rx_buf_sz		= 32 * 1024;
9337 		tp->eee_en		= true;
9338 		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
9339 		break;
9340 
9341 	default:
9342 		ret = -ENODEV;
9343 		dev_err(&tp->intf->dev, "Unknown Device\n");
9344 		break;
9345 	}
9346 
9347 	return ret;
9348 }
9349 
9350 #define FIRMWARE_8153A_2	"rtl_nic/rtl8153a-2.fw"
9351 #define FIRMWARE_8153A_3	"rtl_nic/rtl8153a-3.fw"
9352 #define FIRMWARE_8153A_4	"rtl_nic/rtl8153a-4.fw"
9353 #define FIRMWARE_8153B_2	"rtl_nic/rtl8153b-2.fw"
9354 #define FIRMWARE_8153C_1	"rtl_nic/rtl8153c-1.fw"
9355 #define FIRMWARE_8156A_2	"rtl_nic/rtl8156a-2.fw"
9356 #define FIRMWARE_8156B_2	"rtl_nic/rtl8156b-2.fw"
9357 
9358 MODULE_FIRMWARE(FIRMWARE_8153A_2);
9359 MODULE_FIRMWARE(FIRMWARE_8153A_3);
9360 MODULE_FIRMWARE(FIRMWARE_8153A_4);
9361 MODULE_FIRMWARE(FIRMWARE_8153B_2);
9362 MODULE_FIRMWARE(FIRMWARE_8153C_1);
9363 MODULE_FIRMWARE(FIRMWARE_8156A_2);
9364 MODULE_FIRMWARE(FIRMWARE_8156B_2);
9365 
9366 static int rtl_fw_init(struct r8152 *tp)
9367 {
9368 	struct rtl_fw *rtl_fw = &tp->rtl_fw;
9369 
9370 	switch (tp->version) {
9371 	case RTL_VER_04:
9372 		rtl_fw->fw_name		= FIRMWARE_8153A_2;
9373 		rtl_fw->pre_fw		= r8153_pre_firmware_1;
9374 		rtl_fw->post_fw		= r8153_post_firmware_1;
9375 		break;
9376 	case RTL_VER_05:
9377 		rtl_fw->fw_name		= FIRMWARE_8153A_3;
9378 		rtl_fw->pre_fw		= r8153_pre_firmware_2;
9379 		rtl_fw->post_fw		= r8153_post_firmware_2;
9380 		break;
9381 	case RTL_VER_06:
9382 		rtl_fw->fw_name		= FIRMWARE_8153A_4;
9383 		rtl_fw->post_fw		= r8153_post_firmware_3;
9384 		break;
9385 	case RTL_VER_09:
9386 		rtl_fw->fw_name		= FIRMWARE_8153B_2;
9387 		rtl_fw->pre_fw		= r8153b_pre_firmware_1;
9388 		rtl_fw->post_fw		= r8153b_post_firmware_1;
9389 		break;
9390 	case RTL_VER_11:
9391 		rtl_fw->fw_name		= FIRMWARE_8156A_2;
9392 		rtl_fw->post_fw		= r8156a_post_firmware_1;
9393 		break;
9394 	case RTL_VER_13:
9395 	case RTL_VER_15:
9396 		rtl_fw->fw_name		= FIRMWARE_8156B_2;
9397 		break;
9398 	case RTL_VER_14:
9399 		rtl_fw->fw_name		= FIRMWARE_8153C_1;
9400 		rtl_fw->pre_fw		= r8153b_pre_firmware_1;
9401 		rtl_fw->post_fw		= r8153c_post_firmware_1;
9402 		break;
9403 	default:
9404 		break;
9405 	}
9406 
9407 	return 0;
9408 }
9409 
9410 u8 rtl8152_get_version(struct usb_interface *intf)
9411 {
9412 	struct usb_device *udev = interface_to_usbdev(intf);
9413 	u32 ocp_data = 0;
9414 	__le32 *tmp;
9415 	u8 version;
9416 	int ret;
9417 
9418 	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
9419 	if (!tmp)
9420 		return 0;
9421 
9422 	ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
9423 			      RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
9424 			      PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
9425 	if (ret > 0)
9426 		ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
9427 
9428 	kfree(tmp);
9429 
9430 	switch (ocp_data) {
9431 	case 0x4c00:
9432 		version = RTL_VER_01;
9433 		break;
9434 	case 0x4c10:
9435 		version = RTL_VER_02;
9436 		break;
9437 	case 0x5c00:
9438 		version = RTL_VER_03;
9439 		break;
9440 	case 0x5c10:
9441 		version = RTL_VER_04;
9442 		break;
9443 	case 0x5c20:
9444 		version = RTL_VER_05;
9445 		break;
9446 	case 0x5c30:
9447 		version = RTL_VER_06;
9448 		break;
9449 	case 0x4800:
9450 		version = RTL_VER_07;
9451 		break;
9452 	case 0x6000:
9453 		version = RTL_VER_08;
9454 		break;
9455 	case 0x6010:
9456 		version = RTL_VER_09;
9457 		break;
9458 	case 0x7010:
9459 		version = RTL_TEST_01;
9460 		break;
9461 	case 0x7020:
9462 		version = RTL_VER_10;
9463 		break;
9464 	case 0x7030:
9465 		version = RTL_VER_11;
9466 		break;
9467 	case 0x7400:
9468 		version = RTL_VER_12;
9469 		break;
9470 	case 0x7410:
9471 		version = RTL_VER_13;
9472 		break;
9473 	case 0x6400:
9474 		version = RTL_VER_14;
9475 		break;
9476 	case 0x7420:
9477 		version = RTL_VER_15;
9478 		break;
9479 	default:
9480 		version = RTL_VER_UNKNOWN;
9481 		dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
9482 		break;
9483 	}
9484 
9485 	dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
9486 
9487 	return version;
9488 }
9489 EXPORT_SYMBOL_GPL(rtl8152_get_version);
9490 
9491 static int rtl8152_probe(struct usb_interface *intf,
9492 			 const struct usb_device_id *id)
9493 {
9494 	struct usb_device *udev = interface_to_usbdev(intf);
9495 	u8 version = rtl8152_get_version(intf);
9496 	struct r8152 *tp;
9497 	struct net_device *netdev;
9498 	int ret;
9499 
9500 	if (version == RTL_VER_UNKNOWN)
9501 		return -ENODEV;
9502 
9503 	if (!rtl_vendor_mode(intf))
9504 		return -ENODEV;
9505 
9506 	usb_reset_device(udev);
9507 	netdev = alloc_etherdev(sizeof(struct r8152));
9508 	if (!netdev) {
9509 		dev_err(&intf->dev, "Out of memory\n");
9510 		return -ENOMEM;
9511 	}
9512 
9513 	SET_NETDEV_DEV(netdev, &intf->dev);
9514 	tp = netdev_priv(netdev);
9515 	tp->msg_enable = 0x7FFF;
9516 
9517 	tp->udev = udev;
9518 	tp->netdev = netdev;
9519 	tp->intf = intf;
9520 	tp->version = version;
9521 
9522 	tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0);
9523 	tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0);
9524 	tp->pipe_in = usb_rcvbulkpipe(udev, 1);
9525 	tp->pipe_out = usb_sndbulkpipe(udev, 2);
9526 	tp->pipe_intr = usb_rcvintpipe(udev, 3);
9527 
9528 	switch (version) {
9529 	case RTL_VER_01:
9530 	case RTL_VER_02:
9531 	case RTL_VER_07:
9532 		tp->mii.supports_gmii = 0;
9533 		break;
9534 	default:
9535 		tp->mii.supports_gmii = 1;
9536 		break;
9537 	}
9538 
9539 	ret = rtl_ops_init(tp);
9540 	if (ret)
9541 		goto out;
9542 
9543 	rtl_fw_init(tp);
9544 
9545 	mutex_init(&tp->control);
9546 	INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
9547 	INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
9548 	tasklet_setup(&tp->tx_tl, bottom_half);
9549 	tasklet_disable(&tp->tx_tl);
9550 
9551 	netdev->netdev_ops = &rtl8152_netdev_ops;
9552 	netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
9553 
9554 	netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9555 			    NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
9556 			    NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
9557 			    NETIF_F_HW_VLAN_CTAG_TX;
9558 	netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9559 			      NETIF_F_TSO | NETIF_F_FRAGLIST |
9560 			      NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
9561 			      NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
9562 	netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
9563 				NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
9564 				NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
9565 
9566 	if (tp->version == RTL_VER_01) {
9567 		netdev->features &= ~NETIF_F_RXCSUM;
9568 		netdev->hw_features &= ~NETIF_F_RXCSUM;
9569 	}
9570 
9571 	if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO) {
9572 		switch (le16_to_cpu(udev->descriptor.idProduct)) {
9573 		case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
9574 		case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
9575 			tp->lenovo_macpassthru = 1;
9576 		}
9577 	}
9578 
9579 	if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
9580 	    (!strcmp(udev->serial, "000001000000") ||
9581 	     !strcmp(udev->serial, "000002000000"))) {
9582 		dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
9583 		tp->dell_tb_rx_agg_bug = 1;
9584 	}
9585 
9586 	netdev->ethtool_ops = &ops;
9587 	netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
9588 
9589 	/* MTU range: 68 - 1500 or 9194 */
9590 	netdev->min_mtu = ETH_MIN_MTU;
9591 	switch (tp->version) {
9592 	case RTL_VER_03:
9593 	case RTL_VER_04:
9594 	case RTL_VER_05:
9595 	case RTL_VER_06:
9596 	case RTL_VER_08:
9597 	case RTL_VER_09:
9598 	case RTL_VER_14:
9599 		netdev->max_mtu = size_to_mtu(9 * 1024);
9600 		break;
9601 	case RTL_VER_10:
9602 	case RTL_VER_11:
9603 		netdev->max_mtu = size_to_mtu(15 * 1024);
9604 		break;
9605 	case RTL_VER_12:
9606 	case RTL_VER_13:
9607 	case RTL_VER_15:
9608 		netdev->max_mtu = size_to_mtu(16 * 1024);
9609 		break;
9610 	case RTL_VER_01:
9611 	case RTL_VER_02:
9612 	case RTL_VER_07:
9613 	default:
9614 		netdev->max_mtu = ETH_DATA_LEN;
9615 		break;
9616 	}
9617 
9618 	tp->mii.dev = netdev;
9619 	tp->mii.mdio_read = read_mii_word;
9620 	tp->mii.mdio_write = write_mii_word;
9621 	tp->mii.phy_id_mask = 0x3f;
9622 	tp->mii.reg_num_mask = 0x1f;
9623 	tp->mii.phy_id = R8152_PHY_ID;
9624 
9625 	tp->autoneg = AUTONEG_ENABLE;
9626 	tp->speed = SPEED_100;
9627 	tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
9628 			  RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
9629 	if (tp->mii.supports_gmii) {
9630 		if (tp->support_2500full &&
9631 		    tp->udev->speed >= USB_SPEED_SUPER) {
9632 			tp->speed = SPEED_2500;
9633 			tp->advertising |= RTL_ADVERTISED_2500_FULL;
9634 		} else {
9635 			tp->speed = SPEED_1000;
9636 		}
9637 		tp->advertising |= RTL_ADVERTISED_1000_FULL;
9638 	}
9639 	tp->duplex = DUPLEX_FULL;
9640 
9641 	tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
9642 	tp->rx_pending = 10 * RTL8152_MAX_RX;
9643 
9644 	intf->needs_remote_wakeup = 1;
9645 
9646 	if (!rtl_can_wakeup(tp))
9647 		__rtl_set_wol(tp, 0);
9648 	else
9649 		tp->saved_wolopts = __rtl_get_wol(tp);
9650 
9651 	tp->rtl_ops.init(tp);
9652 #if IS_BUILTIN(CONFIG_USB_RTL8152)
9653 	/* Retry in case request_firmware() is not ready yet. */
9654 	tp->rtl_fw.retry = true;
9655 #endif
9656 	queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
9657 	set_ethernet_addr(tp, false);
9658 
9659 	usb_set_intfdata(intf, tp);
9660 
9661 	if (tp->support_2500full)
9662 		netif_napi_add(netdev, &tp->napi, r8152_poll, 256);
9663 	else
9664 		netif_napi_add(netdev, &tp->napi, r8152_poll, 64);
9665 
9666 	ret = register_netdev(netdev);
9667 	if (ret != 0) {
9668 		dev_err(&intf->dev, "couldn't register the device\n");
9669 		goto out1;
9670 	}
9671 
9672 	if (tp->saved_wolopts)
9673 		device_set_wakeup_enable(&udev->dev, true);
9674 	else
9675 		device_set_wakeup_enable(&udev->dev, false);
9676 
9677 	netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
9678 
9679 	return 0;
9680 
9681 out1:
9682 	tasklet_kill(&tp->tx_tl);
9683 	usb_set_intfdata(intf, NULL);
9684 out:
9685 	free_netdev(netdev);
9686 	return ret;
9687 }
9688 
9689 static void rtl8152_disconnect(struct usb_interface *intf)
9690 {
9691 	struct r8152 *tp = usb_get_intfdata(intf);
9692 
9693 	usb_set_intfdata(intf, NULL);
9694 	if (tp) {
9695 		rtl_set_unplug(tp);
9696 
9697 		unregister_netdev(tp->netdev);
9698 		tasklet_kill(&tp->tx_tl);
9699 		cancel_delayed_work_sync(&tp->hw_phy_work);
9700 		if (tp->rtl_ops.unload)
9701 			tp->rtl_ops.unload(tp);
9702 		rtl8152_release_firmware(tp);
9703 		free_netdev(tp->netdev);
9704 	}
9705 }
9706 
9707 #define REALTEK_USB_DEVICE(vend, prod)	{ \
9708 	USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC), \
9709 }, \
9710 { \
9711 	USB_DEVICE_AND_INTERFACE_INFO(vend, prod, USB_CLASS_COMM, \
9712 			USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE), \
9713 }
9714 
9715 /* table of devices that work with this driver */
9716 static const struct usb_device_id rtl8152_table[] = {
9717 	/* Realtek */
9718 	REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050),
9719 	REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8053),
9720 	REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152),
9721 	REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153),
9722 	REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8155),
9723 	REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8156),
9724 
9725 	/* Microsoft */
9726 	REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab),
9727 	REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6),
9728 	REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927),
9729 	REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101),
9730 	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f),
9731 	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3062),
9732 	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3069),
9733 	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3082),
9734 	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205),
9735 	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x720c),
9736 	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7214),
9737 	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x721e),
9738 	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0xa387),
9739 	REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041),
9740 	REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff),
9741 	REALTEK_USB_DEVICE(VENDOR_ID_TPLINK,  0x0601),
9742 	{}
9743 };
9744 
9745 MODULE_DEVICE_TABLE(usb, rtl8152_table);
9746 
9747 static struct usb_driver rtl8152_driver = {
9748 	.name =		MODULENAME,
9749 	.id_table =	rtl8152_table,
9750 	.probe =	rtl8152_probe,
9751 	.disconnect =	rtl8152_disconnect,
9752 	.suspend =	rtl8152_suspend,
9753 	.resume =	rtl8152_resume,
9754 	.reset_resume =	rtl8152_reset_resume,
9755 	.pre_reset =	rtl8152_pre_reset,
9756 	.post_reset =	rtl8152_post_reset,
9757 	.supports_autosuspend = 1,
9758 	.disable_hub_initiated_lpm = 1,
9759 };
9760 
9761 module_usb_driver(rtl8152_driver);
9762 
9763 MODULE_AUTHOR(DRIVER_AUTHOR);
9764 MODULE_DESCRIPTION(DRIVER_DESC);
9765 MODULE_LICENSE("GPL");
9766 MODULE_VERSION(DRIVER_VERSION);
9767