1 /* 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2 as published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/signal.h> 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/usb.h> 18 #include <linux/crc32.h> 19 #include <linux/if_vlan.h> 20 #include <linux/uaccess.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include <net/ip6_checksum.h> 25 26 /* Version Information */ 27 #define DRIVER_VERSION "v1.06.0 (2014/03/03)" 28 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 29 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 30 #define MODULENAME "r8152" 31 32 #define R8152_PHY_ID 32 33 34 #define PLA_IDR 0xc000 35 #define PLA_RCR 0xc010 36 #define PLA_RMS 0xc016 37 #define PLA_RXFIFO_CTRL0 0xc0a0 38 #define PLA_RXFIFO_CTRL1 0xc0a4 39 #define PLA_RXFIFO_CTRL2 0xc0a8 40 #define PLA_FMC 0xc0b4 41 #define PLA_CFG_WOL 0xc0b6 42 #define PLA_TEREDO_CFG 0xc0bc 43 #define PLA_MAR 0xcd00 44 #define PLA_BACKUP 0xd000 45 #define PAL_BDC_CR 0xd1a0 46 #define PLA_TEREDO_TIMER 0xd2cc 47 #define PLA_REALWOW_TIMER 0xd2e8 48 #define PLA_LEDSEL 0xdd90 49 #define PLA_LED_FEATURE 0xdd92 50 #define PLA_PHYAR 0xde00 51 #define PLA_BOOT_CTRL 0xe004 52 #define PLA_GPHY_INTR_IMR 0xe022 53 #define PLA_EEE_CR 0xe040 54 #define PLA_EEEP_CR 0xe080 55 #define PLA_MAC_PWR_CTRL 0xe0c0 56 #define PLA_MAC_PWR_CTRL2 0xe0ca 57 #define PLA_MAC_PWR_CTRL3 0xe0cc 58 #define PLA_MAC_PWR_CTRL4 0xe0ce 59 #define PLA_WDT6_CTRL 0xe428 60 #define PLA_TCR0 0xe610 61 #define PLA_TCR1 0xe612 62 #define PLA_TXFIFO_CTRL 0xe618 63 #define PLA_RSTTALLY 0xe800 64 #define PLA_CR 0xe813 65 #define PLA_CRWECR 0xe81c 66 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 67 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 68 #define PLA_CONFIG5 0xe822 69 #define PLA_PHY_PWR 0xe84c 70 #define PLA_OOB_CTRL 0xe84f 71 #define PLA_CPCR 0xe854 72 #define PLA_MISC_0 0xe858 73 #define PLA_MISC_1 0xe85a 74 #define PLA_OCP_GPHY_BASE 0xe86c 75 #define PLA_TALLYCNT 0xe890 76 #define PLA_SFF_STS_7 0xe8de 77 #define PLA_PHYSTATUS 0xe908 78 #define PLA_BP_BA 0xfc26 79 #define PLA_BP_0 0xfc28 80 #define PLA_BP_1 0xfc2a 81 #define PLA_BP_2 0xfc2c 82 #define PLA_BP_3 0xfc2e 83 #define PLA_BP_4 0xfc30 84 #define PLA_BP_5 0xfc32 85 #define PLA_BP_6 0xfc34 86 #define PLA_BP_7 0xfc36 87 #define PLA_BP_EN 0xfc38 88 89 #define USB_U2P3_CTRL 0xb460 90 #define USB_DEV_STAT 0xb808 91 #define USB_USB_CTRL 0xd406 92 #define USB_PHY_CTRL 0xd408 93 #define USB_TX_AGG 0xd40a 94 #define USB_RX_BUF_TH 0xd40c 95 #define USB_USB_TIMER 0xd428 96 #define USB_RX_EARLY_AGG 0xd42c 97 #define USB_PM_CTRL_STATUS 0xd432 98 #define USB_TX_DMA 0xd434 99 #define USB_TOLERANCE 0xd490 100 #define USB_LPM_CTRL 0xd41a 101 #define USB_UPS_CTRL 0xd800 102 #define USB_MISC_0 0xd81a 103 #define USB_POWER_CUT 0xd80a 104 #define USB_AFE_CTRL2 0xd824 105 #define USB_WDT11_CTRL 0xe43c 106 #define USB_BP_BA 0xfc26 107 #define USB_BP_0 0xfc28 108 #define USB_BP_1 0xfc2a 109 #define USB_BP_2 0xfc2c 110 #define USB_BP_3 0xfc2e 111 #define USB_BP_4 0xfc30 112 #define USB_BP_5 0xfc32 113 #define USB_BP_6 0xfc34 114 #define USB_BP_7 0xfc36 115 #define USB_BP_EN 0xfc38 116 117 /* OCP Registers */ 118 #define OCP_ALDPS_CONFIG 0x2010 119 #define OCP_EEE_CONFIG1 0x2080 120 #define OCP_EEE_CONFIG2 0x2092 121 #define OCP_EEE_CONFIG3 0x2094 122 #define OCP_BASE_MII 0xa400 123 #define OCP_EEE_AR 0xa41a 124 #define OCP_EEE_DATA 0xa41c 125 #define OCP_PHY_STATUS 0xa420 126 #define OCP_POWER_CFG 0xa430 127 #define OCP_EEE_CFG 0xa432 128 #define OCP_SRAM_ADDR 0xa436 129 #define OCP_SRAM_DATA 0xa438 130 #define OCP_DOWN_SPEED 0xa442 131 #define OCP_EEE_CFG2 0xa5d0 132 #define OCP_ADC_CFG 0xbc06 133 134 /* SRAM Register */ 135 #define SRAM_LPF_CFG 0x8012 136 #define SRAM_10M_AMP1 0x8080 137 #define SRAM_10M_AMP2 0x8082 138 #define SRAM_IMPEDANCE 0x8084 139 140 /* PLA_RCR */ 141 #define RCR_AAP 0x00000001 142 #define RCR_APM 0x00000002 143 #define RCR_AM 0x00000004 144 #define RCR_AB 0x00000008 145 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 146 147 /* PLA_RXFIFO_CTRL0 */ 148 #define RXFIFO_THR1_NORMAL 0x00080002 149 #define RXFIFO_THR1_OOB 0x01800003 150 151 /* PLA_RXFIFO_CTRL1 */ 152 #define RXFIFO_THR2_FULL 0x00000060 153 #define RXFIFO_THR2_HIGH 0x00000038 154 #define RXFIFO_THR2_OOB 0x0000004a 155 #define RXFIFO_THR2_NORMAL 0x00a0 156 157 /* PLA_RXFIFO_CTRL2 */ 158 #define RXFIFO_THR3_FULL 0x00000078 159 #define RXFIFO_THR3_HIGH 0x00000048 160 #define RXFIFO_THR3_OOB 0x0000005a 161 #define RXFIFO_THR3_NORMAL 0x0110 162 163 /* PLA_TXFIFO_CTRL */ 164 #define TXFIFO_THR_NORMAL 0x00400008 165 #define TXFIFO_THR_NORMAL2 0x01000008 166 167 /* PLA_FMC */ 168 #define FMC_FCR_MCU_EN 0x0001 169 170 /* PLA_EEEP_CR */ 171 #define EEEP_CR_EEEP_TX 0x0002 172 173 /* PLA_WDT6_CTRL */ 174 #define WDT6_SET_MODE 0x0010 175 176 /* PLA_TCR0 */ 177 #define TCR0_TX_EMPTY 0x0800 178 #define TCR0_AUTO_FIFO 0x0080 179 180 /* PLA_TCR1 */ 181 #define VERSION_MASK 0x7cf0 182 183 /* PLA_RSTTALLY */ 184 #define TALLY_RESET 0x0001 185 186 /* PLA_CR */ 187 #define CR_RST 0x10 188 #define CR_RE 0x08 189 #define CR_TE 0x04 190 191 /* PLA_CRWECR */ 192 #define CRWECR_NORAML 0x00 193 #define CRWECR_CONFIG 0xc0 194 195 /* PLA_OOB_CTRL */ 196 #define NOW_IS_OOB 0x80 197 #define TXFIFO_EMPTY 0x20 198 #define RXFIFO_EMPTY 0x10 199 #define LINK_LIST_READY 0x02 200 #define DIS_MCU_CLROOB 0x01 201 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 202 203 /* PLA_MISC_1 */ 204 #define RXDY_GATED_EN 0x0008 205 206 /* PLA_SFF_STS_7 */ 207 #define RE_INIT_LL 0x8000 208 #define MCU_BORW_EN 0x4000 209 210 /* PLA_CPCR */ 211 #define CPCR_RX_VLAN 0x0040 212 213 /* PLA_CFG_WOL */ 214 #define MAGIC_EN 0x0001 215 216 /* PLA_TEREDO_CFG */ 217 #define TEREDO_SEL 0x8000 218 #define TEREDO_WAKE_MASK 0x7f00 219 #define TEREDO_RS_EVENT_MASK 0x00fe 220 #define OOB_TEREDO_EN 0x0001 221 222 /* PAL_BDC_CR */ 223 #define ALDPS_PROXY_MODE 0x0001 224 225 /* PLA_CONFIG34 */ 226 #define LINK_ON_WAKE_EN 0x0010 227 #define LINK_OFF_WAKE_EN 0x0008 228 229 /* PLA_CONFIG5 */ 230 #define BWF_EN 0x0040 231 #define MWF_EN 0x0020 232 #define UWF_EN 0x0010 233 #define LAN_WAKE_EN 0x0002 234 235 /* PLA_LED_FEATURE */ 236 #define LED_MODE_MASK 0x0700 237 238 /* PLA_PHY_PWR */ 239 #define TX_10M_IDLE_EN 0x0080 240 #define PFM_PWM_SWITCH 0x0040 241 242 /* PLA_MAC_PWR_CTRL */ 243 #define D3_CLK_GATED_EN 0x00004000 244 #define MCU_CLK_RATIO 0x07010f07 245 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 246 #define ALDPS_SPDWN_RATIO 0x0f87 247 248 /* PLA_MAC_PWR_CTRL2 */ 249 #define EEE_SPDWN_RATIO 0x8007 250 251 /* PLA_MAC_PWR_CTRL3 */ 252 #define PKT_AVAIL_SPDWN_EN 0x0100 253 #define SUSPEND_SPDWN_EN 0x0004 254 #define U1U2_SPDWN_EN 0x0002 255 #define L1_SPDWN_EN 0x0001 256 257 /* PLA_MAC_PWR_CTRL4 */ 258 #define PWRSAVE_SPDWN_EN 0x1000 259 #define RXDV_SPDWN_EN 0x0800 260 #define TX10MIDLE_EN 0x0100 261 #define TP100_SPDWN_EN 0x0020 262 #define TP500_SPDWN_EN 0x0010 263 #define TP1000_SPDWN_EN 0x0008 264 #define EEE_SPDWN_EN 0x0001 265 266 /* PLA_GPHY_INTR_IMR */ 267 #define GPHY_STS_MSK 0x0001 268 #define SPEED_DOWN_MSK 0x0002 269 #define SPDWN_RXDV_MSK 0x0004 270 #define SPDWN_LINKCHG_MSK 0x0008 271 272 /* PLA_PHYAR */ 273 #define PHYAR_FLAG 0x80000000 274 275 /* PLA_EEE_CR */ 276 #define EEE_RX_EN 0x0001 277 #define EEE_TX_EN 0x0002 278 279 /* PLA_BOOT_CTRL */ 280 #define AUTOLOAD_DONE 0x0002 281 282 /* USB_DEV_STAT */ 283 #define STAT_SPEED_MASK 0x0006 284 #define STAT_SPEED_HIGH 0x0000 285 #define STAT_SPEED_FULL 0x0001 286 287 /* USB_TX_AGG */ 288 #define TX_AGG_MAX_THRESHOLD 0x03 289 290 /* USB_RX_BUF_TH */ 291 #define RX_THR_SUPPER 0x0c350180 292 #define RX_THR_HIGH 0x7a120180 293 #define RX_THR_SLOW 0xffff0180 294 295 /* USB_TX_DMA */ 296 #define TEST_MODE_DISABLE 0x00000001 297 #define TX_SIZE_ADJUST1 0x00000100 298 299 /* USB_UPS_CTRL */ 300 #define POWER_CUT 0x0100 301 302 /* USB_PM_CTRL_STATUS */ 303 #define RESUME_INDICATE 0x0001 304 305 /* USB_USB_CTRL */ 306 #define RX_AGG_DISABLE 0x0010 307 308 /* USB_U2P3_CTRL */ 309 #define U2P3_ENABLE 0x0001 310 311 /* USB_POWER_CUT */ 312 #define PWR_EN 0x0001 313 #define PHASE2_EN 0x0008 314 315 /* USB_MISC_0 */ 316 #define PCUT_STATUS 0x0001 317 318 /* USB_RX_EARLY_AGG */ 319 #define EARLY_AGG_SUPPER 0x0e832981 320 #define EARLY_AGG_HIGH 0x0e837a12 321 #define EARLY_AGG_SLOW 0x0e83ffff 322 323 /* USB_WDT11_CTRL */ 324 #define TIMER11_EN 0x0001 325 326 /* USB_LPM_CTRL */ 327 #define LPM_TIMER_MASK 0x0c 328 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 329 #define LPM_TIMER_500US 0x0c /* 500 us */ 330 331 /* USB_AFE_CTRL2 */ 332 #define SEN_VAL_MASK 0xf800 333 #define SEN_VAL_NORMAL 0xa000 334 #define SEL_RXIDLE 0x0100 335 336 /* OCP_ALDPS_CONFIG */ 337 #define ENPWRSAVE 0x8000 338 #define ENPDNPS 0x0200 339 #define LINKENA 0x0100 340 #define DIS_SDSAVE 0x0010 341 342 /* OCP_PHY_STATUS */ 343 #define PHY_STAT_MASK 0x0007 344 #define PHY_STAT_LAN_ON 3 345 #define PHY_STAT_PWRDN 5 346 347 /* OCP_POWER_CFG */ 348 #define EEE_CLKDIV_EN 0x8000 349 #define EN_ALDPS 0x0004 350 #define EN_10M_PLLOFF 0x0001 351 352 /* OCP_EEE_CONFIG1 */ 353 #define RG_TXLPI_MSK_HFDUP 0x8000 354 #define RG_MATCLR_EN 0x4000 355 #define EEE_10_CAP 0x2000 356 #define EEE_NWAY_EN 0x1000 357 #define TX_QUIET_EN 0x0200 358 #define RX_QUIET_EN 0x0100 359 #define SDRISETIME 0x0010 /* bit 4 ~ 6 */ 360 #define RG_RXLPI_MSK_HFDUP 0x0008 361 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 362 363 /* OCP_EEE_CONFIG2 */ 364 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 365 #define RG_DACQUIET_EN 0x0400 366 #define RG_LDVQUIET_EN 0x0200 367 #define RG_CKRSEL 0x0020 368 #define RG_EEEPRG_EN 0x0010 369 370 /* OCP_EEE_CONFIG3 */ 371 #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */ 372 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 373 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 374 375 /* OCP_EEE_AR */ 376 /* bit[15:14] function */ 377 #define FUN_ADDR 0x0000 378 #define FUN_DATA 0x4000 379 /* bit[4:0] device addr */ 380 #define DEVICE_ADDR 0x0007 381 382 /* OCP_EEE_DATA */ 383 #define EEE_ADDR 0x003C 384 #define EEE_DATA 0x0002 385 386 /* OCP_EEE_CFG */ 387 #define CTAP_SHORT_EN 0x0040 388 #define EEE10_EN 0x0010 389 390 /* OCP_DOWN_SPEED */ 391 #define EN_10M_BGOFF 0x0080 392 393 /* OCP_EEE_CFG2 */ 394 #define MY1000_EEE 0x0004 395 #define MY100_EEE 0x0002 396 397 /* OCP_ADC_CFG */ 398 #define CKADSEL_L 0x0100 399 #define ADC_EN 0x0080 400 #define EN_EMI_L 0x0040 401 402 /* SRAM_LPF_CFG */ 403 #define LPF_AUTO_TUNE 0x8000 404 405 /* SRAM_10M_AMP1 */ 406 #define GDAC_IB_UPALL 0x0008 407 408 /* SRAM_10M_AMP2 */ 409 #define AMP_DN 0x0200 410 411 /* SRAM_IMPEDANCE */ 412 #define RX_DRIVING_MASK 0x6000 413 414 enum rtl_register_content { 415 _1000bps = 0x10, 416 _100bps = 0x08, 417 _10bps = 0x04, 418 LINK_STATUS = 0x02, 419 FULL_DUP = 0x01, 420 }; 421 422 #define RTL8152_MAX_TX 10 423 #define RTL8152_MAX_RX 10 424 #define INTBUFSIZE 2 425 #define CRC_SIZE 4 426 #define TX_ALIGN 4 427 #define RX_ALIGN 8 428 429 #define INTR_LINK 0x0004 430 431 #define RTL8152_REQT_READ 0xc0 432 #define RTL8152_REQT_WRITE 0x40 433 #define RTL8152_REQ_GET_REGS 0x05 434 #define RTL8152_REQ_SET_REGS 0x05 435 436 #define BYTE_EN_DWORD 0xff 437 #define BYTE_EN_WORD 0x33 438 #define BYTE_EN_BYTE 0x11 439 #define BYTE_EN_SIX_BYTES 0x3f 440 #define BYTE_EN_START_MASK 0x0f 441 #define BYTE_EN_END_MASK 0xf0 442 443 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) 444 #define RTL8152_TX_TIMEOUT (HZ) 445 446 /* rtl8152 flags */ 447 enum rtl8152_flags { 448 RTL8152_UNPLUG = 0, 449 RTL8152_SET_RX_MODE, 450 WORK_ENABLE, 451 RTL8152_LINK_CHG, 452 SELECTIVE_SUSPEND, 453 PHY_RESET, 454 SCHEDULE_TASKLET, 455 }; 456 457 /* Define these values to match your device */ 458 #define VENDOR_ID_REALTEK 0x0bda 459 #define PRODUCT_ID_RTL8152 0x8152 460 #define PRODUCT_ID_RTL8153 0x8153 461 462 #define VENDOR_ID_SAMSUNG 0x04e8 463 #define PRODUCT_ID_SAMSUNG 0xa101 464 465 #define MCU_TYPE_PLA 0x0100 466 #define MCU_TYPE_USB 0x0000 467 468 #define REALTEK_USB_DEVICE(vend, prod) \ 469 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC) 470 471 struct tally_counter { 472 __le64 tx_packets; 473 __le64 rx_packets; 474 __le64 tx_errors; 475 __le32 rx_errors; 476 __le16 rx_missed; 477 __le16 align_errors; 478 __le32 tx_one_collision; 479 __le32 tx_multi_collision; 480 __le64 rx_unicast; 481 __le64 rx_broadcast; 482 __le32 rx_multicast; 483 __le16 tx_aborted; 484 __le16 tx_underun; 485 }; 486 487 struct rx_desc { 488 __le32 opts1; 489 #define RX_LEN_MASK 0x7fff 490 491 __le32 opts2; 492 #define RD_UDP_CS (1 << 23) 493 #define RD_TCP_CS (1 << 22) 494 #define RD_IPV6_CS (1 << 20) 495 #define RD_IPV4_CS (1 << 19) 496 497 __le32 opts3; 498 #define IPF (1 << 23) /* IP checksum fail */ 499 #define UDPF (1 << 22) /* UDP checksum fail */ 500 #define TCPF (1 << 21) /* TCP checksum fail */ 501 502 __le32 opts4; 503 __le32 opts5; 504 __le32 opts6; 505 }; 506 507 struct tx_desc { 508 __le32 opts1; 509 #define TX_FS (1 << 31) /* First segment of a packet */ 510 #define TX_LS (1 << 30) /* Final segment of a packet */ 511 #define GTSENDV4 (1 << 28) 512 #define GTSENDV6 (1 << 27) 513 #define GTTCPHO_SHIFT 18 514 #define GTTCPHO_MAX 0x7fU 515 #define TX_LEN_MAX 0x3ffffU 516 517 __le32 opts2; 518 #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */ 519 #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */ 520 #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */ 521 #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */ 522 #define MSS_SHIFT 17 523 #define MSS_MAX 0x7ffU 524 #define TCPHO_SHIFT 17 525 #define TCPHO_MAX 0x7ffU 526 }; 527 528 struct r8152; 529 530 struct rx_agg { 531 struct list_head list; 532 struct urb *urb; 533 struct r8152 *context; 534 void *buffer; 535 void *head; 536 }; 537 538 struct tx_agg { 539 struct list_head list; 540 struct urb *urb; 541 struct r8152 *context; 542 void *buffer; 543 void *head; 544 u32 skb_num; 545 u32 skb_len; 546 }; 547 548 struct r8152 { 549 unsigned long flags; 550 struct usb_device *udev; 551 struct tasklet_struct tl; 552 struct usb_interface *intf; 553 struct net_device *netdev; 554 struct urb *intr_urb; 555 struct tx_agg tx_info[RTL8152_MAX_TX]; 556 struct rx_agg rx_info[RTL8152_MAX_RX]; 557 struct list_head rx_done, tx_free; 558 struct sk_buff_head tx_queue; 559 spinlock_t rx_lock, tx_lock; 560 struct delayed_work schedule; 561 struct mii_if_info mii; 562 563 struct rtl_ops { 564 void (*init)(struct r8152 *); 565 int (*enable)(struct r8152 *); 566 void (*disable)(struct r8152 *); 567 void (*up)(struct r8152 *); 568 void (*down)(struct r8152 *); 569 void (*unload)(struct r8152 *); 570 } rtl_ops; 571 572 int intr_interval; 573 u32 saved_wolopts; 574 u32 msg_enable; 575 u32 tx_qlen; 576 u16 ocp_base; 577 u8 *intr_buff; 578 u8 version; 579 u8 speed; 580 }; 581 582 enum rtl_version { 583 RTL_VER_UNKNOWN = 0, 584 RTL_VER_01, 585 RTL_VER_02, 586 RTL_VER_03, 587 RTL_VER_04, 588 RTL_VER_05, 589 RTL_VER_MAX 590 }; 591 592 enum tx_csum_stat { 593 TX_CSUM_SUCCESS = 0, 594 TX_CSUM_TSO, 595 TX_CSUM_NONE 596 }; 597 598 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 599 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 600 */ 601 static const int multicast_filter_limit = 32; 602 static unsigned int rx_buf_sz = 16384; 603 604 #define RTL_LIMITED_TSO_SIZE (rx_buf_sz - sizeof(struct tx_desc) - \ 605 VLAN_ETH_HLEN - VLAN_HLEN) 606 607 static 608 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 609 { 610 int ret; 611 void *tmp; 612 613 tmp = kmalloc(size, GFP_KERNEL); 614 if (!tmp) 615 return -ENOMEM; 616 617 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 618 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 619 value, index, tmp, size, 500); 620 621 memcpy(data, tmp, size); 622 kfree(tmp); 623 624 return ret; 625 } 626 627 static 628 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 629 { 630 int ret; 631 void *tmp; 632 633 tmp = kmemdup(data, size, GFP_KERNEL); 634 if (!tmp) 635 return -ENOMEM; 636 637 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 638 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 639 value, index, tmp, size, 500); 640 641 kfree(tmp); 642 643 return ret; 644 } 645 646 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 647 void *data, u16 type) 648 { 649 u16 limit = 64; 650 int ret = 0; 651 652 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 653 return -ENODEV; 654 655 /* both size and indix must be 4 bytes align */ 656 if ((size & 3) || !size || (index & 3) || !data) 657 return -EPERM; 658 659 if ((u32)index + (u32)size > 0xffff) 660 return -EPERM; 661 662 while (size) { 663 if (size > limit) { 664 ret = get_registers(tp, index, type, limit, data); 665 if (ret < 0) 666 break; 667 668 index += limit; 669 data += limit; 670 size -= limit; 671 } else { 672 ret = get_registers(tp, index, type, size, data); 673 if (ret < 0) 674 break; 675 676 index += size; 677 data += size; 678 size = 0; 679 break; 680 } 681 } 682 683 return ret; 684 } 685 686 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 687 u16 size, void *data, u16 type) 688 { 689 int ret; 690 u16 byteen_start, byteen_end, byen; 691 u16 limit = 512; 692 693 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 694 return -ENODEV; 695 696 /* both size and indix must be 4 bytes align */ 697 if ((size & 3) || !size || (index & 3) || !data) 698 return -EPERM; 699 700 if ((u32)index + (u32)size > 0xffff) 701 return -EPERM; 702 703 byteen_start = byteen & BYTE_EN_START_MASK; 704 byteen_end = byteen & BYTE_EN_END_MASK; 705 706 byen = byteen_start | (byteen_start << 4); 707 ret = set_registers(tp, index, type | byen, 4, data); 708 if (ret < 0) 709 goto error1; 710 711 index += 4; 712 data += 4; 713 size -= 4; 714 715 if (size) { 716 size -= 4; 717 718 while (size) { 719 if (size > limit) { 720 ret = set_registers(tp, index, 721 type | BYTE_EN_DWORD, 722 limit, data); 723 if (ret < 0) 724 goto error1; 725 726 index += limit; 727 data += limit; 728 size -= limit; 729 } else { 730 ret = set_registers(tp, index, 731 type | BYTE_EN_DWORD, 732 size, data); 733 if (ret < 0) 734 goto error1; 735 736 index += size; 737 data += size; 738 size = 0; 739 break; 740 } 741 } 742 743 byen = byteen_end | (byteen_end >> 4); 744 ret = set_registers(tp, index, type | byen, 4, data); 745 if (ret < 0) 746 goto error1; 747 } 748 749 error1: 750 return ret; 751 } 752 753 static inline 754 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 755 { 756 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 757 } 758 759 static inline 760 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 761 { 762 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 763 } 764 765 static inline 766 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 767 { 768 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); 769 } 770 771 static inline 772 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 773 { 774 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 775 } 776 777 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 778 { 779 __le32 data; 780 781 generic_ocp_read(tp, index, sizeof(data), &data, type); 782 783 return __le32_to_cpu(data); 784 } 785 786 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 787 { 788 __le32 tmp = __cpu_to_le32(data); 789 790 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 791 } 792 793 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 794 { 795 u32 data; 796 __le32 tmp; 797 u8 shift = index & 2; 798 799 index &= ~3; 800 801 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 802 803 data = __le32_to_cpu(tmp); 804 data >>= (shift * 8); 805 data &= 0xffff; 806 807 return (u16)data; 808 } 809 810 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 811 { 812 u32 mask = 0xffff; 813 __le32 tmp; 814 u16 byen = BYTE_EN_WORD; 815 u8 shift = index & 2; 816 817 data &= mask; 818 819 if (index & 2) { 820 byen <<= shift; 821 mask <<= (shift * 8); 822 data <<= (shift * 8); 823 index &= ~3; 824 } 825 826 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 827 828 data |= __le32_to_cpu(tmp) & ~mask; 829 tmp = __cpu_to_le32(data); 830 831 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 832 } 833 834 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 835 { 836 u32 data; 837 __le32 tmp; 838 u8 shift = index & 3; 839 840 index &= ~3; 841 842 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 843 844 data = __le32_to_cpu(tmp); 845 data >>= (shift * 8); 846 data &= 0xff; 847 848 return (u8)data; 849 } 850 851 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 852 { 853 u32 mask = 0xff; 854 __le32 tmp; 855 u16 byen = BYTE_EN_BYTE; 856 u8 shift = index & 3; 857 858 data &= mask; 859 860 if (index & 3) { 861 byen <<= shift; 862 mask <<= (shift * 8); 863 data <<= (shift * 8); 864 index &= ~3; 865 } 866 867 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 868 869 data |= __le32_to_cpu(tmp) & ~mask; 870 tmp = __cpu_to_le32(data); 871 872 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 873 } 874 875 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 876 { 877 u16 ocp_base, ocp_index; 878 879 ocp_base = addr & 0xf000; 880 if (ocp_base != tp->ocp_base) { 881 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 882 tp->ocp_base = ocp_base; 883 } 884 885 ocp_index = (addr & 0x0fff) | 0xb000; 886 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 887 } 888 889 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 890 { 891 u16 ocp_base, ocp_index; 892 893 ocp_base = addr & 0xf000; 894 if (ocp_base != tp->ocp_base) { 895 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 896 tp->ocp_base = ocp_base; 897 } 898 899 ocp_index = (addr & 0x0fff) | 0xb000; 900 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 901 } 902 903 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 904 { 905 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 906 } 907 908 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 909 { 910 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 911 } 912 913 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 914 { 915 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 916 ocp_reg_write(tp, OCP_SRAM_DATA, data); 917 } 918 919 static u16 sram_read(struct r8152 *tp, u16 addr) 920 { 921 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 922 return ocp_reg_read(tp, OCP_SRAM_DATA); 923 } 924 925 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 926 { 927 struct r8152 *tp = netdev_priv(netdev); 928 int ret; 929 930 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 931 return -ENODEV; 932 933 if (phy_id != R8152_PHY_ID) 934 return -EINVAL; 935 936 ret = usb_autopm_get_interface(tp->intf); 937 if (ret < 0) 938 goto out; 939 940 ret = r8152_mdio_read(tp, reg); 941 942 usb_autopm_put_interface(tp->intf); 943 944 out: 945 return ret; 946 } 947 948 static 949 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 950 { 951 struct r8152 *tp = netdev_priv(netdev); 952 953 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 954 return; 955 956 if (phy_id != R8152_PHY_ID) 957 return; 958 959 if (usb_autopm_get_interface(tp->intf) < 0) 960 return; 961 962 r8152_mdio_write(tp, reg, val); 963 964 usb_autopm_put_interface(tp->intf); 965 } 966 967 static 968 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 969 970 static inline void set_ethernet_addr(struct r8152 *tp) 971 { 972 struct net_device *dev = tp->netdev; 973 int ret; 974 u8 node_id[8] = {0}; 975 976 if (tp->version == RTL_VER_01) 977 ret = pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id); 978 else 979 ret = pla_ocp_read(tp, PLA_BACKUP, sizeof(node_id), node_id); 980 981 if (ret < 0) { 982 netif_notice(tp, probe, dev, "inet addr fail\n"); 983 } else { 984 if (tp->version != RTL_VER_01) { 985 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, 986 CRWECR_CONFIG); 987 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 988 sizeof(node_id), node_id); 989 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, 990 CRWECR_NORAML); 991 } 992 993 memcpy(dev->dev_addr, node_id, dev->addr_len); 994 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 995 } 996 } 997 998 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 999 { 1000 struct r8152 *tp = netdev_priv(netdev); 1001 struct sockaddr *addr = p; 1002 1003 if (!is_valid_ether_addr(addr->sa_data)) 1004 return -EADDRNOTAVAIL; 1005 1006 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1007 1008 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1009 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1010 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1011 1012 return 0; 1013 } 1014 1015 static void read_bulk_callback(struct urb *urb) 1016 { 1017 struct net_device *netdev; 1018 int status = urb->status; 1019 struct rx_agg *agg; 1020 struct r8152 *tp; 1021 int result; 1022 1023 agg = urb->context; 1024 if (!agg) 1025 return; 1026 1027 tp = agg->context; 1028 if (!tp) 1029 return; 1030 1031 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1032 return; 1033 1034 if (!test_bit(WORK_ENABLE, &tp->flags)) 1035 return; 1036 1037 netdev = tp->netdev; 1038 1039 /* When link down, the driver would cancel all bulks. */ 1040 /* This avoid the re-submitting bulk */ 1041 if (!netif_carrier_ok(netdev)) 1042 return; 1043 1044 usb_mark_last_busy(tp->udev); 1045 1046 switch (status) { 1047 case 0: 1048 if (urb->actual_length < ETH_ZLEN) 1049 break; 1050 1051 spin_lock(&tp->rx_lock); 1052 list_add_tail(&agg->list, &tp->rx_done); 1053 spin_unlock(&tp->rx_lock); 1054 tasklet_schedule(&tp->tl); 1055 return; 1056 case -ESHUTDOWN: 1057 set_bit(RTL8152_UNPLUG, &tp->flags); 1058 netif_device_detach(tp->netdev); 1059 return; 1060 case -ENOENT: 1061 return; /* the urb is in unlink state */ 1062 case -ETIME: 1063 if (net_ratelimit()) 1064 netdev_warn(netdev, "maybe reset is needed?\n"); 1065 break; 1066 default: 1067 if (net_ratelimit()) 1068 netdev_warn(netdev, "Rx status %d\n", status); 1069 break; 1070 } 1071 1072 result = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1073 if (result == -ENODEV) { 1074 netif_device_detach(tp->netdev); 1075 } else if (result) { 1076 spin_lock(&tp->rx_lock); 1077 list_add_tail(&agg->list, &tp->rx_done); 1078 spin_unlock(&tp->rx_lock); 1079 tasklet_schedule(&tp->tl); 1080 } 1081 } 1082 1083 static void write_bulk_callback(struct urb *urb) 1084 { 1085 struct net_device_stats *stats; 1086 struct net_device *netdev; 1087 struct tx_agg *agg; 1088 struct r8152 *tp; 1089 int status = urb->status; 1090 1091 agg = urb->context; 1092 if (!agg) 1093 return; 1094 1095 tp = agg->context; 1096 if (!tp) 1097 return; 1098 1099 netdev = tp->netdev; 1100 stats = &netdev->stats; 1101 if (status) { 1102 if (net_ratelimit()) 1103 netdev_warn(netdev, "Tx status %d\n", status); 1104 stats->tx_errors += agg->skb_num; 1105 } else { 1106 stats->tx_packets += agg->skb_num; 1107 stats->tx_bytes += agg->skb_len; 1108 } 1109 1110 spin_lock(&tp->tx_lock); 1111 list_add_tail(&agg->list, &tp->tx_free); 1112 spin_unlock(&tp->tx_lock); 1113 1114 usb_autopm_put_interface_async(tp->intf); 1115 1116 if (!netif_carrier_ok(netdev)) 1117 return; 1118 1119 if (!test_bit(WORK_ENABLE, &tp->flags)) 1120 return; 1121 1122 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1123 return; 1124 1125 if (!skb_queue_empty(&tp->tx_queue)) 1126 tasklet_schedule(&tp->tl); 1127 } 1128 1129 static void intr_callback(struct urb *urb) 1130 { 1131 struct r8152 *tp; 1132 __le16 *d; 1133 int status = urb->status; 1134 int res; 1135 1136 tp = urb->context; 1137 if (!tp) 1138 return; 1139 1140 if (!test_bit(WORK_ENABLE, &tp->flags)) 1141 return; 1142 1143 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1144 return; 1145 1146 switch (status) { 1147 case 0: /* success */ 1148 break; 1149 case -ECONNRESET: /* unlink */ 1150 case -ESHUTDOWN: 1151 netif_device_detach(tp->netdev); 1152 case -ENOENT: 1153 return; 1154 case -EOVERFLOW: 1155 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1156 goto resubmit; 1157 /* -EPIPE: should clear the halt */ 1158 default: 1159 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1160 goto resubmit; 1161 } 1162 1163 d = urb->transfer_buffer; 1164 if (INTR_LINK & __le16_to_cpu(d[0])) { 1165 if (!(tp->speed & LINK_STATUS)) { 1166 set_bit(RTL8152_LINK_CHG, &tp->flags); 1167 schedule_delayed_work(&tp->schedule, 0); 1168 } 1169 } else { 1170 if (tp->speed & LINK_STATUS) { 1171 set_bit(RTL8152_LINK_CHG, &tp->flags); 1172 schedule_delayed_work(&tp->schedule, 0); 1173 } 1174 } 1175 1176 resubmit: 1177 res = usb_submit_urb(urb, GFP_ATOMIC); 1178 if (res == -ENODEV) 1179 netif_device_detach(tp->netdev); 1180 else if (res) 1181 netif_err(tp, intr, tp->netdev, 1182 "can't resubmit intr, status %d\n", res); 1183 } 1184 1185 static inline void *rx_agg_align(void *data) 1186 { 1187 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1188 } 1189 1190 static inline void *tx_agg_align(void *data) 1191 { 1192 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1193 } 1194 1195 static void free_all_mem(struct r8152 *tp) 1196 { 1197 int i; 1198 1199 for (i = 0; i < RTL8152_MAX_RX; i++) { 1200 usb_free_urb(tp->rx_info[i].urb); 1201 tp->rx_info[i].urb = NULL; 1202 1203 kfree(tp->rx_info[i].buffer); 1204 tp->rx_info[i].buffer = NULL; 1205 tp->rx_info[i].head = NULL; 1206 } 1207 1208 for (i = 0; i < RTL8152_MAX_TX; i++) { 1209 usb_free_urb(tp->tx_info[i].urb); 1210 tp->tx_info[i].urb = NULL; 1211 1212 kfree(tp->tx_info[i].buffer); 1213 tp->tx_info[i].buffer = NULL; 1214 tp->tx_info[i].head = NULL; 1215 } 1216 1217 usb_free_urb(tp->intr_urb); 1218 tp->intr_urb = NULL; 1219 1220 kfree(tp->intr_buff); 1221 tp->intr_buff = NULL; 1222 } 1223 1224 static int alloc_all_mem(struct r8152 *tp) 1225 { 1226 struct net_device *netdev = tp->netdev; 1227 struct usb_interface *intf = tp->intf; 1228 struct usb_host_interface *alt = intf->cur_altsetting; 1229 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1230 struct urb *urb; 1231 int node, i; 1232 u8 *buf; 1233 1234 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1235 1236 spin_lock_init(&tp->rx_lock); 1237 spin_lock_init(&tp->tx_lock); 1238 INIT_LIST_HEAD(&tp->rx_done); 1239 INIT_LIST_HEAD(&tp->tx_free); 1240 skb_queue_head_init(&tp->tx_queue); 1241 1242 for (i = 0; i < RTL8152_MAX_RX; i++) { 1243 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); 1244 if (!buf) 1245 goto err1; 1246 1247 if (buf != rx_agg_align(buf)) { 1248 kfree(buf); 1249 buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL, 1250 node); 1251 if (!buf) 1252 goto err1; 1253 } 1254 1255 urb = usb_alloc_urb(0, GFP_KERNEL); 1256 if (!urb) { 1257 kfree(buf); 1258 goto err1; 1259 } 1260 1261 INIT_LIST_HEAD(&tp->rx_info[i].list); 1262 tp->rx_info[i].context = tp; 1263 tp->rx_info[i].urb = urb; 1264 tp->rx_info[i].buffer = buf; 1265 tp->rx_info[i].head = rx_agg_align(buf); 1266 } 1267 1268 for (i = 0; i < RTL8152_MAX_TX; i++) { 1269 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); 1270 if (!buf) 1271 goto err1; 1272 1273 if (buf != tx_agg_align(buf)) { 1274 kfree(buf); 1275 buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL, 1276 node); 1277 if (!buf) 1278 goto err1; 1279 } 1280 1281 urb = usb_alloc_urb(0, GFP_KERNEL); 1282 if (!urb) { 1283 kfree(buf); 1284 goto err1; 1285 } 1286 1287 INIT_LIST_HEAD(&tp->tx_info[i].list); 1288 tp->tx_info[i].context = tp; 1289 tp->tx_info[i].urb = urb; 1290 tp->tx_info[i].buffer = buf; 1291 tp->tx_info[i].head = tx_agg_align(buf); 1292 1293 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1294 } 1295 1296 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1297 if (!tp->intr_urb) 1298 goto err1; 1299 1300 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1301 if (!tp->intr_buff) 1302 goto err1; 1303 1304 tp->intr_interval = (int)ep_intr->desc.bInterval; 1305 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1306 tp->intr_buff, INTBUFSIZE, intr_callback, 1307 tp, tp->intr_interval); 1308 1309 return 0; 1310 1311 err1: 1312 free_all_mem(tp); 1313 return -ENOMEM; 1314 } 1315 1316 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1317 { 1318 struct tx_agg *agg = NULL; 1319 unsigned long flags; 1320 1321 if (list_empty(&tp->tx_free)) 1322 return NULL; 1323 1324 spin_lock_irqsave(&tp->tx_lock, flags); 1325 if (!list_empty(&tp->tx_free)) { 1326 struct list_head *cursor; 1327 1328 cursor = tp->tx_free.next; 1329 list_del_init(cursor); 1330 agg = list_entry(cursor, struct tx_agg, list); 1331 } 1332 spin_unlock_irqrestore(&tp->tx_lock, flags); 1333 1334 return agg; 1335 } 1336 1337 static inline __be16 get_protocol(struct sk_buff *skb) 1338 { 1339 __be16 protocol; 1340 1341 if (skb->protocol == htons(ETH_P_8021Q)) 1342 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; 1343 else 1344 protocol = skb->protocol; 1345 1346 return protocol; 1347 } 1348 1349 /* 1350 * r8152_csum_workaround() 1351 * The hw limites the value the transport offset. When the offset is out of the 1352 * range, calculate the checksum by sw. 1353 */ 1354 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1355 struct sk_buff_head *list) 1356 { 1357 if (skb_shinfo(skb)->gso_size) { 1358 netdev_features_t features = tp->netdev->features; 1359 struct sk_buff_head seg_list; 1360 struct sk_buff *segs, *nskb; 1361 1362 features &= ~(NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO); 1363 segs = skb_gso_segment(skb, features); 1364 if (IS_ERR(segs) || !segs) 1365 goto drop; 1366 1367 __skb_queue_head_init(&seg_list); 1368 1369 do { 1370 nskb = segs; 1371 segs = segs->next; 1372 nskb->next = NULL; 1373 __skb_queue_tail(&seg_list, nskb); 1374 } while (segs); 1375 1376 skb_queue_splice(&seg_list, list); 1377 dev_kfree_skb(skb); 1378 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1379 if (skb_checksum_help(skb) < 0) 1380 goto drop; 1381 1382 __skb_queue_head(list, skb); 1383 } else { 1384 struct net_device_stats *stats; 1385 1386 drop: 1387 stats = &tp->netdev->stats; 1388 stats->tx_dropped++; 1389 dev_kfree_skb(skb); 1390 } 1391 } 1392 1393 /* 1394 * msdn_giant_send_check() 1395 * According to the document of microsoft, the TCP Pseudo Header excludes the 1396 * packet length for IPv6 TCP large packets. 1397 */ 1398 static int msdn_giant_send_check(struct sk_buff *skb) 1399 { 1400 const struct ipv6hdr *ipv6h; 1401 struct tcphdr *th; 1402 int ret; 1403 1404 ret = skb_cow_head(skb, 0); 1405 if (ret) 1406 return ret; 1407 1408 ipv6h = ipv6_hdr(skb); 1409 th = tcp_hdr(skb); 1410 1411 th->check = 0; 1412 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1413 1414 return ret; 1415 } 1416 1417 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1418 struct sk_buff *skb, u32 len, u32 transport_offset) 1419 { 1420 u32 mss = skb_shinfo(skb)->gso_size; 1421 u32 opts1, opts2 = 0; 1422 int ret = TX_CSUM_SUCCESS; 1423 1424 WARN_ON_ONCE(len > TX_LEN_MAX); 1425 1426 opts1 = len | TX_FS | TX_LS; 1427 1428 if (mss) { 1429 if (transport_offset > GTTCPHO_MAX) { 1430 netif_warn(tp, tx_err, tp->netdev, 1431 "Invalid transport offset 0x%x for TSO\n", 1432 transport_offset); 1433 ret = TX_CSUM_TSO; 1434 goto unavailable; 1435 } 1436 1437 switch (get_protocol(skb)) { 1438 case htons(ETH_P_IP): 1439 opts1 |= GTSENDV4; 1440 break; 1441 1442 case htons(ETH_P_IPV6): 1443 if (msdn_giant_send_check(skb)) { 1444 ret = TX_CSUM_TSO; 1445 goto unavailable; 1446 } 1447 opts1 |= GTSENDV6; 1448 break; 1449 1450 default: 1451 WARN_ON_ONCE(1); 1452 break; 1453 } 1454 1455 opts1 |= transport_offset << GTTCPHO_SHIFT; 1456 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1457 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1458 u8 ip_protocol; 1459 1460 if (transport_offset > TCPHO_MAX) { 1461 netif_warn(tp, tx_err, tp->netdev, 1462 "Invalid transport offset 0x%x\n", 1463 transport_offset); 1464 ret = TX_CSUM_NONE; 1465 goto unavailable; 1466 } 1467 1468 switch (get_protocol(skb)) { 1469 case htons(ETH_P_IP): 1470 opts2 |= IPV4_CS; 1471 ip_protocol = ip_hdr(skb)->protocol; 1472 break; 1473 1474 case htons(ETH_P_IPV6): 1475 opts2 |= IPV6_CS; 1476 ip_protocol = ipv6_hdr(skb)->nexthdr; 1477 break; 1478 1479 default: 1480 ip_protocol = IPPROTO_RAW; 1481 break; 1482 } 1483 1484 if (ip_protocol == IPPROTO_TCP) 1485 opts2 |= TCP_CS; 1486 else if (ip_protocol == IPPROTO_UDP) 1487 opts2 |= UDP_CS; 1488 else 1489 WARN_ON_ONCE(1); 1490 1491 opts2 |= transport_offset << TCPHO_SHIFT; 1492 } 1493 1494 desc->opts2 = cpu_to_le32(opts2); 1495 desc->opts1 = cpu_to_le32(opts1); 1496 1497 unavailable: 1498 return ret; 1499 } 1500 1501 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1502 { 1503 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1504 int remain, ret; 1505 u8 *tx_data; 1506 1507 __skb_queue_head_init(&skb_head); 1508 spin_lock(&tx_queue->lock); 1509 skb_queue_splice_init(tx_queue, &skb_head); 1510 spin_unlock(&tx_queue->lock); 1511 1512 tx_data = agg->head; 1513 agg->skb_num = agg->skb_len = 0; 1514 remain = rx_buf_sz; 1515 1516 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1517 struct tx_desc *tx_desc; 1518 struct sk_buff *skb; 1519 unsigned int len; 1520 u32 offset; 1521 1522 skb = __skb_dequeue(&skb_head); 1523 if (!skb) 1524 break; 1525 1526 len = skb->len + sizeof(*tx_desc); 1527 1528 if (len > remain) { 1529 __skb_queue_head(&skb_head, skb); 1530 break; 1531 } 1532 1533 tx_data = tx_agg_align(tx_data); 1534 tx_desc = (struct tx_desc *)tx_data; 1535 1536 offset = (u32)skb_transport_offset(skb); 1537 1538 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1539 r8152_csum_workaround(tp, skb, &skb_head); 1540 continue; 1541 } 1542 1543 tx_data += sizeof(*tx_desc); 1544 1545 len = skb->len; 1546 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1547 struct net_device_stats *stats = &tp->netdev->stats; 1548 1549 stats->tx_dropped++; 1550 dev_kfree_skb_any(skb); 1551 tx_data -= sizeof(*tx_desc); 1552 continue; 1553 } 1554 1555 tx_data += len; 1556 agg->skb_len += len; 1557 agg->skb_num++; 1558 1559 dev_kfree_skb_any(skb); 1560 1561 remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1562 } 1563 1564 if (!skb_queue_empty(&skb_head)) { 1565 spin_lock(&tx_queue->lock); 1566 skb_queue_splice(&skb_head, tx_queue); 1567 spin_unlock(&tx_queue->lock); 1568 } 1569 1570 netif_tx_lock(tp->netdev); 1571 1572 if (netif_queue_stopped(tp->netdev) && 1573 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1574 netif_wake_queue(tp->netdev); 1575 1576 netif_tx_unlock(tp->netdev); 1577 1578 ret = usb_autopm_get_interface_async(tp->intf); 1579 if (ret < 0) 1580 goto out_tx_fill; 1581 1582 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1583 agg->head, (int)(tx_data - (u8 *)agg->head), 1584 (usb_complete_t)write_bulk_callback, agg); 1585 1586 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1587 if (ret < 0) 1588 usb_autopm_put_interface_async(tp->intf); 1589 1590 out_tx_fill: 1591 return ret; 1592 } 1593 1594 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1595 { 1596 u8 checksum = CHECKSUM_NONE; 1597 u32 opts2, opts3; 1598 1599 if (tp->version == RTL_VER_01) 1600 goto return_result; 1601 1602 opts2 = le32_to_cpu(rx_desc->opts2); 1603 opts3 = le32_to_cpu(rx_desc->opts3); 1604 1605 if (opts2 & RD_IPV4_CS) { 1606 if (opts3 & IPF) 1607 checksum = CHECKSUM_NONE; 1608 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) 1609 checksum = CHECKSUM_NONE; 1610 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) 1611 checksum = CHECKSUM_NONE; 1612 else 1613 checksum = CHECKSUM_UNNECESSARY; 1614 } else if (RD_IPV6_CS) { 1615 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1616 checksum = CHECKSUM_UNNECESSARY; 1617 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1618 checksum = CHECKSUM_UNNECESSARY; 1619 } 1620 1621 return_result: 1622 return checksum; 1623 } 1624 1625 static void rx_bottom(struct r8152 *tp) 1626 { 1627 unsigned long flags; 1628 struct list_head *cursor, *next, rx_queue; 1629 1630 if (list_empty(&tp->rx_done)) 1631 return; 1632 1633 INIT_LIST_HEAD(&rx_queue); 1634 spin_lock_irqsave(&tp->rx_lock, flags); 1635 list_splice_init(&tp->rx_done, &rx_queue); 1636 spin_unlock_irqrestore(&tp->rx_lock, flags); 1637 1638 list_for_each_safe(cursor, next, &rx_queue) { 1639 struct rx_desc *rx_desc; 1640 struct rx_agg *agg; 1641 int len_used = 0; 1642 struct urb *urb; 1643 u8 *rx_data; 1644 int ret; 1645 1646 list_del_init(cursor); 1647 1648 agg = list_entry(cursor, struct rx_agg, list); 1649 urb = agg->urb; 1650 if (urb->actual_length < ETH_ZLEN) 1651 goto submit; 1652 1653 rx_desc = agg->head; 1654 rx_data = agg->head; 1655 len_used += sizeof(struct rx_desc); 1656 1657 while (urb->actual_length > len_used) { 1658 struct net_device *netdev = tp->netdev; 1659 struct net_device_stats *stats = &netdev->stats; 1660 unsigned int pkt_len; 1661 struct sk_buff *skb; 1662 1663 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1664 if (pkt_len < ETH_ZLEN) 1665 break; 1666 1667 len_used += pkt_len; 1668 if (urb->actual_length < len_used) 1669 break; 1670 1671 pkt_len -= CRC_SIZE; 1672 rx_data += sizeof(struct rx_desc); 1673 1674 skb = netdev_alloc_skb_ip_align(netdev, pkt_len); 1675 if (!skb) { 1676 stats->rx_dropped++; 1677 goto find_next_rx; 1678 } 1679 1680 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 1681 memcpy(skb->data, rx_data, pkt_len); 1682 skb_put(skb, pkt_len); 1683 skb->protocol = eth_type_trans(skb, netdev); 1684 netif_receive_skb(skb); 1685 stats->rx_packets++; 1686 stats->rx_bytes += pkt_len; 1687 1688 find_next_rx: 1689 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); 1690 rx_desc = (struct rx_desc *)rx_data; 1691 len_used = (int)(rx_data - (u8 *)agg->head); 1692 len_used += sizeof(struct rx_desc); 1693 } 1694 1695 submit: 1696 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1697 if (ret && ret != -ENODEV) { 1698 spin_lock_irqsave(&tp->rx_lock, flags); 1699 list_add_tail(&agg->list, &tp->rx_done); 1700 spin_unlock_irqrestore(&tp->rx_lock, flags); 1701 tasklet_schedule(&tp->tl); 1702 } 1703 } 1704 } 1705 1706 static void tx_bottom(struct r8152 *tp) 1707 { 1708 int res; 1709 1710 do { 1711 struct tx_agg *agg; 1712 1713 if (skb_queue_empty(&tp->tx_queue)) 1714 break; 1715 1716 agg = r8152_get_tx_agg(tp); 1717 if (!agg) 1718 break; 1719 1720 res = r8152_tx_agg_fill(tp, agg); 1721 if (res) { 1722 struct net_device *netdev = tp->netdev; 1723 1724 if (res == -ENODEV) { 1725 netif_device_detach(netdev); 1726 } else { 1727 struct net_device_stats *stats = &netdev->stats; 1728 unsigned long flags; 1729 1730 netif_warn(tp, tx_err, netdev, 1731 "failed tx_urb %d\n", res); 1732 stats->tx_dropped += agg->skb_num; 1733 1734 spin_lock_irqsave(&tp->tx_lock, flags); 1735 list_add_tail(&agg->list, &tp->tx_free); 1736 spin_unlock_irqrestore(&tp->tx_lock, flags); 1737 } 1738 } 1739 } while (res == 0); 1740 } 1741 1742 static void bottom_half(unsigned long data) 1743 { 1744 struct r8152 *tp; 1745 1746 tp = (struct r8152 *)data; 1747 1748 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1749 return; 1750 1751 if (!test_bit(WORK_ENABLE, &tp->flags)) 1752 return; 1753 1754 /* When link down, the driver would cancel all bulks. */ 1755 /* This avoid the re-submitting bulk */ 1756 if (!netif_carrier_ok(tp->netdev)) 1757 return; 1758 1759 rx_bottom(tp); 1760 tx_bottom(tp); 1761 } 1762 1763 static 1764 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 1765 { 1766 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 1767 agg->head, rx_buf_sz, 1768 (usb_complete_t)read_bulk_callback, agg); 1769 1770 return usb_submit_urb(agg->urb, mem_flags); 1771 } 1772 1773 static void rtl_drop_queued_tx(struct r8152 *tp) 1774 { 1775 struct net_device_stats *stats = &tp->netdev->stats; 1776 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1777 struct sk_buff *skb; 1778 1779 if (skb_queue_empty(tx_queue)) 1780 return; 1781 1782 __skb_queue_head_init(&skb_head); 1783 spin_lock_bh(&tx_queue->lock); 1784 skb_queue_splice_init(tx_queue, &skb_head); 1785 spin_unlock_bh(&tx_queue->lock); 1786 1787 while ((skb = __skb_dequeue(&skb_head))) { 1788 dev_kfree_skb(skb); 1789 stats->tx_dropped++; 1790 } 1791 } 1792 1793 static void rtl8152_tx_timeout(struct net_device *netdev) 1794 { 1795 struct r8152 *tp = netdev_priv(netdev); 1796 int i; 1797 1798 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 1799 for (i = 0; i < RTL8152_MAX_TX; i++) 1800 usb_unlink_urb(tp->tx_info[i].urb); 1801 } 1802 1803 static void rtl8152_set_rx_mode(struct net_device *netdev) 1804 { 1805 struct r8152 *tp = netdev_priv(netdev); 1806 1807 if (tp->speed & LINK_STATUS) { 1808 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 1809 schedule_delayed_work(&tp->schedule, 0); 1810 } 1811 } 1812 1813 static void _rtl8152_set_rx_mode(struct net_device *netdev) 1814 { 1815 struct r8152 *tp = netdev_priv(netdev); 1816 u32 mc_filter[2]; /* Multicast hash filter */ 1817 __le32 tmp[2]; 1818 u32 ocp_data; 1819 1820 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 1821 netif_stop_queue(netdev); 1822 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 1823 ocp_data &= ~RCR_ACPT_ALL; 1824 ocp_data |= RCR_AB | RCR_APM; 1825 1826 if (netdev->flags & IFF_PROMISC) { 1827 /* Unconditionally log net taps. */ 1828 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 1829 ocp_data |= RCR_AM | RCR_AAP; 1830 mc_filter[1] = mc_filter[0] = 0xffffffff; 1831 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 1832 (netdev->flags & IFF_ALLMULTI)) { 1833 /* Too many to filter perfectly -- accept all multicasts. */ 1834 ocp_data |= RCR_AM; 1835 mc_filter[1] = mc_filter[0] = 0xffffffff; 1836 } else { 1837 struct netdev_hw_addr *ha; 1838 1839 mc_filter[1] = mc_filter[0] = 0; 1840 netdev_for_each_mc_addr(ha, netdev) { 1841 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 1842 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 1843 ocp_data |= RCR_AM; 1844 } 1845 } 1846 1847 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 1848 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 1849 1850 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 1851 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 1852 netif_wake_queue(netdev); 1853 } 1854 1855 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 1856 struct net_device *netdev) 1857 { 1858 struct r8152 *tp = netdev_priv(netdev); 1859 1860 skb_tx_timestamp(skb); 1861 1862 skb_queue_tail(&tp->tx_queue, skb); 1863 1864 if (!list_empty(&tp->tx_free)) { 1865 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 1866 set_bit(SCHEDULE_TASKLET, &tp->flags); 1867 schedule_delayed_work(&tp->schedule, 0); 1868 } else { 1869 usb_mark_last_busy(tp->udev); 1870 tasklet_schedule(&tp->tl); 1871 } 1872 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) 1873 netif_stop_queue(netdev); 1874 1875 return NETDEV_TX_OK; 1876 } 1877 1878 static void r8152b_reset_packet_filter(struct r8152 *tp) 1879 { 1880 u32 ocp_data; 1881 1882 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 1883 ocp_data &= ~FMC_FCR_MCU_EN; 1884 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 1885 ocp_data |= FMC_FCR_MCU_EN; 1886 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 1887 } 1888 1889 static void rtl8152_nic_reset(struct r8152 *tp) 1890 { 1891 int i; 1892 1893 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 1894 1895 for (i = 0; i < 1000; i++) { 1896 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 1897 break; 1898 udelay(100); 1899 } 1900 } 1901 1902 static void set_tx_qlen(struct r8152 *tp) 1903 { 1904 struct net_device *netdev = tp->netdev; 1905 1906 tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + 1907 sizeof(struct tx_desc)); 1908 } 1909 1910 static inline u8 rtl8152_get_speed(struct r8152 *tp) 1911 { 1912 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 1913 } 1914 1915 static void rtl_set_eee_plus(struct r8152 *tp) 1916 { 1917 u32 ocp_data; 1918 u8 speed; 1919 1920 speed = rtl8152_get_speed(tp); 1921 if (speed & _10bps) { 1922 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 1923 ocp_data |= EEEP_CR_EEEP_TX; 1924 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 1925 } else { 1926 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 1927 ocp_data &= ~EEEP_CR_EEEP_TX; 1928 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 1929 } 1930 } 1931 1932 static void rxdy_gated_en(struct r8152 *tp, bool enable) 1933 { 1934 u32 ocp_data; 1935 1936 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 1937 if (enable) 1938 ocp_data |= RXDY_GATED_EN; 1939 else 1940 ocp_data &= ~RXDY_GATED_EN; 1941 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 1942 } 1943 1944 static int rtl_enable(struct r8152 *tp) 1945 { 1946 u32 ocp_data; 1947 int i, ret; 1948 1949 r8152b_reset_packet_filter(tp); 1950 1951 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 1952 ocp_data |= CR_RE | CR_TE; 1953 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 1954 1955 rxdy_gated_en(tp, false); 1956 1957 INIT_LIST_HEAD(&tp->rx_done); 1958 ret = 0; 1959 for (i = 0; i < RTL8152_MAX_RX; i++) { 1960 INIT_LIST_HEAD(&tp->rx_info[i].list); 1961 ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 1962 } 1963 1964 return ret; 1965 } 1966 1967 static int rtl8152_enable(struct r8152 *tp) 1968 { 1969 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1970 return -ENODEV; 1971 1972 set_tx_qlen(tp); 1973 rtl_set_eee_plus(tp); 1974 1975 return rtl_enable(tp); 1976 } 1977 1978 static void r8153_set_rx_agg(struct r8152 *tp) 1979 { 1980 u8 speed; 1981 1982 speed = rtl8152_get_speed(tp); 1983 if (speed & _1000bps) { 1984 if (tp->udev->speed == USB_SPEED_SUPER) { 1985 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 1986 RX_THR_SUPPER); 1987 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, 1988 EARLY_AGG_SUPPER); 1989 } else { 1990 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 1991 RX_THR_HIGH); 1992 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, 1993 EARLY_AGG_HIGH); 1994 } 1995 } else { 1996 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW); 1997 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, 1998 EARLY_AGG_SLOW); 1999 } 2000 } 2001 2002 static int rtl8153_enable(struct r8152 *tp) 2003 { 2004 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2005 return -ENODEV; 2006 2007 set_tx_qlen(tp); 2008 rtl_set_eee_plus(tp); 2009 r8153_set_rx_agg(tp); 2010 2011 return rtl_enable(tp); 2012 } 2013 2014 static void rtl8152_disable(struct r8152 *tp) 2015 { 2016 u32 ocp_data; 2017 int i; 2018 2019 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2020 rtl_drop_queued_tx(tp); 2021 return; 2022 } 2023 2024 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2025 ocp_data &= ~RCR_ACPT_ALL; 2026 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2027 2028 rtl_drop_queued_tx(tp); 2029 2030 for (i = 0; i < RTL8152_MAX_TX; i++) 2031 usb_kill_urb(tp->tx_info[i].urb); 2032 2033 rxdy_gated_en(tp, true); 2034 2035 for (i = 0; i < 1000; i++) { 2036 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2037 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2038 break; 2039 mdelay(1); 2040 } 2041 2042 for (i = 0; i < 1000; i++) { 2043 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2044 break; 2045 mdelay(1); 2046 } 2047 2048 for (i = 0; i < RTL8152_MAX_RX; i++) 2049 usb_kill_urb(tp->rx_info[i].urb); 2050 2051 rtl8152_nic_reset(tp); 2052 } 2053 2054 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2055 { 2056 u32 ocp_data; 2057 2058 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2059 if (enable) 2060 ocp_data |= POWER_CUT; 2061 else 2062 ocp_data &= ~POWER_CUT; 2063 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2064 2065 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2066 ocp_data &= ~RESUME_INDICATE; 2067 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2068 } 2069 2070 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2071 2072 static u32 __rtl_get_wol(struct r8152 *tp) 2073 { 2074 u32 ocp_data; 2075 u32 wolopts = 0; 2076 2077 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2078 if (!(ocp_data & LAN_WAKE_EN)) 2079 return 0; 2080 2081 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2082 if (ocp_data & LINK_ON_WAKE_EN) 2083 wolopts |= WAKE_PHY; 2084 2085 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2086 if (ocp_data & UWF_EN) 2087 wolopts |= WAKE_UCAST; 2088 if (ocp_data & BWF_EN) 2089 wolopts |= WAKE_BCAST; 2090 if (ocp_data & MWF_EN) 2091 wolopts |= WAKE_MCAST; 2092 2093 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2094 if (ocp_data & MAGIC_EN) 2095 wolopts |= WAKE_MAGIC; 2096 2097 return wolopts; 2098 } 2099 2100 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2101 { 2102 u32 ocp_data; 2103 2104 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2105 2106 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2107 ocp_data &= ~LINK_ON_WAKE_EN; 2108 if (wolopts & WAKE_PHY) 2109 ocp_data |= LINK_ON_WAKE_EN; 2110 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2111 2112 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2113 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN); 2114 if (wolopts & WAKE_UCAST) 2115 ocp_data |= UWF_EN; 2116 if (wolopts & WAKE_BCAST) 2117 ocp_data |= BWF_EN; 2118 if (wolopts & WAKE_MCAST) 2119 ocp_data |= MWF_EN; 2120 if (wolopts & WAKE_ANY) 2121 ocp_data |= LAN_WAKE_EN; 2122 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2123 2124 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2125 2126 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2127 ocp_data &= ~MAGIC_EN; 2128 if (wolopts & WAKE_MAGIC) 2129 ocp_data |= MAGIC_EN; 2130 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2131 2132 if (wolopts & WAKE_ANY) 2133 device_set_wakeup_enable(&tp->udev->dev, true); 2134 else 2135 device_set_wakeup_enable(&tp->udev->dev, false); 2136 } 2137 2138 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 2139 { 2140 if (enable) { 2141 u32 ocp_data; 2142 2143 __rtl_set_wol(tp, WAKE_ANY); 2144 2145 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2146 2147 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2148 ocp_data |= LINK_OFF_WAKE_EN; 2149 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2150 2151 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2152 } else { 2153 __rtl_set_wol(tp, tp->saved_wolopts); 2154 } 2155 } 2156 2157 static void rtl_phy_reset(struct r8152 *tp) 2158 { 2159 u16 data; 2160 int i; 2161 2162 clear_bit(PHY_RESET, &tp->flags); 2163 2164 data = r8152_mdio_read(tp, MII_BMCR); 2165 2166 /* don't reset again before the previous one complete */ 2167 if (data & BMCR_RESET) 2168 return; 2169 2170 data |= BMCR_RESET; 2171 r8152_mdio_write(tp, MII_BMCR, data); 2172 2173 for (i = 0; i < 50; i++) { 2174 msleep(20); 2175 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 2176 break; 2177 } 2178 } 2179 2180 static void rtl_clear_bp(struct r8152 *tp) 2181 { 2182 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0); 2183 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0); 2184 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0); 2185 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0); 2186 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0); 2187 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0); 2188 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0); 2189 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0); 2190 mdelay(3); 2191 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0); 2192 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0); 2193 } 2194 2195 static void r8153_clear_bp(struct r8152 *tp) 2196 { 2197 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0); 2198 ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0); 2199 rtl_clear_bp(tp); 2200 } 2201 2202 static void r8153_teredo_off(struct r8152 *tp) 2203 { 2204 u32 ocp_data; 2205 2206 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2207 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); 2208 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2209 2210 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 2211 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 2212 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 2213 } 2214 2215 static void r8152b_disable_aldps(struct r8152 *tp) 2216 { 2217 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); 2218 msleep(20); 2219 } 2220 2221 static inline void r8152b_enable_aldps(struct r8152 *tp) 2222 { 2223 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 2224 LINKENA | DIS_SDSAVE); 2225 } 2226 2227 static void r8152b_hw_phy_cfg(struct r8152 *tp) 2228 { 2229 u16 data; 2230 2231 data = r8152_mdio_read(tp, MII_BMCR); 2232 if (data & BMCR_PDOWN) { 2233 data &= ~BMCR_PDOWN; 2234 r8152_mdio_write(tp, MII_BMCR, data); 2235 } 2236 2237 r8152b_disable_aldps(tp); 2238 2239 rtl_clear_bp(tp); 2240 2241 r8152b_enable_aldps(tp); 2242 set_bit(PHY_RESET, &tp->flags); 2243 } 2244 2245 static void r8152b_exit_oob(struct r8152 *tp) 2246 { 2247 u32 ocp_data; 2248 int i; 2249 2250 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2251 return; 2252 2253 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2254 ocp_data &= ~RCR_ACPT_ALL; 2255 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2256 2257 rxdy_gated_en(tp, true); 2258 r8153_teredo_off(tp); 2259 r8152b_hw_phy_cfg(tp); 2260 2261 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2262 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 2263 2264 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2265 ocp_data &= ~NOW_IS_OOB; 2266 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2267 2268 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2269 ocp_data &= ~MCU_BORW_EN; 2270 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2271 2272 for (i = 0; i < 1000; i++) { 2273 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2274 if (ocp_data & LINK_LIST_READY) 2275 break; 2276 mdelay(1); 2277 } 2278 2279 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2280 ocp_data |= RE_INIT_LL; 2281 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2282 2283 for (i = 0; i < 1000; i++) { 2284 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2285 if (ocp_data & LINK_LIST_READY) 2286 break; 2287 mdelay(1); 2288 } 2289 2290 rtl8152_nic_reset(tp); 2291 2292 /* rx share fifo credit full threshold */ 2293 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2294 2295 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT); 2296 ocp_data &= STAT_SPEED_MASK; 2297 if (ocp_data == STAT_SPEED_FULL) { 2298 /* rx share fifo credit near full threshold */ 2299 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2300 RXFIFO_THR2_FULL); 2301 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2302 RXFIFO_THR3_FULL); 2303 } else { 2304 /* rx share fifo credit near full threshold */ 2305 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2306 RXFIFO_THR2_HIGH); 2307 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2308 RXFIFO_THR3_HIGH); 2309 } 2310 2311 /* TX share fifo free credit full threshold */ 2312 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 2313 2314 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 2315 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 2316 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 2317 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 2318 2319 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2320 ocp_data &= ~CPCR_RX_VLAN; 2321 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2322 2323 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2324 2325 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2326 ocp_data |= TCR0_AUTO_FIFO; 2327 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2328 } 2329 2330 static void r8152b_enter_oob(struct r8152 *tp) 2331 { 2332 u32 ocp_data; 2333 int i; 2334 2335 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2336 ocp_data &= ~NOW_IS_OOB; 2337 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2338 2339 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 2340 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 2341 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 2342 2343 rtl8152_disable(tp); 2344 2345 for (i = 0; i < 1000; i++) { 2346 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2347 if (ocp_data & LINK_LIST_READY) 2348 break; 2349 mdelay(1); 2350 } 2351 2352 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2353 ocp_data |= RE_INIT_LL; 2354 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2355 2356 for (i = 0; i < 1000; i++) { 2357 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2358 if (ocp_data & LINK_LIST_READY) 2359 break; 2360 mdelay(1); 2361 } 2362 2363 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2364 2365 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2366 ocp_data |= CPCR_RX_VLAN; 2367 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2368 2369 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2370 ocp_data |= ALDPS_PROXY_MODE; 2371 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2372 2373 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2374 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2375 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2376 2377 rxdy_gated_en(tp, false); 2378 2379 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2380 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2381 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2382 } 2383 2384 static void r8153_hw_phy_cfg(struct r8152 *tp) 2385 { 2386 u32 ocp_data; 2387 u16 data; 2388 2389 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 2390 data = r8152_mdio_read(tp, MII_BMCR); 2391 if (data & BMCR_PDOWN) { 2392 data &= ~BMCR_PDOWN; 2393 r8152_mdio_write(tp, MII_BMCR, data); 2394 } 2395 2396 r8153_clear_bp(tp); 2397 2398 if (tp->version == RTL_VER_03) { 2399 data = ocp_reg_read(tp, OCP_EEE_CFG); 2400 data &= ~CTAP_SHORT_EN; 2401 ocp_reg_write(tp, OCP_EEE_CFG, data); 2402 } 2403 2404 data = ocp_reg_read(tp, OCP_POWER_CFG); 2405 data |= EEE_CLKDIV_EN; 2406 ocp_reg_write(tp, OCP_POWER_CFG, data); 2407 2408 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 2409 data |= EN_10M_BGOFF; 2410 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 2411 data = ocp_reg_read(tp, OCP_POWER_CFG); 2412 data |= EN_10M_PLLOFF; 2413 ocp_reg_write(tp, OCP_POWER_CFG, data); 2414 data = sram_read(tp, SRAM_IMPEDANCE); 2415 data &= ~RX_DRIVING_MASK; 2416 sram_write(tp, SRAM_IMPEDANCE, data); 2417 2418 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 2419 ocp_data |= PFM_PWM_SWITCH; 2420 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 2421 2422 data = sram_read(tp, SRAM_LPF_CFG); 2423 data |= LPF_AUTO_TUNE; 2424 sram_write(tp, SRAM_LPF_CFG, data); 2425 2426 data = sram_read(tp, SRAM_10M_AMP1); 2427 data |= GDAC_IB_UPALL; 2428 sram_write(tp, SRAM_10M_AMP1, data); 2429 data = sram_read(tp, SRAM_10M_AMP2); 2430 data |= AMP_DN; 2431 sram_write(tp, SRAM_10M_AMP2, data); 2432 2433 set_bit(PHY_RESET, &tp->flags); 2434 } 2435 2436 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2437 { 2438 u8 u1u2[8]; 2439 2440 if (enable) 2441 memset(u1u2, 0xff, sizeof(u1u2)); 2442 else 2443 memset(u1u2, 0x00, sizeof(u1u2)); 2444 2445 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2446 } 2447 2448 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2449 { 2450 u32 ocp_data; 2451 2452 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2453 if (enable) 2454 ocp_data |= U2P3_ENABLE; 2455 else 2456 ocp_data &= ~U2P3_ENABLE; 2457 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2458 } 2459 2460 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2461 { 2462 u32 ocp_data; 2463 2464 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2465 if (enable) 2466 ocp_data |= PWR_EN | PHASE2_EN; 2467 else 2468 ocp_data &= ~(PWR_EN | PHASE2_EN); 2469 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2470 2471 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2472 ocp_data &= ~PCUT_STATUS; 2473 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2474 } 2475 2476 static void r8153_first_init(struct r8152 *tp) 2477 { 2478 u32 ocp_data; 2479 int i; 2480 2481 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2482 return; 2483 2484 rxdy_gated_en(tp, true); 2485 r8153_teredo_off(tp); 2486 2487 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2488 ocp_data &= ~RCR_ACPT_ALL; 2489 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2490 2491 r8153_hw_phy_cfg(tp); 2492 2493 rtl8152_nic_reset(tp); 2494 2495 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2496 ocp_data &= ~NOW_IS_OOB; 2497 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2498 2499 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2500 ocp_data &= ~MCU_BORW_EN; 2501 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2502 2503 for (i = 0; i < 1000; i++) { 2504 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2505 if (ocp_data & LINK_LIST_READY) 2506 break; 2507 mdelay(1); 2508 } 2509 2510 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2511 ocp_data |= RE_INIT_LL; 2512 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2513 2514 for (i = 0; i < 1000; i++) { 2515 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2516 if (ocp_data & LINK_LIST_READY) 2517 break; 2518 mdelay(1); 2519 } 2520 2521 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2522 ocp_data &= ~CPCR_RX_VLAN; 2523 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2524 2525 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2526 2527 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2528 ocp_data |= TCR0_AUTO_FIFO; 2529 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2530 2531 rtl8152_nic_reset(tp); 2532 2533 /* rx share fifo credit full threshold */ 2534 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2535 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 2536 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 2537 /* TX share fifo free credit full threshold */ 2538 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 2539 2540 /* rx aggregation */ 2541 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 2542 ocp_data &= ~RX_AGG_DISABLE; 2543 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 2544 } 2545 2546 static void r8153_enter_oob(struct r8152 *tp) 2547 { 2548 u32 ocp_data; 2549 int i; 2550 2551 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2552 ocp_data &= ~NOW_IS_OOB; 2553 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2554 2555 rtl8152_disable(tp); 2556 2557 for (i = 0; i < 1000; i++) { 2558 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2559 if (ocp_data & LINK_LIST_READY) 2560 break; 2561 mdelay(1); 2562 } 2563 2564 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2565 ocp_data |= RE_INIT_LL; 2566 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2567 2568 for (i = 0; i < 1000; i++) { 2569 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2570 if (ocp_data & LINK_LIST_READY) 2571 break; 2572 mdelay(1); 2573 } 2574 2575 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2576 2577 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2578 ocp_data &= ~TEREDO_WAKE_MASK; 2579 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2580 2581 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2582 ocp_data |= CPCR_RX_VLAN; 2583 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2584 2585 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2586 ocp_data |= ALDPS_PROXY_MODE; 2587 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2588 2589 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2590 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2591 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2592 2593 rxdy_gated_en(tp, false); 2594 2595 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2596 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2597 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2598 } 2599 2600 static void r8153_disable_aldps(struct r8152 *tp) 2601 { 2602 u16 data; 2603 2604 data = ocp_reg_read(tp, OCP_POWER_CFG); 2605 data &= ~EN_ALDPS; 2606 ocp_reg_write(tp, OCP_POWER_CFG, data); 2607 msleep(20); 2608 } 2609 2610 static void r8153_enable_aldps(struct r8152 *tp) 2611 { 2612 u16 data; 2613 2614 data = ocp_reg_read(tp, OCP_POWER_CFG); 2615 data |= EN_ALDPS; 2616 ocp_reg_write(tp, OCP_POWER_CFG, data); 2617 } 2618 2619 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 2620 { 2621 u16 bmcr, anar, gbcr; 2622 int ret = 0; 2623 2624 cancel_delayed_work_sync(&tp->schedule); 2625 anar = r8152_mdio_read(tp, MII_ADVERTISE); 2626 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 2627 ADVERTISE_100HALF | ADVERTISE_100FULL); 2628 if (tp->mii.supports_gmii) { 2629 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 2630 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 2631 } else { 2632 gbcr = 0; 2633 } 2634 2635 if (autoneg == AUTONEG_DISABLE) { 2636 if (speed == SPEED_10) { 2637 bmcr = 0; 2638 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2639 } else if (speed == SPEED_100) { 2640 bmcr = BMCR_SPEED100; 2641 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2642 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 2643 bmcr = BMCR_SPEED1000; 2644 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 2645 } else { 2646 ret = -EINVAL; 2647 goto out; 2648 } 2649 2650 if (duplex == DUPLEX_FULL) 2651 bmcr |= BMCR_FULLDPLX; 2652 } else { 2653 if (speed == SPEED_10) { 2654 if (duplex == DUPLEX_FULL) 2655 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2656 else 2657 anar |= ADVERTISE_10HALF; 2658 } else if (speed == SPEED_100) { 2659 if (duplex == DUPLEX_FULL) { 2660 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2661 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2662 } else { 2663 anar |= ADVERTISE_10HALF; 2664 anar |= ADVERTISE_100HALF; 2665 } 2666 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 2667 if (duplex == DUPLEX_FULL) { 2668 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2669 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2670 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 2671 } else { 2672 anar |= ADVERTISE_10HALF; 2673 anar |= ADVERTISE_100HALF; 2674 gbcr |= ADVERTISE_1000HALF; 2675 } 2676 } else { 2677 ret = -EINVAL; 2678 goto out; 2679 } 2680 2681 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 2682 } 2683 2684 if (test_bit(PHY_RESET, &tp->flags)) 2685 bmcr |= BMCR_RESET; 2686 2687 if (tp->mii.supports_gmii) 2688 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 2689 2690 r8152_mdio_write(tp, MII_ADVERTISE, anar); 2691 r8152_mdio_write(tp, MII_BMCR, bmcr); 2692 2693 if (test_bit(PHY_RESET, &tp->flags)) { 2694 int i; 2695 2696 clear_bit(PHY_RESET, &tp->flags); 2697 for (i = 0; i < 50; i++) { 2698 msleep(20); 2699 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 2700 break; 2701 } 2702 } 2703 2704 out: 2705 2706 return ret; 2707 } 2708 2709 static void rtl8152_down(struct r8152 *tp) 2710 { 2711 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2712 rtl_drop_queued_tx(tp); 2713 return; 2714 } 2715 2716 r8152_power_cut_en(tp, false); 2717 r8152b_disable_aldps(tp); 2718 r8152b_enter_oob(tp); 2719 r8152b_enable_aldps(tp); 2720 } 2721 2722 static void rtl8153_down(struct r8152 *tp) 2723 { 2724 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2725 rtl_drop_queued_tx(tp); 2726 return; 2727 } 2728 2729 r8153_u1u2en(tp, false); 2730 r8153_power_cut_en(tp, false); 2731 r8153_disable_aldps(tp); 2732 r8153_enter_oob(tp); 2733 r8153_enable_aldps(tp); 2734 } 2735 2736 static void set_carrier(struct r8152 *tp) 2737 { 2738 struct net_device *netdev = tp->netdev; 2739 u8 speed; 2740 2741 clear_bit(RTL8152_LINK_CHG, &tp->flags); 2742 speed = rtl8152_get_speed(tp); 2743 2744 if (speed & LINK_STATUS) { 2745 if (!(tp->speed & LINK_STATUS)) { 2746 tp->rtl_ops.enable(tp); 2747 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2748 netif_carrier_on(netdev); 2749 } 2750 } else { 2751 if (tp->speed & LINK_STATUS) { 2752 netif_carrier_off(netdev); 2753 tasklet_disable(&tp->tl); 2754 tp->rtl_ops.disable(tp); 2755 tasklet_enable(&tp->tl); 2756 } 2757 } 2758 tp->speed = speed; 2759 } 2760 2761 static void rtl_work_func_t(struct work_struct *work) 2762 { 2763 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 2764 2765 if (usb_autopm_get_interface(tp->intf) < 0) 2766 return; 2767 2768 if (!test_bit(WORK_ENABLE, &tp->flags)) 2769 goto out1; 2770 2771 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2772 goto out1; 2773 2774 if (test_bit(RTL8152_LINK_CHG, &tp->flags)) 2775 set_carrier(tp); 2776 2777 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) 2778 _rtl8152_set_rx_mode(tp->netdev); 2779 2780 if (test_bit(SCHEDULE_TASKLET, &tp->flags) && 2781 (tp->speed & LINK_STATUS)) { 2782 clear_bit(SCHEDULE_TASKLET, &tp->flags); 2783 tasklet_schedule(&tp->tl); 2784 } 2785 2786 if (test_bit(PHY_RESET, &tp->flags)) 2787 rtl_phy_reset(tp); 2788 2789 out1: 2790 usb_autopm_put_interface(tp->intf); 2791 } 2792 2793 static int rtl8152_open(struct net_device *netdev) 2794 { 2795 struct r8152 *tp = netdev_priv(netdev); 2796 int res = 0; 2797 2798 res = alloc_all_mem(tp); 2799 if (res) 2800 goto out; 2801 2802 res = usb_autopm_get_interface(tp->intf); 2803 if (res < 0) { 2804 free_all_mem(tp); 2805 goto out; 2806 } 2807 2808 /* The WORK_ENABLE may be set when autoresume occurs */ 2809 if (test_bit(WORK_ENABLE, &tp->flags)) { 2810 clear_bit(WORK_ENABLE, &tp->flags); 2811 usb_kill_urb(tp->intr_urb); 2812 cancel_delayed_work_sync(&tp->schedule); 2813 if (tp->speed & LINK_STATUS) 2814 tp->rtl_ops.disable(tp); 2815 } 2816 2817 tp->rtl_ops.up(tp); 2818 2819 rtl8152_set_speed(tp, AUTONEG_ENABLE, 2820 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, 2821 DUPLEX_FULL); 2822 tp->speed = 0; 2823 netif_carrier_off(netdev); 2824 netif_start_queue(netdev); 2825 set_bit(WORK_ENABLE, &tp->flags); 2826 2827 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 2828 if (res) { 2829 if (res == -ENODEV) 2830 netif_device_detach(tp->netdev); 2831 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 2832 res); 2833 free_all_mem(tp); 2834 } 2835 2836 usb_autopm_put_interface(tp->intf); 2837 2838 out: 2839 return res; 2840 } 2841 2842 static int rtl8152_close(struct net_device *netdev) 2843 { 2844 struct r8152 *tp = netdev_priv(netdev); 2845 int res = 0; 2846 2847 clear_bit(WORK_ENABLE, &tp->flags); 2848 usb_kill_urb(tp->intr_urb); 2849 cancel_delayed_work_sync(&tp->schedule); 2850 netif_stop_queue(netdev); 2851 2852 res = usb_autopm_get_interface(tp->intf); 2853 if (res < 0) { 2854 rtl_drop_queued_tx(tp); 2855 } else { 2856 /* 2857 * The autosuspend may have been enabled and wouldn't 2858 * be disable when autoresume occurs, because the 2859 * netif_running() would be false. 2860 */ 2861 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2862 rtl_runtime_suspend_enable(tp, false); 2863 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 2864 } 2865 2866 tasklet_disable(&tp->tl); 2867 tp->rtl_ops.down(tp); 2868 tasklet_enable(&tp->tl); 2869 usb_autopm_put_interface(tp->intf); 2870 } 2871 2872 free_all_mem(tp); 2873 2874 return res; 2875 } 2876 2877 static void r8152b_enable_eee(struct r8152 *tp) 2878 { 2879 u32 ocp_data; 2880 2881 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 2882 ocp_data |= EEE_RX_EN | EEE_TX_EN; 2883 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 2884 ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN | 2885 EEE_10_CAP | EEE_NWAY_EN | 2886 TX_QUIET_EN | RX_QUIET_EN | 2887 SDRISETIME | RG_RXLPI_MSK_HFDUP | 2888 SDFALLTIME); 2889 ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN | 2890 RG_LDVQUIET_EN | RG_CKRSEL | 2891 RG_EEEPRG_EN); 2892 ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH); 2893 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR); 2894 ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR); 2895 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR); 2896 ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA); 2897 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 2898 } 2899 2900 static void r8153_enable_eee(struct r8152 *tp) 2901 { 2902 u32 ocp_data; 2903 u16 data; 2904 2905 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 2906 ocp_data |= EEE_RX_EN | EEE_TX_EN; 2907 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 2908 data = ocp_reg_read(tp, OCP_EEE_CFG); 2909 data |= EEE10_EN; 2910 ocp_reg_write(tp, OCP_EEE_CFG, data); 2911 data = ocp_reg_read(tp, OCP_EEE_CFG2); 2912 data |= MY1000_EEE | MY100_EEE; 2913 ocp_reg_write(tp, OCP_EEE_CFG2, data); 2914 } 2915 2916 static void r8152b_enable_fc(struct r8152 *tp) 2917 { 2918 u16 anar; 2919 2920 anar = r8152_mdio_read(tp, MII_ADVERTISE); 2921 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 2922 r8152_mdio_write(tp, MII_ADVERTISE, anar); 2923 } 2924 2925 static void rtl_tally_reset(struct r8152 *tp) 2926 { 2927 u32 ocp_data; 2928 2929 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 2930 ocp_data |= TALLY_RESET; 2931 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 2932 } 2933 2934 static void r8152b_init(struct r8152 *tp) 2935 { 2936 u32 ocp_data; 2937 2938 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2939 return; 2940 2941 if (tp->version == RTL_VER_01) { 2942 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 2943 ocp_data &= ~LED_MODE_MASK; 2944 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 2945 } 2946 2947 r8152_power_cut_en(tp, false); 2948 2949 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 2950 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 2951 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 2952 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 2953 ocp_data &= ~MCU_CLK_RATIO_MASK; 2954 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 2955 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 2956 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 2957 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 2958 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 2959 2960 r8152b_enable_eee(tp); 2961 r8152b_enable_aldps(tp); 2962 r8152b_enable_fc(tp); 2963 rtl_tally_reset(tp); 2964 2965 /* enable rx aggregation */ 2966 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 2967 ocp_data &= ~RX_AGG_DISABLE; 2968 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 2969 } 2970 2971 static void r8153_init(struct r8152 *tp) 2972 { 2973 u32 ocp_data; 2974 int i; 2975 2976 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2977 return; 2978 2979 r8153_u1u2en(tp, false); 2980 2981 for (i = 0; i < 500; i++) { 2982 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 2983 AUTOLOAD_DONE) 2984 break; 2985 msleep(20); 2986 } 2987 2988 for (i = 0; i < 500; i++) { 2989 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; 2990 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) 2991 break; 2992 msleep(20); 2993 } 2994 2995 r8153_u2p3en(tp, false); 2996 2997 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 2998 ocp_data &= ~TIMER11_EN; 2999 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 3000 3001 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 3002 ocp_data &= ~LED_MODE_MASK; 3003 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 3004 3005 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL); 3006 ocp_data &= ~LPM_TIMER_MASK; 3007 if (tp->udev->speed == USB_SPEED_SUPER) 3008 ocp_data |= LPM_TIMER_500US; 3009 else 3010 ocp_data |= LPM_TIMER_500MS; 3011 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 3012 3013 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 3014 ocp_data &= ~SEN_VAL_MASK; 3015 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 3016 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 3017 3018 r8153_power_cut_en(tp, false); 3019 r8153_u1u2en(tp, true); 3020 3021 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); 3022 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); 3023 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 3024 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | 3025 U1U2_SPDWN_EN | L1_SPDWN_EN); 3026 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 3027 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | 3028 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | 3029 EEE_SPDWN_EN); 3030 3031 r8153_enable_eee(tp); 3032 r8153_enable_aldps(tp); 3033 r8152b_enable_fc(tp); 3034 rtl_tally_reset(tp); 3035 } 3036 3037 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 3038 { 3039 struct r8152 *tp = usb_get_intfdata(intf); 3040 3041 if (PMSG_IS_AUTO(message)) 3042 set_bit(SELECTIVE_SUSPEND, &tp->flags); 3043 else 3044 netif_device_detach(tp->netdev); 3045 3046 if (netif_running(tp->netdev)) { 3047 clear_bit(WORK_ENABLE, &tp->flags); 3048 usb_kill_urb(tp->intr_urb); 3049 cancel_delayed_work_sync(&tp->schedule); 3050 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3051 rtl_runtime_suspend_enable(tp, true); 3052 } else { 3053 tasklet_disable(&tp->tl); 3054 tp->rtl_ops.down(tp); 3055 tasklet_enable(&tp->tl); 3056 } 3057 } 3058 3059 return 0; 3060 } 3061 3062 static int rtl8152_resume(struct usb_interface *intf) 3063 { 3064 struct r8152 *tp = usb_get_intfdata(intf); 3065 3066 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3067 tp->rtl_ops.init(tp); 3068 netif_device_attach(tp->netdev); 3069 } 3070 3071 if (netif_running(tp->netdev)) { 3072 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3073 rtl_runtime_suspend_enable(tp, false); 3074 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3075 if (tp->speed & LINK_STATUS) 3076 tp->rtl_ops.disable(tp); 3077 } else { 3078 tp->rtl_ops.up(tp); 3079 rtl8152_set_speed(tp, AUTONEG_ENABLE, 3080 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, 3081 DUPLEX_FULL); 3082 } 3083 tp->speed = 0; 3084 netif_carrier_off(tp->netdev); 3085 set_bit(WORK_ENABLE, &tp->flags); 3086 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3087 } 3088 3089 return 0; 3090 } 3091 3092 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3093 { 3094 struct r8152 *tp = netdev_priv(dev); 3095 3096 if (usb_autopm_get_interface(tp->intf) < 0) 3097 return; 3098 3099 wol->supported = WAKE_ANY; 3100 wol->wolopts = __rtl_get_wol(tp); 3101 3102 usb_autopm_put_interface(tp->intf); 3103 } 3104 3105 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3106 { 3107 struct r8152 *tp = netdev_priv(dev); 3108 int ret; 3109 3110 ret = usb_autopm_get_interface(tp->intf); 3111 if (ret < 0) 3112 goto out_set_wol; 3113 3114 __rtl_set_wol(tp, wol->wolopts); 3115 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 3116 3117 usb_autopm_put_interface(tp->intf); 3118 3119 out_set_wol: 3120 return ret; 3121 } 3122 3123 static u32 rtl8152_get_msglevel(struct net_device *dev) 3124 { 3125 struct r8152 *tp = netdev_priv(dev); 3126 3127 return tp->msg_enable; 3128 } 3129 3130 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 3131 { 3132 struct r8152 *tp = netdev_priv(dev); 3133 3134 tp->msg_enable = value; 3135 } 3136 3137 static void rtl8152_get_drvinfo(struct net_device *netdev, 3138 struct ethtool_drvinfo *info) 3139 { 3140 struct r8152 *tp = netdev_priv(netdev); 3141 3142 strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN); 3143 strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN); 3144 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 3145 } 3146 3147 static 3148 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) 3149 { 3150 struct r8152 *tp = netdev_priv(netdev); 3151 3152 if (!tp->mii.mdio_read) 3153 return -EOPNOTSUPP; 3154 3155 return mii_ethtool_gset(&tp->mii, cmd); 3156 } 3157 3158 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 3159 { 3160 struct r8152 *tp = netdev_priv(dev); 3161 int ret; 3162 3163 ret = usb_autopm_get_interface(tp->intf); 3164 if (ret < 0) 3165 goto out; 3166 3167 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); 3168 3169 usb_autopm_put_interface(tp->intf); 3170 3171 out: 3172 return ret; 3173 } 3174 3175 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 3176 "tx_packets", 3177 "rx_packets", 3178 "tx_errors", 3179 "rx_errors", 3180 "rx_missed", 3181 "align_errors", 3182 "tx_single_collisions", 3183 "tx_multi_collisions", 3184 "rx_unicast", 3185 "rx_broadcast", 3186 "rx_multicast", 3187 "tx_aborted", 3188 "tx_underrun", 3189 }; 3190 3191 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 3192 { 3193 switch (sset) { 3194 case ETH_SS_STATS: 3195 return ARRAY_SIZE(rtl8152_gstrings); 3196 default: 3197 return -EOPNOTSUPP; 3198 } 3199 } 3200 3201 static void rtl8152_get_ethtool_stats(struct net_device *dev, 3202 struct ethtool_stats *stats, u64 *data) 3203 { 3204 struct r8152 *tp = netdev_priv(dev); 3205 struct tally_counter tally; 3206 3207 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 3208 3209 data[0] = le64_to_cpu(tally.tx_packets); 3210 data[1] = le64_to_cpu(tally.rx_packets); 3211 data[2] = le64_to_cpu(tally.tx_errors); 3212 data[3] = le32_to_cpu(tally.rx_errors); 3213 data[4] = le16_to_cpu(tally.rx_missed); 3214 data[5] = le16_to_cpu(tally.align_errors); 3215 data[6] = le32_to_cpu(tally.tx_one_collision); 3216 data[7] = le32_to_cpu(tally.tx_multi_collision); 3217 data[8] = le64_to_cpu(tally.rx_unicast); 3218 data[9] = le64_to_cpu(tally.rx_broadcast); 3219 data[10] = le32_to_cpu(tally.rx_multicast); 3220 data[11] = le16_to_cpu(tally.tx_aborted); 3221 data[12] = le16_to_cpu(tally.tx_underun); 3222 } 3223 3224 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 3225 { 3226 switch (stringset) { 3227 case ETH_SS_STATS: 3228 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 3229 break; 3230 } 3231 } 3232 3233 static struct ethtool_ops ops = { 3234 .get_drvinfo = rtl8152_get_drvinfo, 3235 .get_settings = rtl8152_get_settings, 3236 .set_settings = rtl8152_set_settings, 3237 .get_link = ethtool_op_get_link, 3238 .get_msglevel = rtl8152_get_msglevel, 3239 .set_msglevel = rtl8152_set_msglevel, 3240 .get_wol = rtl8152_get_wol, 3241 .set_wol = rtl8152_set_wol, 3242 .get_strings = rtl8152_get_strings, 3243 .get_sset_count = rtl8152_get_sset_count, 3244 .get_ethtool_stats = rtl8152_get_ethtool_stats, 3245 }; 3246 3247 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 3248 { 3249 struct r8152 *tp = netdev_priv(netdev); 3250 struct mii_ioctl_data *data = if_mii(rq); 3251 int res; 3252 3253 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3254 return -ENODEV; 3255 3256 res = usb_autopm_get_interface(tp->intf); 3257 if (res < 0) 3258 goto out; 3259 3260 switch (cmd) { 3261 case SIOCGMIIPHY: 3262 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 3263 break; 3264 3265 case SIOCGMIIREG: 3266 data->val_out = r8152_mdio_read(tp, data->reg_num); 3267 break; 3268 3269 case SIOCSMIIREG: 3270 if (!capable(CAP_NET_ADMIN)) { 3271 res = -EPERM; 3272 break; 3273 } 3274 r8152_mdio_write(tp, data->reg_num, data->val_in); 3275 break; 3276 3277 default: 3278 res = -EOPNOTSUPP; 3279 } 3280 3281 usb_autopm_put_interface(tp->intf); 3282 3283 out: 3284 return res; 3285 } 3286 3287 static const struct net_device_ops rtl8152_netdev_ops = { 3288 .ndo_open = rtl8152_open, 3289 .ndo_stop = rtl8152_close, 3290 .ndo_do_ioctl = rtl8152_ioctl, 3291 .ndo_start_xmit = rtl8152_start_xmit, 3292 .ndo_tx_timeout = rtl8152_tx_timeout, 3293 .ndo_set_rx_mode = rtl8152_set_rx_mode, 3294 .ndo_set_mac_address = rtl8152_set_mac_address, 3295 3296 .ndo_change_mtu = eth_change_mtu, 3297 .ndo_validate_addr = eth_validate_addr, 3298 }; 3299 3300 static void r8152b_get_version(struct r8152 *tp) 3301 { 3302 u32 ocp_data; 3303 u16 version; 3304 3305 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); 3306 version = (u16)(ocp_data & VERSION_MASK); 3307 3308 switch (version) { 3309 case 0x4c00: 3310 tp->version = RTL_VER_01; 3311 break; 3312 case 0x4c10: 3313 tp->version = RTL_VER_02; 3314 break; 3315 case 0x5c00: 3316 tp->version = RTL_VER_03; 3317 tp->mii.supports_gmii = 1; 3318 break; 3319 case 0x5c10: 3320 tp->version = RTL_VER_04; 3321 tp->mii.supports_gmii = 1; 3322 break; 3323 case 0x5c20: 3324 tp->version = RTL_VER_05; 3325 tp->mii.supports_gmii = 1; 3326 break; 3327 default: 3328 netif_info(tp, probe, tp->netdev, 3329 "Unknown version 0x%04x\n", version); 3330 break; 3331 } 3332 } 3333 3334 static void rtl8152_unload(struct r8152 *tp) 3335 { 3336 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3337 return; 3338 3339 if (tp->version != RTL_VER_01) 3340 r8152_power_cut_en(tp, true); 3341 } 3342 3343 static void rtl8153_unload(struct r8152 *tp) 3344 { 3345 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3346 return; 3347 3348 r8153_power_cut_en(tp, true); 3349 } 3350 3351 static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id) 3352 { 3353 struct rtl_ops *ops = &tp->rtl_ops; 3354 int ret = -ENODEV; 3355 3356 switch (id->idVendor) { 3357 case VENDOR_ID_REALTEK: 3358 switch (id->idProduct) { 3359 case PRODUCT_ID_RTL8152: 3360 ops->init = r8152b_init; 3361 ops->enable = rtl8152_enable; 3362 ops->disable = rtl8152_disable; 3363 ops->up = r8152b_exit_oob; 3364 ops->down = rtl8152_down; 3365 ops->unload = rtl8152_unload; 3366 ret = 0; 3367 break; 3368 case PRODUCT_ID_RTL8153: 3369 ops->init = r8153_init; 3370 ops->enable = rtl8153_enable; 3371 ops->disable = rtl8152_disable; 3372 ops->up = r8153_first_init; 3373 ops->down = rtl8153_down; 3374 ops->unload = rtl8153_unload; 3375 ret = 0; 3376 break; 3377 default: 3378 break; 3379 } 3380 break; 3381 3382 case VENDOR_ID_SAMSUNG: 3383 switch (id->idProduct) { 3384 case PRODUCT_ID_SAMSUNG: 3385 ops->init = r8153_init; 3386 ops->enable = rtl8153_enable; 3387 ops->disable = rtl8152_disable; 3388 ops->up = r8153_first_init; 3389 ops->down = rtl8153_down; 3390 ops->unload = rtl8153_unload; 3391 ret = 0; 3392 break; 3393 default: 3394 break; 3395 } 3396 break; 3397 3398 default: 3399 break; 3400 } 3401 3402 if (ret) 3403 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 3404 3405 return ret; 3406 } 3407 3408 static int rtl8152_probe(struct usb_interface *intf, 3409 const struct usb_device_id *id) 3410 { 3411 struct usb_device *udev = interface_to_usbdev(intf); 3412 struct r8152 *tp; 3413 struct net_device *netdev; 3414 int ret; 3415 3416 if (udev->actconfig->desc.bConfigurationValue != 1) { 3417 usb_driver_set_configuration(udev, 1); 3418 return -ENODEV; 3419 } 3420 3421 usb_reset_device(udev); 3422 netdev = alloc_etherdev(sizeof(struct r8152)); 3423 if (!netdev) { 3424 dev_err(&intf->dev, "Out of memory\n"); 3425 return -ENOMEM; 3426 } 3427 3428 SET_NETDEV_DEV(netdev, &intf->dev); 3429 tp = netdev_priv(netdev); 3430 tp->msg_enable = 0x7FFF; 3431 3432 tp->udev = udev; 3433 tp->netdev = netdev; 3434 tp->intf = intf; 3435 3436 ret = rtl_ops_init(tp, id); 3437 if (ret) 3438 goto out; 3439 3440 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp); 3441 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 3442 3443 netdev->netdev_ops = &rtl8152_netdev_ops; 3444 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 3445 3446 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 3447 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 3448 NETIF_F_TSO6; 3449 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 3450 NETIF_F_TSO | NETIF_F_FRAGLIST | 3451 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 3452 3453 netdev->ethtool_ops = &ops; 3454 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 3455 3456 tp->mii.dev = netdev; 3457 tp->mii.mdio_read = read_mii_word; 3458 tp->mii.mdio_write = write_mii_word; 3459 tp->mii.phy_id_mask = 0x3f; 3460 tp->mii.reg_num_mask = 0x1f; 3461 tp->mii.phy_id = R8152_PHY_ID; 3462 tp->mii.supports_gmii = 0; 3463 3464 intf->needs_remote_wakeup = 1; 3465 3466 r8152b_get_version(tp); 3467 tp->rtl_ops.init(tp); 3468 set_ethernet_addr(tp); 3469 3470 usb_set_intfdata(intf, tp); 3471 3472 ret = register_netdev(netdev); 3473 if (ret != 0) { 3474 netif_err(tp, probe, netdev, "couldn't register the device\n"); 3475 goto out1; 3476 } 3477 3478 tp->saved_wolopts = __rtl_get_wol(tp); 3479 if (tp->saved_wolopts) 3480 device_set_wakeup_enable(&udev->dev, true); 3481 else 3482 device_set_wakeup_enable(&udev->dev, false); 3483 3484 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 3485 3486 return 0; 3487 3488 out1: 3489 usb_set_intfdata(intf, NULL); 3490 out: 3491 free_netdev(netdev); 3492 return ret; 3493 } 3494 3495 static void rtl8152_disconnect(struct usb_interface *intf) 3496 { 3497 struct r8152 *tp = usb_get_intfdata(intf); 3498 3499 usb_set_intfdata(intf, NULL); 3500 if (tp) { 3501 set_bit(RTL8152_UNPLUG, &tp->flags); 3502 tasklet_kill(&tp->tl); 3503 unregister_netdev(tp->netdev); 3504 tp->rtl_ops.unload(tp); 3505 free_netdev(tp->netdev); 3506 } 3507 } 3508 3509 /* table of devices that work with this driver */ 3510 static struct usb_device_id rtl8152_table[] = { 3511 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)}, 3512 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)}, 3513 {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)}, 3514 {} 3515 }; 3516 3517 MODULE_DEVICE_TABLE(usb, rtl8152_table); 3518 3519 static struct usb_driver rtl8152_driver = { 3520 .name = MODULENAME, 3521 .id_table = rtl8152_table, 3522 .probe = rtl8152_probe, 3523 .disconnect = rtl8152_disconnect, 3524 .suspend = rtl8152_suspend, 3525 .resume = rtl8152_resume, 3526 .reset_resume = rtl8152_resume, 3527 .supports_autosuspend = 1, 3528 .disable_hub_initiated_lpm = 1, 3529 }; 3530 3531 module_usb_driver(rtl8152_driver); 3532 3533 MODULE_AUTHOR(DRIVER_AUTHOR); 3534 MODULE_DESCRIPTION(DRIVER_DESC); 3535 MODULE_LICENSE("GPL"); 3536