1 /* 2 * Copyright (c) 2013 Realtek Semiconductor Corp. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2 as published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/init.h> 11 #include <linux/signal.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/mii.h> 17 #include <linux/ethtool.h> 18 #include <linux/usb.h> 19 #include <linux/crc32.h> 20 #include <linux/if_vlan.h> 21 #include <linux/uaccess.h> 22 #include <linux/list.h> 23 #include <linux/ip.h> 24 #include <linux/ipv6.h> 25 26 /* Version Information */ 27 #define DRIVER_VERSION "v1.01.0 (2013/08/12)" 28 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 29 #define DRIVER_DESC "Realtek RTL8152 Based USB 2.0 Ethernet Adapters" 30 #define MODULENAME "r8152" 31 32 #define R8152_PHY_ID 32 33 34 #define PLA_IDR 0xc000 35 #define PLA_RCR 0xc010 36 #define PLA_RMS 0xc016 37 #define PLA_RXFIFO_CTRL0 0xc0a0 38 #define PLA_RXFIFO_CTRL1 0xc0a4 39 #define PLA_RXFIFO_CTRL2 0xc0a8 40 #define PLA_FMC 0xc0b4 41 #define PLA_CFG_WOL 0xc0b6 42 #define PLA_MAR 0xcd00 43 #define PAL_BDC_CR 0xd1a0 44 #define PLA_LEDSEL 0xdd90 45 #define PLA_LED_FEATURE 0xdd92 46 #define PLA_PHYAR 0xde00 47 #define PLA_GPHY_INTR_IMR 0xe022 48 #define PLA_EEE_CR 0xe040 49 #define PLA_EEEP_CR 0xe080 50 #define PLA_MAC_PWR_CTRL 0xe0c0 51 #define PLA_TCR0 0xe610 52 #define PLA_TCR1 0xe612 53 #define PLA_TXFIFO_CTRL 0xe618 54 #define PLA_RSTTELLY 0xe800 55 #define PLA_CR 0xe813 56 #define PLA_CRWECR 0xe81c 57 #define PLA_CONFIG5 0xe822 58 #define PLA_PHY_PWR 0xe84c 59 #define PLA_OOB_CTRL 0xe84f 60 #define PLA_CPCR 0xe854 61 #define PLA_MISC_0 0xe858 62 #define PLA_MISC_1 0xe85a 63 #define PLA_OCP_GPHY_BASE 0xe86c 64 #define PLA_TELLYCNT 0xe890 65 #define PLA_SFF_STS_7 0xe8de 66 #define PLA_PHYSTATUS 0xe908 67 #define PLA_BP_BA 0xfc26 68 #define PLA_BP_0 0xfc28 69 #define PLA_BP_1 0xfc2a 70 #define PLA_BP_2 0xfc2c 71 #define PLA_BP_3 0xfc2e 72 #define PLA_BP_4 0xfc30 73 #define PLA_BP_5 0xfc32 74 #define PLA_BP_6 0xfc34 75 #define PLA_BP_7 0xfc36 76 77 #define USB_DEV_STAT 0xb808 78 #define USB_USB_CTRL 0xd406 79 #define USB_PHY_CTRL 0xd408 80 #define USB_TX_AGG 0xd40a 81 #define USB_RX_BUF_TH 0xd40c 82 #define USB_USB_TIMER 0xd428 83 #define USB_PM_CTRL_STATUS 0xd432 84 #define USB_TX_DMA 0xd434 85 #define USB_UPS_CTRL 0xd800 86 #define USB_BP_BA 0xfc26 87 #define USB_BP_0 0xfc28 88 #define USB_BP_1 0xfc2a 89 #define USB_BP_2 0xfc2c 90 #define USB_BP_3 0xfc2e 91 #define USB_BP_4 0xfc30 92 #define USB_BP_5 0xfc32 93 #define USB_BP_6 0xfc34 94 #define USB_BP_7 0xfc36 95 96 /* OCP Registers */ 97 #define OCP_ALDPS_CONFIG 0x2010 98 #define OCP_EEE_CONFIG1 0x2080 99 #define OCP_EEE_CONFIG2 0x2092 100 #define OCP_EEE_CONFIG3 0x2094 101 #define OCP_EEE_AR 0xa41a 102 #define OCP_EEE_DATA 0xa41c 103 104 /* PLA_RCR */ 105 #define RCR_AAP 0x00000001 106 #define RCR_APM 0x00000002 107 #define RCR_AM 0x00000004 108 #define RCR_AB 0x00000008 109 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 110 111 /* PLA_RXFIFO_CTRL0 */ 112 #define RXFIFO_THR1_NORMAL 0x00080002 113 #define RXFIFO_THR1_OOB 0x01800003 114 115 /* PLA_RXFIFO_CTRL1 */ 116 #define RXFIFO_THR2_FULL 0x00000060 117 #define RXFIFO_THR2_HIGH 0x00000038 118 #define RXFIFO_THR2_OOB 0x0000004a 119 120 /* PLA_RXFIFO_CTRL2 */ 121 #define RXFIFO_THR3_FULL 0x00000078 122 #define RXFIFO_THR3_HIGH 0x00000048 123 #define RXFIFO_THR3_OOB 0x0000005a 124 125 /* PLA_TXFIFO_CTRL */ 126 #define TXFIFO_THR_NORMAL 0x00400008 127 128 /* PLA_FMC */ 129 #define FMC_FCR_MCU_EN 0x0001 130 131 /* PLA_EEEP_CR */ 132 #define EEEP_CR_EEEP_TX 0x0002 133 134 /* PLA_TCR0 */ 135 #define TCR0_TX_EMPTY 0x0800 136 #define TCR0_AUTO_FIFO 0x0080 137 138 /* PLA_TCR1 */ 139 #define VERSION_MASK 0x7cf0 140 141 /* PLA_CR */ 142 #define CR_RST 0x10 143 #define CR_RE 0x08 144 #define CR_TE 0x04 145 146 /* PLA_CRWECR */ 147 #define CRWECR_NORAML 0x00 148 #define CRWECR_CONFIG 0xc0 149 150 /* PLA_OOB_CTRL */ 151 #define NOW_IS_OOB 0x80 152 #define TXFIFO_EMPTY 0x20 153 #define RXFIFO_EMPTY 0x10 154 #define LINK_LIST_READY 0x02 155 #define DIS_MCU_CLROOB 0x01 156 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 157 158 /* PLA_MISC_1 */ 159 #define RXDY_GATED_EN 0x0008 160 161 /* PLA_SFF_STS_7 */ 162 #define RE_INIT_LL 0x8000 163 #define MCU_BORW_EN 0x4000 164 165 /* PLA_CPCR */ 166 #define CPCR_RX_VLAN 0x0040 167 168 /* PLA_CFG_WOL */ 169 #define MAGIC_EN 0x0001 170 171 /* PAL_BDC_CR */ 172 #define ALDPS_PROXY_MODE 0x0001 173 174 /* PLA_CONFIG5 */ 175 #define LAN_WAKE_EN 0x0002 176 177 /* PLA_LED_FEATURE */ 178 #define LED_MODE_MASK 0x0700 179 180 /* PLA_PHY_PWR */ 181 #define TX_10M_IDLE_EN 0x0080 182 #define PFM_PWM_SWITCH 0x0040 183 184 /* PLA_MAC_PWR_CTRL */ 185 #define D3_CLK_GATED_EN 0x00004000 186 #define MCU_CLK_RATIO 0x07010f07 187 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 188 189 /* PLA_GPHY_INTR_IMR */ 190 #define GPHY_STS_MSK 0x0001 191 #define SPEED_DOWN_MSK 0x0002 192 #define SPDWN_RXDV_MSK 0x0004 193 #define SPDWN_LINKCHG_MSK 0x0008 194 195 /* PLA_PHYAR */ 196 #define PHYAR_FLAG 0x80000000 197 198 /* PLA_EEE_CR */ 199 #define EEE_RX_EN 0x0001 200 #define EEE_TX_EN 0x0002 201 202 /* USB_DEV_STAT */ 203 #define STAT_SPEED_MASK 0x0006 204 #define STAT_SPEED_HIGH 0x0000 205 #define STAT_SPEED_FULL 0x0001 206 207 /* USB_TX_AGG */ 208 #define TX_AGG_MAX_THRESHOLD 0x03 209 210 /* USB_RX_BUF_TH */ 211 #define RX_BUF_THR 0x7a120180 212 213 /* USB_TX_DMA */ 214 #define TEST_MODE_DISABLE 0x00000001 215 #define TX_SIZE_ADJUST1 0x00000100 216 217 /* USB_UPS_CTRL */ 218 #define POWER_CUT 0x0100 219 220 /* USB_PM_CTRL_STATUS */ 221 #define RWSUME_INDICATE 0x0001 222 223 /* USB_USB_CTRL */ 224 #define RX_AGG_DISABLE 0x0010 225 226 /* OCP_ALDPS_CONFIG */ 227 #define ENPWRSAVE 0x8000 228 #define ENPDNPS 0x0200 229 #define LINKENA 0x0100 230 #define DIS_SDSAVE 0x0010 231 232 /* OCP_EEE_CONFIG1 */ 233 #define RG_TXLPI_MSK_HFDUP 0x8000 234 #define RG_MATCLR_EN 0x4000 235 #define EEE_10_CAP 0x2000 236 #define EEE_NWAY_EN 0x1000 237 #define TX_QUIET_EN 0x0200 238 #define RX_QUIET_EN 0x0100 239 #define SDRISETIME 0x0010 /* bit 4 ~ 6 */ 240 #define RG_RXLPI_MSK_HFDUP 0x0008 241 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 242 243 /* OCP_EEE_CONFIG2 */ 244 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 245 #define RG_DACQUIET_EN 0x0400 246 #define RG_LDVQUIET_EN 0x0200 247 #define RG_CKRSEL 0x0020 248 #define RG_EEEPRG_EN 0x0010 249 250 /* OCP_EEE_CONFIG3 */ 251 #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */ 252 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 253 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 254 255 /* OCP_EEE_AR */ 256 /* bit[15:14] function */ 257 #define FUN_ADDR 0x0000 258 #define FUN_DATA 0x4000 259 /* bit[4:0] device addr */ 260 #define DEVICE_ADDR 0x0007 261 262 /* OCP_EEE_DATA */ 263 #define EEE_ADDR 0x003C 264 #define EEE_DATA 0x0002 265 266 enum rtl_register_content { 267 _100bps = 0x08, 268 _10bps = 0x04, 269 LINK_STATUS = 0x02, 270 FULL_DUP = 0x01, 271 }; 272 273 #define RTL8152_MAX_TX 10 274 #define RTL8152_MAX_RX 10 275 #define INTBUFSIZE 2 276 277 #define INTR_LINK 0x0004 278 279 #define RTL8152_REQT_READ 0xc0 280 #define RTL8152_REQT_WRITE 0x40 281 #define RTL8152_REQ_GET_REGS 0x05 282 #define RTL8152_REQ_SET_REGS 0x05 283 284 #define BYTE_EN_DWORD 0xff 285 #define BYTE_EN_WORD 0x33 286 #define BYTE_EN_BYTE 0x11 287 #define BYTE_EN_SIX_BYTES 0x3f 288 #define BYTE_EN_START_MASK 0x0f 289 #define BYTE_EN_END_MASK 0xf0 290 291 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) 292 #define RTL8152_TX_TIMEOUT (HZ) 293 294 /* rtl8152 flags */ 295 enum rtl8152_flags { 296 RTL8152_UNPLUG = 0, 297 RTL8152_SET_RX_MODE, 298 WORK_ENABLE, 299 RTL8152_LINK_CHG, 300 }; 301 302 /* Define these values to match your device */ 303 #define VENDOR_ID_REALTEK 0x0bda 304 #define PRODUCT_ID_RTL8152 0x8152 305 306 #define MCU_TYPE_PLA 0x0100 307 #define MCU_TYPE_USB 0x0000 308 309 struct rx_desc { 310 u32 opts1; 311 #define RX_LEN_MASK 0x7fff 312 u32 opts2; 313 u32 opts3; 314 u32 opts4; 315 u32 opts5; 316 u32 opts6; 317 }; 318 319 struct tx_desc { 320 u32 opts1; 321 #define TX_FS (1 << 31) /* First segment of a packet */ 322 #define TX_LS (1 << 30) /* Final segment of a packet */ 323 #define TX_LEN_MASK 0x3ffff 324 325 u32 opts2; 326 #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */ 327 #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */ 328 #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */ 329 #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */ 330 }; 331 332 struct r8152; 333 334 struct rx_agg { 335 struct list_head list; 336 struct urb *urb; 337 struct r8152 *context; 338 void *buffer; 339 void *head; 340 }; 341 342 struct tx_agg { 343 struct list_head list; 344 struct urb *urb; 345 struct r8152 *context; 346 void *buffer; 347 void *head; 348 u32 skb_num; 349 u32 skb_len; 350 }; 351 352 struct r8152 { 353 unsigned long flags; 354 struct usb_device *udev; 355 struct tasklet_struct tl; 356 struct usb_interface *intf; 357 struct net_device *netdev; 358 struct urb *intr_urb; 359 struct tx_agg tx_info[RTL8152_MAX_TX]; 360 struct rx_agg rx_info[RTL8152_MAX_RX]; 361 struct list_head rx_done, tx_free; 362 struct sk_buff_head tx_queue; 363 spinlock_t rx_lock, tx_lock; 364 struct delayed_work schedule; 365 struct mii_if_info mii; 366 int intr_interval; 367 u32 msg_enable; 368 u16 ocp_base; 369 u8 *intr_buff; 370 u8 version; 371 u8 speed; 372 }; 373 374 enum rtl_version { 375 RTL_VER_UNKNOWN = 0, 376 RTL_VER_01, 377 RTL_VER_02 378 }; 379 380 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 381 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 382 */ 383 static const int multicast_filter_limit = 32; 384 static unsigned int rx_buf_sz = 16384; 385 386 static 387 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 388 { 389 int ret; 390 void *tmp; 391 392 tmp = kmalloc(size, GFP_KERNEL); 393 if (!tmp) 394 return -ENOMEM; 395 396 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 397 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 398 value, index, tmp, size, 500); 399 400 memcpy(data, tmp, size); 401 kfree(tmp); 402 403 return ret; 404 } 405 406 static 407 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 408 { 409 int ret; 410 void *tmp; 411 412 tmp = kmalloc(size, GFP_KERNEL); 413 if (!tmp) 414 return -ENOMEM; 415 416 memcpy(tmp, data, size); 417 418 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 419 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 420 value, index, tmp, size, 500); 421 422 kfree(tmp); 423 return ret; 424 } 425 426 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 427 void *data, u16 type) 428 { 429 u16 limit = 64; 430 int ret = 0; 431 432 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 433 return -ENODEV; 434 435 /* both size and indix must be 4 bytes align */ 436 if ((size & 3) || !size || (index & 3) || !data) 437 return -EPERM; 438 439 if ((u32)index + (u32)size > 0xffff) 440 return -EPERM; 441 442 while (size) { 443 if (size > limit) { 444 ret = get_registers(tp, index, type, limit, data); 445 if (ret < 0) 446 break; 447 448 index += limit; 449 data += limit; 450 size -= limit; 451 } else { 452 ret = get_registers(tp, index, type, size, data); 453 if (ret < 0) 454 break; 455 456 index += size; 457 data += size; 458 size = 0; 459 break; 460 } 461 } 462 463 return ret; 464 } 465 466 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 467 u16 size, void *data, u16 type) 468 { 469 int ret; 470 u16 byteen_start, byteen_end, byen; 471 u16 limit = 512; 472 473 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 474 return -ENODEV; 475 476 /* both size and indix must be 4 bytes align */ 477 if ((size & 3) || !size || (index & 3) || !data) 478 return -EPERM; 479 480 if ((u32)index + (u32)size > 0xffff) 481 return -EPERM; 482 483 byteen_start = byteen & BYTE_EN_START_MASK; 484 byteen_end = byteen & BYTE_EN_END_MASK; 485 486 byen = byteen_start | (byteen_start << 4); 487 ret = set_registers(tp, index, type | byen, 4, data); 488 if (ret < 0) 489 goto error1; 490 491 index += 4; 492 data += 4; 493 size -= 4; 494 495 if (size) { 496 size -= 4; 497 498 while (size) { 499 if (size > limit) { 500 ret = set_registers(tp, index, 501 type | BYTE_EN_DWORD, 502 limit, data); 503 if (ret < 0) 504 goto error1; 505 506 index += limit; 507 data += limit; 508 size -= limit; 509 } else { 510 ret = set_registers(tp, index, 511 type | BYTE_EN_DWORD, 512 size, data); 513 if (ret < 0) 514 goto error1; 515 516 index += size; 517 data += size; 518 size = 0; 519 break; 520 } 521 } 522 523 byen = byteen_end | (byteen_end >> 4); 524 ret = set_registers(tp, index, type | byen, 4, data); 525 if (ret < 0) 526 goto error1; 527 } 528 529 error1: 530 return ret; 531 } 532 533 static inline 534 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 535 { 536 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 537 } 538 539 static inline 540 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 541 { 542 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 543 } 544 545 static inline 546 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 547 { 548 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); 549 } 550 551 static inline 552 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 553 { 554 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 555 } 556 557 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 558 { 559 __le32 data; 560 561 generic_ocp_read(tp, index, sizeof(data), &data, type); 562 563 return __le32_to_cpu(data); 564 } 565 566 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 567 { 568 __le32 tmp = __cpu_to_le32(data); 569 570 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 571 } 572 573 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 574 { 575 u32 data; 576 __le32 tmp; 577 u8 shift = index & 2; 578 579 index &= ~3; 580 581 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 582 583 data = __le32_to_cpu(tmp); 584 data >>= (shift * 8); 585 data &= 0xffff; 586 587 return (u16)data; 588 } 589 590 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 591 { 592 u32 mask = 0xffff; 593 __le32 tmp; 594 u16 byen = BYTE_EN_WORD; 595 u8 shift = index & 2; 596 597 data &= mask; 598 599 if (index & 2) { 600 byen <<= shift; 601 mask <<= (shift * 8); 602 data <<= (shift * 8); 603 index &= ~3; 604 } 605 606 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 607 608 data |= __le32_to_cpu(tmp) & ~mask; 609 tmp = __cpu_to_le32(data); 610 611 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 612 } 613 614 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 615 { 616 u32 data; 617 __le32 tmp; 618 u8 shift = index & 3; 619 620 index &= ~3; 621 622 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 623 624 data = __le32_to_cpu(tmp); 625 data >>= (shift * 8); 626 data &= 0xff; 627 628 return (u8)data; 629 } 630 631 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 632 { 633 u32 mask = 0xff; 634 __le32 tmp; 635 u16 byen = BYTE_EN_BYTE; 636 u8 shift = index & 3; 637 638 data &= mask; 639 640 if (index & 3) { 641 byen <<= shift; 642 mask <<= (shift * 8); 643 data <<= (shift * 8); 644 index &= ~3; 645 } 646 647 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 648 649 data |= __le32_to_cpu(tmp) & ~mask; 650 tmp = __cpu_to_le32(data); 651 652 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 653 } 654 655 static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 656 { 657 u32 ocp_data; 658 int i; 659 660 ocp_data = PHYAR_FLAG | ((reg_addr & 0x1f) << 16) | 661 (value & 0xffff); 662 663 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data); 664 665 for (i = 20; i > 0; i--) { 666 udelay(25); 667 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR); 668 if (!(ocp_data & PHYAR_FLAG)) 669 break; 670 } 671 udelay(20); 672 } 673 674 static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 675 { 676 u32 ocp_data; 677 int i; 678 679 ocp_data = (reg_addr & 0x1f) << 16; 680 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data); 681 682 for (i = 20; i > 0; i--) { 683 udelay(25); 684 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR); 685 if (ocp_data & PHYAR_FLAG) 686 break; 687 } 688 udelay(20); 689 690 if (!(ocp_data & PHYAR_FLAG)) 691 return -EAGAIN; 692 693 return (u16)(ocp_data & 0xffff); 694 } 695 696 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 697 { 698 struct r8152 *tp = netdev_priv(netdev); 699 700 if (phy_id != R8152_PHY_ID) 701 return -EINVAL; 702 703 return r8152_mdio_read(tp, reg); 704 } 705 706 static 707 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 708 { 709 struct r8152 *tp = netdev_priv(netdev); 710 711 if (phy_id != R8152_PHY_ID) 712 return; 713 714 r8152_mdio_write(tp, reg, val); 715 } 716 717 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 718 { 719 u16 ocp_base, ocp_index; 720 721 ocp_base = addr & 0xf000; 722 if (ocp_base != tp->ocp_base) { 723 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 724 tp->ocp_base = ocp_base; 725 } 726 727 ocp_index = (addr & 0x0fff) | 0xb000; 728 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 729 } 730 731 static 732 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 733 734 static inline void set_ethernet_addr(struct r8152 *tp) 735 { 736 struct net_device *dev = tp->netdev; 737 u8 node_id[8] = {0}; 738 739 if (pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id) < 0) 740 netif_notice(tp, probe, dev, "inet addr fail\n"); 741 else { 742 memcpy(dev->dev_addr, node_id, dev->addr_len); 743 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 744 } 745 } 746 747 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 748 { 749 struct r8152 *tp = netdev_priv(netdev); 750 struct sockaddr *addr = p; 751 752 if (!is_valid_ether_addr(addr->sa_data)) 753 return -EADDRNOTAVAIL; 754 755 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 756 757 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 758 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 759 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 760 761 return 0; 762 } 763 764 static struct net_device_stats *rtl8152_get_stats(struct net_device *dev) 765 { 766 return &dev->stats; 767 } 768 769 static void read_bulk_callback(struct urb *urb) 770 { 771 struct net_device *netdev; 772 unsigned long flags; 773 int status = urb->status; 774 struct rx_agg *agg; 775 struct r8152 *tp; 776 int result; 777 778 agg = urb->context; 779 if (!agg) 780 return; 781 782 tp = agg->context; 783 if (!tp) 784 return; 785 786 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 787 return; 788 789 if (!test_bit(WORK_ENABLE, &tp->flags)) 790 return; 791 792 netdev = tp->netdev; 793 794 /* When link down, the driver would cancel all bulks. */ 795 /* This avoid the re-submitting bulk */ 796 if (!netif_carrier_ok(netdev)) 797 return; 798 799 switch (status) { 800 case 0: 801 if (urb->actual_length < ETH_ZLEN) 802 break; 803 804 spin_lock_irqsave(&tp->rx_lock, flags); 805 list_add_tail(&agg->list, &tp->rx_done); 806 spin_unlock_irqrestore(&tp->rx_lock, flags); 807 tasklet_schedule(&tp->tl); 808 return; 809 case -ESHUTDOWN: 810 set_bit(RTL8152_UNPLUG, &tp->flags); 811 netif_device_detach(tp->netdev); 812 return; 813 case -ENOENT: 814 return; /* the urb is in unlink state */ 815 case -ETIME: 816 pr_warn_ratelimited("may be reset is needed?..\n"); 817 break; 818 default: 819 pr_warn_ratelimited("Rx status %d\n", status); 820 break; 821 } 822 823 result = r8152_submit_rx(tp, agg, GFP_ATOMIC); 824 if (result == -ENODEV) { 825 netif_device_detach(tp->netdev); 826 } else if (result) { 827 spin_lock_irqsave(&tp->rx_lock, flags); 828 list_add_tail(&agg->list, &tp->rx_done); 829 spin_unlock_irqrestore(&tp->rx_lock, flags); 830 tasklet_schedule(&tp->tl); 831 } 832 } 833 834 static void write_bulk_callback(struct urb *urb) 835 { 836 struct net_device_stats *stats; 837 unsigned long flags; 838 struct tx_agg *agg; 839 struct r8152 *tp; 840 int status = urb->status; 841 842 agg = urb->context; 843 if (!agg) 844 return; 845 846 tp = agg->context; 847 if (!tp) 848 return; 849 850 stats = rtl8152_get_stats(tp->netdev); 851 if (status) { 852 pr_warn_ratelimited("Tx status %d\n", status); 853 stats->tx_errors += agg->skb_num; 854 } else { 855 stats->tx_packets += agg->skb_num; 856 stats->tx_bytes += agg->skb_len; 857 } 858 859 spin_lock_irqsave(&tp->tx_lock, flags); 860 list_add_tail(&agg->list, &tp->tx_free); 861 spin_unlock_irqrestore(&tp->tx_lock, flags); 862 863 if (!netif_carrier_ok(tp->netdev)) 864 return; 865 866 if (!test_bit(WORK_ENABLE, &tp->flags)) 867 return; 868 869 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 870 return; 871 872 if (!skb_queue_empty(&tp->tx_queue)) 873 tasklet_schedule(&tp->tl); 874 } 875 876 static void intr_callback(struct urb *urb) 877 { 878 struct r8152 *tp; 879 __u16 *d; 880 int status = urb->status; 881 int res; 882 883 tp = urb->context; 884 if (!tp) 885 return; 886 887 if (!test_bit(WORK_ENABLE, &tp->flags)) 888 return; 889 890 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 891 return; 892 893 switch (status) { 894 case 0: /* success */ 895 break; 896 case -ECONNRESET: /* unlink */ 897 case -ESHUTDOWN: 898 netif_device_detach(tp->netdev); 899 case -ENOENT: 900 return; 901 case -EOVERFLOW: 902 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 903 goto resubmit; 904 /* -EPIPE: should clear the halt */ 905 default: 906 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 907 goto resubmit; 908 } 909 910 d = urb->transfer_buffer; 911 if (INTR_LINK & __le16_to_cpu(d[0])) { 912 if (!(tp->speed & LINK_STATUS)) { 913 set_bit(RTL8152_LINK_CHG, &tp->flags); 914 schedule_delayed_work(&tp->schedule, 0); 915 } 916 } else { 917 if (tp->speed & LINK_STATUS) { 918 set_bit(RTL8152_LINK_CHG, &tp->flags); 919 schedule_delayed_work(&tp->schedule, 0); 920 } 921 } 922 923 resubmit: 924 res = usb_submit_urb(urb, GFP_ATOMIC); 925 if (res == -ENODEV) 926 netif_device_detach(tp->netdev); 927 else if (res) 928 netif_err(tp, intr, tp->netdev, 929 "can't resubmit intr, status %d\n", res); 930 } 931 932 static inline void *rx_agg_align(void *data) 933 { 934 return (void *)ALIGN((uintptr_t)data, 8); 935 } 936 937 static inline void *tx_agg_align(void *data) 938 { 939 return (void *)ALIGN((uintptr_t)data, 4); 940 } 941 942 static void free_all_mem(struct r8152 *tp) 943 { 944 int i; 945 946 for (i = 0; i < RTL8152_MAX_RX; i++) { 947 if (tp->rx_info[i].urb) { 948 usb_free_urb(tp->rx_info[i].urb); 949 tp->rx_info[i].urb = NULL; 950 } 951 952 if (tp->rx_info[i].buffer) { 953 kfree(tp->rx_info[i].buffer); 954 tp->rx_info[i].buffer = NULL; 955 tp->rx_info[i].head = NULL; 956 } 957 } 958 959 for (i = 0; i < RTL8152_MAX_TX; i++) { 960 if (tp->tx_info[i].urb) { 961 usb_free_urb(tp->tx_info[i].urb); 962 tp->tx_info[i].urb = NULL; 963 } 964 965 if (tp->tx_info[i].buffer) { 966 kfree(tp->tx_info[i].buffer); 967 tp->tx_info[i].buffer = NULL; 968 tp->tx_info[i].head = NULL; 969 } 970 } 971 972 if (tp->intr_urb) { 973 usb_free_urb(tp->intr_urb); 974 tp->intr_urb = NULL; 975 } 976 977 if (tp->intr_buff) { 978 kfree(tp->intr_buff); 979 tp->intr_buff = NULL; 980 } 981 } 982 983 static int alloc_all_mem(struct r8152 *tp) 984 { 985 struct net_device *netdev = tp->netdev; 986 struct usb_interface *intf = tp->intf; 987 struct usb_host_interface *alt = intf->cur_altsetting; 988 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 989 struct urb *urb; 990 int node, i; 991 u8 *buf; 992 993 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 994 995 spin_lock_init(&tp->rx_lock); 996 spin_lock_init(&tp->tx_lock); 997 INIT_LIST_HEAD(&tp->rx_done); 998 INIT_LIST_HEAD(&tp->tx_free); 999 skb_queue_head_init(&tp->tx_queue); 1000 1001 for (i = 0; i < RTL8152_MAX_RX; i++) { 1002 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); 1003 if (!buf) 1004 goto err1; 1005 1006 if (buf != rx_agg_align(buf)) { 1007 kfree(buf); 1008 buf = kmalloc_node(rx_buf_sz + 8, GFP_KERNEL, node); 1009 if (!buf) 1010 goto err1; 1011 } 1012 1013 urb = usb_alloc_urb(0, GFP_KERNEL); 1014 if (!urb) { 1015 kfree(buf); 1016 goto err1; 1017 } 1018 1019 INIT_LIST_HEAD(&tp->rx_info[i].list); 1020 tp->rx_info[i].context = tp; 1021 tp->rx_info[i].urb = urb; 1022 tp->rx_info[i].buffer = buf; 1023 tp->rx_info[i].head = rx_agg_align(buf); 1024 } 1025 1026 for (i = 0; i < RTL8152_MAX_TX; i++) { 1027 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); 1028 if (!buf) 1029 goto err1; 1030 1031 if (buf != tx_agg_align(buf)) { 1032 kfree(buf); 1033 buf = kmalloc_node(rx_buf_sz + 4, GFP_KERNEL, node); 1034 if (!buf) 1035 goto err1; 1036 } 1037 1038 urb = usb_alloc_urb(0, GFP_KERNEL); 1039 if (!urb) { 1040 kfree(buf); 1041 goto err1; 1042 } 1043 1044 INIT_LIST_HEAD(&tp->tx_info[i].list); 1045 tp->tx_info[i].context = tp; 1046 tp->tx_info[i].urb = urb; 1047 tp->tx_info[i].buffer = buf; 1048 tp->tx_info[i].head = tx_agg_align(buf); 1049 1050 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1051 } 1052 1053 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1054 if (!tp->intr_urb) 1055 goto err1; 1056 1057 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1058 if (!tp->intr_buff) 1059 goto err1; 1060 1061 tp->intr_interval = (int)ep_intr->desc.bInterval; 1062 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1063 tp->intr_buff, INTBUFSIZE, intr_callback, 1064 tp, tp->intr_interval); 1065 1066 return 0; 1067 1068 err1: 1069 free_all_mem(tp); 1070 return -ENOMEM; 1071 } 1072 1073 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1074 { 1075 struct tx_agg *agg = NULL; 1076 unsigned long flags; 1077 1078 spin_lock_irqsave(&tp->tx_lock, flags); 1079 if (!list_empty(&tp->tx_free)) { 1080 struct list_head *cursor; 1081 1082 cursor = tp->tx_free.next; 1083 list_del_init(cursor); 1084 agg = list_entry(cursor, struct tx_agg, list); 1085 } 1086 spin_unlock_irqrestore(&tp->tx_lock, flags); 1087 1088 return agg; 1089 } 1090 1091 static void 1092 r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb) 1093 { 1094 memset(desc, 0, sizeof(*desc)); 1095 1096 desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS); 1097 1098 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1099 __be16 protocol; 1100 u8 ip_protocol; 1101 u32 opts2 = 0; 1102 1103 if (skb->protocol == htons(ETH_P_8021Q)) 1104 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; 1105 else 1106 protocol = skb->protocol; 1107 1108 switch (protocol) { 1109 case htons(ETH_P_IP): 1110 opts2 |= IPV4_CS; 1111 ip_protocol = ip_hdr(skb)->protocol; 1112 break; 1113 1114 case htons(ETH_P_IPV6): 1115 opts2 |= IPV6_CS; 1116 ip_protocol = ipv6_hdr(skb)->nexthdr; 1117 break; 1118 1119 default: 1120 ip_protocol = IPPROTO_RAW; 1121 break; 1122 } 1123 1124 if (ip_protocol == IPPROTO_TCP) { 1125 opts2 |= TCP_CS; 1126 opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17; 1127 } else if (ip_protocol == IPPROTO_UDP) { 1128 opts2 |= UDP_CS; 1129 } else { 1130 WARN_ON_ONCE(1); 1131 } 1132 1133 desc->opts2 = cpu_to_le32(opts2); 1134 } 1135 } 1136 1137 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1138 { 1139 u32 remain; 1140 u8 *tx_data; 1141 1142 tx_data = agg->head; 1143 agg->skb_num = agg->skb_len = 0; 1144 remain = rx_buf_sz - sizeof(struct tx_desc); 1145 1146 while (remain >= ETH_ZLEN) { 1147 struct tx_desc *tx_desc; 1148 struct sk_buff *skb; 1149 unsigned int len; 1150 1151 skb = skb_dequeue(&tp->tx_queue); 1152 if (!skb) 1153 break; 1154 1155 len = skb->len; 1156 if (remain < len) { 1157 skb_queue_head(&tp->tx_queue, skb); 1158 break; 1159 } 1160 1161 tx_desc = (struct tx_desc *)tx_data; 1162 tx_data += sizeof(*tx_desc); 1163 1164 r8152_tx_csum(tp, tx_desc, skb); 1165 memcpy(tx_data, skb->data, len); 1166 agg->skb_num++; 1167 agg->skb_len += len; 1168 dev_kfree_skb_any(skb); 1169 1170 tx_data = tx_agg_align(tx_data + len); 1171 remain = rx_buf_sz - sizeof(*tx_desc) - 1172 (u32)((void *)tx_data - agg->head); 1173 } 1174 1175 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1176 agg->head, (int)(tx_data - (u8 *)agg->head), 1177 (usb_complete_t)write_bulk_callback, agg); 1178 1179 return usb_submit_urb(agg->urb, GFP_ATOMIC); 1180 } 1181 1182 static void rx_bottom(struct r8152 *tp) 1183 { 1184 unsigned long flags; 1185 struct list_head *cursor, *next; 1186 1187 spin_lock_irqsave(&tp->rx_lock, flags); 1188 list_for_each_safe(cursor, next, &tp->rx_done) { 1189 struct rx_desc *rx_desc; 1190 struct rx_agg *agg; 1191 unsigned pkt_len; 1192 int len_used = 0; 1193 struct urb *urb; 1194 u8 *rx_data; 1195 int ret; 1196 1197 list_del_init(cursor); 1198 spin_unlock_irqrestore(&tp->rx_lock, flags); 1199 1200 agg = list_entry(cursor, struct rx_agg, list); 1201 urb = agg->urb; 1202 if (urb->actual_length < ETH_ZLEN) 1203 goto submit; 1204 1205 rx_desc = agg->head; 1206 rx_data = agg->head; 1207 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1208 len_used += sizeof(struct rx_desc) + pkt_len; 1209 1210 while (urb->actual_length >= len_used) { 1211 struct net_device *netdev = tp->netdev; 1212 struct net_device_stats *stats; 1213 struct sk_buff *skb; 1214 1215 if (pkt_len < ETH_ZLEN) 1216 break; 1217 1218 stats = rtl8152_get_stats(netdev); 1219 1220 pkt_len -= 4; /* CRC */ 1221 rx_data += sizeof(struct rx_desc); 1222 1223 skb = netdev_alloc_skb_ip_align(netdev, pkt_len); 1224 if (!skb) { 1225 stats->rx_dropped++; 1226 break; 1227 } 1228 memcpy(skb->data, rx_data, pkt_len); 1229 skb_put(skb, pkt_len); 1230 skb->protocol = eth_type_trans(skb, netdev); 1231 netif_rx(skb); 1232 stats->rx_packets++; 1233 stats->rx_bytes += pkt_len; 1234 1235 rx_data = rx_agg_align(rx_data + pkt_len + 4); 1236 rx_desc = (struct rx_desc *)rx_data; 1237 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1238 len_used = (int)(rx_data - (u8 *)agg->head); 1239 len_used += sizeof(struct rx_desc) + pkt_len; 1240 } 1241 1242 submit: 1243 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1244 spin_lock_irqsave(&tp->rx_lock, flags); 1245 if (ret && ret != -ENODEV) { 1246 list_add_tail(&agg->list, next); 1247 tasklet_schedule(&tp->tl); 1248 } 1249 } 1250 spin_unlock_irqrestore(&tp->rx_lock, flags); 1251 } 1252 1253 static void tx_bottom(struct r8152 *tp) 1254 { 1255 int res; 1256 1257 do { 1258 struct tx_agg *agg; 1259 1260 if (skb_queue_empty(&tp->tx_queue)) 1261 break; 1262 1263 agg = r8152_get_tx_agg(tp); 1264 if (!agg) 1265 break; 1266 1267 res = r8152_tx_agg_fill(tp, agg); 1268 if (res) { 1269 struct net_device_stats *stats; 1270 struct net_device *netdev; 1271 unsigned long flags; 1272 1273 netdev = tp->netdev; 1274 stats = rtl8152_get_stats(netdev); 1275 1276 if (res == -ENODEV) { 1277 netif_device_detach(netdev); 1278 } else { 1279 netif_warn(tp, tx_err, netdev, 1280 "failed tx_urb %d\n", res); 1281 stats->tx_dropped += agg->skb_num; 1282 spin_lock_irqsave(&tp->tx_lock, flags); 1283 list_add_tail(&agg->list, &tp->tx_free); 1284 spin_unlock_irqrestore(&tp->tx_lock, flags); 1285 } 1286 } 1287 } while (res == 0); 1288 } 1289 1290 static void bottom_half(unsigned long data) 1291 { 1292 struct r8152 *tp; 1293 1294 tp = (struct r8152 *)data; 1295 1296 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1297 return; 1298 1299 if (!test_bit(WORK_ENABLE, &tp->flags)) 1300 return; 1301 1302 /* When link down, the driver would cancel all bulks. */ 1303 /* This avoid the re-submitting bulk */ 1304 if (!netif_carrier_ok(tp->netdev)) 1305 return; 1306 1307 rx_bottom(tp); 1308 tx_bottom(tp); 1309 } 1310 1311 static 1312 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 1313 { 1314 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 1315 agg->head, rx_buf_sz, 1316 (usb_complete_t)read_bulk_callback, agg); 1317 1318 return usb_submit_urb(agg->urb, mem_flags); 1319 } 1320 1321 static void rtl8152_tx_timeout(struct net_device *netdev) 1322 { 1323 struct r8152 *tp = netdev_priv(netdev); 1324 int i; 1325 1326 netif_warn(tp, tx_err, netdev, "Tx timeout.\n"); 1327 for (i = 0; i < RTL8152_MAX_TX; i++) 1328 usb_unlink_urb(tp->tx_info[i].urb); 1329 } 1330 1331 static void rtl8152_set_rx_mode(struct net_device *netdev) 1332 { 1333 struct r8152 *tp = netdev_priv(netdev); 1334 1335 if (tp->speed & LINK_STATUS) { 1336 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 1337 schedule_delayed_work(&tp->schedule, 0); 1338 } 1339 } 1340 1341 static void _rtl8152_set_rx_mode(struct net_device *netdev) 1342 { 1343 struct r8152 *tp = netdev_priv(netdev); 1344 u32 mc_filter[2]; /* Multicast hash filter */ 1345 __le32 tmp[2]; 1346 u32 ocp_data; 1347 1348 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 1349 netif_stop_queue(netdev); 1350 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 1351 ocp_data &= ~RCR_ACPT_ALL; 1352 ocp_data |= RCR_AB | RCR_APM; 1353 1354 if (netdev->flags & IFF_PROMISC) { 1355 /* Unconditionally log net taps. */ 1356 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 1357 ocp_data |= RCR_AM | RCR_AAP; 1358 mc_filter[1] = mc_filter[0] = 0xffffffff; 1359 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 1360 (netdev->flags & IFF_ALLMULTI)) { 1361 /* Too many to filter perfectly -- accept all multicasts. */ 1362 ocp_data |= RCR_AM; 1363 mc_filter[1] = mc_filter[0] = 0xffffffff; 1364 } else { 1365 struct netdev_hw_addr *ha; 1366 1367 mc_filter[1] = mc_filter[0] = 0; 1368 netdev_for_each_mc_addr(ha, netdev) { 1369 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 1370 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 1371 ocp_data |= RCR_AM; 1372 } 1373 } 1374 1375 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 1376 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 1377 1378 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 1379 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 1380 netif_wake_queue(netdev); 1381 } 1382 1383 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 1384 struct net_device *netdev) 1385 { 1386 struct r8152 *tp = netdev_priv(netdev); 1387 struct net_device_stats *stats = rtl8152_get_stats(netdev); 1388 unsigned long flags; 1389 struct tx_agg *agg = NULL; 1390 struct tx_desc *tx_desc; 1391 unsigned int len; 1392 u8 *tx_data; 1393 int res; 1394 1395 skb_tx_timestamp(skb); 1396 1397 /* If tx_queue is not empty, it means at least one previous packt */ 1398 /* is waiting for sending. Don't send current one before it. */ 1399 if (skb_queue_empty(&tp->tx_queue)) 1400 agg = r8152_get_tx_agg(tp); 1401 1402 if (!agg) { 1403 skb_queue_tail(&tp->tx_queue, skb); 1404 return NETDEV_TX_OK; 1405 } 1406 1407 tx_desc = (struct tx_desc *)agg->head; 1408 tx_data = agg->head + sizeof(*tx_desc); 1409 agg->skb_num = agg->skb_len = 0; 1410 1411 len = skb->len; 1412 r8152_tx_csum(tp, tx_desc, skb); 1413 memcpy(tx_data, skb->data, len); 1414 dev_kfree_skb_any(skb); 1415 agg->skb_num++; 1416 agg->skb_len += len; 1417 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1418 agg->head, len + sizeof(*tx_desc), 1419 (usb_complete_t)write_bulk_callback, agg); 1420 res = usb_submit_urb(agg->urb, GFP_ATOMIC); 1421 if (res) { 1422 /* Can we get/handle EPIPE here? */ 1423 if (res == -ENODEV) { 1424 netif_device_detach(tp->netdev); 1425 } else { 1426 netif_warn(tp, tx_err, netdev, 1427 "failed tx_urb %d\n", res); 1428 stats->tx_dropped++; 1429 spin_lock_irqsave(&tp->tx_lock, flags); 1430 list_add_tail(&agg->list, &tp->tx_free); 1431 spin_unlock_irqrestore(&tp->tx_lock, flags); 1432 } 1433 } 1434 1435 return NETDEV_TX_OK; 1436 } 1437 1438 static void r8152b_reset_packet_filter(struct r8152 *tp) 1439 { 1440 u32 ocp_data; 1441 1442 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 1443 ocp_data &= ~FMC_FCR_MCU_EN; 1444 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 1445 ocp_data |= FMC_FCR_MCU_EN; 1446 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 1447 } 1448 1449 static void rtl8152_nic_reset(struct r8152 *tp) 1450 { 1451 int i; 1452 1453 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 1454 1455 for (i = 0; i < 1000; i++) { 1456 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 1457 break; 1458 udelay(100); 1459 } 1460 } 1461 1462 static inline u8 rtl8152_get_speed(struct r8152 *tp) 1463 { 1464 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 1465 } 1466 1467 static int rtl8152_enable(struct r8152 *tp) 1468 { 1469 u32 ocp_data; 1470 int i, ret; 1471 u8 speed; 1472 1473 speed = rtl8152_get_speed(tp); 1474 if (speed & _10bps) { 1475 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 1476 ocp_data |= EEEP_CR_EEEP_TX; 1477 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 1478 } else { 1479 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 1480 ocp_data &= ~EEEP_CR_EEEP_TX; 1481 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 1482 } 1483 1484 r8152b_reset_packet_filter(tp); 1485 1486 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 1487 ocp_data |= CR_RE | CR_TE; 1488 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 1489 1490 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 1491 ocp_data &= ~RXDY_GATED_EN; 1492 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 1493 1494 INIT_LIST_HEAD(&tp->rx_done); 1495 ret = 0; 1496 for (i = 0; i < RTL8152_MAX_RX; i++) { 1497 INIT_LIST_HEAD(&tp->rx_info[i].list); 1498 ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 1499 } 1500 1501 return ret; 1502 } 1503 1504 static void rtl8152_disable(struct r8152 *tp) 1505 { 1506 struct net_device_stats *stats = rtl8152_get_stats(tp->netdev); 1507 struct sk_buff *skb; 1508 u32 ocp_data; 1509 int i; 1510 1511 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 1512 ocp_data &= ~RCR_ACPT_ALL; 1513 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 1514 1515 while ((skb = skb_dequeue(&tp->tx_queue))) { 1516 dev_kfree_skb(skb); 1517 stats->tx_dropped++; 1518 } 1519 1520 for (i = 0; i < RTL8152_MAX_TX; i++) 1521 usb_kill_urb(tp->tx_info[i].urb); 1522 1523 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 1524 ocp_data |= RXDY_GATED_EN; 1525 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 1526 1527 for (i = 0; i < 1000; i++) { 1528 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 1529 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 1530 break; 1531 mdelay(1); 1532 } 1533 1534 for (i = 0; i < 1000; i++) { 1535 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 1536 break; 1537 mdelay(1); 1538 } 1539 1540 for (i = 0; i < RTL8152_MAX_RX; i++) 1541 usb_kill_urb(tp->rx_info[i].urb); 1542 1543 rtl8152_nic_reset(tp); 1544 } 1545 1546 static void r8152b_exit_oob(struct r8152 *tp) 1547 { 1548 u32 ocp_data; 1549 int i; 1550 1551 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 1552 ocp_data &= ~RCR_ACPT_ALL; 1553 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 1554 1555 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 1556 ocp_data |= RXDY_GATED_EN; 1557 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 1558 1559 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1560 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 1561 1562 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 1563 ocp_data &= ~NOW_IS_OOB; 1564 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 1565 1566 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 1567 ocp_data &= ~MCU_BORW_EN; 1568 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 1569 1570 for (i = 0; i < 1000; i++) { 1571 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 1572 if (ocp_data & LINK_LIST_READY) 1573 break; 1574 mdelay(1); 1575 } 1576 1577 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 1578 ocp_data |= RE_INIT_LL; 1579 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 1580 1581 for (i = 0; i < 1000; i++) { 1582 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 1583 if (ocp_data & LINK_LIST_READY) 1584 break; 1585 mdelay(1); 1586 } 1587 1588 rtl8152_nic_reset(tp); 1589 1590 /* rx share fifo credit full threshold */ 1591 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 1592 1593 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT); 1594 ocp_data &= STAT_SPEED_MASK; 1595 if (ocp_data == STAT_SPEED_FULL) { 1596 /* rx share fifo credit near full threshold */ 1597 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 1598 RXFIFO_THR2_FULL); 1599 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 1600 RXFIFO_THR3_FULL); 1601 } else { 1602 /* rx share fifo credit near full threshold */ 1603 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 1604 RXFIFO_THR2_HIGH); 1605 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 1606 RXFIFO_THR3_HIGH); 1607 } 1608 1609 /* TX share fifo free credit full threshold */ 1610 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 1611 1612 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 1613 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_BUF_THR); 1614 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 1615 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 1616 1617 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 1618 ocp_data &= ~CPCR_RX_VLAN; 1619 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 1620 1621 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 1622 1623 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 1624 ocp_data |= TCR0_AUTO_FIFO; 1625 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 1626 } 1627 1628 static void r8152b_enter_oob(struct r8152 *tp) 1629 { 1630 u32 ocp_data; 1631 int i; 1632 1633 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 1634 ocp_data &= ~NOW_IS_OOB; 1635 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 1636 1637 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 1638 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 1639 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 1640 1641 rtl8152_disable(tp); 1642 1643 for (i = 0; i < 1000; i++) { 1644 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 1645 if (ocp_data & LINK_LIST_READY) 1646 break; 1647 mdelay(1); 1648 } 1649 1650 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 1651 ocp_data |= RE_INIT_LL; 1652 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 1653 1654 for (i = 0; i < 1000; i++) { 1655 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 1656 if (ocp_data & LINK_LIST_READY) 1657 break; 1658 mdelay(1); 1659 } 1660 1661 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 1662 1663 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 1664 ocp_data |= MAGIC_EN; 1665 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 1666 1667 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 1668 ocp_data |= CPCR_RX_VLAN; 1669 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 1670 1671 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 1672 ocp_data |= ALDPS_PROXY_MODE; 1673 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 1674 1675 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 1676 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 1677 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 1678 1679 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN); 1680 1681 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 1682 ocp_data &= ~RXDY_GATED_EN; 1683 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 1684 1685 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 1686 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 1687 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 1688 } 1689 1690 static void r8152b_disable_aldps(struct r8152 *tp) 1691 { 1692 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); 1693 msleep(20); 1694 } 1695 1696 static inline void r8152b_enable_aldps(struct r8152 *tp) 1697 { 1698 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 1699 LINKENA | DIS_SDSAVE); 1700 } 1701 1702 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 1703 { 1704 u16 bmcr, anar; 1705 int ret = 0; 1706 1707 cancel_delayed_work_sync(&tp->schedule); 1708 anar = r8152_mdio_read(tp, MII_ADVERTISE); 1709 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 1710 ADVERTISE_100HALF | ADVERTISE_100FULL); 1711 1712 if (autoneg == AUTONEG_DISABLE) { 1713 if (speed == SPEED_10) { 1714 bmcr = 0; 1715 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 1716 } else if (speed == SPEED_100) { 1717 bmcr = BMCR_SPEED100; 1718 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 1719 } else { 1720 ret = -EINVAL; 1721 goto out; 1722 } 1723 1724 if (duplex == DUPLEX_FULL) 1725 bmcr |= BMCR_FULLDPLX; 1726 } else { 1727 if (speed == SPEED_10) { 1728 if (duplex == DUPLEX_FULL) 1729 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 1730 else 1731 anar |= ADVERTISE_10HALF; 1732 } else if (speed == SPEED_100) { 1733 if (duplex == DUPLEX_FULL) { 1734 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 1735 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 1736 } else { 1737 anar |= ADVERTISE_10HALF; 1738 anar |= ADVERTISE_100HALF; 1739 } 1740 } else { 1741 ret = -EINVAL; 1742 goto out; 1743 } 1744 1745 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 1746 } 1747 1748 r8152_mdio_write(tp, MII_ADVERTISE, anar); 1749 r8152_mdio_write(tp, MII_BMCR, bmcr); 1750 1751 out: 1752 1753 return ret; 1754 } 1755 1756 static void rtl8152_down(struct r8152 *tp) 1757 { 1758 u32 ocp_data; 1759 1760 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 1761 ocp_data &= ~POWER_CUT; 1762 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 1763 1764 r8152b_disable_aldps(tp); 1765 r8152b_enter_oob(tp); 1766 r8152b_enable_aldps(tp); 1767 } 1768 1769 static void set_carrier(struct r8152 *tp) 1770 { 1771 struct net_device *netdev = tp->netdev; 1772 u8 speed; 1773 1774 clear_bit(RTL8152_LINK_CHG, &tp->flags); 1775 speed = rtl8152_get_speed(tp); 1776 1777 if (speed & LINK_STATUS) { 1778 if (!(tp->speed & LINK_STATUS)) { 1779 rtl8152_enable(tp); 1780 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 1781 netif_carrier_on(netdev); 1782 } 1783 } else { 1784 if (tp->speed & LINK_STATUS) { 1785 netif_carrier_off(netdev); 1786 tasklet_disable(&tp->tl); 1787 rtl8152_disable(tp); 1788 tasklet_enable(&tp->tl); 1789 } 1790 } 1791 tp->speed = speed; 1792 } 1793 1794 static void rtl_work_func_t(struct work_struct *work) 1795 { 1796 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 1797 1798 if (!test_bit(WORK_ENABLE, &tp->flags)) 1799 goto out1; 1800 1801 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1802 goto out1; 1803 1804 if (test_bit(RTL8152_LINK_CHG, &tp->flags)) 1805 set_carrier(tp); 1806 1807 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) 1808 _rtl8152_set_rx_mode(tp->netdev); 1809 1810 out1: 1811 return; 1812 } 1813 1814 static int rtl8152_open(struct net_device *netdev) 1815 { 1816 struct r8152 *tp = netdev_priv(netdev); 1817 int res = 0; 1818 1819 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 1820 if (res) { 1821 if (res == -ENODEV) 1822 netif_device_detach(tp->netdev); 1823 netif_warn(tp, ifup, netdev, 1824 "intr_urb submit failed: %d\n", res); 1825 return res; 1826 } 1827 1828 rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL); 1829 tp->speed = 0; 1830 netif_carrier_off(netdev); 1831 netif_start_queue(netdev); 1832 set_bit(WORK_ENABLE, &tp->flags); 1833 1834 return res; 1835 } 1836 1837 static int rtl8152_close(struct net_device *netdev) 1838 { 1839 struct r8152 *tp = netdev_priv(netdev); 1840 int res = 0; 1841 1842 usb_kill_urb(tp->intr_urb); 1843 clear_bit(WORK_ENABLE, &tp->flags); 1844 cancel_delayed_work_sync(&tp->schedule); 1845 netif_stop_queue(netdev); 1846 tasklet_disable(&tp->tl); 1847 rtl8152_disable(tp); 1848 tasklet_enable(&tp->tl); 1849 1850 return res; 1851 } 1852 1853 static void rtl_clear_bp(struct r8152 *tp) 1854 { 1855 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0); 1856 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0); 1857 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0); 1858 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0); 1859 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0); 1860 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0); 1861 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0); 1862 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0); 1863 mdelay(3); 1864 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0); 1865 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0); 1866 } 1867 1868 static void r8152b_enable_eee(struct r8152 *tp) 1869 { 1870 u32 ocp_data; 1871 1872 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 1873 ocp_data |= EEE_RX_EN | EEE_TX_EN; 1874 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 1875 ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN | 1876 EEE_10_CAP | EEE_NWAY_EN | 1877 TX_QUIET_EN | RX_QUIET_EN | 1878 SDRISETIME | RG_RXLPI_MSK_HFDUP | 1879 SDFALLTIME); 1880 ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN | 1881 RG_LDVQUIET_EN | RG_CKRSEL | 1882 RG_EEEPRG_EN); 1883 ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH); 1884 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR); 1885 ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR); 1886 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR); 1887 ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA); 1888 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 1889 } 1890 1891 static void r8152b_enable_fc(struct r8152 *tp) 1892 { 1893 u16 anar; 1894 1895 anar = r8152_mdio_read(tp, MII_ADVERTISE); 1896 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 1897 r8152_mdio_write(tp, MII_ADVERTISE, anar); 1898 } 1899 1900 static void r8152b_hw_phy_cfg(struct r8152 *tp) 1901 { 1902 r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE); 1903 r8152b_disable_aldps(tp); 1904 } 1905 1906 static void r8152b_init(struct r8152 *tp) 1907 { 1908 u32 ocp_data; 1909 int i; 1910 1911 rtl_clear_bp(tp); 1912 1913 if (tp->version == RTL_VER_01) { 1914 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 1915 ocp_data &= ~LED_MODE_MASK; 1916 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 1917 } 1918 1919 r8152b_hw_phy_cfg(tp); 1920 1921 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 1922 ocp_data &= ~POWER_CUT; 1923 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 1924 1925 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 1926 ocp_data &= ~RWSUME_INDICATE; 1927 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 1928 1929 r8152b_exit_oob(tp); 1930 1931 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 1932 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 1933 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 1934 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 1935 ocp_data &= ~MCU_CLK_RATIO_MASK; 1936 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 1937 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 1938 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 1939 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 1940 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 1941 1942 r8152b_enable_eee(tp); 1943 r8152b_enable_aldps(tp); 1944 r8152b_enable_fc(tp); 1945 1946 r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | 1947 BMCR_ANRESTART); 1948 for (i = 0; i < 100; i++) { 1949 udelay(100); 1950 if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET)) 1951 break; 1952 } 1953 1954 /* enable rx aggregation */ 1955 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 1956 ocp_data &= ~RX_AGG_DISABLE; 1957 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 1958 } 1959 1960 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 1961 { 1962 struct r8152 *tp = usb_get_intfdata(intf); 1963 1964 netif_device_detach(tp->netdev); 1965 1966 if (netif_running(tp->netdev)) { 1967 clear_bit(WORK_ENABLE, &tp->flags); 1968 usb_kill_urb(tp->intr_urb); 1969 cancel_delayed_work_sync(&tp->schedule); 1970 tasklet_disable(&tp->tl); 1971 } 1972 1973 rtl8152_down(tp); 1974 1975 return 0; 1976 } 1977 1978 static int rtl8152_resume(struct usb_interface *intf) 1979 { 1980 struct r8152 *tp = usb_get_intfdata(intf); 1981 1982 r8152b_init(tp); 1983 netif_device_attach(tp->netdev); 1984 if (netif_running(tp->netdev)) { 1985 rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL); 1986 tp->speed = 0; 1987 netif_carrier_off(tp->netdev); 1988 set_bit(WORK_ENABLE, &tp->flags); 1989 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 1990 tasklet_enable(&tp->tl); 1991 } 1992 1993 return 0; 1994 } 1995 1996 static void rtl8152_get_drvinfo(struct net_device *netdev, 1997 struct ethtool_drvinfo *info) 1998 { 1999 struct r8152 *tp = netdev_priv(netdev); 2000 2001 strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN); 2002 strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN); 2003 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 2004 } 2005 2006 static 2007 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) 2008 { 2009 struct r8152 *tp = netdev_priv(netdev); 2010 2011 if (!tp->mii.mdio_read) 2012 return -EOPNOTSUPP; 2013 2014 return mii_ethtool_gset(&tp->mii, cmd); 2015 } 2016 2017 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2018 { 2019 struct r8152 *tp = netdev_priv(dev); 2020 2021 return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); 2022 } 2023 2024 static struct ethtool_ops ops = { 2025 .get_drvinfo = rtl8152_get_drvinfo, 2026 .get_settings = rtl8152_get_settings, 2027 .set_settings = rtl8152_set_settings, 2028 .get_link = ethtool_op_get_link, 2029 }; 2030 2031 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 2032 { 2033 struct r8152 *tp = netdev_priv(netdev); 2034 struct mii_ioctl_data *data = if_mii(rq); 2035 int res = 0; 2036 2037 switch (cmd) { 2038 case SIOCGMIIPHY: 2039 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 2040 break; 2041 2042 case SIOCGMIIREG: 2043 data->val_out = r8152_mdio_read(tp, data->reg_num); 2044 break; 2045 2046 case SIOCSMIIREG: 2047 if (!capable(CAP_NET_ADMIN)) { 2048 res = -EPERM; 2049 break; 2050 } 2051 r8152_mdio_write(tp, data->reg_num, data->val_in); 2052 break; 2053 2054 default: 2055 res = -EOPNOTSUPP; 2056 } 2057 2058 return res; 2059 } 2060 2061 static const struct net_device_ops rtl8152_netdev_ops = { 2062 .ndo_open = rtl8152_open, 2063 .ndo_stop = rtl8152_close, 2064 .ndo_do_ioctl = rtl8152_ioctl, 2065 .ndo_start_xmit = rtl8152_start_xmit, 2066 .ndo_tx_timeout = rtl8152_tx_timeout, 2067 .ndo_set_rx_mode = rtl8152_set_rx_mode, 2068 .ndo_set_mac_address = rtl8152_set_mac_address, 2069 2070 .ndo_change_mtu = eth_change_mtu, 2071 .ndo_validate_addr = eth_validate_addr, 2072 }; 2073 2074 static void r8152b_get_version(struct r8152 *tp) 2075 { 2076 u32 ocp_data; 2077 u16 version; 2078 2079 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); 2080 version = (u16)(ocp_data & VERSION_MASK); 2081 2082 switch (version) { 2083 case 0x4c00: 2084 tp->version = RTL_VER_01; 2085 break; 2086 case 0x4c10: 2087 tp->version = RTL_VER_02; 2088 break; 2089 default: 2090 netif_info(tp, probe, tp->netdev, 2091 "Unknown version 0x%04x\n", version); 2092 break; 2093 } 2094 } 2095 2096 static int rtl8152_probe(struct usb_interface *intf, 2097 const struct usb_device_id *id) 2098 { 2099 struct usb_device *udev = interface_to_usbdev(intf); 2100 struct r8152 *tp; 2101 struct net_device *netdev; 2102 int ret; 2103 2104 if (udev->actconfig->desc.bConfigurationValue != 1) { 2105 usb_driver_set_configuration(udev, 1); 2106 return -ENODEV; 2107 } 2108 2109 netdev = alloc_etherdev(sizeof(struct r8152)); 2110 if (!netdev) { 2111 dev_err(&intf->dev, "Out of memory"); 2112 return -ENOMEM; 2113 } 2114 2115 SET_NETDEV_DEV(netdev, &intf->dev); 2116 tp = netdev_priv(netdev); 2117 tp->msg_enable = 0x7FFF; 2118 2119 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp); 2120 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 2121 2122 tp->udev = udev; 2123 tp->netdev = netdev; 2124 tp->intf = intf; 2125 netdev->netdev_ops = &rtl8152_netdev_ops; 2126 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 2127 2128 netdev->features |= NETIF_F_IP_CSUM; 2129 netdev->hw_features = NETIF_F_IP_CSUM; 2130 SET_ETHTOOL_OPS(netdev, &ops); 2131 2132 tp->mii.dev = netdev; 2133 tp->mii.mdio_read = read_mii_word; 2134 tp->mii.mdio_write = write_mii_word; 2135 tp->mii.phy_id_mask = 0x3f; 2136 tp->mii.reg_num_mask = 0x1f; 2137 tp->mii.phy_id = R8152_PHY_ID; 2138 tp->mii.supports_gmii = 0; 2139 2140 r8152b_get_version(tp); 2141 r8152b_init(tp); 2142 set_ethernet_addr(tp); 2143 2144 ret = alloc_all_mem(tp); 2145 if (ret) 2146 goto out; 2147 2148 usb_set_intfdata(intf, tp); 2149 2150 ret = register_netdev(netdev); 2151 if (ret != 0) { 2152 netif_err(tp, probe, netdev, "couldn't register the device"); 2153 goto out1; 2154 } 2155 2156 netif_info(tp, probe, netdev, "%s", DRIVER_VERSION); 2157 2158 return 0; 2159 2160 out1: 2161 usb_set_intfdata(intf, NULL); 2162 out: 2163 free_netdev(netdev); 2164 return ret; 2165 } 2166 2167 static void rtl8152_unload(struct r8152 *tp) 2168 { 2169 u32 ocp_data; 2170 2171 if (tp->version != RTL_VER_01) { 2172 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2173 ocp_data |= POWER_CUT; 2174 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2175 } 2176 2177 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2178 ocp_data &= ~RWSUME_INDICATE; 2179 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2180 } 2181 2182 static void rtl8152_disconnect(struct usb_interface *intf) 2183 { 2184 struct r8152 *tp = usb_get_intfdata(intf); 2185 2186 usb_set_intfdata(intf, NULL); 2187 if (tp) { 2188 set_bit(RTL8152_UNPLUG, &tp->flags); 2189 tasklet_kill(&tp->tl); 2190 unregister_netdev(tp->netdev); 2191 rtl8152_unload(tp); 2192 free_all_mem(tp); 2193 free_netdev(tp->netdev); 2194 } 2195 } 2196 2197 /* table of devices that work with this driver */ 2198 static struct usb_device_id rtl8152_table[] = { 2199 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)}, 2200 {} 2201 }; 2202 2203 MODULE_DEVICE_TABLE(usb, rtl8152_table); 2204 2205 static struct usb_driver rtl8152_driver = { 2206 .name = MODULENAME, 2207 .id_table = rtl8152_table, 2208 .probe = rtl8152_probe, 2209 .disconnect = rtl8152_disconnect, 2210 .suspend = rtl8152_suspend, 2211 .resume = rtl8152_resume, 2212 .reset_resume = rtl8152_resume, 2213 }; 2214 2215 module_usb_driver(rtl8152_driver); 2216 2217 MODULE_AUTHOR(DRIVER_AUTHOR); 2218 MODULE_DESCRIPTION(DRIVER_DESC); 2219 MODULE_LICENSE("GPL"); 2220