1 /* 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2 as published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/signal.h> 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/usb.h> 18 #include <linux/crc32.h> 19 #include <linux/if_vlan.h> 20 #include <linux/uaccess.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include <net/ip6_checksum.h> 25 26 /* Version Information */ 27 #define DRIVER_VERSION "v1.06.0 (2014/03/03)" 28 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 29 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 30 #define MODULENAME "r8152" 31 32 #define R8152_PHY_ID 32 33 34 #define PLA_IDR 0xc000 35 #define PLA_RCR 0xc010 36 #define PLA_RMS 0xc016 37 #define PLA_RXFIFO_CTRL0 0xc0a0 38 #define PLA_RXFIFO_CTRL1 0xc0a4 39 #define PLA_RXFIFO_CTRL2 0xc0a8 40 #define PLA_FMC 0xc0b4 41 #define PLA_CFG_WOL 0xc0b6 42 #define PLA_TEREDO_CFG 0xc0bc 43 #define PLA_MAR 0xcd00 44 #define PLA_BACKUP 0xd000 45 #define PAL_BDC_CR 0xd1a0 46 #define PLA_TEREDO_TIMER 0xd2cc 47 #define PLA_REALWOW_TIMER 0xd2e8 48 #define PLA_LEDSEL 0xdd90 49 #define PLA_LED_FEATURE 0xdd92 50 #define PLA_PHYAR 0xde00 51 #define PLA_BOOT_CTRL 0xe004 52 #define PLA_GPHY_INTR_IMR 0xe022 53 #define PLA_EEE_CR 0xe040 54 #define PLA_EEEP_CR 0xe080 55 #define PLA_MAC_PWR_CTRL 0xe0c0 56 #define PLA_MAC_PWR_CTRL2 0xe0ca 57 #define PLA_MAC_PWR_CTRL3 0xe0cc 58 #define PLA_MAC_PWR_CTRL4 0xe0ce 59 #define PLA_WDT6_CTRL 0xe428 60 #define PLA_TCR0 0xe610 61 #define PLA_TCR1 0xe612 62 #define PLA_MTPS 0xe615 63 #define PLA_TXFIFO_CTRL 0xe618 64 #define PLA_RSTTALLY 0xe800 65 #define PLA_CR 0xe813 66 #define PLA_CRWECR 0xe81c 67 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 68 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 69 #define PLA_CONFIG5 0xe822 70 #define PLA_PHY_PWR 0xe84c 71 #define PLA_OOB_CTRL 0xe84f 72 #define PLA_CPCR 0xe854 73 #define PLA_MISC_0 0xe858 74 #define PLA_MISC_1 0xe85a 75 #define PLA_OCP_GPHY_BASE 0xe86c 76 #define PLA_TALLYCNT 0xe890 77 #define PLA_SFF_STS_7 0xe8de 78 #define PLA_PHYSTATUS 0xe908 79 #define PLA_BP_BA 0xfc26 80 #define PLA_BP_0 0xfc28 81 #define PLA_BP_1 0xfc2a 82 #define PLA_BP_2 0xfc2c 83 #define PLA_BP_3 0xfc2e 84 #define PLA_BP_4 0xfc30 85 #define PLA_BP_5 0xfc32 86 #define PLA_BP_6 0xfc34 87 #define PLA_BP_7 0xfc36 88 #define PLA_BP_EN 0xfc38 89 90 #define USB_U2P3_CTRL 0xb460 91 #define USB_DEV_STAT 0xb808 92 #define USB_USB_CTRL 0xd406 93 #define USB_PHY_CTRL 0xd408 94 #define USB_TX_AGG 0xd40a 95 #define USB_RX_BUF_TH 0xd40c 96 #define USB_USB_TIMER 0xd428 97 #define USB_RX_EARLY_AGG 0xd42c 98 #define USB_PM_CTRL_STATUS 0xd432 99 #define USB_TX_DMA 0xd434 100 #define USB_TOLERANCE 0xd490 101 #define USB_LPM_CTRL 0xd41a 102 #define USB_UPS_CTRL 0xd800 103 #define USB_MISC_0 0xd81a 104 #define USB_POWER_CUT 0xd80a 105 #define USB_AFE_CTRL2 0xd824 106 #define USB_WDT11_CTRL 0xe43c 107 #define USB_BP_BA 0xfc26 108 #define USB_BP_0 0xfc28 109 #define USB_BP_1 0xfc2a 110 #define USB_BP_2 0xfc2c 111 #define USB_BP_3 0xfc2e 112 #define USB_BP_4 0xfc30 113 #define USB_BP_5 0xfc32 114 #define USB_BP_6 0xfc34 115 #define USB_BP_7 0xfc36 116 #define USB_BP_EN 0xfc38 117 118 /* OCP Registers */ 119 #define OCP_ALDPS_CONFIG 0x2010 120 #define OCP_EEE_CONFIG1 0x2080 121 #define OCP_EEE_CONFIG2 0x2092 122 #define OCP_EEE_CONFIG3 0x2094 123 #define OCP_BASE_MII 0xa400 124 #define OCP_EEE_AR 0xa41a 125 #define OCP_EEE_DATA 0xa41c 126 #define OCP_PHY_STATUS 0xa420 127 #define OCP_POWER_CFG 0xa430 128 #define OCP_EEE_CFG 0xa432 129 #define OCP_SRAM_ADDR 0xa436 130 #define OCP_SRAM_DATA 0xa438 131 #define OCP_DOWN_SPEED 0xa442 132 #define OCP_EEE_CFG2 0xa5d0 133 #define OCP_ADC_CFG 0xbc06 134 135 /* SRAM Register */ 136 #define SRAM_LPF_CFG 0x8012 137 #define SRAM_10M_AMP1 0x8080 138 #define SRAM_10M_AMP2 0x8082 139 #define SRAM_IMPEDANCE 0x8084 140 141 /* PLA_RCR */ 142 #define RCR_AAP 0x00000001 143 #define RCR_APM 0x00000002 144 #define RCR_AM 0x00000004 145 #define RCR_AB 0x00000008 146 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 147 148 /* PLA_RXFIFO_CTRL0 */ 149 #define RXFIFO_THR1_NORMAL 0x00080002 150 #define RXFIFO_THR1_OOB 0x01800003 151 152 /* PLA_RXFIFO_CTRL1 */ 153 #define RXFIFO_THR2_FULL 0x00000060 154 #define RXFIFO_THR2_HIGH 0x00000038 155 #define RXFIFO_THR2_OOB 0x0000004a 156 #define RXFIFO_THR2_NORMAL 0x00a0 157 158 /* PLA_RXFIFO_CTRL2 */ 159 #define RXFIFO_THR3_FULL 0x00000078 160 #define RXFIFO_THR3_HIGH 0x00000048 161 #define RXFIFO_THR3_OOB 0x0000005a 162 #define RXFIFO_THR3_NORMAL 0x0110 163 164 /* PLA_TXFIFO_CTRL */ 165 #define TXFIFO_THR_NORMAL 0x00400008 166 #define TXFIFO_THR_NORMAL2 0x01000008 167 168 /* PLA_FMC */ 169 #define FMC_FCR_MCU_EN 0x0001 170 171 /* PLA_EEEP_CR */ 172 #define EEEP_CR_EEEP_TX 0x0002 173 174 /* PLA_WDT6_CTRL */ 175 #define WDT6_SET_MODE 0x0010 176 177 /* PLA_TCR0 */ 178 #define TCR0_TX_EMPTY 0x0800 179 #define TCR0_AUTO_FIFO 0x0080 180 181 /* PLA_TCR1 */ 182 #define VERSION_MASK 0x7cf0 183 184 /* PLA_MTPS */ 185 #define MTPS_JUMBO (12 * 1024 / 64) 186 #define MTPS_DEFAULT (6 * 1024 / 64) 187 188 /* PLA_RSTTALLY */ 189 #define TALLY_RESET 0x0001 190 191 /* PLA_CR */ 192 #define CR_RST 0x10 193 #define CR_RE 0x08 194 #define CR_TE 0x04 195 196 /* PLA_CRWECR */ 197 #define CRWECR_NORAML 0x00 198 #define CRWECR_CONFIG 0xc0 199 200 /* PLA_OOB_CTRL */ 201 #define NOW_IS_OOB 0x80 202 #define TXFIFO_EMPTY 0x20 203 #define RXFIFO_EMPTY 0x10 204 #define LINK_LIST_READY 0x02 205 #define DIS_MCU_CLROOB 0x01 206 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 207 208 /* PLA_MISC_1 */ 209 #define RXDY_GATED_EN 0x0008 210 211 /* PLA_SFF_STS_7 */ 212 #define RE_INIT_LL 0x8000 213 #define MCU_BORW_EN 0x4000 214 215 /* PLA_CPCR */ 216 #define CPCR_RX_VLAN 0x0040 217 218 /* PLA_CFG_WOL */ 219 #define MAGIC_EN 0x0001 220 221 /* PLA_TEREDO_CFG */ 222 #define TEREDO_SEL 0x8000 223 #define TEREDO_WAKE_MASK 0x7f00 224 #define TEREDO_RS_EVENT_MASK 0x00fe 225 #define OOB_TEREDO_EN 0x0001 226 227 /* PAL_BDC_CR */ 228 #define ALDPS_PROXY_MODE 0x0001 229 230 /* PLA_CONFIG34 */ 231 #define LINK_ON_WAKE_EN 0x0010 232 #define LINK_OFF_WAKE_EN 0x0008 233 234 /* PLA_CONFIG5 */ 235 #define BWF_EN 0x0040 236 #define MWF_EN 0x0020 237 #define UWF_EN 0x0010 238 #define LAN_WAKE_EN 0x0002 239 240 /* PLA_LED_FEATURE */ 241 #define LED_MODE_MASK 0x0700 242 243 /* PLA_PHY_PWR */ 244 #define TX_10M_IDLE_EN 0x0080 245 #define PFM_PWM_SWITCH 0x0040 246 247 /* PLA_MAC_PWR_CTRL */ 248 #define D3_CLK_GATED_EN 0x00004000 249 #define MCU_CLK_RATIO 0x07010f07 250 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 251 #define ALDPS_SPDWN_RATIO 0x0f87 252 253 /* PLA_MAC_PWR_CTRL2 */ 254 #define EEE_SPDWN_RATIO 0x8007 255 256 /* PLA_MAC_PWR_CTRL3 */ 257 #define PKT_AVAIL_SPDWN_EN 0x0100 258 #define SUSPEND_SPDWN_EN 0x0004 259 #define U1U2_SPDWN_EN 0x0002 260 #define L1_SPDWN_EN 0x0001 261 262 /* PLA_MAC_PWR_CTRL4 */ 263 #define PWRSAVE_SPDWN_EN 0x1000 264 #define RXDV_SPDWN_EN 0x0800 265 #define TX10MIDLE_EN 0x0100 266 #define TP100_SPDWN_EN 0x0020 267 #define TP500_SPDWN_EN 0x0010 268 #define TP1000_SPDWN_EN 0x0008 269 #define EEE_SPDWN_EN 0x0001 270 271 /* PLA_GPHY_INTR_IMR */ 272 #define GPHY_STS_MSK 0x0001 273 #define SPEED_DOWN_MSK 0x0002 274 #define SPDWN_RXDV_MSK 0x0004 275 #define SPDWN_LINKCHG_MSK 0x0008 276 277 /* PLA_PHYAR */ 278 #define PHYAR_FLAG 0x80000000 279 280 /* PLA_EEE_CR */ 281 #define EEE_RX_EN 0x0001 282 #define EEE_TX_EN 0x0002 283 284 /* PLA_BOOT_CTRL */ 285 #define AUTOLOAD_DONE 0x0002 286 287 /* USB_DEV_STAT */ 288 #define STAT_SPEED_MASK 0x0006 289 #define STAT_SPEED_HIGH 0x0000 290 #define STAT_SPEED_FULL 0x0002 291 292 /* USB_TX_AGG */ 293 #define TX_AGG_MAX_THRESHOLD 0x03 294 295 /* USB_RX_BUF_TH */ 296 #define RX_THR_SUPPER 0x0c350180 297 #define RX_THR_HIGH 0x7a120180 298 #define RX_THR_SLOW 0xffff0180 299 300 /* USB_TX_DMA */ 301 #define TEST_MODE_DISABLE 0x00000001 302 #define TX_SIZE_ADJUST1 0x00000100 303 304 /* USB_UPS_CTRL */ 305 #define POWER_CUT 0x0100 306 307 /* USB_PM_CTRL_STATUS */ 308 #define RESUME_INDICATE 0x0001 309 310 /* USB_USB_CTRL */ 311 #define RX_AGG_DISABLE 0x0010 312 313 /* USB_U2P3_CTRL */ 314 #define U2P3_ENABLE 0x0001 315 316 /* USB_POWER_CUT */ 317 #define PWR_EN 0x0001 318 #define PHASE2_EN 0x0008 319 320 /* USB_MISC_0 */ 321 #define PCUT_STATUS 0x0001 322 323 /* USB_RX_EARLY_AGG */ 324 #define EARLY_AGG_SUPPER 0x0e832981 325 #define EARLY_AGG_HIGH 0x0e837a12 326 #define EARLY_AGG_SLOW 0x0e83ffff 327 328 /* USB_WDT11_CTRL */ 329 #define TIMER11_EN 0x0001 330 331 /* USB_LPM_CTRL */ 332 #define LPM_TIMER_MASK 0x0c 333 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 334 #define LPM_TIMER_500US 0x0c /* 500 us */ 335 336 /* USB_AFE_CTRL2 */ 337 #define SEN_VAL_MASK 0xf800 338 #define SEN_VAL_NORMAL 0xa000 339 #define SEL_RXIDLE 0x0100 340 341 /* OCP_ALDPS_CONFIG */ 342 #define ENPWRSAVE 0x8000 343 #define ENPDNPS 0x0200 344 #define LINKENA 0x0100 345 #define DIS_SDSAVE 0x0010 346 347 /* OCP_PHY_STATUS */ 348 #define PHY_STAT_MASK 0x0007 349 #define PHY_STAT_LAN_ON 3 350 #define PHY_STAT_PWRDN 5 351 352 /* OCP_POWER_CFG */ 353 #define EEE_CLKDIV_EN 0x8000 354 #define EN_ALDPS 0x0004 355 #define EN_10M_PLLOFF 0x0001 356 357 /* OCP_EEE_CONFIG1 */ 358 #define RG_TXLPI_MSK_HFDUP 0x8000 359 #define RG_MATCLR_EN 0x4000 360 #define EEE_10_CAP 0x2000 361 #define EEE_NWAY_EN 0x1000 362 #define TX_QUIET_EN 0x0200 363 #define RX_QUIET_EN 0x0100 364 #define SDRISETIME 0x0010 /* bit 4 ~ 6 */ 365 #define RG_RXLPI_MSK_HFDUP 0x0008 366 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 367 368 /* OCP_EEE_CONFIG2 */ 369 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 370 #define RG_DACQUIET_EN 0x0400 371 #define RG_LDVQUIET_EN 0x0200 372 #define RG_CKRSEL 0x0020 373 #define RG_EEEPRG_EN 0x0010 374 375 /* OCP_EEE_CONFIG3 */ 376 #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */ 377 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 378 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 379 380 /* OCP_EEE_AR */ 381 /* bit[15:14] function */ 382 #define FUN_ADDR 0x0000 383 #define FUN_DATA 0x4000 384 /* bit[4:0] device addr */ 385 #define DEVICE_ADDR 0x0007 386 387 /* OCP_EEE_DATA */ 388 #define EEE_ADDR 0x003C 389 #define EEE_DATA 0x0002 390 391 /* OCP_EEE_CFG */ 392 #define CTAP_SHORT_EN 0x0040 393 #define EEE10_EN 0x0010 394 395 /* OCP_DOWN_SPEED */ 396 #define EN_10M_BGOFF 0x0080 397 398 /* OCP_EEE_CFG2 */ 399 #define MY1000_EEE 0x0004 400 #define MY100_EEE 0x0002 401 402 /* OCP_ADC_CFG */ 403 #define CKADSEL_L 0x0100 404 #define ADC_EN 0x0080 405 #define EN_EMI_L 0x0040 406 407 /* SRAM_LPF_CFG */ 408 #define LPF_AUTO_TUNE 0x8000 409 410 /* SRAM_10M_AMP1 */ 411 #define GDAC_IB_UPALL 0x0008 412 413 /* SRAM_10M_AMP2 */ 414 #define AMP_DN 0x0200 415 416 /* SRAM_IMPEDANCE */ 417 #define RX_DRIVING_MASK 0x6000 418 419 enum rtl_register_content { 420 _1000bps = 0x10, 421 _100bps = 0x08, 422 _10bps = 0x04, 423 LINK_STATUS = 0x02, 424 FULL_DUP = 0x01, 425 }; 426 427 #define RTL8152_MAX_TX 10 428 #define RTL8152_MAX_RX 10 429 #define INTBUFSIZE 2 430 #define CRC_SIZE 4 431 #define TX_ALIGN 4 432 #define RX_ALIGN 8 433 434 #define INTR_LINK 0x0004 435 436 #define RTL8152_REQT_READ 0xc0 437 #define RTL8152_REQT_WRITE 0x40 438 #define RTL8152_REQ_GET_REGS 0x05 439 #define RTL8152_REQ_SET_REGS 0x05 440 441 #define BYTE_EN_DWORD 0xff 442 #define BYTE_EN_WORD 0x33 443 #define BYTE_EN_BYTE 0x11 444 #define BYTE_EN_SIX_BYTES 0x3f 445 #define BYTE_EN_START_MASK 0x0f 446 #define BYTE_EN_END_MASK 0xf0 447 448 #define RTL8153_MAX_PACKET 9216 /* 9K */ 449 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN) 450 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) 451 #define RTL8153_RMS RTL8153_MAX_PACKET 452 #define RTL8152_TX_TIMEOUT (5 * HZ) 453 454 /* rtl8152 flags */ 455 enum rtl8152_flags { 456 RTL8152_UNPLUG = 0, 457 RTL8152_SET_RX_MODE, 458 WORK_ENABLE, 459 RTL8152_LINK_CHG, 460 SELECTIVE_SUSPEND, 461 PHY_RESET, 462 SCHEDULE_TASKLET, 463 }; 464 465 /* Define these values to match your device */ 466 #define VENDOR_ID_REALTEK 0x0bda 467 #define PRODUCT_ID_RTL8152 0x8152 468 #define PRODUCT_ID_RTL8153 0x8153 469 470 #define VENDOR_ID_SAMSUNG 0x04e8 471 #define PRODUCT_ID_SAMSUNG 0xa101 472 473 #define MCU_TYPE_PLA 0x0100 474 #define MCU_TYPE_USB 0x0000 475 476 #define REALTEK_USB_DEVICE(vend, prod) \ 477 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC) 478 479 struct tally_counter { 480 __le64 tx_packets; 481 __le64 rx_packets; 482 __le64 tx_errors; 483 __le32 rx_errors; 484 __le16 rx_missed; 485 __le16 align_errors; 486 __le32 tx_one_collision; 487 __le32 tx_multi_collision; 488 __le64 rx_unicast; 489 __le64 rx_broadcast; 490 __le32 rx_multicast; 491 __le16 tx_aborted; 492 __le16 tx_underun; 493 }; 494 495 struct rx_desc { 496 __le32 opts1; 497 #define RX_LEN_MASK 0x7fff 498 499 __le32 opts2; 500 #define RD_UDP_CS (1 << 23) 501 #define RD_TCP_CS (1 << 22) 502 #define RD_IPV6_CS (1 << 20) 503 #define RD_IPV4_CS (1 << 19) 504 505 __le32 opts3; 506 #define IPF (1 << 23) /* IP checksum fail */ 507 #define UDPF (1 << 22) /* UDP checksum fail */ 508 #define TCPF (1 << 21) /* TCP checksum fail */ 509 510 __le32 opts4; 511 __le32 opts5; 512 __le32 opts6; 513 }; 514 515 struct tx_desc { 516 __le32 opts1; 517 #define TX_FS (1 << 31) /* First segment of a packet */ 518 #define TX_LS (1 << 30) /* Final segment of a packet */ 519 #define GTSENDV4 (1 << 28) 520 #define GTSENDV6 (1 << 27) 521 #define GTTCPHO_SHIFT 18 522 #define GTTCPHO_MAX 0x7fU 523 #define TX_LEN_MAX 0x3ffffU 524 525 __le32 opts2; 526 #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */ 527 #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */ 528 #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */ 529 #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */ 530 #define MSS_SHIFT 17 531 #define MSS_MAX 0x7ffU 532 #define TCPHO_SHIFT 17 533 #define TCPHO_MAX 0x7ffU 534 }; 535 536 struct r8152; 537 538 struct rx_agg { 539 struct list_head list; 540 struct urb *urb; 541 struct r8152 *context; 542 void *buffer; 543 void *head; 544 }; 545 546 struct tx_agg { 547 struct list_head list; 548 struct urb *urb; 549 struct r8152 *context; 550 void *buffer; 551 void *head; 552 u32 skb_num; 553 u32 skb_len; 554 }; 555 556 struct r8152 { 557 unsigned long flags; 558 struct usb_device *udev; 559 struct tasklet_struct tl; 560 struct usb_interface *intf; 561 struct net_device *netdev; 562 struct urb *intr_urb; 563 struct tx_agg tx_info[RTL8152_MAX_TX]; 564 struct rx_agg rx_info[RTL8152_MAX_RX]; 565 struct list_head rx_done, tx_free; 566 struct sk_buff_head tx_queue; 567 spinlock_t rx_lock, tx_lock; 568 struct delayed_work schedule; 569 struct mii_if_info mii; 570 571 struct rtl_ops { 572 void (*init)(struct r8152 *); 573 int (*enable)(struct r8152 *); 574 void (*disable)(struct r8152 *); 575 void (*up)(struct r8152 *); 576 void (*down)(struct r8152 *); 577 void (*unload)(struct r8152 *); 578 } rtl_ops; 579 580 int intr_interval; 581 u32 saved_wolopts; 582 u32 msg_enable; 583 u32 tx_qlen; 584 u16 ocp_base; 585 u8 *intr_buff; 586 u8 version; 587 u8 speed; 588 }; 589 590 enum rtl_version { 591 RTL_VER_UNKNOWN = 0, 592 RTL_VER_01, 593 RTL_VER_02, 594 RTL_VER_03, 595 RTL_VER_04, 596 RTL_VER_05, 597 RTL_VER_MAX 598 }; 599 600 enum tx_csum_stat { 601 TX_CSUM_SUCCESS = 0, 602 TX_CSUM_TSO, 603 TX_CSUM_NONE 604 }; 605 606 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 607 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 608 */ 609 static const int multicast_filter_limit = 32; 610 static unsigned int rx_buf_sz = 16384; 611 612 #define RTL_LIMITED_TSO_SIZE (rx_buf_sz - sizeof(struct tx_desc) - \ 613 VLAN_ETH_HLEN - VLAN_HLEN) 614 615 static 616 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 617 { 618 int ret; 619 void *tmp; 620 621 tmp = kmalloc(size, GFP_KERNEL); 622 if (!tmp) 623 return -ENOMEM; 624 625 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 626 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 627 value, index, tmp, size, 500); 628 629 memcpy(data, tmp, size); 630 kfree(tmp); 631 632 return ret; 633 } 634 635 static 636 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 637 { 638 int ret; 639 void *tmp; 640 641 tmp = kmemdup(data, size, GFP_KERNEL); 642 if (!tmp) 643 return -ENOMEM; 644 645 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 646 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 647 value, index, tmp, size, 500); 648 649 kfree(tmp); 650 651 return ret; 652 } 653 654 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 655 void *data, u16 type) 656 { 657 u16 limit = 64; 658 int ret = 0; 659 660 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 661 return -ENODEV; 662 663 /* both size and indix must be 4 bytes align */ 664 if ((size & 3) || !size || (index & 3) || !data) 665 return -EPERM; 666 667 if ((u32)index + (u32)size > 0xffff) 668 return -EPERM; 669 670 while (size) { 671 if (size > limit) { 672 ret = get_registers(tp, index, type, limit, data); 673 if (ret < 0) 674 break; 675 676 index += limit; 677 data += limit; 678 size -= limit; 679 } else { 680 ret = get_registers(tp, index, type, size, data); 681 if (ret < 0) 682 break; 683 684 index += size; 685 data += size; 686 size = 0; 687 break; 688 } 689 } 690 691 return ret; 692 } 693 694 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 695 u16 size, void *data, u16 type) 696 { 697 int ret; 698 u16 byteen_start, byteen_end, byen; 699 u16 limit = 512; 700 701 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 702 return -ENODEV; 703 704 /* both size and indix must be 4 bytes align */ 705 if ((size & 3) || !size || (index & 3) || !data) 706 return -EPERM; 707 708 if ((u32)index + (u32)size > 0xffff) 709 return -EPERM; 710 711 byteen_start = byteen & BYTE_EN_START_MASK; 712 byteen_end = byteen & BYTE_EN_END_MASK; 713 714 byen = byteen_start | (byteen_start << 4); 715 ret = set_registers(tp, index, type | byen, 4, data); 716 if (ret < 0) 717 goto error1; 718 719 index += 4; 720 data += 4; 721 size -= 4; 722 723 if (size) { 724 size -= 4; 725 726 while (size) { 727 if (size > limit) { 728 ret = set_registers(tp, index, 729 type | BYTE_EN_DWORD, 730 limit, data); 731 if (ret < 0) 732 goto error1; 733 734 index += limit; 735 data += limit; 736 size -= limit; 737 } else { 738 ret = set_registers(tp, index, 739 type | BYTE_EN_DWORD, 740 size, data); 741 if (ret < 0) 742 goto error1; 743 744 index += size; 745 data += size; 746 size = 0; 747 break; 748 } 749 } 750 751 byen = byteen_end | (byteen_end >> 4); 752 ret = set_registers(tp, index, type | byen, 4, data); 753 if (ret < 0) 754 goto error1; 755 } 756 757 error1: 758 return ret; 759 } 760 761 static inline 762 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 763 { 764 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 765 } 766 767 static inline 768 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 769 { 770 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 771 } 772 773 static inline 774 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 775 { 776 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); 777 } 778 779 static inline 780 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 781 { 782 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 783 } 784 785 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 786 { 787 __le32 data; 788 789 generic_ocp_read(tp, index, sizeof(data), &data, type); 790 791 return __le32_to_cpu(data); 792 } 793 794 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 795 { 796 __le32 tmp = __cpu_to_le32(data); 797 798 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 799 } 800 801 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 802 { 803 u32 data; 804 __le32 tmp; 805 u8 shift = index & 2; 806 807 index &= ~3; 808 809 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 810 811 data = __le32_to_cpu(tmp); 812 data >>= (shift * 8); 813 data &= 0xffff; 814 815 return (u16)data; 816 } 817 818 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 819 { 820 u32 mask = 0xffff; 821 __le32 tmp; 822 u16 byen = BYTE_EN_WORD; 823 u8 shift = index & 2; 824 825 data &= mask; 826 827 if (index & 2) { 828 byen <<= shift; 829 mask <<= (shift * 8); 830 data <<= (shift * 8); 831 index &= ~3; 832 } 833 834 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 835 836 data |= __le32_to_cpu(tmp) & ~mask; 837 tmp = __cpu_to_le32(data); 838 839 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 840 } 841 842 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 843 { 844 u32 data; 845 __le32 tmp; 846 u8 shift = index & 3; 847 848 index &= ~3; 849 850 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 851 852 data = __le32_to_cpu(tmp); 853 data >>= (shift * 8); 854 data &= 0xff; 855 856 return (u8)data; 857 } 858 859 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 860 { 861 u32 mask = 0xff; 862 __le32 tmp; 863 u16 byen = BYTE_EN_BYTE; 864 u8 shift = index & 3; 865 866 data &= mask; 867 868 if (index & 3) { 869 byen <<= shift; 870 mask <<= (shift * 8); 871 data <<= (shift * 8); 872 index &= ~3; 873 } 874 875 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 876 877 data |= __le32_to_cpu(tmp) & ~mask; 878 tmp = __cpu_to_le32(data); 879 880 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 881 } 882 883 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 884 { 885 u16 ocp_base, ocp_index; 886 887 ocp_base = addr & 0xf000; 888 if (ocp_base != tp->ocp_base) { 889 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 890 tp->ocp_base = ocp_base; 891 } 892 893 ocp_index = (addr & 0x0fff) | 0xb000; 894 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 895 } 896 897 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 898 { 899 u16 ocp_base, ocp_index; 900 901 ocp_base = addr & 0xf000; 902 if (ocp_base != tp->ocp_base) { 903 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 904 tp->ocp_base = ocp_base; 905 } 906 907 ocp_index = (addr & 0x0fff) | 0xb000; 908 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 909 } 910 911 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 912 { 913 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 914 } 915 916 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 917 { 918 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 919 } 920 921 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 922 { 923 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 924 ocp_reg_write(tp, OCP_SRAM_DATA, data); 925 } 926 927 static u16 sram_read(struct r8152 *tp, u16 addr) 928 { 929 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 930 return ocp_reg_read(tp, OCP_SRAM_DATA); 931 } 932 933 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 934 { 935 struct r8152 *tp = netdev_priv(netdev); 936 int ret; 937 938 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 939 return -ENODEV; 940 941 if (phy_id != R8152_PHY_ID) 942 return -EINVAL; 943 944 ret = usb_autopm_get_interface(tp->intf); 945 if (ret < 0) 946 goto out; 947 948 ret = r8152_mdio_read(tp, reg); 949 950 usb_autopm_put_interface(tp->intf); 951 952 out: 953 return ret; 954 } 955 956 static 957 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 958 { 959 struct r8152 *tp = netdev_priv(netdev); 960 961 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 962 return; 963 964 if (phy_id != R8152_PHY_ID) 965 return; 966 967 if (usb_autopm_get_interface(tp->intf) < 0) 968 return; 969 970 r8152_mdio_write(tp, reg, val); 971 972 usb_autopm_put_interface(tp->intf); 973 } 974 975 static 976 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 977 978 static inline void set_ethernet_addr(struct r8152 *tp) 979 { 980 struct net_device *dev = tp->netdev; 981 int ret; 982 u8 node_id[8] = {0}; 983 984 if (tp->version == RTL_VER_01) 985 ret = pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id); 986 else 987 ret = pla_ocp_read(tp, PLA_BACKUP, sizeof(node_id), node_id); 988 989 if (ret < 0) { 990 netif_notice(tp, probe, dev, "inet addr fail\n"); 991 } else { 992 if (tp->version != RTL_VER_01) { 993 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, 994 CRWECR_CONFIG); 995 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 996 sizeof(node_id), node_id); 997 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, 998 CRWECR_NORAML); 999 } 1000 1001 memcpy(dev->dev_addr, node_id, dev->addr_len); 1002 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 1003 } 1004 } 1005 1006 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1007 { 1008 struct r8152 *tp = netdev_priv(netdev); 1009 struct sockaddr *addr = p; 1010 1011 if (!is_valid_ether_addr(addr->sa_data)) 1012 return -EADDRNOTAVAIL; 1013 1014 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1015 1016 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1017 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1018 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1019 1020 return 0; 1021 } 1022 1023 static void read_bulk_callback(struct urb *urb) 1024 { 1025 struct net_device *netdev; 1026 int status = urb->status; 1027 struct rx_agg *agg; 1028 struct r8152 *tp; 1029 int result; 1030 1031 agg = urb->context; 1032 if (!agg) 1033 return; 1034 1035 tp = agg->context; 1036 if (!tp) 1037 return; 1038 1039 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1040 return; 1041 1042 if (!test_bit(WORK_ENABLE, &tp->flags)) 1043 return; 1044 1045 netdev = tp->netdev; 1046 1047 /* When link down, the driver would cancel all bulks. */ 1048 /* This avoid the re-submitting bulk */ 1049 if (!netif_carrier_ok(netdev)) 1050 return; 1051 1052 usb_mark_last_busy(tp->udev); 1053 1054 switch (status) { 1055 case 0: 1056 if (urb->actual_length < ETH_ZLEN) 1057 break; 1058 1059 spin_lock(&tp->rx_lock); 1060 list_add_tail(&agg->list, &tp->rx_done); 1061 spin_unlock(&tp->rx_lock); 1062 tasklet_schedule(&tp->tl); 1063 return; 1064 case -ESHUTDOWN: 1065 set_bit(RTL8152_UNPLUG, &tp->flags); 1066 netif_device_detach(tp->netdev); 1067 return; 1068 case -ENOENT: 1069 return; /* the urb is in unlink state */ 1070 case -ETIME: 1071 if (net_ratelimit()) 1072 netdev_warn(netdev, "maybe reset is needed?\n"); 1073 break; 1074 default: 1075 if (net_ratelimit()) 1076 netdev_warn(netdev, "Rx status %d\n", status); 1077 break; 1078 } 1079 1080 result = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1081 if (result == -ENODEV) { 1082 netif_device_detach(tp->netdev); 1083 } else if (result) { 1084 spin_lock(&tp->rx_lock); 1085 list_add_tail(&agg->list, &tp->rx_done); 1086 spin_unlock(&tp->rx_lock); 1087 tasklet_schedule(&tp->tl); 1088 } 1089 } 1090 1091 static void write_bulk_callback(struct urb *urb) 1092 { 1093 struct net_device_stats *stats; 1094 struct net_device *netdev; 1095 struct tx_agg *agg; 1096 struct r8152 *tp; 1097 int status = urb->status; 1098 1099 agg = urb->context; 1100 if (!agg) 1101 return; 1102 1103 tp = agg->context; 1104 if (!tp) 1105 return; 1106 1107 netdev = tp->netdev; 1108 stats = &netdev->stats; 1109 if (status) { 1110 if (net_ratelimit()) 1111 netdev_warn(netdev, "Tx status %d\n", status); 1112 stats->tx_errors += agg->skb_num; 1113 } else { 1114 stats->tx_packets += agg->skb_num; 1115 stats->tx_bytes += agg->skb_len; 1116 } 1117 1118 spin_lock(&tp->tx_lock); 1119 list_add_tail(&agg->list, &tp->tx_free); 1120 spin_unlock(&tp->tx_lock); 1121 1122 usb_autopm_put_interface_async(tp->intf); 1123 1124 if (!netif_carrier_ok(netdev)) 1125 return; 1126 1127 if (!test_bit(WORK_ENABLE, &tp->flags)) 1128 return; 1129 1130 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1131 return; 1132 1133 if (!skb_queue_empty(&tp->tx_queue)) 1134 tasklet_schedule(&tp->tl); 1135 } 1136 1137 static void intr_callback(struct urb *urb) 1138 { 1139 struct r8152 *tp; 1140 __le16 *d; 1141 int status = urb->status; 1142 int res; 1143 1144 tp = urb->context; 1145 if (!tp) 1146 return; 1147 1148 if (!test_bit(WORK_ENABLE, &tp->flags)) 1149 return; 1150 1151 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1152 return; 1153 1154 switch (status) { 1155 case 0: /* success */ 1156 break; 1157 case -ECONNRESET: /* unlink */ 1158 case -ESHUTDOWN: 1159 netif_device_detach(tp->netdev); 1160 case -ENOENT: 1161 return; 1162 case -EOVERFLOW: 1163 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1164 goto resubmit; 1165 /* -EPIPE: should clear the halt */ 1166 default: 1167 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1168 goto resubmit; 1169 } 1170 1171 d = urb->transfer_buffer; 1172 if (INTR_LINK & __le16_to_cpu(d[0])) { 1173 if (!(tp->speed & LINK_STATUS)) { 1174 set_bit(RTL8152_LINK_CHG, &tp->flags); 1175 schedule_delayed_work(&tp->schedule, 0); 1176 } 1177 } else { 1178 if (tp->speed & LINK_STATUS) { 1179 set_bit(RTL8152_LINK_CHG, &tp->flags); 1180 schedule_delayed_work(&tp->schedule, 0); 1181 } 1182 } 1183 1184 resubmit: 1185 res = usb_submit_urb(urb, GFP_ATOMIC); 1186 if (res == -ENODEV) 1187 netif_device_detach(tp->netdev); 1188 else if (res) 1189 netif_err(tp, intr, tp->netdev, 1190 "can't resubmit intr, status %d\n", res); 1191 } 1192 1193 static inline void *rx_agg_align(void *data) 1194 { 1195 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1196 } 1197 1198 static inline void *tx_agg_align(void *data) 1199 { 1200 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1201 } 1202 1203 static void free_all_mem(struct r8152 *tp) 1204 { 1205 int i; 1206 1207 for (i = 0; i < RTL8152_MAX_RX; i++) { 1208 usb_free_urb(tp->rx_info[i].urb); 1209 tp->rx_info[i].urb = NULL; 1210 1211 kfree(tp->rx_info[i].buffer); 1212 tp->rx_info[i].buffer = NULL; 1213 tp->rx_info[i].head = NULL; 1214 } 1215 1216 for (i = 0; i < RTL8152_MAX_TX; i++) { 1217 usb_free_urb(tp->tx_info[i].urb); 1218 tp->tx_info[i].urb = NULL; 1219 1220 kfree(tp->tx_info[i].buffer); 1221 tp->tx_info[i].buffer = NULL; 1222 tp->tx_info[i].head = NULL; 1223 } 1224 1225 usb_free_urb(tp->intr_urb); 1226 tp->intr_urb = NULL; 1227 1228 kfree(tp->intr_buff); 1229 tp->intr_buff = NULL; 1230 } 1231 1232 static int alloc_all_mem(struct r8152 *tp) 1233 { 1234 struct net_device *netdev = tp->netdev; 1235 struct usb_interface *intf = tp->intf; 1236 struct usb_host_interface *alt = intf->cur_altsetting; 1237 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1238 struct urb *urb; 1239 int node, i; 1240 u8 *buf; 1241 1242 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1243 1244 spin_lock_init(&tp->rx_lock); 1245 spin_lock_init(&tp->tx_lock); 1246 INIT_LIST_HEAD(&tp->rx_done); 1247 INIT_LIST_HEAD(&tp->tx_free); 1248 skb_queue_head_init(&tp->tx_queue); 1249 1250 for (i = 0; i < RTL8152_MAX_RX; i++) { 1251 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); 1252 if (!buf) 1253 goto err1; 1254 1255 if (buf != rx_agg_align(buf)) { 1256 kfree(buf); 1257 buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL, 1258 node); 1259 if (!buf) 1260 goto err1; 1261 } 1262 1263 urb = usb_alloc_urb(0, GFP_KERNEL); 1264 if (!urb) { 1265 kfree(buf); 1266 goto err1; 1267 } 1268 1269 INIT_LIST_HEAD(&tp->rx_info[i].list); 1270 tp->rx_info[i].context = tp; 1271 tp->rx_info[i].urb = urb; 1272 tp->rx_info[i].buffer = buf; 1273 tp->rx_info[i].head = rx_agg_align(buf); 1274 } 1275 1276 for (i = 0; i < RTL8152_MAX_TX; i++) { 1277 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); 1278 if (!buf) 1279 goto err1; 1280 1281 if (buf != tx_agg_align(buf)) { 1282 kfree(buf); 1283 buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL, 1284 node); 1285 if (!buf) 1286 goto err1; 1287 } 1288 1289 urb = usb_alloc_urb(0, GFP_KERNEL); 1290 if (!urb) { 1291 kfree(buf); 1292 goto err1; 1293 } 1294 1295 INIT_LIST_HEAD(&tp->tx_info[i].list); 1296 tp->tx_info[i].context = tp; 1297 tp->tx_info[i].urb = urb; 1298 tp->tx_info[i].buffer = buf; 1299 tp->tx_info[i].head = tx_agg_align(buf); 1300 1301 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1302 } 1303 1304 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1305 if (!tp->intr_urb) 1306 goto err1; 1307 1308 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1309 if (!tp->intr_buff) 1310 goto err1; 1311 1312 tp->intr_interval = (int)ep_intr->desc.bInterval; 1313 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1314 tp->intr_buff, INTBUFSIZE, intr_callback, 1315 tp, tp->intr_interval); 1316 1317 return 0; 1318 1319 err1: 1320 free_all_mem(tp); 1321 return -ENOMEM; 1322 } 1323 1324 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1325 { 1326 struct tx_agg *agg = NULL; 1327 unsigned long flags; 1328 1329 if (list_empty(&tp->tx_free)) 1330 return NULL; 1331 1332 spin_lock_irqsave(&tp->tx_lock, flags); 1333 if (!list_empty(&tp->tx_free)) { 1334 struct list_head *cursor; 1335 1336 cursor = tp->tx_free.next; 1337 list_del_init(cursor); 1338 agg = list_entry(cursor, struct tx_agg, list); 1339 } 1340 spin_unlock_irqrestore(&tp->tx_lock, flags); 1341 1342 return agg; 1343 } 1344 1345 static inline __be16 get_protocol(struct sk_buff *skb) 1346 { 1347 __be16 protocol; 1348 1349 if (skb->protocol == htons(ETH_P_8021Q)) 1350 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; 1351 else 1352 protocol = skb->protocol; 1353 1354 return protocol; 1355 } 1356 1357 /* 1358 * r8152_csum_workaround() 1359 * The hw limites the value the transport offset. When the offset is out of the 1360 * range, calculate the checksum by sw. 1361 */ 1362 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1363 struct sk_buff_head *list) 1364 { 1365 if (skb_shinfo(skb)->gso_size) { 1366 netdev_features_t features = tp->netdev->features; 1367 struct sk_buff_head seg_list; 1368 struct sk_buff *segs, *nskb; 1369 1370 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 1371 segs = skb_gso_segment(skb, features); 1372 if (IS_ERR(segs) || !segs) 1373 goto drop; 1374 1375 __skb_queue_head_init(&seg_list); 1376 1377 do { 1378 nskb = segs; 1379 segs = segs->next; 1380 nskb->next = NULL; 1381 __skb_queue_tail(&seg_list, nskb); 1382 } while (segs); 1383 1384 skb_queue_splice(&seg_list, list); 1385 dev_kfree_skb(skb); 1386 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1387 if (skb_checksum_help(skb) < 0) 1388 goto drop; 1389 1390 __skb_queue_head(list, skb); 1391 } else { 1392 struct net_device_stats *stats; 1393 1394 drop: 1395 stats = &tp->netdev->stats; 1396 stats->tx_dropped++; 1397 dev_kfree_skb(skb); 1398 } 1399 } 1400 1401 /* 1402 * msdn_giant_send_check() 1403 * According to the document of microsoft, the TCP Pseudo Header excludes the 1404 * packet length for IPv6 TCP large packets. 1405 */ 1406 static int msdn_giant_send_check(struct sk_buff *skb) 1407 { 1408 const struct ipv6hdr *ipv6h; 1409 struct tcphdr *th; 1410 int ret; 1411 1412 ret = skb_cow_head(skb, 0); 1413 if (ret) 1414 return ret; 1415 1416 ipv6h = ipv6_hdr(skb); 1417 th = tcp_hdr(skb); 1418 1419 th->check = 0; 1420 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1421 1422 return ret; 1423 } 1424 1425 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1426 struct sk_buff *skb, u32 len, u32 transport_offset) 1427 { 1428 u32 mss = skb_shinfo(skb)->gso_size; 1429 u32 opts1, opts2 = 0; 1430 int ret = TX_CSUM_SUCCESS; 1431 1432 WARN_ON_ONCE(len > TX_LEN_MAX); 1433 1434 opts1 = len | TX_FS | TX_LS; 1435 1436 if (mss) { 1437 if (transport_offset > GTTCPHO_MAX) { 1438 netif_warn(tp, tx_err, tp->netdev, 1439 "Invalid transport offset 0x%x for TSO\n", 1440 transport_offset); 1441 ret = TX_CSUM_TSO; 1442 goto unavailable; 1443 } 1444 1445 switch (get_protocol(skb)) { 1446 case htons(ETH_P_IP): 1447 opts1 |= GTSENDV4; 1448 break; 1449 1450 case htons(ETH_P_IPV6): 1451 if (msdn_giant_send_check(skb)) { 1452 ret = TX_CSUM_TSO; 1453 goto unavailable; 1454 } 1455 opts1 |= GTSENDV6; 1456 break; 1457 1458 default: 1459 WARN_ON_ONCE(1); 1460 break; 1461 } 1462 1463 opts1 |= transport_offset << GTTCPHO_SHIFT; 1464 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1465 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1466 u8 ip_protocol; 1467 1468 if (transport_offset > TCPHO_MAX) { 1469 netif_warn(tp, tx_err, tp->netdev, 1470 "Invalid transport offset 0x%x\n", 1471 transport_offset); 1472 ret = TX_CSUM_NONE; 1473 goto unavailable; 1474 } 1475 1476 switch (get_protocol(skb)) { 1477 case htons(ETH_P_IP): 1478 opts2 |= IPV4_CS; 1479 ip_protocol = ip_hdr(skb)->protocol; 1480 break; 1481 1482 case htons(ETH_P_IPV6): 1483 opts2 |= IPV6_CS; 1484 ip_protocol = ipv6_hdr(skb)->nexthdr; 1485 break; 1486 1487 default: 1488 ip_protocol = IPPROTO_RAW; 1489 break; 1490 } 1491 1492 if (ip_protocol == IPPROTO_TCP) 1493 opts2 |= TCP_CS; 1494 else if (ip_protocol == IPPROTO_UDP) 1495 opts2 |= UDP_CS; 1496 else 1497 WARN_ON_ONCE(1); 1498 1499 opts2 |= transport_offset << TCPHO_SHIFT; 1500 } 1501 1502 desc->opts2 = cpu_to_le32(opts2); 1503 desc->opts1 = cpu_to_le32(opts1); 1504 1505 unavailable: 1506 return ret; 1507 } 1508 1509 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1510 { 1511 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1512 int remain, ret; 1513 u8 *tx_data; 1514 1515 __skb_queue_head_init(&skb_head); 1516 spin_lock(&tx_queue->lock); 1517 skb_queue_splice_init(tx_queue, &skb_head); 1518 spin_unlock(&tx_queue->lock); 1519 1520 tx_data = agg->head; 1521 agg->skb_num = agg->skb_len = 0; 1522 remain = rx_buf_sz; 1523 1524 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1525 struct tx_desc *tx_desc; 1526 struct sk_buff *skb; 1527 unsigned int len; 1528 u32 offset; 1529 1530 skb = __skb_dequeue(&skb_head); 1531 if (!skb) 1532 break; 1533 1534 len = skb->len + sizeof(*tx_desc); 1535 1536 if (len > remain) { 1537 __skb_queue_head(&skb_head, skb); 1538 break; 1539 } 1540 1541 tx_data = tx_agg_align(tx_data); 1542 tx_desc = (struct tx_desc *)tx_data; 1543 1544 offset = (u32)skb_transport_offset(skb); 1545 1546 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1547 r8152_csum_workaround(tp, skb, &skb_head); 1548 continue; 1549 } 1550 1551 tx_data += sizeof(*tx_desc); 1552 1553 len = skb->len; 1554 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1555 struct net_device_stats *stats = &tp->netdev->stats; 1556 1557 stats->tx_dropped++; 1558 dev_kfree_skb_any(skb); 1559 tx_data -= sizeof(*tx_desc); 1560 continue; 1561 } 1562 1563 tx_data += len; 1564 agg->skb_len += len; 1565 agg->skb_num++; 1566 1567 dev_kfree_skb_any(skb); 1568 1569 remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1570 } 1571 1572 if (!skb_queue_empty(&skb_head)) { 1573 spin_lock(&tx_queue->lock); 1574 skb_queue_splice(&skb_head, tx_queue); 1575 spin_unlock(&tx_queue->lock); 1576 } 1577 1578 netif_tx_lock(tp->netdev); 1579 1580 if (netif_queue_stopped(tp->netdev) && 1581 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1582 netif_wake_queue(tp->netdev); 1583 1584 netif_tx_unlock(tp->netdev); 1585 1586 ret = usb_autopm_get_interface_async(tp->intf); 1587 if (ret < 0) 1588 goto out_tx_fill; 1589 1590 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1591 agg->head, (int)(tx_data - (u8 *)agg->head), 1592 (usb_complete_t)write_bulk_callback, agg); 1593 1594 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1595 if (ret < 0) 1596 usb_autopm_put_interface_async(tp->intf); 1597 1598 out_tx_fill: 1599 return ret; 1600 } 1601 1602 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1603 { 1604 u8 checksum = CHECKSUM_NONE; 1605 u32 opts2, opts3; 1606 1607 if (tp->version == RTL_VER_01) 1608 goto return_result; 1609 1610 opts2 = le32_to_cpu(rx_desc->opts2); 1611 opts3 = le32_to_cpu(rx_desc->opts3); 1612 1613 if (opts2 & RD_IPV4_CS) { 1614 if (opts3 & IPF) 1615 checksum = CHECKSUM_NONE; 1616 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) 1617 checksum = CHECKSUM_NONE; 1618 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) 1619 checksum = CHECKSUM_NONE; 1620 else 1621 checksum = CHECKSUM_UNNECESSARY; 1622 } else if (RD_IPV6_CS) { 1623 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1624 checksum = CHECKSUM_UNNECESSARY; 1625 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1626 checksum = CHECKSUM_UNNECESSARY; 1627 } 1628 1629 return_result: 1630 return checksum; 1631 } 1632 1633 static void rx_bottom(struct r8152 *tp) 1634 { 1635 unsigned long flags; 1636 struct list_head *cursor, *next, rx_queue; 1637 1638 if (list_empty(&tp->rx_done)) 1639 return; 1640 1641 INIT_LIST_HEAD(&rx_queue); 1642 spin_lock_irqsave(&tp->rx_lock, flags); 1643 list_splice_init(&tp->rx_done, &rx_queue); 1644 spin_unlock_irqrestore(&tp->rx_lock, flags); 1645 1646 list_for_each_safe(cursor, next, &rx_queue) { 1647 struct rx_desc *rx_desc; 1648 struct rx_agg *agg; 1649 int len_used = 0; 1650 struct urb *urb; 1651 u8 *rx_data; 1652 int ret; 1653 1654 list_del_init(cursor); 1655 1656 agg = list_entry(cursor, struct rx_agg, list); 1657 urb = agg->urb; 1658 if (urb->actual_length < ETH_ZLEN) 1659 goto submit; 1660 1661 rx_desc = agg->head; 1662 rx_data = agg->head; 1663 len_used += sizeof(struct rx_desc); 1664 1665 while (urb->actual_length > len_used) { 1666 struct net_device *netdev = tp->netdev; 1667 struct net_device_stats *stats = &netdev->stats; 1668 unsigned int pkt_len; 1669 struct sk_buff *skb; 1670 1671 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1672 if (pkt_len < ETH_ZLEN) 1673 break; 1674 1675 len_used += pkt_len; 1676 if (urb->actual_length < len_used) 1677 break; 1678 1679 pkt_len -= CRC_SIZE; 1680 rx_data += sizeof(struct rx_desc); 1681 1682 skb = netdev_alloc_skb_ip_align(netdev, pkt_len); 1683 if (!skb) { 1684 stats->rx_dropped++; 1685 goto find_next_rx; 1686 } 1687 1688 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 1689 memcpy(skb->data, rx_data, pkt_len); 1690 skb_put(skb, pkt_len); 1691 skb->protocol = eth_type_trans(skb, netdev); 1692 netif_receive_skb(skb); 1693 stats->rx_packets++; 1694 stats->rx_bytes += pkt_len; 1695 1696 find_next_rx: 1697 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); 1698 rx_desc = (struct rx_desc *)rx_data; 1699 len_used = (int)(rx_data - (u8 *)agg->head); 1700 len_used += sizeof(struct rx_desc); 1701 } 1702 1703 submit: 1704 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1705 if (ret && ret != -ENODEV) { 1706 spin_lock_irqsave(&tp->rx_lock, flags); 1707 list_add_tail(&agg->list, &tp->rx_done); 1708 spin_unlock_irqrestore(&tp->rx_lock, flags); 1709 tasklet_schedule(&tp->tl); 1710 } 1711 } 1712 } 1713 1714 static void tx_bottom(struct r8152 *tp) 1715 { 1716 int res; 1717 1718 do { 1719 struct tx_agg *agg; 1720 1721 if (skb_queue_empty(&tp->tx_queue)) 1722 break; 1723 1724 agg = r8152_get_tx_agg(tp); 1725 if (!agg) 1726 break; 1727 1728 res = r8152_tx_agg_fill(tp, agg); 1729 if (res) { 1730 struct net_device *netdev = tp->netdev; 1731 1732 if (res == -ENODEV) { 1733 netif_device_detach(netdev); 1734 } else { 1735 struct net_device_stats *stats = &netdev->stats; 1736 unsigned long flags; 1737 1738 netif_warn(tp, tx_err, netdev, 1739 "failed tx_urb %d\n", res); 1740 stats->tx_dropped += agg->skb_num; 1741 1742 spin_lock_irqsave(&tp->tx_lock, flags); 1743 list_add_tail(&agg->list, &tp->tx_free); 1744 spin_unlock_irqrestore(&tp->tx_lock, flags); 1745 } 1746 } 1747 } while (res == 0); 1748 } 1749 1750 static void bottom_half(unsigned long data) 1751 { 1752 struct r8152 *tp; 1753 1754 tp = (struct r8152 *)data; 1755 1756 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1757 return; 1758 1759 if (!test_bit(WORK_ENABLE, &tp->flags)) 1760 return; 1761 1762 /* When link down, the driver would cancel all bulks. */ 1763 /* This avoid the re-submitting bulk */ 1764 if (!netif_carrier_ok(tp->netdev)) 1765 return; 1766 1767 rx_bottom(tp); 1768 tx_bottom(tp); 1769 } 1770 1771 static 1772 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 1773 { 1774 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 1775 agg->head, rx_buf_sz, 1776 (usb_complete_t)read_bulk_callback, agg); 1777 1778 return usb_submit_urb(agg->urb, mem_flags); 1779 } 1780 1781 static void rtl_drop_queued_tx(struct r8152 *tp) 1782 { 1783 struct net_device_stats *stats = &tp->netdev->stats; 1784 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1785 struct sk_buff *skb; 1786 1787 if (skb_queue_empty(tx_queue)) 1788 return; 1789 1790 __skb_queue_head_init(&skb_head); 1791 spin_lock_bh(&tx_queue->lock); 1792 skb_queue_splice_init(tx_queue, &skb_head); 1793 spin_unlock_bh(&tx_queue->lock); 1794 1795 while ((skb = __skb_dequeue(&skb_head))) { 1796 dev_kfree_skb(skb); 1797 stats->tx_dropped++; 1798 } 1799 } 1800 1801 static void rtl8152_tx_timeout(struct net_device *netdev) 1802 { 1803 struct r8152 *tp = netdev_priv(netdev); 1804 int i; 1805 1806 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 1807 for (i = 0; i < RTL8152_MAX_TX; i++) 1808 usb_unlink_urb(tp->tx_info[i].urb); 1809 } 1810 1811 static void rtl8152_set_rx_mode(struct net_device *netdev) 1812 { 1813 struct r8152 *tp = netdev_priv(netdev); 1814 1815 if (tp->speed & LINK_STATUS) { 1816 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 1817 schedule_delayed_work(&tp->schedule, 0); 1818 } 1819 } 1820 1821 static void _rtl8152_set_rx_mode(struct net_device *netdev) 1822 { 1823 struct r8152 *tp = netdev_priv(netdev); 1824 u32 mc_filter[2]; /* Multicast hash filter */ 1825 __le32 tmp[2]; 1826 u32 ocp_data; 1827 1828 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 1829 netif_stop_queue(netdev); 1830 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 1831 ocp_data &= ~RCR_ACPT_ALL; 1832 ocp_data |= RCR_AB | RCR_APM; 1833 1834 if (netdev->flags & IFF_PROMISC) { 1835 /* Unconditionally log net taps. */ 1836 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 1837 ocp_data |= RCR_AM | RCR_AAP; 1838 mc_filter[1] = mc_filter[0] = 0xffffffff; 1839 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 1840 (netdev->flags & IFF_ALLMULTI)) { 1841 /* Too many to filter perfectly -- accept all multicasts. */ 1842 ocp_data |= RCR_AM; 1843 mc_filter[1] = mc_filter[0] = 0xffffffff; 1844 } else { 1845 struct netdev_hw_addr *ha; 1846 1847 mc_filter[1] = mc_filter[0] = 0; 1848 netdev_for_each_mc_addr(ha, netdev) { 1849 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 1850 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 1851 ocp_data |= RCR_AM; 1852 } 1853 } 1854 1855 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 1856 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 1857 1858 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 1859 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 1860 netif_wake_queue(netdev); 1861 } 1862 1863 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 1864 struct net_device *netdev) 1865 { 1866 struct r8152 *tp = netdev_priv(netdev); 1867 1868 skb_tx_timestamp(skb); 1869 1870 skb_queue_tail(&tp->tx_queue, skb); 1871 1872 if (!list_empty(&tp->tx_free)) { 1873 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 1874 set_bit(SCHEDULE_TASKLET, &tp->flags); 1875 schedule_delayed_work(&tp->schedule, 0); 1876 } else { 1877 usb_mark_last_busy(tp->udev); 1878 tasklet_schedule(&tp->tl); 1879 } 1880 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) 1881 netif_stop_queue(netdev); 1882 1883 return NETDEV_TX_OK; 1884 } 1885 1886 static void r8152b_reset_packet_filter(struct r8152 *tp) 1887 { 1888 u32 ocp_data; 1889 1890 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 1891 ocp_data &= ~FMC_FCR_MCU_EN; 1892 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 1893 ocp_data |= FMC_FCR_MCU_EN; 1894 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 1895 } 1896 1897 static void rtl8152_nic_reset(struct r8152 *tp) 1898 { 1899 int i; 1900 1901 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 1902 1903 for (i = 0; i < 1000; i++) { 1904 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 1905 break; 1906 udelay(100); 1907 } 1908 } 1909 1910 static void set_tx_qlen(struct r8152 *tp) 1911 { 1912 struct net_device *netdev = tp->netdev; 1913 1914 tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + 1915 sizeof(struct tx_desc)); 1916 } 1917 1918 static inline u8 rtl8152_get_speed(struct r8152 *tp) 1919 { 1920 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 1921 } 1922 1923 static void rtl_set_eee_plus(struct r8152 *tp) 1924 { 1925 u32 ocp_data; 1926 u8 speed; 1927 1928 speed = rtl8152_get_speed(tp); 1929 if (speed & _10bps) { 1930 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 1931 ocp_data |= EEEP_CR_EEEP_TX; 1932 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 1933 } else { 1934 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 1935 ocp_data &= ~EEEP_CR_EEEP_TX; 1936 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 1937 } 1938 } 1939 1940 static void rxdy_gated_en(struct r8152 *tp, bool enable) 1941 { 1942 u32 ocp_data; 1943 1944 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 1945 if (enable) 1946 ocp_data |= RXDY_GATED_EN; 1947 else 1948 ocp_data &= ~RXDY_GATED_EN; 1949 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 1950 } 1951 1952 static int rtl_enable(struct r8152 *tp) 1953 { 1954 u32 ocp_data; 1955 int i, ret; 1956 1957 r8152b_reset_packet_filter(tp); 1958 1959 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 1960 ocp_data |= CR_RE | CR_TE; 1961 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 1962 1963 rxdy_gated_en(tp, false); 1964 1965 INIT_LIST_HEAD(&tp->rx_done); 1966 ret = 0; 1967 for (i = 0; i < RTL8152_MAX_RX; i++) { 1968 INIT_LIST_HEAD(&tp->rx_info[i].list); 1969 ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 1970 } 1971 1972 return ret; 1973 } 1974 1975 static int rtl8152_enable(struct r8152 *tp) 1976 { 1977 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1978 return -ENODEV; 1979 1980 set_tx_qlen(tp); 1981 rtl_set_eee_plus(tp); 1982 1983 return rtl_enable(tp); 1984 } 1985 1986 static void r8153_set_rx_agg(struct r8152 *tp) 1987 { 1988 u8 speed; 1989 1990 speed = rtl8152_get_speed(tp); 1991 if (speed & _1000bps) { 1992 if (tp->udev->speed == USB_SPEED_SUPER) { 1993 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 1994 RX_THR_SUPPER); 1995 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, 1996 EARLY_AGG_SUPPER); 1997 } else { 1998 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 1999 RX_THR_HIGH); 2000 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, 2001 EARLY_AGG_HIGH); 2002 } 2003 } else { 2004 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW); 2005 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, 2006 EARLY_AGG_SLOW); 2007 } 2008 } 2009 2010 static int rtl8153_enable(struct r8152 *tp) 2011 { 2012 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2013 return -ENODEV; 2014 2015 set_tx_qlen(tp); 2016 rtl_set_eee_plus(tp); 2017 r8153_set_rx_agg(tp); 2018 2019 return rtl_enable(tp); 2020 } 2021 2022 static void rtl8152_disable(struct r8152 *tp) 2023 { 2024 u32 ocp_data; 2025 int i; 2026 2027 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2028 rtl_drop_queued_tx(tp); 2029 return; 2030 } 2031 2032 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2033 ocp_data &= ~RCR_ACPT_ALL; 2034 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2035 2036 rtl_drop_queued_tx(tp); 2037 2038 for (i = 0; i < RTL8152_MAX_TX; i++) 2039 usb_kill_urb(tp->tx_info[i].urb); 2040 2041 rxdy_gated_en(tp, true); 2042 2043 for (i = 0; i < 1000; i++) { 2044 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2045 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2046 break; 2047 mdelay(1); 2048 } 2049 2050 for (i = 0; i < 1000; i++) { 2051 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2052 break; 2053 mdelay(1); 2054 } 2055 2056 for (i = 0; i < RTL8152_MAX_RX; i++) 2057 usb_kill_urb(tp->rx_info[i].urb); 2058 2059 rtl8152_nic_reset(tp); 2060 } 2061 2062 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2063 { 2064 u32 ocp_data; 2065 2066 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2067 if (enable) 2068 ocp_data |= POWER_CUT; 2069 else 2070 ocp_data &= ~POWER_CUT; 2071 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2072 2073 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2074 ocp_data &= ~RESUME_INDICATE; 2075 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2076 } 2077 2078 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2079 2080 static u32 __rtl_get_wol(struct r8152 *tp) 2081 { 2082 u32 ocp_data; 2083 u32 wolopts = 0; 2084 2085 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2086 if (!(ocp_data & LAN_WAKE_EN)) 2087 return 0; 2088 2089 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2090 if (ocp_data & LINK_ON_WAKE_EN) 2091 wolopts |= WAKE_PHY; 2092 2093 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2094 if (ocp_data & UWF_EN) 2095 wolopts |= WAKE_UCAST; 2096 if (ocp_data & BWF_EN) 2097 wolopts |= WAKE_BCAST; 2098 if (ocp_data & MWF_EN) 2099 wolopts |= WAKE_MCAST; 2100 2101 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2102 if (ocp_data & MAGIC_EN) 2103 wolopts |= WAKE_MAGIC; 2104 2105 return wolopts; 2106 } 2107 2108 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2109 { 2110 u32 ocp_data; 2111 2112 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2113 2114 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2115 ocp_data &= ~LINK_ON_WAKE_EN; 2116 if (wolopts & WAKE_PHY) 2117 ocp_data |= LINK_ON_WAKE_EN; 2118 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2119 2120 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2121 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN); 2122 if (wolopts & WAKE_UCAST) 2123 ocp_data |= UWF_EN; 2124 if (wolopts & WAKE_BCAST) 2125 ocp_data |= BWF_EN; 2126 if (wolopts & WAKE_MCAST) 2127 ocp_data |= MWF_EN; 2128 if (wolopts & WAKE_ANY) 2129 ocp_data |= LAN_WAKE_EN; 2130 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2131 2132 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2133 2134 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2135 ocp_data &= ~MAGIC_EN; 2136 if (wolopts & WAKE_MAGIC) 2137 ocp_data |= MAGIC_EN; 2138 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2139 2140 if (wolopts & WAKE_ANY) 2141 device_set_wakeup_enable(&tp->udev->dev, true); 2142 else 2143 device_set_wakeup_enable(&tp->udev->dev, false); 2144 } 2145 2146 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 2147 { 2148 if (enable) { 2149 u32 ocp_data; 2150 2151 __rtl_set_wol(tp, WAKE_ANY); 2152 2153 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2154 2155 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2156 ocp_data |= LINK_OFF_WAKE_EN; 2157 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2158 2159 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2160 } else { 2161 __rtl_set_wol(tp, tp->saved_wolopts); 2162 } 2163 } 2164 2165 static void rtl_phy_reset(struct r8152 *tp) 2166 { 2167 u16 data; 2168 int i; 2169 2170 clear_bit(PHY_RESET, &tp->flags); 2171 2172 data = r8152_mdio_read(tp, MII_BMCR); 2173 2174 /* don't reset again before the previous one complete */ 2175 if (data & BMCR_RESET) 2176 return; 2177 2178 data |= BMCR_RESET; 2179 r8152_mdio_write(tp, MII_BMCR, data); 2180 2181 for (i = 0; i < 50; i++) { 2182 msleep(20); 2183 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 2184 break; 2185 } 2186 } 2187 2188 static void rtl_clear_bp(struct r8152 *tp) 2189 { 2190 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0); 2191 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0); 2192 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0); 2193 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0); 2194 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0); 2195 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0); 2196 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0); 2197 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0); 2198 mdelay(3); 2199 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0); 2200 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0); 2201 } 2202 2203 static void r8153_clear_bp(struct r8152 *tp) 2204 { 2205 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0); 2206 ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0); 2207 rtl_clear_bp(tp); 2208 } 2209 2210 static void r8153_teredo_off(struct r8152 *tp) 2211 { 2212 u32 ocp_data; 2213 2214 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2215 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); 2216 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2217 2218 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 2219 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 2220 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 2221 } 2222 2223 static void r8152b_disable_aldps(struct r8152 *tp) 2224 { 2225 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); 2226 msleep(20); 2227 } 2228 2229 static inline void r8152b_enable_aldps(struct r8152 *tp) 2230 { 2231 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 2232 LINKENA | DIS_SDSAVE); 2233 } 2234 2235 static void r8152b_hw_phy_cfg(struct r8152 *tp) 2236 { 2237 u16 data; 2238 2239 data = r8152_mdio_read(tp, MII_BMCR); 2240 if (data & BMCR_PDOWN) { 2241 data &= ~BMCR_PDOWN; 2242 r8152_mdio_write(tp, MII_BMCR, data); 2243 } 2244 2245 r8152b_disable_aldps(tp); 2246 2247 rtl_clear_bp(tp); 2248 2249 r8152b_enable_aldps(tp); 2250 set_bit(PHY_RESET, &tp->flags); 2251 } 2252 2253 static void r8152b_exit_oob(struct r8152 *tp) 2254 { 2255 u32 ocp_data; 2256 int i; 2257 2258 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2259 return; 2260 2261 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2262 ocp_data &= ~RCR_ACPT_ALL; 2263 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2264 2265 rxdy_gated_en(tp, true); 2266 r8153_teredo_off(tp); 2267 r8152b_hw_phy_cfg(tp); 2268 2269 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2270 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 2271 2272 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2273 ocp_data &= ~NOW_IS_OOB; 2274 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2275 2276 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2277 ocp_data &= ~MCU_BORW_EN; 2278 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2279 2280 for (i = 0; i < 1000; i++) { 2281 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2282 if (ocp_data & LINK_LIST_READY) 2283 break; 2284 mdelay(1); 2285 } 2286 2287 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2288 ocp_data |= RE_INIT_LL; 2289 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2290 2291 for (i = 0; i < 1000; i++) { 2292 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2293 if (ocp_data & LINK_LIST_READY) 2294 break; 2295 mdelay(1); 2296 } 2297 2298 rtl8152_nic_reset(tp); 2299 2300 /* rx share fifo credit full threshold */ 2301 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2302 2303 if (tp->udev->speed == USB_SPEED_FULL || 2304 tp->udev->speed == USB_SPEED_LOW) { 2305 /* rx share fifo credit near full threshold */ 2306 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2307 RXFIFO_THR2_FULL); 2308 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2309 RXFIFO_THR3_FULL); 2310 } else { 2311 /* rx share fifo credit near full threshold */ 2312 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2313 RXFIFO_THR2_HIGH); 2314 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2315 RXFIFO_THR3_HIGH); 2316 } 2317 2318 /* TX share fifo free credit full threshold */ 2319 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 2320 2321 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 2322 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 2323 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 2324 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 2325 2326 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2327 ocp_data &= ~CPCR_RX_VLAN; 2328 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2329 2330 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2331 2332 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2333 ocp_data |= TCR0_AUTO_FIFO; 2334 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2335 } 2336 2337 static void r8152b_enter_oob(struct r8152 *tp) 2338 { 2339 u32 ocp_data; 2340 int i; 2341 2342 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2343 ocp_data &= ~NOW_IS_OOB; 2344 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2345 2346 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 2347 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 2348 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 2349 2350 rtl8152_disable(tp); 2351 2352 for (i = 0; i < 1000; i++) { 2353 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2354 if (ocp_data & LINK_LIST_READY) 2355 break; 2356 mdelay(1); 2357 } 2358 2359 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2360 ocp_data |= RE_INIT_LL; 2361 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2362 2363 for (i = 0; i < 1000; i++) { 2364 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2365 if (ocp_data & LINK_LIST_READY) 2366 break; 2367 mdelay(1); 2368 } 2369 2370 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2371 2372 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2373 ocp_data |= CPCR_RX_VLAN; 2374 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2375 2376 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2377 ocp_data |= ALDPS_PROXY_MODE; 2378 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2379 2380 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2381 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2382 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2383 2384 rxdy_gated_en(tp, false); 2385 2386 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2387 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2388 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2389 } 2390 2391 static void r8153_hw_phy_cfg(struct r8152 *tp) 2392 { 2393 u32 ocp_data; 2394 u16 data; 2395 2396 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 2397 data = r8152_mdio_read(tp, MII_BMCR); 2398 if (data & BMCR_PDOWN) { 2399 data &= ~BMCR_PDOWN; 2400 r8152_mdio_write(tp, MII_BMCR, data); 2401 } 2402 2403 r8153_clear_bp(tp); 2404 2405 if (tp->version == RTL_VER_03) { 2406 data = ocp_reg_read(tp, OCP_EEE_CFG); 2407 data &= ~CTAP_SHORT_EN; 2408 ocp_reg_write(tp, OCP_EEE_CFG, data); 2409 } 2410 2411 data = ocp_reg_read(tp, OCP_POWER_CFG); 2412 data |= EEE_CLKDIV_EN; 2413 ocp_reg_write(tp, OCP_POWER_CFG, data); 2414 2415 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 2416 data |= EN_10M_BGOFF; 2417 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 2418 data = ocp_reg_read(tp, OCP_POWER_CFG); 2419 data |= EN_10M_PLLOFF; 2420 ocp_reg_write(tp, OCP_POWER_CFG, data); 2421 data = sram_read(tp, SRAM_IMPEDANCE); 2422 data &= ~RX_DRIVING_MASK; 2423 sram_write(tp, SRAM_IMPEDANCE, data); 2424 2425 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 2426 ocp_data |= PFM_PWM_SWITCH; 2427 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 2428 2429 data = sram_read(tp, SRAM_LPF_CFG); 2430 data |= LPF_AUTO_TUNE; 2431 sram_write(tp, SRAM_LPF_CFG, data); 2432 2433 data = sram_read(tp, SRAM_10M_AMP1); 2434 data |= GDAC_IB_UPALL; 2435 sram_write(tp, SRAM_10M_AMP1, data); 2436 data = sram_read(tp, SRAM_10M_AMP2); 2437 data |= AMP_DN; 2438 sram_write(tp, SRAM_10M_AMP2, data); 2439 2440 set_bit(PHY_RESET, &tp->flags); 2441 } 2442 2443 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2444 { 2445 u8 u1u2[8]; 2446 2447 if (enable) 2448 memset(u1u2, 0xff, sizeof(u1u2)); 2449 else 2450 memset(u1u2, 0x00, sizeof(u1u2)); 2451 2452 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2453 } 2454 2455 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2456 { 2457 u32 ocp_data; 2458 2459 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2460 if (enable) 2461 ocp_data |= U2P3_ENABLE; 2462 else 2463 ocp_data &= ~U2P3_ENABLE; 2464 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2465 } 2466 2467 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2468 { 2469 u32 ocp_data; 2470 2471 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2472 if (enable) 2473 ocp_data |= PWR_EN | PHASE2_EN; 2474 else 2475 ocp_data &= ~(PWR_EN | PHASE2_EN); 2476 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2477 2478 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2479 ocp_data &= ~PCUT_STATUS; 2480 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2481 } 2482 2483 static void r8153_first_init(struct r8152 *tp) 2484 { 2485 u32 ocp_data; 2486 int i; 2487 2488 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2489 return; 2490 2491 rxdy_gated_en(tp, true); 2492 r8153_teredo_off(tp); 2493 2494 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2495 ocp_data &= ~RCR_ACPT_ALL; 2496 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2497 2498 r8153_hw_phy_cfg(tp); 2499 2500 rtl8152_nic_reset(tp); 2501 2502 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2503 ocp_data &= ~NOW_IS_OOB; 2504 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2505 2506 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2507 ocp_data &= ~MCU_BORW_EN; 2508 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2509 2510 for (i = 0; i < 1000; i++) { 2511 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2512 if (ocp_data & LINK_LIST_READY) 2513 break; 2514 mdelay(1); 2515 } 2516 2517 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2518 ocp_data |= RE_INIT_LL; 2519 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2520 2521 for (i = 0; i < 1000; i++) { 2522 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2523 if (ocp_data & LINK_LIST_READY) 2524 break; 2525 mdelay(1); 2526 } 2527 2528 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2529 ocp_data &= ~CPCR_RX_VLAN; 2530 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2531 2532 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); 2533 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 2534 2535 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2536 ocp_data |= TCR0_AUTO_FIFO; 2537 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2538 2539 rtl8152_nic_reset(tp); 2540 2541 /* rx share fifo credit full threshold */ 2542 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2543 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 2544 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 2545 /* TX share fifo free credit full threshold */ 2546 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 2547 2548 /* rx aggregation */ 2549 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 2550 ocp_data &= ~RX_AGG_DISABLE; 2551 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 2552 } 2553 2554 static void r8153_enter_oob(struct r8152 *tp) 2555 { 2556 u32 ocp_data; 2557 int i; 2558 2559 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2560 ocp_data &= ~NOW_IS_OOB; 2561 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2562 2563 rtl8152_disable(tp); 2564 2565 for (i = 0; i < 1000; i++) { 2566 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2567 if (ocp_data & LINK_LIST_READY) 2568 break; 2569 mdelay(1); 2570 } 2571 2572 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2573 ocp_data |= RE_INIT_LL; 2574 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2575 2576 for (i = 0; i < 1000; i++) { 2577 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2578 if (ocp_data & LINK_LIST_READY) 2579 break; 2580 mdelay(1); 2581 } 2582 2583 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); 2584 2585 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2586 ocp_data &= ~TEREDO_WAKE_MASK; 2587 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2588 2589 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2590 ocp_data |= CPCR_RX_VLAN; 2591 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2592 2593 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2594 ocp_data |= ALDPS_PROXY_MODE; 2595 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2596 2597 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2598 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2599 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2600 2601 rxdy_gated_en(tp, false); 2602 2603 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2604 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2605 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2606 } 2607 2608 static void r8153_disable_aldps(struct r8152 *tp) 2609 { 2610 u16 data; 2611 2612 data = ocp_reg_read(tp, OCP_POWER_CFG); 2613 data &= ~EN_ALDPS; 2614 ocp_reg_write(tp, OCP_POWER_CFG, data); 2615 msleep(20); 2616 } 2617 2618 static void r8153_enable_aldps(struct r8152 *tp) 2619 { 2620 u16 data; 2621 2622 data = ocp_reg_read(tp, OCP_POWER_CFG); 2623 data |= EN_ALDPS; 2624 ocp_reg_write(tp, OCP_POWER_CFG, data); 2625 } 2626 2627 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 2628 { 2629 u16 bmcr, anar, gbcr; 2630 int ret = 0; 2631 2632 cancel_delayed_work_sync(&tp->schedule); 2633 anar = r8152_mdio_read(tp, MII_ADVERTISE); 2634 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 2635 ADVERTISE_100HALF | ADVERTISE_100FULL); 2636 if (tp->mii.supports_gmii) { 2637 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 2638 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 2639 } else { 2640 gbcr = 0; 2641 } 2642 2643 if (autoneg == AUTONEG_DISABLE) { 2644 if (speed == SPEED_10) { 2645 bmcr = 0; 2646 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2647 } else if (speed == SPEED_100) { 2648 bmcr = BMCR_SPEED100; 2649 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2650 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 2651 bmcr = BMCR_SPEED1000; 2652 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 2653 } else { 2654 ret = -EINVAL; 2655 goto out; 2656 } 2657 2658 if (duplex == DUPLEX_FULL) 2659 bmcr |= BMCR_FULLDPLX; 2660 } else { 2661 if (speed == SPEED_10) { 2662 if (duplex == DUPLEX_FULL) 2663 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2664 else 2665 anar |= ADVERTISE_10HALF; 2666 } else if (speed == SPEED_100) { 2667 if (duplex == DUPLEX_FULL) { 2668 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2669 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2670 } else { 2671 anar |= ADVERTISE_10HALF; 2672 anar |= ADVERTISE_100HALF; 2673 } 2674 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 2675 if (duplex == DUPLEX_FULL) { 2676 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2677 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2678 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 2679 } else { 2680 anar |= ADVERTISE_10HALF; 2681 anar |= ADVERTISE_100HALF; 2682 gbcr |= ADVERTISE_1000HALF; 2683 } 2684 } else { 2685 ret = -EINVAL; 2686 goto out; 2687 } 2688 2689 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 2690 } 2691 2692 if (test_bit(PHY_RESET, &tp->flags)) 2693 bmcr |= BMCR_RESET; 2694 2695 if (tp->mii.supports_gmii) 2696 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 2697 2698 r8152_mdio_write(tp, MII_ADVERTISE, anar); 2699 r8152_mdio_write(tp, MII_BMCR, bmcr); 2700 2701 if (test_bit(PHY_RESET, &tp->flags)) { 2702 int i; 2703 2704 clear_bit(PHY_RESET, &tp->flags); 2705 for (i = 0; i < 50; i++) { 2706 msleep(20); 2707 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 2708 break; 2709 } 2710 } 2711 2712 out: 2713 2714 return ret; 2715 } 2716 2717 static void rtl8152_down(struct r8152 *tp) 2718 { 2719 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2720 rtl_drop_queued_tx(tp); 2721 return; 2722 } 2723 2724 r8152_power_cut_en(tp, false); 2725 r8152b_disable_aldps(tp); 2726 r8152b_enter_oob(tp); 2727 r8152b_enable_aldps(tp); 2728 } 2729 2730 static void rtl8153_down(struct r8152 *tp) 2731 { 2732 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2733 rtl_drop_queued_tx(tp); 2734 return; 2735 } 2736 2737 r8153_u1u2en(tp, false); 2738 r8153_power_cut_en(tp, false); 2739 r8153_disable_aldps(tp); 2740 r8153_enter_oob(tp); 2741 r8153_enable_aldps(tp); 2742 } 2743 2744 static void set_carrier(struct r8152 *tp) 2745 { 2746 struct net_device *netdev = tp->netdev; 2747 u8 speed; 2748 2749 clear_bit(RTL8152_LINK_CHG, &tp->flags); 2750 speed = rtl8152_get_speed(tp); 2751 2752 if (speed & LINK_STATUS) { 2753 if (!(tp->speed & LINK_STATUS)) { 2754 tp->rtl_ops.enable(tp); 2755 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2756 netif_carrier_on(netdev); 2757 } 2758 } else { 2759 if (tp->speed & LINK_STATUS) { 2760 netif_carrier_off(netdev); 2761 tasklet_disable(&tp->tl); 2762 tp->rtl_ops.disable(tp); 2763 tasklet_enable(&tp->tl); 2764 } 2765 } 2766 tp->speed = speed; 2767 } 2768 2769 static void rtl_work_func_t(struct work_struct *work) 2770 { 2771 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 2772 2773 if (usb_autopm_get_interface(tp->intf) < 0) 2774 return; 2775 2776 if (!test_bit(WORK_ENABLE, &tp->flags)) 2777 goto out1; 2778 2779 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2780 goto out1; 2781 2782 if (test_bit(RTL8152_LINK_CHG, &tp->flags)) 2783 set_carrier(tp); 2784 2785 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) 2786 _rtl8152_set_rx_mode(tp->netdev); 2787 2788 if (test_bit(SCHEDULE_TASKLET, &tp->flags) && 2789 (tp->speed & LINK_STATUS)) { 2790 clear_bit(SCHEDULE_TASKLET, &tp->flags); 2791 tasklet_schedule(&tp->tl); 2792 } 2793 2794 if (test_bit(PHY_RESET, &tp->flags)) 2795 rtl_phy_reset(tp); 2796 2797 out1: 2798 usb_autopm_put_interface(tp->intf); 2799 } 2800 2801 static int rtl8152_open(struct net_device *netdev) 2802 { 2803 struct r8152 *tp = netdev_priv(netdev); 2804 int res = 0; 2805 2806 res = alloc_all_mem(tp); 2807 if (res) 2808 goto out; 2809 2810 res = usb_autopm_get_interface(tp->intf); 2811 if (res < 0) { 2812 free_all_mem(tp); 2813 goto out; 2814 } 2815 2816 /* The WORK_ENABLE may be set when autoresume occurs */ 2817 if (test_bit(WORK_ENABLE, &tp->flags)) { 2818 clear_bit(WORK_ENABLE, &tp->flags); 2819 usb_kill_urb(tp->intr_urb); 2820 cancel_delayed_work_sync(&tp->schedule); 2821 if (tp->speed & LINK_STATUS) 2822 tp->rtl_ops.disable(tp); 2823 } 2824 2825 tp->rtl_ops.up(tp); 2826 2827 rtl8152_set_speed(tp, AUTONEG_ENABLE, 2828 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, 2829 DUPLEX_FULL); 2830 tp->speed = 0; 2831 netif_carrier_off(netdev); 2832 netif_start_queue(netdev); 2833 set_bit(WORK_ENABLE, &tp->flags); 2834 2835 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 2836 if (res) { 2837 if (res == -ENODEV) 2838 netif_device_detach(tp->netdev); 2839 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 2840 res); 2841 free_all_mem(tp); 2842 } 2843 2844 usb_autopm_put_interface(tp->intf); 2845 2846 out: 2847 return res; 2848 } 2849 2850 static int rtl8152_close(struct net_device *netdev) 2851 { 2852 struct r8152 *tp = netdev_priv(netdev); 2853 int res = 0; 2854 2855 clear_bit(WORK_ENABLE, &tp->flags); 2856 usb_kill_urb(tp->intr_urb); 2857 cancel_delayed_work_sync(&tp->schedule); 2858 netif_stop_queue(netdev); 2859 2860 res = usb_autopm_get_interface(tp->intf); 2861 if (res < 0) { 2862 rtl_drop_queued_tx(tp); 2863 } else { 2864 /* 2865 * The autosuspend may have been enabled and wouldn't 2866 * be disable when autoresume occurs, because the 2867 * netif_running() would be false. 2868 */ 2869 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2870 rtl_runtime_suspend_enable(tp, false); 2871 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 2872 } 2873 2874 tasklet_disable(&tp->tl); 2875 tp->rtl_ops.down(tp); 2876 tasklet_enable(&tp->tl); 2877 usb_autopm_put_interface(tp->intf); 2878 } 2879 2880 free_all_mem(tp); 2881 2882 return res; 2883 } 2884 2885 static void r8152b_enable_eee(struct r8152 *tp) 2886 { 2887 u32 ocp_data; 2888 2889 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 2890 ocp_data |= EEE_RX_EN | EEE_TX_EN; 2891 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 2892 ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN | 2893 EEE_10_CAP | EEE_NWAY_EN | 2894 TX_QUIET_EN | RX_QUIET_EN | 2895 SDRISETIME | RG_RXLPI_MSK_HFDUP | 2896 SDFALLTIME); 2897 ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN | 2898 RG_LDVQUIET_EN | RG_CKRSEL | 2899 RG_EEEPRG_EN); 2900 ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH); 2901 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR); 2902 ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR); 2903 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR); 2904 ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA); 2905 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 2906 } 2907 2908 static void r8153_enable_eee(struct r8152 *tp) 2909 { 2910 u32 ocp_data; 2911 u16 data; 2912 2913 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 2914 ocp_data |= EEE_RX_EN | EEE_TX_EN; 2915 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 2916 data = ocp_reg_read(tp, OCP_EEE_CFG); 2917 data |= EEE10_EN; 2918 ocp_reg_write(tp, OCP_EEE_CFG, data); 2919 data = ocp_reg_read(tp, OCP_EEE_CFG2); 2920 data |= MY1000_EEE | MY100_EEE; 2921 ocp_reg_write(tp, OCP_EEE_CFG2, data); 2922 } 2923 2924 static void r8152b_enable_fc(struct r8152 *tp) 2925 { 2926 u16 anar; 2927 2928 anar = r8152_mdio_read(tp, MII_ADVERTISE); 2929 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 2930 r8152_mdio_write(tp, MII_ADVERTISE, anar); 2931 } 2932 2933 static void rtl_tally_reset(struct r8152 *tp) 2934 { 2935 u32 ocp_data; 2936 2937 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 2938 ocp_data |= TALLY_RESET; 2939 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 2940 } 2941 2942 static void r8152b_init(struct r8152 *tp) 2943 { 2944 u32 ocp_data; 2945 2946 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2947 return; 2948 2949 if (tp->version == RTL_VER_01) { 2950 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 2951 ocp_data &= ~LED_MODE_MASK; 2952 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 2953 } 2954 2955 r8152_power_cut_en(tp, false); 2956 2957 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 2958 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 2959 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 2960 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 2961 ocp_data &= ~MCU_CLK_RATIO_MASK; 2962 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 2963 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 2964 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 2965 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 2966 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 2967 2968 r8152b_enable_eee(tp); 2969 r8152b_enable_aldps(tp); 2970 r8152b_enable_fc(tp); 2971 rtl_tally_reset(tp); 2972 2973 /* enable rx aggregation */ 2974 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 2975 ocp_data &= ~RX_AGG_DISABLE; 2976 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 2977 } 2978 2979 static void r8153_init(struct r8152 *tp) 2980 { 2981 u32 ocp_data; 2982 int i; 2983 2984 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2985 return; 2986 2987 r8153_u1u2en(tp, false); 2988 2989 for (i = 0; i < 500; i++) { 2990 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 2991 AUTOLOAD_DONE) 2992 break; 2993 msleep(20); 2994 } 2995 2996 for (i = 0; i < 500; i++) { 2997 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; 2998 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) 2999 break; 3000 msleep(20); 3001 } 3002 3003 r8153_u2p3en(tp, false); 3004 3005 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 3006 ocp_data &= ~TIMER11_EN; 3007 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 3008 3009 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 3010 ocp_data &= ~LED_MODE_MASK; 3011 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 3012 3013 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL); 3014 ocp_data &= ~LPM_TIMER_MASK; 3015 if (tp->udev->speed == USB_SPEED_SUPER) 3016 ocp_data |= LPM_TIMER_500US; 3017 else 3018 ocp_data |= LPM_TIMER_500MS; 3019 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 3020 3021 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 3022 ocp_data &= ~SEN_VAL_MASK; 3023 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 3024 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 3025 3026 r8153_power_cut_en(tp, false); 3027 r8153_u1u2en(tp, true); 3028 3029 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); 3030 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); 3031 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 3032 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | 3033 U1U2_SPDWN_EN | L1_SPDWN_EN); 3034 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 3035 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | 3036 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | 3037 EEE_SPDWN_EN); 3038 3039 r8153_enable_eee(tp); 3040 r8153_enable_aldps(tp); 3041 r8152b_enable_fc(tp); 3042 rtl_tally_reset(tp); 3043 } 3044 3045 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 3046 { 3047 struct r8152 *tp = usb_get_intfdata(intf); 3048 3049 if (PMSG_IS_AUTO(message)) 3050 set_bit(SELECTIVE_SUSPEND, &tp->flags); 3051 else 3052 netif_device_detach(tp->netdev); 3053 3054 if (netif_running(tp->netdev)) { 3055 clear_bit(WORK_ENABLE, &tp->flags); 3056 usb_kill_urb(tp->intr_urb); 3057 cancel_delayed_work_sync(&tp->schedule); 3058 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3059 rtl_runtime_suspend_enable(tp, true); 3060 } else { 3061 tasklet_disable(&tp->tl); 3062 tp->rtl_ops.down(tp); 3063 tasklet_enable(&tp->tl); 3064 } 3065 } 3066 3067 return 0; 3068 } 3069 3070 static int rtl8152_resume(struct usb_interface *intf) 3071 { 3072 struct r8152 *tp = usb_get_intfdata(intf); 3073 3074 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3075 tp->rtl_ops.init(tp); 3076 netif_device_attach(tp->netdev); 3077 } 3078 3079 if (netif_running(tp->netdev)) { 3080 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3081 rtl_runtime_suspend_enable(tp, false); 3082 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3083 if (tp->speed & LINK_STATUS) 3084 tp->rtl_ops.disable(tp); 3085 } else { 3086 tp->rtl_ops.up(tp); 3087 rtl8152_set_speed(tp, AUTONEG_ENABLE, 3088 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, 3089 DUPLEX_FULL); 3090 } 3091 tp->speed = 0; 3092 netif_carrier_off(tp->netdev); 3093 set_bit(WORK_ENABLE, &tp->flags); 3094 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3095 } 3096 3097 return 0; 3098 } 3099 3100 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3101 { 3102 struct r8152 *tp = netdev_priv(dev); 3103 3104 if (usb_autopm_get_interface(tp->intf) < 0) 3105 return; 3106 3107 wol->supported = WAKE_ANY; 3108 wol->wolopts = __rtl_get_wol(tp); 3109 3110 usb_autopm_put_interface(tp->intf); 3111 } 3112 3113 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3114 { 3115 struct r8152 *tp = netdev_priv(dev); 3116 int ret; 3117 3118 ret = usb_autopm_get_interface(tp->intf); 3119 if (ret < 0) 3120 goto out_set_wol; 3121 3122 __rtl_set_wol(tp, wol->wolopts); 3123 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 3124 3125 usb_autopm_put_interface(tp->intf); 3126 3127 out_set_wol: 3128 return ret; 3129 } 3130 3131 static u32 rtl8152_get_msglevel(struct net_device *dev) 3132 { 3133 struct r8152 *tp = netdev_priv(dev); 3134 3135 return tp->msg_enable; 3136 } 3137 3138 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 3139 { 3140 struct r8152 *tp = netdev_priv(dev); 3141 3142 tp->msg_enable = value; 3143 } 3144 3145 static void rtl8152_get_drvinfo(struct net_device *netdev, 3146 struct ethtool_drvinfo *info) 3147 { 3148 struct r8152 *tp = netdev_priv(netdev); 3149 3150 strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN); 3151 strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN); 3152 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 3153 } 3154 3155 static 3156 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) 3157 { 3158 struct r8152 *tp = netdev_priv(netdev); 3159 3160 if (!tp->mii.mdio_read) 3161 return -EOPNOTSUPP; 3162 3163 return mii_ethtool_gset(&tp->mii, cmd); 3164 } 3165 3166 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 3167 { 3168 struct r8152 *tp = netdev_priv(dev); 3169 int ret; 3170 3171 ret = usb_autopm_get_interface(tp->intf); 3172 if (ret < 0) 3173 goto out; 3174 3175 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); 3176 3177 usb_autopm_put_interface(tp->intf); 3178 3179 out: 3180 return ret; 3181 } 3182 3183 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 3184 "tx_packets", 3185 "rx_packets", 3186 "tx_errors", 3187 "rx_errors", 3188 "rx_missed", 3189 "align_errors", 3190 "tx_single_collisions", 3191 "tx_multi_collisions", 3192 "rx_unicast", 3193 "rx_broadcast", 3194 "rx_multicast", 3195 "tx_aborted", 3196 "tx_underrun", 3197 }; 3198 3199 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 3200 { 3201 switch (sset) { 3202 case ETH_SS_STATS: 3203 return ARRAY_SIZE(rtl8152_gstrings); 3204 default: 3205 return -EOPNOTSUPP; 3206 } 3207 } 3208 3209 static void rtl8152_get_ethtool_stats(struct net_device *dev, 3210 struct ethtool_stats *stats, u64 *data) 3211 { 3212 struct r8152 *tp = netdev_priv(dev); 3213 struct tally_counter tally; 3214 3215 if (usb_autopm_get_interface(tp->intf) < 0) 3216 return; 3217 3218 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 3219 3220 usb_autopm_put_interface(tp->intf); 3221 3222 data[0] = le64_to_cpu(tally.tx_packets); 3223 data[1] = le64_to_cpu(tally.rx_packets); 3224 data[2] = le64_to_cpu(tally.tx_errors); 3225 data[3] = le32_to_cpu(tally.rx_errors); 3226 data[4] = le16_to_cpu(tally.rx_missed); 3227 data[5] = le16_to_cpu(tally.align_errors); 3228 data[6] = le32_to_cpu(tally.tx_one_collision); 3229 data[7] = le32_to_cpu(tally.tx_multi_collision); 3230 data[8] = le64_to_cpu(tally.rx_unicast); 3231 data[9] = le64_to_cpu(tally.rx_broadcast); 3232 data[10] = le32_to_cpu(tally.rx_multicast); 3233 data[11] = le16_to_cpu(tally.tx_aborted); 3234 data[12] = le16_to_cpu(tally.tx_underun); 3235 } 3236 3237 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 3238 { 3239 switch (stringset) { 3240 case ETH_SS_STATS: 3241 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 3242 break; 3243 } 3244 } 3245 3246 static struct ethtool_ops ops = { 3247 .get_drvinfo = rtl8152_get_drvinfo, 3248 .get_settings = rtl8152_get_settings, 3249 .set_settings = rtl8152_set_settings, 3250 .get_link = ethtool_op_get_link, 3251 .get_msglevel = rtl8152_get_msglevel, 3252 .set_msglevel = rtl8152_set_msglevel, 3253 .get_wol = rtl8152_get_wol, 3254 .set_wol = rtl8152_set_wol, 3255 .get_strings = rtl8152_get_strings, 3256 .get_sset_count = rtl8152_get_sset_count, 3257 .get_ethtool_stats = rtl8152_get_ethtool_stats, 3258 }; 3259 3260 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 3261 { 3262 struct r8152 *tp = netdev_priv(netdev); 3263 struct mii_ioctl_data *data = if_mii(rq); 3264 int res; 3265 3266 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3267 return -ENODEV; 3268 3269 res = usb_autopm_get_interface(tp->intf); 3270 if (res < 0) 3271 goto out; 3272 3273 switch (cmd) { 3274 case SIOCGMIIPHY: 3275 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 3276 break; 3277 3278 case SIOCGMIIREG: 3279 data->val_out = r8152_mdio_read(tp, data->reg_num); 3280 break; 3281 3282 case SIOCSMIIREG: 3283 if (!capable(CAP_NET_ADMIN)) { 3284 res = -EPERM; 3285 break; 3286 } 3287 r8152_mdio_write(tp, data->reg_num, data->val_in); 3288 break; 3289 3290 default: 3291 res = -EOPNOTSUPP; 3292 } 3293 3294 usb_autopm_put_interface(tp->intf); 3295 3296 out: 3297 return res; 3298 } 3299 3300 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 3301 { 3302 struct r8152 *tp = netdev_priv(dev); 3303 3304 switch (tp->version) { 3305 case RTL_VER_01: 3306 case RTL_VER_02: 3307 return eth_change_mtu(dev, new_mtu); 3308 default: 3309 break; 3310 } 3311 3312 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU) 3313 return -EINVAL; 3314 3315 dev->mtu = new_mtu; 3316 3317 return 0; 3318 } 3319 3320 static const struct net_device_ops rtl8152_netdev_ops = { 3321 .ndo_open = rtl8152_open, 3322 .ndo_stop = rtl8152_close, 3323 .ndo_do_ioctl = rtl8152_ioctl, 3324 .ndo_start_xmit = rtl8152_start_xmit, 3325 .ndo_tx_timeout = rtl8152_tx_timeout, 3326 .ndo_set_rx_mode = rtl8152_set_rx_mode, 3327 .ndo_set_mac_address = rtl8152_set_mac_address, 3328 .ndo_change_mtu = rtl8152_change_mtu, 3329 .ndo_validate_addr = eth_validate_addr, 3330 }; 3331 3332 static void r8152b_get_version(struct r8152 *tp) 3333 { 3334 u32 ocp_data; 3335 u16 version; 3336 3337 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); 3338 version = (u16)(ocp_data & VERSION_MASK); 3339 3340 switch (version) { 3341 case 0x4c00: 3342 tp->version = RTL_VER_01; 3343 break; 3344 case 0x4c10: 3345 tp->version = RTL_VER_02; 3346 break; 3347 case 0x5c00: 3348 tp->version = RTL_VER_03; 3349 tp->mii.supports_gmii = 1; 3350 break; 3351 case 0x5c10: 3352 tp->version = RTL_VER_04; 3353 tp->mii.supports_gmii = 1; 3354 break; 3355 case 0x5c20: 3356 tp->version = RTL_VER_05; 3357 tp->mii.supports_gmii = 1; 3358 break; 3359 default: 3360 netif_info(tp, probe, tp->netdev, 3361 "Unknown version 0x%04x\n", version); 3362 break; 3363 } 3364 } 3365 3366 static void rtl8152_unload(struct r8152 *tp) 3367 { 3368 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3369 return; 3370 3371 if (tp->version != RTL_VER_01) 3372 r8152_power_cut_en(tp, true); 3373 } 3374 3375 static void rtl8153_unload(struct r8152 *tp) 3376 { 3377 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3378 return; 3379 3380 r8153_power_cut_en(tp, true); 3381 } 3382 3383 static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id) 3384 { 3385 struct rtl_ops *ops = &tp->rtl_ops; 3386 int ret = -ENODEV; 3387 3388 switch (id->idVendor) { 3389 case VENDOR_ID_REALTEK: 3390 switch (id->idProduct) { 3391 case PRODUCT_ID_RTL8152: 3392 ops->init = r8152b_init; 3393 ops->enable = rtl8152_enable; 3394 ops->disable = rtl8152_disable; 3395 ops->up = r8152b_exit_oob; 3396 ops->down = rtl8152_down; 3397 ops->unload = rtl8152_unload; 3398 ret = 0; 3399 break; 3400 case PRODUCT_ID_RTL8153: 3401 ops->init = r8153_init; 3402 ops->enable = rtl8153_enable; 3403 ops->disable = rtl8152_disable; 3404 ops->up = r8153_first_init; 3405 ops->down = rtl8153_down; 3406 ops->unload = rtl8153_unload; 3407 ret = 0; 3408 break; 3409 default: 3410 break; 3411 } 3412 break; 3413 3414 case VENDOR_ID_SAMSUNG: 3415 switch (id->idProduct) { 3416 case PRODUCT_ID_SAMSUNG: 3417 ops->init = r8153_init; 3418 ops->enable = rtl8153_enable; 3419 ops->disable = rtl8152_disable; 3420 ops->up = r8153_first_init; 3421 ops->down = rtl8153_down; 3422 ops->unload = rtl8153_unload; 3423 ret = 0; 3424 break; 3425 default: 3426 break; 3427 } 3428 break; 3429 3430 default: 3431 break; 3432 } 3433 3434 if (ret) 3435 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 3436 3437 return ret; 3438 } 3439 3440 static int rtl8152_probe(struct usb_interface *intf, 3441 const struct usb_device_id *id) 3442 { 3443 struct usb_device *udev = interface_to_usbdev(intf); 3444 struct r8152 *tp; 3445 struct net_device *netdev; 3446 int ret; 3447 3448 if (udev->actconfig->desc.bConfigurationValue != 1) { 3449 usb_driver_set_configuration(udev, 1); 3450 return -ENODEV; 3451 } 3452 3453 usb_reset_device(udev); 3454 netdev = alloc_etherdev(sizeof(struct r8152)); 3455 if (!netdev) { 3456 dev_err(&intf->dev, "Out of memory\n"); 3457 return -ENOMEM; 3458 } 3459 3460 SET_NETDEV_DEV(netdev, &intf->dev); 3461 tp = netdev_priv(netdev); 3462 tp->msg_enable = 0x7FFF; 3463 3464 tp->udev = udev; 3465 tp->netdev = netdev; 3466 tp->intf = intf; 3467 3468 ret = rtl_ops_init(tp, id); 3469 if (ret) 3470 goto out; 3471 3472 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp); 3473 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 3474 3475 netdev->netdev_ops = &rtl8152_netdev_ops; 3476 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 3477 3478 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 3479 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 3480 NETIF_F_TSO6; 3481 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 3482 NETIF_F_TSO | NETIF_F_FRAGLIST | 3483 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 3484 3485 netdev->ethtool_ops = &ops; 3486 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 3487 3488 tp->mii.dev = netdev; 3489 tp->mii.mdio_read = read_mii_word; 3490 tp->mii.mdio_write = write_mii_word; 3491 tp->mii.phy_id_mask = 0x3f; 3492 tp->mii.reg_num_mask = 0x1f; 3493 tp->mii.phy_id = R8152_PHY_ID; 3494 tp->mii.supports_gmii = 0; 3495 3496 intf->needs_remote_wakeup = 1; 3497 3498 r8152b_get_version(tp); 3499 tp->rtl_ops.init(tp); 3500 set_ethernet_addr(tp); 3501 3502 usb_set_intfdata(intf, tp); 3503 3504 ret = register_netdev(netdev); 3505 if (ret != 0) { 3506 netif_err(tp, probe, netdev, "couldn't register the device\n"); 3507 goto out1; 3508 } 3509 3510 tp->saved_wolopts = __rtl_get_wol(tp); 3511 if (tp->saved_wolopts) 3512 device_set_wakeup_enable(&udev->dev, true); 3513 else 3514 device_set_wakeup_enable(&udev->dev, false); 3515 3516 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 3517 3518 return 0; 3519 3520 out1: 3521 usb_set_intfdata(intf, NULL); 3522 out: 3523 free_netdev(netdev); 3524 return ret; 3525 } 3526 3527 static void rtl8152_disconnect(struct usb_interface *intf) 3528 { 3529 struct r8152 *tp = usb_get_intfdata(intf); 3530 3531 usb_set_intfdata(intf, NULL); 3532 if (tp) { 3533 set_bit(RTL8152_UNPLUG, &tp->flags); 3534 tasklet_kill(&tp->tl); 3535 unregister_netdev(tp->netdev); 3536 tp->rtl_ops.unload(tp); 3537 free_netdev(tp->netdev); 3538 } 3539 } 3540 3541 /* table of devices that work with this driver */ 3542 static struct usb_device_id rtl8152_table[] = { 3543 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)}, 3544 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)}, 3545 {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)}, 3546 {} 3547 }; 3548 3549 MODULE_DEVICE_TABLE(usb, rtl8152_table); 3550 3551 static struct usb_driver rtl8152_driver = { 3552 .name = MODULENAME, 3553 .id_table = rtl8152_table, 3554 .probe = rtl8152_probe, 3555 .disconnect = rtl8152_disconnect, 3556 .suspend = rtl8152_suspend, 3557 .resume = rtl8152_resume, 3558 .reset_resume = rtl8152_resume, 3559 .supports_autosuspend = 1, 3560 .disable_hub_initiated_lpm = 1, 3561 }; 3562 3563 module_usb_driver(rtl8152_driver); 3564 3565 MODULE_AUTHOR(DRIVER_AUTHOR); 3566 MODULE_DESCRIPTION(DRIVER_DESC); 3567 MODULE_LICENSE("GPL"); 3568