1 /* 2 * Copyright (c) 2013 Realtek Semiconductor Corp. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2 as published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/init.h> 11 #include <linux/signal.h> 12 #include <linux/slab.h> 13 #include <linux/module.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/mii.h> 17 #include <linux/ethtool.h> 18 #include <linux/usb.h> 19 #include <linux/crc32.h> 20 #include <linux/if_vlan.h> 21 #include <linux/uaccess.h> 22 #include <linux/list.h> 23 #include <linux/ip.h> 24 #include <linux/ipv6.h> 25 26 /* Version Information */ 27 #define DRIVER_VERSION "v1.02.0 (2013/10/28)" 28 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 29 #define DRIVER_DESC "Realtek RTL8152 Based USB 2.0 Ethernet Adapters" 30 #define MODULENAME "r8152" 31 32 #define R8152_PHY_ID 32 33 34 #define PLA_IDR 0xc000 35 #define PLA_RCR 0xc010 36 #define PLA_RMS 0xc016 37 #define PLA_RXFIFO_CTRL0 0xc0a0 38 #define PLA_RXFIFO_CTRL1 0xc0a4 39 #define PLA_RXFIFO_CTRL2 0xc0a8 40 #define PLA_FMC 0xc0b4 41 #define PLA_CFG_WOL 0xc0b6 42 #define PLA_MAR 0xcd00 43 #define PAL_BDC_CR 0xd1a0 44 #define PLA_LEDSEL 0xdd90 45 #define PLA_LED_FEATURE 0xdd92 46 #define PLA_PHYAR 0xde00 47 #define PLA_GPHY_INTR_IMR 0xe022 48 #define PLA_EEE_CR 0xe040 49 #define PLA_EEEP_CR 0xe080 50 #define PLA_MAC_PWR_CTRL 0xe0c0 51 #define PLA_TCR0 0xe610 52 #define PLA_TCR1 0xe612 53 #define PLA_TXFIFO_CTRL 0xe618 54 #define PLA_RSTTELLY 0xe800 55 #define PLA_CR 0xe813 56 #define PLA_CRWECR 0xe81c 57 #define PLA_CONFIG5 0xe822 58 #define PLA_PHY_PWR 0xe84c 59 #define PLA_OOB_CTRL 0xe84f 60 #define PLA_CPCR 0xe854 61 #define PLA_MISC_0 0xe858 62 #define PLA_MISC_1 0xe85a 63 #define PLA_OCP_GPHY_BASE 0xe86c 64 #define PLA_TELLYCNT 0xe890 65 #define PLA_SFF_STS_7 0xe8de 66 #define PLA_PHYSTATUS 0xe908 67 #define PLA_BP_BA 0xfc26 68 #define PLA_BP_0 0xfc28 69 #define PLA_BP_1 0xfc2a 70 #define PLA_BP_2 0xfc2c 71 #define PLA_BP_3 0xfc2e 72 #define PLA_BP_4 0xfc30 73 #define PLA_BP_5 0xfc32 74 #define PLA_BP_6 0xfc34 75 #define PLA_BP_7 0xfc36 76 77 #define USB_DEV_STAT 0xb808 78 #define USB_USB_CTRL 0xd406 79 #define USB_PHY_CTRL 0xd408 80 #define USB_TX_AGG 0xd40a 81 #define USB_RX_BUF_TH 0xd40c 82 #define USB_USB_TIMER 0xd428 83 #define USB_PM_CTRL_STATUS 0xd432 84 #define USB_TX_DMA 0xd434 85 #define USB_UPS_CTRL 0xd800 86 #define USB_BP_BA 0xfc26 87 #define USB_BP_0 0xfc28 88 #define USB_BP_1 0xfc2a 89 #define USB_BP_2 0xfc2c 90 #define USB_BP_3 0xfc2e 91 #define USB_BP_4 0xfc30 92 #define USB_BP_5 0xfc32 93 #define USB_BP_6 0xfc34 94 #define USB_BP_7 0xfc36 95 96 /* OCP Registers */ 97 #define OCP_ALDPS_CONFIG 0x2010 98 #define OCP_EEE_CONFIG1 0x2080 99 #define OCP_EEE_CONFIG2 0x2092 100 #define OCP_EEE_CONFIG3 0x2094 101 #define OCP_EEE_AR 0xa41a 102 #define OCP_EEE_DATA 0xa41c 103 104 /* PLA_RCR */ 105 #define RCR_AAP 0x00000001 106 #define RCR_APM 0x00000002 107 #define RCR_AM 0x00000004 108 #define RCR_AB 0x00000008 109 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 110 111 /* PLA_RXFIFO_CTRL0 */ 112 #define RXFIFO_THR1_NORMAL 0x00080002 113 #define RXFIFO_THR1_OOB 0x01800003 114 115 /* PLA_RXFIFO_CTRL1 */ 116 #define RXFIFO_THR2_FULL 0x00000060 117 #define RXFIFO_THR2_HIGH 0x00000038 118 #define RXFIFO_THR2_OOB 0x0000004a 119 120 /* PLA_RXFIFO_CTRL2 */ 121 #define RXFIFO_THR3_FULL 0x00000078 122 #define RXFIFO_THR3_HIGH 0x00000048 123 #define RXFIFO_THR3_OOB 0x0000005a 124 125 /* PLA_TXFIFO_CTRL */ 126 #define TXFIFO_THR_NORMAL 0x00400008 127 128 /* PLA_FMC */ 129 #define FMC_FCR_MCU_EN 0x0001 130 131 /* PLA_EEEP_CR */ 132 #define EEEP_CR_EEEP_TX 0x0002 133 134 /* PLA_TCR0 */ 135 #define TCR0_TX_EMPTY 0x0800 136 #define TCR0_AUTO_FIFO 0x0080 137 138 /* PLA_TCR1 */ 139 #define VERSION_MASK 0x7cf0 140 141 /* PLA_CR */ 142 #define CR_RST 0x10 143 #define CR_RE 0x08 144 #define CR_TE 0x04 145 146 /* PLA_CRWECR */ 147 #define CRWECR_NORAML 0x00 148 #define CRWECR_CONFIG 0xc0 149 150 /* PLA_OOB_CTRL */ 151 #define NOW_IS_OOB 0x80 152 #define TXFIFO_EMPTY 0x20 153 #define RXFIFO_EMPTY 0x10 154 #define LINK_LIST_READY 0x02 155 #define DIS_MCU_CLROOB 0x01 156 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 157 158 /* PLA_MISC_1 */ 159 #define RXDY_GATED_EN 0x0008 160 161 /* PLA_SFF_STS_7 */ 162 #define RE_INIT_LL 0x8000 163 #define MCU_BORW_EN 0x4000 164 165 /* PLA_CPCR */ 166 #define CPCR_RX_VLAN 0x0040 167 168 /* PLA_CFG_WOL */ 169 #define MAGIC_EN 0x0001 170 171 /* PAL_BDC_CR */ 172 #define ALDPS_PROXY_MODE 0x0001 173 174 /* PLA_CONFIG5 */ 175 #define LAN_WAKE_EN 0x0002 176 177 /* PLA_LED_FEATURE */ 178 #define LED_MODE_MASK 0x0700 179 180 /* PLA_PHY_PWR */ 181 #define TX_10M_IDLE_EN 0x0080 182 #define PFM_PWM_SWITCH 0x0040 183 184 /* PLA_MAC_PWR_CTRL */ 185 #define D3_CLK_GATED_EN 0x00004000 186 #define MCU_CLK_RATIO 0x07010f07 187 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 188 189 /* PLA_GPHY_INTR_IMR */ 190 #define GPHY_STS_MSK 0x0001 191 #define SPEED_DOWN_MSK 0x0002 192 #define SPDWN_RXDV_MSK 0x0004 193 #define SPDWN_LINKCHG_MSK 0x0008 194 195 /* PLA_PHYAR */ 196 #define PHYAR_FLAG 0x80000000 197 198 /* PLA_EEE_CR */ 199 #define EEE_RX_EN 0x0001 200 #define EEE_TX_EN 0x0002 201 202 /* USB_DEV_STAT */ 203 #define STAT_SPEED_MASK 0x0006 204 #define STAT_SPEED_HIGH 0x0000 205 #define STAT_SPEED_FULL 0x0001 206 207 /* USB_TX_AGG */ 208 #define TX_AGG_MAX_THRESHOLD 0x03 209 210 /* USB_RX_BUF_TH */ 211 #define RX_BUF_THR 0x7a120180 212 213 /* USB_TX_DMA */ 214 #define TEST_MODE_DISABLE 0x00000001 215 #define TX_SIZE_ADJUST1 0x00000100 216 217 /* USB_UPS_CTRL */ 218 #define POWER_CUT 0x0100 219 220 /* USB_PM_CTRL_STATUS */ 221 #define RWSUME_INDICATE 0x0001 222 223 /* USB_USB_CTRL */ 224 #define RX_AGG_DISABLE 0x0010 225 226 /* OCP_ALDPS_CONFIG */ 227 #define ENPWRSAVE 0x8000 228 #define ENPDNPS 0x0200 229 #define LINKENA 0x0100 230 #define DIS_SDSAVE 0x0010 231 232 /* OCP_EEE_CONFIG1 */ 233 #define RG_TXLPI_MSK_HFDUP 0x8000 234 #define RG_MATCLR_EN 0x4000 235 #define EEE_10_CAP 0x2000 236 #define EEE_NWAY_EN 0x1000 237 #define TX_QUIET_EN 0x0200 238 #define RX_QUIET_EN 0x0100 239 #define SDRISETIME 0x0010 /* bit 4 ~ 6 */ 240 #define RG_RXLPI_MSK_HFDUP 0x0008 241 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 242 243 /* OCP_EEE_CONFIG2 */ 244 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 245 #define RG_DACQUIET_EN 0x0400 246 #define RG_LDVQUIET_EN 0x0200 247 #define RG_CKRSEL 0x0020 248 #define RG_EEEPRG_EN 0x0010 249 250 /* OCP_EEE_CONFIG3 */ 251 #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */ 252 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 253 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 254 255 /* OCP_EEE_AR */ 256 /* bit[15:14] function */ 257 #define FUN_ADDR 0x0000 258 #define FUN_DATA 0x4000 259 /* bit[4:0] device addr */ 260 #define DEVICE_ADDR 0x0007 261 262 /* OCP_EEE_DATA */ 263 #define EEE_ADDR 0x003C 264 #define EEE_DATA 0x0002 265 266 enum rtl_register_content { 267 _100bps = 0x08, 268 _10bps = 0x04, 269 LINK_STATUS = 0x02, 270 FULL_DUP = 0x01, 271 }; 272 273 #define RTL8152_MAX_TX 10 274 #define RTL8152_MAX_RX 10 275 #define INTBUFSIZE 2 276 277 #define INTR_LINK 0x0004 278 279 #define RTL8152_REQT_READ 0xc0 280 #define RTL8152_REQT_WRITE 0x40 281 #define RTL8152_REQ_GET_REGS 0x05 282 #define RTL8152_REQ_SET_REGS 0x05 283 284 #define BYTE_EN_DWORD 0xff 285 #define BYTE_EN_WORD 0x33 286 #define BYTE_EN_BYTE 0x11 287 #define BYTE_EN_SIX_BYTES 0x3f 288 #define BYTE_EN_START_MASK 0x0f 289 #define BYTE_EN_END_MASK 0xf0 290 291 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) 292 #define RTL8152_TX_TIMEOUT (HZ) 293 294 /* rtl8152 flags */ 295 enum rtl8152_flags { 296 RTL8152_UNPLUG = 0, 297 RTL8152_SET_RX_MODE, 298 WORK_ENABLE, 299 RTL8152_LINK_CHG, 300 }; 301 302 /* Define these values to match your device */ 303 #define VENDOR_ID_REALTEK 0x0bda 304 #define PRODUCT_ID_RTL8152 0x8152 305 306 #define MCU_TYPE_PLA 0x0100 307 #define MCU_TYPE_USB 0x0000 308 309 struct rx_desc { 310 __le32 opts1; 311 #define RX_LEN_MASK 0x7fff 312 __le32 opts2; 313 __le32 opts3; 314 __le32 opts4; 315 __le32 opts5; 316 __le32 opts6; 317 }; 318 319 struct tx_desc { 320 __le32 opts1; 321 #define TX_FS (1 << 31) /* First segment of a packet */ 322 #define TX_LS (1 << 30) /* Final segment of a packet */ 323 #define TX_LEN_MASK 0x3ffff 324 325 __le32 opts2; 326 #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */ 327 #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */ 328 #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */ 329 #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */ 330 }; 331 332 struct r8152; 333 334 struct rx_agg { 335 struct list_head list; 336 struct urb *urb; 337 struct r8152 *context; 338 void *buffer; 339 void *head; 340 }; 341 342 struct tx_agg { 343 struct list_head list; 344 struct urb *urb; 345 struct r8152 *context; 346 void *buffer; 347 void *head; 348 u32 skb_num; 349 u32 skb_len; 350 }; 351 352 struct r8152 { 353 unsigned long flags; 354 struct usb_device *udev; 355 struct tasklet_struct tl; 356 struct usb_interface *intf; 357 struct net_device *netdev; 358 struct urb *intr_urb; 359 struct tx_agg tx_info[RTL8152_MAX_TX]; 360 struct rx_agg rx_info[RTL8152_MAX_RX]; 361 struct list_head rx_done, tx_free; 362 struct sk_buff_head tx_queue; 363 spinlock_t rx_lock, tx_lock; 364 struct delayed_work schedule; 365 struct mii_if_info mii; 366 int intr_interval; 367 u32 msg_enable; 368 u32 tx_qlen; 369 u16 ocp_base; 370 u8 *intr_buff; 371 u8 version; 372 u8 speed; 373 }; 374 375 enum rtl_version { 376 RTL_VER_UNKNOWN = 0, 377 RTL_VER_01, 378 RTL_VER_02 379 }; 380 381 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 382 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 383 */ 384 static const int multicast_filter_limit = 32; 385 static unsigned int rx_buf_sz = 16384; 386 387 static 388 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 389 { 390 int ret; 391 void *tmp; 392 393 tmp = kmalloc(size, GFP_KERNEL); 394 if (!tmp) 395 return -ENOMEM; 396 397 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 398 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 399 value, index, tmp, size, 500); 400 401 memcpy(data, tmp, size); 402 kfree(tmp); 403 404 return ret; 405 } 406 407 static 408 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 409 { 410 int ret; 411 void *tmp; 412 413 tmp = kmalloc(size, GFP_KERNEL); 414 if (!tmp) 415 return -ENOMEM; 416 417 memcpy(tmp, data, size); 418 419 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 420 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 421 value, index, tmp, size, 500); 422 423 kfree(tmp); 424 return ret; 425 } 426 427 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 428 void *data, u16 type) 429 { 430 u16 limit = 64; 431 int ret = 0; 432 433 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 434 return -ENODEV; 435 436 /* both size and indix must be 4 bytes align */ 437 if ((size & 3) || !size || (index & 3) || !data) 438 return -EPERM; 439 440 if ((u32)index + (u32)size > 0xffff) 441 return -EPERM; 442 443 while (size) { 444 if (size > limit) { 445 ret = get_registers(tp, index, type, limit, data); 446 if (ret < 0) 447 break; 448 449 index += limit; 450 data += limit; 451 size -= limit; 452 } else { 453 ret = get_registers(tp, index, type, size, data); 454 if (ret < 0) 455 break; 456 457 index += size; 458 data += size; 459 size = 0; 460 break; 461 } 462 } 463 464 return ret; 465 } 466 467 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 468 u16 size, void *data, u16 type) 469 { 470 int ret; 471 u16 byteen_start, byteen_end, byen; 472 u16 limit = 512; 473 474 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 475 return -ENODEV; 476 477 /* both size and indix must be 4 bytes align */ 478 if ((size & 3) || !size || (index & 3) || !data) 479 return -EPERM; 480 481 if ((u32)index + (u32)size > 0xffff) 482 return -EPERM; 483 484 byteen_start = byteen & BYTE_EN_START_MASK; 485 byteen_end = byteen & BYTE_EN_END_MASK; 486 487 byen = byteen_start | (byteen_start << 4); 488 ret = set_registers(tp, index, type | byen, 4, data); 489 if (ret < 0) 490 goto error1; 491 492 index += 4; 493 data += 4; 494 size -= 4; 495 496 if (size) { 497 size -= 4; 498 499 while (size) { 500 if (size > limit) { 501 ret = set_registers(tp, index, 502 type | BYTE_EN_DWORD, 503 limit, data); 504 if (ret < 0) 505 goto error1; 506 507 index += limit; 508 data += limit; 509 size -= limit; 510 } else { 511 ret = set_registers(tp, index, 512 type | BYTE_EN_DWORD, 513 size, data); 514 if (ret < 0) 515 goto error1; 516 517 index += size; 518 data += size; 519 size = 0; 520 break; 521 } 522 } 523 524 byen = byteen_end | (byteen_end >> 4); 525 ret = set_registers(tp, index, type | byen, 4, data); 526 if (ret < 0) 527 goto error1; 528 } 529 530 error1: 531 return ret; 532 } 533 534 static inline 535 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 536 { 537 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 538 } 539 540 static inline 541 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 542 { 543 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 544 } 545 546 static inline 547 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 548 { 549 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); 550 } 551 552 static inline 553 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 554 { 555 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 556 } 557 558 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 559 { 560 __le32 data; 561 562 generic_ocp_read(tp, index, sizeof(data), &data, type); 563 564 return __le32_to_cpu(data); 565 } 566 567 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 568 { 569 __le32 tmp = __cpu_to_le32(data); 570 571 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 572 } 573 574 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 575 { 576 u32 data; 577 __le32 tmp; 578 u8 shift = index & 2; 579 580 index &= ~3; 581 582 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 583 584 data = __le32_to_cpu(tmp); 585 data >>= (shift * 8); 586 data &= 0xffff; 587 588 return (u16)data; 589 } 590 591 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 592 { 593 u32 mask = 0xffff; 594 __le32 tmp; 595 u16 byen = BYTE_EN_WORD; 596 u8 shift = index & 2; 597 598 data &= mask; 599 600 if (index & 2) { 601 byen <<= shift; 602 mask <<= (shift * 8); 603 data <<= (shift * 8); 604 index &= ~3; 605 } 606 607 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 608 609 data |= __le32_to_cpu(tmp) & ~mask; 610 tmp = __cpu_to_le32(data); 611 612 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 613 } 614 615 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 616 { 617 u32 data; 618 __le32 tmp; 619 u8 shift = index & 3; 620 621 index &= ~3; 622 623 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 624 625 data = __le32_to_cpu(tmp); 626 data >>= (shift * 8); 627 data &= 0xff; 628 629 return (u8)data; 630 } 631 632 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 633 { 634 u32 mask = 0xff; 635 __le32 tmp; 636 u16 byen = BYTE_EN_BYTE; 637 u8 shift = index & 3; 638 639 data &= mask; 640 641 if (index & 3) { 642 byen <<= shift; 643 mask <<= (shift * 8); 644 data <<= (shift * 8); 645 index &= ~3; 646 } 647 648 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 649 650 data |= __le32_to_cpu(tmp) & ~mask; 651 tmp = __cpu_to_le32(data); 652 653 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 654 } 655 656 static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 657 { 658 u32 ocp_data; 659 int i; 660 661 ocp_data = PHYAR_FLAG | ((reg_addr & 0x1f) << 16) | 662 (value & 0xffff); 663 664 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data); 665 666 for (i = 20; i > 0; i--) { 667 udelay(25); 668 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR); 669 if (!(ocp_data & PHYAR_FLAG)) 670 break; 671 } 672 udelay(20); 673 } 674 675 static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 676 { 677 u32 ocp_data; 678 int i; 679 680 ocp_data = (reg_addr & 0x1f) << 16; 681 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data); 682 683 for (i = 20; i > 0; i--) { 684 udelay(25); 685 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR); 686 if (ocp_data & PHYAR_FLAG) 687 break; 688 } 689 udelay(20); 690 691 if (!(ocp_data & PHYAR_FLAG)) 692 return -EAGAIN; 693 694 return (u16)(ocp_data & 0xffff); 695 } 696 697 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 698 { 699 struct r8152 *tp = netdev_priv(netdev); 700 701 if (phy_id != R8152_PHY_ID) 702 return -EINVAL; 703 704 return r8152_mdio_read(tp, reg); 705 } 706 707 static 708 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 709 { 710 struct r8152 *tp = netdev_priv(netdev); 711 712 if (phy_id != R8152_PHY_ID) 713 return; 714 715 r8152_mdio_write(tp, reg, val); 716 } 717 718 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 719 { 720 u16 ocp_base, ocp_index; 721 722 ocp_base = addr & 0xf000; 723 if (ocp_base != tp->ocp_base) { 724 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 725 tp->ocp_base = ocp_base; 726 } 727 728 ocp_index = (addr & 0x0fff) | 0xb000; 729 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 730 } 731 732 static 733 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 734 735 static inline void set_ethernet_addr(struct r8152 *tp) 736 { 737 struct net_device *dev = tp->netdev; 738 u8 node_id[8] = {0}; 739 740 if (pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id) < 0) 741 netif_notice(tp, probe, dev, "inet addr fail\n"); 742 else { 743 memcpy(dev->dev_addr, node_id, dev->addr_len); 744 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 745 } 746 } 747 748 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 749 { 750 struct r8152 *tp = netdev_priv(netdev); 751 struct sockaddr *addr = p; 752 753 if (!is_valid_ether_addr(addr->sa_data)) 754 return -EADDRNOTAVAIL; 755 756 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 757 758 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 759 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 760 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 761 762 return 0; 763 } 764 765 static struct net_device_stats *rtl8152_get_stats(struct net_device *dev) 766 { 767 return &dev->stats; 768 } 769 770 static void read_bulk_callback(struct urb *urb) 771 { 772 struct net_device *netdev; 773 unsigned long flags; 774 int status = urb->status; 775 struct rx_agg *agg; 776 struct r8152 *tp; 777 int result; 778 779 agg = urb->context; 780 if (!agg) 781 return; 782 783 tp = agg->context; 784 if (!tp) 785 return; 786 787 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 788 return; 789 790 if (!test_bit(WORK_ENABLE, &tp->flags)) 791 return; 792 793 netdev = tp->netdev; 794 795 /* When link down, the driver would cancel all bulks. */ 796 /* This avoid the re-submitting bulk */ 797 if (!netif_carrier_ok(netdev)) 798 return; 799 800 switch (status) { 801 case 0: 802 if (urb->actual_length < ETH_ZLEN) 803 break; 804 805 spin_lock_irqsave(&tp->rx_lock, flags); 806 list_add_tail(&agg->list, &tp->rx_done); 807 spin_unlock_irqrestore(&tp->rx_lock, flags); 808 tasklet_schedule(&tp->tl); 809 return; 810 case -ESHUTDOWN: 811 set_bit(RTL8152_UNPLUG, &tp->flags); 812 netif_device_detach(tp->netdev); 813 return; 814 case -ENOENT: 815 return; /* the urb is in unlink state */ 816 case -ETIME: 817 pr_warn_ratelimited("may be reset is needed?..\n"); 818 break; 819 default: 820 pr_warn_ratelimited("Rx status %d\n", status); 821 break; 822 } 823 824 result = r8152_submit_rx(tp, agg, GFP_ATOMIC); 825 if (result == -ENODEV) { 826 netif_device_detach(tp->netdev); 827 } else if (result) { 828 spin_lock_irqsave(&tp->rx_lock, flags); 829 list_add_tail(&agg->list, &tp->rx_done); 830 spin_unlock_irqrestore(&tp->rx_lock, flags); 831 tasklet_schedule(&tp->tl); 832 } 833 } 834 835 static void write_bulk_callback(struct urb *urb) 836 { 837 struct net_device_stats *stats; 838 unsigned long flags; 839 struct tx_agg *agg; 840 struct r8152 *tp; 841 int status = urb->status; 842 843 agg = urb->context; 844 if (!agg) 845 return; 846 847 tp = agg->context; 848 if (!tp) 849 return; 850 851 stats = rtl8152_get_stats(tp->netdev); 852 if (status) { 853 pr_warn_ratelimited("Tx status %d\n", status); 854 stats->tx_errors += agg->skb_num; 855 } else { 856 stats->tx_packets += agg->skb_num; 857 stats->tx_bytes += agg->skb_len; 858 } 859 860 spin_lock_irqsave(&tp->tx_lock, flags); 861 list_add_tail(&agg->list, &tp->tx_free); 862 spin_unlock_irqrestore(&tp->tx_lock, flags); 863 864 if (!netif_carrier_ok(tp->netdev)) 865 return; 866 867 if (!test_bit(WORK_ENABLE, &tp->flags)) 868 return; 869 870 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 871 return; 872 873 if (!skb_queue_empty(&tp->tx_queue)) 874 tasklet_schedule(&tp->tl); 875 } 876 877 static void intr_callback(struct urb *urb) 878 { 879 struct r8152 *tp; 880 __le16 *d; 881 int status = urb->status; 882 int res; 883 884 tp = urb->context; 885 if (!tp) 886 return; 887 888 if (!test_bit(WORK_ENABLE, &tp->flags)) 889 return; 890 891 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 892 return; 893 894 switch (status) { 895 case 0: /* success */ 896 break; 897 case -ECONNRESET: /* unlink */ 898 case -ESHUTDOWN: 899 netif_device_detach(tp->netdev); 900 case -ENOENT: 901 return; 902 case -EOVERFLOW: 903 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 904 goto resubmit; 905 /* -EPIPE: should clear the halt */ 906 default: 907 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 908 goto resubmit; 909 } 910 911 d = urb->transfer_buffer; 912 if (INTR_LINK & __le16_to_cpu(d[0])) { 913 if (!(tp->speed & LINK_STATUS)) { 914 set_bit(RTL8152_LINK_CHG, &tp->flags); 915 schedule_delayed_work(&tp->schedule, 0); 916 } 917 } else { 918 if (tp->speed & LINK_STATUS) { 919 set_bit(RTL8152_LINK_CHG, &tp->flags); 920 schedule_delayed_work(&tp->schedule, 0); 921 } 922 } 923 924 resubmit: 925 res = usb_submit_urb(urb, GFP_ATOMIC); 926 if (res == -ENODEV) 927 netif_device_detach(tp->netdev); 928 else if (res) 929 netif_err(tp, intr, tp->netdev, 930 "can't resubmit intr, status %d\n", res); 931 } 932 933 static inline void *rx_agg_align(void *data) 934 { 935 return (void *)ALIGN((uintptr_t)data, 8); 936 } 937 938 static inline void *tx_agg_align(void *data) 939 { 940 return (void *)ALIGN((uintptr_t)data, 4); 941 } 942 943 static void free_all_mem(struct r8152 *tp) 944 { 945 int i; 946 947 for (i = 0; i < RTL8152_MAX_RX; i++) { 948 if (tp->rx_info[i].urb) { 949 usb_free_urb(tp->rx_info[i].urb); 950 tp->rx_info[i].urb = NULL; 951 } 952 953 if (tp->rx_info[i].buffer) { 954 kfree(tp->rx_info[i].buffer); 955 tp->rx_info[i].buffer = NULL; 956 tp->rx_info[i].head = NULL; 957 } 958 } 959 960 for (i = 0; i < RTL8152_MAX_TX; i++) { 961 if (tp->tx_info[i].urb) { 962 usb_free_urb(tp->tx_info[i].urb); 963 tp->tx_info[i].urb = NULL; 964 } 965 966 if (tp->tx_info[i].buffer) { 967 kfree(tp->tx_info[i].buffer); 968 tp->tx_info[i].buffer = NULL; 969 tp->tx_info[i].head = NULL; 970 } 971 } 972 973 if (tp->intr_urb) { 974 usb_free_urb(tp->intr_urb); 975 tp->intr_urb = NULL; 976 } 977 978 if (tp->intr_buff) { 979 kfree(tp->intr_buff); 980 tp->intr_buff = NULL; 981 } 982 } 983 984 static int alloc_all_mem(struct r8152 *tp) 985 { 986 struct net_device *netdev = tp->netdev; 987 struct usb_interface *intf = tp->intf; 988 struct usb_host_interface *alt = intf->cur_altsetting; 989 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 990 struct urb *urb; 991 int node, i; 992 u8 *buf; 993 994 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 995 996 spin_lock_init(&tp->rx_lock); 997 spin_lock_init(&tp->tx_lock); 998 INIT_LIST_HEAD(&tp->rx_done); 999 INIT_LIST_HEAD(&tp->tx_free); 1000 skb_queue_head_init(&tp->tx_queue); 1001 1002 for (i = 0; i < RTL8152_MAX_RX; i++) { 1003 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); 1004 if (!buf) 1005 goto err1; 1006 1007 if (buf != rx_agg_align(buf)) { 1008 kfree(buf); 1009 buf = kmalloc_node(rx_buf_sz + 8, GFP_KERNEL, node); 1010 if (!buf) 1011 goto err1; 1012 } 1013 1014 urb = usb_alloc_urb(0, GFP_KERNEL); 1015 if (!urb) { 1016 kfree(buf); 1017 goto err1; 1018 } 1019 1020 INIT_LIST_HEAD(&tp->rx_info[i].list); 1021 tp->rx_info[i].context = tp; 1022 tp->rx_info[i].urb = urb; 1023 tp->rx_info[i].buffer = buf; 1024 tp->rx_info[i].head = rx_agg_align(buf); 1025 } 1026 1027 for (i = 0; i < RTL8152_MAX_TX; i++) { 1028 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); 1029 if (!buf) 1030 goto err1; 1031 1032 if (buf != tx_agg_align(buf)) { 1033 kfree(buf); 1034 buf = kmalloc_node(rx_buf_sz + 4, GFP_KERNEL, node); 1035 if (!buf) 1036 goto err1; 1037 } 1038 1039 urb = usb_alloc_urb(0, GFP_KERNEL); 1040 if (!urb) { 1041 kfree(buf); 1042 goto err1; 1043 } 1044 1045 INIT_LIST_HEAD(&tp->tx_info[i].list); 1046 tp->tx_info[i].context = tp; 1047 tp->tx_info[i].urb = urb; 1048 tp->tx_info[i].buffer = buf; 1049 tp->tx_info[i].head = tx_agg_align(buf); 1050 1051 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1052 } 1053 1054 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1055 if (!tp->intr_urb) 1056 goto err1; 1057 1058 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1059 if (!tp->intr_buff) 1060 goto err1; 1061 1062 tp->intr_interval = (int)ep_intr->desc.bInterval; 1063 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1064 tp->intr_buff, INTBUFSIZE, intr_callback, 1065 tp, tp->intr_interval); 1066 1067 return 0; 1068 1069 err1: 1070 free_all_mem(tp); 1071 return -ENOMEM; 1072 } 1073 1074 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1075 { 1076 struct tx_agg *agg = NULL; 1077 unsigned long flags; 1078 1079 spin_lock_irqsave(&tp->tx_lock, flags); 1080 if (!list_empty(&tp->tx_free)) { 1081 struct list_head *cursor; 1082 1083 cursor = tp->tx_free.next; 1084 list_del_init(cursor); 1085 agg = list_entry(cursor, struct tx_agg, list); 1086 } 1087 spin_unlock_irqrestore(&tp->tx_lock, flags); 1088 1089 return agg; 1090 } 1091 1092 static void 1093 r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb) 1094 { 1095 memset(desc, 0, sizeof(*desc)); 1096 1097 desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS); 1098 1099 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1100 __be16 protocol; 1101 u8 ip_protocol; 1102 u32 opts2 = 0; 1103 1104 if (skb->protocol == htons(ETH_P_8021Q)) 1105 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; 1106 else 1107 protocol = skb->protocol; 1108 1109 switch (protocol) { 1110 case htons(ETH_P_IP): 1111 opts2 |= IPV4_CS; 1112 ip_protocol = ip_hdr(skb)->protocol; 1113 break; 1114 1115 case htons(ETH_P_IPV6): 1116 opts2 |= IPV6_CS; 1117 ip_protocol = ipv6_hdr(skb)->nexthdr; 1118 break; 1119 1120 default: 1121 ip_protocol = IPPROTO_RAW; 1122 break; 1123 } 1124 1125 if (ip_protocol == IPPROTO_TCP) { 1126 opts2 |= TCP_CS; 1127 opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17; 1128 } else if (ip_protocol == IPPROTO_UDP) { 1129 opts2 |= UDP_CS; 1130 } else { 1131 WARN_ON_ONCE(1); 1132 } 1133 1134 desc->opts2 = cpu_to_le32(opts2); 1135 } 1136 } 1137 1138 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1139 { 1140 int remain; 1141 u8 *tx_data; 1142 1143 tx_data = agg->head; 1144 agg->skb_num = agg->skb_len = 0; 1145 remain = rx_buf_sz; 1146 1147 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1148 struct tx_desc *tx_desc; 1149 struct sk_buff *skb; 1150 unsigned int len; 1151 1152 skb = skb_dequeue(&tp->tx_queue); 1153 if (!skb) 1154 break; 1155 1156 remain -= sizeof(*tx_desc); 1157 len = skb->len; 1158 if (remain < len) { 1159 skb_queue_head(&tp->tx_queue, skb); 1160 break; 1161 } 1162 1163 tx_data = tx_agg_align(tx_data); 1164 tx_desc = (struct tx_desc *)tx_data; 1165 tx_data += sizeof(*tx_desc); 1166 1167 r8152_tx_csum(tp, tx_desc, skb); 1168 memcpy(tx_data, skb->data, len); 1169 agg->skb_num++; 1170 agg->skb_len += len; 1171 dev_kfree_skb_any(skb); 1172 1173 tx_data += len; 1174 remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1175 } 1176 1177 netif_tx_lock(tp->netdev); 1178 1179 if (netif_queue_stopped(tp->netdev) && 1180 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1181 netif_wake_queue(tp->netdev); 1182 1183 netif_tx_unlock(tp->netdev); 1184 1185 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1186 agg->head, (int)(tx_data - (u8 *)agg->head), 1187 (usb_complete_t)write_bulk_callback, agg); 1188 1189 return usb_submit_urb(agg->urb, GFP_ATOMIC); 1190 } 1191 1192 static void rx_bottom(struct r8152 *tp) 1193 { 1194 unsigned long flags; 1195 struct list_head *cursor, *next; 1196 1197 spin_lock_irqsave(&tp->rx_lock, flags); 1198 list_for_each_safe(cursor, next, &tp->rx_done) { 1199 struct rx_desc *rx_desc; 1200 struct rx_agg *agg; 1201 int len_used = 0; 1202 struct urb *urb; 1203 u8 *rx_data; 1204 int ret; 1205 1206 list_del_init(cursor); 1207 spin_unlock_irqrestore(&tp->rx_lock, flags); 1208 1209 agg = list_entry(cursor, struct rx_agg, list); 1210 urb = agg->urb; 1211 if (urb->actual_length < ETH_ZLEN) 1212 goto submit; 1213 1214 rx_desc = agg->head; 1215 rx_data = agg->head; 1216 len_used += sizeof(struct rx_desc); 1217 1218 while (urb->actual_length > len_used) { 1219 struct net_device *netdev = tp->netdev; 1220 struct net_device_stats *stats; 1221 unsigned int pkt_len; 1222 struct sk_buff *skb; 1223 1224 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1225 if (pkt_len < ETH_ZLEN) 1226 break; 1227 1228 len_used += pkt_len; 1229 if (urb->actual_length < len_used) 1230 break; 1231 1232 stats = rtl8152_get_stats(netdev); 1233 1234 pkt_len -= 4; /* CRC */ 1235 rx_data += sizeof(struct rx_desc); 1236 1237 skb = netdev_alloc_skb_ip_align(netdev, pkt_len); 1238 if (!skb) { 1239 stats->rx_dropped++; 1240 break; 1241 } 1242 memcpy(skb->data, rx_data, pkt_len); 1243 skb_put(skb, pkt_len); 1244 skb->protocol = eth_type_trans(skb, netdev); 1245 netif_rx(skb); 1246 stats->rx_packets++; 1247 stats->rx_bytes += pkt_len; 1248 1249 rx_data = rx_agg_align(rx_data + pkt_len + 4); 1250 rx_desc = (struct rx_desc *)rx_data; 1251 len_used = (int)(rx_data - (u8 *)agg->head); 1252 len_used += sizeof(struct rx_desc); 1253 } 1254 1255 submit: 1256 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1257 spin_lock_irqsave(&tp->rx_lock, flags); 1258 if (ret && ret != -ENODEV) { 1259 list_add_tail(&agg->list, next); 1260 tasklet_schedule(&tp->tl); 1261 } 1262 } 1263 spin_unlock_irqrestore(&tp->rx_lock, flags); 1264 } 1265 1266 static void tx_bottom(struct r8152 *tp) 1267 { 1268 int res; 1269 1270 do { 1271 struct tx_agg *agg; 1272 1273 if (skb_queue_empty(&tp->tx_queue)) 1274 break; 1275 1276 agg = r8152_get_tx_agg(tp); 1277 if (!agg) 1278 break; 1279 1280 res = r8152_tx_agg_fill(tp, agg); 1281 if (res) { 1282 struct net_device_stats *stats; 1283 struct net_device *netdev; 1284 unsigned long flags; 1285 1286 netdev = tp->netdev; 1287 stats = rtl8152_get_stats(netdev); 1288 1289 if (res == -ENODEV) { 1290 netif_device_detach(netdev); 1291 } else { 1292 netif_warn(tp, tx_err, netdev, 1293 "failed tx_urb %d\n", res); 1294 stats->tx_dropped += agg->skb_num; 1295 spin_lock_irqsave(&tp->tx_lock, flags); 1296 list_add_tail(&agg->list, &tp->tx_free); 1297 spin_unlock_irqrestore(&tp->tx_lock, flags); 1298 } 1299 } 1300 } while (res == 0); 1301 } 1302 1303 static void bottom_half(unsigned long data) 1304 { 1305 struct r8152 *tp; 1306 1307 tp = (struct r8152 *)data; 1308 1309 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1310 return; 1311 1312 if (!test_bit(WORK_ENABLE, &tp->flags)) 1313 return; 1314 1315 /* When link down, the driver would cancel all bulks. */ 1316 /* This avoid the re-submitting bulk */ 1317 if (!netif_carrier_ok(tp->netdev)) 1318 return; 1319 1320 rx_bottom(tp); 1321 tx_bottom(tp); 1322 } 1323 1324 static 1325 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 1326 { 1327 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 1328 agg->head, rx_buf_sz, 1329 (usb_complete_t)read_bulk_callback, agg); 1330 1331 return usb_submit_urb(agg->urb, mem_flags); 1332 } 1333 1334 static void rtl8152_tx_timeout(struct net_device *netdev) 1335 { 1336 struct r8152 *tp = netdev_priv(netdev); 1337 int i; 1338 1339 netif_warn(tp, tx_err, netdev, "Tx timeout.\n"); 1340 for (i = 0; i < RTL8152_MAX_TX; i++) 1341 usb_unlink_urb(tp->tx_info[i].urb); 1342 } 1343 1344 static void rtl8152_set_rx_mode(struct net_device *netdev) 1345 { 1346 struct r8152 *tp = netdev_priv(netdev); 1347 1348 if (tp->speed & LINK_STATUS) { 1349 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 1350 schedule_delayed_work(&tp->schedule, 0); 1351 } 1352 } 1353 1354 static void _rtl8152_set_rx_mode(struct net_device *netdev) 1355 { 1356 struct r8152 *tp = netdev_priv(netdev); 1357 u32 mc_filter[2]; /* Multicast hash filter */ 1358 __le32 tmp[2]; 1359 u32 ocp_data; 1360 1361 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 1362 netif_stop_queue(netdev); 1363 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 1364 ocp_data &= ~RCR_ACPT_ALL; 1365 ocp_data |= RCR_AB | RCR_APM; 1366 1367 if (netdev->flags & IFF_PROMISC) { 1368 /* Unconditionally log net taps. */ 1369 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 1370 ocp_data |= RCR_AM | RCR_AAP; 1371 mc_filter[1] = mc_filter[0] = 0xffffffff; 1372 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 1373 (netdev->flags & IFF_ALLMULTI)) { 1374 /* Too many to filter perfectly -- accept all multicasts. */ 1375 ocp_data |= RCR_AM; 1376 mc_filter[1] = mc_filter[0] = 0xffffffff; 1377 } else { 1378 struct netdev_hw_addr *ha; 1379 1380 mc_filter[1] = mc_filter[0] = 0; 1381 netdev_for_each_mc_addr(ha, netdev) { 1382 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 1383 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 1384 ocp_data |= RCR_AM; 1385 } 1386 } 1387 1388 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 1389 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 1390 1391 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 1392 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 1393 netif_wake_queue(netdev); 1394 } 1395 1396 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 1397 struct net_device *netdev) 1398 { 1399 struct r8152 *tp = netdev_priv(netdev); 1400 1401 skb_tx_timestamp(skb); 1402 1403 skb_queue_tail(&tp->tx_queue, skb); 1404 1405 if (list_empty(&tp->tx_free) && 1406 skb_queue_len(&tp->tx_queue) > tp->tx_qlen) 1407 netif_stop_queue(netdev); 1408 1409 if (!list_empty(&tp->tx_free)) 1410 tasklet_schedule(&tp->tl); 1411 1412 return NETDEV_TX_OK; 1413 } 1414 1415 static void r8152b_reset_packet_filter(struct r8152 *tp) 1416 { 1417 u32 ocp_data; 1418 1419 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 1420 ocp_data &= ~FMC_FCR_MCU_EN; 1421 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 1422 ocp_data |= FMC_FCR_MCU_EN; 1423 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 1424 } 1425 1426 static void rtl8152_nic_reset(struct r8152 *tp) 1427 { 1428 int i; 1429 1430 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 1431 1432 for (i = 0; i < 1000; i++) { 1433 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 1434 break; 1435 udelay(100); 1436 } 1437 } 1438 1439 static void set_tx_qlen(struct r8152 *tp) 1440 { 1441 struct net_device *netdev = tp->netdev; 1442 1443 tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + 1444 sizeof(struct tx_desc)); 1445 } 1446 1447 static inline u8 rtl8152_get_speed(struct r8152 *tp) 1448 { 1449 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 1450 } 1451 1452 static int rtl8152_enable(struct r8152 *tp) 1453 { 1454 u32 ocp_data; 1455 int i, ret; 1456 u8 speed; 1457 1458 set_tx_qlen(tp); 1459 speed = rtl8152_get_speed(tp); 1460 if (speed & _10bps) { 1461 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 1462 ocp_data |= EEEP_CR_EEEP_TX; 1463 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 1464 } else { 1465 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 1466 ocp_data &= ~EEEP_CR_EEEP_TX; 1467 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 1468 } 1469 1470 r8152b_reset_packet_filter(tp); 1471 1472 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 1473 ocp_data |= CR_RE | CR_TE; 1474 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 1475 1476 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 1477 ocp_data &= ~RXDY_GATED_EN; 1478 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 1479 1480 INIT_LIST_HEAD(&tp->rx_done); 1481 ret = 0; 1482 for (i = 0; i < RTL8152_MAX_RX; i++) { 1483 INIT_LIST_HEAD(&tp->rx_info[i].list); 1484 ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 1485 } 1486 1487 return ret; 1488 } 1489 1490 static void rtl8152_disable(struct r8152 *tp) 1491 { 1492 struct net_device_stats *stats = rtl8152_get_stats(tp->netdev); 1493 struct sk_buff *skb; 1494 u32 ocp_data; 1495 int i; 1496 1497 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 1498 ocp_data &= ~RCR_ACPT_ALL; 1499 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 1500 1501 while ((skb = skb_dequeue(&tp->tx_queue))) { 1502 dev_kfree_skb(skb); 1503 stats->tx_dropped++; 1504 } 1505 1506 for (i = 0; i < RTL8152_MAX_TX; i++) 1507 usb_kill_urb(tp->tx_info[i].urb); 1508 1509 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 1510 ocp_data |= RXDY_GATED_EN; 1511 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 1512 1513 for (i = 0; i < 1000; i++) { 1514 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 1515 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 1516 break; 1517 mdelay(1); 1518 } 1519 1520 for (i = 0; i < 1000; i++) { 1521 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 1522 break; 1523 mdelay(1); 1524 } 1525 1526 for (i = 0; i < RTL8152_MAX_RX; i++) 1527 usb_kill_urb(tp->rx_info[i].urb); 1528 1529 rtl8152_nic_reset(tp); 1530 } 1531 1532 static void r8152b_exit_oob(struct r8152 *tp) 1533 { 1534 u32 ocp_data; 1535 int i; 1536 1537 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 1538 ocp_data &= ~RCR_ACPT_ALL; 1539 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 1540 1541 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 1542 ocp_data |= RXDY_GATED_EN; 1543 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 1544 1545 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1546 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 1547 1548 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 1549 ocp_data &= ~NOW_IS_OOB; 1550 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 1551 1552 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 1553 ocp_data &= ~MCU_BORW_EN; 1554 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 1555 1556 for (i = 0; i < 1000; i++) { 1557 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 1558 if (ocp_data & LINK_LIST_READY) 1559 break; 1560 mdelay(1); 1561 } 1562 1563 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 1564 ocp_data |= RE_INIT_LL; 1565 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 1566 1567 for (i = 0; i < 1000; i++) { 1568 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 1569 if (ocp_data & LINK_LIST_READY) 1570 break; 1571 mdelay(1); 1572 } 1573 1574 rtl8152_nic_reset(tp); 1575 1576 /* rx share fifo credit full threshold */ 1577 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 1578 1579 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT); 1580 ocp_data &= STAT_SPEED_MASK; 1581 if (ocp_data == STAT_SPEED_FULL) { 1582 /* rx share fifo credit near full threshold */ 1583 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 1584 RXFIFO_THR2_FULL); 1585 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 1586 RXFIFO_THR3_FULL); 1587 } else { 1588 /* rx share fifo credit near full threshold */ 1589 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 1590 RXFIFO_THR2_HIGH); 1591 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 1592 RXFIFO_THR3_HIGH); 1593 } 1594 1595 /* TX share fifo free credit full threshold */ 1596 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 1597 1598 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 1599 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_BUF_THR); 1600 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 1601 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 1602 1603 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 1604 ocp_data &= ~CPCR_RX_VLAN; 1605 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 1606 1607 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 1608 1609 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 1610 ocp_data |= TCR0_AUTO_FIFO; 1611 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 1612 } 1613 1614 static void r8152b_enter_oob(struct r8152 *tp) 1615 { 1616 u32 ocp_data; 1617 int i; 1618 1619 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 1620 ocp_data &= ~NOW_IS_OOB; 1621 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 1622 1623 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 1624 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 1625 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 1626 1627 rtl8152_disable(tp); 1628 1629 for (i = 0; i < 1000; i++) { 1630 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 1631 if (ocp_data & LINK_LIST_READY) 1632 break; 1633 mdelay(1); 1634 } 1635 1636 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 1637 ocp_data |= RE_INIT_LL; 1638 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 1639 1640 for (i = 0; i < 1000; i++) { 1641 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 1642 if (ocp_data & LINK_LIST_READY) 1643 break; 1644 mdelay(1); 1645 } 1646 1647 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 1648 1649 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 1650 ocp_data |= MAGIC_EN; 1651 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 1652 1653 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 1654 ocp_data |= CPCR_RX_VLAN; 1655 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 1656 1657 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 1658 ocp_data |= ALDPS_PROXY_MODE; 1659 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 1660 1661 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 1662 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 1663 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 1664 1665 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN); 1666 1667 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 1668 ocp_data &= ~RXDY_GATED_EN; 1669 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 1670 1671 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 1672 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 1673 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 1674 } 1675 1676 static void r8152b_disable_aldps(struct r8152 *tp) 1677 { 1678 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); 1679 msleep(20); 1680 } 1681 1682 static inline void r8152b_enable_aldps(struct r8152 *tp) 1683 { 1684 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 1685 LINKENA | DIS_SDSAVE); 1686 } 1687 1688 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 1689 { 1690 u16 bmcr, anar; 1691 int ret = 0; 1692 1693 cancel_delayed_work_sync(&tp->schedule); 1694 anar = r8152_mdio_read(tp, MII_ADVERTISE); 1695 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 1696 ADVERTISE_100HALF | ADVERTISE_100FULL); 1697 1698 if (autoneg == AUTONEG_DISABLE) { 1699 if (speed == SPEED_10) { 1700 bmcr = 0; 1701 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 1702 } else if (speed == SPEED_100) { 1703 bmcr = BMCR_SPEED100; 1704 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 1705 } else { 1706 ret = -EINVAL; 1707 goto out; 1708 } 1709 1710 if (duplex == DUPLEX_FULL) 1711 bmcr |= BMCR_FULLDPLX; 1712 } else { 1713 if (speed == SPEED_10) { 1714 if (duplex == DUPLEX_FULL) 1715 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 1716 else 1717 anar |= ADVERTISE_10HALF; 1718 } else if (speed == SPEED_100) { 1719 if (duplex == DUPLEX_FULL) { 1720 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 1721 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 1722 } else { 1723 anar |= ADVERTISE_10HALF; 1724 anar |= ADVERTISE_100HALF; 1725 } 1726 } else { 1727 ret = -EINVAL; 1728 goto out; 1729 } 1730 1731 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 1732 } 1733 1734 r8152_mdio_write(tp, MII_ADVERTISE, anar); 1735 r8152_mdio_write(tp, MII_BMCR, bmcr); 1736 1737 out: 1738 1739 return ret; 1740 } 1741 1742 static void rtl8152_down(struct r8152 *tp) 1743 { 1744 u32 ocp_data; 1745 1746 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 1747 ocp_data &= ~POWER_CUT; 1748 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 1749 1750 r8152b_disable_aldps(tp); 1751 r8152b_enter_oob(tp); 1752 r8152b_enable_aldps(tp); 1753 } 1754 1755 static void set_carrier(struct r8152 *tp) 1756 { 1757 struct net_device *netdev = tp->netdev; 1758 u8 speed; 1759 1760 clear_bit(RTL8152_LINK_CHG, &tp->flags); 1761 speed = rtl8152_get_speed(tp); 1762 1763 if (speed & LINK_STATUS) { 1764 if (!(tp->speed & LINK_STATUS)) { 1765 rtl8152_enable(tp); 1766 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 1767 netif_carrier_on(netdev); 1768 } 1769 } else { 1770 if (tp->speed & LINK_STATUS) { 1771 netif_carrier_off(netdev); 1772 tasklet_disable(&tp->tl); 1773 rtl8152_disable(tp); 1774 tasklet_enable(&tp->tl); 1775 } 1776 } 1777 tp->speed = speed; 1778 } 1779 1780 static void rtl_work_func_t(struct work_struct *work) 1781 { 1782 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 1783 1784 if (!test_bit(WORK_ENABLE, &tp->flags)) 1785 goto out1; 1786 1787 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1788 goto out1; 1789 1790 if (test_bit(RTL8152_LINK_CHG, &tp->flags)) 1791 set_carrier(tp); 1792 1793 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) 1794 _rtl8152_set_rx_mode(tp->netdev); 1795 1796 out1: 1797 return; 1798 } 1799 1800 static int rtl8152_open(struct net_device *netdev) 1801 { 1802 struct r8152 *tp = netdev_priv(netdev); 1803 int res = 0; 1804 1805 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 1806 if (res) { 1807 if (res == -ENODEV) 1808 netif_device_detach(tp->netdev); 1809 netif_warn(tp, ifup, netdev, 1810 "intr_urb submit failed: %d\n", res); 1811 return res; 1812 } 1813 1814 rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL); 1815 tp->speed = 0; 1816 netif_carrier_off(netdev); 1817 netif_start_queue(netdev); 1818 set_bit(WORK_ENABLE, &tp->flags); 1819 1820 return res; 1821 } 1822 1823 static int rtl8152_close(struct net_device *netdev) 1824 { 1825 struct r8152 *tp = netdev_priv(netdev); 1826 int res = 0; 1827 1828 usb_kill_urb(tp->intr_urb); 1829 clear_bit(WORK_ENABLE, &tp->flags); 1830 cancel_delayed_work_sync(&tp->schedule); 1831 netif_stop_queue(netdev); 1832 tasklet_disable(&tp->tl); 1833 rtl8152_disable(tp); 1834 tasklet_enable(&tp->tl); 1835 1836 return res; 1837 } 1838 1839 static void rtl_clear_bp(struct r8152 *tp) 1840 { 1841 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0); 1842 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0); 1843 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0); 1844 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0); 1845 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0); 1846 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0); 1847 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0); 1848 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0); 1849 mdelay(3); 1850 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0); 1851 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0); 1852 } 1853 1854 static void r8152b_enable_eee(struct r8152 *tp) 1855 { 1856 u32 ocp_data; 1857 1858 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 1859 ocp_data |= EEE_RX_EN | EEE_TX_EN; 1860 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 1861 ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN | 1862 EEE_10_CAP | EEE_NWAY_EN | 1863 TX_QUIET_EN | RX_QUIET_EN | 1864 SDRISETIME | RG_RXLPI_MSK_HFDUP | 1865 SDFALLTIME); 1866 ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN | 1867 RG_LDVQUIET_EN | RG_CKRSEL | 1868 RG_EEEPRG_EN); 1869 ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH); 1870 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR); 1871 ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR); 1872 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR); 1873 ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA); 1874 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 1875 } 1876 1877 static void r8152b_enable_fc(struct r8152 *tp) 1878 { 1879 u16 anar; 1880 1881 anar = r8152_mdio_read(tp, MII_ADVERTISE); 1882 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 1883 r8152_mdio_write(tp, MII_ADVERTISE, anar); 1884 } 1885 1886 static void r8152b_hw_phy_cfg(struct r8152 *tp) 1887 { 1888 r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE); 1889 r8152b_disable_aldps(tp); 1890 } 1891 1892 static void r8152b_init(struct r8152 *tp) 1893 { 1894 u32 ocp_data; 1895 int i; 1896 1897 rtl_clear_bp(tp); 1898 1899 if (tp->version == RTL_VER_01) { 1900 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 1901 ocp_data &= ~LED_MODE_MASK; 1902 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 1903 } 1904 1905 r8152b_hw_phy_cfg(tp); 1906 1907 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 1908 ocp_data &= ~POWER_CUT; 1909 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 1910 1911 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 1912 ocp_data &= ~RWSUME_INDICATE; 1913 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 1914 1915 r8152b_exit_oob(tp); 1916 1917 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 1918 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 1919 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 1920 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 1921 ocp_data &= ~MCU_CLK_RATIO_MASK; 1922 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 1923 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 1924 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 1925 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 1926 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 1927 1928 r8152b_enable_eee(tp); 1929 r8152b_enable_aldps(tp); 1930 r8152b_enable_fc(tp); 1931 1932 r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | 1933 BMCR_ANRESTART); 1934 for (i = 0; i < 100; i++) { 1935 udelay(100); 1936 if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET)) 1937 break; 1938 } 1939 1940 /* enable rx aggregation */ 1941 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 1942 ocp_data &= ~RX_AGG_DISABLE; 1943 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 1944 } 1945 1946 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 1947 { 1948 struct r8152 *tp = usb_get_intfdata(intf); 1949 1950 netif_device_detach(tp->netdev); 1951 1952 if (netif_running(tp->netdev)) { 1953 clear_bit(WORK_ENABLE, &tp->flags); 1954 usb_kill_urb(tp->intr_urb); 1955 cancel_delayed_work_sync(&tp->schedule); 1956 tasklet_disable(&tp->tl); 1957 } 1958 1959 rtl8152_down(tp); 1960 1961 return 0; 1962 } 1963 1964 static int rtl8152_resume(struct usb_interface *intf) 1965 { 1966 struct r8152 *tp = usb_get_intfdata(intf); 1967 1968 r8152b_init(tp); 1969 netif_device_attach(tp->netdev); 1970 if (netif_running(tp->netdev)) { 1971 rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL); 1972 tp->speed = 0; 1973 netif_carrier_off(tp->netdev); 1974 set_bit(WORK_ENABLE, &tp->flags); 1975 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 1976 tasklet_enable(&tp->tl); 1977 } 1978 1979 return 0; 1980 } 1981 1982 static void rtl8152_get_drvinfo(struct net_device *netdev, 1983 struct ethtool_drvinfo *info) 1984 { 1985 struct r8152 *tp = netdev_priv(netdev); 1986 1987 strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN); 1988 strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN); 1989 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 1990 } 1991 1992 static 1993 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) 1994 { 1995 struct r8152 *tp = netdev_priv(netdev); 1996 1997 if (!tp->mii.mdio_read) 1998 return -EOPNOTSUPP; 1999 2000 return mii_ethtool_gset(&tp->mii, cmd); 2001 } 2002 2003 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2004 { 2005 struct r8152 *tp = netdev_priv(dev); 2006 2007 return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); 2008 } 2009 2010 static struct ethtool_ops ops = { 2011 .get_drvinfo = rtl8152_get_drvinfo, 2012 .get_settings = rtl8152_get_settings, 2013 .set_settings = rtl8152_set_settings, 2014 .get_link = ethtool_op_get_link, 2015 }; 2016 2017 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 2018 { 2019 struct r8152 *tp = netdev_priv(netdev); 2020 struct mii_ioctl_data *data = if_mii(rq); 2021 int res = 0; 2022 2023 switch (cmd) { 2024 case SIOCGMIIPHY: 2025 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 2026 break; 2027 2028 case SIOCGMIIREG: 2029 data->val_out = r8152_mdio_read(tp, data->reg_num); 2030 break; 2031 2032 case SIOCSMIIREG: 2033 if (!capable(CAP_NET_ADMIN)) { 2034 res = -EPERM; 2035 break; 2036 } 2037 r8152_mdio_write(tp, data->reg_num, data->val_in); 2038 break; 2039 2040 default: 2041 res = -EOPNOTSUPP; 2042 } 2043 2044 return res; 2045 } 2046 2047 static const struct net_device_ops rtl8152_netdev_ops = { 2048 .ndo_open = rtl8152_open, 2049 .ndo_stop = rtl8152_close, 2050 .ndo_do_ioctl = rtl8152_ioctl, 2051 .ndo_start_xmit = rtl8152_start_xmit, 2052 .ndo_tx_timeout = rtl8152_tx_timeout, 2053 .ndo_set_rx_mode = rtl8152_set_rx_mode, 2054 .ndo_set_mac_address = rtl8152_set_mac_address, 2055 2056 .ndo_change_mtu = eth_change_mtu, 2057 .ndo_validate_addr = eth_validate_addr, 2058 }; 2059 2060 static void r8152b_get_version(struct r8152 *tp) 2061 { 2062 u32 ocp_data; 2063 u16 version; 2064 2065 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); 2066 version = (u16)(ocp_data & VERSION_MASK); 2067 2068 switch (version) { 2069 case 0x4c00: 2070 tp->version = RTL_VER_01; 2071 break; 2072 case 0x4c10: 2073 tp->version = RTL_VER_02; 2074 break; 2075 default: 2076 netif_info(tp, probe, tp->netdev, 2077 "Unknown version 0x%04x\n", version); 2078 break; 2079 } 2080 } 2081 2082 static int rtl8152_probe(struct usb_interface *intf, 2083 const struct usb_device_id *id) 2084 { 2085 struct usb_device *udev = interface_to_usbdev(intf); 2086 struct r8152 *tp; 2087 struct net_device *netdev; 2088 int ret; 2089 2090 if (udev->actconfig->desc.bConfigurationValue != 1) { 2091 usb_driver_set_configuration(udev, 1); 2092 return -ENODEV; 2093 } 2094 2095 netdev = alloc_etherdev(sizeof(struct r8152)); 2096 if (!netdev) { 2097 dev_err(&intf->dev, "Out of memory"); 2098 return -ENOMEM; 2099 } 2100 2101 SET_NETDEV_DEV(netdev, &intf->dev); 2102 tp = netdev_priv(netdev); 2103 tp->msg_enable = 0x7FFF; 2104 2105 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp); 2106 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 2107 2108 tp->udev = udev; 2109 tp->netdev = netdev; 2110 tp->intf = intf; 2111 netdev->netdev_ops = &rtl8152_netdev_ops; 2112 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 2113 2114 netdev->features |= NETIF_F_IP_CSUM; 2115 netdev->hw_features = NETIF_F_IP_CSUM; 2116 SET_ETHTOOL_OPS(netdev, &ops); 2117 2118 tp->mii.dev = netdev; 2119 tp->mii.mdio_read = read_mii_word; 2120 tp->mii.mdio_write = write_mii_word; 2121 tp->mii.phy_id_mask = 0x3f; 2122 tp->mii.reg_num_mask = 0x1f; 2123 tp->mii.phy_id = R8152_PHY_ID; 2124 tp->mii.supports_gmii = 0; 2125 2126 r8152b_get_version(tp); 2127 r8152b_init(tp); 2128 set_ethernet_addr(tp); 2129 2130 ret = alloc_all_mem(tp); 2131 if (ret) 2132 goto out; 2133 2134 usb_set_intfdata(intf, tp); 2135 2136 ret = register_netdev(netdev); 2137 if (ret != 0) { 2138 netif_err(tp, probe, netdev, "couldn't register the device"); 2139 goto out1; 2140 } 2141 2142 netif_info(tp, probe, netdev, "%s", DRIVER_VERSION); 2143 2144 return 0; 2145 2146 out1: 2147 usb_set_intfdata(intf, NULL); 2148 out: 2149 free_netdev(netdev); 2150 return ret; 2151 } 2152 2153 static void rtl8152_unload(struct r8152 *tp) 2154 { 2155 u32 ocp_data; 2156 2157 if (tp->version != RTL_VER_01) { 2158 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2159 ocp_data |= POWER_CUT; 2160 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2161 } 2162 2163 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2164 ocp_data &= ~RWSUME_INDICATE; 2165 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2166 } 2167 2168 static void rtl8152_disconnect(struct usb_interface *intf) 2169 { 2170 struct r8152 *tp = usb_get_intfdata(intf); 2171 2172 usb_set_intfdata(intf, NULL); 2173 if (tp) { 2174 set_bit(RTL8152_UNPLUG, &tp->flags); 2175 tasklet_kill(&tp->tl); 2176 unregister_netdev(tp->netdev); 2177 rtl8152_unload(tp); 2178 free_all_mem(tp); 2179 free_netdev(tp->netdev); 2180 } 2181 } 2182 2183 /* table of devices that work with this driver */ 2184 static struct usb_device_id rtl8152_table[] = { 2185 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)}, 2186 {} 2187 }; 2188 2189 MODULE_DEVICE_TABLE(usb, rtl8152_table); 2190 2191 static struct usb_driver rtl8152_driver = { 2192 .name = MODULENAME, 2193 .id_table = rtl8152_table, 2194 .probe = rtl8152_probe, 2195 .disconnect = rtl8152_disconnect, 2196 .suspend = rtl8152_suspend, 2197 .resume = rtl8152_resume, 2198 .reset_resume = rtl8152_resume, 2199 }; 2200 2201 module_usb_driver(rtl8152_driver); 2202 2203 MODULE_AUTHOR(DRIVER_AUTHOR); 2204 MODULE_DESCRIPTION(DRIVER_DESC); 2205 MODULE_LICENSE("GPL"); 2206