1 /* 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2 as published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/signal.h> 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/usb.h> 18 #include <linux/crc32.h> 19 #include <linux/if_vlan.h> 20 #include <linux/uaccess.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include <net/ip6_checksum.h> 25 #include <uapi/linux/mdio.h> 26 #include <linux/mdio.h> 27 #include <linux/usb/cdc.h> 28 #include <linux/suspend.h> 29 30 /* Information for net-next */ 31 #define NETNEXT_VERSION "08" 32 33 /* Information for net */ 34 #define NET_VERSION "4" 35 36 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION 37 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 38 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 39 #define MODULENAME "r8152" 40 41 #define R8152_PHY_ID 32 42 43 #define PLA_IDR 0xc000 44 #define PLA_RCR 0xc010 45 #define PLA_RMS 0xc016 46 #define PLA_RXFIFO_CTRL0 0xc0a0 47 #define PLA_RXFIFO_CTRL1 0xc0a4 48 #define PLA_RXFIFO_CTRL2 0xc0a8 49 #define PLA_DMY_REG0 0xc0b0 50 #define PLA_FMC 0xc0b4 51 #define PLA_CFG_WOL 0xc0b6 52 #define PLA_TEREDO_CFG 0xc0bc 53 #define PLA_MAR 0xcd00 54 #define PLA_BACKUP 0xd000 55 #define PAL_BDC_CR 0xd1a0 56 #define PLA_TEREDO_TIMER 0xd2cc 57 #define PLA_REALWOW_TIMER 0xd2e8 58 #define PLA_LEDSEL 0xdd90 59 #define PLA_LED_FEATURE 0xdd92 60 #define PLA_PHYAR 0xde00 61 #define PLA_BOOT_CTRL 0xe004 62 #define PLA_GPHY_INTR_IMR 0xe022 63 #define PLA_EEE_CR 0xe040 64 #define PLA_EEEP_CR 0xe080 65 #define PLA_MAC_PWR_CTRL 0xe0c0 66 #define PLA_MAC_PWR_CTRL2 0xe0ca 67 #define PLA_MAC_PWR_CTRL3 0xe0cc 68 #define PLA_MAC_PWR_CTRL4 0xe0ce 69 #define PLA_WDT6_CTRL 0xe428 70 #define PLA_TCR0 0xe610 71 #define PLA_TCR1 0xe612 72 #define PLA_MTPS 0xe615 73 #define PLA_TXFIFO_CTRL 0xe618 74 #define PLA_RSTTALLY 0xe800 75 #define PLA_CR 0xe813 76 #define PLA_CRWECR 0xe81c 77 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 78 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 79 #define PLA_CONFIG5 0xe822 80 #define PLA_PHY_PWR 0xe84c 81 #define PLA_OOB_CTRL 0xe84f 82 #define PLA_CPCR 0xe854 83 #define PLA_MISC_0 0xe858 84 #define PLA_MISC_1 0xe85a 85 #define PLA_OCP_GPHY_BASE 0xe86c 86 #define PLA_TALLYCNT 0xe890 87 #define PLA_SFF_STS_7 0xe8de 88 #define PLA_PHYSTATUS 0xe908 89 #define PLA_BP_BA 0xfc26 90 #define PLA_BP_0 0xfc28 91 #define PLA_BP_1 0xfc2a 92 #define PLA_BP_2 0xfc2c 93 #define PLA_BP_3 0xfc2e 94 #define PLA_BP_4 0xfc30 95 #define PLA_BP_5 0xfc32 96 #define PLA_BP_6 0xfc34 97 #define PLA_BP_7 0xfc36 98 #define PLA_BP_EN 0xfc38 99 100 #define USB_USB2PHY 0xb41e 101 #define USB_SSPHYLINK2 0xb428 102 #define USB_U2P3_CTRL 0xb460 103 #define USB_CSR_DUMMY1 0xb464 104 #define USB_CSR_DUMMY2 0xb466 105 #define USB_DEV_STAT 0xb808 106 #define USB_CONNECT_TIMER 0xcbf8 107 #define USB_BURST_SIZE 0xcfc0 108 #define USB_USB_CTRL 0xd406 109 #define USB_PHY_CTRL 0xd408 110 #define USB_TX_AGG 0xd40a 111 #define USB_RX_BUF_TH 0xd40c 112 #define USB_USB_TIMER 0xd428 113 #define USB_RX_EARLY_TIMEOUT 0xd42c 114 #define USB_RX_EARLY_SIZE 0xd42e 115 #define USB_PM_CTRL_STATUS 0xd432 116 #define USB_TX_DMA 0xd434 117 #define USB_TOLERANCE 0xd490 118 #define USB_LPM_CTRL 0xd41a 119 #define USB_BMU_RESET 0xd4b0 120 #define USB_UPS_CTRL 0xd800 121 #define USB_MISC_0 0xd81a 122 #define USB_POWER_CUT 0xd80a 123 #define USB_AFE_CTRL2 0xd824 124 #define USB_WDT11_CTRL 0xe43c 125 #define USB_BP_BA 0xfc26 126 #define USB_BP_0 0xfc28 127 #define USB_BP_1 0xfc2a 128 #define USB_BP_2 0xfc2c 129 #define USB_BP_3 0xfc2e 130 #define USB_BP_4 0xfc30 131 #define USB_BP_5 0xfc32 132 #define USB_BP_6 0xfc34 133 #define USB_BP_7 0xfc36 134 #define USB_BP_EN 0xfc38 135 136 /* OCP Registers */ 137 #define OCP_ALDPS_CONFIG 0x2010 138 #define OCP_EEE_CONFIG1 0x2080 139 #define OCP_EEE_CONFIG2 0x2092 140 #define OCP_EEE_CONFIG3 0x2094 141 #define OCP_BASE_MII 0xa400 142 #define OCP_EEE_AR 0xa41a 143 #define OCP_EEE_DATA 0xa41c 144 #define OCP_PHY_STATUS 0xa420 145 #define OCP_POWER_CFG 0xa430 146 #define OCP_EEE_CFG 0xa432 147 #define OCP_SRAM_ADDR 0xa436 148 #define OCP_SRAM_DATA 0xa438 149 #define OCP_DOWN_SPEED 0xa442 150 #define OCP_EEE_ABLE 0xa5c4 151 #define OCP_EEE_ADV 0xa5d0 152 #define OCP_EEE_LPABLE 0xa5d2 153 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ 154 #define OCP_ADC_CFG 0xbc06 155 156 /* SRAM Register */ 157 #define SRAM_LPF_CFG 0x8012 158 #define SRAM_10M_AMP1 0x8080 159 #define SRAM_10M_AMP2 0x8082 160 #define SRAM_IMPEDANCE 0x8084 161 162 /* PLA_RCR */ 163 #define RCR_AAP 0x00000001 164 #define RCR_APM 0x00000002 165 #define RCR_AM 0x00000004 166 #define RCR_AB 0x00000008 167 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 168 169 /* PLA_RXFIFO_CTRL0 */ 170 #define RXFIFO_THR1_NORMAL 0x00080002 171 #define RXFIFO_THR1_OOB 0x01800003 172 173 /* PLA_RXFIFO_CTRL1 */ 174 #define RXFIFO_THR2_FULL 0x00000060 175 #define RXFIFO_THR2_HIGH 0x00000038 176 #define RXFIFO_THR2_OOB 0x0000004a 177 #define RXFIFO_THR2_NORMAL 0x00a0 178 179 /* PLA_RXFIFO_CTRL2 */ 180 #define RXFIFO_THR3_FULL 0x00000078 181 #define RXFIFO_THR3_HIGH 0x00000048 182 #define RXFIFO_THR3_OOB 0x0000005a 183 #define RXFIFO_THR3_NORMAL 0x0110 184 185 /* PLA_TXFIFO_CTRL */ 186 #define TXFIFO_THR_NORMAL 0x00400008 187 #define TXFIFO_THR_NORMAL2 0x01000008 188 189 /* PLA_DMY_REG0 */ 190 #define ECM_ALDPS 0x0002 191 192 /* PLA_FMC */ 193 #define FMC_FCR_MCU_EN 0x0001 194 195 /* PLA_EEEP_CR */ 196 #define EEEP_CR_EEEP_TX 0x0002 197 198 /* PLA_WDT6_CTRL */ 199 #define WDT6_SET_MODE 0x0010 200 201 /* PLA_TCR0 */ 202 #define TCR0_TX_EMPTY 0x0800 203 #define TCR0_AUTO_FIFO 0x0080 204 205 /* PLA_TCR1 */ 206 #define VERSION_MASK 0x7cf0 207 208 /* PLA_MTPS */ 209 #define MTPS_JUMBO (12 * 1024 / 64) 210 #define MTPS_DEFAULT (6 * 1024 / 64) 211 212 /* PLA_RSTTALLY */ 213 #define TALLY_RESET 0x0001 214 215 /* PLA_CR */ 216 #define CR_RST 0x10 217 #define CR_RE 0x08 218 #define CR_TE 0x04 219 220 /* PLA_CRWECR */ 221 #define CRWECR_NORAML 0x00 222 #define CRWECR_CONFIG 0xc0 223 224 /* PLA_OOB_CTRL */ 225 #define NOW_IS_OOB 0x80 226 #define TXFIFO_EMPTY 0x20 227 #define RXFIFO_EMPTY 0x10 228 #define LINK_LIST_READY 0x02 229 #define DIS_MCU_CLROOB 0x01 230 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 231 232 /* PLA_MISC_1 */ 233 #define RXDY_GATED_EN 0x0008 234 235 /* PLA_SFF_STS_7 */ 236 #define RE_INIT_LL 0x8000 237 #define MCU_BORW_EN 0x4000 238 239 /* PLA_CPCR */ 240 #define CPCR_RX_VLAN 0x0040 241 242 /* PLA_CFG_WOL */ 243 #define MAGIC_EN 0x0001 244 245 /* PLA_TEREDO_CFG */ 246 #define TEREDO_SEL 0x8000 247 #define TEREDO_WAKE_MASK 0x7f00 248 #define TEREDO_RS_EVENT_MASK 0x00fe 249 #define OOB_TEREDO_EN 0x0001 250 251 /* PAL_BDC_CR */ 252 #define ALDPS_PROXY_MODE 0x0001 253 254 /* PLA_CONFIG34 */ 255 #define LINK_ON_WAKE_EN 0x0010 256 #define LINK_OFF_WAKE_EN 0x0008 257 258 /* PLA_CONFIG5 */ 259 #define BWF_EN 0x0040 260 #define MWF_EN 0x0020 261 #define UWF_EN 0x0010 262 #define LAN_WAKE_EN 0x0002 263 264 /* PLA_LED_FEATURE */ 265 #define LED_MODE_MASK 0x0700 266 267 /* PLA_PHY_PWR */ 268 #define TX_10M_IDLE_EN 0x0080 269 #define PFM_PWM_SWITCH 0x0040 270 271 /* PLA_MAC_PWR_CTRL */ 272 #define D3_CLK_GATED_EN 0x00004000 273 #define MCU_CLK_RATIO 0x07010f07 274 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 275 #define ALDPS_SPDWN_RATIO 0x0f87 276 277 /* PLA_MAC_PWR_CTRL2 */ 278 #define EEE_SPDWN_RATIO 0x8007 279 280 /* PLA_MAC_PWR_CTRL3 */ 281 #define PKT_AVAIL_SPDWN_EN 0x0100 282 #define SUSPEND_SPDWN_EN 0x0004 283 #define U1U2_SPDWN_EN 0x0002 284 #define L1_SPDWN_EN 0x0001 285 286 /* PLA_MAC_PWR_CTRL4 */ 287 #define PWRSAVE_SPDWN_EN 0x1000 288 #define RXDV_SPDWN_EN 0x0800 289 #define TX10MIDLE_EN 0x0100 290 #define TP100_SPDWN_EN 0x0020 291 #define TP500_SPDWN_EN 0x0010 292 #define TP1000_SPDWN_EN 0x0008 293 #define EEE_SPDWN_EN 0x0001 294 295 /* PLA_GPHY_INTR_IMR */ 296 #define GPHY_STS_MSK 0x0001 297 #define SPEED_DOWN_MSK 0x0002 298 #define SPDWN_RXDV_MSK 0x0004 299 #define SPDWN_LINKCHG_MSK 0x0008 300 301 /* PLA_PHYAR */ 302 #define PHYAR_FLAG 0x80000000 303 304 /* PLA_EEE_CR */ 305 #define EEE_RX_EN 0x0001 306 #define EEE_TX_EN 0x0002 307 308 /* PLA_BOOT_CTRL */ 309 #define AUTOLOAD_DONE 0x0002 310 311 /* USB_USB2PHY */ 312 #define USB2PHY_SUSPEND 0x0001 313 #define USB2PHY_L1 0x0002 314 315 /* USB_SSPHYLINK2 */ 316 #define pwd_dn_scale_mask 0x3ffe 317 #define pwd_dn_scale(x) ((x) << 1) 318 319 /* USB_CSR_DUMMY1 */ 320 #define DYNAMIC_BURST 0x0001 321 322 /* USB_CSR_DUMMY2 */ 323 #define EP4_FULL_FC 0x0001 324 325 /* USB_DEV_STAT */ 326 #define STAT_SPEED_MASK 0x0006 327 #define STAT_SPEED_HIGH 0x0000 328 #define STAT_SPEED_FULL 0x0002 329 330 /* USB_TX_AGG */ 331 #define TX_AGG_MAX_THRESHOLD 0x03 332 333 /* USB_RX_BUF_TH */ 334 #define RX_THR_SUPPER 0x0c350180 335 #define RX_THR_HIGH 0x7a120180 336 #define RX_THR_SLOW 0xffff0180 337 338 /* USB_TX_DMA */ 339 #define TEST_MODE_DISABLE 0x00000001 340 #define TX_SIZE_ADJUST1 0x00000100 341 342 /* USB_BMU_RESET */ 343 #define BMU_RESET_EP_IN 0x01 344 #define BMU_RESET_EP_OUT 0x02 345 346 /* USB_UPS_CTRL */ 347 #define POWER_CUT 0x0100 348 349 /* USB_PM_CTRL_STATUS */ 350 #define RESUME_INDICATE 0x0001 351 352 /* USB_USB_CTRL */ 353 #define RX_AGG_DISABLE 0x0010 354 #define RX_ZERO_EN 0x0080 355 356 /* USB_U2P3_CTRL */ 357 #define U2P3_ENABLE 0x0001 358 359 /* USB_POWER_CUT */ 360 #define PWR_EN 0x0001 361 #define PHASE2_EN 0x0008 362 363 /* USB_MISC_0 */ 364 #define PCUT_STATUS 0x0001 365 366 /* USB_RX_EARLY_TIMEOUT */ 367 #define COALESCE_SUPER 85000U 368 #define COALESCE_HIGH 250000U 369 #define COALESCE_SLOW 524280U 370 371 /* USB_WDT11_CTRL */ 372 #define TIMER11_EN 0x0001 373 374 /* USB_LPM_CTRL */ 375 /* bit 4 ~ 5: fifo empty boundary */ 376 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 377 /* bit 2 ~ 3: LMP timer */ 378 #define LPM_TIMER_MASK 0x0c 379 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 380 #define LPM_TIMER_500US 0x0c /* 500 us */ 381 #define ROK_EXIT_LPM 0x02 382 383 /* USB_AFE_CTRL2 */ 384 #define SEN_VAL_MASK 0xf800 385 #define SEN_VAL_NORMAL 0xa000 386 #define SEL_RXIDLE 0x0100 387 388 /* OCP_ALDPS_CONFIG */ 389 #define ENPWRSAVE 0x8000 390 #define ENPDNPS 0x0200 391 #define LINKENA 0x0100 392 #define DIS_SDSAVE 0x0010 393 394 /* OCP_PHY_STATUS */ 395 #define PHY_STAT_MASK 0x0007 396 #define PHY_STAT_LAN_ON 3 397 #define PHY_STAT_PWRDN 5 398 399 /* OCP_POWER_CFG */ 400 #define EEE_CLKDIV_EN 0x8000 401 #define EN_ALDPS 0x0004 402 #define EN_10M_PLLOFF 0x0001 403 404 /* OCP_EEE_CONFIG1 */ 405 #define RG_TXLPI_MSK_HFDUP 0x8000 406 #define RG_MATCLR_EN 0x4000 407 #define EEE_10_CAP 0x2000 408 #define EEE_NWAY_EN 0x1000 409 #define TX_QUIET_EN 0x0200 410 #define RX_QUIET_EN 0x0100 411 #define sd_rise_time_mask 0x0070 412 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 413 #define RG_RXLPI_MSK_HFDUP 0x0008 414 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 415 416 /* OCP_EEE_CONFIG2 */ 417 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 418 #define RG_DACQUIET_EN 0x0400 419 #define RG_LDVQUIET_EN 0x0200 420 #define RG_CKRSEL 0x0020 421 #define RG_EEEPRG_EN 0x0010 422 423 /* OCP_EEE_CONFIG3 */ 424 #define fast_snr_mask 0xff80 425 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 426 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 427 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 428 429 /* OCP_EEE_AR */ 430 /* bit[15:14] function */ 431 #define FUN_ADDR 0x0000 432 #define FUN_DATA 0x4000 433 /* bit[4:0] device addr */ 434 435 /* OCP_EEE_CFG */ 436 #define CTAP_SHORT_EN 0x0040 437 #define EEE10_EN 0x0010 438 439 /* OCP_DOWN_SPEED */ 440 #define EN_10M_BGOFF 0x0080 441 442 /* OCP_PHY_STATE */ 443 #define TXDIS_STATE 0x01 444 #define ABD_STATE 0x02 445 446 /* OCP_ADC_CFG */ 447 #define CKADSEL_L 0x0100 448 #define ADC_EN 0x0080 449 #define EN_EMI_L 0x0040 450 451 /* SRAM_LPF_CFG */ 452 #define LPF_AUTO_TUNE 0x8000 453 454 /* SRAM_10M_AMP1 */ 455 #define GDAC_IB_UPALL 0x0008 456 457 /* SRAM_10M_AMP2 */ 458 #define AMP_DN 0x0200 459 460 /* SRAM_IMPEDANCE */ 461 #define RX_DRIVING_MASK 0x6000 462 463 enum rtl_register_content { 464 _1000bps = 0x10, 465 _100bps = 0x08, 466 _10bps = 0x04, 467 LINK_STATUS = 0x02, 468 FULL_DUP = 0x01, 469 }; 470 471 #define RTL8152_MAX_TX 4 472 #define RTL8152_MAX_RX 10 473 #define INTBUFSIZE 2 474 #define CRC_SIZE 4 475 #define TX_ALIGN 4 476 #define RX_ALIGN 8 477 478 #define INTR_LINK 0x0004 479 480 #define RTL8152_REQT_READ 0xc0 481 #define RTL8152_REQT_WRITE 0x40 482 #define RTL8152_REQ_GET_REGS 0x05 483 #define RTL8152_REQ_SET_REGS 0x05 484 485 #define BYTE_EN_DWORD 0xff 486 #define BYTE_EN_WORD 0x33 487 #define BYTE_EN_BYTE 0x11 488 #define BYTE_EN_SIX_BYTES 0x3f 489 #define BYTE_EN_START_MASK 0x0f 490 #define BYTE_EN_END_MASK 0xf0 491 492 #define RTL8153_MAX_PACKET 9216 /* 9K */ 493 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN) 494 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) 495 #define RTL8153_RMS RTL8153_MAX_PACKET 496 #define RTL8152_TX_TIMEOUT (5 * HZ) 497 #define RTL8152_NAPI_WEIGHT 64 498 499 /* rtl8152 flags */ 500 enum rtl8152_flags { 501 RTL8152_UNPLUG = 0, 502 RTL8152_SET_RX_MODE, 503 WORK_ENABLE, 504 RTL8152_LINK_CHG, 505 SELECTIVE_SUSPEND, 506 PHY_RESET, 507 SCHEDULE_NAPI, 508 }; 509 510 /* Define these values to match your device */ 511 #define VENDOR_ID_REALTEK 0x0bda 512 #define VENDOR_ID_SAMSUNG 0x04e8 513 #define VENDOR_ID_LENOVO 0x17ef 514 #define VENDOR_ID_NVIDIA 0x0955 515 516 #define MCU_TYPE_PLA 0x0100 517 #define MCU_TYPE_USB 0x0000 518 519 struct tally_counter { 520 __le64 tx_packets; 521 __le64 rx_packets; 522 __le64 tx_errors; 523 __le32 rx_errors; 524 __le16 rx_missed; 525 __le16 align_errors; 526 __le32 tx_one_collision; 527 __le32 tx_multi_collision; 528 __le64 rx_unicast; 529 __le64 rx_broadcast; 530 __le32 rx_multicast; 531 __le16 tx_aborted; 532 __le16 tx_underrun; 533 }; 534 535 struct rx_desc { 536 __le32 opts1; 537 #define RX_LEN_MASK 0x7fff 538 539 __le32 opts2; 540 #define RD_UDP_CS BIT(23) 541 #define RD_TCP_CS BIT(22) 542 #define RD_IPV6_CS BIT(20) 543 #define RD_IPV4_CS BIT(19) 544 545 __le32 opts3; 546 #define IPF BIT(23) /* IP checksum fail */ 547 #define UDPF BIT(22) /* UDP checksum fail */ 548 #define TCPF BIT(21) /* TCP checksum fail */ 549 #define RX_VLAN_TAG BIT(16) 550 551 __le32 opts4; 552 __le32 opts5; 553 __le32 opts6; 554 }; 555 556 struct tx_desc { 557 __le32 opts1; 558 #define TX_FS BIT(31) /* First segment of a packet */ 559 #define TX_LS BIT(30) /* Final segment of a packet */ 560 #define GTSENDV4 BIT(28) 561 #define GTSENDV6 BIT(27) 562 #define GTTCPHO_SHIFT 18 563 #define GTTCPHO_MAX 0x7fU 564 #define TX_LEN_MAX 0x3ffffU 565 566 __le32 opts2; 567 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 568 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 569 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 570 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 571 #define MSS_SHIFT 17 572 #define MSS_MAX 0x7ffU 573 #define TCPHO_SHIFT 17 574 #define TCPHO_MAX 0x7ffU 575 #define TX_VLAN_TAG BIT(16) 576 }; 577 578 struct r8152; 579 580 struct rx_agg { 581 struct list_head list; 582 struct urb *urb; 583 struct r8152 *context; 584 void *buffer; 585 void *head; 586 }; 587 588 struct tx_agg { 589 struct list_head list; 590 struct urb *urb; 591 struct r8152 *context; 592 void *buffer; 593 void *head; 594 u32 skb_num; 595 u32 skb_len; 596 }; 597 598 struct r8152 { 599 unsigned long flags; 600 struct usb_device *udev; 601 struct napi_struct napi; 602 struct usb_interface *intf; 603 struct net_device *netdev; 604 struct urb *intr_urb; 605 struct tx_agg tx_info[RTL8152_MAX_TX]; 606 struct rx_agg rx_info[RTL8152_MAX_RX]; 607 struct list_head rx_done, tx_free; 608 struct sk_buff_head tx_queue, rx_queue; 609 spinlock_t rx_lock, tx_lock; 610 struct delayed_work schedule; 611 struct mii_if_info mii; 612 struct mutex control; /* use for hw setting */ 613 #ifdef CONFIG_PM_SLEEP 614 struct notifier_block pm_notifier; 615 #endif 616 617 struct rtl_ops { 618 void (*init)(struct r8152 *); 619 int (*enable)(struct r8152 *); 620 void (*disable)(struct r8152 *); 621 void (*up)(struct r8152 *); 622 void (*down)(struct r8152 *); 623 void (*unload)(struct r8152 *); 624 int (*eee_get)(struct r8152 *, struct ethtool_eee *); 625 int (*eee_set)(struct r8152 *, struct ethtool_eee *); 626 bool (*in_nway)(struct r8152 *); 627 } rtl_ops; 628 629 int intr_interval; 630 u32 saved_wolopts; 631 u32 msg_enable; 632 u32 tx_qlen; 633 u32 coalesce; 634 u16 ocp_base; 635 u8 *intr_buff; 636 u8 version; 637 }; 638 639 enum rtl_version { 640 RTL_VER_UNKNOWN = 0, 641 RTL_VER_01, 642 RTL_VER_02, 643 RTL_VER_03, 644 RTL_VER_04, 645 RTL_VER_05, 646 RTL_VER_06, 647 RTL_VER_MAX 648 }; 649 650 enum tx_csum_stat { 651 TX_CSUM_SUCCESS = 0, 652 TX_CSUM_TSO, 653 TX_CSUM_NONE 654 }; 655 656 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 657 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 658 */ 659 static const int multicast_filter_limit = 32; 660 static unsigned int agg_buf_sz = 16384; 661 662 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ 663 VLAN_ETH_HLEN - VLAN_HLEN) 664 665 static 666 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 667 { 668 int ret; 669 void *tmp; 670 671 tmp = kmalloc(size, GFP_KERNEL); 672 if (!tmp) 673 return -ENOMEM; 674 675 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 676 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 677 value, index, tmp, size, 500); 678 679 memcpy(data, tmp, size); 680 kfree(tmp); 681 682 return ret; 683 } 684 685 static 686 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 687 { 688 int ret; 689 void *tmp; 690 691 tmp = kmemdup(data, size, GFP_KERNEL); 692 if (!tmp) 693 return -ENOMEM; 694 695 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 696 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 697 value, index, tmp, size, 500); 698 699 kfree(tmp); 700 701 return ret; 702 } 703 704 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 705 void *data, u16 type) 706 { 707 u16 limit = 64; 708 int ret = 0; 709 710 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 711 return -ENODEV; 712 713 /* both size and indix must be 4 bytes align */ 714 if ((size & 3) || !size || (index & 3) || !data) 715 return -EPERM; 716 717 if ((u32)index + (u32)size > 0xffff) 718 return -EPERM; 719 720 while (size) { 721 if (size > limit) { 722 ret = get_registers(tp, index, type, limit, data); 723 if (ret < 0) 724 break; 725 726 index += limit; 727 data += limit; 728 size -= limit; 729 } else { 730 ret = get_registers(tp, index, type, size, data); 731 if (ret < 0) 732 break; 733 734 index += size; 735 data += size; 736 size = 0; 737 break; 738 } 739 } 740 741 if (ret == -ENODEV) 742 set_bit(RTL8152_UNPLUG, &tp->flags); 743 744 return ret; 745 } 746 747 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 748 u16 size, void *data, u16 type) 749 { 750 int ret; 751 u16 byteen_start, byteen_end, byen; 752 u16 limit = 512; 753 754 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 755 return -ENODEV; 756 757 /* both size and indix must be 4 bytes align */ 758 if ((size & 3) || !size || (index & 3) || !data) 759 return -EPERM; 760 761 if ((u32)index + (u32)size > 0xffff) 762 return -EPERM; 763 764 byteen_start = byteen & BYTE_EN_START_MASK; 765 byteen_end = byteen & BYTE_EN_END_MASK; 766 767 byen = byteen_start | (byteen_start << 4); 768 ret = set_registers(tp, index, type | byen, 4, data); 769 if (ret < 0) 770 goto error1; 771 772 index += 4; 773 data += 4; 774 size -= 4; 775 776 if (size) { 777 size -= 4; 778 779 while (size) { 780 if (size > limit) { 781 ret = set_registers(tp, index, 782 type | BYTE_EN_DWORD, 783 limit, data); 784 if (ret < 0) 785 goto error1; 786 787 index += limit; 788 data += limit; 789 size -= limit; 790 } else { 791 ret = set_registers(tp, index, 792 type | BYTE_EN_DWORD, 793 size, data); 794 if (ret < 0) 795 goto error1; 796 797 index += size; 798 data += size; 799 size = 0; 800 break; 801 } 802 } 803 804 byen = byteen_end | (byteen_end >> 4); 805 ret = set_registers(tp, index, type | byen, 4, data); 806 if (ret < 0) 807 goto error1; 808 } 809 810 error1: 811 if (ret == -ENODEV) 812 set_bit(RTL8152_UNPLUG, &tp->flags); 813 814 return ret; 815 } 816 817 static inline 818 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 819 { 820 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 821 } 822 823 static inline 824 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 825 { 826 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 827 } 828 829 static inline 830 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 831 { 832 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); 833 } 834 835 static inline 836 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 837 { 838 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 839 } 840 841 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 842 { 843 __le32 data; 844 845 generic_ocp_read(tp, index, sizeof(data), &data, type); 846 847 return __le32_to_cpu(data); 848 } 849 850 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 851 { 852 __le32 tmp = __cpu_to_le32(data); 853 854 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 855 } 856 857 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 858 { 859 u32 data; 860 __le32 tmp; 861 u8 shift = index & 2; 862 863 index &= ~3; 864 865 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 866 867 data = __le32_to_cpu(tmp); 868 data >>= (shift * 8); 869 data &= 0xffff; 870 871 return (u16)data; 872 } 873 874 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 875 { 876 u32 mask = 0xffff; 877 __le32 tmp; 878 u16 byen = BYTE_EN_WORD; 879 u8 shift = index & 2; 880 881 data &= mask; 882 883 if (index & 2) { 884 byen <<= shift; 885 mask <<= (shift * 8); 886 data <<= (shift * 8); 887 index &= ~3; 888 } 889 890 tmp = __cpu_to_le32(data); 891 892 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 893 } 894 895 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 896 { 897 u32 data; 898 __le32 tmp; 899 u8 shift = index & 3; 900 901 index &= ~3; 902 903 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 904 905 data = __le32_to_cpu(tmp); 906 data >>= (shift * 8); 907 data &= 0xff; 908 909 return (u8)data; 910 } 911 912 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 913 { 914 u32 mask = 0xff; 915 __le32 tmp; 916 u16 byen = BYTE_EN_BYTE; 917 u8 shift = index & 3; 918 919 data &= mask; 920 921 if (index & 3) { 922 byen <<= shift; 923 mask <<= (shift * 8); 924 data <<= (shift * 8); 925 index &= ~3; 926 } 927 928 tmp = __cpu_to_le32(data); 929 930 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 931 } 932 933 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 934 { 935 u16 ocp_base, ocp_index; 936 937 ocp_base = addr & 0xf000; 938 if (ocp_base != tp->ocp_base) { 939 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 940 tp->ocp_base = ocp_base; 941 } 942 943 ocp_index = (addr & 0x0fff) | 0xb000; 944 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 945 } 946 947 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 948 { 949 u16 ocp_base, ocp_index; 950 951 ocp_base = addr & 0xf000; 952 if (ocp_base != tp->ocp_base) { 953 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 954 tp->ocp_base = ocp_base; 955 } 956 957 ocp_index = (addr & 0x0fff) | 0xb000; 958 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 959 } 960 961 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 962 { 963 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 964 } 965 966 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 967 { 968 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 969 } 970 971 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 972 { 973 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 974 ocp_reg_write(tp, OCP_SRAM_DATA, data); 975 } 976 977 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 978 { 979 struct r8152 *tp = netdev_priv(netdev); 980 int ret; 981 982 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 983 return -ENODEV; 984 985 if (phy_id != R8152_PHY_ID) 986 return -EINVAL; 987 988 ret = r8152_mdio_read(tp, reg); 989 990 return ret; 991 } 992 993 static 994 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 995 { 996 struct r8152 *tp = netdev_priv(netdev); 997 998 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 999 return; 1000 1001 if (phy_id != R8152_PHY_ID) 1002 return; 1003 1004 r8152_mdio_write(tp, reg, val); 1005 } 1006 1007 static int 1008 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 1009 1010 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1011 { 1012 struct r8152 *tp = netdev_priv(netdev); 1013 struct sockaddr *addr = p; 1014 int ret = -EADDRNOTAVAIL; 1015 1016 if (!is_valid_ether_addr(addr->sa_data)) 1017 goto out1; 1018 1019 ret = usb_autopm_get_interface(tp->intf); 1020 if (ret < 0) 1021 goto out1; 1022 1023 mutex_lock(&tp->control); 1024 1025 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1026 1027 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1028 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1029 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1030 1031 mutex_unlock(&tp->control); 1032 1033 usb_autopm_put_interface(tp->intf); 1034 out1: 1035 return ret; 1036 } 1037 1038 static int set_ethernet_addr(struct r8152 *tp) 1039 { 1040 struct net_device *dev = tp->netdev; 1041 struct sockaddr sa; 1042 int ret; 1043 1044 if (tp->version == RTL_VER_01) 1045 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); 1046 else 1047 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); 1048 1049 if (ret < 0) { 1050 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1051 } else if (!is_valid_ether_addr(sa.sa_data)) { 1052 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1053 sa.sa_data); 1054 eth_hw_addr_random(dev); 1055 ether_addr_copy(sa.sa_data, dev->dev_addr); 1056 ret = rtl8152_set_mac_address(dev, &sa); 1057 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1058 sa.sa_data); 1059 } else { 1060 if (tp->version == RTL_VER_01) 1061 ether_addr_copy(dev->dev_addr, sa.sa_data); 1062 else 1063 ret = rtl8152_set_mac_address(dev, &sa); 1064 } 1065 1066 return ret; 1067 } 1068 1069 static void read_bulk_callback(struct urb *urb) 1070 { 1071 struct net_device *netdev; 1072 int status = urb->status; 1073 struct rx_agg *agg; 1074 struct r8152 *tp; 1075 1076 agg = urb->context; 1077 if (!agg) 1078 return; 1079 1080 tp = agg->context; 1081 if (!tp) 1082 return; 1083 1084 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1085 return; 1086 1087 if (!test_bit(WORK_ENABLE, &tp->flags)) 1088 return; 1089 1090 netdev = tp->netdev; 1091 1092 /* When link down, the driver would cancel all bulks. */ 1093 /* This avoid the re-submitting bulk */ 1094 if (!netif_carrier_ok(netdev)) 1095 return; 1096 1097 usb_mark_last_busy(tp->udev); 1098 1099 switch (status) { 1100 case 0: 1101 if (urb->actual_length < ETH_ZLEN) 1102 break; 1103 1104 spin_lock(&tp->rx_lock); 1105 list_add_tail(&agg->list, &tp->rx_done); 1106 spin_unlock(&tp->rx_lock); 1107 napi_schedule(&tp->napi); 1108 return; 1109 case -ESHUTDOWN: 1110 set_bit(RTL8152_UNPLUG, &tp->flags); 1111 netif_device_detach(tp->netdev); 1112 return; 1113 case -ENOENT: 1114 return; /* the urb is in unlink state */ 1115 case -ETIME: 1116 if (net_ratelimit()) 1117 netdev_warn(netdev, "maybe reset is needed?\n"); 1118 break; 1119 default: 1120 if (net_ratelimit()) 1121 netdev_warn(netdev, "Rx status %d\n", status); 1122 break; 1123 } 1124 1125 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1126 } 1127 1128 static void write_bulk_callback(struct urb *urb) 1129 { 1130 struct net_device_stats *stats; 1131 struct net_device *netdev; 1132 struct tx_agg *agg; 1133 struct r8152 *tp; 1134 int status = urb->status; 1135 1136 agg = urb->context; 1137 if (!agg) 1138 return; 1139 1140 tp = agg->context; 1141 if (!tp) 1142 return; 1143 1144 netdev = tp->netdev; 1145 stats = &netdev->stats; 1146 if (status) { 1147 if (net_ratelimit()) 1148 netdev_warn(netdev, "Tx status %d\n", status); 1149 stats->tx_errors += agg->skb_num; 1150 } else { 1151 stats->tx_packets += agg->skb_num; 1152 stats->tx_bytes += agg->skb_len; 1153 } 1154 1155 spin_lock(&tp->tx_lock); 1156 list_add_tail(&agg->list, &tp->tx_free); 1157 spin_unlock(&tp->tx_lock); 1158 1159 usb_autopm_put_interface_async(tp->intf); 1160 1161 if (!netif_carrier_ok(netdev)) 1162 return; 1163 1164 if (!test_bit(WORK_ENABLE, &tp->flags)) 1165 return; 1166 1167 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1168 return; 1169 1170 if (!skb_queue_empty(&tp->tx_queue)) 1171 napi_schedule(&tp->napi); 1172 } 1173 1174 static void intr_callback(struct urb *urb) 1175 { 1176 struct r8152 *tp; 1177 __le16 *d; 1178 int status = urb->status; 1179 int res; 1180 1181 tp = urb->context; 1182 if (!tp) 1183 return; 1184 1185 if (!test_bit(WORK_ENABLE, &tp->flags)) 1186 return; 1187 1188 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1189 return; 1190 1191 switch (status) { 1192 case 0: /* success */ 1193 break; 1194 case -ECONNRESET: /* unlink */ 1195 case -ESHUTDOWN: 1196 netif_device_detach(tp->netdev); 1197 case -ENOENT: 1198 case -EPROTO: 1199 netif_info(tp, intr, tp->netdev, 1200 "Stop submitting intr, status %d\n", status); 1201 return; 1202 case -EOVERFLOW: 1203 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1204 goto resubmit; 1205 /* -EPIPE: should clear the halt */ 1206 default: 1207 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1208 goto resubmit; 1209 } 1210 1211 d = urb->transfer_buffer; 1212 if (INTR_LINK & __le16_to_cpu(d[0])) { 1213 if (!netif_carrier_ok(tp->netdev)) { 1214 set_bit(RTL8152_LINK_CHG, &tp->flags); 1215 schedule_delayed_work(&tp->schedule, 0); 1216 } 1217 } else { 1218 if (netif_carrier_ok(tp->netdev)) { 1219 set_bit(RTL8152_LINK_CHG, &tp->flags); 1220 schedule_delayed_work(&tp->schedule, 0); 1221 } 1222 } 1223 1224 resubmit: 1225 res = usb_submit_urb(urb, GFP_ATOMIC); 1226 if (res == -ENODEV) { 1227 set_bit(RTL8152_UNPLUG, &tp->flags); 1228 netif_device_detach(tp->netdev); 1229 } else if (res) { 1230 netif_err(tp, intr, tp->netdev, 1231 "can't resubmit intr, status %d\n", res); 1232 } 1233 } 1234 1235 static inline void *rx_agg_align(void *data) 1236 { 1237 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1238 } 1239 1240 static inline void *tx_agg_align(void *data) 1241 { 1242 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1243 } 1244 1245 static void free_all_mem(struct r8152 *tp) 1246 { 1247 int i; 1248 1249 for (i = 0; i < RTL8152_MAX_RX; i++) { 1250 usb_free_urb(tp->rx_info[i].urb); 1251 tp->rx_info[i].urb = NULL; 1252 1253 kfree(tp->rx_info[i].buffer); 1254 tp->rx_info[i].buffer = NULL; 1255 tp->rx_info[i].head = NULL; 1256 } 1257 1258 for (i = 0; i < RTL8152_MAX_TX; i++) { 1259 usb_free_urb(tp->tx_info[i].urb); 1260 tp->tx_info[i].urb = NULL; 1261 1262 kfree(tp->tx_info[i].buffer); 1263 tp->tx_info[i].buffer = NULL; 1264 tp->tx_info[i].head = NULL; 1265 } 1266 1267 usb_free_urb(tp->intr_urb); 1268 tp->intr_urb = NULL; 1269 1270 kfree(tp->intr_buff); 1271 tp->intr_buff = NULL; 1272 } 1273 1274 static int alloc_all_mem(struct r8152 *tp) 1275 { 1276 struct net_device *netdev = tp->netdev; 1277 struct usb_interface *intf = tp->intf; 1278 struct usb_host_interface *alt = intf->cur_altsetting; 1279 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1280 struct urb *urb; 1281 int node, i; 1282 u8 *buf; 1283 1284 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1285 1286 spin_lock_init(&tp->rx_lock); 1287 spin_lock_init(&tp->tx_lock); 1288 INIT_LIST_HEAD(&tp->tx_free); 1289 skb_queue_head_init(&tp->tx_queue); 1290 skb_queue_head_init(&tp->rx_queue); 1291 1292 for (i = 0; i < RTL8152_MAX_RX; i++) { 1293 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1294 if (!buf) 1295 goto err1; 1296 1297 if (buf != rx_agg_align(buf)) { 1298 kfree(buf); 1299 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, 1300 node); 1301 if (!buf) 1302 goto err1; 1303 } 1304 1305 urb = usb_alloc_urb(0, GFP_KERNEL); 1306 if (!urb) { 1307 kfree(buf); 1308 goto err1; 1309 } 1310 1311 INIT_LIST_HEAD(&tp->rx_info[i].list); 1312 tp->rx_info[i].context = tp; 1313 tp->rx_info[i].urb = urb; 1314 tp->rx_info[i].buffer = buf; 1315 tp->rx_info[i].head = rx_agg_align(buf); 1316 } 1317 1318 for (i = 0; i < RTL8152_MAX_TX; i++) { 1319 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1320 if (!buf) 1321 goto err1; 1322 1323 if (buf != tx_agg_align(buf)) { 1324 kfree(buf); 1325 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 1326 node); 1327 if (!buf) 1328 goto err1; 1329 } 1330 1331 urb = usb_alloc_urb(0, GFP_KERNEL); 1332 if (!urb) { 1333 kfree(buf); 1334 goto err1; 1335 } 1336 1337 INIT_LIST_HEAD(&tp->tx_info[i].list); 1338 tp->tx_info[i].context = tp; 1339 tp->tx_info[i].urb = urb; 1340 tp->tx_info[i].buffer = buf; 1341 tp->tx_info[i].head = tx_agg_align(buf); 1342 1343 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1344 } 1345 1346 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1347 if (!tp->intr_urb) 1348 goto err1; 1349 1350 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1351 if (!tp->intr_buff) 1352 goto err1; 1353 1354 tp->intr_interval = (int)ep_intr->desc.bInterval; 1355 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1356 tp->intr_buff, INTBUFSIZE, intr_callback, 1357 tp, tp->intr_interval); 1358 1359 return 0; 1360 1361 err1: 1362 free_all_mem(tp); 1363 return -ENOMEM; 1364 } 1365 1366 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1367 { 1368 struct tx_agg *agg = NULL; 1369 unsigned long flags; 1370 1371 if (list_empty(&tp->tx_free)) 1372 return NULL; 1373 1374 spin_lock_irqsave(&tp->tx_lock, flags); 1375 if (!list_empty(&tp->tx_free)) { 1376 struct list_head *cursor; 1377 1378 cursor = tp->tx_free.next; 1379 list_del_init(cursor); 1380 agg = list_entry(cursor, struct tx_agg, list); 1381 } 1382 spin_unlock_irqrestore(&tp->tx_lock, flags); 1383 1384 return agg; 1385 } 1386 1387 /* r8152_csum_workaround() 1388 * The hw limites the value the transport offset. When the offset is out of the 1389 * range, calculate the checksum by sw. 1390 */ 1391 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1392 struct sk_buff_head *list) 1393 { 1394 if (skb_shinfo(skb)->gso_size) { 1395 netdev_features_t features = tp->netdev->features; 1396 struct sk_buff_head seg_list; 1397 struct sk_buff *segs, *nskb; 1398 1399 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 1400 segs = skb_gso_segment(skb, features); 1401 if (IS_ERR(segs) || !segs) 1402 goto drop; 1403 1404 __skb_queue_head_init(&seg_list); 1405 1406 do { 1407 nskb = segs; 1408 segs = segs->next; 1409 nskb->next = NULL; 1410 __skb_queue_tail(&seg_list, nskb); 1411 } while (segs); 1412 1413 skb_queue_splice(&seg_list, list); 1414 dev_kfree_skb(skb); 1415 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1416 if (skb_checksum_help(skb) < 0) 1417 goto drop; 1418 1419 __skb_queue_head(list, skb); 1420 } else { 1421 struct net_device_stats *stats; 1422 1423 drop: 1424 stats = &tp->netdev->stats; 1425 stats->tx_dropped++; 1426 dev_kfree_skb(skb); 1427 } 1428 } 1429 1430 /* msdn_giant_send_check() 1431 * According to the document of microsoft, the TCP Pseudo Header excludes the 1432 * packet length for IPv6 TCP large packets. 1433 */ 1434 static int msdn_giant_send_check(struct sk_buff *skb) 1435 { 1436 const struct ipv6hdr *ipv6h; 1437 struct tcphdr *th; 1438 int ret; 1439 1440 ret = skb_cow_head(skb, 0); 1441 if (ret) 1442 return ret; 1443 1444 ipv6h = ipv6_hdr(skb); 1445 th = tcp_hdr(skb); 1446 1447 th->check = 0; 1448 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1449 1450 return ret; 1451 } 1452 1453 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 1454 { 1455 if (skb_vlan_tag_present(skb)) { 1456 u32 opts2; 1457 1458 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); 1459 desc->opts2 |= cpu_to_le32(opts2); 1460 } 1461 } 1462 1463 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 1464 { 1465 u32 opts2 = le32_to_cpu(desc->opts2); 1466 1467 if (opts2 & RX_VLAN_TAG) 1468 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1469 swab16(opts2 & 0xffff)); 1470 } 1471 1472 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1473 struct sk_buff *skb, u32 len, u32 transport_offset) 1474 { 1475 u32 mss = skb_shinfo(skb)->gso_size; 1476 u32 opts1, opts2 = 0; 1477 int ret = TX_CSUM_SUCCESS; 1478 1479 WARN_ON_ONCE(len > TX_LEN_MAX); 1480 1481 opts1 = len | TX_FS | TX_LS; 1482 1483 if (mss) { 1484 if (transport_offset > GTTCPHO_MAX) { 1485 netif_warn(tp, tx_err, tp->netdev, 1486 "Invalid transport offset 0x%x for TSO\n", 1487 transport_offset); 1488 ret = TX_CSUM_TSO; 1489 goto unavailable; 1490 } 1491 1492 switch (vlan_get_protocol(skb)) { 1493 case htons(ETH_P_IP): 1494 opts1 |= GTSENDV4; 1495 break; 1496 1497 case htons(ETH_P_IPV6): 1498 if (msdn_giant_send_check(skb)) { 1499 ret = TX_CSUM_TSO; 1500 goto unavailable; 1501 } 1502 opts1 |= GTSENDV6; 1503 break; 1504 1505 default: 1506 WARN_ON_ONCE(1); 1507 break; 1508 } 1509 1510 opts1 |= transport_offset << GTTCPHO_SHIFT; 1511 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1512 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1513 u8 ip_protocol; 1514 1515 if (transport_offset > TCPHO_MAX) { 1516 netif_warn(tp, tx_err, tp->netdev, 1517 "Invalid transport offset 0x%x\n", 1518 transport_offset); 1519 ret = TX_CSUM_NONE; 1520 goto unavailable; 1521 } 1522 1523 switch (vlan_get_protocol(skb)) { 1524 case htons(ETH_P_IP): 1525 opts2 |= IPV4_CS; 1526 ip_protocol = ip_hdr(skb)->protocol; 1527 break; 1528 1529 case htons(ETH_P_IPV6): 1530 opts2 |= IPV6_CS; 1531 ip_protocol = ipv6_hdr(skb)->nexthdr; 1532 break; 1533 1534 default: 1535 ip_protocol = IPPROTO_RAW; 1536 break; 1537 } 1538 1539 if (ip_protocol == IPPROTO_TCP) 1540 opts2 |= TCP_CS; 1541 else if (ip_protocol == IPPROTO_UDP) 1542 opts2 |= UDP_CS; 1543 else 1544 WARN_ON_ONCE(1); 1545 1546 opts2 |= transport_offset << TCPHO_SHIFT; 1547 } 1548 1549 desc->opts2 = cpu_to_le32(opts2); 1550 desc->opts1 = cpu_to_le32(opts1); 1551 1552 unavailable: 1553 return ret; 1554 } 1555 1556 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1557 { 1558 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1559 int remain, ret; 1560 u8 *tx_data; 1561 1562 __skb_queue_head_init(&skb_head); 1563 spin_lock(&tx_queue->lock); 1564 skb_queue_splice_init(tx_queue, &skb_head); 1565 spin_unlock(&tx_queue->lock); 1566 1567 tx_data = agg->head; 1568 agg->skb_num = 0; 1569 agg->skb_len = 0; 1570 remain = agg_buf_sz; 1571 1572 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1573 struct tx_desc *tx_desc; 1574 struct sk_buff *skb; 1575 unsigned int len; 1576 u32 offset; 1577 1578 skb = __skb_dequeue(&skb_head); 1579 if (!skb) 1580 break; 1581 1582 len = skb->len + sizeof(*tx_desc); 1583 1584 if (len > remain) { 1585 __skb_queue_head(&skb_head, skb); 1586 break; 1587 } 1588 1589 tx_data = tx_agg_align(tx_data); 1590 tx_desc = (struct tx_desc *)tx_data; 1591 1592 offset = (u32)skb_transport_offset(skb); 1593 1594 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1595 r8152_csum_workaround(tp, skb, &skb_head); 1596 continue; 1597 } 1598 1599 rtl_tx_vlan_tag(tx_desc, skb); 1600 1601 tx_data += sizeof(*tx_desc); 1602 1603 len = skb->len; 1604 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1605 struct net_device_stats *stats = &tp->netdev->stats; 1606 1607 stats->tx_dropped++; 1608 dev_kfree_skb_any(skb); 1609 tx_data -= sizeof(*tx_desc); 1610 continue; 1611 } 1612 1613 tx_data += len; 1614 agg->skb_len += len; 1615 agg->skb_num++; 1616 1617 dev_kfree_skb_any(skb); 1618 1619 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1620 } 1621 1622 if (!skb_queue_empty(&skb_head)) { 1623 spin_lock(&tx_queue->lock); 1624 skb_queue_splice(&skb_head, tx_queue); 1625 spin_unlock(&tx_queue->lock); 1626 } 1627 1628 netif_tx_lock(tp->netdev); 1629 1630 if (netif_queue_stopped(tp->netdev) && 1631 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1632 netif_wake_queue(tp->netdev); 1633 1634 netif_tx_unlock(tp->netdev); 1635 1636 ret = usb_autopm_get_interface_async(tp->intf); 1637 if (ret < 0) 1638 goto out_tx_fill; 1639 1640 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1641 agg->head, (int)(tx_data - (u8 *)agg->head), 1642 (usb_complete_t)write_bulk_callback, agg); 1643 1644 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1645 if (ret < 0) 1646 usb_autopm_put_interface_async(tp->intf); 1647 1648 out_tx_fill: 1649 return ret; 1650 } 1651 1652 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1653 { 1654 u8 checksum = CHECKSUM_NONE; 1655 u32 opts2, opts3; 1656 1657 if (tp->version == RTL_VER_01) 1658 goto return_result; 1659 1660 opts2 = le32_to_cpu(rx_desc->opts2); 1661 opts3 = le32_to_cpu(rx_desc->opts3); 1662 1663 if (opts2 & RD_IPV4_CS) { 1664 if (opts3 & IPF) 1665 checksum = CHECKSUM_NONE; 1666 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) 1667 checksum = CHECKSUM_NONE; 1668 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) 1669 checksum = CHECKSUM_NONE; 1670 else 1671 checksum = CHECKSUM_UNNECESSARY; 1672 } else if (RD_IPV6_CS) { 1673 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1674 checksum = CHECKSUM_UNNECESSARY; 1675 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1676 checksum = CHECKSUM_UNNECESSARY; 1677 } 1678 1679 return_result: 1680 return checksum; 1681 } 1682 1683 static int rx_bottom(struct r8152 *tp, int budget) 1684 { 1685 unsigned long flags; 1686 struct list_head *cursor, *next, rx_queue; 1687 int ret = 0, work_done = 0; 1688 1689 if (!skb_queue_empty(&tp->rx_queue)) { 1690 while (work_done < budget) { 1691 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); 1692 struct net_device *netdev = tp->netdev; 1693 struct net_device_stats *stats = &netdev->stats; 1694 unsigned int pkt_len; 1695 1696 if (!skb) 1697 break; 1698 1699 pkt_len = skb->len; 1700 napi_gro_receive(&tp->napi, skb); 1701 work_done++; 1702 stats->rx_packets++; 1703 stats->rx_bytes += pkt_len; 1704 } 1705 } 1706 1707 if (list_empty(&tp->rx_done)) 1708 goto out1; 1709 1710 INIT_LIST_HEAD(&rx_queue); 1711 spin_lock_irqsave(&tp->rx_lock, flags); 1712 list_splice_init(&tp->rx_done, &rx_queue); 1713 spin_unlock_irqrestore(&tp->rx_lock, flags); 1714 1715 list_for_each_safe(cursor, next, &rx_queue) { 1716 struct rx_desc *rx_desc; 1717 struct rx_agg *agg; 1718 int len_used = 0; 1719 struct urb *urb; 1720 u8 *rx_data; 1721 1722 list_del_init(cursor); 1723 1724 agg = list_entry(cursor, struct rx_agg, list); 1725 urb = agg->urb; 1726 if (urb->actual_length < ETH_ZLEN) 1727 goto submit; 1728 1729 rx_desc = agg->head; 1730 rx_data = agg->head; 1731 len_used += sizeof(struct rx_desc); 1732 1733 while (urb->actual_length > len_used) { 1734 struct net_device *netdev = tp->netdev; 1735 struct net_device_stats *stats = &netdev->stats; 1736 unsigned int pkt_len; 1737 struct sk_buff *skb; 1738 1739 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1740 if (pkt_len < ETH_ZLEN) 1741 break; 1742 1743 len_used += pkt_len; 1744 if (urb->actual_length < len_used) 1745 break; 1746 1747 pkt_len -= CRC_SIZE; 1748 rx_data += sizeof(struct rx_desc); 1749 1750 skb = netdev_alloc_skb_ip_align(netdev, pkt_len); 1751 if (!skb) { 1752 stats->rx_dropped++; 1753 goto find_next_rx; 1754 } 1755 1756 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 1757 memcpy(skb->data, rx_data, pkt_len); 1758 skb_put(skb, pkt_len); 1759 skb->protocol = eth_type_trans(skb, netdev); 1760 rtl_rx_vlan_tag(rx_desc, skb); 1761 if (work_done < budget) { 1762 napi_gro_receive(&tp->napi, skb); 1763 work_done++; 1764 stats->rx_packets++; 1765 stats->rx_bytes += pkt_len; 1766 } else { 1767 __skb_queue_tail(&tp->rx_queue, skb); 1768 } 1769 1770 find_next_rx: 1771 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); 1772 rx_desc = (struct rx_desc *)rx_data; 1773 len_used = (int)(rx_data - (u8 *)agg->head); 1774 len_used += sizeof(struct rx_desc); 1775 } 1776 1777 submit: 1778 if (!ret) { 1779 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1780 } else { 1781 urb->actual_length = 0; 1782 list_add_tail(&agg->list, next); 1783 } 1784 } 1785 1786 if (!list_empty(&rx_queue)) { 1787 spin_lock_irqsave(&tp->rx_lock, flags); 1788 list_splice_tail(&rx_queue, &tp->rx_done); 1789 spin_unlock_irqrestore(&tp->rx_lock, flags); 1790 } 1791 1792 out1: 1793 return work_done; 1794 } 1795 1796 static void tx_bottom(struct r8152 *tp) 1797 { 1798 int res; 1799 1800 do { 1801 struct tx_agg *agg; 1802 1803 if (skb_queue_empty(&tp->tx_queue)) 1804 break; 1805 1806 agg = r8152_get_tx_agg(tp); 1807 if (!agg) 1808 break; 1809 1810 res = r8152_tx_agg_fill(tp, agg); 1811 if (res) { 1812 struct net_device *netdev = tp->netdev; 1813 1814 if (res == -ENODEV) { 1815 set_bit(RTL8152_UNPLUG, &tp->flags); 1816 netif_device_detach(netdev); 1817 } else { 1818 struct net_device_stats *stats = &netdev->stats; 1819 unsigned long flags; 1820 1821 netif_warn(tp, tx_err, netdev, 1822 "failed tx_urb %d\n", res); 1823 stats->tx_dropped += agg->skb_num; 1824 1825 spin_lock_irqsave(&tp->tx_lock, flags); 1826 list_add_tail(&agg->list, &tp->tx_free); 1827 spin_unlock_irqrestore(&tp->tx_lock, flags); 1828 } 1829 } 1830 } while (res == 0); 1831 } 1832 1833 static void bottom_half(struct r8152 *tp) 1834 { 1835 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1836 return; 1837 1838 if (!test_bit(WORK_ENABLE, &tp->flags)) 1839 return; 1840 1841 /* When link down, the driver would cancel all bulks. */ 1842 /* This avoid the re-submitting bulk */ 1843 if (!netif_carrier_ok(tp->netdev)) 1844 return; 1845 1846 clear_bit(SCHEDULE_NAPI, &tp->flags); 1847 1848 tx_bottom(tp); 1849 } 1850 1851 static int r8152_poll(struct napi_struct *napi, int budget) 1852 { 1853 struct r8152 *tp = container_of(napi, struct r8152, napi); 1854 int work_done; 1855 1856 work_done = rx_bottom(tp, budget); 1857 bottom_half(tp); 1858 1859 if (work_done < budget) { 1860 napi_complete(napi); 1861 if (!list_empty(&tp->rx_done)) 1862 napi_schedule(napi); 1863 } 1864 1865 return work_done; 1866 } 1867 1868 static 1869 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 1870 { 1871 int ret; 1872 1873 /* The rx would be stopped, so skip submitting */ 1874 if (test_bit(RTL8152_UNPLUG, &tp->flags) || 1875 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) 1876 return 0; 1877 1878 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 1879 agg->head, agg_buf_sz, 1880 (usb_complete_t)read_bulk_callback, agg); 1881 1882 ret = usb_submit_urb(agg->urb, mem_flags); 1883 if (ret == -ENODEV) { 1884 set_bit(RTL8152_UNPLUG, &tp->flags); 1885 netif_device_detach(tp->netdev); 1886 } else if (ret) { 1887 struct urb *urb = agg->urb; 1888 unsigned long flags; 1889 1890 urb->actual_length = 0; 1891 spin_lock_irqsave(&tp->rx_lock, flags); 1892 list_add_tail(&agg->list, &tp->rx_done); 1893 spin_unlock_irqrestore(&tp->rx_lock, flags); 1894 1895 netif_err(tp, rx_err, tp->netdev, 1896 "Couldn't submit rx[%p], ret = %d\n", agg, ret); 1897 1898 napi_schedule(&tp->napi); 1899 } 1900 1901 return ret; 1902 } 1903 1904 static void rtl_drop_queued_tx(struct r8152 *tp) 1905 { 1906 struct net_device_stats *stats = &tp->netdev->stats; 1907 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1908 struct sk_buff *skb; 1909 1910 if (skb_queue_empty(tx_queue)) 1911 return; 1912 1913 __skb_queue_head_init(&skb_head); 1914 spin_lock_bh(&tx_queue->lock); 1915 skb_queue_splice_init(tx_queue, &skb_head); 1916 spin_unlock_bh(&tx_queue->lock); 1917 1918 while ((skb = __skb_dequeue(&skb_head))) { 1919 dev_kfree_skb(skb); 1920 stats->tx_dropped++; 1921 } 1922 } 1923 1924 static void rtl8152_tx_timeout(struct net_device *netdev) 1925 { 1926 struct r8152 *tp = netdev_priv(netdev); 1927 1928 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 1929 1930 usb_queue_reset_device(tp->intf); 1931 } 1932 1933 static void rtl8152_set_rx_mode(struct net_device *netdev) 1934 { 1935 struct r8152 *tp = netdev_priv(netdev); 1936 1937 if (netif_carrier_ok(netdev)) { 1938 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 1939 schedule_delayed_work(&tp->schedule, 0); 1940 } 1941 } 1942 1943 static void _rtl8152_set_rx_mode(struct net_device *netdev) 1944 { 1945 struct r8152 *tp = netdev_priv(netdev); 1946 u32 mc_filter[2]; /* Multicast hash filter */ 1947 __le32 tmp[2]; 1948 u32 ocp_data; 1949 1950 netif_stop_queue(netdev); 1951 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 1952 ocp_data &= ~RCR_ACPT_ALL; 1953 ocp_data |= RCR_AB | RCR_APM; 1954 1955 if (netdev->flags & IFF_PROMISC) { 1956 /* Unconditionally log net taps. */ 1957 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 1958 ocp_data |= RCR_AM | RCR_AAP; 1959 mc_filter[1] = 0xffffffff; 1960 mc_filter[0] = 0xffffffff; 1961 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 1962 (netdev->flags & IFF_ALLMULTI)) { 1963 /* Too many to filter perfectly -- accept all multicasts. */ 1964 ocp_data |= RCR_AM; 1965 mc_filter[1] = 0xffffffff; 1966 mc_filter[0] = 0xffffffff; 1967 } else { 1968 struct netdev_hw_addr *ha; 1969 1970 mc_filter[1] = 0; 1971 mc_filter[0] = 0; 1972 netdev_for_each_mc_addr(ha, netdev) { 1973 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 1974 1975 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 1976 ocp_data |= RCR_AM; 1977 } 1978 } 1979 1980 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 1981 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 1982 1983 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 1984 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 1985 netif_wake_queue(netdev); 1986 } 1987 1988 static netdev_features_t 1989 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 1990 netdev_features_t features) 1991 { 1992 u32 mss = skb_shinfo(skb)->gso_size; 1993 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 1994 int offset = skb_transport_offset(skb); 1995 1996 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) 1997 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 1998 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 1999 features &= ~NETIF_F_GSO_MASK; 2000 2001 return features; 2002 } 2003 2004 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 2005 struct net_device *netdev) 2006 { 2007 struct r8152 *tp = netdev_priv(netdev); 2008 2009 skb_tx_timestamp(skb); 2010 2011 skb_queue_tail(&tp->tx_queue, skb); 2012 2013 if (!list_empty(&tp->tx_free)) { 2014 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2015 set_bit(SCHEDULE_NAPI, &tp->flags); 2016 schedule_delayed_work(&tp->schedule, 0); 2017 } else { 2018 usb_mark_last_busy(tp->udev); 2019 napi_schedule(&tp->napi); 2020 } 2021 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 2022 netif_stop_queue(netdev); 2023 } 2024 2025 return NETDEV_TX_OK; 2026 } 2027 2028 static void r8152b_reset_packet_filter(struct r8152 *tp) 2029 { 2030 u32 ocp_data; 2031 2032 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 2033 ocp_data &= ~FMC_FCR_MCU_EN; 2034 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2035 ocp_data |= FMC_FCR_MCU_EN; 2036 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2037 } 2038 2039 static void rtl8152_nic_reset(struct r8152 *tp) 2040 { 2041 int i; 2042 2043 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 2044 2045 for (i = 0; i < 1000; i++) { 2046 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 2047 break; 2048 usleep_range(100, 400); 2049 } 2050 } 2051 2052 static void set_tx_qlen(struct r8152 *tp) 2053 { 2054 struct net_device *netdev = tp->netdev; 2055 2056 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + 2057 sizeof(struct tx_desc)); 2058 } 2059 2060 static inline u8 rtl8152_get_speed(struct r8152 *tp) 2061 { 2062 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 2063 } 2064 2065 static void rtl_set_eee_plus(struct r8152 *tp) 2066 { 2067 u32 ocp_data; 2068 u8 speed; 2069 2070 speed = rtl8152_get_speed(tp); 2071 if (speed & _10bps) { 2072 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2073 ocp_data |= EEEP_CR_EEEP_TX; 2074 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2075 } else { 2076 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2077 ocp_data &= ~EEEP_CR_EEEP_TX; 2078 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2079 } 2080 } 2081 2082 static void rxdy_gated_en(struct r8152 *tp, bool enable) 2083 { 2084 u32 ocp_data; 2085 2086 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 2087 if (enable) 2088 ocp_data |= RXDY_GATED_EN; 2089 else 2090 ocp_data &= ~RXDY_GATED_EN; 2091 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 2092 } 2093 2094 static int rtl_start_rx(struct r8152 *tp) 2095 { 2096 int i, ret = 0; 2097 2098 INIT_LIST_HEAD(&tp->rx_done); 2099 for (i = 0; i < RTL8152_MAX_RX; i++) { 2100 INIT_LIST_HEAD(&tp->rx_info[i].list); 2101 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 2102 if (ret) 2103 break; 2104 } 2105 2106 if (ret && ++i < RTL8152_MAX_RX) { 2107 struct list_head rx_queue; 2108 unsigned long flags; 2109 2110 INIT_LIST_HEAD(&rx_queue); 2111 2112 do { 2113 struct rx_agg *agg = &tp->rx_info[i++]; 2114 struct urb *urb = agg->urb; 2115 2116 urb->actual_length = 0; 2117 list_add_tail(&agg->list, &rx_queue); 2118 } while (i < RTL8152_MAX_RX); 2119 2120 spin_lock_irqsave(&tp->rx_lock, flags); 2121 list_splice_tail(&rx_queue, &tp->rx_done); 2122 spin_unlock_irqrestore(&tp->rx_lock, flags); 2123 } 2124 2125 return ret; 2126 } 2127 2128 static int rtl_stop_rx(struct r8152 *tp) 2129 { 2130 int i; 2131 2132 for (i = 0; i < RTL8152_MAX_RX; i++) 2133 usb_kill_urb(tp->rx_info[i].urb); 2134 2135 while (!skb_queue_empty(&tp->rx_queue)) 2136 dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); 2137 2138 return 0; 2139 } 2140 2141 static int rtl_enable(struct r8152 *tp) 2142 { 2143 u32 ocp_data; 2144 2145 r8152b_reset_packet_filter(tp); 2146 2147 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2148 ocp_data |= CR_RE | CR_TE; 2149 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2150 2151 rxdy_gated_en(tp, false); 2152 2153 return 0; 2154 } 2155 2156 static int rtl8152_enable(struct r8152 *tp) 2157 { 2158 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2159 return -ENODEV; 2160 2161 set_tx_qlen(tp); 2162 rtl_set_eee_plus(tp); 2163 2164 return rtl_enable(tp); 2165 } 2166 2167 static void r8153_set_rx_early_timeout(struct r8152 *tp) 2168 { 2169 u32 ocp_data = tp->coalesce / 8; 2170 2171 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data); 2172 } 2173 2174 static void r8153_set_rx_early_size(struct r8152 *tp) 2175 { 2176 u32 mtu = tp->netdev->mtu; 2177 u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 8; 2178 2179 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data); 2180 } 2181 2182 static int rtl8153_enable(struct r8152 *tp) 2183 { 2184 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2185 return -ENODEV; 2186 2187 usb_disable_lpm(tp->udev); 2188 set_tx_qlen(tp); 2189 rtl_set_eee_plus(tp); 2190 r8153_set_rx_early_timeout(tp); 2191 r8153_set_rx_early_size(tp); 2192 2193 return rtl_enable(tp); 2194 } 2195 2196 static void rtl_disable(struct r8152 *tp) 2197 { 2198 u32 ocp_data; 2199 int i; 2200 2201 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2202 rtl_drop_queued_tx(tp); 2203 return; 2204 } 2205 2206 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2207 ocp_data &= ~RCR_ACPT_ALL; 2208 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2209 2210 rtl_drop_queued_tx(tp); 2211 2212 for (i = 0; i < RTL8152_MAX_TX; i++) 2213 usb_kill_urb(tp->tx_info[i].urb); 2214 2215 rxdy_gated_en(tp, true); 2216 2217 for (i = 0; i < 1000; i++) { 2218 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2219 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2220 break; 2221 usleep_range(1000, 2000); 2222 } 2223 2224 for (i = 0; i < 1000; i++) { 2225 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2226 break; 2227 usleep_range(1000, 2000); 2228 } 2229 2230 rtl_stop_rx(tp); 2231 2232 rtl8152_nic_reset(tp); 2233 } 2234 2235 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2236 { 2237 u32 ocp_data; 2238 2239 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2240 if (enable) 2241 ocp_data |= POWER_CUT; 2242 else 2243 ocp_data &= ~POWER_CUT; 2244 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2245 2246 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2247 ocp_data &= ~RESUME_INDICATE; 2248 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2249 } 2250 2251 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 2252 { 2253 u32 ocp_data; 2254 2255 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2256 if (enable) 2257 ocp_data |= CPCR_RX_VLAN; 2258 else 2259 ocp_data &= ~CPCR_RX_VLAN; 2260 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2261 } 2262 2263 static int rtl8152_set_features(struct net_device *dev, 2264 netdev_features_t features) 2265 { 2266 netdev_features_t changed = features ^ dev->features; 2267 struct r8152 *tp = netdev_priv(dev); 2268 int ret; 2269 2270 ret = usb_autopm_get_interface(tp->intf); 2271 if (ret < 0) 2272 goto out; 2273 2274 mutex_lock(&tp->control); 2275 2276 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 2277 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2278 rtl_rx_vlan_en(tp, true); 2279 else 2280 rtl_rx_vlan_en(tp, false); 2281 } 2282 2283 mutex_unlock(&tp->control); 2284 2285 usb_autopm_put_interface(tp->intf); 2286 2287 out: 2288 return ret; 2289 } 2290 2291 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2292 2293 static u32 __rtl_get_wol(struct r8152 *tp) 2294 { 2295 u32 ocp_data; 2296 u32 wolopts = 0; 2297 2298 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2299 if (!(ocp_data & LAN_WAKE_EN)) 2300 return 0; 2301 2302 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2303 if (ocp_data & LINK_ON_WAKE_EN) 2304 wolopts |= WAKE_PHY; 2305 2306 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2307 if (ocp_data & UWF_EN) 2308 wolopts |= WAKE_UCAST; 2309 if (ocp_data & BWF_EN) 2310 wolopts |= WAKE_BCAST; 2311 if (ocp_data & MWF_EN) 2312 wolopts |= WAKE_MCAST; 2313 2314 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2315 if (ocp_data & MAGIC_EN) 2316 wolopts |= WAKE_MAGIC; 2317 2318 return wolopts; 2319 } 2320 2321 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2322 { 2323 u32 ocp_data; 2324 2325 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2326 2327 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2328 ocp_data &= ~LINK_ON_WAKE_EN; 2329 if (wolopts & WAKE_PHY) 2330 ocp_data |= LINK_ON_WAKE_EN; 2331 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2332 2333 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2334 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN); 2335 if (wolopts & WAKE_UCAST) 2336 ocp_data |= UWF_EN; 2337 if (wolopts & WAKE_BCAST) 2338 ocp_data |= BWF_EN; 2339 if (wolopts & WAKE_MCAST) 2340 ocp_data |= MWF_EN; 2341 if (wolopts & WAKE_ANY) 2342 ocp_data |= LAN_WAKE_EN; 2343 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2344 2345 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2346 2347 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2348 ocp_data &= ~MAGIC_EN; 2349 if (wolopts & WAKE_MAGIC) 2350 ocp_data |= MAGIC_EN; 2351 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2352 2353 if (wolopts & WAKE_ANY) 2354 device_set_wakeup_enable(&tp->udev->dev, true); 2355 else 2356 device_set_wakeup_enable(&tp->udev->dev, false); 2357 } 2358 2359 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2360 { 2361 u8 u1u2[8]; 2362 2363 if (enable) 2364 memset(u1u2, 0xff, sizeof(u1u2)); 2365 else 2366 memset(u1u2, 0x00, sizeof(u1u2)); 2367 2368 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2369 } 2370 2371 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2372 { 2373 u32 ocp_data; 2374 2375 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2376 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04) 2377 ocp_data |= U2P3_ENABLE; 2378 else 2379 ocp_data &= ~U2P3_ENABLE; 2380 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2381 } 2382 2383 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2384 { 2385 u32 ocp_data; 2386 2387 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2388 if (enable) 2389 ocp_data |= PWR_EN | PHASE2_EN; 2390 else 2391 ocp_data &= ~(PWR_EN | PHASE2_EN); 2392 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2393 2394 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2395 ocp_data &= ~PCUT_STATUS; 2396 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2397 } 2398 2399 static bool rtl_can_wakeup(struct r8152 *tp) 2400 { 2401 struct usb_device *udev = tp->udev; 2402 2403 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); 2404 } 2405 2406 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 2407 { 2408 if (enable) { 2409 u32 ocp_data; 2410 2411 r8153_u1u2en(tp, false); 2412 r8153_u2p3en(tp, false); 2413 2414 __rtl_set_wol(tp, WAKE_ANY); 2415 2416 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2417 2418 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2419 ocp_data |= LINK_OFF_WAKE_EN; 2420 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2421 2422 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2423 } else { 2424 __rtl_set_wol(tp, tp->saved_wolopts); 2425 r8153_u2p3en(tp, true); 2426 r8153_u1u2en(tp, true); 2427 } 2428 } 2429 2430 static void rtl_phy_reset(struct r8152 *tp) 2431 { 2432 u16 data; 2433 int i; 2434 2435 data = r8152_mdio_read(tp, MII_BMCR); 2436 2437 /* don't reset again before the previous one complete */ 2438 if (data & BMCR_RESET) 2439 return; 2440 2441 data |= BMCR_RESET; 2442 r8152_mdio_write(tp, MII_BMCR, data); 2443 2444 for (i = 0; i < 50; i++) { 2445 msleep(20); 2446 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 2447 break; 2448 } 2449 } 2450 2451 static void r8153_teredo_off(struct r8152 *tp) 2452 { 2453 u32 ocp_data; 2454 2455 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2456 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); 2457 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2458 2459 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 2460 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 2461 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 2462 } 2463 2464 static void rtl_reset_bmu(struct r8152 *tp) 2465 { 2466 u32 ocp_data; 2467 2468 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); 2469 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 2470 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2471 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 2472 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2473 } 2474 2475 static void r8152_aldps_en(struct r8152 *tp, bool enable) 2476 { 2477 if (enable) { 2478 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 2479 LINKENA | DIS_SDSAVE); 2480 } else { 2481 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | 2482 DIS_SDSAVE); 2483 msleep(20); 2484 } 2485 } 2486 2487 static void rtl8152_disable(struct r8152 *tp) 2488 { 2489 r8152_aldps_en(tp, false); 2490 rtl_disable(tp); 2491 r8152_aldps_en(tp, true); 2492 } 2493 2494 static void r8152b_hw_phy_cfg(struct r8152 *tp) 2495 { 2496 u16 data; 2497 2498 data = r8152_mdio_read(tp, MII_BMCR); 2499 if (data & BMCR_PDOWN) { 2500 data &= ~BMCR_PDOWN; 2501 r8152_mdio_write(tp, MII_BMCR, data); 2502 } 2503 2504 set_bit(PHY_RESET, &tp->flags); 2505 } 2506 2507 static void r8152b_exit_oob(struct r8152 *tp) 2508 { 2509 u32 ocp_data; 2510 int i; 2511 2512 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2513 ocp_data &= ~RCR_ACPT_ALL; 2514 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2515 2516 rxdy_gated_en(tp, true); 2517 r8153_teredo_off(tp); 2518 r8152b_hw_phy_cfg(tp); 2519 2520 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2521 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 2522 2523 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2524 ocp_data &= ~NOW_IS_OOB; 2525 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2526 2527 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2528 ocp_data &= ~MCU_BORW_EN; 2529 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2530 2531 for (i = 0; i < 1000; i++) { 2532 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2533 if (ocp_data & LINK_LIST_READY) 2534 break; 2535 usleep_range(1000, 2000); 2536 } 2537 2538 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2539 ocp_data |= RE_INIT_LL; 2540 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2541 2542 for (i = 0; i < 1000; i++) { 2543 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2544 if (ocp_data & LINK_LIST_READY) 2545 break; 2546 usleep_range(1000, 2000); 2547 } 2548 2549 rtl8152_nic_reset(tp); 2550 2551 /* rx share fifo credit full threshold */ 2552 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2553 2554 if (tp->udev->speed == USB_SPEED_FULL || 2555 tp->udev->speed == USB_SPEED_LOW) { 2556 /* rx share fifo credit near full threshold */ 2557 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2558 RXFIFO_THR2_FULL); 2559 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2560 RXFIFO_THR3_FULL); 2561 } else { 2562 /* rx share fifo credit near full threshold */ 2563 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2564 RXFIFO_THR2_HIGH); 2565 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2566 RXFIFO_THR3_HIGH); 2567 } 2568 2569 /* TX share fifo free credit full threshold */ 2570 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 2571 2572 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 2573 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 2574 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 2575 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 2576 2577 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 2578 2579 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2580 2581 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2582 ocp_data |= TCR0_AUTO_FIFO; 2583 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2584 } 2585 2586 static void r8152b_enter_oob(struct r8152 *tp) 2587 { 2588 u32 ocp_data; 2589 int i; 2590 2591 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2592 ocp_data &= ~NOW_IS_OOB; 2593 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2594 2595 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 2596 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 2597 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 2598 2599 rtl_disable(tp); 2600 2601 for (i = 0; i < 1000; i++) { 2602 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2603 if (ocp_data & LINK_LIST_READY) 2604 break; 2605 usleep_range(1000, 2000); 2606 } 2607 2608 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2609 ocp_data |= RE_INIT_LL; 2610 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2611 2612 for (i = 0; i < 1000; i++) { 2613 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2614 if (ocp_data & LINK_LIST_READY) 2615 break; 2616 usleep_range(1000, 2000); 2617 } 2618 2619 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2620 2621 rtl_rx_vlan_en(tp, true); 2622 2623 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2624 ocp_data |= ALDPS_PROXY_MODE; 2625 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2626 2627 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2628 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2629 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2630 2631 rxdy_gated_en(tp, false); 2632 2633 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2634 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2635 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2636 } 2637 2638 static void r8153_hw_phy_cfg(struct r8152 *tp) 2639 { 2640 u32 ocp_data; 2641 u16 data; 2642 2643 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 2644 tp->version == RTL_VER_05) 2645 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 2646 2647 data = r8152_mdio_read(tp, MII_BMCR); 2648 if (data & BMCR_PDOWN) { 2649 data &= ~BMCR_PDOWN; 2650 r8152_mdio_write(tp, MII_BMCR, data); 2651 } 2652 2653 if (tp->version == RTL_VER_03) { 2654 data = ocp_reg_read(tp, OCP_EEE_CFG); 2655 data &= ~CTAP_SHORT_EN; 2656 ocp_reg_write(tp, OCP_EEE_CFG, data); 2657 } 2658 2659 data = ocp_reg_read(tp, OCP_POWER_CFG); 2660 data |= EEE_CLKDIV_EN; 2661 ocp_reg_write(tp, OCP_POWER_CFG, data); 2662 2663 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 2664 data |= EN_10M_BGOFF; 2665 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 2666 data = ocp_reg_read(tp, OCP_POWER_CFG); 2667 data |= EN_10M_PLLOFF; 2668 ocp_reg_write(tp, OCP_POWER_CFG, data); 2669 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 2670 2671 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 2672 ocp_data |= PFM_PWM_SWITCH; 2673 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 2674 2675 /* Enable LPF corner auto tune */ 2676 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 2677 2678 /* Adjust 10M Amplitude */ 2679 sram_write(tp, SRAM_10M_AMP1, 0x00af); 2680 sram_write(tp, SRAM_10M_AMP2, 0x0208); 2681 2682 set_bit(PHY_RESET, &tp->flags); 2683 } 2684 2685 static void r8153_first_init(struct r8152 *tp) 2686 { 2687 u32 ocp_data; 2688 int i; 2689 2690 rxdy_gated_en(tp, true); 2691 r8153_teredo_off(tp); 2692 2693 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2694 ocp_data &= ~RCR_ACPT_ALL; 2695 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2696 2697 r8153_hw_phy_cfg(tp); 2698 2699 rtl8152_nic_reset(tp); 2700 rtl_reset_bmu(tp); 2701 2702 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2703 ocp_data &= ~NOW_IS_OOB; 2704 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2705 2706 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2707 ocp_data &= ~MCU_BORW_EN; 2708 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2709 2710 for (i = 0; i < 1000; i++) { 2711 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2712 if (ocp_data & LINK_LIST_READY) 2713 break; 2714 usleep_range(1000, 2000); 2715 } 2716 2717 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2718 ocp_data |= RE_INIT_LL; 2719 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2720 2721 for (i = 0; i < 1000; i++) { 2722 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2723 if (ocp_data & LINK_LIST_READY) 2724 break; 2725 usleep_range(1000, 2000); 2726 } 2727 2728 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 2729 2730 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); 2731 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 2732 2733 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2734 ocp_data |= TCR0_AUTO_FIFO; 2735 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2736 2737 rtl8152_nic_reset(tp); 2738 2739 /* rx share fifo credit full threshold */ 2740 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2741 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 2742 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 2743 /* TX share fifo free credit full threshold */ 2744 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 2745 2746 /* rx aggregation */ 2747 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 2748 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 2749 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 2750 } 2751 2752 static void r8153_enter_oob(struct r8152 *tp) 2753 { 2754 u32 ocp_data; 2755 int i; 2756 2757 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2758 ocp_data &= ~NOW_IS_OOB; 2759 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2760 2761 rtl_disable(tp); 2762 rtl_reset_bmu(tp); 2763 2764 for (i = 0; i < 1000; i++) { 2765 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2766 if (ocp_data & LINK_LIST_READY) 2767 break; 2768 usleep_range(1000, 2000); 2769 } 2770 2771 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2772 ocp_data |= RE_INIT_LL; 2773 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2774 2775 for (i = 0; i < 1000; i++) { 2776 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2777 if (ocp_data & LINK_LIST_READY) 2778 break; 2779 usleep_range(1000, 2000); 2780 } 2781 2782 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); 2783 2784 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2785 ocp_data &= ~TEREDO_WAKE_MASK; 2786 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2787 2788 rtl_rx_vlan_en(tp, true); 2789 2790 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2791 ocp_data |= ALDPS_PROXY_MODE; 2792 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2793 2794 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2795 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2796 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2797 2798 rxdy_gated_en(tp, false); 2799 2800 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2801 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2802 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2803 } 2804 2805 static void r8153_aldps_en(struct r8152 *tp, bool enable) 2806 { 2807 u16 data; 2808 2809 data = ocp_reg_read(tp, OCP_POWER_CFG); 2810 if (enable) { 2811 data |= EN_ALDPS; 2812 ocp_reg_write(tp, OCP_POWER_CFG, data); 2813 } else { 2814 data &= ~EN_ALDPS; 2815 ocp_reg_write(tp, OCP_POWER_CFG, data); 2816 msleep(20); 2817 } 2818 } 2819 2820 static void rtl8153_disable(struct r8152 *tp) 2821 { 2822 r8153_aldps_en(tp, false); 2823 rtl_disable(tp); 2824 rtl_reset_bmu(tp); 2825 r8153_aldps_en(tp, true); 2826 usb_enable_lpm(tp->udev); 2827 } 2828 2829 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 2830 { 2831 u16 bmcr, anar, gbcr; 2832 int ret = 0; 2833 2834 cancel_delayed_work_sync(&tp->schedule); 2835 anar = r8152_mdio_read(tp, MII_ADVERTISE); 2836 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 2837 ADVERTISE_100HALF | ADVERTISE_100FULL); 2838 if (tp->mii.supports_gmii) { 2839 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 2840 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 2841 } else { 2842 gbcr = 0; 2843 } 2844 2845 if (autoneg == AUTONEG_DISABLE) { 2846 if (speed == SPEED_10) { 2847 bmcr = 0; 2848 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2849 } else if (speed == SPEED_100) { 2850 bmcr = BMCR_SPEED100; 2851 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2852 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 2853 bmcr = BMCR_SPEED1000; 2854 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 2855 } else { 2856 ret = -EINVAL; 2857 goto out; 2858 } 2859 2860 if (duplex == DUPLEX_FULL) 2861 bmcr |= BMCR_FULLDPLX; 2862 } else { 2863 if (speed == SPEED_10) { 2864 if (duplex == DUPLEX_FULL) 2865 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2866 else 2867 anar |= ADVERTISE_10HALF; 2868 } else if (speed == SPEED_100) { 2869 if (duplex == DUPLEX_FULL) { 2870 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2871 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2872 } else { 2873 anar |= ADVERTISE_10HALF; 2874 anar |= ADVERTISE_100HALF; 2875 } 2876 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 2877 if (duplex == DUPLEX_FULL) { 2878 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2879 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2880 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 2881 } else { 2882 anar |= ADVERTISE_10HALF; 2883 anar |= ADVERTISE_100HALF; 2884 gbcr |= ADVERTISE_1000HALF; 2885 } 2886 } else { 2887 ret = -EINVAL; 2888 goto out; 2889 } 2890 2891 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 2892 } 2893 2894 if (test_bit(PHY_RESET, &tp->flags)) 2895 bmcr |= BMCR_RESET; 2896 2897 if (tp->mii.supports_gmii) 2898 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 2899 2900 r8152_mdio_write(tp, MII_ADVERTISE, anar); 2901 r8152_mdio_write(tp, MII_BMCR, bmcr); 2902 2903 if (test_and_clear_bit(PHY_RESET, &tp->flags)) { 2904 int i; 2905 2906 for (i = 0; i < 50; i++) { 2907 msleep(20); 2908 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 2909 break; 2910 } 2911 } 2912 2913 out: 2914 return ret; 2915 } 2916 2917 static void rtl8152_up(struct r8152 *tp) 2918 { 2919 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2920 return; 2921 2922 r8152_aldps_en(tp, false); 2923 r8152b_exit_oob(tp); 2924 r8152_aldps_en(tp, true); 2925 } 2926 2927 static void rtl8152_down(struct r8152 *tp) 2928 { 2929 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2930 rtl_drop_queued_tx(tp); 2931 return; 2932 } 2933 2934 r8152_power_cut_en(tp, false); 2935 r8152_aldps_en(tp, false); 2936 r8152b_enter_oob(tp); 2937 r8152_aldps_en(tp, true); 2938 } 2939 2940 static void rtl8153_up(struct r8152 *tp) 2941 { 2942 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2943 return; 2944 2945 r8153_u1u2en(tp, false); 2946 r8153_aldps_en(tp, false); 2947 r8153_first_init(tp); 2948 r8153_aldps_en(tp, true); 2949 r8153_u2p3en(tp, true); 2950 r8153_u1u2en(tp, true); 2951 usb_enable_lpm(tp->udev); 2952 } 2953 2954 static void rtl8153_down(struct r8152 *tp) 2955 { 2956 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2957 rtl_drop_queued_tx(tp); 2958 return; 2959 } 2960 2961 r8153_u1u2en(tp, false); 2962 r8153_u2p3en(tp, false); 2963 r8153_power_cut_en(tp, false); 2964 r8153_aldps_en(tp, false); 2965 r8153_enter_oob(tp); 2966 r8153_aldps_en(tp, true); 2967 } 2968 2969 static bool rtl8152_in_nway(struct r8152 *tp) 2970 { 2971 u16 nway_state; 2972 2973 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); 2974 tp->ocp_base = 0x2000; 2975 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ 2976 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); 2977 2978 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ 2979 if (nway_state & 0xc000) 2980 return false; 2981 else 2982 return true; 2983 } 2984 2985 static bool rtl8153_in_nway(struct r8152 *tp) 2986 { 2987 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; 2988 2989 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) 2990 return false; 2991 else 2992 return true; 2993 } 2994 2995 static void set_carrier(struct r8152 *tp) 2996 { 2997 struct net_device *netdev = tp->netdev; 2998 u8 speed; 2999 3000 speed = rtl8152_get_speed(tp); 3001 3002 if (speed & LINK_STATUS) { 3003 if (!netif_carrier_ok(netdev)) { 3004 tp->rtl_ops.enable(tp); 3005 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 3006 napi_disable(&tp->napi); 3007 netif_carrier_on(netdev); 3008 rtl_start_rx(tp); 3009 napi_enable(&tp->napi); 3010 } 3011 } else { 3012 if (netif_carrier_ok(netdev)) { 3013 netif_carrier_off(netdev); 3014 napi_disable(&tp->napi); 3015 tp->rtl_ops.disable(tp); 3016 napi_enable(&tp->napi); 3017 } 3018 } 3019 } 3020 3021 static void rtl_work_func_t(struct work_struct *work) 3022 { 3023 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 3024 3025 /* If the device is unplugged or !netif_running(), the workqueue 3026 * doesn't need to wake the device, and could return directly. 3027 */ 3028 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) 3029 return; 3030 3031 if (usb_autopm_get_interface(tp->intf) < 0) 3032 return; 3033 3034 if (!test_bit(WORK_ENABLE, &tp->flags)) 3035 goto out1; 3036 3037 if (!mutex_trylock(&tp->control)) { 3038 schedule_delayed_work(&tp->schedule, 0); 3039 goto out1; 3040 } 3041 3042 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) 3043 set_carrier(tp); 3044 3045 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) 3046 _rtl8152_set_rx_mode(tp->netdev); 3047 3048 /* don't schedule napi before linking */ 3049 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) && 3050 netif_carrier_ok(tp->netdev)) 3051 napi_schedule(&tp->napi); 3052 3053 if (test_and_clear_bit(PHY_RESET, &tp->flags)) 3054 rtl_phy_reset(tp); 3055 3056 mutex_unlock(&tp->control); 3057 3058 out1: 3059 usb_autopm_put_interface(tp->intf); 3060 } 3061 3062 #ifdef CONFIG_PM_SLEEP 3063 static int rtl_notifier(struct notifier_block *nb, unsigned long action, 3064 void *data) 3065 { 3066 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); 3067 3068 switch (action) { 3069 case PM_HIBERNATION_PREPARE: 3070 case PM_SUSPEND_PREPARE: 3071 usb_autopm_get_interface(tp->intf); 3072 break; 3073 3074 case PM_POST_HIBERNATION: 3075 case PM_POST_SUSPEND: 3076 usb_autopm_put_interface(tp->intf); 3077 break; 3078 3079 case PM_POST_RESTORE: 3080 case PM_RESTORE_PREPARE: 3081 default: 3082 break; 3083 } 3084 3085 return NOTIFY_DONE; 3086 } 3087 #endif 3088 3089 static int rtl8152_open(struct net_device *netdev) 3090 { 3091 struct r8152 *tp = netdev_priv(netdev); 3092 int res = 0; 3093 3094 res = alloc_all_mem(tp); 3095 if (res) 3096 goto out; 3097 3098 netif_carrier_off(netdev); 3099 3100 res = usb_autopm_get_interface(tp->intf); 3101 if (res < 0) { 3102 free_all_mem(tp); 3103 goto out; 3104 } 3105 3106 mutex_lock(&tp->control); 3107 3108 tp->rtl_ops.up(tp); 3109 3110 rtl8152_set_speed(tp, AUTONEG_ENABLE, 3111 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, 3112 DUPLEX_FULL); 3113 netif_carrier_off(netdev); 3114 netif_start_queue(netdev); 3115 set_bit(WORK_ENABLE, &tp->flags); 3116 3117 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3118 if (res) { 3119 if (res == -ENODEV) 3120 netif_device_detach(tp->netdev); 3121 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 3122 res); 3123 free_all_mem(tp); 3124 } else { 3125 napi_enable(&tp->napi); 3126 } 3127 3128 mutex_unlock(&tp->control); 3129 3130 usb_autopm_put_interface(tp->intf); 3131 #ifdef CONFIG_PM_SLEEP 3132 tp->pm_notifier.notifier_call = rtl_notifier; 3133 register_pm_notifier(&tp->pm_notifier); 3134 #endif 3135 3136 out: 3137 return res; 3138 } 3139 3140 static int rtl8152_close(struct net_device *netdev) 3141 { 3142 struct r8152 *tp = netdev_priv(netdev); 3143 int res = 0; 3144 3145 #ifdef CONFIG_PM_SLEEP 3146 unregister_pm_notifier(&tp->pm_notifier); 3147 #endif 3148 napi_disable(&tp->napi); 3149 clear_bit(WORK_ENABLE, &tp->flags); 3150 usb_kill_urb(tp->intr_urb); 3151 cancel_delayed_work_sync(&tp->schedule); 3152 netif_stop_queue(netdev); 3153 3154 res = usb_autopm_get_interface(tp->intf); 3155 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { 3156 rtl_drop_queued_tx(tp); 3157 rtl_stop_rx(tp); 3158 } else { 3159 mutex_lock(&tp->control); 3160 3161 tp->rtl_ops.down(tp); 3162 3163 mutex_unlock(&tp->control); 3164 3165 usb_autopm_put_interface(tp->intf); 3166 } 3167 3168 free_all_mem(tp); 3169 3170 return res; 3171 } 3172 3173 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 3174 { 3175 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 3176 ocp_reg_write(tp, OCP_EEE_DATA, reg); 3177 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 3178 } 3179 3180 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 3181 { 3182 u16 data; 3183 3184 r8152_mmd_indirect(tp, dev, reg); 3185 data = ocp_reg_read(tp, OCP_EEE_DATA); 3186 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3187 3188 return data; 3189 } 3190 3191 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 3192 { 3193 r8152_mmd_indirect(tp, dev, reg); 3194 ocp_reg_write(tp, OCP_EEE_DATA, data); 3195 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3196 } 3197 3198 static void r8152_eee_en(struct r8152 *tp, bool enable) 3199 { 3200 u16 config1, config2, config3; 3201 u32 ocp_data; 3202 3203 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3204 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 3205 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 3206 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 3207 3208 if (enable) { 3209 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3210 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 3211 config1 |= sd_rise_time(1); 3212 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 3213 config3 |= fast_snr(42); 3214 } else { 3215 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3216 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 3217 RX_QUIET_EN); 3218 config1 |= sd_rise_time(7); 3219 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 3220 config3 |= fast_snr(511); 3221 } 3222 3223 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3224 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 3225 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 3226 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 3227 } 3228 3229 static void r8152b_enable_eee(struct r8152 *tp) 3230 { 3231 r8152_eee_en(tp, true); 3232 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); 3233 } 3234 3235 static void r8153_eee_en(struct r8152 *tp, bool enable) 3236 { 3237 u32 ocp_data; 3238 u16 config; 3239 3240 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3241 config = ocp_reg_read(tp, OCP_EEE_CFG); 3242 3243 if (enable) { 3244 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3245 config |= EEE10_EN; 3246 } else { 3247 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3248 config &= ~EEE10_EN; 3249 } 3250 3251 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3252 ocp_reg_write(tp, OCP_EEE_CFG, config); 3253 } 3254 3255 static void r8153_enable_eee(struct r8152 *tp) 3256 { 3257 r8153_eee_en(tp, true); 3258 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3259 } 3260 3261 static void r8152b_enable_fc(struct r8152 *tp) 3262 { 3263 u16 anar; 3264 3265 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3266 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 3267 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3268 } 3269 3270 static void rtl_tally_reset(struct r8152 *tp) 3271 { 3272 u32 ocp_data; 3273 3274 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 3275 ocp_data |= TALLY_RESET; 3276 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 3277 } 3278 3279 static void r8152b_init(struct r8152 *tp) 3280 { 3281 u32 ocp_data; 3282 3283 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3284 return; 3285 3286 r8152_aldps_en(tp, false); 3287 3288 if (tp->version == RTL_VER_01) { 3289 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 3290 ocp_data &= ~LED_MODE_MASK; 3291 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 3292 } 3293 3294 r8152_power_cut_en(tp, false); 3295 3296 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3297 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 3298 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3299 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 3300 ocp_data &= ~MCU_CLK_RATIO_MASK; 3301 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 3302 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 3303 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 3304 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 3305 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 3306 3307 r8152b_enable_eee(tp); 3308 r8152_aldps_en(tp, true); 3309 r8152b_enable_fc(tp); 3310 rtl_tally_reset(tp); 3311 3312 /* enable rx aggregation */ 3313 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 3314 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 3315 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 3316 } 3317 3318 static void r8153_init(struct r8152 *tp) 3319 { 3320 u32 ocp_data; 3321 int i; 3322 3323 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3324 return; 3325 3326 r8153_aldps_en(tp, false); 3327 r8153_u1u2en(tp, false); 3328 3329 for (i = 0; i < 500; i++) { 3330 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 3331 AUTOLOAD_DONE) 3332 break; 3333 msleep(20); 3334 } 3335 3336 for (i = 0; i < 500; i++) { 3337 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; 3338 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) 3339 break; 3340 msleep(20); 3341 } 3342 3343 usb_disable_lpm(tp->udev); 3344 r8153_u2p3en(tp, false); 3345 3346 if (tp->version == RTL_VER_04) { 3347 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 3348 ocp_data &= ~pwd_dn_scale_mask; 3349 ocp_data |= pwd_dn_scale(96); 3350 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 3351 3352 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 3353 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 3354 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 3355 } else if (tp->version == RTL_VER_05) { 3356 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 3357 ocp_data &= ~ECM_ALDPS; 3358 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 3359 3360 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 3361 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 3362 ocp_data &= ~DYNAMIC_BURST; 3363 else 3364 ocp_data |= DYNAMIC_BURST; 3365 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 3366 } else if (tp->version == RTL_VER_06) { 3367 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 3368 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 3369 ocp_data &= ~DYNAMIC_BURST; 3370 else 3371 ocp_data |= DYNAMIC_BURST; 3372 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 3373 } 3374 3375 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 3376 ocp_data |= EP4_FULL_FC; 3377 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 3378 3379 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 3380 ocp_data &= ~TIMER11_EN; 3381 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 3382 3383 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 3384 ocp_data &= ~LED_MODE_MASK; 3385 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 3386 3387 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 3388 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) 3389 ocp_data |= LPM_TIMER_500MS; 3390 else 3391 ocp_data |= LPM_TIMER_500US; 3392 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 3393 3394 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 3395 ocp_data &= ~SEN_VAL_MASK; 3396 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 3397 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 3398 3399 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 3400 3401 r8153_power_cut_en(tp, false); 3402 r8153_u1u2en(tp, true); 3403 3404 /* MAC clock speed down */ 3405 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); 3406 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); 3407 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); 3408 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); 3409 3410 r8153_enable_eee(tp); 3411 r8153_aldps_en(tp, true); 3412 r8152b_enable_fc(tp); 3413 rtl_tally_reset(tp); 3414 r8153_u2p3en(tp, true); 3415 } 3416 3417 static int rtl8152_pre_reset(struct usb_interface *intf) 3418 { 3419 struct r8152 *tp = usb_get_intfdata(intf); 3420 struct net_device *netdev; 3421 3422 if (!tp) 3423 return 0; 3424 3425 netdev = tp->netdev; 3426 if (!netif_running(netdev)) 3427 return 0; 3428 3429 napi_disable(&tp->napi); 3430 clear_bit(WORK_ENABLE, &tp->flags); 3431 usb_kill_urb(tp->intr_urb); 3432 cancel_delayed_work_sync(&tp->schedule); 3433 if (netif_carrier_ok(netdev)) { 3434 netif_stop_queue(netdev); 3435 mutex_lock(&tp->control); 3436 tp->rtl_ops.disable(tp); 3437 mutex_unlock(&tp->control); 3438 } 3439 3440 return 0; 3441 } 3442 3443 static int rtl8152_post_reset(struct usb_interface *intf) 3444 { 3445 struct r8152 *tp = usb_get_intfdata(intf); 3446 struct net_device *netdev; 3447 3448 if (!tp) 3449 return 0; 3450 3451 netdev = tp->netdev; 3452 if (!netif_running(netdev)) 3453 return 0; 3454 3455 set_bit(WORK_ENABLE, &tp->flags); 3456 if (netif_carrier_ok(netdev)) { 3457 mutex_lock(&tp->control); 3458 tp->rtl_ops.enable(tp); 3459 rtl8152_set_rx_mode(netdev); 3460 mutex_unlock(&tp->control); 3461 netif_wake_queue(netdev); 3462 } 3463 3464 napi_enable(&tp->napi); 3465 3466 return 0; 3467 } 3468 3469 static bool delay_autosuspend(struct r8152 *tp) 3470 { 3471 bool sw_linking = !!netif_carrier_ok(tp->netdev); 3472 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); 3473 3474 /* This means a linking change occurs and the driver doesn't detect it, 3475 * yet. If the driver has disabled tx/rx and hw is linking on, the 3476 * device wouldn't wake up by receiving any packet. 3477 */ 3478 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) 3479 return true; 3480 3481 /* If the linking down is occurred by nway, the device may miss the 3482 * linking change event. And it wouldn't wake when linking on. 3483 */ 3484 if (!sw_linking && tp->rtl_ops.in_nway(tp)) 3485 return true; 3486 else 3487 return false; 3488 } 3489 3490 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 3491 { 3492 struct r8152 *tp = usb_get_intfdata(intf); 3493 struct net_device *netdev = tp->netdev; 3494 int ret = 0; 3495 3496 mutex_lock(&tp->control); 3497 3498 if (PMSG_IS_AUTO(message)) { 3499 if (netif_running(netdev) && delay_autosuspend(tp)) { 3500 ret = -EBUSY; 3501 goto out1; 3502 } 3503 3504 set_bit(SELECTIVE_SUSPEND, &tp->flags); 3505 } else { 3506 netif_device_detach(netdev); 3507 } 3508 3509 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 3510 clear_bit(WORK_ENABLE, &tp->flags); 3511 usb_kill_urb(tp->intr_urb); 3512 napi_disable(&tp->napi); 3513 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3514 rtl_stop_rx(tp); 3515 rtl_runtime_suspend_enable(tp, true); 3516 } else { 3517 cancel_delayed_work_sync(&tp->schedule); 3518 tp->rtl_ops.down(tp); 3519 } 3520 napi_enable(&tp->napi); 3521 } 3522 out1: 3523 mutex_unlock(&tp->control); 3524 3525 return ret; 3526 } 3527 3528 static int rtl8152_resume(struct usb_interface *intf) 3529 { 3530 struct r8152 *tp = usb_get_intfdata(intf); 3531 3532 mutex_lock(&tp->control); 3533 3534 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3535 tp->rtl_ops.init(tp); 3536 netif_device_attach(tp->netdev); 3537 } 3538 3539 if (netif_running(tp->netdev) && tp->netdev->flags & IFF_UP) { 3540 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3541 rtl_runtime_suspend_enable(tp, false); 3542 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3543 napi_disable(&tp->napi); 3544 set_bit(WORK_ENABLE, &tp->flags); 3545 if (netif_carrier_ok(tp->netdev)) 3546 rtl_start_rx(tp); 3547 napi_enable(&tp->napi); 3548 } else { 3549 tp->rtl_ops.up(tp); 3550 rtl8152_set_speed(tp, AUTONEG_ENABLE, 3551 tp->mii.supports_gmii ? 3552 SPEED_1000 : SPEED_100, 3553 DUPLEX_FULL); 3554 netif_carrier_off(tp->netdev); 3555 set_bit(WORK_ENABLE, &tp->flags); 3556 } 3557 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3558 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3559 if (tp->netdev->flags & IFF_UP) 3560 rtl_runtime_suspend_enable(tp, false); 3561 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3562 } 3563 3564 mutex_unlock(&tp->control); 3565 3566 return 0; 3567 } 3568 3569 static int rtl8152_reset_resume(struct usb_interface *intf) 3570 { 3571 struct r8152 *tp = usb_get_intfdata(intf); 3572 3573 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3574 return rtl8152_resume(intf); 3575 } 3576 3577 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3578 { 3579 struct r8152 *tp = netdev_priv(dev); 3580 3581 if (usb_autopm_get_interface(tp->intf) < 0) 3582 return; 3583 3584 if (!rtl_can_wakeup(tp)) { 3585 wol->supported = 0; 3586 wol->wolopts = 0; 3587 } else { 3588 mutex_lock(&tp->control); 3589 wol->supported = WAKE_ANY; 3590 wol->wolopts = __rtl_get_wol(tp); 3591 mutex_unlock(&tp->control); 3592 } 3593 3594 usb_autopm_put_interface(tp->intf); 3595 } 3596 3597 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3598 { 3599 struct r8152 *tp = netdev_priv(dev); 3600 int ret; 3601 3602 if (!rtl_can_wakeup(tp)) 3603 return -EOPNOTSUPP; 3604 3605 ret = usb_autopm_get_interface(tp->intf); 3606 if (ret < 0) 3607 goto out_set_wol; 3608 3609 mutex_lock(&tp->control); 3610 3611 __rtl_set_wol(tp, wol->wolopts); 3612 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 3613 3614 mutex_unlock(&tp->control); 3615 3616 usb_autopm_put_interface(tp->intf); 3617 3618 out_set_wol: 3619 return ret; 3620 } 3621 3622 static u32 rtl8152_get_msglevel(struct net_device *dev) 3623 { 3624 struct r8152 *tp = netdev_priv(dev); 3625 3626 return tp->msg_enable; 3627 } 3628 3629 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 3630 { 3631 struct r8152 *tp = netdev_priv(dev); 3632 3633 tp->msg_enable = value; 3634 } 3635 3636 static void rtl8152_get_drvinfo(struct net_device *netdev, 3637 struct ethtool_drvinfo *info) 3638 { 3639 struct r8152 *tp = netdev_priv(netdev); 3640 3641 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 3642 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 3643 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 3644 } 3645 3646 static 3647 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) 3648 { 3649 struct r8152 *tp = netdev_priv(netdev); 3650 int ret; 3651 3652 if (!tp->mii.mdio_read) 3653 return -EOPNOTSUPP; 3654 3655 ret = usb_autopm_get_interface(tp->intf); 3656 if (ret < 0) 3657 goto out; 3658 3659 mutex_lock(&tp->control); 3660 3661 ret = mii_ethtool_gset(&tp->mii, cmd); 3662 3663 mutex_unlock(&tp->control); 3664 3665 usb_autopm_put_interface(tp->intf); 3666 3667 out: 3668 return ret; 3669 } 3670 3671 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 3672 { 3673 struct r8152 *tp = netdev_priv(dev); 3674 int ret; 3675 3676 ret = usb_autopm_get_interface(tp->intf); 3677 if (ret < 0) 3678 goto out; 3679 3680 mutex_lock(&tp->control); 3681 3682 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); 3683 3684 mutex_unlock(&tp->control); 3685 3686 usb_autopm_put_interface(tp->intf); 3687 3688 out: 3689 return ret; 3690 } 3691 3692 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 3693 "tx_packets", 3694 "rx_packets", 3695 "tx_errors", 3696 "rx_errors", 3697 "rx_missed", 3698 "align_errors", 3699 "tx_single_collisions", 3700 "tx_multi_collisions", 3701 "rx_unicast", 3702 "rx_broadcast", 3703 "rx_multicast", 3704 "tx_aborted", 3705 "tx_underrun", 3706 }; 3707 3708 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 3709 { 3710 switch (sset) { 3711 case ETH_SS_STATS: 3712 return ARRAY_SIZE(rtl8152_gstrings); 3713 default: 3714 return -EOPNOTSUPP; 3715 } 3716 } 3717 3718 static void rtl8152_get_ethtool_stats(struct net_device *dev, 3719 struct ethtool_stats *stats, u64 *data) 3720 { 3721 struct r8152 *tp = netdev_priv(dev); 3722 struct tally_counter tally; 3723 3724 if (usb_autopm_get_interface(tp->intf) < 0) 3725 return; 3726 3727 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 3728 3729 usb_autopm_put_interface(tp->intf); 3730 3731 data[0] = le64_to_cpu(tally.tx_packets); 3732 data[1] = le64_to_cpu(tally.rx_packets); 3733 data[2] = le64_to_cpu(tally.tx_errors); 3734 data[3] = le32_to_cpu(tally.rx_errors); 3735 data[4] = le16_to_cpu(tally.rx_missed); 3736 data[5] = le16_to_cpu(tally.align_errors); 3737 data[6] = le32_to_cpu(tally.tx_one_collision); 3738 data[7] = le32_to_cpu(tally.tx_multi_collision); 3739 data[8] = le64_to_cpu(tally.rx_unicast); 3740 data[9] = le64_to_cpu(tally.rx_broadcast); 3741 data[10] = le32_to_cpu(tally.rx_multicast); 3742 data[11] = le16_to_cpu(tally.tx_aborted); 3743 data[12] = le16_to_cpu(tally.tx_underrun); 3744 } 3745 3746 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 3747 { 3748 switch (stringset) { 3749 case ETH_SS_STATS: 3750 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 3751 break; 3752 } 3753 } 3754 3755 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 3756 { 3757 u32 ocp_data, lp, adv, supported = 0; 3758 u16 val; 3759 3760 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 3761 supported = mmd_eee_cap_to_ethtool_sup_t(val); 3762 3763 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 3764 adv = mmd_eee_adv_to_ethtool_adv_t(val); 3765 3766 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 3767 lp = mmd_eee_adv_to_ethtool_adv_t(val); 3768 3769 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3770 ocp_data &= EEE_RX_EN | EEE_TX_EN; 3771 3772 eee->eee_enabled = !!ocp_data; 3773 eee->eee_active = !!(supported & adv & lp); 3774 eee->supported = supported; 3775 eee->advertised = adv; 3776 eee->lp_advertised = lp; 3777 3778 return 0; 3779 } 3780 3781 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 3782 { 3783 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 3784 3785 r8152_eee_en(tp, eee->eee_enabled); 3786 3787 if (!eee->eee_enabled) 3788 val = 0; 3789 3790 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); 3791 3792 return 0; 3793 } 3794 3795 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 3796 { 3797 u32 ocp_data, lp, adv, supported = 0; 3798 u16 val; 3799 3800 val = ocp_reg_read(tp, OCP_EEE_ABLE); 3801 supported = mmd_eee_cap_to_ethtool_sup_t(val); 3802 3803 val = ocp_reg_read(tp, OCP_EEE_ADV); 3804 adv = mmd_eee_adv_to_ethtool_adv_t(val); 3805 3806 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 3807 lp = mmd_eee_adv_to_ethtool_adv_t(val); 3808 3809 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3810 ocp_data &= EEE_RX_EN | EEE_TX_EN; 3811 3812 eee->eee_enabled = !!ocp_data; 3813 eee->eee_active = !!(supported & adv & lp); 3814 eee->supported = supported; 3815 eee->advertised = adv; 3816 eee->lp_advertised = lp; 3817 3818 return 0; 3819 } 3820 3821 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 3822 { 3823 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 3824 3825 r8153_eee_en(tp, eee->eee_enabled); 3826 3827 if (!eee->eee_enabled) 3828 val = 0; 3829 3830 ocp_reg_write(tp, OCP_EEE_ADV, val); 3831 3832 return 0; 3833 } 3834 3835 static int 3836 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) 3837 { 3838 struct r8152 *tp = netdev_priv(net); 3839 int ret; 3840 3841 ret = usb_autopm_get_interface(tp->intf); 3842 if (ret < 0) 3843 goto out; 3844 3845 mutex_lock(&tp->control); 3846 3847 ret = tp->rtl_ops.eee_get(tp, edata); 3848 3849 mutex_unlock(&tp->control); 3850 3851 usb_autopm_put_interface(tp->intf); 3852 3853 out: 3854 return ret; 3855 } 3856 3857 static int 3858 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) 3859 { 3860 struct r8152 *tp = netdev_priv(net); 3861 int ret; 3862 3863 ret = usb_autopm_get_interface(tp->intf); 3864 if (ret < 0) 3865 goto out; 3866 3867 mutex_lock(&tp->control); 3868 3869 ret = tp->rtl_ops.eee_set(tp, edata); 3870 if (!ret) 3871 ret = mii_nway_restart(&tp->mii); 3872 3873 mutex_unlock(&tp->control); 3874 3875 usb_autopm_put_interface(tp->intf); 3876 3877 out: 3878 return ret; 3879 } 3880 3881 static int rtl8152_nway_reset(struct net_device *dev) 3882 { 3883 struct r8152 *tp = netdev_priv(dev); 3884 int ret; 3885 3886 ret = usb_autopm_get_interface(tp->intf); 3887 if (ret < 0) 3888 goto out; 3889 3890 mutex_lock(&tp->control); 3891 3892 ret = mii_nway_restart(&tp->mii); 3893 3894 mutex_unlock(&tp->control); 3895 3896 usb_autopm_put_interface(tp->intf); 3897 3898 out: 3899 return ret; 3900 } 3901 3902 static int rtl8152_get_coalesce(struct net_device *netdev, 3903 struct ethtool_coalesce *coalesce) 3904 { 3905 struct r8152 *tp = netdev_priv(netdev); 3906 3907 switch (tp->version) { 3908 case RTL_VER_01: 3909 case RTL_VER_02: 3910 return -EOPNOTSUPP; 3911 default: 3912 break; 3913 } 3914 3915 coalesce->rx_coalesce_usecs = tp->coalesce; 3916 3917 return 0; 3918 } 3919 3920 static int rtl8152_set_coalesce(struct net_device *netdev, 3921 struct ethtool_coalesce *coalesce) 3922 { 3923 struct r8152 *tp = netdev_priv(netdev); 3924 int ret; 3925 3926 switch (tp->version) { 3927 case RTL_VER_01: 3928 case RTL_VER_02: 3929 return -EOPNOTSUPP; 3930 default: 3931 break; 3932 } 3933 3934 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) 3935 return -EINVAL; 3936 3937 ret = usb_autopm_get_interface(tp->intf); 3938 if (ret < 0) 3939 return ret; 3940 3941 mutex_lock(&tp->control); 3942 3943 if (tp->coalesce != coalesce->rx_coalesce_usecs) { 3944 tp->coalesce = coalesce->rx_coalesce_usecs; 3945 3946 if (netif_running(tp->netdev) && netif_carrier_ok(netdev)) 3947 r8153_set_rx_early_timeout(tp); 3948 } 3949 3950 mutex_unlock(&tp->control); 3951 3952 usb_autopm_put_interface(tp->intf); 3953 3954 return ret; 3955 } 3956 3957 static struct ethtool_ops ops = { 3958 .get_drvinfo = rtl8152_get_drvinfo, 3959 .get_settings = rtl8152_get_settings, 3960 .set_settings = rtl8152_set_settings, 3961 .get_link = ethtool_op_get_link, 3962 .nway_reset = rtl8152_nway_reset, 3963 .get_msglevel = rtl8152_get_msglevel, 3964 .set_msglevel = rtl8152_set_msglevel, 3965 .get_wol = rtl8152_get_wol, 3966 .set_wol = rtl8152_set_wol, 3967 .get_strings = rtl8152_get_strings, 3968 .get_sset_count = rtl8152_get_sset_count, 3969 .get_ethtool_stats = rtl8152_get_ethtool_stats, 3970 .get_coalesce = rtl8152_get_coalesce, 3971 .set_coalesce = rtl8152_set_coalesce, 3972 .get_eee = rtl_ethtool_get_eee, 3973 .set_eee = rtl_ethtool_set_eee, 3974 }; 3975 3976 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 3977 { 3978 struct r8152 *tp = netdev_priv(netdev); 3979 struct mii_ioctl_data *data = if_mii(rq); 3980 int res; 3981 3982 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3983 return -ENODEV; 3984 3985 res = usb_autopm_get_interface(tp->intf); 3986 if (res < 0) 3987 goto out; 3988 3989 switch (cmd) { 3990 case SIOCGMIIPHY: 3991 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 3992 break; 3993 3994 case SIOCGMIIREG: 3995 mutex_lock(&tp->control); 3996 data->val_out = r8152_mdio_read(tp, data->reg_num); 3997 mutex_unlock(&tp->control); 3998 break; 3999 4000 case SIOCSMIIREG: 4001 if (!capable(CAP_NET_ADMIN)) { 4002 res = -EPERM; 4003 break; 4004 } 4005 mutex_lock(&tp->control); 4006 r8152_mdio_write(tp, data->reg_num, data->val_in); 4007 mutex_unlock(&tp->control); 4008 break; 4009 4010 default: 4011 res = -EOPNOTSUPP; 4012 } 4013 4014 usb_autopm_put_interface(tp->intf); 4015 4016 out: 4017 return res; 4018 } 4019 4020 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 4021 { 4022 struct r8152 *tp = netdev_priv(dev); 4023 int ret; 4024 4025 switch (tp->version) { 4026 case RTL_VER_01: 4027 case RTL_VER_02: 4028 return eth_change_mtu(dev, new_mtu); 4029 default: 4030 break; 4031 } 4032 4033 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU) 4034 return -EINVAL; 4035 4036 ret = usb_autopm_get_interface(tp->intf); 4037 if (ret < 0) 4038 return ret; 4039 4040 mutex_lock(&tp->control); 4041 4042 dev->mtu = new_mtu; 4043 4044 if (netif_running(dev) && netif_carrier_ok(dev)) 4045 r8153_set_rx_early_size(tp); 4046 4047 mutex_unlock(&tp->control); 4048 4049 usb_autopm_put_interface(tp->intf); 4050 4051 return ret; 4052 } 4053 4054 static const struct net_device_ops rtl8152_netdev_ops = { 4055 .ndo_open = rtl8152_open, 4056 .ndo_stop = rtl8152_close, 4057 .ndo_do_ioctl = rtl8152_ioctl, 4058 .ndo_start_xmit = rtl8152_start_xmit, 4059 .ndo_tx_timeout = rtl8152_tx_timeout, 4060 .ndo_set_features = rtl8152_set_features, 4061 .ndo_set_rx_mode = rtl8152_set_rx_mode, 4062 .ndo_set_mac_address = rtl8152_set_mac_address, 4063 .ndo_change_mtu = rtl8152_change_mtu, 4064 .ndo_validate_addr = eth_validate_addr, 4065 .ndo_features_check = rtl8152_features_check, 4066 }; 4067 4068 static void r8152b_get_version(struct r8152 *tp) 4069 { 4070 u32 ocp_data; 4071 u16 version; 4072 4073 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); 4074 version = (u16)(ocp_data & VERSION_MASK); 4075 4076 switch (version) { 4077 case 0x4c00: 4078 tp->version = RTL_VER_01; 4079 break; 4080 case 0x4c10: 4081 tp->version = RTL_VER_02; 4082 break; 4083 case 0x5c00: 4084 tp->version = RTL_VER_03; 4085 tp->mii.supports_gmii = 1; 4086 break; 4087 case 0x5c10: 4088 tp->version = RTL_VER_04; 4089 tp->mii.supports_gmii = 1; 4090 break; 4091 case 0x5c20: 4092 tp->version = RTL_VER_05; 4093 tp->mii.supports_gmii = 1; 4094 break; 4095 case 0x5c30: 4096 tp->version = RTL_VER_06; 4097 tp->mii.supports_gmii = 1; 4098 break; 4099 default: 4100 netif_info(tp, probe, tp->netdev, 4101 "Unknown version 0x%04x\n", version); 4102 break; 4103 } 4104 } 4105 4106 static void rtl8152_unload(struct r8152 *tp) 4107 { 4108 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4109 return; 4110 4111 if (tp->version != RTL_VER_01) 4112 r8152_power_cut_en(tp, true); 4113 } 4114 4115 static void rtl8153_unload(struct r8152 *tp) 4116 { 4117 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4118 return; 4119 4120 r8153_power_cut_en(tp, false); 4121 } 4122 4123 static int rtl_ops_init(struct r8152 *tp) 4124 { 4125 struct rtl_ops *ops = &tp->rtl_ops; 4126 int ret = 0; 4127 4128 switch (tp->version) { 4129 case RTL_VER_01: 4130 case RTL_VER_02: 4131 ops->init = r8152b_init; 4132 ops->enable = rtl8152_enable; 4133 ops->disable = rtl8152_disable; 4134 ops->up = rtl8152_up; 4135 ops->down = rtl8152_down; 4136 ops->unload = rtl8152_unload; 4137 ops->eee_get = r8152_get_eee; 4138 ops->eee_set = r8152_set_eee; 4139 ops->in_nway = rtl8152_in_nway; 4140 break; 4141 4142 case RTL_VER_03: 4143 case RTL_VER_04: 4144 case RTL_VER_05: 4145 case RTL_VER_06: 4146 ops->init = r8153_init; 4147 ops->enable = rtl8153_enable; 4148 ops->disable = rtl8153_disable; 4149 ops->up = rtl8153_up; 4150 ops->down = rtl8153_down; 4151 ops->unload = rtl8153_unload; 4152 ops->eee_get = r8153_get_eee; 4153 ops->eee_set = r8153_set_eee; 4154 ops->in_nway = rtl8153_in_nway; 4155 break; 4156 4157 default: 4158 ret = -ENODEV; 4159 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 4160 break; 4161 } 4162 4163 return ret; 4164 } 4165 4166 static int rtl8152_probe(struct usb_interface *intf, 4167 const struct usb_device_id *id) 4168 { 4169 struct usb_device *udev = interface_to_usbdev(intf); 4170 struct r8152 *tp; 4171 struct net_device *netdev; 4172 int ret; 4173 4174 if (udev->actconfig->desc.bConfigurationValue != 1) { 4175 usb_driver_set_configuration(udev, 1); 4176 return -ENODEV; 4177 } 4178 4179 usb_reset_device(udev); 4180 netdev = alloc_etherdev(sizeof(struct r8152)); 4181 if (!netdev) { 4182 dev_err(&intf->dev, "Out of memory\n"); 4183 return -ENOMEM; 4184 } 4185 4186 SET_NETDEV_DEV(netdev, &intf->dev); 4187 tp = netdev_priv(netdev); 4188 tp->msg_enable = 0x7FFF; 4189 4190 tp->udev = udev; 4191 tp->netdev = netdev; 4192 tp->intf = intf; 4193 4194 r8152b_get_version(tp); 4195 ret = rtl_ops_init(tp); 4196 if (ret) 4197 goto out; 4198 4199 mutex_init(&tp->control); 4200 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 4201 4202 netdev->netdev_ops = &rtl8152_netdev_ops; 4203 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 4204 4205 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 4206 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 4207 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 4208 NETIF_F_HW_VLAN_CTAG_TX; 4209 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 4210 NETIF_F_TSO | NETIF_F_FRAGLIST | 4211 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 4212 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; 4213 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 4214 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 4215 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 4216 4217 netdev->ethtool_ops = &ops; 4218 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 4219 4220 tp->mii.dev = netdev; 4221 tp->mii.mdio_read = read_mii_word; 4222 tp->mii.mdio_write = write_mii_word; 4223 tp->mii.phy_id_mask = 0x3f; 4224 tp->mii.reg_num_mask = 0x1f; 4225 tp->mii.phy_id = R8152_PHY_ID; 4226 4227 switch (udev->speed) { 4228 case USB_SPEED_SUPER: 4229 case USB_SPEED_SUPER_PLUS: 4230 tp->coalesce = COALESCE_SUPER; 4231 break; 4232 case USB_SPEED_HIGH: 4233 tp->coalesce = COALESCE_HIGH; 4234 break; 4235 default: 4236 tp->coalesce = COALESCE_SLOW; 4237 break; 4238 } 4239 4240 intf->needs_remote_wakeup = 1; 4241 4242 tp->rtl_ops.init(tp); 4243 set_ethernet_addr(tp); 4244 4245 usb_set_intfdata(intf, tp); 4246 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); 4247 4248 ret = register_netdev(netdev); 4249 if (ret != 0) { 4250 netif_err(tp, probe, netdev, "couldn't register the device\n"); 4251 goto out1; 4252 } 4253 4254 if (!rtl_can_wakeup(tp)) 4255 __rtl_set_wol(tp, 0); 4256 4257 tp->saved_wolopts = __rtl_get_wol(tp); 4258 if (tp->saved_wolopts) 4259 device_set_wakeup_enable(&udev->dev, true); 4260 else 4261 device_set_wakeup_enable(&udev->dev, false); 4262 4263 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 4264 4265 return 0; 4266 4267 out1: 4268 netif_napi_del(&tp->napi); 4269 usb_set_intfdata(intf, NULL); 4270 out: 4271 free_netdev(netdev); 4272 return ret; 4273 } 4274 4275 static void rtl8152_disconnect(struct usb_interface *intf) 4276 { 4277 struct r8152 *tp = usb_get_intfdata(intf); 4278 4279 usb_set_intfdata(intf, NULL); 4280 if (tp) { 4281 struct usb_device *udev = tp->udev; 4282 4283 if (udev->state == USB_STATE_NOTATTACHED) 4284 set_bit(RTL8152_UNPLUG, &tp->flags); 4285 4286 netif_napi_del(&tp->napi); 4287 unregister_netdev(tp->netdev); 4288 tp->rtl_ops.unload(tp); 4289 free_netdev(tp->netdev); 4290 } 4291 } 4292 4293 #define REALTEK_USB_DEVICE(vend, prod) \ 4294 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ 4295 USB_DEVICE_ID_MATCH_INT_CLASS, \ 4296 .idVendor = (vend), \ 4297 .idProduct = (prod), \ 4298 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ 4299 }, \ 4300 { \ 4301 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ 4302 USB_DEVICE_ID_MATCH_DEVICE, \ 4303 .idVendor = (vend), \ 4304 .idProduct = (prod), \ 4305 .bInterfaceClass = USB_CLASS_COMM, \ 4306 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ 4307 .bInterfaceProtocol = USB_CDC_PROTO_NONE 4308 4309 /* table of devices that work with this driver */ 4310 static struct usb_device_id rtl8152_table[] = { 4311 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, 4312 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, 4313 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, 4314 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, 4315 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, 4316 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, 4317 {} 4318 }; 4319 4320 MODULE_DEVICE_TABLE(usb, rtl8152_table); 4321 4322 static struct usb_driver rtl8152_driver = { 4323 .name = MODULENAME, 4324 .id_table = rtl8152_table, 4325 .probe = rtl8152_probe, 4326 .disconnect = rtl8152_disconnect, 4327 .suspend = rtl8152_suspend, 4328 .resume = rtl8152_resume, 4329 .reset_resume = rtl8152_reset_resume, 4330 .pre_reset = rtl8152_pre_reset, 4331 .post_reset = rtl8152_post_reset, 4332 .supports_autosuspend = 1, 4333 .disable_hub_initiated_lpm = 1, 4334 }; 4335 4336 module_usb_driver(rtl8152_driver); 4337 4338 MODULE_AUTHOR(DRIVER_AUTHOR); 4339 MODULE_DESCRIPTION(DRIVER_DESC); 4340 MODULE_LICENSE("GPL"); 4341