1 /* 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2 as published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/signal.h> 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/usb.h> 18 #include <linux/crc32.h> 19 #include <linux/if_vlan.h> 20 #include <linux/uaccess.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include <net/ip6_checksum.h> 25 26 /* Version Information */ 27 #define DRIVER_VERSION "v1.06.0 (2014/03/03)" 28 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 29 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 30 #define MODULENAME "r8152" 31 32 #define R8152_PHY_ID 32 33 34 #define PLA_IDR 0xc000 35 #define PLA_RCR 0xc010 36 #define PLA_RMS 0xc016 37 #define PLA_RXFIFO_CTRL0 0xc0a0 38 #define PLA_RXFIFO_CTRL1 0xc0a4 39 #define PLA_RXFIFO_CTRL2 0xc0a8 40 #define PLA_FMC 0xc0b4 41 #define PLA_CFG_WOL 0xc0b6 42 #define PLA_TEREDO_CFG 0xc0bc 43 #define PLA_MAR 0xcd00 44 #define PLA_BACKUP 0xd000 45 #define PAL_BDC_CR 0xd1a0 46 #define PLA_TEREDO_TIMER 0xd2cc 47 #define PLA_REALWOW_TIMER 0xd2e8 48 #define PLA_LEDSEL 0xdd90 49 #define PLA_LED_FEATURE 0xdd92 50 #define PLA_PHYAR 0xde00 51 #define PLA_BOOT_CTRL 0xe004 52 #define PLA_GPHY_INTR_IMR 0xe022 53 #define PLA_EEE_CR 0xe040 54 #define PLA_EEEP_CR 0xe080 55 #define PLA_MAC_PWR_CTRL 0xe0c0 56 #define PLA_MAC_PWR_CTRL2 0xe0ca 57 #define PLA_MAC_PWR_CTRL3 0xe0cc 58 #define PLA_MAC_PWR_CTRL4 0xe0ce 59 #define PLA_WDT6_CTRL 0xe428 60 #define PLA_TCR0 0xe610 61 #define PLA_TCR1 0xe612 62 #define PLA_TXFIFO_CTRL 0xe618 63 #define PLA_RSTTALLY 0xe800 64 #define PLA_CR 0xe813 65 #define PLA_CRWECR 0xe81c 66 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 67 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 68 #define PLA_CONFIG5 0xe822 69 #define PLA_PHY_PWR 0xe84c 70 #define PLA_OOB_CTRL 0xe84f 71 #define PLA_CPCR 0xe854 72 #define PLA_MISC_0 0xe858 73 #define PLA_MISC_1 0xe85a 74 #define PLA_OCP_GPHY_BASE 0xe86c 75 #define PLA_TALLYCNT 0xe890 76 #define PLA_SFF_STS_7 0xe8de 77 #define PLA_PHYSTATUS 0xe908 78 #define PLA_BP_BA 0xfc26 79 #define PLA_BP_0 0xfc28 80 #define PLA_BP_1 0xfc2a 81 #define PLA_BP_2 0xfc2c 82 #define PLA_BP_3 0xfc2e 83 #define PLA_BP_4 0xfc30 84 #define PLA_BP_5 0xfc32 85 #define PLA_BP_6 0xfc34 86 #define PLA_BP_7 0xfc36 87 #define PLA_BP_EN 0xfc38 88 89 #define USB_U2P3_CTRL 0xb460 90 #define USB_DEV_STAT 0xb808 91 #define USB_USB_CTRL 0xd406 92 #define USB_PHY_CTRL 0xd408 93 #define USB_TX_AGG 0xd40a 94 #define USB_RX_BUF_TH 0xd40c 95 #define USB_USB_TIMER 0xd428 96 #define USB_RX_EARLY_AGG 0xd42c 97 #define USB_PM_CTRL_STATUS 0xd432 98 #define USB_TX_DMA 0xd434 99 #define USB_TOLERANCE 0xd490 100 #define USB_LPM_CTRL 0xd41a 101 #define USB_UPS_CTRL 0xd800 102 #define USB_MISC_0 0xd81a 103 #define USB_POWER_CUT 0xd80a 104 #define USB_AFE_CTRL2 0xd824 105 #define USB_WDT11_CTRL 0xe43c 106 #define USB_BP_BA 0xfc26 107 #define USB_BP_0 0xfc28 108 #define USB_BP_1 0xfc2a 109 #define USB_BP_2 0xfc2c 110 #define USB_BP_3 0xfc2e 111 #define USB_BP_4 0xfc30 112 #define USB_BP_5 0xfc32 113 #define USB_BP_6 0xfc34 114 #define USB_BP_7 0xfc36 115 #define USB_BP_EN 0xfc38 116 117 /* OCP Registers */ 118 #define OCP_ALDPS_CONFIG 0x2010 119 #define OCP_EEE_CONFIG1 0x2080 120 #define OCP_EEE_CONFIG2 0x2092 121 #define OCP_EEE_CONFIG3 0x2094 122 #define OCP_BASE_MII 0xa400 123 #define OCP_EEE_AR 0xa41a 124 #define OCP_EEE_DATA 0xa41c 125 #define OCP_PHY_STATUS 0xa420 126 #define OCP_POWER_CFG 0xa430 127 #define OCP_EEE_CFG 0xa432 128 #define OCP_SRAM_ADDR 0xa436 129 #define OCP_SRAM_DATA 0xa438 130 #define OCP_DOWN_SPEED 0xa442 131 #define OCP_EEE_CFG2 0xa5d0 132 #define OCP_ADC_CFG 0xbc06 133 134 /* SRAM Register */ 135 #define SRAM_LPF_CFG 0x8012 136 #define SRAM_10M_AMP1 0x8080 137 #define SRAM_10M_AMP2 0x8082 138 #define SRAM_IMPEDANCE 0x8084 139 140 /* PLA_RCR */ 141 #define RCR_AAP 0x00000001 142 #define RCR_APM 0x00000002 143 #define RCR_AM 0x00000004 144 #define RCR_AB 0x00000008 145 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 146 147 /* PLA_RXFIFO_CTRL0 */ 148 #define RXFIFO_THR1_NORMAL 0x00080002 149 #define RXFIFO_THR1_OOB 0x01800003 150 151 /* PLA_RXFIFO_CTRL1 */ 152 #define RXFIFO_THR2_FULL 0x00000060 153 #define RXFIFO_THR2_HIGH 0x00000038 154 #define RXFIFO_THR2_OOB 0x0000004a 155 #define RXFIFO_THR2_NORMAL 0x00a0 156 157 /* PLA_RXFIFO_CTRL2 */ 158 #define RXFIFO_THR3_FULL 0x00000078 159 #define RXFIFO_THR3_HIGH 0x00000048 160 #define RXFIFO_THR3_OOB 0x0000005a 161 #define RXFIFO_THR3_NORMAL 0x0110 162 163 /* PLA_TXFIFO_CTRL */ 164 #define TXFIFO_THR_NORMAL 0x00400008 165 #define TXFIFO_THR_NORMAL2 0x01000008 166 167 /* PLA_FMC */ 168 #define FMC_FCR_MCU_EN 0x0001 169 170 /* PLA_EEEP_CR */ 171 #define EEEP_CR_EEEP_TX 0x0002 172 173 /* PLA_WDT6_CTRL */ 174 #define WDT6_SET_MODE 0x0010 175 176 /* PLA_TCR0 */ 177 #define TCR0_TX_EMPTY 0x0800 178 #define TCR0_AUTO_FIFO 0x0080 179 180 /* PLA_TCR1 */ 181 #define VERSION_MASK 0x7cf0 182 183 /* PLA_RSTTALLY */ 184 #define TALLY_RESET 0x0001 185 186 /* PLA_CR */ 187 #define CR_RST 0x10 188 #define CR_RE 0x08 189 #define CR_TE 0x04 190 191 /* PLA_CRWECR */ 192 #define CRWECR_NORAML 0x00 193 #define CRWECR_CONFIG 0xc0 194 195 /* PLA_OOB_CTRL */ 196 #define NOW_IS_OOB 0x80 197 #define TXFIFO_EMPTY 0x20 198 #define RXFIFO_EMPTY 0x10 199 #define LINK_LIST_READY 0x02 200 #define DIS_MCU_CLROOB 0x01 201 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 202 203 /* PLA_MISC_1 */ 204 #define RXDY_GATED_EN 0x0008 205 206 /* PLA_SFF_STS_7 */ 207 #define RE_INIT_LL 0x8000 208 #define MCU_BORW_EN 0x4000 209 210 /* PLA_CPCR */ 211 #define CPCR_RX_VLAN 0x0040 212 213 /* PLA_CFG_WOL */ 214 #define MAGIC_EN 0x0001 215 216 /* PLA_TEREDO_CFG */ 217 #define TEREDO_SEL 0x8000 218 #define TEREDO_WAKE_MASK 0x7f00 219 #define TEREDO_RS_EVENT_MASK 0x00fe 220 #define OOB_TEREDO_EN 0x0001 221 222 /* PAL_BDC_CR */ 223 #define ALDPS_PROXY_MODE 0x0001 224 225 /* PLA_CONFIG34 */ 226 #define LINK_ON_WAKE_EN 0x0010 227 #define LINK_OFF_WAKE_EN 0x0008 228 229 /* PLA_CONFIG5 */ 230 #define BWF_EN 0x0040 231 #define MWF_EN 0x0020 232 #define UWF_EN 0x0010 233 #define LAN_WAKE_EN 0x0002 234 235 /* PLA_LED_FEATURE */ 236 #define LED_MODE_MASK 0x0700 237 238 /* PLA_PHY_PWR */ 239 #define TX_10M_IDLE_EN 0x0080 240 #define PFM_PWM_SWITCH 0x0040 241 242 /* PLA_MAC_PWR_CTRL */ 243 #define D3_CLK_GATED_EN 0x00004000 244 #define MCU_CLK_RATIO 0x07010f07 245 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 246 #define ALDPS_SPDWN_RATIO 0x0f87 247 248 /* PLA_MAC_PWR_CTRL2 */ 249 #define EEE_SPDWN_RATIO 0x8007 250 251 /* PLA_MAC_PWR_CTRL3 */ 252 #define PKT_AVAIL_SPDWN_EN 0x0100 253 #define SUSPEND_SPDWN_EN 0x0004 254 #define U1U2_SPDWN_EN 0x0002 255 #define L1_SPDWN_EN 0x0001 256 257 /* PLA_MAC_PWR_CTRL4 */ 258 #define PWRSAVE_SPDWN_EN 0x1000 259 #define RXDV_SPDWN_EN 0x0800 260 #define TX10MIDLE_EN 0x0100 261 #define TP100_SPDWN_EN 0x0020 262 #define TP500_SPDWN_EN 0x0010 263 #define TP1000_SPDWN_EN 0x0008 264 #define EEE_SPDWN_EN 0x0001 265 266 /* PLA_GPHY_INTR_IMR */ 267 #define GPHY_STS_MSK 0x0001 268 #define SPEED_DOWN_MSK 0x0002 269 #define SPDWN_RXDV_MSK 0x0004 270 #define SPDWN_LINKCHG_MSK 0x0008 271 272 /* PLA_PHYAR */ 273 #define PHYAR_FLAG 0x80000000 274 275 /* PLA_EEE_CR */ 276 #define EEE_RX_EN 0x0001 277 #define EEE_TX_EN 0x0002 278 279 /* PLA_BOOT_CTRL */ 280 #define AUTOLOAD_DONE 0x0002 281 282 /* USB_DEV_STAT */ 283 #define STAT_SPEED_MASK 0x0006 284 #define STAT_SPEED_HIGH 0x0000 285 #define STAT_SPEED_FULL 0x0001 286 287 /* USB_TX_AGG */ 288 #define TX_AGG_MAX_THRESHOLD 0x03 289 290 /* USB_RX_BUF_TH */ 291 #define RX_THR_SUPPER 0x0c350180 292 #define RX_THR_HIGH 0x7a120180 293 #define RX_THR_SLOW 0xffff0180 294 295 /* USB_TX_DMA */ 296 #define TEST_MODE_DISABLE 0x00000001 297 #define TX_SIZE_ADJUST1 0x00000100 298 299 /* USB_UPS_CTRL */ 300 #define POWER_CUT 0x0100 301 302 /* USB_PM_CTRL_STATUS */ 303 #define RESUME_INDICATE 0x0001 304 305 /* USB_USB_CTRL */ 306 #define RX_AGG_DISABLE 0x0010 307 308 /* USB_U2P3_CTRL */ 309 #define U2P3_ENABLE 0x0001 310 311 /* USB_POWER_CUT */ 312 #define PWR_EN 0x0001 313 #define PHASE2_EN 0x0008 314 315 /* USB_MISC_0 */ 316 #define PCUT_STATUS 0x0001 317 318 /* USB_RX_EARLY_AGG */ 319 #define EARLY_AGG_SUPPER 0x0e832981 320 #define EARLY_AGG_HIGH 0x0e837a12 321 #define EARLY_AGG_SLOW 0x0e83ffff 322 323 /* USB_WDT11_CTRL */ 324 #define TIMER11_EN 0x0001 325 326 /* USB_LPM_CTRL */ 327 #define LPM_TIMER_MASK 0x0c 328 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 329 #define LPM_TIMER_500US 0x0c /* 500 us */ 330 331 /* USB_AFE_CTRL2 */ 332 #define SEN_VAL_MASK 0xf800 333 #define SEN_VAL_NORMAL 0xa000 334 #define SEL_RXIDLE 0x0100 335 336 /* OCP_ALDPS_CONFIG */ 337 #define ENPWRSAVE 0x8000 338 #define ENPDNPS 0x0200 339 #define LINKENA 0x0100 340 #define DIS_SDSAVE 0x0010 341 342 /* OCP_PHY_STATUS */ 343 #define PHY_STAT_MASK 0x0007 344 #define PHY_STAT_LAN_ON 3 345 #define PHY_STAT_PWRDN 5 346 347 /* OCP_POWER_CFG */ 348 #define EEE_CLKDIV_EN 0x8000 349 #define EN_ALDPS 0x0004 350 #define EN_10M_PLLOFF 0x0001 351 352 /* OCP_EEE_CONFIG1 */ 353 #define RG_TXLPI_MSK_HFDUP 0x8000 354 #define RG_MATCLR_EN 0x4000 355 #define EEE_10_CAP 0x2000 356 #define EEE_NWAY_EN 0x1000 357 #define TX_QUIET_EN 0x0200 358 #define RX_QUIET_EN 0x0100 359 #define SDRISETIME 0x0010 /* bit 4 ~ 6 */ 360 #define RG_RXLPI_MSK_HFDUP 0x0008 361 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 362 363 /* OCP_EEE_CONFIG2 */ 364 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 365 #define RG_DACQUIET_EN 0x0400 366 #define RG_LDVQUIET_EN 0x0200 367 #define RG_CKRSEL 0x0020 368 #define RG_EEEPRG_EN 0x0010 369 370 /* OCP_EEE_CONFIG3 */ 371 #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */ 372 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 373 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 374 375 /* OCP_EEE_AR */ 376 /* bit[15:14] function */ 377 #define FUN_ADDR 0x0000 378 #define FUN_DATA 0x4000 379 /* bit[4:0] device addr */ 380 #define DEVICE_ADDR 0x0007 381 382 /* OCP_EEE_DATA */ 383 #define EEE_ADDR 0x003C 384 #define EEE_DATA 0x0002 385 386 /* OCP_EEE_CFG */ 387 #define CTAP_SHORT_EN 0x0040 388 #define EEE10_EN 0x0010 389 390 /* OCP_DOWN_SPEED */ 391 #define EN_10M_BGOFF 0x0080 392 393 /* OCP_EEE_CFG2 */ 394 #define MY1000_EEE 0x0004 395 #define MY100_EEE 0x0002 396 397 /* OCP_ADC_CFG */ 398 #define CKADSEL_L 0x0100 399 #define ADC_EN 0x0080 400 #define EN_EMI_L 0x0040 401 402 /* SRAM_LPF_CFG */ 403 #define LPF_AUTO_TUNE 0x8000 404 405 /* SRAM_10M_AMP1 */ 406 #define GDAC_IB_UPALL 0x0008 407 408 /* SRAM_10M_AMP2 */ 409 #define AMP_DN 0x0200 410 411 /* SRAM_IMPEDANCE */ 412 #define RX_DRIVING_MASK 0x6000 413 414 enum rtl_register_content { 415 _1000bps = 0x10, 416 _100bps = 0x08, 417 _10bps = 0x04, 418 LINK_STATUS = 0x02, 419 FULL_DUP = 0x01, 420 }; 421 422 #define RTL8152_MAX_TX 10 423 #define RTL8152_MAX_RX 10 424 #define INTBUFSIZE 2 425 #define CRC_SIZE 4 426 #define TX_ALIGN 4 427 #define RX_ALIGN 8 428 429 #define INTR_LINK 0x0004 430 431 #define RTL8152_REQT_READ 0xc0 432 #define RTL8152_REQT_WRITE 0x40 433 #define RTL8152_REQ_GET_REGS 0x05 434 #define RTL8152_REQ_SET_REGS 0x05 435 436 #define BYTE_EN_DWORD 0xff 437 #define BYTE_EN_WORD 0x33 438 #define BYTE_EN_BYTE 0x11 439 #define BYTE_EN_SIX_BYTES 0x3f 440 #define BYTE_EN_START_MASK 0x0f 441 #define BYTE_EN_END_MASK 0xf0 442 443 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) 444 #define RTL8152_TX_TIMEOUT (HZ) 445 446 /* rtl8152 flags */ 447 enum rtl8152_flags { 448 RTL8152_UNPLUG = 0, 449 RTL8152_SET_RX_MODE, 450 WORK_ENABLE, 451 RTL8152_LINK_CHG, 452 SELECTIVE_SUSPEND, 453 PHY_RESET, 454 SCHEDULE_TASKLET, 455 }; 456 457 /* Define these values to match your device */ 458 #define VENDOR_ID_REALTEK 0x0bda 459 #define PRODUCT_ID_RTL8152 0x8152 460 #define PRODUCT_ID_RTL8153 0x8153 461 462 #define VENDOR_ID_SAMSUNG 0x04e8 463 #define PRODUCT_ID_SAMSUNG 0xa101 464 465 #define MCU_TYPE_PLA 0x0100 466 #define MCU_TYPE_USB 0x0000 467 468 #define REALTEK_USB_DEVICE(vend, prod) \ 469 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC) 470 471 struct tally_counter { 472 __le64 tx_packets; 473 __le64 rx_packets; 474 __le64 tx_errors; 475 __le32 rx_errors; 476 __le16 rx_missed; 477 __le16 align_errors; 478 __le32 tx_one_collision; 479 __le32 tx_multi_collision; 480 __le64 rx_unicast; 481 __le64 rx_broadcast; 482 __le32 rx_multicast; 483 __le16 tx_aborted; 484 __le16 tx_underun; 485 }; 486 487 struct rx_desc { 488 __le32 opts1; 489 #define RX_LEN_MASK 0x7fff 490 491 __le32 opts2; 492 #define RD_UDP_CS (1 << 23) 493 #define RD_TCP_CS (1 << 22) 494 #define RD_IPV6_CS (1 << 20) 495 #define RD_IPV4_CS (1 << 19) 496 497 __le32 opts3; 498 #define IPF (1 << 23) /* IP checksum fail */ 499 #define UDPF (1 << 22) /* UDP checksum fail */ 500 #define TCPF (1 << 21) /* TCP checksum fail */ 501 502 __le32 opts4; 503 __le32 opts5; 504 __le32 opts6; 505 }; 506 507 struct tx_desc { 508 __le32 opts1; 509 #define TX_FS (1 << 31) /* First segment of a packet */ 510 #define TX_LS (1 << 30) /* Final segment of a packet */ 511 #define GTSENDV4 (1 << 28) 512 #define GTSENDV6 (1 << 27) 513 #define GTTCPHO_SHIFT 18 514 #define GTTCPHO_MAX 0x7fU 515 #define TX_LEN_MAX 0x3ffffU 516 517 __le32 opts2; 518 #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */ 519 #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */ 520 #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */ 521 #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */ 522 #define MSS_SHIFT 17 523 #define MSS_MAX 0x7ffU 524 #define TCPHO_SHIFT 17 525 #define TCPHO_MAX 0x7ffU 526 }; 527 528 struct r8152; 529 530 struct rx_agg { 531 struct list_head list; 532 struct urb *urb; 533 struct r8152 *context; 534 void *buffer; 535 void *head; 536 }; 537 538 struct tx_agg { 539 struct list_head list; 540 struct urb *urb; 541 struct r8152 *context; 542 void *buffer; 543 void *head; 544 u32 skb_num; 545 u32 skb_len; 546 }; 547 548 struct r8152 { 549 unsigned long flags; 550 struct usb_device *udev; 551 struct tasklet_struct tl; 552 struct usb_interface *intf; 553 struct net_device *netdev; 554 struct urb *intr_urb; 555 struct tx_agg tx_info[RTL8152_MAX_TX]; 556 struct rx_agg rx_info[RTL8152_MAX_RX]; 557 struct list_head rx_done, tx_free; 558 struct sk_buff_head tx_queue; 559 spinlock_t rx_lock, tx_lock; 560 struct delayed_work schedule; 561 struct mii_if_info mii; 562 563 struct rtl_ops { 564 void (*init)(struct r8152 *); 565 int (*enable)(struct r8152 *); 566 void (*disable)(struct r8152 *); 567 void (*up)(struct r8152 *); 568 void (*down)(struct r8152 *); 569 void (*unload)(struct r8152 *); 570 } rtl_ops; 571 572 int intr_interval; 573 u32 saved_wolopts; 574 u32 msg_enable; 575 u32 tx_qlen; 576 u16 ocp_base; 577 u8 *intr_buff; 578 u8 version; 579 u8 speed; 580 }; 581 582 enum rtl_version { 583 RTL_VER_UNKNOWN = 0, 584 RTL_VER_01, 585 RTL_VER_02, 586 RTL_VER_03, 587 RTL_VER_04, 588 RTL_VER_05, 589 RTL_VER_MAX 590 }; 591 592 enum tx_csum_stat { 593 TX_CSUM_SUCCESS = 0, 594 TX_CSUM_TSO, 595 TX_CSUM_NONE 596 }; 597 598 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 599 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 600 */ 601 static const int multicast_filter_limit = 32; 602 static unsigned int rx_buf_sz = 16384; 603 604 #define RTL_LIMITED_TSO_SIZE (rx_buf_sz - sizeof(struct tx_desc) - \ 605 VLAN_ETH_HLEN - VLAN_HLEN) 606 607 static 608 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 609 { 610 int ret; 611 void *tmp; 612 613 tmp = kmalloc(size, GFP_KERNEL); 614 if (!tmp) 615 return -ENOMEM; 616 617 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 618 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 619 value, index, tmp, size, 500); 620 621 memcpy(data, tmp, size); 622 kfree(tmp); 623 624 return ret; 625 } 626 627 static 628 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 629 { 630 int ret; 631 void *tmp; 632 633 tmp = kmalloc(size, GFP_KERNEL); 634 if (!tmp) 635 return -ENOMEM; 636 637 memcpy(tmp, data, size); 638 639 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 640 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 641 value, index, tmp, size, 500); 642 643 kfree(tmp); 644 645 return ret; 646 } 647 648 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 649 void *data, u16 type) 650 { 651 u16 limit = 64; 652 int ret = 0; 653 654 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 655 return -ENODEV; 656 657 /* both size and indix must be 4 bytes align */ 658 if ((size & 3) || !size || (index & 3) || !data) 659 return -EPERM; 660 661 if ((u32)index + (u32)size > 0xffff) 662 return -EPERM; 663 664 while (size) { 665 if (size > limit) { 666 ret = get_registers(tp, index, type, limit, data); 667 if (ret < 0) 668 break; 669 670 index += limit; 671 data += limit; 672 size -= limit; 673 } else { 674 ret = get_registers(tp, index, type, size, data); 675 if (ret < 0) 676 break; 677 678 index += size; 679 data += size; 680 size = 0; 681 break; 682 } 683 } 684 685 return ret; 686 } 687 688 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 689 u16 size, void *data, u16 type) 690 { 691 int ret; 692 u16 byteen_start, byteen_end, byen; 693 u16 limit = 512; 694 695 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 696 return -ENODEV; 697 698 /* both size and indix must be 4 bytes align */ 699 if ((size & 3) || !size || (index & 3) || !data) 700 return -EPERM; 701 702 if ((u32)index + (u32)size > 0xffff) 703 return -EPERM; 704 705 byteen_start = byteen & BYTE_EN_START_MASK; 706 byteen_end = byteen & BYTE_EN_END_MASK; 707 708 byen = byteen_start | (byteen_start << 4); 709 ret = set_registers(tp, index, type | byen, 4, data); 710 if (ret < 0) 711 goto error1; 712 713 index += 4; 714 data += 4; 715 size -= 4; 716 717 if (size) { 718 size -= 4; 719 720 while (size) { 721 if (size > limit) { 722 ret = set_registers(tp, index, 723 type | BYTE_EN_DWORD, 724 limit, data); 725 if (ret < 0) 726 goto error1; 727 728 index += limit; 729 data += limit; 730 size -= limit; 731 } else { 732 ret = set_registers(tp, index, 733 type | BYTE_EN_DWORD, 734 size, data); 735 if (ret < 0) 736 goto error1; 737 738 index += size; 739 data += size; 740 size = 0; 741 break; 742 } 743 } 744 745 byen = byteen_end | (byteen_end >> 4); 746 ret = set_registers(tp, index, type | byen, 4, data); 747 if (ret < 0) 748 goto error1; 749 } 750 751 error1: 752 return ret; 753 } 754 755 static inline 756 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 757 { 758 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 759 } 760 761 static inline 762 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 763 { 764 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 765 } 766 767 static inline 768 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 769 { 770 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); 771 } 772 773 static inline 774 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 775 { 776 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 777 } 778 779 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 780 { 781 __le32 data; 782 783 generic_ocp_read(tp, index, sizeof(data), &data, type); 784 785 return __le32_to_cpu(data); 786 } 787 788 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 789 { 790 __le32 tmp = __cpu_to_le32(data); 791 792 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 793 } 794 795 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 796 { 797 u32 data; 798 __le32 tmp; 799 u8 shift = index & 2; 800 801 index &= ~3; 802 803 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 804 805 data = __le32_to_cpu(tmp); 806 data >>= (shift * 8); 807 data &= 0xffff; 808 809 return (u16)data; 810 } 811 812 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 813 { 814 u32 mask = 0xffff; 815 __le32 tmp; 816 u16 byen = BYTE_EN_WORD; 817 u8 shift = index & 2; 818 819 data &= mask; 820 821 if (index & 2) { 822 byen <<= shift; 823 mask <<= (shift * 8); 824 data <<= (shift * 8); 825 index &= ~3; 826 } 827 828 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 829 830 data |= __le32_to_cpu(tmp) & ~mask; 831 tmp = __cpu_to_le32(data); 832 833 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 834 } 835 836 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 837 { 838 u32 data; 839 __le32 tmp; 840 u8 shift = index & 3; 841 842 index &= ~3; 843 844 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 845 846 data = __le32_to_cpu(tmp); 847 data >>= (shift * 8); 848 data &= 0xff; 849 850 return (u8)data; 851 } 852 853 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 854 { 855 u32 mask = 0xff; 856 __le32 tmp; 857 u16 byen = BYTE_EN_BYTE; 858 u8 shift = index & 3; 859 860 data &= mask; 861 862 if (index & 3) { 863 byen <<= shift; 864 mask <<= (shift * 8); 865 data <<= (shift * 8); 866 index &= ~3; 867 } 868 869 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 870 871 data |= __le32_to_cpu(tmp) & ~mask; 872 tmp = __cpu_to_le32(data); 873 874 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 875 } 876 877 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 878 { 879 u16 ocp_base, ocp_index; 880 881 ocp_base = addr & 0xf000; 882 if (ocp_base != tp->ocp_base) { 883 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 884 tp->ocp_base = ocp_base; 885 } 886 887 ocp_index = (addr & 0x0fff) | 0xb000; 888 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 889 } 890 891 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 892 { 893 u16 ocp_base, ocp_index; 894 895 ocp_base = addr & 0xf000; 896 if (ocp_base != tp->ocp_base) { 897 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 898 tp->ocp_base = ocp_base; 899 } 900 901 ocp_index = (addr & 0x0fff) | 0xb000; 902 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 903 } 904 905 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 906 { 907 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 908 } 909 910 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 911 { 912 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 913 } 914 915 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 916 { 917 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 918 ocp_reg_write(tp, OCP_SRAM_DATA, data); 919 } 920 921 static u16 sram_read(struct r8152 *tp, u16 addr) 922 { 923 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 924 return ocp_reg_read(tp, OCP_SRAM_DATA); 925 } 926 927 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 928 { 929 struct r8152 *tp = netdev_priv(netdev); 930 int ret; 931 932 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 933 return -ENODEV; 934 935 if (phy_id != R8152_PHY_ID) 936 return -EINVAL; 937 938 ret = usb_autopm_get_interface(tp->intf); 939 if (ret < 0) 940 goto out; 941 942 ret = r8152_mdio_read(tp, reg); 943 944 usb_autopm_put_interface(tp->intf); 945 946 out: 947 return ret; 948 } 949 950 static 951 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 952 { 953 struct r8152 *tp = netdev_priv(netdev); 954 955 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 956 return; 957 958 if (phy_id != R8152_PHY_ID) 959 return; 960 961 if (usb_autopm_get_interface(tp->intf) < 0) 962 return; 963 964 r8152_mdio_write(tp, reg, val); 965 966 usb_autopm_put_interface(tp->intf); 967 } 968 969 static 970 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 971 972 static inline void set_ethernet_addr(struct r8152 *tp) 973 { 974 struct net_device *dev = tp->netdev; 975 int ret; 976 u8 node_id[8] = {0}; 977 978 if (tp->version == RTL_VER_01) 979 ret = pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id); 980 else 981 ret = pla_ocp_read(tp, PLA_BACKUP, sizeof(node_id), node_id); 982 983 if (ret < 0) { 984 netif_notice(tp, probe, dev, "inet addr fail\n"); 985 } else { 986 if (tp->version != RTL_VER_01) { 987 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, 988 CRWECR_CONFIG); 989 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 990 sizeof(node_id), node_id); 991 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, 992 CRWECR_NORAML); 993 } 994 995 memcpy(dev->dev_addr, node_id, dev->addr_len); 996 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 997 } 998 } 999 1000 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1001 { 1002 struct r8152 *tp = netdev_priv(netdev); 1003 struct sockaddr *addr = p; 1004 1005 if (!is_valid_ether_addr(addr->sa_data)) 1006 return -EADDRNOTAVAIL; 1007 1008 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1009 1010 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1011 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1012 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1013 1014 return 0; 1015 } 1016 1017 static void read_bulk_callback(struct urb *urb) 1018 { 1019 struct net_device *netdev; 1020 int status = urb->status; 1021 struct rx_agg *agg; 1022 struct r8152 *tp; 1023 int result; 1024 1025 agg = urb->context; 1026 if (!agg) 1027 return; 1028 1029 tp = agg->context; 1030 if (!tp) 1031 return; 1032 1033 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1034 return; 1035 1036 if (!test_bit(WORK_ENABLE, &tp->flags)) 1037 return; 1038 1039 netdev = tp->netdev; 1040 1041 /* When link down, the driver would cancel all bulks. */ 1042 /* This avoid the re-submitting bulk */ 1043 if (!netif_carrier_ok(netdev)) 1044 return; 1045 1046 usb_mark_last_busy(tp->udev); 1047 1048 switch (status) { 1049 case 0: 1050 if (urb->actual_length < ETH_ZLEN) 1051 break; 1052 1053 spin_lock(&tp->rx_lock); 1054 list_add_tail(&agg->list, &tp->rx_done); 1055 spin_unlock(&tp->rx_lock); 1056 tasklet_schedule(&tp->tl); 1057 return; 1058 case -ESHUTDOWN: 1059 set_bit(RTL8152_UNPLUG, &tp->flags); 1060 netif_device_detach(tp->netdev); 1061 return; 1062 case -ENOENT: 1063 return; /* the urb is in unlink state */ 1064 case -ETIME: 1065 if (net_ratelimit()) 1066 netdev_warn(netdev, "maybe reset is needed?\n"); 1067 break; 1068 default: 1069 if (net_ratelimit()) 1070 netdev_warn(netdev, "Rx status %d\n", status); 1071 break; 1072 } 1073 1074 result = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1075 if (result == -ENODEV) { 1076 netif_device_detach(tp->netdev); 1077 } else if (result) { 1078 spin_lock(&tp->rx_lock); 1079 list_add_tail(&agg->list, &tp->rx_done); 1080 spin_unlock(&tp->rx_lock); 1081 tasklet_schedule(&tp->tl); 1082 } 1083 } 1084 1085 static void write_bulk_callback(struct urb *urb) 1086 { 1087 struct net_device_stats *stats; 1088 struct net_device *netdev; 1089 struct tx_agg *agg; 1090 struct r8152 *tp; 1091 int status = urb->status; 1092 1093 agg = urb->context; 1094 if (!agg) 1095 return; 1096 1097 tp = agg->context; 1098 if (!tp) 1099 return; 1100 1101 netdev = tp->netdev; 1102 stats = &netdev->stats; 1103 if (status) { 1104 if (net_ratelimit()) 1105 netdev_warn(netdev, "Tx status %d\n", status); 1106 stats->tx_errors += agg->skb_num; 1107 } else { 1108 stats->tx_packets += agg->skb_num; 1109 stats->tx_bytes += agg->skb_len; 1110 } 1111 1112 spin_lock(&tp->tx_lock); 1113 list_add_tail(&agg->list, &tp->tx_free); 1114 spin_unlock(&tp->tx_lock); 1115 1116 usb_autopm_put_interface_async(tp->intf); 1117 1118 if (!netif_carrier_ok(netdev)) 1119 return; 1120 1121 if (!test_bit(WORK_ENABLE, &tp->flags)) 1122 return; 1123 1124 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1125 return; 1126 1127 if (!skb_queue_empty(&tp->tx_queue)) 1128 tasklet_schedule(&tp->tl); 1129 } 1130 1131 static void intr_callback(struct urb *urb) 1132 { 1133 struct r8152 *tp; 1134 __le16 *d; 1135 int status = urb->status; 1136 int res; 1137 1138 tp = urb->context; 1139 if (!tp) 1140 return; 1141 1142 if (!test_bit(WORK_ENABLE, &tp->flags)) 1143 return; 1144 1145 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1146 return; 1147 1148 switch (status) { 1149 case 0: /* success */ 1150 break; 1151 case -ECONNRESET: /* unlink */ 1152 case -ESHUTDOWN: 1153 netif_device_detach(tp->netdev); 1154 case -ENOENT: 1155 return; 1156 case -EOVERFLOW: 1157 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1158 goto resubmit; 1159 /* -EPIPE: should clear the halt */ 1160 default: 1161 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1162 goto resubmit; 1163 } 1164 1165 d = urb->transfer_buffer; 1166 if (INTR_LINK & __le16_to_cpu(d[0])) { 1167 if (!(tp->speed & LINK_STATUS)) { 1168 set_bit(RTL8152_LINK_CHG, &tp->flags); 1169 schedule_delayed_work(&tp->schedule, 0); 1170 } 1171 } else { 1172 if (tp->speed & LINK_STATUS) { 1173 set_bit(RTL8152_LINK_CHG, &tp->flags); 1174 schedule_delayed_work(&tp->schedule, 0); 1175 } 1176 } 1177 1178 resubmit: 1179 res = usb_submit_urb(urb, GFP_ATOMIC); 1180 if (res == -ENODEV) 1181 netif_device_detach(tp->netdev); 1182 else if (res) 1183 netif_err(tp, intr, tp->netdev, 1184 "can't resubmit intr, status %d\n", res); 1185 } 1186 1187 static inline void *rx_agg_align(void *data) 1188 { 1189 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1190 } 1191 1192 static inline void *tx_agg_align(void *data) 1193 { 1194 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1195 } 1196 1197 static void free_all_mem(struct r8152 *tp) 1198 { 1199 int i; 1200 1201 for (i = 0; i < RTL8152_MAX_RX; i++) { 1202 usb_free_urb(tp->rx_info[i].urb); 1203 tp->rx_info[i].urb = NULL; 1204 1205 kfree(tp->rx_info[i].buffer); 1206 tp->rx_info[i].buffer = NULL; 1207 tp->rx_info[i].head = NULL; 1208 } 1209 1210 for (i = 0; i < RTL8152_MAX_TX; i++) { 1211 usb_free_urb(tp->tx_info[i].urb); 1212 tp->tx_info[i].urb = NULL; 1213 1214 kfree(tp->tx_info[i].buffer); 1215 tp->tx_info[i].buffer = NULL; 1216 tp->tx_info[i].head = NULL; 1217 } 1218 1219 usb_free_urb(tp->intr_urb); 1220 tp->intr_urb = NULL; 1221 1222 kfree(tp->intr_buff); 1223 tp->intr_buff = NULL; 1224 } 1225 1226 static int alloc_all_mem(struct r8152 *tp) 1227 { 1228 struct net_device *netdev = tp->netdev; 1229 struct usb_interface *intf = tp->intf; 1230 struct usb_host_interface *alt = intf->cur_altsetting; 1231 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1232 struct urb *urb; 1233 int node, i; 1234 u8 *buf; 1235 1236 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1237 1238 spin_lock_init(&tp->rx_lock); 1239 spin_lock_init(&tp->tx_lock); 1240 INIT_LIST_HEAD(&tp->rx_done); 1241 INIT_LIST_HEAD(&tp->tx_free); 1242 skb_queue_head_init(&tp->tx_queue); 1243 1244 for (i = 0; i < RTL8152_MAX_RX; i++) { 1245 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); 1246 if (!buf) 1247 goto err1; 1248 1249 if (buf != rx_agg_align(buf)) { 1250 kfree(buf); 1251 buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL, 1252 node); 1253 if (!buf) 1254 goto err1; 1255 } 1256 1257 urb = usb_alloc_urb(0, GFP_KERNEL); 1258 if (!urb) { 1259 kfree(buf); 1260 goto err1; 1261 } 1262 1263 INIT_LIST_HEAD(&tp->rx_info[i].list); 1264 tp->rx_info[i].context = tp; 1265 tp->rx_info[i].urb = urb; 1266 tp->rx_info[i].buffer = buf; 1267 tp->rx_info[i].head = rx_agg_align(buf); 1268 } 1269 1270 for (i = 0; i < RTL8152_MAX_TX; i++) { 1271 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); 1272 if (!buf) 1273 goto err1; 1274 1275 if (buf != tx_agg_align(buf)) { 1276 kfree(buf); 1277 buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL, 1278 node); 1279 if (!buf) 1280 goto err1; 1281 } 1282 1283 urb = usb_alloc_urb(0, GFP_KERNEL); 1284 if (!urb) { 1285 kfree(buf); 1286 goto err1; 1287 } 1288 1289 INIT_LIST_HEAD(&tp->tx_info[i].list); 1290 tp->tx_info[i].context = tp; 1291 tp->tx_info[i].urb = urb; 1292 tp->tx_info[i].buffer = buf; 1293 tp->tx_info[i].head = tx_agg_align(buf); 1294 1295 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1296 } 1297 1298 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1299 if (!tp->intr_urb) 1300 goto err1; 1301 1302 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1303 if (!tp->intr_buff) 1304 goto err1; 1305 1306 tp->intr_interval = (int)ep_intr->desc.bInterval; 1307 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1308 tp->intr_buff, INTBUFSIZE, intr_callback, 1309 tp, tp->intr_interval); 1310 1311 return 0; 1312 1313 err1: 1314 free_all_mem(tp); 1315 return -ENOMEM; 1316 } 1317 1318 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1319 { 1320 struct tx_agg *agg = NULL; 1321 unsigned long flags; 1322 1323 if (list_empty(&tp->tx_free)) 1324 return NULL; 1325 1326 spin_lock_irqsave(&tp->tx_lock, flags); 1327 if (!list_empty(&tp->tx_free)) { 1328 struct list_head *cursor; 1329 1330 cursor = tp->tx_free.next; 1331 list_del_init(cursor); 1332 agg = list_entry(cursor, struct tx_agg, list); 1333 } 1334 spin_unlock_irqrestore(&tp->tx_lock, flags); 1335 1336 return agg; 1337 } 1338 1339 static inline __be16 get_protocol(struct sk_buff *skb) 1340 { 1341 __be16 protocol; 1342 1343 if (skb->protocol == htons(ETH_P_8021Q)) 1344 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; 1345 else 1346 protocol = skb->protocol; 1347 1348 return protocol; 1349 } 1350 1351 /* 1352 * r8152_csum_workaround() 1353 * The hw limites the value the transport offset. When the offset is out of the 1354 * range, calculate the checksum by sw. 1355 */ 1356 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1357 struct sk_buff_head *list) 1358 { 1359 if (skb_shinfo(skb)->gso_size) { 1360 netdev_features_t features = tp->netdev->features; 1361 struct sk_buff_head seg_list; 1362 struct sk_buff *segs, *nskb; 1363 1364 features &= ~(NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO); 1365 segs = skb_gso_segment(skb, features); 1366 if (IS_ERR(segs) || !segs) 1367 goto drop; 1368 1369 __skb_queue_head_init(&seg_list); 1370 1371 do { 1372 nskb = segs; 1373 segs = segs->next; 1374 nskb->next = NULL; 1375 __skb_queue_tail(&seg_list, nskb); 1376 } while (segs); 1377 1378 skb_queue_splice(&seg_list, list); 1379 dev_kfree_skb(skb); 1380 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1381 if (skb_checksum_help(skb) < 0) 1382 goto drop; 1383 1384 __skb_queue_head(list, skb); 1385 } else { 1386 struct net_device_stats *stats; 1387 1388 drop: 1389 stats = &tp->netdev->stats; 1390 stats->tx_dropped++; 1391 dev_kfree_skb(skb); 1392 } 1393 } 1394 1395 /* 1396 * msdn_giant_send_check() 1397 * According to the document of microsoft, the TCP Pseudo Header excludes the 1398 * packet length for IPv6 TCP large packets. 1399 */ 1400 static int msdn_giant_send_check(struct sk_buff *skb) 1401 { 1402 const struct ipv6hdr *ipv6h; 1403 struct tcphdr *th; 1404 int ret; 1405 1406 ret = skb_cow_head(skb, 0); 1407 if (ret) 1408 return ret; 1409 1410 ipv6h = ipv6_hdr(skb); 1411 th = tcp_hdr(skb); 1412 1413 th->check = 0; 1414 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1415 1416 return ret; 1417 } 1418 1419 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1420 struct sk_buff *skb, u32 len, u32 transport_offset) 1421 { 1422 u32 mss = skb_shinfo(skb)->gso_size; 1423 u32 opts1, opts2 = 0; 1424 int ret = TX_CSUM_SUCCESS; 1425 1426 WARN_ON_ONCE(len > TX_LEN_MAX); 1427 1428 opts1 = len | TX_FS | TX_LS; 1429 1430 if (mss) { 1431 if (transport_offset > GTTCPHO_MAX) { 1432 netif_warn(tp, tx_err, tp->netdev, 1433 "Invalid transport offset 0x%x for TSO\n", 1434 transport_offset); 1435 ret = TX_CSUM_TSO; 1436 goto unavailable; 1437 } 1438 1439 switch (get_protocol(skb)) { 1440 case htons(ETH_P_IP): 1441 opts1 |= GTSENDV4; 1442 break; 1443 1444 case htons(ETH_P_IPV6): 1445 if (msdn_giant_send_check(skb)) { 1446 ret = TX_CSUM_TSO; 1447 goto unavailable; 1448 } 1449 opts1 |= GTSENDV6; 1450 break; 1451 1452 default: 1453 WARN_ON_ONCE(1); 1454 break; 1455 } 1456 1457 opts1 |= transport_offset << GTTCPHO_SHIFT; 1458 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1459 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1460 u8 ip_protocol; 1461 1462 if (transport_offset > TCPHO_MAX) { 1463 netif_warn(tp, tx_err, tp->netdev, 1464 "Invalid transport offset 0x%x\n", 1465 transport_offset); 1466 ret = TX_CSUM_NONE; 1467 goto unavailable; 1468 } 1469 1470 switch (get_protocol(skb)) { 1471 case htons(ETH_P_IP): 1472 opts2 |= IPV4_CS; 1473 ip_protocol = ip_hdr(skb)->protocol; 1474 break; 1475 1476 case htons(ETH_P_IPV6): 1477 opts2 |= IPV6_CS; 1478 ip_protocol = ipv6_hdr(skb)->nexthdr; 1479 break; 1480 1481 default: 1482 ip_protocol = IPPROTO_RAW; 1483 break; 1484 } 1485 1486 if (ip_protocol == IPPROTO_TCP) 1487 opts2 |= TCP_CS; 1488 else if (ip_protocol == IPPROTO_UDP) 1489 opts2 |= UDP_CS; 1490 else 1491 WARN_ON_ONCE(1); 1492 1493 opts2 |= transport_offset << TCPHO_SHIFT; 1494 } 1495 1496 desc->opts2 = cpu_to_le32(opts2); 1497 desc->opts1 = cpu_to_le32(opts1); 1498 1499 unavailable: 1500 return ret; 1501 } 1502 1503 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1504 { 1505 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1506 int remain, ret; 1507 u8 *tx_data; 1508 1509 __skb_queue_head_init(&skb_head); 1510 spin_lock(&tx_queue->lock); 1511 skb_queue_splice_init(tx_queue, &skb_head); 1512 spin_unlock(&tx_queue->lock); 1513 1514 tx_data = agg->head; 1515 agg->skb_num = agg->skb_len = 0; 1516 remain = rx_buf_sz; 1517 1518 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1519 struct tx_desc *tx_desc; 1520 struct sk_buff *skb; 1521 unsigned int len; 1522 u32 offset; 1523 1524 skb = __skb_dequeue(&skb_head); 1525 if (!skb) 1526 break; 1527 1528 len = skb->len + sizeof(*tx_desc); 1529 1530 if (len > remain) { 1531 __skb_queue_head(&skb_head, skb); 1532 break; 1533 } 1534 1535 tx_data = tx_agg_align(tx_data); 1536 tx_desc = (struct tx_desc *)tx_data; 1537 1538 offset = (u32)skb_transport_offset(skb); 1539 1540 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1541 r8152_csum_workaround(tp, skb, &skb_head); 1542 continue; 1543 } 1544 1545 tx_data += sizeof(*tx_desc); 1546 1547 len = skb->len; 1548 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1549 struct net_device_stats *stats = &tp->netdev->stats; 1550 1551 stats->tx_dropped++; 1552 dev_kfree_skb_any(skb); 1553 tx_data -= sizeof(*tx_desc); 1554 continue; 1555 } 1556 1557 tx_data += len; 1558 agg->skb_len += len; 1559 agg->skb_num++; 1560 1561 dev_kfree_skb_any(skb); 1562 1563 remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1564 } 1565 1566 if (!skb_queue_empty(&skb_head)) { 1567 spin_lock(&tx_queue->lock); 1568 skb_queue_splice(&skb_head, tx_queue); 1569 spin_unlock(&tx_queue->lock); 1570 } 1571 1572 netif_tx_lock(tp->netdev); 1573 1574 if (netif_queue_stopped(tp->netdev) && 1575 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1576 netif_wake_queue(tp->netdev); 1577 1578 netif_tx_unlock(tp->netdev); 1579 1580 ret = usb_autopm_get_interface_async(tp->intf); 1581 if (ret < 0) 1582 goto out_tx_fill; 1583 1584 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1585 agg->head, (int)(tx_data - (u8 *)agg->head), 1586 (usb_complete_t)write_bulk_callback, agg); 1587 1588 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1589 if (ret < 0) 1590 usb_autopm_put_interface_async(tp->intf); 1591 1592 out_tx_fill: 1593 return ret; 1594 } 1595 1596 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1597 { 1598 u8 checksum = CHECKSUM_NONE; 1599 u32 opts2, opts3; 1600 1601 if (tp->version == RTL_VER_01) 1602 goto return_result; 1603 1604 opts2 = le32_to_cpu(rx_desc->opts2); 1605 opts3 = le32_to_cpu(rx_desc->opts3); 1606 1607 if (opts2 & RD_IPV4_CS) { 1608 if (opts3 & IPF) 1609 checksum = CHECKSUM_NONE; 1610 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) 1611 checksum = CHECKSUM_NONE; 1612 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) 1613 checksum = CHECKSUM_NONE; 1614 else 1615 checksum = CHECKSUM_UNNECESSARY; 1616 } else if (RD_IPV6_CS) { 1617 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1618 checksum = CHECKSUM_UNNECESSARY; 1619 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1620 checksum = CHECKSUM_UNNECESSARY; 1621 } 1622 1623 return_result: 1624 return checksum; 1625 } 1626 1627 static void rx_bottom(struct r8152 *tp) 1628 { 1629 unsigned long flags; 1630 struct list_head *cursor, *next, rx_queue; 1631 1632 if (list_empty(&tp->rx_done)) 1633 return; 1634 1635 INIT_LIST_HEAD(&rx_queue); 1636 spin_lock_irqsave(&tp->rx_lock, flags); 1637 list_splice_init(&tp->rx_done, &rx_queue); 1638 spin_unlock_irqrestore(&tp->rx_lock, flags); 1639 1640 list_for_each_safe(cursor, next, &rx_queue) { 1641 struct rx_desc *rx_desc; 1642 struct rx_agg *agg; 1643 int len_used = 0; 1644 struct urb *urb; 1645 u8 *rx_data; 1646 int ret; 1647 1648 list_del_init(cursor); 1649 1650 agg = list_entry(cursor, struct rx_agg, list); 1651 urb = agg->urb; 1652 if (urb->actual_length < ETH_ZLEN) 1653 goto submit; 1654 1655 rx_desc = agg->head; 1656 rx_data = agg->head; 1657 len_used += sizeof(struct rx_desc); 1658 1659 while (urb->actual_length > len_used) { 1660 struct net_device *netdev = tp->netdev; 1661 struct net_device_stats *stats = &netdev->stats; 1662 unsigned int pkt_len; 1663 struct sk_buff *skb; 1664 1665 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1666 if (pkt_len < ETH_ZLEN) 1667 break; 1668 1669 len_used += pkt_len; 1670 if (urb->actual_length < len_used) 1671 break; 1672 1673 pkt_len -= CRC_SIZE; 1674 rx_data += sizeof(struct rx_desc); 1675 1676 skb = netdev_alloc_skb_ip_align(netdev, pkt_len); 1677 if (!skb) { 1678 stats->rx_dropped++; 1679 goto find_next_rx; 1680 } 1681 1682 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 1683 memcpy(skb->data, rx_data, pkt_len); 1684 skb_put(skb, pkt_len); 1685 skb->protocol = eth_type_trans(skb, netdev); 1686 netif_receive_skb(skb); 1687 stats->rx_packets++; 1688 stats->rx_bytes += pkt_len; 1689 1690 find_next_rx: 1691 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); 1692 rx_desc = (struct rx_desc *)rx_data; 1693 len_used = (int)(rx_data - (u8 *)agg->head); 1694 len_used += sizeof(struct rx_desc); 1695 } 1696 1697 submit: 1698 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1699 if (ret && ret != -ENODEV) { 1700 spin_lock_irqsave(&tp->rx_lock, flags); 1701 list_add_tail(&agg->list, &tp->rx_done); 1702 spin_unlock_irqrestore(&tp->rx_lock, flags); 1703 tasklet_schedule(&tp->tl); 1704 } 1705 } 1706 } 1707 1708 static void tx_bottom(struct r8152 *tp) 1709 { 1710 int res; 1711 1712 do { 1713 struct tx_agg *agg; 1714 1715 if (skb_queue_empty(&tp->tx_queue)) 1716 break; 1717 1718 agg = r8152_get_tx_agg(tp); 1719 if (!agg) 1720 break; 1721 1722 res = r8152_tx_agg_fill(tp, agg); 1723 if (res) { 1724 struct net_device *netdev = tp->netdev; 1725 1726 if (res == -ENODEV) { 1727 netif_device_detach(netdev); 1728 } else { 1729 struct net_device_stats *stats = &netdev->stats; 1730 unsigned long flags; 1731 1732 netif_warn(tp, tx_err, netdev, 1733 "failed tx_urb %d\n", res); 1734 stats->tx_dropped += agg->skb_num; 1735 1736 spin_lock_irqsave(&tp->tx_lock, flags); 1737 list_add_tail(&agg->list, &tp->tx_free); 1738 spin_unlock_irqrestore(&tp->tx_lock, flags); 1739 } 1740 } 1741 } while (res == 0); 1742 } 1743 1744 static void bottom_half(unsigned long data) 1745 { 1746 struct r8152 *tp; 1747 1748 tp = (struct r8152 *)data; 1749 1750 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1751 return; 1752 1753 if (!test_bit(WORK_ENABLE, &tp->flags)) 1754 return; 1755 1756 /* When link down, the driver would cancel all bulks. */ 1757 /* This avoid the re-submitting bulk */ 1758 if (!netif_carrier_ok(tp->netdev)) 1759 return; 1760 1761 rx_bottom(tp); 1762 tx_bottom(tp); 1763 } 1764 1765 static 1766 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 1767 { 1768 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 1769 agg->head, rx_buf_sz, 1770 (usb_complete_t)read_bulk_callback, agg); 1771 1772 return usb_submit_urb(agg->urb, mem_flags); 1773 } 1774 1775 static void rtl_drop_queued_tx(struct r8152 *tp) 1776 { 1777 struct net_device_stats *stats = &tp->netdev->stats; 1778 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1779 struct sk_buff *skb; 1780 1781 if (skb_queue_empty(tx_queue)) 1782 return; 1783 1784 __skb_queue_head_init(&skb_head); 1785 spin_lock_bh(&tx_queue->lock); 1786 skb_queue_splice_init(tx_queue, &skb_head); 1787 spin_unlock_bh(&tx_queue->lock); 1788 1789 while ((skb = __skb_dequeue(&skb_head))) { 1790 dev_kfree_skb(skb); 1791 stats->tx_dropped++; 1792 } 1793 } 1794 1795 static void rtl8152_tx_timeout(struct net_device *netdev) 1796 { 1797 struct r8152 *tp = netdev_priv(netdev); 1798 int i; 1799 1800 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 1801 for (i = 0; i < RTL8152_MAX_TX; i++) 1802 usb_unlink_urb(tp->tx_info[i].urb); 1803 } 1804 1805 static void rtl8152_set_rx_mode(struct net_device *netdev) 1806 { 1807 struct r8152 *tp = netdev_priv(netdev); 1808 1809 if (tp->speed & LINK_STATUS) { 1810 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 1811 schedule_delayed_work(&tp->schedule, 0); 1812 } 1813 } 1814 1815 static void _rtl8152_set_rx_mode(struct net_device *netdev) 1816 { 1817 struct r8152 *tp = netdev_priv(netdev); 1818 u32 mc_filter[2]; /* Multicast hash filter */ 1819 __le32 tmp[2]; 1820 u32 ocp_data; 1821 1822 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 1823 netif_stop_queue(netdev); 1824 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 1825 ocp_data &= ~RCR_ACPT_ALL; 1826 ocp_data |= RCR_AB | RCR_APM; 1827 1828 if (netdev->flags & IFF_PROMISC) { 1829 /* Unconditionally log net taps. */ 1830 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 1831 ocp_data |= RCR_AM | RCR_AAP; 1832 mc_filter[1] = mc_filter[0] = 0xffffffff; 1833 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 1834 (netdev->flags & IFF_ALLMULTI)) { 1835 /* Too many to filter perfectly -- accept all multicasts. */ 1836 ocp_data |= RCR_AM; 1837 mc_filter[1] = mc_filter[0] = 0xffffffff; 1838 } else { 1839 struct netdev_hw_addr *ha; 1840 1841 mc_filter[1] = mc_filter[0] = 0; 1842 netdev_for_each_mc_addr(ha, netdev) { 1843 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 1844 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 1845 ocp_data |= RCR_AM; 1846 } 1847 } 1848 1849 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 1850 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 1851 1852 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 1853 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 1854 netif_wake_queue(netdev); 1855 } 1856 1857 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 1858 struct net_device *netdev) 1859 { 1860 struct r8152 *tp = netdev_priv(netdev); 1861 1862 skb_tx_timestamp(skb); 1863 1864 skb_queue_tail(&tp->tx_queue, skb); 1865 1866 if (!list_empty(&tp->tx_free)) { 1867 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 1868 set_bit(SCHEDULE_TASKLET, &tp->flags); 1869 schedule_delayed_work(&tp->schedule, 0); 1870 } else { 1871 usb_mark_last_busy(tp->udev); 1872 tasklet_schedule(&tp->tl); 1873 } 1874 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) 1875 netif_stop_queue(netdev); 1876 1877 return NETDEV_TX_OK; 1878 } 1879 1880 static void r8152b_reset_packet_filter(struct r8152 *tp) 1881 { 1882 u32 ocp_data; 1883 1884 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 1885 ocp_data &= ~FMC_FCR_MCU_EN; 1886 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 1887 ocp_data |= FMC_FCR_MCU_EN; 1888 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 1889 } 1890 1891 static void rtl8152_nic_reset(struct r8152 *tp) 1892 { 1893 int i; 1894 1895 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 1896 1897 for (i = 0; i < 1000; i++) { 1898 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 1899 break; 1900 udelay(100); 1901 } 1902 } 1903 1904 static void set_tx_qlen(struct r8152 *tp) 1905 { 1906 struct net_device *netdev = tp->netdev; 1907 1908 tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + 1909 sizeof(struct tx_desc)); 1910 } 1911 1912 static inline u8 rtl8152_get_speed(struct r8152 *tp) 1913 { 1914 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 1915 } 1916 1917 static void rtl_set_eee_plus(struct r8152 *tp) 1918 { 1919 u32 ocp_data; 1920 u8 speed; 1921 1922 speed = rtl8152_get_speed(tp); 1923 if (speed & _10bps) { 1924 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 1925 ocp_data |= EEEP_CR_EEEP_TX; 1926 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 1927 } else { 1928 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 1929 ocp_data &= ~EEEP_CR_EEEP_TX; 1930 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 1931 } 1932 } 1933 1934 static void rxdy_gated_en(struct r8152 *tp, bool enable) 1935 { 1936 u32 ocp_data; 1937 1938 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 1939 if (enable) 1940 ocp_data |= RXDY_GATED_EN; 1941 else 1942 ocp_data &= ~RXDY_GATED_EN; 1943 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 1944 } 1945 1946 static int rtl_enable(struct r8152 *tp) 1947 { 1948 u32 ocp_data; 1949 int i, ret; 1950 1951 r8152b_reset_packet_filter(tp); 1952 1953 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 1954 ocp_data |= CR_RE | CR_TE; 1955 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 1956 1957 rxdy_gated_en(tp, false); 1958 1959 INIT_LIST_HEAD(&tp->rx_done); 1960 ret = 0; 1961 for (i = 0; i < RTL8152_MAX_RX; i++) { 1962 INIT_LIST_HEAD(&tp->rx_info[i].list); 1963 ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 1964 } 1965 1966 return ret; 1967 } 1968 1969 static int rtl8152_enable(struct r8152 *tp) 1970 { 1971 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1972 return -ENODEV; 1973 1974 set_tx_qlen(tp); 1975 rtl_set_eee_plus(tp); 1976 1977 return rtl_enable(tp); 1978 } 1979 1980 static void r8153_set_rx_agg(struct r8152 *tp) 1981 { 1982 u8 speed; 1983 1984 speed = rtl8152_get_speed(tp); 1985 if (speed & _1000bps) { 1986 if (tp->udev->speed == USB_SPEED_SUPER) { 1987 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 1988 RX_THR_SUPPER); 1989 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, 1990 EARLY_AGG_SUPPER); 1991 } else { 1992 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 1993 RX_THR_HIGH); 1994 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, 1995 EARLY_AGG_HIGH); 1996 } 1997 } else { 1998 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW); 1999 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, 2000 EARLY_AGG_SLOW); 2001 } 2002 } 2003 2004 static int rtl8153_enable(struct r8152 *tp) 2005 { 2006 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2007 return -ENODEV; 2008 2009 set_tx_qlen(tp); 2010 rtl_set_eee_plus(tp); 2011 r8153_set_rx_agg(tp); 2012 2013 return rtl_enable(tp); 2014 } 2015 2016 static void rtl8152_disable(struct r8152 *tp) 2017 { 2018 u32 ocp_data; 2019 int i; 2020 2021 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2022 rtl_drop_queued_tx(tp); 2023 return; 2024 } 2025 2026 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2027 ocp_data &= ~RCR_ACPT_ALL; 2028 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2029 2030 rtl_drop_queued_tx(tp); 2031 2032 for (i = 0; i < RTL8152_MAX_TX; i++) 2033 usb_kill_urb(tp->tx_info[i].urb); 2034 2035 rxdy_gated_en(tp, true); 2036 2037 for (i = 0; i < 1000; i++) { 2038 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2039 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2040 break; 2041 mdelay(1); 2042 } 2043 2044 for (i = 0; i < 1000; i++) { 2045 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2046 break; 2047 mdelay(1); 2048 } 2049 2050 for (i = 0; i < RTL8152_MAX_RX; i++) 2051 usb_kill_urb(tp->rx_info[i].urb); 2052 2053 rtl8152_nic_reset(tp); 2054 } 2055 2056 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2057 { 2058 u32 ocp_data; 2059 2060 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2061 if (enable) 2062 ocp_data |= POWER_CUT; 2063 else 2064 ocp_data &= ~POWER_CUT; 2065 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2066 2067 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2068 ocp_data &= ~RESUME_INDICATE; 2069 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2070 } 2071 2072 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2073 2074 static u32 __rtl_get_wol(struct r8152 *tp) 2075 { 2076 u32 ocp_data; 2077 u32 wolopts = 0; 2078 2079 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2080 if (!(ocp_data & LAN_WAKE_EN)) 2081 return 0; 2082 2083 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2084 if (ocp_data & LINK_ON_WAKE_EN) 2085 wolopts |= WAKE_PHY; 2086 2087 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2088 if (ocp_data & UWF_EN) 2089 wolopts |= WAKE_UCAST; 2090 if (ocp_data & BWF_EN) 2091 wolopts |= WAKE_BCAST; 2092 if (ocp_data & MWF_EN) 2093 wolopts |= WAKE_MCAST; 2094 2095 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2096 if (ocp_data & MAGIC_EN) 2097 wolopts |= WAKE_MAGIC; 2098 2099 return wolopts; 2100 } 2101 2102 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2103 { 2104 u32 ocp_data; 2105 2106 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2107 2108 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2109 ocp_data &= ~LINK_ON_WAKE_EN; 2110 if (wolopts & WAKE_PHY) 2111 ocp_data |= LINK_ON_WAKE_EN; 2112 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2113 2114 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2115 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN); 2116 if (wolopts & WAKE_UCAST) 2117 ocp_data |= UWF_EN; 2118 if (wolopts & WAKE_BCAST) 2119 ocp_data |= BWF_EN; 2120 if (wolopts & WAKE_MCAST) 2121 ocp_data |= MWF_EN; 2122 if (wolopts & WAKE_ANY) 2123 ocp_data |= LAN_WAKE_EN; 2124 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2125 2126 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2127 2128 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2129 ocp_data &= ~MAGIC_EN; 2130 if (wolopts & WAKE_MAGIC) 2131 ocp_data |= MAGIC_EN; 2132 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2133 2134 if (wolopts & WAKE_ANY) 2135 device_set_wakeup_enable(&tp->udev->dev, true); 2136 else 2137 device_set_wakeup_enable(&tp->udev->dev, false); 2138 } 2139 2140 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 2141 { 2142 if (enable) { 2143 u32 ocp_data; 2144 2145 __rtl_set_wol(tp, WAKE_ANY); 2146 2147 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2148 2149 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2150 ocp_data |= LINK_OFF_WAKE_EN; 2151 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2152 2153 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2154 } else { 2155 __rtl_set_wol(tp, tp->saved_wolopts); 2156 } 2157 } 2158 2159 static void rtl_phy_reset(struct r8152 *tp) 2160 { 2161 u16 data; 2162 int i; 2163 2164 clear_bit(PHY_RESET, &tp->flags); 2165 2166 data = r8152_mdio_read(tp, MII_BMCR); 2167 2168 /* don't reset again before the previous one complete */ 2169 if (data & BMCR_RESET) 2170 return; 2171 2172 data |= BMCR_RESET; 2173 r8152_mdio_write(tp, MII_BMCR, data); 2174 2175 for (i = 0; i < 50; i++) { 2176 msleep(20); 2177 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 2178 break; 2179 } 2180 } 2181 2182 static void rtl_clear_bp(struct r8152 *tp) 2183 { 2184 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0); 2185 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0); 2186 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0); 2187 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0); 2188 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0); 2189 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0); 2190 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0); 2191 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0); 2192 mdelay(3); 2193 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0); 2194 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0); 2195 } 2196 2197 static void r8153_clear_bp(struct r8152 *tp) 2198 { 2199 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0); 2200 ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0); 2201 rtl_clear_bp(tp); 2202 } 2203 2204 static void r8153_teredo_off(struct r8152 *tp) 2205 { 2206 u32 ocp_data; 2207 2208 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2209 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); 2210 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2211 2212 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 2213 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 2214 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 2215 } 2216 2217 static void r8152b_disable_aldps(struct r8152 *tp) 2218 { 2219 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); 2220 msleep(20); 2221 } 2222 2223 static inline void r8152b_enable_aldps(struct r8152 *tp) 2224 { 2225 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 2226 LINKENA | DIS_SDSAVE); 2227 } 2228 2229 static void r8152b_hw_phy_cfg(struct r8152 *tp) 2230 { 2231 u16 data; 2232 2233 data = r8152_mdio_read(tp, MII_BMCR); 2234 if (data & BMCR_PDOWN) { 2235 data &= ~BMCR_PDOWN; 2236 r8152_mdio_write(tp, MII_BMCR, data); 2237 } 2238 2239 r8152b_disable_aldps(tp); 2240 2241 rtl_clear_bp(tp); 2242 2243 r8152b_enable_aldps(tp); 2244 set_bit(PHY_RESET, &tp->flags); 2245 } 2246 2247 static void r8152b_exit_oob(struct r8152 *tp) 2248 { 2249 u32 ocp_data; 2250 int i; 2251 2252 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2253 return; 2254 2255 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2256 ocp_data &= ~RCR_ACPT_ALL; 2257 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2258 2259 rxdy_gated_en(tp, true); 2260 r8153_teredo_off(tp); 2261 r8152b_hw_phy_cfg(tp); 2262 2263 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2264 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 2265 2266 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2267 ocp_data &= ~NOW_IS_OOB; 2268 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2269 2270 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2271 ocp_data &= ~MCU_BORW_EN; 2272 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2273 2274 for (i = 0; i < 1000; i++) { 2275 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2276 if (ocp_data & LINK_LIST_READY) 2277 break; 2278 mdelay(1); 2279 } 2280 2281 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2282 ocp_data |= RE_INIT_LL; 2283 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2284 2285 for (i = 0; i < 1000; i++) { 2286 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2287 if (ocp_data & LINK_LIST_READY) 2288 break; 2289 mdelay(1); 2290 } 2291 2292 rtl8152_nic_reset(tp); 2293 2294 /* rx share fifo credit full threshold */ 2295 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2296 2297 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT); 2298 ocp_data &= STAT_SPEED_MASK; 2299 if (ocp_data == STAT_SPEED_FULL) { 2300 /* rx share fifo credit near full threshold */ 2301 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2302 RXFIFO_THR2_FULL); 2303 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2304 RXFIFO_THR3_FULL); 2305 } else { 2306 /* rx share fifo credit near full threshold */ 2307 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2308 RXFIFO_THR2_HIGH); 2309 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2310 RXFIFO_THR3_HIGH); 2311 } 2312 2313 /* TX share fifo free credit full threshold */ 2314 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 2315 2316 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 2317 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 2318 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 2319 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 2320 2321 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2322 ocp_data &= ~CPCR_RX_VLAN; 2323 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2324 2325 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2326 2327 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2328 ocp_data |= TCR0_AUTO_FIFO; 2329 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2330 } 2331 2332 static void r8152b_enter_oob(struct r8152 *tp) 2333 { 2334 u32 ocp_data; 2335 int i; 2336 2337 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2338 ocp_data &= ~NOW_IS_OOB; 2339 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2340 2341 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 2342 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 2343 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 2344 2345 rtl8152_disable(tp); 2346 2347 for (i = 0; i < 1000; i++) { 2348 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2349 if (ocp_data & LINK_LIST_READY) 2350 break; 2351 mdelay(1); 2352 } 2353 2354 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2355 ocp_data |= RE_INIT_LL; 2356 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2357 2358 for (i = 0; i < 1000; i++) { 2359 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2360 if (ocp_data & LINK_LIST_READY) 2361 break; 2362 mdelay(1); 2363 } 2364 2365 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2366 2367 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2368 ocp_data |= CPCR_RX_VLAN; 2369 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2370 2371 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2372 ocp_data |= ALDPS_PROXY_MODE; 2373 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2374 2375 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2376 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2377 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2378 2379 rxdy_gated_en(tp, false); 2380 2381 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2382 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2383 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2384 } 2385 2386 static void r8153_hw_phy_cfg(struct r8152 *tp) 2387 { 2388 u32 ocp_data; 2389 u16 data; 2390 2391 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 2392 data = r8152_mdio_read(tp, MII_BMCR); 2393 if (data & BMCR_PDOWN) { 2394 data &= ~BMCR_PDOWN; 2395 r8152_mdio_write(tp, MII_BMCR, data); 2396 } 2397 2398 r8153_clear_bp(tp); 2399 2400 if (tp->version == RTL_VER_03) { 2401 data = ocp_reg_read(tp, OCP_EEE_CFG); 2402 data &= ~CTAP_SHORT_EN; 2403 ocp_reg_write(tp, OCP_EEE_CFG, data); 2404 } 2405 2406 data = ocp_reg_read(tp, OCP_POWER_CFG); 2407 data |= EEE_CLKDIV_EN; 2408 ocp_reg_write(tp, OCP_POWER_CFG, data); 2409 2410 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 2411 data |= EN_10M_BGOFF; 2412 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 2413 data = ocp_reg_read(tp, OCP_POWER_CFG); 2414 data |= EN_10M_PLLOFF; 2415 ocp_reg_write(tp, OCP_POWER_CFG, data); 2416 data = sram_read(tp, SRAM_IMPEDANCE); 2417 data &= ~RX_DRIVING_MASK; 2418 sram_write(tp, SRAM_IMPEDANCE, data); 2419 2420 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 2421 ocp_data |= PFM_PWM_SWITCH; 2422 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 2423 2424 data = sram_read(tp, SRAM_LPF_CFG); 2425 data |= LPF_AUTO_TUNE; 2426 sram_write(tp, SRAM_LPF_CFG, data); 2427 2428 data = sram_read(tp, SRAM_10M_AMP1); 2429 data |= GDAC_IB_UPALL; 2430 sram_write(tp, SRAM_10M_AMP1, data); 2431 data = sram_read(tp, SRAM_10M_AMP2); 2432 data |= AMP_DN; 2433 sram_write(tp, SRAM_10M_AMP2, data); 2434 2435 set_bit(PHY_RESET, &tp->flags); 2436 } 2437 2438 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2439 { 2440 u8 u1u2[8]; 2441 2442 if (enable) 2443 memset(u1u2, 0xff, sizeof(u1u2)); 2444 else 2445 memset(u1u2, 0x00, sizeof(u1u2)); 2446 2447 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2448 } 2449 2450 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2451 { 2452 u32 ocp_data; 2453 2454 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2455 if (enable) 2456 ocp_data |= U2P3_ENABLE; 2457 else 2458 ocp_data &= ~U2P3_ENABLE; 2459 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2460 } 2461 2462 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2463 { 2464 u32 ocp_data; 2465 2466 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2467 if (enable) 2468 ocp_data |= PWR_EN | PHASE2_EN; 2469 else 2470 ocp_data &= ~(PWR_EN | PHASE2_EN); 2471 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2472 2473 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2474 ocp_data &= ~PCUT_STATUS; 2475 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2476 } 2477 2478 static void r8153_first_init(struct r8152 *tp) 2479 { 2480 u32 ocp_data; 2481 int i; 2482 2483 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2484 return; 2485 2486 rxdy_gated_en(tp, true); 2487 r8153_teredo_off(tp); 2488 2489 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2490 ocp_data &= ~RCR_ACPT_ALL; 2491 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2492 2493 r8153_hw_phy_cfg(tp); 2494 2495 rtl8152_nic_reset(tp); 2496 2497 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2498 ocp_data &= ~NOW_IS_OOB; 2499 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2500 2501 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2502 ocp_data &= ~MCU_BORW_EN; 2503 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2504 2505 for (i = 0; i < 1000; i++) { 2506 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2507 if (ocp_data & LINK_LIST_READY) 2508 break; 2509 mdelay(1); 2510 } 2511 2512 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2513 ocp_data |= RE_INIT_LL; 2514 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2515 2516 for (i = 0; i < 1000; i++) { 2517 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2518 if (ocp_data & LINK_LIST_READY) 2519 break; 2520 mdelay(1); 2521 } 2522 2523 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2524 ocp_data &= ~CPCR_RX_VLAN; 2525 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2526 2527 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2528 2529 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2530 ocp_data |= TCR0_AUTO_FIFO; 2531 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2532 2533 rtl8152_nic_reset(tp); 2534 2535 /* rx share fifo credit full threshold */ 2536 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2537 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 2538 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 2539 /* TX share fifo free credit full threshold */ 2540 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 2541 2542 /* rx aggregation */ 2543 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 2544 ocp_data &= ~RX_AGG_DISABLE; 2545 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 2546 } 2547 2548 static void r8153_enter_oob(struct r8152 *tp) 2549 { 2550 u32 ocp_data; 2551 int i; 2552 2553 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2554 ocp_data &= ~NOW_IS_OOB; 2555 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2556 2557 rtl8152_disable(tp); 2558 2559 for (i = 0; i < 1000; i++) { 2560 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2561 if (ocp_data & LINK_LIST_READY) 2562 break; 2563 mdelay(1); 2564 } 2565 2566 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2567 ocp_data |= RE_INIT_LL; 2568 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2569 2570 for (i = 0; i < 1000; i++) { 2571 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2572 if (ocp_data & LINK_LIST_READY) 2573 break; 2574 mdelay(1); 2575 } 2576 2577 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2578 2579 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2580 ocp_data &= ~TEREDO_WAKE_MASK; 2581 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2582 2583 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2584 ocp_data |= CPCR_RX_VLAN; 2585 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2586 2587 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2588 ocp_data |= ALDPS_PROXY_MODE; 2589 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2590 2591 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2592 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2593 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2594 2595 rxdy_gated_en(tp, false); 2596 2597 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2598 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2599 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2600 } 2601 2602 static void r8153_disable_aldps(struct r8152 *tp) 2603 { 2604 u16 data; 2605 2606 data = ocp_reg_read(tp, OCP_POWER_CFG); 2607 data &= ~EN_ALDPS; 2608 ocp_reg_write(tp, OCP_POWER_CFG, data); 2609 msleep(20); 2610 } 2611 2612 static void r8153_enable_aldps(struct r8152 *tp) 2613 { 2614 u16 data; 2615 2616 data = ocp_reg_read(tp, OCP_POWER_CFG); 2617 data |= EN_ALDPS; 2618 ocp_reg_write(tp, OCP_POWER_CFG, data); 2619 } 2620 2621 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 2622 { 2623 u16 bmcr, anar, gbcr; 2624 int ret = 0; 2625 2626 cancel_delayed_work_sync(&tp->schedule); 2627 anar = r8152_mdio_read(tp, MII_ADVERTISE); 2628 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 2629 ADVERTISE_100HALF | ADVERTISE_100FULL); 2630 if (tp->mii.supports_gmii) { 2631 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 2632 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 2633 } else { 2634 gbcr = 0; 2635 } 2636 2637 if (autoneg == AUTONEG_DISABLE) { 2638 if (speed == SPEED_10) { 2639 bmcr = 0; 2640 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2641 } else if (speed == SPEED_100) { 2642 bmcr = BMCR_SPEED100; 2643 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2644 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 2645 bmcr = BMCR_SPEED1000; 2646 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 2647 } else { 2648 ret = -EINVAL; 2649 goto out; 2650 } 2651 2652 if (duplex == DUPLEX_FULL) 2653 bmcr |= BMCR_FULLDPLX; 2654 } else { 2655 if (speed == SPEED_10) { 2656 if (duplex == DUPLEX_FULL) 2657 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2658 else 2659 anar |= ADVERTISE_10HALF; 2660 } else if (speed == SPEED_100) { 2661 if (duplex == DUPLEX_FULL) { 2662 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2663 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2664 } else { 2665 anar |= ADVERTISE_10HALF; 2666 anar |= ADVERTISE_100HALF; 2667 } 2668 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 2669 if (duplex == DUPLEX_FULL) { 2670 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2671 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2672 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 2673 } else { 2674 anar |= ADVERTISE_10HALF; 2675 anar |= ADVERTISE_100HALF; 2676 gbcr |= ADVERTISE_1000HALF; 2677 } 2678 } else { 2679 ret = -EINVAL; 2680 goto out; 2681 } 2682 2683 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 2684 } 2685 2686 if (test_bit(PHY_RESET, &tp->flags)) 2687 bmcr |= BMCR_RESET; 2688 2689 if (tp->mii.supports_gmii) 2690 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 2691 2692 r8152_mdio_write(tp, MII_ADVERTISE, anar); 2693 r8152_mdio_write(tp, MII_BMCR, bmcr); 2694 2695 if (test_bit(PHY_RESET, &tp->flags)) { 2696 int i; 2697 2698 clear_bit(PHY_RESET, &tp->flags); 2699 for (i = 0; i < 50; i++) { 2700 msleep(20); 2701 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 2702 break; 2703 } 2704 } 2705 2706 out: 2707 2708 return ret; 2709 } 2710 2711 static void rtl8152_down(struct r8152 *tp) 2712 { 2713 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2714 rtl_drop_queued_tx(tp); 2715 return; 2716 } 2717 2718 r8152_power_cut_en(tp, false); 2719 r8152b_disable_aldps(tp); 2720 r8152b_enter_oob(tp); 2721 r8152b_enable_aldps(tp); 2722 } 2723 2724 static void rtl8153_down(struct r8152 *tp) 2725 { 2726 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2727 rtl_drop_queued_tx(tp); 2728 return; 2729 } 2730 2731 r8153_u1u2en(tp, false); 2732 r8153_power_cut_en(tp, false); 2733 r8153_disable_aldps(tp); 2734 r8153_enter_oob(tp); 2735 r8153_enable_aldps(tp); 2736 } 2737 2738 static void set_carrier(struct r8152 *tp) 2739 { 2740 struct net_device *netdev = tp->netdev; 2741 u8 speed; 2742 2743 clear_bit(RTL8152_LINK_CHG, &tp->flags); 2744 speed = rtl8152_get_speed(tp); 2745 2746 if (speed & LINK_STATUS) { 2747 if (!(tp->speed & LINK_STATUS)) { 2748 tp->rtl_ops.enable(tp); 2749 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2750 netif_carrier_on(netdev); 2751 } 2752 } else { 2753 if (tp->speed & LINK_STATUS) { 2754 netif_carrier_off(netdev); 2755 tasklet_disable(&tp->tl); 2756 tp->rtl_ops.disable(tp); 2757 tasklet_enable(&tp->tl); 2758 } 2759 } 2760 tp->speed = speed; 2761 } 2762 2763 static void rtl_work_func_t(struct work_struct *work) 2764 { 2765 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 2766 2767 if (usb_autopm_get_interface(tp->intf) < 0) 2768 return; 2769 2770 if (!test_bit(WORK_ENABLE, &tp->flags)) 2771 goto out1; 2772 2773 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2774 goto out1; 2775 2776 if (test_bit(RTL8152_LINK_CHG, &tp->flags)) 2777 set_carrier(tp); 2778 2779 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) 2780 _rtl8152_set_rx_mode(tp->netdev); 2781 2782 if (test_bit(SCHEDULE_TASKLET, &tp->flags) && 2783 (tp->speed & LINK_STATUS)) { 2784 clear_bit(SCHEDULE_TASKLET, &tp->flags); 2785 tasklet_schedule(&tp->tl); 2786 } 2787 2788 if (test_bit(PHY_RESET, &tp->flags)) 2789 rtl_phy_reset(tp); 2790 2791 out1: 2792 usb_autopm_put_interface(tp->intf); 2793 } 2794 2795 static int rtl8152_open(struct net_device *netdev) 2796 { 2797 struct r8152 *tp = netdev_priv(netdev); 2798 int res = 0; 2799 2800 res = alloc_all_mem(tp); 2801 if (res) 2802 goto out; 2803 2804 res = usb_autopm_get_interface(tp->intf); 2805 if (res < 0) { 2806 free_all_mem(tp); 2807 goto out; 2808 } 2809 2810 /* The WORK_ENABLE may be set when autoresume occurs */ 2811 if (test_bit(WORK_ENABLE, &tp->flags)) { 2812 clear_bit(WORK_ENABLE, &tp->flags); 2813 usb_kill_urb(tp->intr_urb); 2814 cancel_delayed_work_sync(&tp->schedule); 2815 if (tp->speed & LINK_STATUS) 2816 tp->rtl_ops.disable(tp); 2817 } 2818 2819 tp->rtl_ops.up(tp); 2820 2821 rtl8152_set_speed(tp, AUTONEG_ENABLE, 2822 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, 2823 DUPLEX_FULL); 2824 tp->speed = 0; 2825 netif_carrier_off(netdev); 2826 netif_start_queue(netdev); 2827 set_bit(WORK_ENABLE, &tp->flags); 2828 2829 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 2830 if (res) { 2831 if (res == -ENODEV) 2832 netif_device_detach(tp->netdev); 2833 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 2834 res); 2835 free_all_mem(tp); 2836 } 2837 2838 usb_autopm_put_interface(tp->intf); 2839 2840 out: 2841 return res; 2842 } 2843 2844 static int rtl8152_close(struct net_device *netdev) 2845 { 2846 struct r8152 *tp = netdev_priv(netdev); 2847 int res = 0; 2848 2849 clear_bit(WORK_ENABLE, &tp->flags); 2850 usb_kill_urb(tp->intr_urb); 2851 cancel_delayed_work_sync(&tp->schedule); 2852 netif_stop_queue(netdev); 2853 2854 res = usb_autopm_get_interface(tp->intf); 2855 if (res < 0) { 2856 rtl_drop_queued_tx(tp); 2857 } else { 2858 /* 2859 * The autosuspend may have been enabled and wouldn't 2860 * be disable when autoresume occurs, because the 2861 * netif_running() would be false. 2862 */ 2863 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2864 rtl_runtime_suspend_enable(tp, false); 2865 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 2866 } 2867 2868 tasklet_disable(&tp->tl); 2869 tp->rtl_ops.down(tp); 2870 tasklet_enable(&tp->tl); 2871 usb_autopm_put_interface(tp->intf); 2872 } 2873 2874 free_all_mem(tp); 2875 2876 return res; 2877 } 2878 2879 static void r8152b_enable_eee(struct r8152 *tp) 2880 { 2881 u32 ocp_data; 2882 2883 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 2884 ocp_data |= EEE_RX_EN | EEE_TX_EN; 2885 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 2886 ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN | 2887 EEE_10_CAP | EEE_NWAY_EN | 2888 TX_QUIET_EN | RX_QUIET_EN | 2889 SDRISETIME | RG_RXLPI_MSK_HFDUP | 2890 SDFALLTIME); 2891 ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN | 2892 RG_LDVQUIET_EN | RG_CKRSEL | 2893 RG_EEEPRG_EN); 2894 ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH); 2895 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR); 2896 ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR); 2897 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR); 2898 ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA); 2899 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 2900 } 2901 2902 static void r8153_enable_eee(struct r8152 *tp) 2903 { 2904 u32 ocp_data; 2905 u16 data; 2906 2907 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 2908 ocp_data |= EEE_RX_EN | EEE_TX_EN; 2909 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 2910 data = ocp_reg_read(tp, OCP_EEE_CFG); 2911 data |= EEE10_EN; 2912 ocp_reg_write(tp, OCP_EEE_CFG, data); 2913 data = ocp_reg_read(tp, OCP_EEE_CFG2); 2914 data |= MY1000_EEE | MY100_EEE; 2915 ocp_reg_write(tp, OCP_EEE_CFG2, data); 2916 } 2917 2918 static void r8152b_enable_fc(struct r8152 *tp) 2919 { 2920 u16 anar; 2921 2922 anar = r8152_mdio_read(tp, MII_ADVERTISE); 2923 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 2924 r8152_mdio_write(tp, MII_ADVERTISE, anar); 2925 } 2926 2927 static void rtl_tally_reset(struct r8152 *tp) 2928 { 2929 u32 ocp_data; 2930 2931 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 2932 ocp_data |= TALLY_RESET; 2933 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 2934 } 2935 2936 static void r8152b_init(struct r8152 *tp) 2937 { 2938 u32 ocp_data; 2939 2940 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2941 return; 2942 2943 if (tp->version == RTL_VER_01) { 2944 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 2945 ocp_data &= ~LED_MODE_MASK; 2946 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 2947 } 2948 2949 r8152_power_cut_en(tp, false); 2950 2951 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 2952 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 2953 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 2954 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 2955 ocp_data &= ~MCU_CLK_RATIO_MASK; 2956 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 2957 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 2958 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 2959 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 2960 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 2961 2962 r8152b_enable_eee(tp); 2963 r8152b_enable_aldps(tp); 2964 r8152b_enable_fc(tp); 2965 rtl_tally_reset(tp); 2966 2967 /* enable rx aggregation */ 2968 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 2969 ocp_data &= ~RX_AGG_DISABLE; 2970 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 2971 } 2972 2973 static void r8153_init(struct r8152 *tp) 2974 { 2975 u32 ocp_data; 2976 int i; 2977 2978 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2979 return; 2980 2981 r8153_u1u2en(tp, false); 2982 2983 for (i = 0; i < 500; i++) { 2984 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 2985 AUTOLOAD_DONE) 2986 break; 2987 msleep(20); 2988 } 2989 2990 for (i = 0; i < 500; i++) { 2991 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; 2992 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) 2993 break; 2994 msleep(20); 2995 } 2996 2997 r8153_u2p3en(tp, false); 2998 2999 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 3000 ocp_data &= ~TIMER11_EN; 3001 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 3002 3003 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 3004 ocp_data &= ~LED_MODE_MASK; 3005 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 3006 3007 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL); 3008 ocp_data &= ~LPM_TIMER_MASK; 3009 if (tp->udev->speed == USB_SPEED_SUPER) 3010 ocp_data |= LPM_TIMER_500US; 3011 else 3012 ocp_data |= LPM_TIMER_500MS; 3013 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 3014 3015 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 3016 ocp_data &= ~SEN_VAL_MASK; 3017 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 3018 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 3019 3020 r8153_power_cut_en(tp, false); 3021 r8153_u1u2en(tp, true); 3022 3023 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); 3024 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); 3025 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 3026 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | 3027 U1U2_SPDWN_EN | L1_SPDWN_EN); 3028 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 3029 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | 3030 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | 3031 EEE_SPDWN_EN); 3032 3033 r8153_enable_eee(tp); 3034 r8153_enable_aldps(tp); 3035 r8152b_enable_fc(tp); 3036 rtl_tally_reset(tp); 3037 } 3038 3039 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 3040 { 3041 struct r8152 *tp = usb_get_intfdata(intf); 3042 3043 if (PMSG_IS_AUTO(message)) 3044 set_bit(SELECTIVE_SUSPEND, &tp->flags); 3045 else 3046 netif_device_detach(tp->netdev); 3047 3048 if (netif_running(tp->netdev)) { 3049 clear_bit(WORK_ENABLE, &tp->flags); 3050 usb_kill_urb(tp->intr_urb); 3051 cancel_delayed_work_sync(&tp->schedule); 3052 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3053 rtl_runtime_suspend_enable(tp, true); 3054 } else { 3055 tasklet_disable(&tp->tl); 3056 tp->rtl_ops.down(tp); 3057 tasklet_enable(&tp->tl); 3058 } 3059 } 3060 3061 return 0; 3062 } 3063 3064 static int rtl8152_resume(struct usb_interface *intf) 3065 { 3066 struct r8152 *tp = usb_get_intfdata(intf); 3067 3068 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3069 tp->rtl_ops.init(tp); 3070 netif_device_attach(tp->netdev); 3071 } 3072 3073 if (netif_running(tp->netdev)) { 3074 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3075 rtl_runtime_suspend_enable(tp, false); 3076 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3077 if (tp->speed & LINK_STATUS) 3078 tp->rtl_ops.disable(tp); 3079 } else { 3080 tp->rtl_ops.up(tp); 3081 rtl8152_set_speed(tp, AUTONEG_ENABLE, 3082 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, 3083 DUPLEX_FULL); 3084 } 3085 tp->speed = 0; 3086 netif_carrier_off(tp->netdev); 3087 set_bit(WORK_ENABLE, &tp->flags); 3088 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3089 } 3090 3091 return 0; 3092 } 3093 3094 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3095 { 3096 struct r8152 *tp = netdev_priv(dev); 3097 3098 if (usb_autopm_get_interface(tp->intf) < 0) 3099 return; 3100 3101 wol->supported = WAKE_ANY; 3102 wol->wolopts = __rtl_get_wol(tp); 3103 3104 usb_autopm_put_interface(tp->intf); 3105 } 3106 3107 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3108 { 3109 struct r8152 *tp = netdev_priv(dev); 3110 int ret; 3111 3112 ret = usb_autopm_get_interface(tp->intf); 3113 if (ret < 0) 3114 goto out_set_wol; 3115 3116 __rtl_set_wol(tp, wol->wolopts); 3117 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 3118 3119 usb_autopm_put_interface(tp->intf); 3120 3121 out_set_wol: 3122 return ret; 3123 } 3124 3125 static u32 rtl8152_get_msglevel(struct net_device *dev) 3126 { 3127 struct r8152 *tp = netdev_priv(dev); 3128 3129 return tp->msg_enable; 3130 } 3131 3132 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 3133 { 3134 struct r8152 *tp = netdev_priv(dev); 3135 3136 tp->msg_enable = value; 3137 } 3138 3139 static void rtl8152_get_drvinfo(struct net_device *netdev, 3140 struct ethtool_drvinfo *info) 3141 { 3142 struct r8152 *tp = netdev_priv(netdev); 3143 3144 strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN); 3145 strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN); 3146 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 3147 } 3148 3149 static 3150 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) 3151 { 3152 struct r8152 *tp = netdev_priv(netdev); 3153 3154 if (!tp->mii.mdio_read) 3155 return -EOPNOTSUPP; 3156 3157 return mii_ethtool_gset(&tp->mii, cmd); 3158 } 3159 3160 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 3161 { 3162 struct r8152 *tp = netdev_priv(dev); 3163 int ret; 3164 3165 ret = usb_autopm_get_interface(tp->intf); 3166 if (ret < 0) 3167 goto out; 3168 3169 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); 3170 3171 usb_autopm_put_interface(tp->intf); 3172 3173 out: 3174 return ret; 3175 } 3176 3177 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 3178 "tx_packets", 3179 "rx_packets", 3180 "tx_errors", 3181 "rx_errors", 3182 "rx_missed", 3183 "align_errors", 3184 "tx_single_collisions", 3185 "tx_multi_collisions", 3186 "rx_unicast", 3187 "rx_broadcast", 3188 "rx_multicast", 3189 "tx_aborted", 3190 "tx_underrun", 3191 }; 3192 3193 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 3194 { 3195 switch (sset) { 3196 case ETH_SS_STATS: 3197 return ARRAY_SIZE(rtl8152_gstrings); 3198 default: 3199 return -EOPNOTSUPP; 3200 } 3201 } 3202 3203 static void rtl8152_get_ethtool_stats(struct net_device *dev, 3204 struct ethtool_stats *stats, u64 *data) 3205 { 3206 struct r8152 *tp = netdev_priv(dev); 3207 struct tally_counter tally; 3208 3209 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 3210 3211 data[0] = le64_to_cpu(tally.tx_packets); 3212 data[1] = le64_to_cpu(tally.rx_packets); 3213 data[2] = le64_to_cpu(tally.tx_errors); 3214 data[3] = le32_to_cpu(tally.rx_errors); 3215 data[4] = le16_to_cpu(tally.rx_missed); 3216 data[5] = le16_to_cpu(tally.align_errors); 3217 data[6] = le32_to_cpu(tally.tx_one_collision); 3218 data[7] = le32_to_cpu(tally.tx_multi_collision); 3219 data[8] = le64_to_cpu(tally.rx_unicast); 3220 data[9] = le64_to_cpu(tally.rx_broadcast); 3221 data[10] = le32_to_cpu(tally.rx_multicast); 3222 data[11] = le16_to_cpu(tally.tx_aborted); 3223 data[12] = le16_to_cpu(tally.tx_underun); 3224 } 3225 3226 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 3227 { 3228 switch (stringset) { 3229 case ETH_SS_STATS: 3230 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 3231 break; 3232 } 3233 } 3234 3235 static struct ethtool_ops ops = { 3236 .get_drvinfo = rtl8152_get_drvinfo, 3237 .get_settings = rtl8152_get_settings, 3238 .set_settings = rtl8152_set_settings, 3239 .get_link = ethtool_op_get_link, 3240 .get_msglevel = rtl8152_get_msglevel, 3241 .set_msglevel = rtl8152_set_msglevel, 3242 .get_wol = rtl8152_get_wol, 3243 .set_wol = rtl8152_set_wol, 3244 .get_strings = rtl8152_get_strings, 3245 .get_sset_count = rtl8152_get_sset_count, 3246 .get_ethtool_stats = rtl8152_get_ethtool_stats, 3247 }; 3248 3249 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 3250 { 3251 struct r8152 *tp = netdev_priv(netdev); 3252 struct mii_ioctl_data *data = if_mii(rq); 3253 int res; 3254 3255 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3256 return -ENODEV; 3257 3258 res = usb_autopm_get_interface(tp->intf); 3259 if (res < 0) 3260 goto out; 3261 3262 switch (cmd) { 3263 case SIOCGMIIPHY: 3264 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 3265 break; 3266 3267 case SIOCGMIIREG: 3268 data->val_out = r8152_mdio_read(tp, data->reg_num); 3269 break; 3270 3271 case SIOCSMIIREG: 3272 if (!capable(CAP_NET_ADMIN)) { 3273 res = -EPERM; 3274 break; 3275 } 3276 r8152_mdio_write(tp, data->reg_num, data->val_in); 3277 break; 3278 3279 default: 3280 res = -EOPNOTSUPP; 3281 } 3282 3283 usb_autopm_put_interface(tp->intf); 3284 3285 out: 3286 return res; 3287 } 3288 3289 static const struct net_device_ops rtl8152_netdev_ops = { 3290 .ndo_open = rtl8152_open, 3291 .ndo_stop = rtl8152_close, 3292 .ndo_do_ioctl = rtl8152_ioctl, 3293 .ndo_start_xmit = rtl8152_start_xmit, 3294 .ndo_tx_timeout = rtl8152_tx_timeout, 3295 .ndo_set_rx_mode = rtl8152_set_rx_mode, 3296 .ndo_set_mac_address = rtl8152_set_mac_address, 3297 3298 .ndo_change_mtu = eth_change_mtu, 3299 .ndo_validate_addr = eth_validate_addr, 3300 }; 3301 3302 static void r8152b_get_version(struct r8152 *tp) 3303 { 3304 u32 ocp_data; 3305 u16 version; 3306 3307 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); 3308 version = (u16)(ocp_data & VERSION_MASK); 3309 3310 switch (version) { 3311 case 0x4c00: 3312 tp->version = RTL_VER_01; 3313 break; 3314 case 0x4c10: 3315 tp->version = RTL_VER_02; 3316 break; 3317 case 0x5c00: 3318 tp->version = RTL_VER_03; 3319 tp->mii.supports_gmii = 1; 3320 break; 3321 case 0x5c10: 3322 tp->version = RTL_VER_04; 3323 tp->mii.supports_gmii = 1; 3324 break; 3325 case 0x5c20: 3326 tp->version = RTL_VER_05; 3327 tp->mii.supports_gmii = 1; 3328 break; 3329 default: 3330 netif_info(tp, probe, tp->netdev, 3331 "Unknown version 0x%04x\n", version); 3332 break; 3333 } 3334 } 3335 3336 static void rtl8152_unload(struct r8152 *tp) 3337 { 3338 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3339 return; 3340 3341 if (tp->version != RTL_VER_01) 3342 r8152_power_cut_en(tp, true); 3343 } 3344 3345 static void rtl8153_unload(struct r8152 *tp) 3346 { 3347 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3348 return; 3349 3350 r8153_power_cut_en(tp, true); 3351 } 3352 3353 static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id) 3354 { 3355 struct rtl_ops *ops = &tp->rtl_ops; 3356 int ret = -ENODEV; 3357 3358 switch (id->idVendor) { 3359 case VENDOR_ID_REALTEK: 3360 switch (id->idProduct) { 3361 case PRODUCT_ID_RTL8152: 3362 ops->init = r8152b_init; 3363 ops->enable = rtl8152_enable; 3364 ops->disable = rtl8152_disable; 3365 ops->up = r8152b_exit_oob; 3366 ops->down = rtl8152_down; 3367 ops->unload = rtl8152_unload; 3368 ret = 0; 3369 break; 3370 case PRODUCT_ID_RTL8153: 3371 ops->init = r8153_init; 3372 ops->enable = rtl8153_enable; 3373 ops->disable = rtl8152_disable; 3374 ops->up = r8153_first_init; 3375 ops->down = rtl8153_down; 3376 ops->unload = rtl8153_unload; 3377 ret = 0; 3378 break; 3379 default: 3380 break; 3381 } 3382 break; 3383 3384 case VENDOR_ID_SAMSUNG: 3385 switch (id->idProduct) { 3386 case PRODUCT_ID_SAMSUNG: 3387 ops->init = r8153_init; 3388 ops->enable = rtl8153_enable; 3389 ops->disable = rtl8152_disable; 3390 ops->up = r8153_first_init; 3391 ops->down = rtl8153_down; 3392 ops->unload = rtl8153_unload; 3393 ret = 0; 3394 break; 3395 default: 3396 break; 3397 } 3398 break; 3399 3400 default: 3401 break; 3402 } 3403 3404 if (ret) 3405 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 3406 3407 return ret; 3408 } 3409 3410 static int rtl8152_probe(struct usb_interface *intf, 3411 const struct usb_device_id *id) 3412 { 3413 struct usb_device *udev = interface_to_usbdev(intf); 3414 struct r8152 *tp; 3415 struct net_device *netdev; 3416 int ret; 3417 3418 if (udev->actconfig->desc.bConfigurationValue != 1) { 3419 usb_driver_set_configuration(udev, 1); 3420 return -ENODEV; 3421 } 3422 3423 usb_reset_device(udev); 3424 netdev = alloc_etherdev(sizeof(struct r8152)); 3425 if (!netdev) { 3426 dev_err(&intf->dev, "Out of memory\n"); 3427 return -ENOMEM; 3428 } 3429 3430 SET_NETDEV_DEV(netdev, &intf->dev); 3431 tp = netdev_priv(netdev); 3432 tp->msg_enable = 0x7FFF; 3433 3434 tp->udev = udev; 3435 tp->netdev = netdev; 3436 tp->intf = intf; 3437 3438 ret = rtl_ops_init(tp, id); 3439 if (ret) 3440 goto out; 3441 3442 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp); 3443 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 3444 3445 netdev->netdev_ops = &rtl8152_netdev_ops; 3446 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 3447 3448 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 3449 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 3450 NETIF_F_TSO6; 3451 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 3452 NETIF_F_TSO | NETIF_F_FRAGLIST | 3453 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 3454 3455 SET_ETHTOOL_OPS(netdev, &ops); 3456 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 3457 3458 tp->mii.dev = netdev; 3459 tp->mii.mdio_read = read_mii_word; 3460 tp->mii.mdio_write = write_mii_word; 3461 tp->mii.phy_id_mask = 0x3f; 3462 tp->mii.reg_num_mask = 0x1f; 3463 tp->mii.phy_id = R8152_PHY_ID; 3464 tp->mii.supports_gmii = 0; 3465 3466 intf->needs_remote_wakeup = 1; 3467 3468 r8152b_get_version(tp); 3469 tp->rtl_ops.init(tp); 3470 set_ethernet_addr(tp); 3471 3472 usb_set_intfdata(intf, tp); 3473 3474 ret = register_netdev(netdev); 3475 if (ret != 0) { 3476 netif_err(tp, probe, netdev, "couldn't register the device\n"); 3477 goto out1; 3478 } 3479 3480 tp->saved_wolopts = __rtl_get_wol(tp); 3481 if (tp->saved_wolopts) 3482 device_set_wakeup_enable(&udev->dev, true); 3483 else 3484 device_set_wakeup_enable(&udev->dev, false); 3485 3486 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 3487 3488 return 0; 3489 3490 out1: 3491 usb_set_intfdata(intf, NULL); 3492 out: 3493 free_netdev(netdev); 3494 return ret; 3495 } 3496 3497 static void rtl8152_disconnect(struct usb_interface *intf) 3498 { 3499 struct r8152 *tp = usb_get_intfdata(intf); 3500 3501 usb_set_intfdata(intf, NULL); 3502 if (tp) { 3503 set_bit(RTL8152_UNPLUG, &tp->flags); 3504 tasklet_kill(&tp->tl); 3505 unregister_netdev(tp->netdev); 3506 tp->rtl_ops.unload(tp); 3507 free_netdev(tp->netdev); 3508 } 3509 } 3510 3511 /* table of devices that work with this driver */ 3512 static struct usb_device_id rtl8152_table[] = { 3513 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)}, 3514 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)}, 3515 {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)}, 3516 {} 3517 }; 3518 3519 MODULE_DEVICE_TABLE(usb, rtl8152_table); 3520 3521 static struct usb_driver rtl8152_driver = { 3522 .name = MODULENAME, 3523 .id_table = rtl8152_table, 3524 .probe = rtl8152_probe, 3525 .disconnect = rtl8152_disconnect, 3526 .suspend = rtl8152_suspend, 3527 .resume = rtl8152_resume, 3528 .reset_resume = rtl8152_resume, 3529 .supports_autosuspend = 1, 3530 .disable_hub_initiated_lpm = 1, 3531 }; 3532 3533 module_usb_driver(rtl8152_driver); 3534 3535 MODULE_AUTHOR(DRIVER_AUTHOR); 3536 MODULE_DESCRIPTION(DRIVER_DESC); 3537 MODULE_LICENSE("GPL"); 3538