1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 4 */ 5 6 #include <linux/signal.h> 7 #include <linux/slab.h> 8 #include <linux/module.h> 9 #include <linux/netdevice.h> 10 #include <linux/etherdevice.h> 11 #include <linux/mii.h> 12 #include <linux/ethtool.h> 13 #include <linux/usb.h> 14 #include <linux/crc32.h> 15 #include <linux/if_vlan.h> 16 #include <linux/uaccess.h> 17 #include <linux/list.h> 18 #include <linux/ip.h> 19 #include <linux/ipv6.h> 20 #include <net/ip6_checksum.h> 21 #include <uapi/linux/mdio.h> 22 #include <linux/mdio.h> 23 #include <linux/usb/cdc.h> 24 #include <linux/suspend.h> 25 #include <linux/atomic.h> 26 #include <linux/acpi.h> 27 28 /* Information for net-next */ 29 #define NETNEXT_VERSION "10" 30 31 /* Information for net */ 32 #define NET_VERSION "10" 33 34 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION 35 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 36 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 37 #define MODULENAME "r8152" 38 39 #define R8152_PHY_ID 32 40 41 #define PLA_IDR 0xc000 42 #define PLA_RCR 0xc010 43 #define PLA_RMS 0xc016 44 #define PLA_RXFIFO_CTRL0 0xc0a0 45 #define PLA_RXFIFO_CTRL1 0xc0a4 46 #define PLA_RXFIFO_CTRL2 0xc0a8 47 #define PLA_DMY_REG0 0xc0b0 48 #define PLA_FMC 0xc0b4 49 #define PLA_CFG_WOL 0xc0b6 50 #define PLA_TEREDO_CFG 0xc0bc 51 #define PLA_TEREDO_WAKE_BASE 0xc0c4 52 #define PLA_MAR 0xcd00 53 #define PLA_BACKUP 0xd000 54 #define PLA_BDC_CR 0xd1a0 55 #define PLA_TEREDO_TIMER 0xd2cc 56 #define PLA_REALWOW_TIMER 0xd2e8 57 #define PLA_SUSPEND_FLAG 0xd38a 58 #define PLA_INDICATE_FALG 0xd38c 59 #define PLA_EXTRA_STATUS 0xd398 60 #define PLA_EFUSE_DATA 0xdd00 61 #define PLA_EFUSE_CMD 0xdd02 62 #define PLA_LEDSEL 0xdd90 63 #define PLA_LED_FEATURE 0xdd92 64 #define PLA_PHYAR 0xde00 65 #define PLA_BOOT_CTRL 0xe004 66 #define PLA_GPHY_INTR_IMR 0xe022 67 #define PLA_EEE_CR 0xe040 68 #define PLA_EEEP_CR 0xe080 69 #define PLA_MAC_PWR_CTRL 0xe0c0 70 #define PLA_MAC_PWR_CTRL2 0xe0ca 71 #define PLA_MAC_PWR_CTRL3 0xe0cc 72 #define PLA_MAC_PWR_CTRL4 0xe0ce 73 #define PLA_WDT6_CTRL 0xe428 74 #define PLA_TCR0 0xe610 75 #define PLA_TCR1 0xe612 76 #define PLA_MTPS 0xe615 77 #define PLA_TXFIFO_CTRL 0xe618 78 #define PLA_RSTTALLY 0xe800 79 #define PLA_CR 0xe813 80 #define PLA_CRWECR 0xe81c 81 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 82 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 83 #define PLA_CONFIG5 0xe822 84 #define PLA_PHY_PWR 0xe84c 85 #define PLA_OOB_CTRL 0xe84f 86 #define PLA_CPCR 0xe854 87 #define PLA_MISC_0 0xe858 88 #define PLA_MISC_1 0xe85a 89 #define PLA_OCP_GPHY_BASE 0xe86c 90 #define PLA_TALLYCNT 0xe890 91 #define PLA_SFF_STS_7 0xe8de 92 #define PLA_PHYSTATUS 0xe908 93 #define PLA_BP_BA 0xfc26 94 #define PLA_BP_0 0xfc28 95 #define PLA_BP_1 0xfc2a 96 #define PLA_BP_2 0xfc2c 97 #define PLA_BP_3 0xfc2e 98 #define PLA_BP_4 0xfc30 99 #define PLA_BP_5 0xfc32 100 #define PLA_BP_6 0xfc34 101 #define PLA_BP_7 0xfc36 102 #define PLA_BP_EN 0xfc38 103 104 #define USB_USB2PHY 0xb41e 105 #define USB_SSPHYLINK2 0xb428 106 #define USB_U2P3_CTRL 0xb460 107 #define USB_CSR_DUMMY1 0xb464 108 #define USB_CSR_DUMMY2 0xb466 109 #define USB_DEV_STAT 0xb808 110 #define USB_CONNECT_TIMER 0xcbf8 111 #define USB_MSC_TIMER 0xcbfc 112 #define USB_BURST_SIZE 0xcfc0 113 #define USB_LPM_CONFIG 0xcfd8 114 #define USB_USB_CTRL 0xd406 115 #define USB_PHY_CTRL 0xd408 116 #define USB_TX_AGG 0xd40a 117 #define USB_RX_BUF_TH 0xd40c 118 #define USB_USB_TIMER 0xd428 119 #define USB_RX_EARLY_TIMEOUT 0xd42c 120 #define USB_RX_EARLY_SIZE 0xd42e 121 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ 122 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ 123 #define USB_TX_DMA 0xd434 124 #define USB_UPT_RXDMA_OWN 0xd437 125 #define USB_TOLERANCE 0xd490 126 #define USB_LPM_CTRL 0xd41a 127 #define USB_BMU_RESET 0xd4b0 128 #define USB_U1U2_TIMER 0xd4da 129 #define USB_UPS_CTRL 0xd800 130 #define USB_POWER_CUT 0xd80a 131 #define USB_MISC_0 0xd81a 132 #define USB_MISC_1 0xd81f 133 #define USB_AFE_CTRL2 0xd824 134 #define USB_UPS_CFG 0xd842 135 #define USB_UPS_FLAGS 0xd848 136 #define USB_WDT11_CTRL 0xe43c 137 #define USB_BP_BA 0xfc26 138 #define USB_BP_0 0xfc28 139 #define USB_BP_1 0xfc2a 140 #define USB_BP_2 0xfc2c 141 #define USB_BP_3 0xfc2e 142 #define USB_BP_4 0xfc30 143 #define USB_BP_5 0xfc32 144 #define USB_BP_6 0xfc34 145 #define USB_BP_7 0xfc36 146 #define USB_BP_EN 0xfc38 147 #define USB_BP_8 0xfc38 148 #define USB_BP_9 0xfc3a 149 #define USB_BP_10 0xfc3c 150 #define USB_BP_11 0xfc3e 151 #define USB_BP_12 0xfc40 152 #define USB_BP_13 0xfc42 153 #define USB_BP_14 0xfc44 154 #define USB_BP_15 0xfc46 155 #define USB_BP2_EN 0xfc48 156 157 /* OCP Registers */ 158 #define OCP_ALDPS_CONFIG 0x2010 159 #define OCP_EEE_CONFIG1 0x2080 160 #define OCP_EEE_CONFIG2 0x2092 161 #define OCP_EEE_CONFIG3 0x2094 162 #define OCP_BASE_MII 0xa400 163 #define OCP_EEE_AR 0xa41a 164 #define OCP_EEE_DATA 0xa41c 165 #define OCP_PHY_STATUS 0xa420 166 #define OCP_NCTL_CFG 0xa42c 167 #define OCP_POWER_CFG 0xa430 168 #define OCP_EEE_CFG 0xa432 169 #define OCP_SRAM_ADDR 0xa436 170 #define OCP_SRAM_DATA 0xa438 171 #define OCP_DOWN_SPEED 0xa442 172 #define OCP_EEE_ABLE 0xa5c4 173 #define OCP_EEE_ADV 0xa5d0 174 #define OCP_EEE_LPABLE 0xa5d2 175 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ 176 #define OCP_PHY_PATCH_STAT 0xb800 177 #define OCP_PHY_PATCH_CMD 0xb820 178 #define OCP_ADC_IOFFSET 0xbcfc 179 #define OCP_ADC_CFG 0xbc06 180 #define OCP_SYSCLK_CFG 0xc416 181 182 /* SRAM Register */ 183 #define SRAM_GREEN_CFG 0x8011 184 #define SRAM_LPF_CFG 0x8012 185 #define SRAM_10M_AMP1 0x8080 186 #define SRAM_10M_AMP2 0x8082 187 #define SRAM_IMPEDANCE 0x8084 188 189 /* PLA_RCR */ 190 #define RCR_AAP 0x00000001 191 #define RCR_APM 0x00000002 192 #define RCR_AM 0x00000004 193 #define RCR_AB 0x00000008 194 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 195 196 /* PLA_RXFIFO_CTRL0 */ 197 #define RXFIFO_THR1_NORMAL 0x00080002 198 #define RXFIFO_THR1_OOB 0x01800003 199 200 /* PLA_RXFIFO_CTRL1 */ 201 #define RXFIFO_THR2_FULL 0x00000060 202 #define RXFIFO_THR2_HIGH 0x00000038 203 #define RXFIFO_THR2_OOB 0x0000004a 204 #define RXFIFO_THR2_NORMAL 0x00a0 205 206 /* PLA_RXFIFO_CTRL2 */ 207 #define RXFIFO_THR3_FULL 0x00000078 208 #define RXFIFO_THR3_HIGH 0x00000048 209 #define RXFIFO_THR3_OOB 0x0000005a 210 #define RXFIFO_THR3_NORMAL 0x0110 211 212 /* PLA_TXFIFO_CTRL */ 213 #define TXFIFO_THR_NORMAL 0x00400008 214 #define TXFIFO_THR_NORMAL2 0x01000008 215 216 /* PLA_DMY_REG0 */ 217 #define ECM_ALDPS 0x0002 218 219 /* PLA_FMC */ 220 #define FMC_FCR_MCU_EN 0x0001 221 222 /* PLA_EEEP_CR */ 223 #define EEEP_CR_EEEP_TX 0x0002 224 225 /* PLA_WDT6_CTRL */ 226 #define WDT6_SET_MODE 0x0010 227 228 /* PLA_TCR0 */ 229 #define TCR0_TX_EMPTY 0x0800 230 #define TCR0_AUTO_FIFO 0x0080 231 232 /* PLA_TCR1 */ 233 #define VERSION_MASK 0x7cf0 234 235 /* PLA_MTPS */ 236 #define MTPS_JUMBO (12 * 1024 / 64) 237 #define MTPS_DEFAULT (6 * 1024 / 64) 238 239 /* PLA_RSTTALLY */ 240 #define TALLY_RESET 0x0001 241 242 /* PLA_CR */ 243 #define CR_RST 0x10 244 #define CR_RE 0x08 245 #define CR_TE 0x04 246 247 /* PLA_CRWECR */ 248 #define CRWECR_NORAML 0x00 249 #define CRWECR_CONFIG 0xc0 250 251 /* PLA_OOB_CTRL */ 252 #define NOW_IS_OOB 0x80 253 #define TXFIFO_EMPTY 0x20 254 #define RXFIFO_EMPTY 0x10 255 #define LINK_LIST_READY 0x02 256 #define DIS_MCU_CLROOB 0x01 257 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 258 259 /* PLA_MISC_1 */ 260 #define RXDY_GATED_EN 0x0008 261 262 /* PLA_SFF_STS_7 */ 263 #define RE_INIT_LL 0x8000 264 #define MCU_BORW_EN 0x4000 265 266 /* PLA_CPCR */ 267 #define CPCR_RX_VLAN 0x0040 268 269 /* PLA_CFG_WOL */ 270 #define MAGIC_EN 0x0001 271 272 /* PLA_TEREDO_CFG */ 273 #define TEREDO_SEL 0x8000 274 #define TEREDO_WAKE_MASK 0x7f00 275 #define TEREDO_RS_EVENT_MASK 0x00fe 276 #define OOB_TEREDO_EN 0x0001 277 278 /* PLA_BDC_CR */ 279 #define ALDPS_PROXY_MODE 0x0001 280 281 /* PLA_EFUSE_CMD */ 282 #define EFUSE_READ_CMD BIT(15) 283 #define EFUSE_DATA_BIT16 BIT(7) 284 285 /* PLA_CONFIG34 */ 286 #define LINK_ON_WAKE_EN 0x0010 287 #define LINK_OFF_WAKE_EN 0x0008 288 289 /* PLA_CONFIG5 */ 290 #define BWF_EN 0x0040 291 #define MWF_EN 0x0020 292 #define UWF_EN 0x0010 293 #define LAN_WAKE_EN 0x0002 294 295 /* PLA_LED_FEATURE */ 296 #define LED_MODE_MASK 0x0700 297 298 /* PLA_PHY_PWR */ 299 #define TX_10M_IDLE_EN 0x0080 300 #define PFM_PWM_SWITCH 0x0040 301 302 /* PLA_MAC_PWR_CTRL */ 303 #define D3_CLK_GATED_EN 0x00004000 304 #define MCU_CLK_RATIO 0x07010f07 305 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 306 #define ALDPS_SPDWN_RATIO 0x0f87 307 308 /* PLA_MAC_PWR_CTRL2 */ 309 #define EEE_SPDWN_RATIO 0x8007 310 #define MAC_CLK_SPDWN_EN BIT(15) 311 312 /* PLA_MAC_PWR_CTRL3 */ 313 #define PKT_AVAIL_SPDWN_EN 0x0100 314 #define SUSPEND_SPDWN_EN 0x0004 315 #define U1U2_SPDWN_EN 0x0002 316 #define L1_SPDWN_EN 0x0001 317 318 /* PLA_MAC_PWR_CTRL4 */ 319 #define PWRSAVE_SPDWN_EN 0x1000 320 #define RXDV_SPDWN_EN 0x0800 321 #define TX10MIDLE_EN 0x0100 322 #define TP100_SPDWN_EN 0x0020 323 #define TP500_SPDWN_EN 0x0010 324 #define TP1000_SPDWN_EN 0x0008 325 #define EEE_SPDWN_EN 0x0001 326 327 /* PLA_GPHY_INTR_IMR */ 328 #define GPHY_STS_MSK 0x0001 329 #define SPEED_DOWN_MSK 0x0002 330 #define SPDWN_RXDV_MSK 0x0004 331 #define SPDWN_LINKCHG_MSK 0x0008 332 333 /* PLA_PHYAR */ 334 #define PHYAR_FLAG 0x80000000 335 336 /* PLA_EEE_CR */ 337 #define EEE_RX_EN 0x0001 338 #define EEE_TX_EN 0x0002 339 340 /* PLA_BOOT_CTRL */ 341 #define AUTOLOAD_DONE 0x0002 342 343 /* PLA_SUSPEND_FLAG */ 344 #define LINK_CHG_EVENT BIT(0) 345 346 /* PLA_INDICATE_FALG */ 347 #define UPCOMING_RUNTIME_D3 BIT(0) 348 349 /* PLA_EXTRA_STATUS */ 350 #define LINK_CHANGE_FLAG BIT(8) 351 352 /* USB_USB2PHY */ 353 #define USB2PHY_SUSPEND 0x0001 354 #define USB2PHY_L1 0x0002 355 356 /* USB_SSPHYLINK2 */ 357 #define pwd_dn_scale_mask 0x3ffe 358 #define pwd_dn_scale(x) ((x) << 1) 359 360 /* USB_CSR_DUMMY1 */ 361 #define DYNAMIC_BURST 0x0001 362 363 /* USB_CSR_DUMMY2 */ 364 #define EP4_FULL_FC 0x0001 365 366 /* USB_DEV_STAT */ 367 #define STAT_SPEED_MASK 0x0006 368 #define STAT_SPEED_HIGH 0x0000 369 #define STAT_SPEED_FULL 0x0002 370 371 /* USB_LPM_CONFIG */ 372 #define LPM_U1U2_EN BIT(0) 373 374 /* USB_TX_AGG */ 375 #define TX_AGG_MAX_THRESHOLD 0x03 376 377 /* USB_RX_BUF_TH */ 378 #define RX_THR_SUPPER 0x0c350180 379 #define RX_THR_HIGH 0x7a120180 380 #define RX_THR_SLOW 0xffff0180 381 #define RX_THR_B 0x00010001 382 383 /* USB_TX_DMA */ 384 #define TEST_MODE_DISABLE 0x00000001 385 #define TX_SIZE_ADJUST1 0x00000100 386 387 /* USB_BMU_RESET */ 388 #define BMU_RESET_EP_IN 0x01 389 #define BMU_RESET_EP_OUT 0x02 390 391 /* USB_UPT_RXDMA_OWN */ 392 #define OWN_UPDATE BIT(0) 393 #define OWN_CLEAR BIT(1) 394 395 /* USB_UPS_CTRL */ 396 #define POWER_CUT 0x0100 397 398 /* USB_PM_CTRL_STATUS */ 399 #define RESUME_INDICATE 0x0001 400 401 /* USB_USB_CTRL */ 402 #define RX_AGG_DISABLE 0x0010 403 #define RX_ZERO_EN 0x0080 404 405 /* USB_U2P3_CTRL */ 406 #define U2P3_ENABLE 0x0001 407 408 /* USB_POWER_CUT */ 409 #define PWR_EN 0x0001 410 #define PHASE2_EN 0x0008 411 #define UPS_EN BIT(4) 412 #define USP_PREWAKE BIT(5) 413 414 /* USB_MISC_0 */ 415 #define PCUT_STATUS 0x0001 416 417 /* USB_RX_EARLY_TIMEOUT */ 418 #define COALESCE_SUPER 85000U 419 #define COALESCE_HIGH 250000U 420 #define COALESCE_SLOW 524280U 421 422 /* USB_WDT11_CTRL */ 423 #define TIMER11_EN 0x0001 424 425 /* USB_LPM_CTRL */ 426 /* bit 4 ~ 5: fifo empty boundary */ 427 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 428 /* bit 2 ~ 3: LMP timer */ 429 #define LPM_TIMER_MASK 0x0c 430 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 431 #define LPM_TIMER_500US 0x0c /* 500 us */ 432 #define ROK_EXIT_LPM 0x02 433 434 /* USB_AFE_CTRL2 */ 435 #define SEN_VAL_MASK 0xf800 436 #define SEN_VAL_NORMAL 0xa000 437 #define SEL_RXIDLE 0x0100 438 439 /* USB_UPS_CFG */ 440 #define SAW_CNT_1MS_MASK 0x0fff 441 442 /* USB_UPS_FLAGS */ 443 #define UPS_FLAGS_R_TUNE BIT(0) 444 #define UPS_FLAGS_EN_10M_CKDIV BIT(1) 445 #define UPS_FLAGS_250M_CKDIV BIT(2) 446 #define UPS_FLAGS_EN_ALDPS BIT(3) 447 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) 448 #define UPS_FLAGS_SPEED_MASK (0xf << 16) 449 #define ups_flags_speed(x) ((x) << 16) 450 #define UPS_FLAGS_EN_EEE BIT(20) 451 #define UPS_FLAGS_EN_500M_EEE BIT(21) 452 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22) 453 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) 454 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) 455 #define UPS_FLAGS_EN_GREEN BIT(26) 456 #define UPS_FLAGS_EN_FLOW_CTR BIT(27) 457 458 enum spd_duplex { 459 NWAY_10M_HALF = 1, 460 NWAY_10M_FULL, 461 NWAY_100M_HALF, 462 NWAY_100M_FULL, 463 NWAY_1000M_FULL, 464 FORCE_10M_HALF, 465 FORCE_10M_FULL, 466 FORCE_100M_HALF, 467 FORCE_100M_FULL, 468 }; 469 470 /* OCP_ALDPS_CONFIG */ 471 #define ENPWRSAVE 0x8000 472 #define ENPDNPS 0x0200 473 #define LINKENA 0x0100 474 #define DIS_SDSAVE 0x0010 475 476 /* OCP_PHY_STATUS */ 477 #define PHY_STAT_MASK 0x0007 478 #define PHY_STAT_EXT_INIT 2 479 #define PHY_STAT_LAN_ON 3 480 #define PHY_STAT_PWRDN 5 481 482 /* OCP_NCTL_CFG */ 483 #define PGA_RETURN_EN BIT(1) 484 485 /* OCP_POWER_CFG */ 486 #define EEE_CLKDIV_EN 0x8000 487 #define EN_ALDPS 0x0004 488 #define EN_10M_PLLOFF 0x0001 489 490 /* OCP_EEE_CONFIG1 */ 491 #define RG_TXLPI_MSK_HFDUP 0x8000 492 #define RG_MATCLR_EN 0x4000 493 #define EEE_10_CAP 0x2000 494 #define EEE_NWAY_EN 0x1000 495 #define TX_QUIET_EN 0x0200 496 #define RX_QUIET_EN 0x0100 497 #define sd_rise_time_mask 0x0070 498 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 499 #define RG_RXLPI_MSK_HFDUP 0x0008 500 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 501 502 /* OCP_EEE_CONFIG2 */ 503 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 504 #define RG_DACQUIET_EN 0x0400 505 #define RG_LDVQUIET_EN 0x0200 506 #define RG_CKRSEL 0x0020 507 #define RG_EEEPRG_EN 0x0010 508 509 /* OCP_EEE_CONFIG3 */ 510 #define fast_snr_mask 0xff80 511 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 512 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 513 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 514 515 /* OCP_EEE_AR */ 516 /* bit[15:14] function */ 517 #define FUN_ADDR 0x0000 518 #define FUN_DATA 0x4000 519 /* bit[4:0] device addr */ 520 521 /* OCP_EEE_CFG */ 522 #define CTAP_SHORT_EN 0x0040 523 #define EEE10_EN 0x0010 524 525 /* OCP_DOWN_SPEED */ 526 #define EN_EEE_CMODE BIT(14) 527 #define EN_EEE_1000 BIT(13) 528 #define EN_EEE_100 BIT(12) 529 #define EN_10M_CLKDIV BIT(11) 530 #define EN_10M_BGOFF 0x0080 531 532 /* OCP_PHY_STATE */ 533 #define TXDIS_STATE 0x01 534 #define ABD_STATE 0x02 535 536 /* OCP_PHY_PATCH_STAT */ 537 #define PATCH_READY BIT(6) 538 539 /* OCP_PHY_PATCH_CMD */ 540 #define PATCH_REQUEST BIT(4) 541 542 /* OCP_ADC_CFG */ 543 #define CKADSEL_L 0x0100 544 #define ADC_EN 0x0080 545 #define EN_EMI_L 0x0040 546 547 /* OCP_SYSCLK_CFG */ 548 #define clk_div_expo(x) (min(x, 5) << 8) 549 550 /* SRAM_GREEN_CFG */ 551 #define GREEN_ETH_EN BIT(15) 552 #define R_TUNE_EN BIT(11) 553 554 /* SRAM_LPF_CFG */ 555 #define LPF_AUTO_TUNE 0x8000 556 557 /* SRAM_10M_AMP1 */ 558 #define GDAC_IB_UPALL 0x0008 559 560 /* SRAM_10M_AMP2 */ 561 #define AMP_DN 0x0200 562 563 /* SRAM_IMPEDANCE */ 564 #define RX_DRIVING_MASK 0x6000 565 566 /* MAC PASSTHRU */ 567 #define AD_MASK 0xfee0 568 #define BND_MASK 0x0004 569 #define BD_MASK 0x0001 570 #define EFUSE 0xcfdb 571 #define PASS_THRU_MASK 0x1 572 573 enum rtl_register_content { 574 _1000bps = 0x10, 575 _100bps = 0x08, 576 _10bps = 0x04, 577 LINK_STATUS = 0x02, 578 FULL_DUP = 0x01, 579 }; 580 581 #define RTL8152_MAX_TX 4 582 #define RTL8152_MAX_RX 10 583 #define INTBUFSIZE 2 584 #define TX_ALIGN 4 585 #define RX_ALIGN 8 586 587 #define RTL8152_RX_MAX_PENDING 4096 588 #define RTL8152_RXFG_HEADSZ 256 589 590 #define INTR_LINK 0x0004 591 592 #define RTL8152_REQT_READ 0xc0 593 #define RTL8152_REQT_WRITE 0x40 594 #define RTL8152_REQ_GET_REGS 0x05 595 #define RTL8152_REQ_SET_REGS 0x05 596 597 #define BYTE_EN_DWORD 0xff 598 #define BYTE_EN_WORD 0x33 599 #define BYTE_EN_BYTE 0x11 600 #define BYTE_EN_SIX_BYTES 0x3f 601 #define BYTE_EN_START_MASK 0x0f 602 #define BYTE_EN_END_MASK 0xf0 603 604 #define RTL8153_MAX_PACKET 9216 /* 9K */ 605 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \ 606 ETH_FCS_LEN) 607 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 608 #define RTL8153_RMS RTL8153_MAX_PACKET 609 #define RTL8152_TX_TIMEOUT (5 * HZ) 610 #define RTL8152_NAPI_WEIGHT 64 611 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \ 612 sizeof(struct rx_desc) + RX_ALIGN) 613 614 /* rtl8152 flags */ 615 enum rtl8152_flags { 616 RTL8152_UNPLUG = 0, 617 RTL8152_SET_RX_MODE, 618 WORK_ENABLE, 619 RTL8152_LINK_CHG, 620 SELECTIVE_SUSPEND, 621 PHY_RESET, 622 SCHEDULE_TASKLET, 623 GREEN_ETHERNET, 624 DELL_TB_RX_AGG_BUG, 625 }; 626 627 /* Define these values to match your device */ 628 #define VENDOR_ID_REALTEK 0x0bda 629 #define VENDOR_ID_MICROSOFT 0x045e 630 #define VENDOR_ID_SAMSUNG 0x04e8 631 #define VENDOR_ID_LENOVO 0x17ef 632 #define VENDOR_ID_LINKSYS 0x13b1 633 #define VENDOR_ID_NVIDIA 0x0955 634 #define VENDOR_ID_TPLINK 0x2357 635 636 #define MCU_TYPE_PLA 0x0100 637 #define MCU_TYPE_USB 0x0000 638 639 struct tally_counter { 640 __le64 tx_packets; 641 __le64 rx_packets; 642 __le64 tx_errors; 643 __le32 rx_errors; 644 __le16 rx_missed; 645 __le16 align_errors; 646 __le32 tx_one_collision; 647 __le32 tx_multi_collision; 648 __le64 rx_unicast; 649 __le64 rx_broadcast; 650 __le32 rx_multicast; 651 __le16 tx_aborted; 652 __le16 tx_underrun; 653 }; 654 655 struct rx_desc { 656 __le32 opts1; 657 #define RX_LEN_MASK 0x7fff 658 659 __le32 opts2; 660 #define RD_UDP_CS BIT(23) 661 #define RD_TCP_CS BIT(22) 662 #define RD_IPV6_CS BIT(20) 663 #define RD_IPV4_CS BIT(19) 664 665 __le32 opts3; 666 #define IPF BIT(23) /* IP checksum fail */ 667 #define UDPF BIT(22) /* UDP checksum fail */ 668 #define TCPF BIT(21) /* TCP checksum fail */ 669 #define RX_VLAN_TAG BIT(16) 670 671 __le32 opts4; 672 __le32 opts5; 673 __le32 opts6; 674 }; 675 676 struct tx_desc { 677 __le32 opts1; 678 #define TX_FS BIT(31) /* First segment of a packet */ 679 #define TX_LS BIT(30) /* Final segment of a packet */ 680 #define GTSENDV4 BIT(28) 681 #define GTSENDV6 BIT(27) 682 #define GTTCPHO_SHIFT 18 683 #define GTTCPHO_MAX 0x7fU 684 #define TX_LEN_MAX 0x3ffffU 685 686 __le32 opts2; 687 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 688 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 689 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 690 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 691 #define MSS_SHIFT 17 692 #define MSS_MAX 0x7ffU 693 #define TCPHO_SHIFT 17 694 #define TCPHO_MAX 0x7ffU 695 #define TX_VLAN_TAG BIT(16) 696 }; 697 698 struct r8152; 699 700 struct rx_agg { 701 struct list_head list, info_list; 702 struct urb *urb; 703 struct r8152 *context; 704 struct page *page; 705 void *buffer; 706 }; 707 708 struct tx_agg { 709 struct list_head list; 710 struct urb *urb; 711 struct r8152 *context; 712 void *buffer; 713 void *head; 714 u32 skb_num; 715 u32 skb_len; 716 }; 717 718 struct r8152 { 719 unsigned long flags; 720 struct usb_device *udev; 721 struct napi_struct napi; 722 struct usb_interface *intf; 723 struct net_device *netdev; 724 struct urb *intr_urb; 725 struct tx_agg tx_info[RTL8152_MAX_TX]; 726 struct list_head rx_info, rx_used; 727 struct list_head rx_done, tx_free; 728 struct sk_buff_head tx_queue, rx_queue; 729 spinlock_t rx_lock, tx_lock; 730 struct delayed_work schedule, hw_phy_work; 731 struct mii_if_info mii; 732 struct mutex control; /* use for hw setting */ 733 #ifdef CONFIG_PM_SLEEP 734 struct notifier_block pm_notifier; 735 #endif 736 struct tasklet_struct tx_tl; 737 738 struct rtl_ops { 739 void (*init)(struct r8152 *); 740 int (*enable)(struct r8152 *); 741 void (*disable)(struct r8152 *); 742 void (*up)(struct r8152 *); 743 void (*down)(struct r8152 *); 744 void (*unload)(struct r8152 *); 745 int (*eee_get)(struct r8152 *, struct ethtool_eee *); 746 int (*eee_set)(struct r8152 *, struct ethtool_eee *); 747 bool (*in_nway)(struct r8152 *); 748 void (*hw_phy_cfg)(struct r8152 *); 749 void (*autosuspend_en)(struct r8152 *tp, bool enable); 750 } rtl_ops; 751 752 atomic_t rx_count; 753 754 bool eee_en; 755 int intr_interval; 756 u32 saved_wolopts; 757 u32 msg_enable; 758 u32 tx_qlen; 759 u32 coalesce; 760 u32 rx_buf_sz; 761 u32 rx_copybreak; 762 u32 rx_pending; 763 764 u16 ocp_base; 765 u16 speed; 766 u16 eee_adv; 767 u8 *intr_buff; 768 u8 version; 769 u8 duplex; 770 u8 autoneg; 771 }; 772 773 enum rtl_version { 774 RTL_VER_UNKNOWN = 0, 775 RTL_VER_01, 776 RTL_VER_02, 777 RTL_VER_03, 778 RTL_VER_04, 779 RTL_VER_05, 780 RTL_VER_06, 781 RTL_VER_07, 782 RTL_VER_08, 783 RTL_VER_09, 784 RTL_VER_MAX 785 }; 786 787 enum tx_csum_stat { 788 TX_CSUM_SUCCESS = 0, 789 TX_CSUM_TSO, 790 TX_CSUM_NONE 791 }; 792 793 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 794 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 795 */ 796 static const int multicast_filter_limit = 32; 797 static unsigned int agg_buf_sz = 16384; 798 799 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ 800 VLAN_ETH_HLEN - ETH_FCS_LEN) 801 802 static 803 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 804 { 805 int ret; 806 void *tmp; 807 808 tmp = kmalloc(size, GFP_KERNEL); 809 if (!tmp) 810 return -ENOMEM; 811 812 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 813 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 814 value, index, tmp, size, 500); 815 if (ret < 0) 816 memset(data, 0xff, size); 817 else 818 memcpy(data, tmp, size); 819 820 kfree(tmp); 821 822 return ret; 823 } 824 825 static 826 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 827 { 828 int ret; 829 void *tmp; 830 831 tmp = kmemdup(data, size, GFP_KERNEL); 832 if (!tmp) 833 return -ENOMEM; 834 835 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 836 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 837 value, index, tmp, size, 500); 838 839 kfree(tmp); 840 841 return ret; 842 } 843 844 static void rtl_set_unplug(struct r8152 *tp) 845 { 846 if (tp->udev->state == USB_STATE_NOTATTACHED) { 847 set_bit(RTL8152_UNPLUG, &tp->flags); 848 smp_mb__after_atomic(); 849 } 850 } 851 852 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 853 void *data, u16 type) 854 { 855 u16 limit = 64; 856 int ret = 0; 857 858 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 859 return -ENODEV; 860 861 /* both size and indix must be 4 bytes align */ 862 if ((size & 3) || !size || (index & 3) || !data) 863 return -EPERM; 864 865 if ((u32)index + (u32)size > 0xffff) 866 return -EPERM; 867 868 while (size) { 869 if (size > limit) { 870 ret = get_registers(tp, index, type, limit, data); 871 if (ret < 0) 872 break; 873 874 index += limit; 875 data += limit; 876 size -= limit; 877 } else { 878 ret = get_registers(tp, index, type, size, data); 879 if (ret < 0) 880 break; 881 882 index += size; 883 data += size; 884 size = 0; 885 break; 886 } 887 } 888 889 if (ret == -ENODEV) 890 rtl_set_unplug(tp); 891 892 return ret; 893 } 894 895 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 896 u16 size, void *data, u16 type) 897 { 898 int ret; 899 u16 byteen_start, byteen_end, byen; 900 u16 limit = 512; 901 902 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 903 return -ENODEV; 904 905 /* both size and indix must be 4 bytes align */ 906 if ((size & 3) || !size || (index & 3) || !data) 907 return -EPERM; 908 909 if ((u32)index + (u32)size > 0xffff) 910 return -EPERM; 911 912 byteen_start = byteen & BYTE_EN_START_MASK; 913 byteen_end = byteen & BYTE_EN_END_MASK; 914 915 byen = byteen_start | (byteen_start << 4); 916 ret = set_registers(tp, index, type | byen, 4, data); 917 if (ret < 0) 918 goto error1; 919 920 index += 4; 921 data += 4; 922 size -= 4; 923 924 if (size) { 925 size -= 4; 926 927 while (size) { 928 if (size > limit) { 929 ret = set_registers(tp, index, 930 type | BYTE_EN_DWORD, 931 limit, data); 932 if (ret < 0) 933 goto error1; 934 935 index += limit; 936 data += limit; 937 size -= limit; 938 } else { 939 ret = set_registers(tp, index, 940 type | BYTE_EN_DWORD, 941 size, data); 942 if (ret < 0) 943 goto error1; 944 945 index += size; 946 data += size; 947 size = 0; 948 break; 949 } 950 } 951 952 byen = byteen_end | (byteen_end >> 4); 953 ret = set_registers(tp, index, type | byen, 4, data); 954 if (ret < 0) 955 goto error1; 956 } 957 958 error1: 959 if (ret == -ENODEV) 960 rtl_set_unplug(tp); 961 962 return ret; 963 } 964 965 static inline 966 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 967 { 968 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 969 } 970 971 static inline 972 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 973 { 974 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 975 } 976 977 static inline 978 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 979 { 980 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 981 } 982 983 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 984 { 985 __le32 data; 986 987 generic_ocp_read(tp, index, sizeof(data), &data, type); 988 989 return __le32_to_cpu(data); 990 } 991 992 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 993 { 994 __le32 tmp = __cpu_to_le32(data); 995 996 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 997 } 998 999 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 1000 { 1001 u32 data; 1002 __le32 tmp; 1003 u16 byen = BYTE_EN_WORD; 1004 u8 shift = index & 2; 1005 1006 index &= ~3; 1007 byen <<= shift; 1008 1009 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen); 1010 1011 data = __le32_to_cpu(tmp); 1012 data >>= (shift * 8); 1013 data &= 0xffff; 1014 1015 return (u16)data; 1016 } 1017 1018 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 1019 { 1020 u32 mask = 0xffff; 1021 __le32 tmp; 1022 u16 byen = BYTE_EN_WORD; 1023 u8 shift = index & 2; 1024 1025 data &= mask; 1026 1027 if (index & 2) { 1028 byen <<= shift; 1029 mask <<= (shift * 8); 1030 data <<= (shift * 8); 1031 index &= ~3; 1032 } 1033 1034 tmp = __cpu_to_le32(data); 1035 1036 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1037 } 1038 1039 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 1040 { 1041 u32 data; 1042 __le32 tmp; 1043 u8 shift = index & 3; 1044 1045 index &= ~3; 1046 1047 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 1048 1049 data = __le32_to_cpu(tmp); 1050 data >>= (shift * 8); 1051 data &= 0xff; 1052 1053 return (u8)data; 1054 } 1055 1056 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 1057 { 1058 u32 mask = 0xff; 1059 __le32 tmp; 1060 u16 byen = BYTE_EN_BYTE; 1061 u8 shift = index & 3; 1062 1063 data &= mask; 1064 1065 if (index & 3) { 1066 byen <<= shift; 1067 mask <<= (shift * 8); 1068 data <<= (shift * 8); 1069 index &= ~3; 1070 } 1071 1072 tmp = __cpu_to_le32(data); 1073 1074 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1075 } 1076 1077 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 1078 { 1079 u16 ocp_base, ocp_index; 1080 1081 ocp_base = addr & 0xf000; 1082 if (ocp_base != tp->ocp_base) { 1083 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1084 tp->ocp_base = ocp_base; 1085 } 1086 1087 ocp_index = (addr & 0x0fff) | 0xb000; 1088 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 1089 } 1090 1091 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 1092 { 1093 u16 ocp_base, ocp_index; 1094 1095 ocp_base = addr & 0xf000; 1096 if (ocp_base != tp->ocp_base) { 1097 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1098 tp->ocp_base = ocp_base; 1099 } 1100 1101 ocp_index = (addr & 0x0fff) | 0xb000; 1102 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 1103 } 1104 1105 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 1106 { 1107 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 1108 } 1109 1110 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 1111 { 1112 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 1113 } 1114 1115 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 1116 { 1117 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1118 ocp_reg_write(tp, OCP_SRAM_DATA, data); 1119 } 1120 1121 static u16 sram_read(struct r8152 *tp, u16 addr) 1122 { 1123 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1124 return ocp_reg_read(tp, OCP_SRAM_DATA); 1125 } 1126 1127 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 1128 { 1129 struct r8152 *tp = netdev_priv(netdev); 1130 int ret; 1131 1132 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1133 return -ENODEV; 1134 1135 if (phy_id != R8152_PHY_ID) 1136 return -EINVAL; 1137 1138 ret = r8152_mdio_read(tp, reg); 1139 1140 return ret; 1141 } 1142 1143 static 1144 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 1145 { 1146 struct r8152 *tp = netdev_priv(netdev); 1147 1148 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1149 return; 1150 1151 if (phy_id != R8152_PHY_ID) 1152 return; 1153 1154 r8152_mdio_write(tp, reg, val); 1155 } 1156 1157 static int 1158 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 1159 1160 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1161 { 1162 struct r8152 *tp = netdev_priv(netdev); 1163 struct sockaddr *addr = p; 1164 int ret = -EADDRNOTAVAIL; 1165 1166 if (!is_valid_ether_addr(addr->sa_data)) 1167 goto out1; 1168 1169 ret = usb_autopm_get_interface(tp->intf); 1170 if (ret < 0) 1171 goto out1; 1172 1173 mutex_lock(&tp->control); 1174 1175 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1176 1177 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1178 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1179 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1180 1181 mutex_unlock(&tp->control); 1182 1183 usb_autopm_put_interface(tp->intf); 1184 out1: 1185 return ret; 1186 } 1187 1188 /* Devices containing proper chips can support a persistent 1189 * host system provided MAC address. 1190 * Examples of this are Dell TB15 and Dell WD15 docks 1191 */ 1192 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) 1193 { 1194 acpi_status status; 1195 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1196 union acpi_object *obj; 1197 int ret = -EINVAL; 1198 u32 ocp_data; 1199 unsigned char buf[6]; 1200 1201 /* test for -AD variant of RTL8153 */ 1202 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 1203 if ((ocp_data & AD_MASK) == 0x1000) { 1204 /* test for MAC address pass-through bit */ 1205 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); 1206 if ((ocp_data & PASS_THRU_MASK) != 1) { 1207 netif_dbg(tp, probe, tp->netdev, 1208 "No efuse for RTL8153-AD MAC pass through\n"); 1209 return -ENODEV; 1210 } 1211 } else { 1212 /* test for RTL8153-BND and RTL8153-BD */ 1213 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); 1214 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) { 1215 netif_dbg(tp, probe, tp->netdev, 1216 "Invalid variant for MAC pass through\n"); 1217 return -ENODEV; 1218 } 1219 } 1220 1221 /* returns _AUXMAC_#AABBCCDDEEFF# */ 1222 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer); 1223 obj = (union acpi_object *)buffer.pointer; 1224 if (!ACPI_SUCCESS(status)) 1225 return -ENODEV; 1226 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) { 1227 netif_warn(tp, probe, tp->netdev, 1228 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", 1229 obj->type, obj->string.length); 1230 goto amacout; 1231 } 1232 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || 1233 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { 1234 netif_warn(tp, probe, tp->netdev, 1235 "Invalid header when reading pass-thru MAC addr\n"); 1236 goto amacout; 1237 } 1238 ret = hex2bin(buf, obj->string.pointer + 9, 6); 1239 if (!(ret == 0 && is_valid_ether_addr(buf))) { 1240 netif_warn(tp, probe, tp->netdev, 1241 "Invalid MAC for pass-thru MAC addr: %d, %pM\n", 1242 ret, buf); 1243 ret = -EINVAL; 1244 goto amacout; 1245 } 1246 memcpy(sa->sa_data, buf, 6); 1247 netif_info(tp, probe, tp->netdev, 1248 "Using pass-thru MAC addr %pM\n", sa->sa_data); 1249 1250 amacout: 1251 kfree(obj); 1252 return ret; 1253 } 1254 1255 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa) 1256 { 1257 struct net_device *dev = tp->netdev; 1258 int ret; 1259 1260 sa->sa_family = dev->type; 1261 1262 if (tp->version == RTL_VER_01) { 1263 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data); 1264 } else { 1265 /* if device doesn't support MAC pass through this will 1266 * be expected to be non-zero 1267 */ 1268 ret = vendor_mac_passthru_addr_read(tp, sa); 1269 if (ret < 0) 1270 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa->sa_data); 1271 } 1272 1273 if (ret < 0) { 1274 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1275 } else if (!is_valid_ether_addr(sa->sa_data)) { 1276 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1277 sa->sa_data); 1278 eth_hw_addr_random(dev); 1279 ether_addr_copy(sa->sa_data, dev->dev_addr); 1280 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1281 sa->sa_data); 1282 return 0; 1283 } 1284 1285 return ret; 1286 } 1287 1288 static int set_ethernet_addr(struct r8152 *tp) 1289 { 1290 struct net_device *dev = tp->netdev; 1291 struct sockaddr sa; 1292 int ret; 1293 1294 ret = determine_ethernet_addr(tp, &sa); 1295 if (ret < 0) 1296 return ret; 1297 1298 if (tp->version == RTL_VER_01) 1299 ether_addr_copy(dev->dev_addr, sa.sa_data); 1300 else 1301 ret = rtl8152_set_mac_address(dev, &sa); 1302 1303 return ret; 1304 } 1305 1306 static void read_bulk_callback(struct urb *urb) 1307 { 1308 struct net_device *netdev; 1309 int status = urb->status; 1310 struct rx_agg *agg; 1311 struct r8152 *tp; 1312 unsigned long flags; 1313 1314 agg = urb->context; 1315 if (!agg) 1316 return; 1317 1318 tp = agg->context; 1319 if (!tp) 1320 return; 1321 1322 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1323 return; 1324 1325 if (!test_bit(WORK_ENABLE, &tp->flags)) 1326 return; 1327 1328 netdev = tp->netdev; 1329 1330 /* When link down, the driver would cancel all bulks. */ 1331 /* This avoid the re-submitting bulk */ 1332 if (!netif_carrier_ok(netdev)) 1333 return; 1334 1335 usb_mark_last_busy(tp->udev); 1336 1337 switch (status) { 1338 case 0: 1339 if (urb->actual_length < ETH_ZLEN) 1340 break; 1341 1342 spin_lock_irqsave(&tp->rx_lock, flags); 1343 list_add_tail(&agg->list, &tp->rx_done); 1344 spin_unlock_irqrestore(&tp->rx_lock, flags); 1345 napi_schedule(&tp->napi); 1346 return; 1347 case -ESHUTDOWN: 1348 rtl_set_unplug(tp); 1349 netif_device_detach(tp->netdev); 1350 return; 1351 case -ENOENT: 1352 return; /* the urb is in unlink state */ 1353 case -ETIME: 1354 if (net_ratelimit()) 1355 netdev_warn(netdev, "maybe reset is needed?\n"); 1356 break; 1357 default: 1358 if (net_ratelimit()) 1359 netdev_warn(netdev, "Rx status %d\n", status); 1360 break; 1361 } 1362 1363 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1364 } 1365 1366 static void write_bulk_callback(struct urb *urb) 1367 { 1368 struct net_device_stats *stats; 1369 struct net_device *netdev; 1370 struct tx_agg *agg; 1371 struct r8152 *tp; 1372 unsigned long flags; 1373 int status = urb->status; 1374 1375 agg = urb->context; 1376 if (!agg) 1377 return; 1378 1379 tp = agg->context; 1380 if (!tp) 1381 return; 1382 1383 netdev = tp->netdev; 1384 stats = &netdev->stats; 1385 if (status) { 1386 if (net_ratelimit()) 1387 netdev_warn(netdev, "Tx status %d\n", status); 1388 stats->tx_errors += agg->skb_num; 1389 } else { 1390 stats->tx_packets += agg->skb_num; 1391 stats->tx_bytes += agg->skb_len; 1392 } 1393 1394 spin_lock_irqsave(&tp->tx_lock, flags); 1395 list_add_tail(&agg->list, &tp->tx_free); 1396 spin_unlock_irqrestore(&tp->tx_lock, flags); 1397 1398 usb_autopm_put_interface_async(tp->intf); 1399 1400 if (!netif_carrier_ok(netdev)) 1401 return; 1402 1403 if (!test_bit(WORK_ENABLE, &tp->flags)) 1404 return; 1405 1406 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1407 return; 1408 1409 if (!skb_queue_empty(&tp->tx_queue)) 1410 tasklet_schedule(&tp->tx_tl); 1411 } 1412 1413 static void intr_callback(struct urb *urb) 1414 { 1415 struct r8152 *tp; 1416 __le16 *d; 1417 int status = urb->status; 1418 int res; 1419 1420 tp = urb->context; 1421 if (!tp) 1422 return; 1423 1424 if (!test_bit(WORK_ENABLE, &tp->flags)) 1425 return; 1426 1427 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1428 return; 1429 1430 switch (status) { 1431 case 0: /* success */ 1432 break; 1433 case -ECONNRESET: /* unlink */ 1434 case -ESHUTDOWN: 1435 netif_device_detach(tp->netdev); 1436 /* fall through */ 1437 case -ENOENT: 1438 case -EPROTO: 1439 netif_info(tp, intr, tp->netdev, 1440 "Stop submitting intr, status %d\n", status); 1441 return; 1442 case -EOVERFLOW: 1443 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1444 goto resubmit; 1445 /* -EPIPE: should clear the halt */ 1446 default: 1447 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1448 goto resubmit; 1449 } 1450 1451 d = urb->transfer_buffer; 1452 if (INTR_LINK & __le16_to_cpu(d[0])) { 1453 if (!netif_carrier_ok(tp->netdev)) { 1454 set_bit(RTL8152_LINK_CHG, &tp->flags); 1455 schedule_delayed_work(&tp->schedule, 0); 1456 } 1457 } else { 1458 if (netif_carrier_ok(tp->netdev)) { 1459 netif_stop_queue(tp->netdev); 1460 set_bit(RTL8152_LINK_CHG, &tp->flags); 1461 schedule_delayed_work(&tp->schedule, 0); 1462 } 1463 } 1464 1465 resubmit: 1466 res = usb_submit_urb(urb, GFP_ATOMIC); 1467 if (res == -ENODEV) { 1468 rtl_set_unplug(tp); 1469 netif_device_detach(tp->netdev); 1470 } else if (res) { 1471 netif_err(tp, intr, tp->netdev, 1472 "can't resubmit intr, status %d\n", res); 1473 } 1474 } 1475 1476 static inline void *rx_agg_align(void *data) 1477 { 1478 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1479 } 1480 1481 static inline void *tx_agg_align(void *data) 1482 { 1483 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1484 } 1485 1486 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg) 1487 { 1488 list_del(&agg->info_list); 1489 1490 usb_free_urb(agg->urb); 1491 put_page(agg->page); 1492 kfree(agg); 1493 1494 atomic_dec(&tp->rx_count); 1495 } 1496 1497 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags) 1498 { 1499 struct net_device *netdev = tp->netdev; 1500 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1501 unsigned int order = get_order(tp->rx_buf_sz); 1502 struct rx_agg *rx_agg; 1503 unsigned long flags; 1504 1505 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node); 1506 if (!rx_agg) 1507 return NULL; 1508 1509 rx_agg->page = alloc_pages(mflags | __GFP_COMP, order); 1510 if (!rx_agg->page) 1511 goto free_rx; 1512 1513 rx_agg->buffer = page_address(rx_agg->page); 1514 1515 rx_agg->urb = usb_alloc_urb(0, mflags); 1516 if (!rx_agg->urb) 1517 goto free_buf; 1518 1519 rx_agg->context = tp; 1520 1521 INIT_LIST_HEAD(&rx_agg->list); 1522 INIT_LIST_HEAD(&rx_agg->info_list); 1523 spin_lock_irqsave(&tp->rx_lock, flags); 1524 list_add_tail(&rx_agg->info_list, &tp->rx_info); 1525 spin_unlock_irqrestore(&tp->rx_lock, flags); 1526 1527 atomic_inc(&tp->rx_count); 1528 1529 return rx_agg; 1530 1531 free_buf: 1532 __free_pages(rx_agg->page, order); 1533 free_rx: 1534 kfree(rx_agg); 1535 return NULL; 1536 } 1537 1538 static void free_all_mem(struct r8152 *tp) 1539 { 1540 struct rx_agg *agg, *agg_next; 1541 unsigned long flags; 1542 int i; 1543 1544 spin_lock_irqsave(&tp->rx_lock, flags); 1545 1546 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list) 1547 free_rx_agg(tp, agg); 1548 1549 spin_unlock_irqrestore(&tp->rx_lock, flags); 1550 1551 WARN_ON(atomic_read(&tp->rx_count)); 1552 1553 for (i = 0; i < RTL8152_MAX_TX; i++) { 1554 usb_free_urb(tp->tx_info[i].urb); 1555 tp->tx_info[i].urb = NULL; 1556 1557 kfree(tp->tx_info[i].buffer); 1558 tp->tx_info[i].buffer = NULL; 1559 tp->tx_info[i].head = NULL; 1560 } 1561 1562 usb_free_urb(tp->intr_urb); 1563 tp->intr_urb = NULL; 1564 1565 kfree(tp->intr_buff); 1566 tp->intr_buff = NULL; 1567 } 1568 1569 static int alloc_all_mem(struct r8152 *tp) 1570 { 1571 struct net_device *netdev = tp->netdev; 1572 struct usb_interface *intf = tp->intf; 1573 struct usb_host_interface *alt = intf->cur_altsetting; 1574 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1575 int node, i; 1576 1577 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1578 1579 spin_lock_init(&tp->rx_lock); 1580 spin_lock_init(&tp->tx_lock); 1581 INIT_LIST_HEAD(&tp->rx_info); 1582 INIT_LIST_HEAD(&tp->tx_free); 1583 INIT_LIST_HEAD(&tp->rx_done); 1584 skb_queue_head_init(&tp->tx_queue); 1585 skb_queue_head_init(&tp->rx_queue); 1586 atomic_set(&tp->rx_count, 0); 1587 1588 for (i = 0; i < RTL8152_MAX_RX; i++) { 1589 if (!alloc_rx_agg(tp, GFP_KERNEL)) 1590 goto err1; 1591 } 1592 1593 for (i = 0; i < RTL8152_MAX_TX; i++) { 1594 struct urb *urb; 1595 u8 *buf; 1596 1597 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1598 if (!buf) 1599 goto err1; 1600 1601 if (buf != tx_agg_align(buf)) { 1602 kfree(buf); 1603 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 1604 node); 1605 if (!buf) 1606 goto err1; 1607 } 1608 1609 urb = usb_alloc_urb(0, GFP_KERNEL); 1610 if (!urb) { 1611 kfree(buf); 1612 goto err1; 1613 } 1614 1615 INIT_LIST_HEAD(&tp->tx_info[i].list); 1616 tp->tx_info[i].context = tp; 1617 tp->tx_info[i].urb = urb; 1618 tp->tx_info[i].buffer = buf; 1619 tp->tx_info[i].head = tx_agg_align(buf); 1620 1621 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1622 } 1623 1624 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1625 if (!tp->intr_urb) 1626 goto err1; 1627 1628 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1629 if (!tp->intr_buff) 1630 goto err1; 1631 1632 tp->intr_interval = (int)ep_intr->desc.bInterval; 1633 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1634 tp->intr_buff, INTBUFSIZE, intr_callback, 1635 tp, tp->intr_interval); 1636 1637 return 0; 1638 1639 err1: 1640 free_all_mem(tp); 1641 return -ENOMEM; 1642 } 1643 1644 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1645 { 1646 struct tx_agg *agg = NULL; 1647 unsigned long flags; 1648 1649 if (list_empty(&tp->tx_free)) 1650 return NULL; 1651 1652 spin_lock_irqsave(&tp->tx_lock, flags); 1653 if (!list_empty(&tp->tx_free)) { 1654 struct list_head *cursor; 1655 1656 cursor = tp->tx_free.next; 1657 list_del_init(cursor); 1658 agg = list_entry(cursor, struct tx_agg, list); 1659 } 1660 spin_unlock_irqrestore(&tp->tx_lock, flags); 1661 1662 return agg; 1663 } 1664 1665 /* r8152_csum_workaround() 1666 * The hw limites the value the transport offset. When the offset is out of the 1667 * range, calculate the checksum by sw. 1668 */ 1669 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1670 struct sk_buff_head *list) 1671 { 1672 if (skb_shinfo(skb)->gso_size) { 1673 netdev_features_t features = tp->netdev->features; 1674 struct sk_buff_head seg_list; 1675 struct sk_buff *segs, *nskb; 1676 1677 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 1678 segs = skb_gso_segment(skb, features); 1679 if (IS_ERR(segs) || !segs) 1680 goto drop; 1681 1682 __skb_queue_head_init(&seg_list); 1683 1684 do { 1685 nskb = segs; 1686 segs = segs->next; 1687 nskb->next = NULL; 1688 __skb_queue_tail(&seg_list, nskb); 1689 } while (segs); 1690 1691 skb_queue_splice(&seg_list, list); 1692 dev_kfree_skb(skb); 1693 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1694 if (skb_checksum_help(skb) < 0) 1695 goto drop; 1696 1697 __skb_queue_head(list, skb); 1698 } else { 1699 struct net_device_stats *stats; 1700 1701 drop: 1702 stats = &tp->netdev->stats; 1703 stats->tx_dropped++; 1704 dev_kfree_skb(skb); 1705 } 1706 } 1707 1708 /* msdn_giant_send_check() 1709 * According to the document of microsoft, the TCP Pseudo Header excludes the 1710 * packet length for IPv6 TCP large packets. 1711 */ 1712 static int msdn_giant_send_check(struct sk_buff *skb) 1713 { 1714 const struct ipv6hdr *ipv6h; 1715 struct tcphdr *th; 1716 int ret; 1717 1718 ret = skb_cow_head(skb, 0); 1719 if (ret) 1720 return ret; 1721 1722 ipv6h = ipv6_hdr(skb); 1723 th = tcp_hdr(skb); 1724 1725 th->check = 0; 1726 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1727 1728 return ret; 1729 } 1730 1731 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 1732 { 1733 if (skb_vlan_tag_present(skb)) { 1734 u32 opts2; 1735 1736 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); 1737 desc->opts2 |= cpu_to_le32(opts2); 1738 } 1739 } 1740 1741 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 1742 { 1743 u32 opts2 = le32_to_cpu(desc->opts2); 1744 1745 if (opts2 & RX_VLAN_TAG) 1746 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1747 swab16(opts2 & 0xffff)); 1748 } 1749 1750 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1751 struct sk_buff *skb, u32 len, u32 transport_offset) 1752 { 1753 u32 mss = skb_shinfo(skb)->gso_size; 1754 u32 opts1, opts2 = 0; 1755 int ret = TX_CSUM_SUCCESS; 1756 1757 WARN_ON_ONCE(len > TX_LEN_MAX); 1758 1759 opts1 = len | TX_FS | TX_LS; 1760 1761 if (mss) { 1762 if (transport_offset > GTTCPHO_MAX) { 1763 netif_warn(tp, tx_err, tp->netdev, 1764 "Invalid transport offset 0x%x for TSO\n", 1765 transport_offset); 1766 ret = TX_CSUM_TSO; 1767 goto unavailable; 1768 } 1769 1770 switch (vlan_get_protocol(skb)) { 1771 case htons(ETH_P_IP): 1772 opts1 |= GTSENDV4; 1773 break; 1774 1775 case htons(ETH_P_IPV6): 1776 if (msdn_giant_send_check(skb)) { 1777 ret = TX_CSUM_TSO; 1778 goto unavailable; 1779 } 1780 opts1 |= GTSENDV6; 1781 break; 1782 1783 default: 1784 WARN_ON_ONCE(1); 1785 break; 1786 } 1787 1788 opts1 |= transport_offset << GTTCPHO_SHIFT; 1789 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1790 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1791 u8 ip_protocol; 1792 1793 if (transport_offset > TCPHO_MAX) { 1794 netif_warn(tp, tx_err, tp->netdev, 1795 "Invalid transport offset 0x%x\n", 1796 transport_offset); 1797 ret = TX_CSUM_NONE; 1798 goto unavailable; 1799 } 1800 1801 switch (vlan_get_protocol(skb)) { 1802 case htons(ETH_P_IP): 1803 opts2 |= IPV4_CS; 1804 ip_protocol = ip_hdr(skb)->protocol; 1805 break; 1806 1807 case htons(ETH_P_IPV6): 1808 opts2 |= IPV6_CS; 1809 ip_protocol = ipv6_hdr(skb)->nexthdr; 1810 break; 1811 1812 default: 1813 ip_protocol = IPPROTO_RAW; 1814 break; 1815 } 1816 1817 if (ip_protocol == IPPROTO_TCP) 1818 opts2 |= TCP_CS; 1819 else if (ip_protocol == IPPROTO_UDP) 1820 opts2 |= UDP_CS; 1821 else 1822 WARN_ON_ONCE(1); 1823 1824 opts2 |= transport_offset << TCPHO_SHIFT; 1825 } 1826 1827 desc->opts2 = cpu_to_le32(opts2); 1828 desc->opts1 = cpu_to_le32(opts1); 1829 1830 unavailable: 1831 return ret; 1832 } 1833 1834 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1835 { 1836 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1837 int remain, ret; 1838 u8 *tx_data; 1839 1840 __skb_queue_head_init(&skb_head); 1841 spin_lock(&tx_queue->lock); 1842 skb_queue_splice_init(tx_queue, &skb_head); 1843 spin_unlock(&tx_queue->lock); 1844 1845 tx_data = agg->head; 1846 agg->skb_num = 0; 1847 agg->skb_len = 0; 1848 remain = agg_buf_sz; 1849 1850 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1851 struct tx_desc *tx_desc; 1852 struct sk_buff *skb; 1853 unsigned int len; 1854 u32 offset; 1855 1856 skb = __skb_dequeue(&skb_head); 1857 if (!skb) 1858 break; 1859 1860 len = skb->len + sizeof(*tx_desc); 1861 1862 if (len > remain) { 1863 __skb_queue_head(&skb_head, skb); 1864 break; 1865 } 1866 1867 tx_data = tx_agg_align(tx_data); 1868 tx_desc = (struct tx_desc *)tx_data; 1869 1870 offset = (u32)skb_transport_offset(skb); 1871 1872 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1873 r8152_csum_workaround(tp, skb, &skb_head); 1874 continue; 1875 } 1876 1877 rtl_tx_vlan_tag(tx_desc, skb); 1878 1879 tx_data += sizeof(*tx_desc); 1880 1881 len = skb->len; 1882 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1883 struct net_device_stats *stats = &tp->netdev->stats; 1884 1885 stats->tx_dropped++; 1886 dev_kfree_skb_any(skb); 1887 tx_data -= sizeof(*tx_desc); 1888 continue; 1889 } 1890 1891 tx_data += len; 1892 agg->skb_len += len; 1893 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1; 1894 1895 dev_kfree_skb_any(skb); 1896 1897 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1898 1899 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags)) 1900 break; 1901 } 1902 1903 if (!skb_queue_empty(&skb_head)) { 1904 spin_lock(&tx_queue->lock); 1905 skb_queue_splice(&skb_head, tx_queue); 1906 spin_unlock(&tx_queue->lock); 1907 } 1908 1909 netif_tx_lock(tp->netdev); 1910 1911 if (netif_queue_stopped(tp->netdev) && 1912 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1913 netif_wake_queue(tp->netdev); 1914 1915 netif_tx_unlock(tp->netdev); 1916 1917 ret = usb_autopm_get_interface_async(tp->intf); 1918 if (ret < 0) 1919 goto out_tx_fill; 1920 1921 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1922 agg->head, (int)(tx_data - (u8 *)agg->head), 1923 (usb_complete_t)write_bulk_callback, agg); 1924 1925 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1926 if (ret < 0) 1927 usb_autopm_put_interface_async(tp->intf); 1928 1929 out_tx_fill: 1930 return ret; 1931 } 1932 1933 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1934 { 1935 u8 checksum = CHECKSUM_NONE; 1936 u32 opts2, opts3; 1937 1938 if (!(tp->netdev->features & NETIF_F_RXCSUM)) 1939 goto return_result; 1940 1941 opts2 = le32_to_cpu(rx_desc->opts2); 1942 opts3 = le32_to_cpu(rx_desc->opts3); 1943 1944 if (opts2 & RD_IPV4_CS) { 1945 if (opts3 & IPF) 1946 checksum = CHECKSUM_NONE; 1947 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1948 checksum = CHECKSUM_UNNECESSARY; 1949 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1950 checksum = CHECKSUM_UNNECESSARY; 1951 } else if (opts2 & RD_IPV6_CS) { 1952 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1953 checksum = CHECKSUM_UNNECESSARY; 1954 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1955 checksum = CHECKSUM_UNNECESSARY; 1956 } 1957 1958 return_result: 1959 return checksum; 1960 } 1961 1962 static inline bool rx_count_exceed(struct r8152 *tp) 1963 { 1964 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX; 1965 } 1966 1967 static inline int agg_offset(struct rx_agg *agg, void *addr) 1968 { 1969 return (int)(addr - agg->buffer); 1970 } 1971 1972 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags) 1973 { 1974 struct rx_agg *agg, *agg_next, *agg_free = NULL; 1975 unsigned long flags; 1976 1977 spin_lock_irqsave(&tp->rx_lock, flags); 1978 1979 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) { 1980 if (page_count(agg->page) == 1) { 1981 if (!agg_free) { 1982 list_del_init(&agg->list); 1983 agg_free = agg; 1984 continue; 1985 } 1986 if (rx_count_exceed(tp)) { 1987 list_del_init(&agg->list); 1988 free_rx_agg(tp, agg); 1989 } 1990 break; 1991 } 1992 } 1993 1994 spin_unlock_irqrestore(&tp->rx_lock, flags); 1995 1996 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending) 1997 agg_free = alloc_rx_agg(tp, mflags); 1998 1999 return agg_free; 2000 } 2001 2002 static int rx_bottom(struct r8152 *tp, int budget) 2003 { 2004 unsigned long flags; 2005 struct list_head *cursor, *next, rx_queue; 2006 int ret = 0, work_done = 0; 2007 struct napi_struct *napi = &tp->napi; 2008 2009 if (!skb_queue_empty(&tp->rx_queue)) { 2010 while (work_done < budget) { 2011 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); 2012 struct net_device *netdev = tp->netdev; 2013 struct net_device_stats *stats = &netdev->stats; 2014 unsigned int pkt_len; 2015 2016 if (!skb) 2017 break; 2018 2019 pkt_len = skb->len; 2020 napi_gro_receive(napi, skb); 2021 work_done++; 2022 stats->rx_packets++; 2023 stats->rx_bytes += pkt_len; 2024 } 2025 } 2026 2027 if (list_empty(&tp->rx_done)) 2028 goto out1; 2029 2030 INIT_LIST_HEAD(&rx_queue); 2031 spin_lock_irqsave(&tp->rx_lock, flags); 2032 list_splice_init(&tp->rx_done, &rx_queue); 2033 spin_unlock_irqrestore(&tp->rx_lock, flags); 2034 2035 list_for_each_safe(cursor, next, &rx_queue) { 2036 struct rx_desc *rx_desc; 2037 struct rx_agg *agg, *agg_free; 2038 int len_used = 0; 2039 struct urb *urb; 2040 u8 *rx_data; 2041 2042 list_del_init(cursor); 2043 2044 agg = list_entry(cursor, struct rx_agg, list); 2045 urb = agg->urb; 2046 if (urb->actual_length < ETH_ZLEN) 2047 goto submit; 2048 2049 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC); 2050 2051 rx_desc = agg->buffer; 2052 rx_data = agg->buffer; 2053 len_used += sizeof(struct rx_desc); 2054 2055 while (urb->actual_length > len_used) { 2056 struct net_device *netdev = tp->netdev; 2057 struct net_device_stats *stats = &netdev->stats; 2058 unsigned int pkt_len, rx_frag_head_sz; 2059 struct sk_buff *skb; 2060 2061 /* limite the skb numbers for rx_queue */ 2062 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000)) 2063 break; 2064 2065 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 2066 if (pkt_len < ETH_ZLEN) 2067 break; 2068 2069 len_used += pkt_len; 2070 if (urb->actual_length < len_used) 2071 break; 2072 2073 pkt_len -= ETH_FCS_LEN; 2074 rx_data += sizeof(struct rx_desc); 2075 2076 if (!agg_free || tp->rx_copybreak > pkt_len) 2077 rx_frag_head_sz = pkt_len; 2078 else 2079 rx_frag_head_sz = tp->rx_copybreak; 2080 2081 skb = napi_alloc_skb(napi, rx_frag_head_sz); 2082 if (!skb) { 2083 stats->rx_dropped++; 2084 goto find_next_rx; 2085 } 2086 2087 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 2088 memcpy(skb->data, rx_data, rx_frag_head_sz); 2089 skb_put(skb, rx_frag_head_sz); 2090 pkt_len -= rx_frag_head_sz; 2091 rx_data += rx_frag_head_sz; 2092 if (pkt_len) { 2093 skb_add_rx_frag(skb, 0, agg->page, 2094 agg_offset(agg, rx_data), 2095 pkt_len, 2096 SKB_DATA_ALIGN(pkt_len)); 2097 get_page(agg->page); 2098 } 2099 2100 skb->protocol = eth_type_trans(skb, netdev); 2101 rtl_rx_vlan_tag(rx_desc, skb); 2102 if (work_done < budget) { 2103 work_done++; 2104 stats->rx_packets++; 2105 stats->rx_bytes += skb->len; 2106 napi_gro_receive(napi, skb); 2107 } else { 2108 __skb_queue_tail(&tp->rx_queue, skb); 2109 } 2110 2111 find_next_rx: 2112 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN); 2113 rx_desc = (struct rx_desc *)rx_data; 2114 len_used = agg_offset(agg, rx_data); 2115 len_used += sizeof(struct rx_desc); 2116 } 2117 2118 WARN_ON(!agg_free && page_count(agg->page) > 1); 2119 2120 if (agg_free) { 2121 spin_lock_irqsave(&tp->rx_lock, flags); 2122 if (page_count(agg->page) == 1) { 2123 list_add(&agg_free->list, &tp->rx_used); 2124 } else { 2125 list_add_tail(&agg->list, &tp->rx_used); 2126 agg = agg_free; 2127 urb = agg->urb; 2128 } 2129 spin_unlock_irqrestore(&tp->rx_lock, flags); 2130 } 2131 2132 submit: 2133 if (!ret) { 2134 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 2135 } else { 2136 urb->actual_length = 0; 2137 list_add_tail(&agg->list, next); 2138 } 2139 } 2140 2141 if (!list_empty(&rx_queue)) { 2142 spin_lock_irqsave(&tp->rx_lock, flags); 2143 list_splice_tail(&rx_queue, &tp->rx_done); 2144 spin_unlock_irqrestore(&tp->rx_lock, flags); 2145 } 2146 2147 out1: 2148 return work_done; 2149 } 2150 2151 static void tx_bottom(struct r8152 *tp) 2152 { 2153 int res; 2154 2155 do { 2156 struct tx_agg *agg; 2157 2158 if (skb_queue_empty(&tp->tx_queue)) 2159 break; 2160 2161 agg = r8152_get_tx_agg(tp); 2162 if (!agg) 2163 break; 2164 2165 res = r8152_tx_agg_fill(tp, agg); 2166 if (res) { 2167 struct net_device *netdev = tp->netdev; 2168 2169 if (res == -ENODEV) { 2170 rtl_set_unplug(tp); 2171 netif_device_detach(netdev); 2172 } else { 2173 struct net_device_stats *stats = &netdev->stats; 2174 unsigned long flags; 2175 2176 netif_warn(tp, tx_err, netdev, 2177 "failed tx_urb %d\n", res); 2178 stats->tx_dropped += agg->skb_num; 2179 2180 spin_lock_irqsave(&tp->tx_lock, flags); 2181 list_add_tail(&agg->list, &tp->tx_free); 2182 spin_unlock_irqrestore(&tp->tx_lock, flags); 2183 } 2184 } 2185 } while (res == 0); 2186 } 2187 2188 static void bottom_half(unsigned long data) 2189 { 2190 struct r8152 *tp; 2191 2192 tp = (struct r8152 *)data; 2193 2194 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2195 return; 2196 2197 if (!test_bit(WORK_ENABLE, &tp->flags)) 2198 return; 2199 2200 /* When link down, the driver would cancel all bulks. */ 2201 /* This avoid the re-submitting bulk */ 2202 if (!netif_carrier_ok(tp->netdev)) 2203 return; 2204 2205 clear_bit(SCHEDULE_TASKLET, &tp->flags); 2206 2207 tx_bottom(tp); 2208 } 2209 2210 static int r8152_poll(struct napi_struct *napi, int budget) 2211 { 2212 struct r8152 *tp = container_of(napi, struct r8152, napi); 2213 int work_done; 2214 2215 work_done = rx_bottom(tp, budget); 2216 2217 if (work_done < budget) { 2218 if (!napi_complete_done(napi, work_done)) 2219 goto out; 2220 if (!list_empty(&tp->rx_done)) 2221 napi_schedule(napi); 2222 } 2223 2224 out: 2225 return work_done; 2226 } 2227 2228 static 2229 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 2230 { 2231 int ret; 2232 2233 /* The rx would be stopped, so skip submitting */ 2234 if (test_bit(RTL8152_UNPLUG, &tp->flags) || 2235 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) 2236 return 0; 2237 2238 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 2239 agg->buffer, tp->rx_buf_sz, 2240 (usb_complete_t)read_bulk_callback, agg); 2241 2242 ret = usb_submit_urb(agg->urb, mem_flags); 2243 if (ret == -ENODEV) { 2244 rtl_set_unplug(tp); 2245 netif_device_detach(tp->netdev); 2246 } else if (ret) { 2247 struct urb *urb = agg->urb; 2248 unsigned long flags; 2249 2250 urb->actual_length = 0; 2251 spin_lock_irqsave(&tp->rx_lock, flags); 2252 list_add_tail(&agg->list, &tp->rx_done); 2253 spin_unlock_irqrestore(&tp->rx_lock, flags); 2254 2255 netif_err(tp, rx_err, tp->netdev, 2256 "Couldn't submit rx[%p], ret = %d\n", agg, ret); 2257 2258 napi_schedule(&tp->napi); 2259 } 2260 2261 return ret; 2262 } 2263 2264 static void rtl_drop_queued_tx(struct r8152 *tp) 2265 { 2266 struct net_device_stats *stats = &tp->netdev->stats; 2267 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 2268 struct sk_buff *skb; 2269 2270 if (skb_queue_empty(tx_queue)) 2271 return; 2272 2273 __skb_queue_head_init(&skb_head); 2274 spin_lock_bh(&tx_queue->lock); 2275 skb_queue_splice_init(tx_queue, &skb_head); 2276 spin_unlock_bh(&tx_queue->lock); 2277 2278 while ((skb = __skb_dequeue(&skb_head))) { 2279 dev_kfree_skb(skb); 2280 stats->tx_dropped++; 2281 } 2282 } 2283 2284 static void rtl8152_tx_timeout(struct net_device *netdev) 2285 { 2286 struct r8152 *tp = netdev_priv(netdev); 2287 2288 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 2289 2290 usb_queue_reset_device(tp->intf); 2291 } 2292 2293 static void rtl8152_set_rx_mode(struct net_device *netdev) 2294 { 2295 struct r8152 *tp = netdev_priv(netdev); 2296 2297 if (netif_carrier_ok(netdev)) { 2298 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2299 schedule_delayed_work(&tp->schedule, 0); 2300 } 2301 } 2302 2303 static void _rtl8152_set_rx_mode(struct net_device *netdev) 2304 { 2305 struct r8152 *tp = netdev_priv(netdev); 2306 u32 mc_filter[2]; /* Multicast hash filter */ 2307 __le32 tmp[2]; 2308 u32 ocp_data; 2309 2310 netif_stop_queue(netdev); 2311 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2312 ocp_data &= ~RCR_ACPT_ALL; 2313 ocp_data |= RCR_AB | RCR_APM; 2314 2315 if (netdev->flags & IFF_PROMISC) { 2316 /* Unconditionally log net taps. */ 2317 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 2318 ocp_data |= RCR_AM | RCR_AAP; 2319 mc_filter[1] = 0xffffffff; 2320 mc_filter[0] = 0xffffffff; 2321 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 2322 (netdev->flags & IFF_ALLMULTI)) { 2323 /* Too many to filter perfectly -- accept all multicasts. */ 2324 ocp_data |= RCR_AM; 2325 mc_filter[1] = 0xffffffff; 2326 mc_filter[0] = 0xffffffff; 2327 } else { 2328 struct netdev_hw_addr *ha; 2329 2330 mc_filter[1] = 0; 2331 mc_filter[0] = 0; 2332 netdev_for_each_mc_addr(ha, netdev) { 2333 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2334 2335 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2336 ocp_data |= RCR_AM; 2337 } 2338 } 2339 2340 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 2341 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 2342 2343 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 2344 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2345 netif_wake_queue(netdev); 2346 } 2347 2348 static netdev_features_t 2349 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 2350 netdev_features_t features) 2351 { 2352 u32 mss = skb_shinfo(skb)->gso_size; 2353 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 2354 int offset = skb_transport_offset(skb); 2355 2356 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) 2357 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2358 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 2359 features &= ~NETIF_F_GSO_MASK; 2360 2361 return features; 2362 } 2363 2364 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 2365 struct net_device *netdev) 2366 { 2367 struct r8152 *tp = netdev_priv(netdev); 2368 2369 skb_tx_timestamp(skb); 2370 2371 skb_queue_tail(&tp->tx_queue, skb); 2372 2373 if (!list_empty(&tp->tx_free)) { 2374 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2375 set_bit(SCHEDULE_TASKLET, &tp->flags); 2376 schedule_delayed_work(&tp->schedule, 0); 2377 } else { 2378 usb_mark_last_busy(tp->udev); 2379 tasklet_schedule(&tp->tx_tl); 2380 } 2381 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 2382 netif_stop_queue(netdev); 2383 } 2384 2385 return NETDEV_TX_OK; 2386 } 2387 2388 static void r8152b_reset_packet_filter(struct r8152 *tp) 2389 { 2390 u32 ocp_data; 2391 2392 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 2393 ocp_data &= ~FMC_FCR_MCU_EN; 2394 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2395 ocp_data |= FMC_FCR_MCU_EN; 2396 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2397 } 2398 2399 static void rtl8152_nic_reset(struct r8152 *tp) 2400 { 2401 int i; 2402 2403 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 2404 2405 for (i = 0; i < 1000; i++) { 2406 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 2407 break; 2408 usleep_range(100, 400); 2409 } 2410 } 2411 2412 static void set_tx_qlen(struct r8152 *tp) 2413 { 2414 struct net_device *netdev = tp->netdev; 2415 2416 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN + 2417 sizeof(struct tx_desc)); 2418 } 2419 2420 static inline u8 rtl8152_get_speed(struct r8152 *tp) 2421 { 2422 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 2423 } 2424 2425 static void rtl_set_eee_plus(struct r8152 *tp) 2426 { 2427 u32 ocp_data; 2428 u8 speed; 2429 2430 speed = rtl8152_get_speed(tp); 2431 if (speed & _10bps) { 2432 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2433 ocp_data |= EEEP_CR_EEEP_TX; 2434 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2435 } else { 2436 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2437 ocp_data &= ~EEEP_CR_EEEP_TX; 2438 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2439 } 2440 } 2441 2442 static void rxdy_gated_en(struct r8152 *tp, bool enable) 2443 { 2444 u32 ocp_data; 2445 2446 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 2447 if (enable) 2448 ocp_data |= RXDY_GATED_EN; 2449 else 2450 ocp_data &= ~RXDY_GATED_EN; 2451 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 2452 } 2453 2454 static int rtl_start_rx(struct r8152 *tp) 2455 { 2456 struct rx_agg *agg, *agg_next; 2457 struct list_head tmp_list; 2458 unsigned long flags; 2459 int ret = 0, i = 0; 2460 2461 INIT_LIST_HEAD(&tmp_list); 2462 2463 spin_lock_irqsave(&tp->rx_lock, flags); 2464 2465 INIT_LIST_HEAD(&tp->rx_done); 2466 INIT_LIST_HEAD(&tp->rx_used); 2467 2468 list_splice_init(&tp->rx_info, &tmp_list); 2469 2470 spin_unlock_irqrestore(&tp->rx_lock, flags); 2471 2472 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) { 2473 INIT_LIST_HEAD(&agg->list); 2474 2475 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */ 2476 if (++i > RTL8152_MAX_RX) { 2477 spin_lock_irqsave(&tp->rx_lock, flags); 2478 list_add_tail(&agg->list, &tp->rx_used); 2479 spin_unlock_irqrestore(&tp->rx_lock, flags); 2480 } else if (unlikely(ret < 0)) { 2481 spin_lock_irqsave(&tp->rx_lock, flags); 2482 list_add_tail(&agg->list, &tp->rx_done); 2483 spin_unlock_irqrestore(&tp->rx_lock, flags); 2484 } else { 2485 ret = r8152_submit_rx(tp, agg, GFP_KERNEL); 2486 } 2487 } 2488 2489 spin_lock_irqsave(&tp->rx_lock, flags); 2490 WARN_ON(!list_empty(&tp->rx_info)); 2491 list_splice(&tmp_list, &tp->rx_info); 2492 spin_unlock_irqrestore(&tp->rx_lock, flags); 2493 2494 return ret; 2495 } 2496 2497 static int rtl_stop_rx(struct r8152 *tp) 2498 { 2499 struct rx_agg *agg, *agg_next; 2500 struct list_head tmp_list; 2501 unsigned long flags; 2502 2503 INIT_LIST_HEAD(&tmp_list); 2504 2505 /* The usb_kill_urb() couldn't be used in atomic. 2506 * Therefore, move the list of rx_info to a tmp one. 2507 * Then, list_for_each_entry_safe could be used without 2508 * spin lock. 2509 */ 2510 2511 spin_lock_irqsave(&tp->rx_lock, flags); 2512 list_splice_init(&tp->rx_info, &tmp_list); 2513 spin_unlock_irqrestore(&tp->rx_lock, flags); 2514 2515 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) { 2516 /* At least RTL8152_MAX_RX rx_agg have the page_count being 2517 * equal to 1, so the other ones could be freed safely. 2518 */ 2519 if (page_count(agg->page) > 1) 2520 free_rx_agg(tp, agg); 2521 else 2522 usb_kill_urb(agg->urb); 2523 } 2524 2525 /* Move back the list of temp to the rx_info */ 2526 spin_lock_irqsave(&tp->rx_lock, flags); 2527 WARN_ON(!list_empty(&tp->rx_info)); 2528 list_splice(&tmp_list, &tp->rx_info); 2529 spin_unlock_irqrestore(&tp->rx_lock, flags); 2530 2531 while (!skb_queue_empty(&tp->rx_queue)) 2532 dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); 2533 2534 return 0; 2535 } 2536 2537 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) 2538 { 2539 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, 2540 OWN_UPDATE | OWN_CLEAR); 2541 } 2542 2543 static int rtl_enable(struct r8152 *tp) 2544 { 2545 u32 ocp_data; 2546 2547 r8152b_reset_packet_filter(tp); 2548 2549 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2550 ocp_data |= CR_RE | CR_TE; 2551 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2552 2553 switch (tp->version) { 2554 case RTL_VER_08: 2555 case RTL_VER_09: 2556 r8153b_rx_agg_chg_indicate(tp); 2557 break; 2558 default: 2559 break; 2560 } 2561 2562 rxdy_gated_en(tp, false); 2563 2564 return 0; 2565 } 2566 2567 static int rtl8152_enable(struct r8152 *tp) 2568 { 2569 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2570 return -ENODEV; 2571 2572 set_tx_qlen(tp); 2573 rtl_set_eee_plus(tp); 2574 2575 return rtl_enable(tp); 2576 } 2577 2578 static void r8153_set_rx_early_timeout(struct r8152 *tp) 2579 { 2580 u32 ocp_data = tp->coalesce / 8; 2581 2582 switch (tp->version) { 2583 case RTL_VER_03: 2584 case RTL_VER_04: 2585 case RTL_VER_05: 2586 case RTL_VER_06: 2587 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2588 ocp_data); 2589 break; 2590 2591 case RTL_VER_08: 2592 case RTL_VER_09: 2593 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout 2594 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns. 2595 */ 2596 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2597 128 / 8); 2598 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, 2599 ocp_data); 2600 break; 2601 2602 default: 2603 break; 2604 } 2605 } 2606 2607 static void r8153_set_rx_early_size(struct r8152 *tp) 2608 { 2609 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu); 2610 2611 switch (tp->version) { 2612 case RTL_VER_03: 2613 case RTL_VER_04: 2614 case RTL_VER_05: 2615 case RTL_VER_06: 2616 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2617 ocp_data / 4); 2618 break; 2619 case RTL_VER_08: 2620 case RTL_VER_09: 2621 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2622 ocp_data / 8); 2623 break; 2624 default: 2625 WARN_ON_ONCE(1); 2626 break; 2627 } 2628 } 2629 2630 static int rtl8153_enable(struct r8152 *tp) 2631 { 2632 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2633 return -ENODEV; 2634 2635 set_tx_qlen(tp); 2636 rtl_set_eee_plus(tp); 2637 r8153_set_rx_early_timeout(tp); 2638 r8153_set_rx_early_size(tp); 2639 2640 return rtl_enable(tp); 2641 } 2642 2643 static void rtl_disable(struct r8152 *tp) 2644 { 2645 u32 ocp_data; 2646 int i; 2647 2648 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2649 rtl_drop_queued_tx(tp); 2650 return; 2651 } 2652 2653 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2654 ocp_data &= ~RCR_ACPT_ALL; 2655 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2656 2657 rtl_drop_queued_tx(tp); 2658 2659 for (i = 0; i < RTL8152_MAX_TX; i++) 2660 usb_kill_urb(tp->tx_info[i].urb); 2661 2662 rxdy_gated_en(tp, true); 2663 2664 for (i = 0; i < 1000; i++) { 2665 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2666 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2667 break; 2668 usleep_range(1000, 2000); 2669 } 2670 2671 for (i = 0; i < 1000; i++) { 2672 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2673 break; 2674 usleep_range(1000, 2000); 2675 } 2676 2677 rtl_stop_rx(tp); 2678 2679 rtl8152_nic_reset(tp); 2680 } 2681 2682 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2683 { 2684 u32 ocp_data; 2685 2686 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2687 if (enable) 2688 ocp_data |= POWER_CUT; 2689 else 2690 ocp_data &= ~POWER_CUT; 2691 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2692 2693 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2694 ocp_data &= ~RESUME_INDICATE; 2695 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2696 } 2697 2698 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 2699 { 2700 u32 ocp_data; 2701 2702 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2703 if (enable) 2704 ocp_data |= CPCR_RX_VLAN; 2705 else 2706 ocp_data &= ~CPCR_RX_VLAN; 2707 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2708 } 2709 2710 static int rtl8152_set_features(struct net_device *dev, 2711 netdev_features_t features) 2712 { 2713 netdev_features_t changed = features ^ dev->features; 2714 struct r8152 *tp = netdev_priv(dev); 2715 int ret; 2716 2717 ret = usb_autopm_get_interface(tp->intf); 2718 if (ret < 0) 2719 goto out; 2720 2721 mutex_lock(&tp->control); 2722 2723 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 2724 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2725 rtl_rx_vlan_en(tp, true); 2726 else 2727 rtl_rx_vlan_en(tp, false); 2728 } 2729 2730 mutex_unlock(&tp->control); 2731 2732 usb_autopm_put_interface(tp->intf); 2733 2734 out: 2735 return ret; 2736 } 2737 2738 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2739 2740 static u32 __rtl_get_wol(struct r8152 *tp) 2741 { 2742 u32 ocp_data; 2743 u32 wolopts = 0; 2744 2745 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2746 if (ocp_data & LINK_ON_WAKE_EN) 2747 wolopts |= WAKE_PHY; 2748 2749 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2750 if (ocp_data & UWF_EN) 2751 wolopts |= WAKE_UCAST; 2752 if (ocp_data & BWF_EN) 2753 wolopts |= WAKE_BCAST; 2754 if (ocp_data & MWF_EN) 2755 wolopts |= WAKE_MCAST; 2756 2757 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2758 if (ocp_data & MAGIC_EN) 2759 wolopts |= WAKE_MAGIC; 2760 2761 return wolopts; 2762 } 2763 2764 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2765 { 2766 u32 ocp_data; 2767 2768 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2769 2770 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2771 ocp_data &= ~LINK_ON_WAKE_EN; 2772 if (wolopts & WAKE_PHY) 2773 ocp_data |= LINK_ON_WAKE_EN; 2774 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2775 2776 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2777 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); 2778 if (wolopts & WAKE_UCAST) 2779 ocp_data |= UWF_EN; 2780 if (wolopts & WAKE_BCAST) 2781 ocp_data |= BWF_EN; 2782 if (wolopts & WAKE_MCAST) 2783 ocp_data |= MWF_EN; 2784 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2785 2786 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2787 2788 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2789 ocp_data &= ~MAGIC_EN; 2790 if (wolopts & WAKE_MAGIC) 2791 ocp_data |= MAGIC_EN; 2792 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2793 2794 if (wolopts & WAKE_ANY) 2795 device_set_wakeup_enable(&tp->udev->dev, true); 2796 else 2797 device_set_wakeup_enable(&tp->udev->dev, false); 2798 } 2799 2800 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable) 2801 { 2802 /* MAC clock speed down */ 2803 if (enable) { 2804 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 2805 ALDPS_SPDWN_RATIO); 2806 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 2807 EEE_SPDWN_RATIO); 2808 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 2809 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | 2810 U1U2_SPDWN_EN | L1_SPDWN_EN); 2811 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 2812 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | 2813 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN | 2814 TP1000_SPDWN_EN); 2815 } else { 2816 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); 2817 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); 2818 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); 2819 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); 2820 } 2821 } 2822 2823 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2824 { 2825 u8 u1u2[8]; 2826 2827 if (enable) 2828 memset(u1u2, 0xff, sizeof(u1u2)); 2829 else 2830 memset(u1u2, 0x00, sizeof(u1u2)); 2831 2832 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2833 } 2834 2835 static void r8153b_u1u2en(struct r8152 *tp, bool enable) 2836 { 2837 u32 ocp_data; 2838 2839 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); 2840 if (enable) 2841 ocp_data |= LPM_U1U2_EN; 2842 else 2843 ocp_data &= ~LPM_U1U2_EN; 2844 2845 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); 2846 } 2847 2848 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2849 { 2850 u32 ocp_data; 2851 2852 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2853 if (enable) 2854 ocp_data |= U2P3_ENABLE; 2855 else 2856 ocp_data &= ~U2P3_ENABLE; 2857 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2858 } 2859 2860 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear) 2861 { 2862 u32 ocp_data; 2863 2864 ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS); 2865 ocp_data &= ~clear; 2866 ocp_data |= set; 2867 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data); 2868 } 2869 2870 static void r8153b_green_en(struct r8152 *tp, bool enable) 2871 { 2872 u16 data; 2873 2874 if (enable) { 2875 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ 2876 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ 2877 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ 2878 } else { 2879 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ 2880 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ 2881 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ 2882 } 2883 2884 data = sram_read(tp, SRAM_GREEN_CFG); 2885 data |= GREEN_ETH_EN; 2886 sram_write(tp, SRAM_GREEN_CFG, data); 2887 2888 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0); 2889 } 2890 2891 static u16 r8153_phy_status(struct r8152 *tp, u16 desired) 2892 { 2893 u16 data; 2894 int i; 2895 2896 for (i = 0; i < 500; i++) { 2897 data = ocp_reg_read(tp, OCP_PHY_STATUS); 2898 data &= PHY_STAT_MASK; 2899 if (desired) { 2900 if (data == desired) 2901 break; 2902 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN || 2903 data == PHY_STAT_EXT_INIT) { 2904 break; 2905 } 2906 2907 msleep(20); 2908 } 2909 2910 return data; 2911 } 2912 2913 static void r8153b_ups_en(struct r8152 *tp, bool enable) 2914 { 2915 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); 2916 2917 if (enable) { 2918 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; 2919 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2920 2921 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 2922 ocp_data |= BIT(0); 2923 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 2924 } else { 2925 u16 data; 2926 2927 ocp_data &= ~(UPS_EN | USP_PREWAKE); 2928 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2929 2930 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 2931 ocp_data &= ~BIT(0); 2932 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 2933 2934 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2935 ocp_data &= ~PCUT_STATUS; 2936 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2937 2938 data = r8153_phy_status(tp, 0); 2939 2940 switch (data) { 2941 case PHY_STAT_PWRDN: 2942 case PHY_STAT_EXT_INIT: 2943 r8153b_green_en(tp, 2944 test_bit(GREEN_ETHERNET, &tp->flags)); 2945 2946 data = r8152_mdio_read(tp, MII_BMCR); 2947 data &= ~BMCR_PDOWN; 2948 data |= BMCR_RESET; 2949 r8152_mdio_write(tp, MII_BMCR, data); 2950 2951 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 2952 /* fall through */ 2953 2954 default: 2955 if (data != PHY_STAT_LAN_ON) 2956 netif_warn(tp, link, tp->netdev, 2957 "PHY not ready"); 2958 break; 2959 } 2960 } 2961 } 2962 2963 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2964 { 2965 u32 ocp_data; 2966 2967 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2968 if (enable) 2969 ocp_data |= PWR_EN | PHASE2_EN; 2970 else 2971 ocp_data &= ~(PWR_EN | PHASE2_EN); 2972 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2973 2974 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2975 ocp_data &= ~PCUT_STATUS; 2976 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2977 } 2978 2979 static void r8153b_power_cut_en(struct r8152 *tp, bool enable) 2980 { 2981 u32 ocp_data; 2982 2983 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2984 if (enable) 2985 ocp_data |= PWR_EN | PHASE2_EN; 2986 else 2987 ocp_data &= ~PWR_EN; 2988 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2989 2990 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2991 ocp_data &= ~PCUT_STATUS; 2992 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2993 } 2994 2995 static void r8153_queue_wake(struct r8152 *tp, bool enable) 2996 { 2997 u32 ocp_data; 2998 2999 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG); 3000 if (enable) 3001 ocp_data |= UPCOMING_RUNTIME_D3; 3002 else 3003 ocp_data &= ~UPCOMING_RUNTIME_D3; 3004 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data); 3005 3006 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG); 3007 ocp_data &= ~LINK_CHG_EVENT; 3008 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data); 3009 3010 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); 3011 ocp_data &= ~LINK_CHANGE_FLAG; 3012 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); 3013 } 3014 3015 static bool rtl_can_wakeup(struct r8152 *tp) 3016 { 3017 struct usb_device *udev = tp->udev; 3018 3019 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); 3020 } 3021 3022 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 3023 { 3024 if (enable) { 3025 u32 ocp_data; 3026 3027 __rtl_set_wol(tp, WAKE_ANY); 3028 3029 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 3030 3031 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 3032 ocp_data |= LINK_OFF_WAKE_EN; 3033 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 3034 3035 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3036 } else { 3037 u32 ocp_data; 3038 3039 __rtl_set_wol(tp, tp->saved_wolopts); 3040 3041 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 3042 3043 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 3044 ocp_data &= ~LINK_OFF_WAKE_EN; 3045 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 3046 3047 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3048 } 3049 } 3050 3051 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) 3052 { 3053 if (enable) { 3054 r8153_u1u2en(tp, false); 3055 r8153_u2p3en(tp, false); 3056 r8153_mac_clk_spd(tp, true); 3057 rtl_runtime_suspend_enable(tp, true); 3058 } else { 3059 rtl_runtime_suspend_enable(tp, false); 3060 r8153_mac_clk_spd(tp, false); 3061 3062 switch (tp->version) { 3063 case RTL_VER_03: 3064 case RTL_VER_04: 3065 break; 3066 case RTL_VER_05: 3067 case RTL_VER_06: 3068 default: 3069 r8153_u2p3en(tp, true); 3070 break; 3071 } 3072 3073 r8153_u1u2en(tp, true); 3074 } 3075 } 3076 3077 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable) 3078 { 3079 if (enable) { 3080 r8153_queue_wake(tp, true); 3081 r8153b_u1u2en(tp, false); 3082 r8153_u2p3en(tp, false); 3083 rtl_runtime_suspend_enable(tp, true); 3084 r8153b_ups_en(tp, true); 3085 } else { 3086 r8153b_ups_en(tp, false); 3087 r8153_queue_wake(tp, false); 3088 rtl_runtime_suspend_enable(tp, false); 3089 r8153_u2p3en(tp, true); 3090 r8153b_u1u2en(tp, true); 3091 } 3092 } 3093 3094 static void r8153_teredo_off(struct r8152 *tp) 3095 { 3096 u32 ocp_data; 3097 3098 switch (tp->version) { 3099 case RTL_VER_01: 3100 case RTL_VER_02: 3101 case RTL_VER_03: 3102 case RTL_VER_04: 3103 case RTL_VER_05: 3104 case RTL_VER_06: 3105 case RTL_VER_07: 3106 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 3107 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | 3108 OOB_TEREDO_EN); 3109 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 3110 break; 3111 3112 case RTL_VER_08: 3113 case RTL_VER_09: 3114 /* The bit 0 ~ 7 are relative with teredo settings. They are 3115 * W1C (write 1 to clear), so set all 1 to disable it. 3116 */ 3117 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); 3118 break; 3119 3120 default: 3121 break; 3122 } 3123 3124 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 3125 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 3126 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 3127 } 3128 3129 static void rtl_reset_bmu(struct r8152 *tp) 3130 { 3131 u32 ocp_data; 3132 3133 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); 3134 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 3135 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 3136 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 3137 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 3138 } 3139 3140 static void r8152_aldps_en(struct r8152 *tp, bool enable) 3141 { 3142 if (enable) { 3143 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 3144 LINKENA | DIS_SDSAVE); 3145 } else { 3146 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | 3147 DIS_SDSAVE); 3148 msleep(20); 3149 } 3150 } 3151 3152 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 3153 { 3154 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 3155 ocp_reg_write(tp, OCP_EEE_DATA, reg); 3156 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 3157 } 3158 3159 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 3160 { 3161 u16 data; 3162 3163 r8152_mmd_indirect(tp, dev, reg); 3164 data = ocp_reg_read(tp, OCP_EEE_DATA); 3165 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3166 3167 return data; 3168 } 3169 3170 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 3171 { 3172 r8152_mmd_indirect(tp, dev, reg); 3173 ocp_reg_write(tp, OCP_EEE_DATA, data); 3174 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3175 } 3176 3177 static void r8152_eee_en(struct r8152 *tp, bool enable) 3178 { 3179 u16 config1, config2, config3; 3180 u32 ocp_data; 3181 3182 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3183 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 3184 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 3185 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 3186 3187 if (enable) { 3188 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3189 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 3190 config1 |= sd_rise_time(1); 3191 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 3192 config3 |= fast_snr(42); 3193 } else { 3194 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3195 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 3196 RX_QUIET_EN); 3197 config1 |= sd_rise_time(7); 3198 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 3199 config3 |= fast_snr(511); 3200 } 3201 3202 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3203 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 3204 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 3205 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 3206 } 3207 3208 static void r8153_eee_en(struct r8152 *tp, bool enable) 3209 { 3210 u32 ocp_data; 3211 u16 config; 3212 3213 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3214 config = ocp_reg_read(tp, OCP_EEE_CFG); 3215 3216 if (enable) { 3217 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3218 config |= EEE10_EN; 3219 } else { 3220 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3221 config &= ~EEE10_EN; 3222 } 3223 3224 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3225 ocp_reg_write(tp, OCP_EEE_CFG, config); 3226 } 3227 3228 static void r8153b_eee_en(struct r8152 *tp, bool enable) 3229 { 3230 r8153_eee_en(tp, enable); 3231 3232 if (enable) 3233 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0); 3234 else 3235 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE); 3236 } 3237 3238 static void rtl_eee_enable(struct r8152 *tp, bool enable) 3239 { 3240 switch (tp->version) { 3241 case RTL_VER_01: 3242 case RTL_VER_02: 3243 case RTL_VER_07: 3244 if (enable) { 3245 r8152_eee_en(tp, true); 3246 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 3247 tp->eee_adv); 3248 } else { 3249 r8152_eee_en(tp, false); 3250 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); 3251 } 3252 break; 3253 case RTL_VER_03: 3254 case RTL_VER_04: 3255 case RTL_VER_05: 3256 case RTL_VER_06: 3257 if (enable) { 3258 r8153_eee_en(tp, true); 3259 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); 3260 } else { 3261 r8153_eee_en(tp, false); 3262 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3263 } 3264 break; 3265 case RTL_VER_08: 3266 case RTL_VER_09: 3267 if (enable) { 3268 r8153b_eee_en(tp, true); 3269 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); 3270 } else { 3271 r8153b_eee_en(tp, false); 3272 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3273 } 3274 break; 3275 default: 3276 break; 3277 } 3278 } 3279 3280 static void r8152b_enable_fc(struct r8152 *tp) 3281 { 3282 u16 anar; 3283 3284 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3285 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 3286 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3287 } 3288 3289 static void rtl8152_disable(struct r8152 *tp) 3290 { 3291 r8152_aldps_en(tp, false); 3292 rtl_disable(tp); 3293 r8152_aldps_en(tp, true); 3294 } 3295 3296 static void r8152b_hw_phy_cfg(struct r8152 *tp) 3297 { 3298 rtl_eee_enable(tp, tp->eee_en); 3299 r8152_aldps_en(tp, true); 3300 r8152b_enable_fc(tp); 3301 3302 set_bit(PHY_RESET, &tp->flags); 3303 } 3304 3305 static void r8152b_exit_oob(struct r8152 *tp) 3306 { 3307 u32 ocp_data; 3308 int i; 3309 3310 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3311 ocp_data &= ~RCR_ACPT_ALL; 3312 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3313 3314 rxdy_gated_en(tp, true); 3315 r8153_teredo_off(tp); 3316 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3317 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 3318 3319 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3320 ocp_data &= ~NOW_IS_OOB; 3321 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3322 3323 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3324 ocp_data &= ~MCU_BORW_EN; 3325 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3326 3327 for (i = 0; i < 1000; i++) { 3328 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3329 if (ocp_data & LINK_LIST_READY) 3330 break; 3331 usleep_range(1000, 2000); 3332 } 3333 3334 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3335 ocp_data |= RE_INIT_LL; 3336 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3337 3338 for (i = 0; i < 1000; i++) { 3339 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3340 if (ocp_data & LINK_LIST_READY) 3341 break; 3342 usleep_range(1000, 2000); 3343 } 3344 3345 rtl8152_nic_reset(tp); 3346 3347 /* rx share fifo credit full threshold */ 3348 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3349 3350 if (tp->udev->speed == USB_SPEED_FULL || 3351 tp->udev->speed == USB_SPEED_LOW) { 3352 /* rx share fifo credit near full threshold */ 3353 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3354 RXFIFO_THR2_FULL); 3355 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3356 RXFIFO_THR3_FULL); 3357 } else { 3358 /* rx share fifo credit near full threshold */ 3359 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3360 RXFIFO_THR2_HIGH); 3361 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3362 RXFIFO_THR3_HIGH); 3363 } 3364 3365 /* TX share fifo free credit full threshold */ 3366 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 3367 3368 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 3369 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 3370 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 3371 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 3372 3373 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3374 3375 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3376 3377 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3378 ocp_data |= TCR0_AUTO_FIFO; 3379 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3380 } 3381 3382 static void r8152b_enter_oob(struct r8152 *tp) 3383 { 3384 u32 ocp_data; 3385 int i; 3386 3387 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3388 ocp_data &= ~NOW_IS_OOB; 3389 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3390 3391 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 3392 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 3393 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 3394 3395 rtl_disable(tp); 3396 3397 for (i = 0; i < 1000; i++) { 3398 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3399 if (ocp_data & LINK_LIST_READY) 3400 break; 3401 usleep_range(1000, 2000); 3402 } 3403 3404 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3405 ocp_data |= RE_INIT_LL; 3406 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3407 3408 for (i = 0; i < 1000; i++) { 3409 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3410 if (ocp_data & LINK_LIST_READY) 3411 break; 3412 usleep_range(1000, 2000); 3413 } 3414 3415 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3416 3417 rtl_rx_vlan_en(tp, true); 3418 3419 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); 3420 ocp_data |= ALDPS_PROXY_MODE; 3421 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); 3422 3423 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3424 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3425 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3426 3427 rxdy_gated_en(tp, false); 3428 3429 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3430 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3431 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3432 } 3433 3434 static int r8153_patch_request(struct r8152 *tp, bool request) 3435 { 3436 u16 data; 3437 int i; 3438 3439 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD); 3440 if (request) 3441 data |= PATCH_REQUEST; 3442 else 3443 data &= ~PATCH_REQUEST; 3444 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); 3445 3446 for (i = 0; request && i < 5000; i++) { 3447 usleep_range(1000, 2000); 3448 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY) 3449 break; 3450 } 3451 3452 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) { 3453 netif_err(tp, drv, tp->netdev, "patch request fail\n"); 3454 r8153_patch_request(tp, false); 3455 return -ETIME; 3456 } else { 3457 return 0; 3458 } 3459 } 3460 3461 static void r8153_aldps_en(struct r8152 *tp, bool enable) 3462 { 3463 u16 data; 3464 3465 data = ocp_reg_read(tp, OCP_POWER_CFG); 3466 if (enable) { 3467 data |= EN_ALDPS; 3468 ocp_reg_write(tp, OCP_POWER_CFG, data); 3469 } else { 3470 int i; 3471 3472 data &= ~EN_ALDPS; 3473 ocp_reg_write(tp, OCP_POWER_CFG, data); 3474 for (i = 0; i < 20; i++) { 3475 usleep_range(1000, 2000); 3476 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) 3477 break; 3478 } 3479 } 3480 } 3481 3482 static void r8153b_aldps_en(struct r8152 *tp, bool enable) 3483 { 3484 r8153_aldps_en(tp, enable); 3485 3486 if (enable) 3487 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0); 3488 else 3489 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS); 3490 } 3491 3492 static void r8153b_enable_fc(struct r8152 *tp) 3493 { 3494 r8152b_enable_fc(tp); 3495 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0); 3496 } 3497 3498 static void r8153_hw_phy_cfg(struct r8152 *tp) 3499 { 3500 u32 ocp_data; 3501 u16 data; 3502 3503 /* disable ALDPS before updating the PHY parameters */ 3504 r8153_aldps_en(tp, false); 3505 3506 /* disable EEE before updating the PHY parameters */ 3507 rtl_eee_enable(tp, false); 3508 3509 if (tp->version == RTL_VER_03) { 3510 data = ocp_reg_read(tp, OCP_EEE_CFG); 3511 data &= ~CTAP_SHORT_EN; 3512 ocp_reg_write(tp, OCP_EEE_CFG, data); 3513 } 3514 3515 data = ocp_reg_read(tp, OCP_POWER_CFG); 3516 data |= EEE_CLKDIV_EN; 3517 ocp_reg_write(tp, OCP_POWER_CFG, data); 3518 3519 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3520 data |= EN_10M_BGOFF; 3521 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3522 data = ocp_reg_read(tp, OCP_POWER_CFG); 3523 data |= EN_10M_PLLOFF; 3524 ocp_reg_write(tp, OCP_POWER_CFG, data); 3525 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 3526 3527 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3528 ocp_data |= PFM_PWM_SWITCH; 3529 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3530 3531 /* Enable LPF corner auto tune */ 3532 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 3533 3534 /* Adjust 10M Amplitude */ 3535 sram_write(tp, SRAM_10M_AMP1, 0x00af); 3536 sram_write(tp, SRAM_10M_AMP2, 0x0208); 3537 3538 if (tp->eee_en) 3539 rtl_eee_enable(tp, true); 3540 3541 r8153_aldps_en(tp, true); 3542 r8152b_enable_fc(tp); 3543 3544 switch (tp->version) { 3545 case RTL_VER_03: 3546 case RTL_VER_04: 3547 break; 3548 case RTL_VER_05: 3549 case RTL_VER_06: 3550 default: 3551 r8153_u2p3en(tp, true); 3552 break; 3553 } 3554 3555 set_bit(PHY_RESET, &tp->flags); 3556 } 3557 3558 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) 3559 { 3560 u32 ocp_data; 3561 3562 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr); 3563 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD); 3564 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */ 3565 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA); 3566 3567 return ocp_data; 3568 } 3569 3570 static void r8153b_hw_phy_cfg(struct r8152 *tp) 3571 { 3572 u32 ocp_data, ups_flags = 0; 3573 u16 data; 3574 3575 /* disable ALDPS before updating the PHY parameters */ 3576 r8153b_aldps_en(tp, false); 3577 3578 /* disable EEE before updating the PHY parameters */ 3579 rtl_eee_enable(tp, false); 3580 3581 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); 3582 3583 data = sram_read(tp, SRAM_GREEN_CFG); 3584 data |= R_TUNE_EN; 3585 sram_write(tp, SRAM_GREEN_CFG, data); 3586 data = ocp_reg_read(tp, OCP_NCTL_CFG); 3587 data |= PGA_RETURN_EN; 3588 ocp_reg_write(tp, OCP_NCTL_CFG, data); 3589 3590 /* ADC Bias Calibration: 3591 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake 3592 * bit (bit3) to rebuild the real 16-bit data. Write the data to the 3593 * ADC ioffset. 3594 */ 3595 ocp_data = r8152_efuse_read(tp, 0x7d); 3596 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); 3597 if (data != 0xffff) 3598 ocp_reg_write(tp, OCP_ADC_IOFFSET, data); 3599 3600 /* ups mode tx-link-pulse timing adjustment: 3601 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] 3602 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt 3603 */ 3604 ocp_data = ocp_reg_read(tp, 0xc426); 3605 ocp_data &= 0x3fff; 3606 if (ocp_data) { 3607 u32 swr_cnt_1ms_ini; 3608 3609 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; 3610 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); 3611 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; 3612 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); 3613 } 3614 3615 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3616 ocp_data |= PFM_PWM_SWITCH; 3617 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3618 3619 /* Advnace EEE */ 3620 if (!r8153_patch_request(tp, true)) { 3621 data = ocp_reg_read(tp, OCP_POWER_CFG); 3622 data |= EEE_CLKDIV_EN; 3623 ocp_reg_write(tp, OCP_POWER_CFG, data); 3624 3625 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3626 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV; 3627 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3628 3629 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); 3630 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5)); 3631 3632 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV | 3633 UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN | 3634 UPS_FLAGS_EEE_PLLOFF_GIGA; 3635 3636 r8153_patch_request(tp, false); 3637 } 3638 3639 r8153b_ups_flags_w1w0(tp, ups_flags, 0); 3640 3641 if (tp->eee_en) 3642 rtl_eee_enable(tp, true); 3643 3644 r8153b_aldps_en(tp, true); 3645 r8153b_enable_fc(tp); 3646 r8153_u2p3en(tp, true); 3647 3648 set_bit(PHY_RESET, &tp->flags); 3649 } 3650 3651 static void r8153_first_init(struct r8152 *tp) 3652 { 3653 u32 ocp_data; 3654 int i; 3655 3656 r8153_mac_clk_spd(tp, false); 3657 rxdy_gated_en(tp, true); 3658 r8153_teredo_off(tp); 3659 3660 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3661 ocp_data &= ~RCR_ACPT_ALL; 3662 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3663 3664 rtl8152_nic_reset(tp); 3665 rtl_reset_bmu(tp); 3666 3667 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3668 ocp_data &= ~NOW_IS_OOB; 3669 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3670 3671 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3672 ocp_data &= ~MCU_BORW_EN; 3673 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3674 3675 for (i = 0; i < 1000; i++) { 3676 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3677 if (ocp_data & LINK_LIST_READY) 3678 break; 3679 usleep_range(1000, 2000); 3680 } 3681 3682 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3683 ocp_data |= RE_INIT_LL; 3684 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3685 3686 for (i = 0; i < 1000; i++) { 3687 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3688 if (ocp_data & LINK_LIST_READY) 3689 break; 3690 usleep_range(1000, 2000); 3691 } 3692 3693 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3694 3695 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3696 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3697 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 3698 3699 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3700 ocp_data |= TCR0_AUTO_FIFO; 3701 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3702 3703 rtl8152_nic_reset(tp); 3704 3705 /* rx share fifo credit full threshold */ 3706 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3707 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 3708 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 3709 /* TX share fifo free credit full threshold */ 3710 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 3711 } 3712 3713 static void r8153_enter_oob(struct r8152 *tp) 3714 { 3715 u32 ocp_data; 3716 int i; 3717 3718 r8153_mac_clk_spd(tp, true); 3719 3720 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3721 ocp_data &= ~NOW_IS_OOB; 3722 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3723 3724 rtl_disable(tp); 3725 rtl_reset_bmu(tp); 3726 3727 for (i = 0; i < 1000; i++) { 3728 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3729 if (ocp_data & LINK_LIST_READY) 3730 break; 3731 usleep_range(1000, 2000); 3732 } 3733 3734 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3735 ocp_data |= RE_INIT_LL; 3736 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3737 3738 for (i = 0; i < 1000; i++) { 3739 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3740 if (ocp_data & LINK_LIST_READY) 3741 break; 3742 usleep_range(1000, 2000); 3743 } 3744 3745 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3746 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3747 3748 switch (tp->version) { 3749 case RTL_VER_03: 3750 case RTL_VER_04: 3751 case RTL_VER_05: 3752 case RTL_VER_06: 3753 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 3754 ocp_data &= ~TEREDO_WAKE_MASK; 3755 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 3756 break; 3757 3758 case RTL_VER_08: 3759 case RTL_VER_09: 3760 /* Clear teredo wake event. bit[15:8] is the teredo wakeup 3761 * type. Set it to zero. bits[7:0] are the W1C bits about 3762 * the events. Set them to all 1 to clear them. 3763 */ 3764 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); 3765 break; 3766 3767 default: 3768 break; 3769 } 3770 3771 rtl_rx_vlan_en(tp, true); 3772 3773 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); 3774 ocp_data |= ALDPS_PROXY_MODE; 3775 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); 3776 3777 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3778 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3779 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3780 3781 rxdy_gated_en(tp, false); 3782 3783 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3784 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3785 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3786 } 3787 3788 static void rtl8153_disable(struct r8152 *tp) 3789 { 3790 r8153_aldps_en(tp, false); 3791 rtl_disable(tp); 3792 rtl_reset_bmu(tp); 3793 r8153_aldps_en(tp, true); 3794 } 3795 3796 static void rtl8153b_disable(struct r8152 *tp) 3797 { 3798 r8153b_aldps_en(tp, false); 3799 rtl_disable(tp); 3800 rtl_reset_bmu(tp); 3801 r8153b_aldps_en(tp, true); 3802 } 3803 3804 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 3805 { 3806 u16 bmcr, anar, gbcr; 3807 enum spd_duplex speed_duplex; 3808 int ret = 0; 3809 3810 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3811 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 3812 ADVERTISE_100HALF | ADVERTISE_100FULL); 3813 if (tp->mii.supports_gmii) { 3814 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 3815 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 3816 } else { 3817 gbcr = 0; 3818 } 3819 3820 if (autoneg == AUTONEG_DISABLE) { 3821 if (speed == SPEED_10) { 3822 bmcr = 0; 3823 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3824 speed_duplex = FORCE_10M_HALF; 3825 } else if (speed == SPEED_100) { 3826 bmcr = BMCR_SPEED100; 3827 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3828 speed_duplex = FORCE_100M_HALF; 3829 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3830 bmcr = BMCR_SPEED1000; 3831 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3832 speed_duplex = NWAY_1000M_FULL; 3833 } else { 3834 ret = -EINVAL; 3835 goto out; 3836 } 3837 3838 if (duplex == DUPLEX_FULL) { 3839 bmcr |= BMCR_FULLDPLX; 3840 if (speed != SPEED_1000) 3841 speed_duplex++; 3842 } 3843 } else { 3844 if (speed == SPEED_10) { 3845 if (duplex == DUPLEX_FULL) { 3846 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3847 speed_duplex = NWAY_10M_FULL; 3848 } else { 3849 anar |= ADVERTISE_10HALF; 3850 speed_duplex = NWAY_10M_HALF; 3851 } 3852 } else if (speed == SPEED_100) { 3853 if (duplex == DUPLEX_FULL) { 3854 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3855 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3856 speed_duplex = NWAY_100M_FULL; 3857 } else { 3858 anar |= ADVERTISE_10HALF; 3859 anar |= ADVERTISE_100HALF; 3860 speed_duplex = NWAY_100M_HALF; 3861 } 3862 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3863 if (duplex == DUPLEX_FULL) { 3864 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3865 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3866 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3867 } else { 3868 anar |= ADVERTISE_10HALF; 3869 anar |= ADVERTISE_100HALF; 3870 gbcr |= ADVERTISE_1000HALF; 3871 } 3872 speed_duplex = NWAY_1000M_FULL; 3873 } else { 3874 ret = -EINVAL; 3875 goto out; 3876 } 3877 3878 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 3879 } 3880 3881 if (test_and_clear_bit(PHY_RESET, &tp->flags)) 3882 bmcr |= BMCR_RESET; 3883 3884 if (tp->mii.supports_gmii) 3885 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 3886 3887 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3888 r8152_mdio_write(tp, MII_BMCR, bmcr); 3889 3890 switch (tp->version) { 3891 case RTL_VER_08: 3892 case RTL_VER_09: 3893 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex), 3894 UPS_FLAGS_SPEED_MASK); 3895 break; 3896 3897 default: 3898 break; 3899 } 3900 3901 if (bmcr & BMCR_RESET) { 3902 int i; 3903 3904 for (i = 0; i < 50; i++) { 3905 msleep(20); 3906 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 3907 break; 3908 } 3909 } 3910 3911 out: 3912 return ret; 3913 } 3914 3915 static void rtl8152_up(struct r8152 *tp) 3916 { 3917 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3918 return; 3919 3920 r8152_aldps_en(tp, false); 3921 r8152b_exit_oob(tp); 3922 r8152_aldps_en(tp, true); 3923 } 3924 3925 static void rtl8152_down(struct r8152 *tp) 3926 { 3927 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3928 rtl_drop_queued_tx(tp); 3929 return; 3930 } 3931 3932 r8152_power_cut_en(tp, false); 3933 r8152_aldps_en(tp, false); 3934 r8152b_enter_oob(tp); 3935 r8152_aldps_en(tp, true); 3936 } 3937 3938 static void rtl8153_up(struct r8152 *tp) 3939 { 3940 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3941 return; 3942 3943 r8153_u1u2en(tp, false); 3944 r8153_u2p3en(tp, false); 3945 r8153_aldps_en(tp, false); 3946 r8153_first_init(tp); 3947 r8153_aldps_en(tp, true); 3948 3949 switch (tp->version) { 3950 case RTL_VER_03: 3951 case RTL_VER_04: 3952 break; 3953 case RTL_VER_05: 3954 case RTL_VER_06: 3955 default: 3956 r8153_u2p3en(tp, true); 3957 break; 3958 } 3959 3960 r8153_u1u2en(tp, true); 3961 } 3962 3963 static void rtl8153_down(struct r8152 *tp) 3964 { 3965 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3966 rtl_drop_queued_tx(tp); 3967 return; 3968 } 3969 3970 r8153_u1u2en(tp, false); 3971 r8153_u2p3en(tp, false); 3972 r8153_power_cut_en(tp, false); 3973 r8153_aldps_en(tp, false); 3974 r8153_enter_oob(tp); 3975 r8153_aldps_en(tp, true); 3976 } 3977 3978 static void rtl8153b_up(struct r8152 *tp) 3979 { 3980 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3981 return; 3982 3983 r8153b_u1u2en(tp, false); 3984 r8153_u2p3en(tp, false); 3985 r8153b_aldps_en(tp, false); 3986 3987 r8153_first_init(tp); 3988 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); 3989 3990 r8153b_aldps_en(tp, true); 3991 r8153_u2p3en(tp, true); 3992 r8153b_u1u2en(tp, true); 3993 } 3994 3995 static void rtl8153b_down(struct r8152 *tp) 3996 { 3997 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3998 rtl_drop_queued_tx(tp); 3999 return; 4000 } 4001 4002 r8153b_u1u2en(tp, false); 4003 r8153_u2p3en(tp, false); 4004 r8153b_power_cut_en(tp, false); 4005 r8153b_aldps_en(tp, false); 4006 r8153_enter_oob(tp); 4007 r8153b_aldps_en(tp, true); 4008 } 4009 4010 static bool rtl8152_in_nway(struct r8152 *tp) 4011 { 4012 u16 nway_state; 4013 4014 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); 4015 tp->ocp_base = 0x2000; 4016 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ 4017 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); 4018 4019 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ 4020 if (nway_state & 0xc000) 4021 return false; 4022 else 4023 return true; 4024 } 4025 4026 static bool rtl8153_in_nway(struct r8152 *tp) 4027 { 4028 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; 4029 4030 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) 4031 return false; 4032 else 4033 return true; 4034 } 4035 4036 static void set_carrier(struct r8152 *tp) 4037 { 4038 struct net_device *netdev = tp->netdev; 4039 struct napi_struct *napi = &tp->napi; 4040 u8 speed; 4041 4042 speed = rtl8152_get_speed(tp); 4043 4044 if (speed & LINK_STATUS) { 4045 if (!netif_carrier_ok(netdev)) { 4046 tp->rtl_ops.enable(tp); 4047 netif_stop_queue(netdev); 4048 napi_disable(napi); 4049 netif_carrier_on(netdev); 4050 rtl_start_rx(tp); 4051 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 4052 _rtl8152_set_rx_mode(netdev); 4053 napi_enable(&tp->napi); 4054 netif_wake_queue(netdev); 4055 netif_info(tp, link, netdev, "carrier on\n"); 4056 } else if (netif_queue_stopped(netdev) && 4057 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) { 4058 netif_wake_queue(netdev); 4059 } 4060 } else { 4061 if (netif_carrier_ok(netdev)) { 4062 netif_carrier_off(netdev); 4063 tasklet_disable(&tp->tx_tl); 4064 napi_disable(napi); 4065 tp->rtl_ops.disable(tp); 4066 napi_enable(napi); 4067 tasklet_enable(&tp->tx_tl); 4068 netif_info(tp, link, netdev, "carrier off\n"); 4069 } 4070 } 4071 } 4072 4073 static void rtl_work_func_t(struct work_struct *work) 4074 { 4075 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 4076 4077 /* If the device is unplugged or !netif_running(), the workqueue 4078 * doesn't need to wake the device, and could return directly. 4079 */ 4080 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) 4081 return; 4082 4083 if (usb_autopm_get_interface(tp->intf) < 0) 4084 return; 4085 4086 if (!test_bit(WORK_ENABLE, &tp->flags)) 4087 goto out1; 4088 4089 if (!mutex_trylock(&tp->control)) { 4090 schedule_delayed_work(&tp->schedule, 0); 4091 goto out1; 4092 } 4093 4094 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) 4095 set_carrier(tp); 4096 4097 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) 4098 _rtl8152_set_rx_mode(tp->netdev); 4099 4100 /* don't schedule tasket before linking */ 4101 if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) && 4102 netif_carrier_ok(tp->netdev)) 4103 tasklet_schedule(&tp->tx_tl); 4104 4105 mutex_unlock(&tp->control); 4106 4107 out1: 4108 usb_autopm_put_interface(tp->intf); 4109 } 4110 4111 static void rtl_hw_phy_work_func_t(struct work_struct *work) 4112 { 4113 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); 4114 4115 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4116 return; 4117 4118 if (usb_autopm_get_interface(tp->intf) < 0) 4119 return; 4120 4121 mutex_lock(&tp->control); 4122 4123 tp->rtl_ops.hw_phy_cfg(tp); 4124 4125 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex); 4126 4127 mutex_unlock(&tp->control); 4128 4129 usb_autopm_put_interface(tp->intf); 4130 } 4131 4132 #ifdef CONFIG_PM_SLEEP 4133 static int rtl_notifier(struct notifier_block *nb, unsigned long action, 4134 void *data) 4135 { 4136 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); 4137 4138 switch (action) { 4139 case PM_HIBERNATION_PREPARE: 4140 case PM_SUSPEND_PREPARE: 4141 usb_autopm_get_interface(tp->intf); 4142 break; 4143 4144 case PM_POST_HIBERNATION: 4145 case PM_POST_SUSPEND: 4146 usb_autopm_put_interface(tp->intf); 4147 break; 4148 4149 case PM_POST_RESTORE: 4150 case PM_RESTORE_PREPARE: 4151 default: 4152 break; 4153 } 4154 4155 return NOTIFY_DONE; 4156 } 4157 #endif 4158 4159 static int rtl8152_open(struct net_device *netdev) 4160 { 4161 struct r8152 *tp = netdev_priv(netdev); 4162 int res = 0; 4163 4164 res = alloc_all_mem(tp); 4165 if (res) 4166 goto out; 4167 4168 res = usb_autopm_get_interface(tp->intf); 4169 if (res < 0) 4170 goto out_free; 4171 4172 mutex_lock(&tp->control); 4173 4174 tp->rtl_ops.up(tp); 4175 4176 netif_carrier_off(netdev); 4177 netif_start_queue(netdev); 4178 set_bit(WORK_ENABLE, &tp->flags); 4179 4180 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 4181 if (res) { 4182 if (res == -ENODEV) 4183 netif_device_detach(tp->netdev); 4184 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 4185 res); 4186 goto out_unlock; 4187 } 4188 napi_enable(&tp->napi); 4189 tasklet_enable(&tp->tx_tl); 4190 4191 mutex_unlock(&tp->control); 4192 4193 usb_autopm_put_interface(tp->intf); 4194 #ifdef CONFIG_PM_SLEEP 4195 tp->pm_notifier.notifier_call = rtl_notifier; 4196 register_pm_notifier(&tp->pm_notifier); 4197 #endif 4198 return 0; 4199 4200 out_unlock: 4201 mutex_unlock(&tp->control); 4202 usb_autopm_put_interface(tp->intf); 4203 out_free: 4204 free_all_mem(tp); 4205 out: 4206 return res; 4207 } 4208 4209 static int rtl8152_close(struct net_device *netdev) 4210 { 4211 struct r8152 *tp = netdev_priv(netdev); 4212 int res = 0; 4213 4214 #ifdef CONFIG_PM_SLEEP 4215 unregister_pm_notifier(&tp->pm_notifier); 4216 #endif 4217 tasklet_disable(&tp->tx_tl); 4218 napi_disable(&tp->napi); 4219 clear_bit(WORK_ENABLE, &tp->flags); 4220 usb_kill_urb(tp->intr_urb); 4221 cancel_delayed_work_sync(&tp->schedule); 4222 netif_stop_queue(netdev); 4223 4224 res = usb_autopm_get_interface(tp->intf); 4225 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { 4226 rtl_drop_queued_tx(tp); 4227 rtl_stop_rx(tp); 4228 } else { 4229 mutex_lock(&tp->control); 4230 4231 tp->rtl_ops.down(tp); 4232 4233 mutex_unlock(&tp->control); 4234 4235 usb_autopm_put_interface(tp->intf); 4236 } 4237 4238 free_all_mem(tp); 4239 4240 return res; 4241 } 4242 4243 static void rtl_tally_reset(struct r8152 *tp) 4244 { 4245 u32 ocp_data; 4246 4247 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 4248 ocp_data |= TALLY_RESET; 4249 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 4250 } 4251 4252 static void r8152b_init(struct r8152 *tp) 4253 { 4254 u32 ocp_data; 4255 u16 data; 4256 4257 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4258 return; 4259 4260 data = r8152_mdio_read(tp, MII_BMCR); 4261 if (data & BMCR_PDOWN) { 4262 data &= ~BMCR_PDOWN; 4263 r8152_mdio_write(tp, MII_BMCR, data); 4264 } 4265 4266 r8152_aldps_en(tp, false); 4267 4268 if (tp->version == RTL_VER_01) { 4269 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4270 ocp_data &= ~LED_MODE_MASK; 4271 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4272 } 4273 4274 r8152_power_cut_en(tp, false); 4275 4276 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 4277 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 4278 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 4279 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 4280 ocp_data &= ~MCU_CLK_RATIO_MASK; 4281 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 4282 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 4283 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 4284 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 4285 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 4286 4287 rtl_tally_reset(tp); 4288 4289 /* enable rx aggregation */ 4290 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4291 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4292 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4293 } 4294 4295 static void r8153_init(struct r8152 *tp) 4296 { 4297 u32 ocp_data; 4298 u16 data; 4299 int i; 4300 4301 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4302 return; 4303 4304 r8153_u1u2en(tp, false); 4305 4306 for (i = 0; i < 500; i++) { 4307 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4308 AUTOLOAD_DONE) 4309 break; 4310 msleep(20); 4311 } 4312 4313 data = r8153_phy_status(tp, 0); 4314 4315 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 4316 tp->version == RTL_VER_05) 4317 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 4318 4319 data = r8152_mdio_read(tp, MII_BMCR); 4320 if (data & BMCR_PDOWN) { 4321 data &= ~BMCR_PDOWN; 4322 r8152_mdio_write(tp, MII_BMCR, data); 4323 } 4324 4325 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4326 4327 r8153_u2p3en(tp, false); 4328 4329 if (tp->version == RTL_VER_04) { 4330 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 4331 ocp_data &= ~pwd_dn_scale_mask; 4332 ocp_data |= pwd_dn_scale(96); 4333 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 4334 4335 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 4336 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 4337 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 4338 } else if (tp->version == RTL_VER_05) { 4339 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 4340 ocp_data &= ~ECM_ALDPS; 4341 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 4342 4343 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4344 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4345 ocp_data &= ~DYNAMIC_BURST; 4346 else 4347 ocp_data |= DYNAMIC_BURST; 4348 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4349 } else if (tp->version == RTL_VER_06) { 4350 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4351 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4352 ocp_data &= ~DYNAMIC_BURST; 4353 else 4354 ocp_data |= DYNAMIC_BURST; 4355 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4356 } 4357 4358 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 4359 ocp_data |= EP4_FULL_FC; 4360 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 4361 4362 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 4363 ocp_data &= ~TIMER11_EN; 4364 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 4365 4366 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4367 ocp_data &= ~LED_MODE_MASK; 4368 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4369 4370 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 4371 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) 4372 ocp_data |= LPM_TIMER_500MS; 4373 else 4374 ocp_data |= LPM_TIMER_500US; 4375 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 4376 4377 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 4378 ocp_data &= ~SEN_VAL_MASK; 4379 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 4380 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 4381 4382 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 4383 4384 r8153_power_cut_en(tp, false); 4385 r8153_u1u2en(tp, true); 4386 r8153_mac_clk_spd(tp, false); 4387 usb_enable_lpm(tp->udev); 4388 4389 /* rx aggregation */ 4390 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4391 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4392 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags)) 4393 ocp_data |= RX_AGG_DISABLE; 4394 4395 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4396 4397 rtl_tally_reset(tp); 4398 4399 switch (tp->udev->speed) { 4400 case USB_SPEED_SUPER: 4401 case USB_SPEED_SUPER_PLUS: 4402 tp->coalesce = COALESCE_SUPER; 4403 break; 4404 case USB_SPEED_HIGH: 4405 tp->coalesce = COALESCE_HIGH; 4406 break; 4407 default: 4408 tp->coalesce = COALESCE_SLOW; 4409 break; 4410 } 4411 } 4412 4413 static void r8153b_init(struct r8152 *tp) 4414 { 4415 u32 ocp_data; 4416 u16 data; 4417 int i; 4418 4419 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4420 return; 4421 4422 r8153b_u1u2en(tp, false); 4423 4424 for (i = 0; i < 500; i++) { 4425 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4426 AUTOLOAD_DONE) 4427 break; 4428 msleep(20); 4429 } 4430 4431 data = r8153_phy_status(tp, 0); 4432 4433 data = r8152_mdio_read(tp, MII_BMCR); 4434 if (data & BMCR_PDOWN) { 4435 data &= ~BMCR_PDOWN; 4436 r8152_mdio_write(tp, MII_BMCR, data); 4437 } 4438 4439 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4440 4441 r8153_u2p3en(tp, false); 4442 4443 /* MSC timer = 0xfff * 8ms = 32760 ms */ 4444 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 4445 4446 /* U1/U2/L1 idle timer. 500 us */ 4447 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 4448 4449 r8153b_power_cut_en(tp, false); 4450 r8153b_ups_en(tp, false); 4451 r8153_queue_wake(tp, false); 4452 rtl_runtime_suspend_enable(tp, false); 4453 r8153b_u1u2en(tp, true); 4454 usb_enable_lpm(tp->udev); 4455 4456 /* MAC clock speed down */ 4457 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); 4458 ocp_data |= MAC_CLK_SPDWN_EN; 4459 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); 4460 4461 set_bit(GREEN_ETHERNET, &tp->flags); 4462 4463 /* rx aggregation */ 4464 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4465 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4466 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4467 4468 rtl_tally_reset(tp); 4469 4470 tp->coalesce = 15000; /* 15 us */ 4471 } 4472 4473 static int rtl8152_pre_reset(struct usb_interface *intf) 4474 { 4475 struct r8152 *tp = usb_get_intfdata(intf); 4476 struct net_device *netdev; 4477 4478 if (!tp) 4479 return 0; 4480 4481 netdev = tp->netdev; 4482 if (!netif_running(netdev)) 4483 return 0; 4484 4485 netif_stop_queue(netdev); 4486 tasklet_disable(&tp->tx_tl); 4487 napi_disable(&tp->napi); 4488 clear_bit(WORK_ENABLE, &tp->flags); 4489 usb_kill_urb(tp->intr_urb); 4490 cancel_delayed_work_sync(&tp->schedule); 4491 if (netif_carrier_ok(netdev)) { 4492 mutex_lock(&tp->control); 4493 tp->rtl_ops.disable(tp); 4494 mutex_unlock(&tp->control); 4495 } 4496 4497 return 0; 4498 } 4499 4500 static int rtl8152_post_reset(struct usb_interface *intf) 4501 { 4502 struct r8152 *tp = usb_get_intfdata(intf); 4503 struct net_device *netdev; 4504 struct sockaddr sa; 4505 4506 if (!tp) 4507 return 0; 4508 4509 /* reset the MAC adddress in case of policy change */ 4510 if (determine_ethernet_addr(tp, &sa) >= 0) { 4511 rtnl_lock(); 4512 dev_set_mac_address (tp->netdev, &sa, NULL); 4513 rtnl_unlock(); 4514 } 4515 4516 netdev = tp->netdev; 4517 if (!netif_running(netdev)) 4518 return 0; 4519 4520 set_bit(WORK_ENABLE, &tp->flags); 4521 if (netif_carrier_ok(netdev)) { 4522 mutex_lock(&tp->control); 4523 tp->rtl_ops.enable(tp); 4524 rtl_start_rx(tp); 4525 _rtl8152_set_rx_mode(netdev); 4526 mutex_unlock(&tp->control); 4527 } 4528 4529 napi_enable(&tp->napi); 4530 tasklet_enable(&tp->tx_tl); 4531 netif_wake_queue(netdev); 4532 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 4533 4534 if (!list_empty(&tp->rx_done)) 4535 napi_schedule(&tp->napi); 4536 4537 return 0; 4538 } 4539 4540 static bool delay_autosuspend(struct r8152 *tp) 4541 { 4542 bool sw_linking = !!netif_carrier_ok(tp->netdev); 4543 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); 4544 4545 /* This means a linking change occurs and the driver doesn't detect it, 4546 * yet. If the driver has disabled tx/rx and hw is linking on, the 4547 * device wouldn't wake up by receiving any packet. 4548 */ 4549 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) 4550 return true; 4551 4552 /* If the linking down is occurred by nway, the device may miss the 4553 * linking change event. And it wouldn't wake when linking on. 4554 */ 4555 if (!sw_linking && tp->rtl_ops.in_nway(tp)) 4556 return true; 4557 else if (!skb_queue_empty(&tp->tx_queue)) 4558 return true; 4559 else 4560 return false; 4561 } 4562 4563 static int rtl8152_runtime_resume(struct r8152 *tp) 4564 { 4565 struct net_device *netdev = tp->netdev; 4566 4567 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4568 struct napi_struct *napi = &tp->napi; 4569 4570 tp->rtl_ops.autosuspend_en(tp, false); 4571 napi_disable(napi); 4572 set_bit(WORK_ENABLE, &tp->flags); 4573 4574 if (netif_carrier_ok(netdev)) { 4575 if (rtl8152_get_speed(tp) & LINK_STATUS) { 4576 rtl_start_rx(tp); 4577 } else { 4578 netif_carrier_off(netdev); 4579 tp->rtl_ops.disable(tp); 4580 netif_info(tp, link, netdev, "linking down\n"); 4581 } 4582 } 4583 4584 napi_enable(napi); 4585 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4586 smp_mb__after_atomic(); 4587 4588 if (!list_empty(&tp->rx_done)) 4589 napi_schedule(&tp->napi); 4590 4591 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4592 } else { 4593 if (netdev->flags & IFF_UP) 4594 tp->rtl_ops.autosuspend_en(tp, false); 4595 4596 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4597 } 4598 4599 return 0; 4600 } 4601 4602 static int rtl8152_system_resume(struct r8152 *tp) 4603 { 4604 struct net_device *netdev = tp->netdev; 4605 4606 netif_device_attach(netdev); 4607 4608 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4609 tp->rtl_ops.up(tp); 4610 netif_carrier_off(netdev); 4611 set_bit(WORK_ENABLE, &tp->flags); 4612 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4613 } 4614 4615 return 0; 4616 } 4617 4618 static int rtl8152_runtime_suspend(struct r8152 *tp) 4619 { 4620 struct net_device *netdev = tp->netdev; 4621 int ret = 0; 4622 4623 set_bit(SELECTIVE_SUSPEND, &tp->flags); 4624 smp_mb__after_atomic(); 4625 4626 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4627 u32 rcr = 0; 4628 4629 if (netif_carrier_ok(netdev)) { 4630 u32 ocp_data; 4631 4632 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 4633 ocp_data = rcr & ~RCR_ACPT_ALL; 4634 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 4635 rxdy_gated_en(tp, true); 4636 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 4637 PLA_OOB_CTRL); 4638 if (!(ocp_data & RXFIFO_EMPTY)) { 4639 rxdy_gated_en(tp, false); 4640 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4641 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4642 smp_mb__after_atomic(); 4643 ret = -EBUSY; 4644 goto out1; 4645 } 4646 } 4647 4648 clear_bit(WORK_ENABLE, &tp->flags); 4649 usb_kill_urb(tp->intr_urb); 4650 4651 tp->rtl_ops.autosuspend_en(tp, true); 4652 4653 if (netif_carrier_ok(netdev)) { 4654 struct napi_struct *napi = &tp->napi; 4655 4656 napi_disable(napi); 4657 rtl_stop_rx(tp); 4658 rxdy_gated_en(tp, false); 4659 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4660 napi_enable(napi); 4661 } 4662 4663 if (delay_autosuspend(tp)) { 4664 rtl8152_runtime_resume(tp); 4665 ret = -EBUSY; 4666 } 4667 } 4668 4669 out1: 4670 return ret; 4671 } 4672 4673 static int rtl8152_system_suspend(struct r8152 *tp) 4674 { 4675 struct net_device *netdev = tp->netdev; 4676 4677 netif_device_detach(netdev); 4678 4679 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4680 struct napi_struct *napi = &tp->napi; 4681 4682 clear_bit(WORK_ENABLE, &tp->flags); 4683 usb_kill_urb(tp->intr_urb); 4684 tasklet_disable(&tp->tx_tl); 4685 napi_disable(napi); 4686 cancel_delayed_work_sync(&tp->schedule); 4687 tp->rtl_ops.down(tp); 4688 napi_enable(napi); 4689 tasklet_enable(&tp->tx_tl); 4690 } 4691 4692 return 0; 4693 } 4694 4695 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 4696 { 4697 struct r8152 *tp = usb_get_intfdata(intf); 4698 int ret; 4699 4700 mutex_lock(&tp->control); 4701 4702 if (PMSG_IS_AUTO(message)) 4703 ret = rtl8152_runtime_suspend(tp); 4704 else 4705 ret = rtl8152_system_suspend(tp); 4706 4707 mutex_unlock(&tp->control); 4708 4709 return ret; 4710 } 4711 4712 static int rtl8152_resume(struct usb_interface *intf) 4713 { 4714 struct r8152 *tp = usb_get_intfdata(intf); 4715 int ret; 4716 4717 mutex_lock(&tp->control); 4718 4719 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) 4720 ret = rtl8152_runtime_resume(tp); 4721 else 4722 ret = rtl8152_system_resume(tp); 4723 4724 mutex_unlock(&tp->control); 4725 4726 return ret; 4727 } 4728 4729 static int rtl8152_reset_resume(struct usb_interface *intf) 4730 { 4731 struct r8152 *tp = usb_get_intfdata(intf); 4732 4733 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4734 mutex_lock(&tp->control); 4735 tp->rtl_ops.init(tp); 4736 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 4737 mutex_unlock(&tp->control); 4738 return rtl8152_resume(intf); 4739 } 4740 4741 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4742 { 4743 struct r8152 *tp = netdev_priv(dev); 4744 4745 if (usb_autopm_get_interface(tp->intf) < 0) 4746 return; 4747 4748 if (!rtl_can_wakeup(tp)) { 4749 wol->supported = 0; 4750 wol->wolopts = 0; 4751 } else { 4752 mutex_lock(&tp->control); 4753 wol->supported = WAKE_ANY; 4754 wol->wolopts = __rtl_get_wol(tp); 4755 mutex_unlock(&tp->control); 4756 } 4757 4758 usb_autopm_put_interface(tp->intf); 4759 } 4760 4761 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4762 { 4763 struct r8152 *tp = netdev_priv(dev); 4764 int ret; 4765 4766 if (!rtl_can_wakeup(tp)) 4767 return -EOPNOTSUPP; 4768 4769 if (wol->wolopts & ~WAKE_ANY) 4770 return -EINVAL; 4771 4772 ret = usb_autopm_get_interface(tp->intf); 4773 if (ret < 0) 4774 goto out_set_wol; 4775 4776 mutex_lock(&tp->control); 4777 4778 __rtl_set_wol(tp, wol->wolopts); 4779 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 4780 4781 mutex_unlock(&tp->control); 4782 4783 usb_autopm_put_interface(tp->intf); 4784 4785 out_set_wol: 4786 return ret; 4787 } 4788 4789 static u32 rtl8152_get_msglevel(struct net_device *dev) 4790 { 4791 struct r8152 *tp = netdev_priv(dev); 4792 4793 return tp->msg_enable; 4794 } 4795 4796 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 4797 { 4798 struct r8152 *tp = netdev_priv(dev); 4799 4800 tp->msg_enable = value; 4801 } 4802 4803 static void rtl8152_get_drvinfo(struct net_device *netdev, 4804 struct ethtool_drvinfo *info) 4805 { 4806 struct r8152 *tp = netdev_priv(netdev); 4807 4808 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 4809 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 4810 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 4811 } 4812 4813 static 4814 int rtl8152_get_link_ksettings(struct net_device *netdev, 4815 struct ethtool_link_ksettings *cmd) 4816 { 4817 struct r8152 *tp = netdev_priv(netdev); 4818 int ret; 4819 4820 if (!tp->mii.mdio_read) 4821 return -EOPNOTSUPP; 4822 4823 ret = usb_autopm_get_interface(tp->intf); 4824 if (ret < 0) 4825 goto out; 4826 4827 mutex_lock(&tp->control); 4828 4829 mii_ethtool_get_link_ksettings(&tp->mii, cmd); 4830 4831 mutex_unlock(&tp->control); 4832 4833 usb_autopm_put_interface(tp->intf); 4834 4835 out: 4836 return ret; 4837 } 4838 4839 static int rtl8152_set_link_ksettings(struct net_device *dev, 4840 const struct ethtool_link_ksettings *cmd) 4841 { 4842 struct r8152 *tp = netdev_priv(dev); 4843 int ret; 4844 4845 ret = usb_autopm_get_interface(tp->intf); 4846 if (ret < 0) 4847 goto out; 4848 4849 mutex_lock(&tp->control); 4850 4851 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, 4852 cmd->base.duplex); 4853 if (!ret) { 4854 tp->autoneg = cmd->base.autoneg; 4855 tp->speed = cmd->base.speed; 4856 tp->duplex = cmd->base.duplex; 4857 } 4858 4859 mutex_unlock(&tp->control); 4860 4861 usb_autopm_put_interface(tp->intf); 4862 4863 out: 4864 return ret; 4865 } 4866 4867 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 4868 "tx_packets", 4869 "rx_packets", 4870 "tx_errors", 4871 "rx_errors", 4872 "rx_missed", 4873 "align_errors", 4874 "tx_single_collisions", 4875 "tx_multi_collisions", 4876 "rx_unicast", 4877 "rx_broadcast", 4878 "rx_multicast", 4879 "tx_aborted", 4880 "tx_underrun", 4881 }; 4882 4883 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 4884 { 4885 switch (sset) { 4886 case ETH_SS_STATS: 4887 return ARRAY_SIZE(rtl8152_gstrings); 4888 default: 4889 return -EOPNOTSUPP; 4890 } 4891 } 4892 4893 static void rtl8152_get_ethtool_stats(struct net_device *dev, 4894 struct ethtool_stats *stats, u64 *data) 4895 { 4896 struct r8152 *tp = netdev_priv(dev); 4897 struct tally_counter tally; 4898 4899 if (usb_autopm_get_interface(tp->intf) < 0) 4900 return; 4901 4902 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 4903 4904 usb_autopm_put_interface(tp->intf); 4905 4906 data[0] = le64_to_cpu(tally.tx_packets); 4907 data[1] = le64_to_cpu(tally.rx_packets); 4908 data[2] = le64_to_cpu(tally.tx_errors); 4909 data[3] = le32_to_cpu(tally.rx_errors); 4910 data[4] = le16_to_cpu(tally.rx_missed); 4911 data[5] = le16_to_cpu(tally.align_errors); 4912 data[6] = le32_to_cpu(tally.tx_one_collision); 4913 data[7] = le32_to_cpu(tally.tx_multi_collision); 4914 data[8] = le64_to_cpu(tally.rx_unicast); 4915 data[9] = le64_to_cpu(tally.rx_broadcast); 4916 data[10] = le32_to_cpu(tally.rx_multicast); 4917 data[11] = le16_to_cpu(tally.tx_aborted); 4918 data[12] = le16_to_cpu(tally.tx_underrun); 4919 } 4920 4921 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4922 { 4923 switch (stringset) { 4924 case ETH_SS_STATS: 4925 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 4926 break; 4927 } 4928 } 4929 4930 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 4931 { 4932 u32 lp, adv, supported = 0; 4933 u16 val; 4934 4935 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 4936 supported = mmd_eee_cap_to_ethtool_sup_t(val); 4937 4938 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 4939 adv = mmd_eee_adv_to_ethtool_adv_t(val); 4940 4941 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 4942 lp = mmd_eee_adv_to_ethtool_adv_t(val); 4943 4944 eee->eee_enabled = tp->eee_en; 4945 eee->eee_active = !!(supported & adv & lp); 4946 eee->supported = supported; 4947 eee->advertised = tp->eee_adv; 4948 eee->lp_advertised = lp; 4949 4950 return 0; 4951 } 4952 4953 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4954 { 4955 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4956 4957 tp->eee_en = eee->eee_enabled; 4958 tp->eee_adv = val; 4959 4960 rtl_eee_enable(tp, tp->eee_en); 4961 4962 return 0; 4963 } 4964 4965 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 4966 { 4967 u32 lp, adv, supported = 0; 4968 u16 val; 4969 4970 val = ocp_reg_read(tp, OCP_EEE_ABLE); 4971 supported = mmd_eee_cap_to_ethtool_sup_t(val); 4972 4973 val = ocp_reg_read(tp, OCP_EEE_ADV); 4974 adv = mmd_eee_adv_to_ethtool_adv_t(val); 4975 4976 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 4977 lp = mmd_eee_adv_to_ethtool_adv_t(val); 4978 4979 eee->eee_enabled = tp->eee_en; 4980 eee->eee_active = !!(supported & adv & lp); 4981 eee->supported = supported; 4982 eee->advertised = tp->eee_adv; 4983 eee->lp_advertised = lp; 4984 4985 return 0; 4986 } 4987 4988 static int 4989 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) 4990 { 4991 struct r8152 *tp = netdev_priv(net); 4992 int ret; 4993 4994 ret = usb_autopm_get_interface(tp->intf); 4995 if (ret < 0) 4996 goto out; 4997 4998 mutex_lock(&tp->control); 4999 5000 ret = tp->rtl_ops.eee_get(tp, edata); 5001 5002 mutex_unlock(&tp->control); 5003 5004 usb_autopm_put_interface(tp->intf); 5005 5006 out: 5007 return ret; 5008 } 5009 5010 static int 5011 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) 5012 { 5013 struct r8152 *tp = netdev_priv(net); 5014 int ret; 5015 5016 ret = usb_autopm_get_interface(tp->intf); 5017 if (ret < 0) 5018 goto out; 5019 5020 mutex_lock(&tp->control); 5021 5022 ret = tp->rtl_ops.eee_set(tp, edata); 5023 if (!ret) 5024 ret = mii_nway_restart(&tp->mii); 5025 5026 mutex_unlock(&tp->control); 5027 5028 usb_autopm_put_interface(tp->intf); 5029 5030 out: 5031 return ret; 5032 } 5033 5034 static int rtl8152_nway_reset(struct net_device *dev) 5035 { 5036 struct r8152 *tp = netdev_priv(dev); 5037 int ret; 5038 5039 ret = usb_autopm_get_interface(tp->intf); 5040 if (ret < 0) 5041 goto out; 5042 5043 mutex_lock(&tp->control); 5044 5045 ret = mii_nway_restart(&tp->mii); 5046 5047 mutex_unlock(&tp->control); 5048 5049 usb_autopm_put_interface(tp->intf); 5050 5051 out: 5052 return ret; 5053 } 5054 5055 static int rtl8152_get_coalesce(struct net_device *netdev, 5056 struct ethtool_coalesce *coalesce) 5057 { 5058 struct r8152 *tp = netdev_priv(netdev); 5059 5060 switch (tp->version) { 5061 case RTL_VER_01: 5062 case RTL_VER_02: 5063 case RTL_VER_07: 5064 return -EOPNOTSUPP; 5065 default: 5066 break; 5067 } 5068 5069 coalesce->rx_coalesce_usecs = tp->coalesce; 5070 5071 return 0; 5072 } 5073 5074 static int rtl8152_set_coalesce(struct net_device *netdev, 5075 struct ethtool_coalesce *coalesce) 5076 { 5077 struct r8152 *tp = netdev_priv(netdev); 5078 int ret; 5079 5080 switch (tp->version) { 5081 case RTL_VER_01: 5082 case RTL_VER_02: 5083 case RTL_VER_07: 5084 return -EOPNOTSUPP; 5085 default: 5086 break; 5087 } 5088 5089 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) 5090 return -EINVAL; 5091 5092 ret = usb_autopm_get_interface(tp->intf); 5093 if (ret < 0) 5094 return ret; 5095 5096 mutex_lock(&tp->control); 5097 5098 if (tp->coalesce != coalesce->rx_coalesce_usecs) { 5099 tp->coalesce = coalesce->rx_coalesce_usecs; 5100 5101 if (netif_running(netdev) && netif_carrier_ok(netdev)) { 5102 netif_stop_queue(netdev); 5103 napi_disable(&tp->napi); 5104 tp->rtl_ops.disable(tp); 5105 tp->rtl_ops.enable(tp); 5106 rtl_start_rx(tp); 5107 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 5108 _rtl8152_set_rx_mode(netdev); 5109 napi_enable(&tp->napi); 5110 netif_wake_queue(netdev); 5111 } 5112 } 5113 5114 mutex_unlock(&tp->control); 5115 5116 usb_autopm_put_interface(tp->intf); 5117 5118 return ret; 5119 } 5120 5121 static int rtl8152_get_tunable(struct net_device *netdev, 5122 const struct ethtool_tunable *tunable, void *d) 5123 { 5124 struct r8152 *tp = netdev_priv(netdev); 5125 5126 switch (tunable->id) { 5127 case ETHTOOL_RX_COPYBREAK: 5128 *(u32 *)d = tp->rx_copybreak; 5129 break; 5130 default: 5131 return -EOPNOTSUPP; 5132 } 5133 5134 return 0; 5135 } 5136 5137 static int rtl8152_set_tunable(struct net_device *netdev, 5138 const struct ethtool_tunable *tunable, 5139 const void *d) 5140 { 5141 struct r8152 *tp = netdev_priv(netdev); 5142 u32 val; 5143 5144 switch (tunable->id) { 5145 case ETHTOOL_RX_COPYBREAK: 5146 val = *(u32 *)d; 5147 if (val < ETH_ZLEN) { 5148 netif_err(tp, rx_err, netdev, 5149 "Invalid rx copy break value\n"); 5150 return -EINVAL; 5151 } 5152 5153 if (tp->rx_copybreak != val) { 5154 napi_disable(&tp->napi); 5155 tp->rx_copybreak = val; 5156 napi_enable(&tp->napi); 5157 } 5158 break; 5159 default: 5160 return -EOPNOTSUPP; 5161 } 5162 5163 return 0; 5164 } 5165 5166 static void rtl8152_get_ringparam(struct net_device *netdev, 5167 struct ethtool_ringparam *ring) 5168 { 5169 struct r8152 *tp = netdev_priv(netdev); 5170 5171 ring->rx_max_pending = RTL8152_RX_MAX_PENDING; 5172 ring->rx_pending = tp->rx_pending; 5173 } 5174 5175 static int rtl8152_set_ringparam(struct net_device *netdev, 5176 struct ethtool_ringparam *ring) 5177 { 5178 struct r8152 *tp = netdev_priv(netdev); 5179 5180 if (ring->rx_pending < (RTL8152_MAX_RX * 2)) 5181 return -EINVAL; 5182 5183 if (tp->rx_pending != ring->rx_pending) { 5184 napi_disable(&tp->napi); 5185 tp->rx_pending = ring->rx_pending; 5186 napi_enable(&tp->napi); 5187 } 5188 5189 return 0; 5190 } 5191 5192 static const struct ethtool_ops ops = { 5193 .get_drvinfo = rtl8152_get_drvinfo, 5194 .get_link = ethtool_op_get_link, 5195 .nway_reset = rtl8152_nway_reset, 5196 .get_msglevel = rtl8152_get_msglevel, 5197 .set_msglevel = rtl8152_set_msglevel, 5198 .get_wol = rtl8152_get_wol, 5199 .set_wol = rtl8152_set_wol, 5200 .get_strings = rtl8152_get_strings, 5201 .get_sset_count = rtl8152_get_sset_count, 5202 .get_ethtool_stats = rtl8152_get_ethtool_stats, 5203 .get_coalesce = rtl8152_get_coalesce, 5204 .set_coalesce = rtl8152_set_coalesce, 5205 .get_eee = rtl_ethtool_get_eee, 5206 .set_eee = rtl_ethtool_set_eee, 5207 .get_link_ksettings = rtl8152_get_link_ksettings, 5208 .set_link_ksettings = rtl8152_set_link_ksettings, 5209 .get_tunable = rtl8152_get_tunable, 5210 .set_tunable = rtl8152_set_tunable, 5211 .get_ringparam = rtl8152_get_ringparam, 5212 .set_ringparam = rtl8152_set_ringparam, 5213 }; 5214 5215 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 5216 { 5217 struct r8152 *tp = netdev_priv(netdev); 5218 struct mii_ioctl_data *data = if_mii(rq); 5219 int res; 5220 5221 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5222 return -ENODEV; 5223 5224 res = usb_autopm_get_interface(tp->intf); 5225 if (res < 0) 5226 goto out; 5227 5228 switch (cmd) { 5229 case SIOCGMIIPHY: 5230 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 5231 break; 5232 5233 case SIOCGMIIREG: 5234 mutex_lock(&tp->control); 5235 data->val_out = r8152_mdio_read(tp, data->reg_num); 5236 mutex_unlock(&tp->control); 5237 break; 5238 5239 case SIOCSMIIREG: 5240 if (!capable(CAP_NET_ADMIN)) { 5241 res = -EPERM; 5242 break; 5243 } 5244 mutex_lock(&tp->control); 5245 r8152_mdio_write(tp, data->reg_num, data->val_in); 5246 mutex_unlock(&tp->control); 5247 break; 5248 5249 default: 5250 res = -EOPNOTSUPP; 5251 } 5252 5253 usb_autopm_put_interface(tp->intf); 5254 5255 out: 5256 return res; 5257 } 5258 5259 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 5260 { 5261 struct r8152 *tp = netdev_priv(dev); 5262 int ret; 5263 5264 switch (tp->version) { 5265 case RTL_VER_01: 5266 case RTL_VER_02: 5267 case RTL_VER_07: 5268 dev->mtu = new_mtu; 5269 return 0; 5270 default: 5271 break; 5272 } 5273 5274 ret = usb_autopm_get_interface(tp->intf); 5275 if (ret < 0) 5276 return ret; 5277 5278 mutex_lock(&tp->control); 5279 5280 dev->mtu = new_mtu; 5281 5282 if (netif_running(dev)) { 5283 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 5284 5285 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms); 5286 5287 if (netif_carrier_ok(dev)) 5288 r8153_set_rx_early_size(tp); 5289 } 5290 5291 mutex_unlock(&tp->control); 5292 5293 usb_autopm_put_interface(tp->intf); 5294 5295 return ret; 5296 } 5297 5298 static const struct net_device_ops rtl8152_netdev_ops = { 5299 .ndo_open = rtl8152_open, 5300 .ndo_stop = rtl8152_close, 5301 .ndo_do_ioctl = rtl8152_ioctl, 5302 .ndo_start_xmit = rtl8152_start_xmit, 5303 .ndo_tx_timeout = rtl8152_tx_timeout, 5304 .ndo_set_features = rtl8152_set_features, 5305 .ndo_set_rx_mode = rtl8152_set_rx_mode, 5306 .ndo_set_mac_address = rtl8152_set_mac_address, 5307 .ndo_change_mtu = rtl8152_change_mtu, 5308 .ndo_validate_addr = eth_validate_addr, 5309 .ndo_features_check = rtl8152_features_check, 5310 }; 5311 5312 static void rtl8152_unload(struct r8152 *tp) 5313 { 5314 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5315 return; 5316 5317 if (tp->version != RTL_VER_01) 5318 r8152_power_cut_en(tp, true); 5319 } 5320 5321 static void rtl8153_unload(struct r8152 *tp) 5322 { 5323 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5324 return; 5325 5326 r8153_power_cut_en(tp, false); 5327 } 5328 5329 static void rtl8153b_unload(struct r8152 *tp) 5330 { 5331 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5332 return; 5333 5334 r8153b_power_cut_en(tp, false); 5335 } 5336 5337 static int rtl_ops_init(struct r8152 *tp) 5338 { 5339 struct rtl_ops *ops = &tp->rtl_ops; 5340 int ret = 0; 5341 5342 switch (tp->version) { 5343 case RTL_VER_01: 5344 case RTL_VER_02: 5345 case RTL_VER_07: 5346 ops->init = r8152b_init; 5347 ops->enable = rtl8152_enable; 5348 ops->disable = rtl8152_disable; 5349 ops->up = rtl8152_up; 5350 ops->down = rtl8152_down; 5351 ops->unload = rtl8152_unload; 5352 ops->eee_get = r8152_get_eee; 5353 ops->eee_set = r8152_set_eee; 5354 ops->in_nway = rtl8152_in_nway; 5355 ops->hw_phy_cfg = r8152b_hw_phy_cfg; 5356 ops->autosuspend_en = rtl_runtime_suspend_enable; 5357 tp->rx_buf_sz = 16 * 1024; 5358 tp->eee_en = true; 5359 tp->eee_adv = MDIO_EEE_100TX; 5360 break; 5361 5362 case RTL_VER_03: 5363 case RTL_VER_04: 5364 case RTL_VER_05: 5365 case RTL_VER_06: 5366 ops->init = r8153_init; 5367 ops->enable = rtl8153_enable; 5368 ops->disable = rtl8153_disable; 5369 ops->up = rtl8153_up; 5370 ops->down = rtl8153_down; 5371 ops->unload = rtl8153_unload; 5372 ops->eee_get = r8153_get_eee; 5373 ops->eee_set = r8152_set_eee; 5374 ops->in_nway = rtl8153_in_nway; 5375 ops->hw_phy_cfg = r8153_hw_phy_cfg; 5376 ops->autosuspend_en = rtl8153_runtime_enable; 5377 tp->rx_buf_sz = 32 * 1024; 5378 tp->eee_en = true; 5379 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 5380 break; 5381 5382 case RTL_VER_08: 5383 case RTL_VER_09: 5384 ops->init = r8153b_init; 5385 ops->enable = rtl8153_enable; 5386 ops->disable = rtl8153b_disable; 5387 ops->up = rtl8153b_up; 5388 ops->down = rtl8153b_down; 5389 ops->unload = rtl8153b_unload; 5390 ops->eee_get = r8153_get_eee; 5391 ops->eee_set = r8152_set_eee; 5392 ops->in_nway = rtl8153_in_nway; 5393 ops->hw_phy_cfg = r8153b_hw_phy_cfg; 5394 ops->autosuspend_en = rtl8153b_runtime_enable; 5395 tp->rx_buf_sz = 32 * 1024; 5396 tp->eee_en = true; 5397 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 5398 break; 5399 5400 default: 5401 ret = -ENODEV; 5402 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 5403 break; 5404 } 5405 5406 return ret; 5407 } 5408 5409 static u8 rtl_get_version(struct usb_interface *intf) 5410 { 5411 struct usb_device *udev = interface_to_usbdev(intf); 5412 u32 ocp_data = 0; 5413 __le32 *tmp; 5414 u8 version; 5415 int ret; 5416 5417 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); 5418 if (!tmp) 5419 return 0; 5420 5421 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 5422 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 5423 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500); 5424 if (ret > 0) 5425 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK; 5426 5427 kfree(tmp); 5428 5429 switch (ocp_data) { 5430 case 0x4c00: 5431 version = RTL_VER_01; 5432 break; 5433 case 0x4c10: 5434 version = RTL_VER_02; 5435 break; 5436 case 0x5c00: 5437 version = RTL_VER_03; 5438 break; 5439 case 0x5c10: 5440 version = RTL_VER_04; 5441 break; 5442 case 0x5c20: 5443 version = RTL_VER_05; 5444 break; 5445 case 0x5c30: 5446 version = RTL_VER_06; 5447 break; 5448 case 0x4800: 5449 version = RTL_VER_07; 5450 break; 5451 case 0x6000: 5452 version = RTL_VER_08; 5453 break; 5454 case 0x6010: 5455 version = RTL_VER_09; 5456 break; 5457 default: 5458 version = RTL_VER_UNKNOWN; 5459 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); 5460 break; 5461 } 5462 5463 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); 5464 5465 return version; 5466 } 5467 5468 static int rtl8152_probe(struct usb_interface *intf, 5469 const struct usb_device_id *id) 5470 { 5471 struct usb_device *udev = interface_to_usbdev(intf); 5472 u8 version = rtl_get_version(intf); 5473 struct r8152 *tp; 5474 struct net_device *netdev; 5475 int ret; 5476 5477 if (version == RTL_VER_UNKNOWN) 5478 return -ENODEV; 5479 5480 if (udev->actconfig->desc.bConfigurationValue != 1) { 5481 usb_driver_set_configuration(udev, 1); 5482 return -ENODEV; 5483 } 5484 5485 usb_reset_device(udev); 5486 netdev = alloc_etherdev(sizeof(struct r8152)); 5487 if (!netdev) { 5488 dev_err(&intf->dev, "Out of memory\n"); 5489 return -ENOMEM; 5490 } 5491 5492 SET_NETDEV_DEV(netdev, &intf->dev); 5493 tp = netdev_priv(netdev); 5494 tp->msg_enable = 0x7FFF; 5495 5496 tp->udev = udev; 5497 tp->netdev = netdev; 5498 tp->intf = intf; 5499 tp->version = version; 5500 5501 switch (version) { 5502 case RTL_VER_01: 5503 case RTL_VER_02: 5504 case RTL_VER_07: 5505 tp->mii.supports_gmii = 0; 5506 break; 5507 default: 5508 tp->mii.supports_gmii = 1; 5509 break; 5510 } 5511 5512 ret = rtl_ops_init(tp); 5513 if (ret) 5514 goto out; 5515 5516 mutex_init(&tp->control); 5517 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 5518 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); 5519 tasklet_init(&tp->tx_tl, bottom_half, (unsigned long)tp); 5520 tasklet_disable(&tp->tx_tl); 5521 5522 netdev->netdev_ops = &rtl8152_netdev_ops; 5523 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 5524 5525 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5526 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 5527 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 5528 NETIF_F_HW_VLAN_CTAG_TX; 5529 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5530 NETIF_F_TSO | NETIF_F_FRAGLIST | 5531 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 5532 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; 5533 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 5534 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 5535 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 5536 5537 if (tp->version == RTL_VER_01) { 5538 netdev->features &= ~NETIF_F_RXCSUM; 5539 netdev->hw_features &= ~NETIF_F_RXCSUM; 5540 } 5541 5542 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial && 5543 (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) { 5544 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation"); 5545 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags); 5546 } 5547 5548 netdev->ethtool_ops = &ops; 5549 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 5550 5551 /* MTU range: 68 - 1500 or 9194 */ 5552 netdev->min_mtu = ETH_MIN_MTU; 5553 switch (tp->version) { 5554 case RTL_VER_01: 5555 case RTL_VER_02: 5556 netdev->max_mtu = ETH_DATA_LEN; 5557 break; 5558 default: 5559 netdev->max_mtu = RTL8153_MAX_MTU; 5560 break; 5561 } 5562 5563 tp->mii.dev = netdev; 5564 tp->mii.mdio_read = read_mii_word; 5565 tp->mii.mdio_write = write_mii_word; 5566 tp->mii.phy_id_mask = 0x3f; 5567 tp->mii.reg_num_mask = 0x1f; 5568 tp->mii.phy_id = R8152_PHY_ID; 5569 5570 tp->autoneg = AUTONEG_ENABLE; 5571 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100; 5572 tp->duplex = DUPLEX_FULL; 5573 5574 tp->rx_copybreak = RTL8152_RXFG_HEADSZ; 5575 tp->rx_pending = 10 * RTL8152_MAX_RX; 5576 5577 intf->needs_remote_wakeup = 1; 5578 5579 tp->rtl_ops.init(tp); 5580 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 5581 set_ethernet_addr(tp); 5582 5583 usb_set_intfdata(intf, tp); 5584 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); 5585 5586 ret = register_netdev(netdev); 5587 if (ret != 0) { 5588 netif_err(tp, probe, netdev, "couldn't register the device\n"); 5589 goto out1; 5590 } 5591 5592 if (!rtl_can_wakeup(tp)) 5593 __rtl_set_wol(tp, 0); 5594 5595 tp->saved_wolopts = __rtl_get_wol(tp); 5596 if (tp->saved_wolopts) 5597 device_set_wakeup_enable(&udev->dev, true); 5598 else 5599 device_set_wakeup_enable(&udev->dev, false); 5600 5601 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 5602 5603 return 0; 5604 5605 out1: 5606 tasklet_kill(&tp->tx_tl); 5607 usb_set_intfdata(intf, NULL); 5608 out: 5609 free_netdev(netdev); 5610 return ret; 5611 } 5612 5613 static void rtl8152_disconnect(struct usb_interface *intf) 5614 { 5615 struct r8152 *tp = usb_get_intfdata(intf); 5616 5617 usb_set_intfdata(intf, NULL); 5618 if (tp) { 5619 rtl_set_unplug(tp); 5620 5621 unregister_netdev(tp->netdev); 5622 tasklet_kill(&tp->tx_tl); 5623 cancel_delayed_work_sync(&tp->hw_phy_work); 5624 tp->rtl_ops.unload(tp); 5625 free_netdev(tp->netdev); 5626 } 5627 } 5628 5629 #define REALTEK_USB_DEVICE(vend, prod) \ 5630 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ 5631 USB_DEVICE_ID_MATCH_INT_CLASS, \ 5632 .idVendor = (vend), \ 5633 .idProduct = (prod), \ 5634 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ 5635 }, \ 5636 { \ 5637 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ 5638 USB_DEVICE_ID_MATCH_DEVICE, \ 5639 .idVendor = (vend), \ 5640 .idProduct = (prod), \ 5641 .bInterfaceClass = USB_CLASS_COMM, \ 5642 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ 5643 .bInterfaceProtocol = USB_CDC_PROTO_NONE 5644 5645 /* table of devices that work with this driver */ 5646 static const struct usb_device_id rtl8152_table[] = { 5647 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)}, 5648 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, 5649 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, 5650 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)}, 5651 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)}, 5652 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, 5653 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, 5654 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)}, 5655 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)}, 5656 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, 5657 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)}, 5658 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)}, 5659 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)}, 5660 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, 5661 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)}, 5662 {} 5663 }; 5664 5665 MODULE_DEVICE_TABLE(usb, rtl8152_table); 5666 5667 static struct usb_driver rtl8152_driver = { 5668 .name = MODULENAME, 5669 .id_table = rtl8152_table, 5670 .probe = rtl8152_probe, 5671 .disconnect = rtl8152_disconnect, 5672 .suspend = rtl8152_suspend, 5673 .resume = rtl8152_resume, 5674 .reset_resume = rtl8152_reset_resume, 5675 .pre_reset = rtl8152_pre_reset, 5676 .post_reset = rtl8152_post_reset, 5677 .supports_autosuspend = 1, 5678 .disable_hub_initiated_lpm = 1, 5679 }; 5680 5681 module_usb_driver(rtl8152_driver); 5682 5683 MODULE_AUTHOR(DRIVER_AUTHOR); 5684 MODULE_DESCRIPTION(DRIVER_DESC); 5685 MODULE_LICENSE("GPL"); 5686 MODULE_VERSION(DRIVER_VERSION); 5687