1 /* 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2 as published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/signal.h> 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/usb.h> 18 #include <linux/crc32.h> 19 #include <linux/if_vlan.h> 20 #include <linux/uaccess.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include <net/ip6_checksum.h> 25 #include <uapi/linux/mdio.h> 26 #include <linux/mdio.h> 27 #include <linux/usb/cdc.h> 28 #include <linux/suspend.h> 29 #include <linux/acpi.h> 30 31 /* Information for net-next */ 32 #define NETNEXT_VERSION "09" 33 34 /* Information for net */ 35 #define NET_VERSION "9" 36 37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION 38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 40 #define MODULENAME "r8152" 41 42 #define R8152_PHY_ID 32 43 44 #define PLA_IDR 0xc000 45 #define PLA_RCR 0xc010 46 #define PLA_RMS 0xc016 47 #define PLA_RXFIFO_CTRL0 0xc0a0 48 #define PLA_RXFIFO_CTRL1 0xc0a4 49 #define PLA_RXFIFO_CTRL2 0xc0a8 50 #define PLA_DMY_REG0 0xc0b0 51 #define PLA_FMC 0xc0b4 52 #define PLA_CFG_WOL 0xc0b6 53 #define PLA_TEREDO_CFG 0xc0bc 54 #define PLA_TEREDO_WAKE_BASE 0xc0c4 55 #define PLA_MAR 0xcd00 56 #define PLA_BACKUP 0xd000 57 #define PAL_BDC_CR 0xd1a0 58 #define PLA_TEREDO_TIMER 0xd2cc 59 #define PLA_REALWOW_TIMER 0xd2e8 60 #define PLA_EFUSE_DATA 0xdd00 61 #define PLA_EFUSE_CMD 0xdd02 62 #define PLA_LEDSEL 0xdd90 63 #define PLA_LED_FEATURE 0xdd92 64 #define PLA_PHYAR 0xde00 65 #define PLA_BOOT_CTRL 0xe004 66 #define PLA_GPHY_INTR_IMR 0xe022 67 #define PLA_EEE_CR 0xe040 68 #define PLA_EEEP_CR 0xe080 69 #define PLA_MAC_PWR_CTRL 0xe0c0 70 #define PLA_MAC_PWR_CTRL2 0xe0ca 71 #define PLA_MAC_PWR_CTRL3 0xe0cc 72 #define PLA_MAC_PWR_CTRL4 0xe0ce 73 #define PLA_WDT6_CTRL 0xe428 74 #define PLA_TCR0 0xe610 75 #define PLA_TCR1 0xe612 76 #define PLA_MTPS 0xe615 77 #define PLA_TXFIFO_CTRL 0xe618 78 #define PLA_RSTTALLY 0xe800 79 #define PLA_CR 0xe813 80 #define PLA_CRWECR 0xe81c 81 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 82 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 83 #define PLA_CONFIG5 0xe822 84 #define PLA_PHY_PWR 0xe84c 85 #define PLA_OOB_CTRL 0xe84f 86 #define PLA_CPCR 0xe854 87 #define PLA_MISC_0 0xe858 88 #define PLA_MISC_1 0xe85a 89 #define PLA_OCP_GPHY_BASE 0xe86c 90 #define PLA_TALLYCNT 0xe890 91 #define PLA_SFF_STS_7 0xe8de 92 #define PLA_PHYSTATUS 0xe908 93 #define PLA_BP_BA 0xfc26 94 #define PLA_BP_0 0xfc28 95 #define PLA_BP_1 0xfc2a 96 #define PLA_BP_2 0xfc2c 97 #define PLA_BP_3 0xfc2e 98 #define PLA_BP_4 0xfc30 99 #define PLA_BP_5 0xfc32 100 #define PLA_BP_6 0xfc34 101 #define PLA_BP_7 0xfc36 102 #define PLA_BP_EN 0xfc38 103 104 #define USB_USB2PHY 0xb41e 105 #define USB_SSPHYLINK2 0xb428 106 #define USB_U2P3_CTRL 0xb460 107 #define USB_CSR_DUMMY1 0xb464 108 #define USB_CSR_DUMMY2 0xb466 109 #define USB_DEV_STAT 0xb808 110 #define USB_CONNECT_TIMER 0xcbf8 111 #define USB_MSC_TIMER 0xcbfc 112 #define USB_BURST_SIZE 0xcfc0 113 #define USB_LPM_CONFIG 0xcfd8 114 #define USB_USB_CTRL 0xd406 115 #define USB_PHY_CTRL 0xd408 116 #define USB_TX_AGG 0xd40a 117 #define USB_RX_BUF_TH 0xd40c 118 #define USB_USB_TIMER 0xd428 119 #define USB_RX_EARLY_TIMEOUT 0xd42c 120 #define USB_RX_EARLY_SIZE 0xd42e 121 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ 122 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ 123 #define USB_TX_DMA 0xd434 124 #define USB_UPT_RXDMA_OWN 0xd437 125 #define USB_TOLERANCE 0xd490 126 #define USB_LPM_CTRL 0xd41a 127 #define USB_BMU_RESET 0xd4b0 128 #define USB_U1U2_TIMER 0xd4da 129 #define USB_UPS_CTRL 0xd800 130 #define USB_POWER_CUT 0xd80a 131 #define USB_MISC_0 0xd81a 132 #define USB_AFE_CTRL2 0xd824 133 #define USB_UPS_CFG 0xd842 134 #define USB_UPS_FLAGS 0xd848 135 #define USB_WDT11_CTRL 0xe43c 136 #define USB_BP_BA 0xfc26 137 #define USB_BP_0 0xfc28 138 #define USB_BP_1 0xfc2a 139 #define USB_BP_2 0xfc2c 140 #define USB_BP_3 0xfc2e 141 #define USB_BP_4 0xfc30 142 #define USB_BP_5 0xfc32 143 #define USB_BP_6 0xfc34 144 #define USB_BP_7 0xfc36 145 #define USB_BP_EN 0xfc38 146 #define USB_BP_8 0xfc38 147 #define USB_BP_9 0xfc3a 148 #define USB_BP_10 0xfc3c 149 #define USB_BP_11 0xfc3e 150 #define USB_BP_12 0xfc40 151 #define USB_BP_13 0xfc42 152 #define USB_BP_14 0xfc44 153 #define USB_BP_15 0xfc46 154 #define USB_BP2_EN 0xfc48 155 156 /* OCP Registers */ 157 #define OCP_ALDPS_CONFIG 0x2010 158 #define OCP_EEE_CONFIG1 0x2080 159 #define OCP_EEE_CONFIG2 0x2092 160 #define OCP_EEE_CONFIG3 0x2094 161 #define OCP_BASE_MII 0xa400 162 #define OCP_EEE_AR 0xa41a 163 #define OCP_EEE_DATA 0xa41c 164 #define OCP_PHY_STATUS 0xa420 165 #define OCP_NCTL_CFG 0xa42c 166 #define OCP_POWER_CFG 0xa430 167 #define OCP_EEE_CFG 0xa432 168 #define OCP_SRAM_ADDR 0xa436 169 #define OCP_SRAM_DATA 0xa438 170 #define OCP_DOWN_SPEED 0xa442 171 #define OCP_EEE_ABLE 0xa5c4 172 #define OCP_EEE_ADV 0xa5d0 173 #define OCP_EEE_LPABLE 0xa5d2 174 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ 175 #define OCP_PHY_PATCH_STAT 0xb800 176 #define OCP_PHY_PATCH_CMD 0xb820 177 #define OCP_ADC_IOFFSET 0xbcfc 178 #define OCP_ADC_CFG 0xbc06 179 #define OCP_SYSCLK_CFG 0xc416 180 181 /* SRAM Register */ 182 #define SRAM_GREEN_CFG 0x8011 183 #define SRAM_LPF_CFG 0x8012 184 #define SRAM_10M_AMP1 0x8080 185 #define SRAM_10M_AMP2 0x8082 186 #define SRAM_IMPEDANCE 0x8084 187 188 /* PLA_RCR */ 189 #define RCR_AAP 0x00000001 190 #define RCR_APM 0x00000002 191 #define RCR_AM 0x00000004 192 #define RCR_AB 0x00000008 193 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 194 195 /* PLA_RXFIFO_CTRL0 */ 196 #define RXFIFO_THR1_NORMAL 0x00080002 197 #define RXFIFO_THR1_OOB 0x01800003 198 199 /* PLA_RXFIFO_CTRL1 */ 200 #define RXFIFO_THR2_FULL 0x00000060 201 #define RXFIFO_THR2_HIGH 0x00000038 202 #define RXFIFO_THR2_OOB 0x0000004a 203 #define RXFIFO_THR2_NORMAL 0x00a0 204 205 /* PLA_RXFIFO_CTRL2 */ 206 #define RXFIFO_THR3_FULL 0x00000078 207 #define RXFIFO_THR3_HIGH 0x00000048 208 #define RXFIFO_THR3_OOB 0x0000005a 209 #define RXFIFO_THR3_NORMAL 0x0110 210 211 /* PLA_TXFIFO_CTRL */ 212 #define TXFIFO_THR_NORMAL 0x00400008 213 #define TXFIFO_THR_NORMAL2 0x01000008 214 215 /* PLA_DMY_REG0 */ 216 #define ECM_ALDPS 0x0002 217 218 /* PLA_FMC */ 219 #define FMC_FCR_MCU_EN 0x0001 220 221 /* PLA_EEEP_CR */ 222 #define EEEP_CR_EEEP_TX 0x0002 223 224 /* PLA_WDT6_CTRL */ 225 #define WDT6_SET_MODE 0x0010 226 227 /* PLA_TCR0 */ 228 #define TCR0_TX_EMPTY 0x0800 229 #define TCR0_AUTO_FIFO 0x0080 230 231 /* PLA_TCR1 */ 232 #define VERSION_MASK 0x7cf0 233 234 /* PLA_MTPS */ 235 #define MTPS_JUMBO (12 * 1024 / 64) 236 #define MTPS_DEFAULT (6 * 1024 / 64) 237 238 /* PLA_RSTTALLY */ 239 #define TALLY_RESET 0x0001 240 241 /* PLA_CR */ 242 #define CR_RST 0x10 243 #define CR_RE 0x08 244 #define CR_TE 0x04 245 246 /* PLA_CRWECR */ 247 #define CRWECR_NORAML 0x00 248 #define CRWECR_CONFIG 0xc0 249 250 /* PLA_OOB_CTRL */ 251 #define NOW_IS_OOB 0x80 252 #define TXFIFO_EMPTY 0x20 253 #define RXFIFO_EMPTY 0x10 254 #define LINK_LIST_READY 0x02 255 #define DIS_MCU_CLROOB 0x01 256 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 257 258 /* PLA_MISC_1 */ 259 #define RXDY_GATED_EN 0x0008 260 261 /* PLA_SFF_STS_7 */ 262 #define RE_INIT_LL 0x8000 263 #define MCU_BORW_EN 0x4000 264 265 /* PLA_CPCR */ 266 #define CPCR_RX_VLAN 0x0040 267 268 /* PLA_CFG_WOL */ 269 #define MAGIC_EN 0x0001 270 271 /* PLA_TEREDO_CFG */ 272 #define TEREDO_SEL 0x8000 273 #define TEREDO_WAKE_MASK 0x7f00 274 #define TEREDO_RS_EVENT_MASK 0x00fe 275 #define OOB_TEREDO_EN 0x0001 276 277 /* PAL_BDC_CR */ 278 #define ALDPS_PROXY_MODE 0x0001 279 280 /* PLA_EFUSE_CMD */ 281 #define EFUSE_READ_CMD BIT(15) 282 #define EFUSE_DATA_BIT16 BIT(7) 283 284 /* PLA_CONFIG34 */ 285 #define LINK_ON_WAKE_EN 0x0010 286 #define LINK_OFF_WAKE_EN 0x0008 287 288 /* PLA_CONFIG5 */ 289 #define BWF_EN 0x0040 290 #define MWF_EN 0x0020 291 #define UWF_EN 0x0010 292 #define LAN_WAKE_EN 0x0002 293 294 /* PLA_LED_FEATURE */ 295 #define LED_MODE_MASK 0x0700 296 297 /* PLA_PHY_PWR */ 298 #define TX_10M_IDLE_EN 0x0080 299 #define PFM_PWM_SWITCH 0x0040 300 301 /* PLA_MAC_PWR_CTRL */ 302 #define D3_CLK_GATED_EN 0x00004000 303 #define MCU_CLK_RATIO 0x07010f07 304 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 305 #define ALDPS_SPDWN_RATIO 0x0f87 306 307 /* PLA_MAC_PWR_CTRL2 */ 308 #define EEE_SPDWN_RATIO 0x8007 309 #define MAC_CLK_SPDWN_EN BIT(15) 310 311 /* PLA_MAC_PWR_CTRL3 */ 312 #define PKT_AVAIL_SPDWN_EN 0x0100 313 #define SUSPEND_SPDWN_EN 0x0004 314 #define U1U2_SPDWN_EN 0x0002 315 #define L1_SPDWN_EN 0x0001 316 317 /* PLA_MAC_PWR_CTRL4 */ 318 #define PWRSAVE_SPDWN_EN 0x1000 319 #define RXDV_SPDWN_EN 0x0800 320 #define TX10MIDLE_EN 0x0100 321 #define TP100_SPDWN_EN 0x0020 322 #define TP500_SPDWN_EN 0x0010 323 #define TP1000_SPDWN_EN 0x0008 324 #define EEE_SPDWN_EN 0x0001 325 326 /* PLA_GPHY_INTR_IMR */ 327 #define GPHY_STS_MSK 0x0001 328 #define SPEED_DOWN_MSK 0x0002 329 #define SPDWN_RXDV_MSK 0x0004 330 #define SPDWN_LINKCHG_MSK 0x0008 331 332 /* PLA_PHYAR */ 333 #define PHYAR_FLAG 0x80000000 334 335 /* PLA_EEE_CR */ 336 #define EEE_RX_EN 0x0001 337 #define EEE_TX_EN 0x0002 338 339 /* PLA_BOOT_CTRL */ 340 #define AUTOLOAD_DONE 0x0002 341 342 /* USB_USB2PHY */ 343 #define USB2PHY_SUSPEND 0x0001 344 #define USB2PHY_L1 0x0002 345 346 /* USB_SSPHYLINK2 */ 347 #define pwd_dn_scale_mask 0x3ffe 348 #define pwd_dn_scale(x) ((x) << 1) 349 350 /* USB_CSR_DUMMY1 */ 351 #define DYNAMIC_BURST 0x0001 352 353 /* USB_CSR_DUMMY2 */ 354 #define EP4_FULL_FC 0x0001 355 356 /* USB_DEV_STAT */ 357 #define STAT_SPEED_MASK 0x0006 358 #define STAT_SPEED_HIGH 0x0000 359 #define STAT_SPEED_FULL 0x0002 360 361 /* USB_LPM_CONFIG */ 362 #define LPM_U1U2_EN BIT(0) 363 364 /* USB_TX_AGG */ 365 #define TX_AGG_MAX_THRESHOLD 0x03 366 367 /* USB_RX_BUF_TH */ 368 #define RX_THR_SUPPER 0x0c350180 369 #define RX_THR_HIGH 0x7a120180 370 #define RX_THR_SLOW 0xffff0180 371 #define RX_THR_B 0x00010001 372 373 /* USB_TX_DMA */ 374 #define TEST_MODE_DISABLE 0x00000001 375 #define TX_SIZE_ADJUST1 0x00000100 376 377 /* USB_BMU_RESET */ 378 #define BMU_RESET_EP_IN 0x01 379 #define BMU_RESET_EP_OUT 0x02 380 381 /* USB_UPT_RXDMA_OWN */ 382 #define OWN_UPDATE BIT(0) 383 #define OWN_CLEAR BIT(1) 384 385 /* USB_UPS_CTRL */ 386 #define POWER_CUT 0x0100 387 388 /* USB_PM_CTRL_STATUS */ 389 #define RESUME_INDICATE 0x0001 390 391 /* USB_USB_CTRL */ 392 #define RX_AGG_DISABLE 0x0010 393 #define RX_ZERO_EN 0x0080 394 395 /* USB_U2P3_CTRL */ 396 #define U2P3_ENABLE 0x0001 397 398 /* USB_POWER_CUT */ 399 #define PWR_EN 0x0001 400 #define PHASE2_EN 0x0008 401 #define UPS_EN BIT(4) 402 #define USP_PREWAKE BIT(5) 403 404 /* USB_MISC_0 */ 405 #define PCUT_STATUS 0x0001 406 407 /* USB_RX_EARLY_TIMEOUT */ 408 #define COALESCE_SUPER 85000U 409 #define COALESCE_HIGH 250000U 410 #define COALESCE_SLOW 524280U 411 412 /* USB_WDT11_CTRL */ 413 #define TIMER11_EN 0x0001 414 415 /* USB_LPM_CTRL */ 416 /* bit 4 ~ 5: fifo empty boundary */ 417 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 418 /* bit 2 ~ 3: LMP timer */ 419 #define LPM_TIMER_MASK 0x0c 420 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 421 #define LPM_TIMER_500US 0x0c /* 500 us */ 422 #define ROK_EXIT_LPM 0x02 423 424 /* USB_AFE_CTRL2 */ 425 #define SEN_VAL_MASK 0xf800 426 #define SEN_VAL_NORMAL 0xa000 427 #define SEL_RXIDLE 0x0100 428 429 /* USB_UPS_CFG */ 430 #define SAW_CNT_1MS_MASK 0x0fff 431 432 /* USB_UPS_FLAGS */ 433 #define UPS_FLAGS_R_TUNE BIT(0) 434 #define UPS_FLAGS_EN_10M_CKDIV BIT(1) 435 #define UPS_FLAGS_250M_CKDIV BIT(2) 436 #define UPS_FLAGS_EN_ALDPS BIT(3) 437 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) 438 #define UPS_FLAGS_SPEED_MASK (0xf << 16) 439 #define ups_flags_speed(x) ((x) << 16) 440 #define UPS_FLAGS_EN_EEE BIT(20) 441 #define UPS_FLAGS_EN_500M_EEE BIT(21) 442 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22) 443 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) 444 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) 445 #define UPS_FLAGS_EN_GREEN BIT(26) 446 #define UPS_FLAGS_EN_FLOW_CTR BIT(27) 447 448 enum spd_duplex { 449 NWAY_10M_HALF = 1, 450 NWAY_10M_FULL, 451 NWAY_100M_HALF, 452 NWAY_100M_FULL, 453 NWAY_1000M_FULL, 454 FORCE_10M_HALF, 455 FORCE_10M_FULL, 456 FORCE_100M_HALF, 457 FORCE_100M_FULL, 458 }; 459 460 /* OCP_ALDPS_CONFIG */ 461 #define ENPWRSAVE 0x8000 462 #define ENPDNPS 0x0200 463 #define LINKENA 0x0100 464 #define DIS_SDSAVE 0x0010 465 466 /* OCP_PHY_STATUS */ 467 #define PHY_STAT_MASK 0x0007 468 #define PHY_STAT_EXT_INIT 2 469 #define PHY_STAT_LAN_ON 3 470 #define PHY_STAT_PWRDN 5 471 472 /* OCP_NCTL_CFG */ 473 #define PGA_RETURN_EN BIT(1) 474 475 /* OCP_POWER_CFG */ 476 #define EEE_CLKDIV_EN 0x8000 477 #define EN_ALDPS 0x0004 478 #define EN_10M_PLLOFF 0x0001 479 480 /* OCP_EEE_CONFIG1 */ 481 #define RG_TXLPI_MSK_HFDUP 0x8000 482 #define RG_MATCLR_EN 0x4000 483 #define EEE_10_CAP 0x2000 484 #define EEE_NWAY_EN 0x1000 485 #define TX_QUIET_EN 0x0200 486 #define RX_QUIET_EN 0x0100 487 #define sd_rise_time_mask 0x0070 488 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 489 #define RG_RXLPI_MSK_HFDUP 0x0008 490 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 491 492 /* OCP_EEE_CONFIG2 */ 493 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 494 #define RG_DACQUIET_EN 0x0400 495 #define RG_LDVQUIET_EN 0x0200 496 #define RG_CKRSEL 0x0020 497 #define RG_EEEPRG_EN 0x0010 498 499 /* OCP_EEE_CONFIG3 */ 500 #define fast_snr_mask 0xff80 501 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 502 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 503 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 504 505 /* OCP_EEE_AR */ 506 /* bit[15:14] function */ 507 #define FUN_ADDR 0x0000 508 #define FUN_DATA 0x4000 509 /* bit[4:0] device addr */ 510 511 /* OCP_EEE_CFG */ 512 #define CTAP_SHORT_EN 0x0040 513 #define EEE10_EN 0x0010 514 515 /* OCP_DOWN_SPEED */ 516 #define EN_EEE_CMODE BIT(14) 517 #define EN_EEE_1000 BIT(13) 518 #define EN_EEE_100 BIT(12) 519 #define EN_10M_CLKDIV BIT(11) 520 #define EN_10M_BGOFF 0x0080 521 522 /* OCP_PHY_STATE */ 523 #define TXDIS_STATE 0x01 524 #define ABD_STATE 0x02 525 526 /* OCP_PHY_PATCH_STAT */ 527 #define PATCH_READY BIT(6) 528 529 /* OCP_PHY_PATCH_CMD */ 530 #define PATCH_REQUEST BIT(4) 531 532 /* OCP_ADC_CFG */ 533 #define CKADSEL_L 0x0100 534 #define ADC_EN 0x0080 535 #define EN_EMI_L 0x0040 536 537 /* OCP_SYSCLK_CFG */ 538 #define clk_div_expo(x) (min(x, 5) << 8) 539 540 /* SRAM_GREEN_CFG */ 541 #define GREEN_ETH_EN BIT(15) 542 #define R_TUNE_EN BIT(11) 543 544 /* SRAM_LPF_CFG */ 545 #define LPF_AUTO_TUNE 0x8000 546 547 /* SRAM_10M_AMP1 */ 548 #define GDAC_IB_UPALL 0x0008 549 550 /* SRAM_10M_AMP2 */ 551 #define AMP_DN 0x0200 552 553 /* SRAM_IMPEDANCE */ 554 #define RX_DRIVING_MASK 0x6000 555 556 /* MAC PASSTHRU */ 557 #define AD_MASK 0xfee0 558 #define EFUSE 0xcfdb 559 #define PASS_THRU_MASK 0x1 560 561 enum rtl_register_content { 562 _1000bps = 0x10, 563 _100bps = 0x08, 564 _10bps = 0x04, 565 LINK_STATUS = 0x02, 566 FULL_DUP = 0x01, 567 }; 568 569 #define RTL8152_MAX_TX 4 570 #define RTL8152_MAX_RX 10 571 #define INTBUFSIZE 2 572 #define TX_ALIGN 4 573 #define RX_ALIGN 8 574 575 #define INTR_LINK 0x0004 576 577 #define RTL8152_REQT_READ 0xc0 578 #define RTL8152_REQT_WRITE 0x40 579 #define RTL8152_REQ_GET_REGS 0x05 580 #define RTL8152_REQ_SET_REGS 0x05 581 582 #define BYTE_EN_DWORD 0xff 583 #define BYTE_EN_WORD 0x33 584 #define BYTE_EN_BYTE 0x11 585 #define BYTE_EN_SIX_BYTES 0x3f 586 #define BYTE_EN_START_MASK 0x0f 587 #define BYTE_EN_END_MASK 0xf0 588 589 #define RTL8153_MAX_PACKET 9216 /* 9K */ 590 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \ 591 ETH_FCS_LEN) 592 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 593 #define RTL8153_RMS RTL8153_MAX_PACKET 594 #define RTL8152_TX_TIMEOUT (5 * HZ) 595 #define RTL8152_NAPI_WEIGHT 64 596 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \ 597 sizeof(struct rx_desc) + RX_ALIGN) 598 599 /* rtl8152 flags */ 600 enum rtl8152_flags { 601 RTL8152_UNPLUG = 0, 602 RTL8152_SET_RX_MODE, 603 WORK_ENABLE, 604 RTL8152_LINK_CHG, 605 SELECTIVE_SUSPEND, 606 PHY_RESET, 607 SCHEDULE_NAPI, 608 GREEN_ETHERNET, 609 }; 610 611 /* Define these values to match your device */ 612 #define VENDOR_ID_REALTEK 0x0bda 613 #define VENDOR_ID_MICROSOFT 0x045e 614 #define VENDOR_ID_SAMSUNG 0x04e8 615 #define VENDOR_ID_LENOVO 0x17ef 616 #define VENDOR_ID_NVIDIA 0x0955 617 618 #define MCU_TYPE_PLA 0x0100 619 #define MCU_TYPE_USB 0x0000 620 621 struct tally_counter { 622 __le64 tx_packets; 623 __le64 rx_packets; 624 __le64 tx_errors; 625 __le32 rx_errors; 626 __le16 rx_missed; 627 __le16 align_errors; 628 __le32 tx_one_collision; 629 __le32 tx_multi_collision; 630 __le64 rx_unicast; 631 __le64 rx_broadcast; 632 __le32 rx_multicast; 633 __le16 tx_aborted; 634 __le16 tx_underrun; 635 }; 636 637 struct rx_desc { 638 __le32 opts1; 639 #define RX_LEN_MASK 0x7fff 640 641 __le32 opts2; 642 #define RD_UDP_CS BIT(23) 643 #define RD_TCP_CS BIT(22) 644 #define RD_IPV6_CS BIT(20) 645 #define RD_IPV4_CS BIT(19) 646 647 __le32 opts3; 648 #define IPF BIT(23) /* IP checksum fail */ 649 #define UDPF BIT(22) /* UDP checksum fail */ 650 #define TCPF BIT(21) /* TCP checksum fail */ 651 #define RX_VLAN_TAG BIT(16) 652 653 __le32 opts4; 654 __le32 opts5; 655 __le32 opts6; 656 }; 657 658 struct tx_desc { 659 __le32 opts1; 660 #define TX_FS BIT(31) /* First segment of a packet */ 661 #define TX_LS BIT(30) /* Final segment of a packet */ 662 #define GTSENDV4 BIT(28) 663 #define GTSENDV6 BIT(27) 664 #define GTTCPHO_SHIFT 18 665 #define GTTCPHO_MAX 0x7fU 666 #define TX_LEN_MAX 0x3ffffU 667 668 __le32 opts2; 669 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 670 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 671 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 672 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 673 #define MSS_SHIFT 17 674 #define MSS_MAX 0x7ffU 675 #define TCPHO_SHIFT 17 676 #define TCPHO_MAX 0x7ffU 677 #define TX_VLAN_TAG BIT(16) 678 }; 679 680 struct r8152; 681 682 struct rx_agg { 683 struct list_head list; 684 struct urb *urb; 685 struct r8152 *context; 686 void *buffer; 687 void *head; 688 }; 689 690 struct tx_agg { 691 struct list_head list; 692 struct urb *urb; 693 struct r8152 *context; 694 void *buffer; 695 void *head; 696 u32 skb_num; 697 u32 skb_len; 698 }; 699 700 struct r8152 { 701 unsigned long flags; 702 struct usb_device *udev; 703 struct napi_struct napi; 704 struct usb_interface *intf; 705 struct net_device *netdev; 706 struct urb *intr_urb; 707 struct tx_agg tx_info[RTL8152_MAX_TX]; 708 struct rx_agg rx_info[RTL8152_MAX_RX]; 709 struct list_head rx_done, tx_free; 710 struct sk_buff_head tx_queue, rx_queue; 711 spinlock_t rx_lock, tx_lock; 712 struct delayed_work schedule, hw_phy_work; 713 struct mii_if_info mii; 714 struct mutex control; /* use for hw setting */ 715 #ifdef CONFIG_PM_SLEEP 716 struct notifier_block pm_notifier; 717 #endif 718 719 struct rtl_ops { 720 void (*init)(struct r8152 *); 721 int (*enable)(struct r8152 *); 722 void (*disable)(struct r8152 *); 723 void (*up)(struct r8152 *); 724 void (*down)(struct r8152 *); 725 void (*unload)(struct r8152 *); 726 int (*eee_get)(struct r8152 *, struct ethtool_eee *); 727 int (*eee_set)(struct r8152 *, struct ethtool_eee *); 728 bool (*in_nway)(struct r8152 *); 729 void (*hw_phy_cfg)(struct r8152 *); 730 void (*autosuspend_en)(struct r8152 *tp, bool enable); 731 } rtl_ops; 732 733 int intr_interval; 734 u32 saved_wolopts; 735 u32 msg_enable; 736 u32 tx_qlen; 737 u32 coalesce; 738 u16 ocp_base; 739 u16 speed; 740 u8 *intr_buff; 741 u8 version; 742 u8 duplex; 743 u8 autoneg; 744 }; 745 746 enum rtl_version { 747 RTL_VER_UNKNOWN = 0, 748 RTL_VER_01, 749 RTL_VER_02, 750 RTL_VER_03, 751 RTL_VER_04, 752 RTL_VER_05, 753 RTL_VER_06, 754 RTL_VER_07, 755 RTL_VER_08, 756 RTL_VER_09, 757 RTL_VER_MAX 758 }; 759 760 enum tx_csum_stat { 761 TX_CSUM_SUCCESS = 0, 762 TX_CSUM_TSO, 763 TX_CSUM_NONE 764 }; 765 766 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 767 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 768 */ 769 static const int multicast_filter_limit = 32; 770 static unsigned int agg_buf_sz = 16384; 771 772 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ 773 VLAN_ETH_HLEN - ETH_FCS_LEN) 774 775 static 776 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 777 { 778 int ret; 779 void *tmp; 780 781 tmp = kmalloc(size, GFP_KERNEL); 782 if (!tmp) 783 return -ENOMEM; 784 785 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 786 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 787 value, index, tmp, size, 500); 788 789 memcpy(data, tmp, size); 790 kfree(tmp); 791 792 return ret; 793 } 794 795 static 796 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 797 { 798 int ret; 799 void *tmp; 800 801 tmp = kmemdup(data, size, GFP_KERNEL); 802 if (!tmp) 803 return -ENOMEM; 804 805 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 806 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 807 value, index, tmp, size, 500); 808 809 kfree(tmp); 810 811 return ret; 812 } 813 814 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 815 void *data, u16 type) 816 { 817 u16 limit = 64; 818 int ret = 0; 819 820 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 821 return -ENODEV; 822 823 /* both size and indix must be 4 bytes align */ 824 if ((size & 3) || !size || (index & 3) || !data) 825 return -EPERM; 826 827 if ((u32)index + (u32)size > 0xffff) 828 return -EPERM; 829 830 while (size) { 831 if (size > limit) { 832 ret = get_registers(tp, index, type, limit, data); 833 if (ret < 0) 834 break; 835 836 index += limit; 837 data += limit; 838 size -= limit; 839 } else { 840 ret = get_registers(tp, index, type, size, data); 841 if (ret < 0) 842 break; 843 844 index += size; 845 data += size; 846 size = 0; 847 break; 848 } 849 } 850 851 if (ret == -ENODEV) 852 set_bit(RTL8152_UNPLUG, &tp->flags); 853 854 return ret; 855 } 856 857 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 858 u16 size, void *data, u16 type) 859 { 860 int ret; 861 u16 byteen_start, byteen_end, byen; 862 u16 limit = 512; 863 864 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 865 return -ENODEV; 866 867 /* both size and indix must be 4 bytes align */ 868 if ((size & 3) || !size || (index & 3) || !data) 869 return -EPERM; 870 871 if ((u32)index + (u32)size > 0xffff) 872 return -EPERM; 873 874 byteen_start = byteen & BYTE_EN_START_MASK; 875 byteen_end = byteen & BYTE_EN_END_MASK; 876 877 byen = byteen_start | (byteen_start << 4); 878 ret = set_registers(tp, index, type | byen, 4, data); 879 if (ret < 0) 880 goto error1; 881 882 index += 4; 883 data += 4; 884 size -= 4; 885 886 if (size) { 887 size -= 4; 888 889 while (size) { 890 if (size > limit) { 891 ret = set_registers(tp, index, 892 type | BYTE_EN_DWORD, 893 limit, data); 894 if (ret < 0) 895 goto error1; 896 897 index += limit; 898 data += limit; 899 size -= limit; 900 } else { 901 ret = set_registers(tp, index, 902 type | BYTE_EN_DWORD, 903 size, data); 904 if (ret < 0) 905 goto error1; 906 907 index += size; 908 data += size; 909 size = 0; 910 break; 911 } 912 } 913 914 byen = byteen_end | (byteen_end >> 4); 915 ret = set_registers(tp, index, type | byen, 4, data); 916 if (ret < 0) 917 goto error1; 918 } 919 920 error1: 921 if (ret == -ENODEV) 922 set_bit(RTL8152_UNPLUG, &tp->flags); 923 924 return ret; 925 } 926 927 static inline 928 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 929 { 930 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 931 } 932 933 static inline 934 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 935 { 936 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 937 } 938 939 static inline 940 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 941 { 942 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 943 } 944 945 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 946 { 947 __le32 data; 948 949 generic_ocp_read(tp, index, sizeof(data), &data, type); 950 951 return __le32_to_cpu(data); 952 } 953 954 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 955 { 956 __le32 tmp = __cpu_to_le32(data); 957 958 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 959 } 960 961 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 962 { 963 u32 data; 964 __le32 tmp; 965 u16 byen = BYTE_EN_WORD; 966 u8 shift = index & 2; 967 968 index &= ~3; 969 byen <<= shift; 970 971 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen); 972 973 data = __le32_to_cpu(tmp); 974 data >>= (shift * 8); 975 data &= 0xffff; 976 977 return (u16)data; 978 } 979 980 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 981 { 982 u32 mask = 0xffff; 983 __le32 tmp; 984 u16 byen = BYTE_EN_WORD; 985 u8 shift = index & 2; 986 987 data &= mask; 988 989 if (index & 2) { 990 byen <<= shift; 991 mask <<= (shift * 8); 992 data <<= (shift * 8); 993 index &= ~3; 994 } 995 996 tmp = __cpu_to_le32(data); 997 998 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 999 } 1000 1001 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 1002 { 1003 u32 data; 1004 __le32 tmp; 1005 u8 shift = index & 3; 1006 1007 index &= ~3; 1008 1009 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 1010 1011 data = __le32_to_cpu(tmp); 1012 data >>= (shift * 8); 1013 data &= 0xff; 1014 1015 return (u8)data; 1016 } 1017 1018 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 1019 { 1020 u32 mask = 0xff; 1021 __le32 tmp; 1022 u16 byen = BYTE_EN_BYTE; 1023 u8 shift = index & 3; 1024 1025 data &= mask; 1026 1027 if (index & 3) { 1028 byen <<= shift; 1029 mask <<= (shift * 8); 1030 data <<= (shift * 8); 1031 index &= ~3; 1032 } 1033 1034 tmp = __cpu_to_le32(data); 1035 1036 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1037 } 1038 1039 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 1040 { 1041 u16 ocp_base, ocp_index; 1042 1043 ocp_base = addr & 0xf000; 1044 if (ocp_base != tp->ocp_base) { 1045 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1046 tp->ocp_base = ocp_base; 1047 } 1048 1049 ocp_index = (addr & 0x0fff) | 0xb000; 1050 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 1051 } 1052 1053 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 1054 { 1055 u16 ocp_base, ocp_index; 1056 1057 ocp_base = addr & 0xf000; 1058 if (ocp_base != tp->ocp_base) { 1059 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1060 tp->ocp_base = ocp_base; 1061 } 1062 1063 ocp_index = (addr & 0x0fff) | 0xb000; 1064 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 1065 } 1066 1067 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 1068 { 1069 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 1070 } 1071 1072 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 1073 { 1074 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 1075 } 1076 1077 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 1078 { 1079 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1080 ocp_reg_write(tp, OCP_SRAM_DATA, data); 1081 } 1082 1083 static u16 sram_read(struct r8152 *tp, u16 addr) 1084 { 1085 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1086 return ocp_reg_read(tp, OCP_SRAM_DATA); 1087 } 1088 1089 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 1090 { 1091 struct r8152 *tp = netdev_priv(netdev); 1092 int ret; 1093 1094 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1095 return -ENODEV; 1096 1097 if (phy_id != R8152_PHY_ID) 1098 return -EINVAL; 1099 1100 ret = r8152_mdio_read(tp, reg); 1101 1102 return ret; 1103 } 1104 1105 static 1106 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 1107 { 1108 struct r8152 *tp = netdev_priv(netdev); 1109 1110 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1111 return; 1112 1113 if (phy_id != R8152_PHY_ID) 1114 return; 1115 1116 r8152_mdio_write(tp, reg, val); 1117 } 1118 1119 static int 1120 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 1121 1122 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1123 { 1124 struct r8152 *tp = netdev_priv(netdev); 1125 struct sockaddr *addr = p; 1126 int ret = -EADDRNOTAVAIL; 1127 1128 if (!is_valid_ether_addr(addr->sa_data)) 1129 goto out1; 1130 1131 ret = usb_autopm_get_interface(tp->intf); 1132 if (ret < 0) 1133 goto out1; 1134 1135 mutex_lock(&tp->control); 1136 1137 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1138 1139 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1140 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1141 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1142 1143 mutex_unlock(&tp->control); 1144 1145 usb_autopm_put_interface(tp->intf); 1146 out1: 1147 return ret; 1148 } 1149 1150 /* Devices containing RTL8153-AD can support a persistent 1151 * host system provided MAC address. 1152 * Examples of this are Dell TB15 and Dell WD15 docks 1153 */ 1154 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) 1155 { 1156 acpi_status status; 1157 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1158 union acpi_object *obj; 1159 int ret = -EINVAL; 1160 u32 ocp_data; 1161 unsigned char buf[6]; 1162 1163 /* test for -AD variant of RTL8153 */ 1164 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 1165 if ((ocp_data & AD_MASK) != 0x1000) 1166 return -ENODEV; 1167 1168 /* test for MAC address pass-through bit */ 1169 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); 1170 if ((ocp_data & PASS_THRU_MASK) != 1) 1171 return -ENODEV; 1172 1173 /* returns _AUXMAC_#AABBCCDDEEFF# */ 1174 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer); 1175 obj = (union acpi_object *)buffer.pointer; 1176 if (!ACPI_SUCCESS(status)) 1177 return -ENODEV; 1178 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) { 1179 netif_warn(tp, probe, tp->netdev, 1180 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", 1181 obj->type, obj->string.length); 1182 goto amacout; 1183 } 1184 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || 1185 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { 1186 netif_warn(tp, probe, tp->netdev, 1187 "Invalid header when reading pass-thru MAC addr\n"); 1188 goto amacout; 1189 } 1190 ret = hex2bin(buf, obj->string.pointer + 9, 6); 1191 if (!(ret == 0 && is_valid_ether_addr(buf))) { 1192 netif_warn(tp, probe, tp->netdev, 1193 "Invalid MAC for pass-thru MAC addr: %d, %pM\n", 1194 ret, buf); 1195 ret = -EINVAL; 1196 goto amacout; 1197 } 1198 memcpy(sa->sa_data, buf, 6); 1199 ether_addr_copy(tp->netdev->dev_addr, sa->sa_data); 1200 netif_info(tp, probe, tp->netdev, 1201 "Using pass-thru MAC addr %pM\n", sa->sa_data); 1202 1203 amacout: 1204 kfree(obj); 1205 return ret; 1206 } 1207 1208 static int set_ethernet_addr(struct r8152 *tp) 1209 { 1210 struct net_device *dev = tp->netdev; 1211 struct sockaddr sa; 1212 int ret; 1213 1214 if (tp->version == RTL_VER_01) { 1215 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); 1216 } else { 1217 /* if this is not an RTL8153-AD, no eFuse mac pass thru set, 1218 * or system doesn't provide valid _SB.AMAC this will be 1219 * be expected to non-zero 1220 */ 1221 ret = vendor_mac_passthru_addr_read(tp, &sa); 1222 if (ret < 0) 1223 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); 1224 } 1225 1226 if (ret < 0) { 1227 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1228 } else if (!is_valid_ether_addr(sa.sa_data)) { 1229 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1230 sa.sa_data); 1231 eth_hw_addr_random(dev); 1232 ether_addr_copy(sa.sa_data, dev->dev_addr); 1233 ret = rtl8152_set_mac_address(dev, &sa); 1234 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1235 sa.sa_data); 1236 } else { 1237 if (tp->version == RTL_VER_01) 1238 ether_addr_copy(dev->dev_addr, sa.sa_data); 1239 else 1240 ret = rtl8152_set_mac_address(dev, &sa); 1241 } 1242 1243 return ret; 1244 } 1245 1246 static void read_bulk_callback(struct urb *urb) 1247 { 1248 struct net_device *netdev; 1249 int status = urb->status; 1250 struct rx_agg *agg; 1251 struct r8152 *tp; 1252 1253 agg = urb->context; 1254 if (!agg) 1255 return; 1256 1257 tp = agg->context; 1258 if (!tp) 1259 return; 1260 1261 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1262 return; 1263 1264 if (!test_bit(WORK_ENABLE, &tp->flags)) 1265 return; 1266 1267 netdev = tp->netdev; 1268 1269 /* When link down, the driver would cancel all bulks. */ 1270 /* This avoid the re-submitting bulk */ 1271 if (!netif_carrier_ok(netdev)) 1272 return; 1273 1274 usb_mark_last_busy(tp->udev); 1275 1276 switch (status) { 1277 case 0: 1278 if (urb->actual_length < ETH_ZLEN) 1279 break; 1280 1281 spin_lock(&tp->rx_lock); 1282 list_add_tail(&agg->list, &tp->rx_done); 1283 spin_unlock(&tp->rx_lock); 1284 napi_schedule(&tp->napi); 1285 return; 1286 case -ESHUTDOWN: 1287 set_bit(RTL8152_UNPLUG, &tp->flags); 1288 netif_device_detach(tp->netdev); 1289 return; 1290 case -ENOENT: 1291 return; /* the urb is in unlink state */ 1292 case -ETIME: 1293 if (net_ratelimit()) 1294 netdev_warn(netdev, "maybe reset is needed?\n"); 1295 break; 1296 default: 1297 if (net_ratelimit()) 1298 netdev_warn(netdev, "Rx status %d\n", status); 1299 break; 1300 } 1301 1302 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1303 } 1304 1305 static void write_bulk_callback(struct urb *urb) 1306 { 1307 struct net_device_stats *stats; 1308 struct net_device *netdev; 1309 struct tx_agg *agg; 1310 struct r8152 *tp; 1311 int status = urb->status; 1312 1313 agg = urb->context; 1314 if (!agg) 1315 return; 1316 1317 tp = agg->context; 1318 if (!tp) 1319 return; 1320 1321 netdev = tp->netdev; 1322 stats = &netdev->stats; 1323 if (status) { 1324 if (net_ratelimit()) 1325 netdev_warn(netdev, "Tx status %d\n", status); 1326 stats->tx_errors += agg->skb_num; 1327 } else { 1328 stats->tx_packets += agg->skb_num; 1329 stats->tx_bytes += agg->skb_len; 1330 } 1331 1332 spin_lock(&tp->tx_lock); 1333 list_add_tail(&agg->list, &tp->tx_free); 1334 spin_unlock(&tp->tx_lock); 1335 1336 usb_autopm_put_interface_async(tp->intf); 1337 1338 if (!netif_carrier_ok(netdev)) 1339 return; 1340 1341 if (!test_bit(WORK_ENABLE, &tp->flags)) 1342 return; 1343 1344 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1345 return; 1346 1347 if (!skb_queue_empty(&tp->tx_queue)) 1348 napi_schedule(&tp->napi); 1349 } 1350 1351 static void intr_callback(struct urb *urb) 1352 { 1353 struct r8152 *tp; 1354 __le16 *d; 1355 int status = urb->status; 1356 int res; 1357 1358 tp = urb->context; 1359 if (!tp) 1360 return; 1361 1362 if (!test_bit(WORK_ENABLE, &tp->flags)) 1363 return; 1364 1365 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1366 return; 1367 1368 switch (status) { 1369 case 0: /* success */ 1370 break; 1371 case -ECONNRESET: /* unlink */ 1372 case -ESHUTDOWN: 1373 netif_device_detach(tp->netdev); 1374 case -ENOENT: 1375 case -EPROTO: 1376 netif_info(tp, intr, tp->netdev, 1377 "Stop submitting intr, status %d\n", status); 1378 return; 1379 case -EOVERFLOW: 1380 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1381 goto resubmit; 1382 /* -EPIPE: should clear the halt */ 1383 default: 1384 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1385 goto resubmit; 1386 } 1387 1388 d = urb->transfer_buffer; 1389 if (INTR_LINK & __le16_to_cpu(d[0])) { 1390 if (!netif_carrier_ok(tp->netdev)) { 1391 set_bit(RTL8152_LINK_CHG, &tp->flags); 1392 schedule_delayed_work(&tp->schedule, 0); 1393 } 1394 } else { 1395 if (netif_carrier_ok(tp->netdev)) { 1396 netif_stop_queue(tp->netdev); 1397 set_bit(RTL8152_LINK_CHG, &tp->flags); 1398 schedule_delayed_work(&tp->schedule, 0); 1399 } 1400 } 1401 1402 resubmit: 1403 res = usb_submit_urb(urb, GFP_ATOMIC); 1404 if (res == -ENODEV) { 1405 set_bit(RTL8152_UNPLUG, &tp->flags); 1406 netif_device_detach(tp->netdev); 1407 } else if (res) { 1408 netif_err(tp, intr, tp->netdev, 1409 "can't resubmit intr, status %d\n", res); 1410 } 1411 } 1412 1413 static inline void *rx_agg_align(void *data) 1414 { 1415 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1416 } 1417 1418 static inline void *tx_agg_align(void *data) 1419 { 1420 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1421 } 1422 1423 static void free_all_mem(struct r8152 *tp) 1424 { 1425 int i; 1426 1427 for (i = 0; i < RTL8152_MAX_RX; i++) { 1428 usb_free_urb(tp->rx_info[i].urb); 1429 tp->rx_info[i].urb = NULL; 1430 1431 kfree(tp->rx_info[i].buffer); 1432 tp->rx_info[i].buffer = NULL; 1433 tp->rx_info[i].head = NULL; 1434 } 1435 1436 for (i = 0; i < RTL8152_MAX_TX; i++) { 1437 usb_free_urb(tp->tx_info[i].urb); 1438 tp->tx_info[i].urb = NULL; 1439 1440 kfree(tp->tx_info[i].buffer); 1441 tp->tx_info[i].buffer = NULL; 1442 tp->tx_info[i].head = NULL; 1443 } 1444 1445 usb_free_urb(tp->intr_urb); 1446 tp->intr_urb = NULL; 1447 1448 kfree(tp->intr_buff); 1449 tp->intr_buff = NULL; 1450 } 1451 1452 static int alloc_all_mem(struct r8152 *tp) 1453 { 1454 struct net_device *netdev = tp->netdev; 1455 struct usb_interface *intf = tp->intf; 1456 struct usb_host_interface *alt = intf->cur_altsetting; 1457 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1458 struct urb *urb; 1459 int node, i; 1460 u8 *buf; 1461 1462 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1463 1464 spin_lock_init(&tp->rx_lock); 1465 spin_lock_init(&tp->tx_lock); 1466 INIT_LIST_HEAD(&tp->tx_free); 1467 INIT_LIST_HEAD(&tp->rx_done); 1468 skb_queue_head_init(&tp->tx_queue); 1469 skb_queue_head_init(&tp->rx_queue); 1470 1471 for (i = 0; i < RTL8152_MAX_RX; i++) { 1472 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1473 if (!buf) 1474 goto err1; 1475 1476 if (buf != rx_agg_align(buf)) { 1477 kfree(buf); 1478 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, 1479 node); 1480 if (!buf) 1481 goto err1; 1482 } 1483 1484 urb = usb_alloc_urb(0, GFP_KERNEL); 1485 if (!urb) { 1486 kfree(buf); 1487 goto err1; 1488 } 1489 1490 INIT_LIST_HEAD(&tp->rx_info[i].list); 1491 tp->rx_info[i].context = tp; 1492 tp->rx_info[i].urb = urb; 1493 tp->rx_info[i].buffer = buf; 1494 tp->rx_info[i].head = rx_agg_align(buf); 1495 } 1496 1497 for (i = 0; i < RTL8152_MAX_TX; i++) { 1498 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1499 if (!buf) 1500 goto err1; 1501 1502 if (buf != tx_agg_align(buf)) { 1503 kfree(buf); 1504 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 1505 node); 1506 if (!buf) 1507 goto err1; 1508 } 1509 1510 urb = usb_alloc_urb(0, GFP_KERNEL); 1511 if (!urb) { 1512 kfree(buf); 1513 goto err1; 1514 } 1515 1516 INIT_LIST_HEAD(&tp->tx_info[i].list); 1517 tp->tx_info[i].context = tp; 1518 tp->tx_info[i].urb = urb; 1519 tp->tx_info[i].buffer = buf; 1520 tp->tx_info[i].head = tx_agg_align(buf); 1521 1522 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1523 } 1524 1525 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1526 if (!tp->intr_urb) 1527 goto err1; 1528 1529 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1530 if (!tp->intr_buff) 1531 goto err1; 1532 1533 tp->intr_interval = (int)ep_intr->desc.bInterval; 1534 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1535 tp->intr_buff, INTBUFSIZE, intr_callback, 1536 tp, tp->intr_interval); 1537 1538 return 0; 1539 1540 err1: 1541 free_all_mem(tp); 1542 return -ENOMEM; 1543 } 1544 1545 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1546 { 1547 struct tx_agg *agg = NULL; 1548 unsigned long flags; 1549 1550 if (list_empty(&tp->tx_free)) 1551 return NULL; 1552 1553 spin_lock_irqsave(&tp->tx_lock, flags); 1554 if (!list_empty(&tp->tx_free)) { 1555 struct list_head *cursor; 1556 1557 cursor = tp->tx_free.next; 1558 list_del_init(cursor); 1559 agg = list_entry(cursor, struct tx_agg, list); 1560 } 1561 spin_unlock_irqrestore(&tp->tx_lock, flags); 1562 1563 return agg; 1564 } 1565 1566 /* r8152_csum_workaround() 1567 * The hw limites the value the transport offset. When the offset is out of the 1568 * range, calculate the checksum by sw. 1569 */ 1570 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1571 struct sk_buff_head *list) 1572 { 1573 if (skb_shinfo(skb)->gso_size) { 1574 netdev_features_t features = tp->netdev->features; 1575 struct sk_buff_head seg_list; 1576 struct sk_buff *segs, *nskb; 1577 1578 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 1579 segs = skb_gso_segment(skb, features); 1580 if (IS_ERR(segs) || !segs) 1581 goto drop; 1582 1583 __skb_queue_head_init(&seg_list); 1584 1585 do { 1586 nskb = segs; 1587 segs = segs->next; 1588 nskb->next = NULL; 1589 __skb_queue_tail(&seg_list, nskb); 1590 } while (segs); 1591 1592 skb_queue_splice(&seg_list, list); 1593 dev_kfree_skb(skb); 1594 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1595 if (skb_checksum_help(skb) < 0) 1596 goto drop; 1597 1598 __skb_queue_head(list, skb); 1599 } else { 1600 struct net_device_stats *stats; 1601 1602 drop: 1603 stats = &tp->netdev->stats; 1604 stats->tx_dropped++; 1605 dev_kfree_skb(skb); 1606 } 1607 } 1608 1609 /* msdn_giant_send_check() 1610 * According to the document of microsoft, the TCP Pseudo Header excludes the 1611 * packet length for IPv6 TCP large packets. 1612 */ 1613 static int msdn_giant_send_check(struct sk_buff *skb) 1614 { 1615 const struct ipv6hdr *ipv6h; 1616 struct tcphdr *th; 1617 int ret; 1618 1619 ret = skb_cow_head(skb, 0); 1620 if (ret) 1621 return ret; 1622 1623 ipv6h = ipv6_hdr(skb); 1624 th = tcp_hdr(skb); 1625 1626 th->check = 0; 1627 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1628 1629 return ret; 1630 } 1631 1632 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 1633 { 1634 if (skb_vlan_tag_present(skb)) { 1635 u32 opts2; 1636 1637 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); 1638 desc->opts2 |= cpu_to_le32(opts2); 1639 } 1640 } 1641 1642 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 1643 { 1644 u32 opts2 = le32_to_cpu(desc->opts2); 1645 1646 if (opts2 & RX_VLAN_TAG) 1647 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1648 swab16(opts2 & 0xffff)); 1649 } 1650 1651 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1652 struct sk_buff *skb, u32 len, u32 transport_offset) 1653 { 1654 u32 mss = skb_shinfo(skb)->gso_size; 1655 u32 opts1, opts2 = 0; 1656 int ret = TX_CSUM_SUCCESS; 1657 1658 WARN_ON_ONCE(len > TX_LEN_MAX); 1659 1660 opts1 = len | TX_FS | TX_LS; 1661 1662 if (mss) { 1663 if (transport_offset > GTTCPHO_MAX) { 1664 netif_warn(tp, tx_err, tp->netdev, 1665 "Invalid transport offset 0x%x for TSO\n", 1666 transport_offset); 1667 ret = TX_CSUM_TSO; 1668 goto unavailable; 1669 } 1670 1671 switch (vlan_get_protocol(skb)) { 1672 case htons(ETH_P_IP): 1673 opts1 |= GTSENDV4; 1674 break; 1675 1676 case htons(ETH_P_IPV6): 1677 if (msdn_giant_send_check(skb)) { 1678 ret = TX_CSUM_TSO; 1679 goto unavailable; 1680 } 1681 opts1 |= GTSENDV6; 1682 break; 1683 1684 default: 1685 WARN_ON_ONCE(1); 1686 break; 1687 } 1688 1689 opts1 |= transport_offset << GTTCPHO_SHIFT; 1690 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1691 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1692 u8 ip_protocol; 1693 1694 if (transport_offset > TCPHO_MAX) { 1695 netif_warn(tp, tx_err, tp->netdev, 1696 "Invalid transport offset 0x%x\n", 1697 transport_offset); 1698 ret = TX_CSUM_NONE; 1699 goto unavailable; 1700 } 1701 1702 switch (vlan_get_protocol(skb)) { 1703 case htons(ETH_P_IP): 1704 opts2 |= IPV4_CS; 1705 ip_protocol = ip_hdr(skb)->protocol; 1706 break; 1707 1708 case htons(ETH_P_IPV6): 1709 opts2 |= IPV6_CS; 1710 ip_protocol = ipv6_hdr(skb)->nexthdr; 1711 break; 1712 1713 default: 1714 ip_protocol = IPPROTO_RAW; 1715 break; 1716 } 1717 1718 if (ip_protocol == IPPROTO_TCP) 1719 opts2 |= TCP_CS; 1720 else if (ip_protocol == IPPROTO_UDP) 1721 opts2 |= UDP_CS; 1722 else 1723 WARN_ON_ONCE(1); 1724 1725 opts2 |= transport_offset << TCPHO_SHIFT; 1726 } 1727 1728 desc->opts2 = cpu_to_le32(opts2); 1729 desc->opts1 = cpu_to_le32(opts1); 1730 1731 unavailable: 1732 return ret; 1733 } 1734 1735 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1736 { 1737 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1738 int remain, ret; 1739 u8 *tx_data; 1740 1741 __skb_queue_head_init(&skb_head); 1742 spin_lock(&tx_queue->lock); 1743 skb_queue_splice_init(tx_queue, &skb_head); 1744 spin_unlock(&tx_queue->lock); 1745 1746 tx_data = agg->head; 1747 agg->skb_num = 0; 1748 agg->skb_len = 0; 1749 remain = agg_buf_sz; 1750 1751 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1752 struct tx_desc *tx_desc; 1753 struct sk_buff *skb; 1754 unsigned int len; 1755 u32 offset; 1756 1757 skb = __skb_dequeue(&skb_head); 1758 if (!skb) 1759 break; 1760 1761 len = skb->len + sizeof(*tx_desc); 1762 1763 if (len > remain) { 1764 __skb_queue_head(&skb_head, skb); 1765 break; 1766 } 1767 1768 tx_data = tx_agg_align(tx_data); 1769 tx_desc = (struct tx_desc *)tx_data; 1770 1771 offset = (u32)skb_transport_offset(skb); 1772 1773 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1774 r8152_csum_workaround(tp, skb, &skb_head); 1775 continue; 1776 } 1777 1778 rtl_tx_vlan_tag(tx_desc, skb); 1779 1780 tx_data += sizeof(*tx_desc); 1781 1782 len = skb->len; 1783 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1784 struct net_device_stats *stats = &tp->netdev->stats; 1785 1786 stats->tx_dropped++; 1787 dev_kfree_skb_any(skb); 1788 tx_data -= sizeof(*tx_desc); 1789 continue; 1790 } 1791 1792 tx_data += len; 1793 agg->skb_len += len; 1794 agg->skb_num++; 1795 1796 dev_kfree_skb_any(skb); 1797 1798 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1799 } 1800 1801 if (!skb_queue_empty(&skb_head)) { 1802 spin_lock(&tx_queue->lock); 1803 skb_queue_splice(&skb_head, tx_queue); 1804 spin_unlock(&tx_queue->lock); 1805 } 1806 1807 netif_tx_lock(tp->netdev); 1808 1809 if (netif_queue_stopped(tp->netdev) && 1810 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1811 netif_wake_queue(tp->netdev); 1812 1813 netif_tx_unlock(tp->netdev); 1814 1815 ret = usb_autopm_get_interface_async(tp->intf); 1816 if (ret < 0) 1817 goto out_tx_fill; 1818 1819 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1820 agg->head, (int)(tx_data - (u8 *)agg->head), 1821 (usb_complete_t)write_bulk_callback, agg); 1822 1823 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1824 if (ret < 0) 1825 usb_autopm_put_interface_async(tp->intf); 1826 1827 out_tx_fill: 1828 return ret; 1829 } 1830 1831 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1832 { 1833 u8 checksum = CHECKSUM_NONE; 1834 u32 opts2, opts3; 1835 1836 if (!(tp->netdev->features & NETIF_F_RXCSUM)) 1837 goto return_result; 1838 1839 opts2 = le32_to_cpu(rx_desc->opts2); 1840 opts3 = le32_to_cpu(rx_desc->opts3); 1841 1842 if (opts2 & RD_IPV4_CS) { 1843 if (opts3 & IPF) 1844 checksum = CHECKSUM_NONE; 1845 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) 1846 checksum = CHECKSUM_NONE; 1847 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) 1848 checksum = CHECKSUM_NONE; 1849 else 1850 checksum = CHECKSUM_UNNECESSARY; 1851 } else if (opts2 & RD_IPV6_CS) { 1852 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1853 checksum = CHECKSUM_UNNECESSARY; 1854 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1855 checksum = CHECKSUM_UNNECESSARY; 1856 } 1857 1858 return_result: 1859 return checksum; 1860 } 1861 1862 static int rx_bottom(struct r8152 *tp, int budget) 1863 { 1864 unsigned long flags; 1865 struct list_head *cursor, *next, rx_queue; 1866 int ret = 0, work_done = 0; 1867 struct napi_struct *napi = &tp->napi; 1868 1869 if (!skb_queue_empty(&tp->rx_queue)) { 1870 while (work_done < budget) { 1871 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); 1872 struct net_device *netdev = tp->netdev; 1873 struct net_device_stats *stats = &netdev->stats; 1874 unsigned int pkt_len; 1875 1876 if (!skb) 1877 break; 1878 1879 pkt_len = skb->len; 1880 napi_gro_receive(napi, skb); 1881 work_done++; 1882 stats->rx_packets++; 1883 stats->rx_bytes += pkt_len; 1884 } 1885 } 1886 1887 if (list_empty(&tp->rx_done)) 1888 goto out1; 1889 1890 INIT_LIST_HEAD(&rx_queue); 1891 spin_lock_irqsave(&tp->rx_lock, flags); 1892 list_splice_init(&tp->rx_done, &rx_queue); 1893 spin_unlock_irqrestore(&tp->rx_lock, flags); 1894 1895 list_for_each_safe(cursor, next, &rx_queue) { 1896 struct rx_desc *rx_desc; 1897 struct rx_agg *agg; 1898 int len_used = 0; 1899 struct urb *urb; 1900 u8 *rx_data; 1901 1902 list_del_init(cursor); 1903 1904 agg = list_entry(cursor, struct rx_agg, list); 1905 urb = agg->urb; 1906 if (urb->actual_length < ETH_ZLEN) 1907 goto submit; 1908 1909 rx_desc = agg->head; 1910 rx_data = agg->head; 1911 len_used += sizeof(struct rx_desc); 1912 1913 while (urb->actual_length > len_used) { 1914 struct net_device *netdev = tp->netdev; 1915 struct net_device_stats *stats = &netdev->stats; 1916 unsigned int pkt_len; 1917 struct sk_buff *skb; 1918 1919 /* limite the skb numbers for rx_queue */ 1920 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000)) 1921 break; 1922 1923 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1924 if (pkt_len < ETH_ZLEN) 1925 break; 1926 1927 len_used += pkt_len; 1928 if (urb->actual_length < len_used) 1929 break; 1930 1931 pkt_len -= ETH_FCS_LEN; 1932 rx_data += sizeof(struct rx_desc); 1933 1934 skb = napi_alloc_skb(napi, pkt_len); 1935 if (!skb) { 1936 stats->rx_dropped++; 1937 goto find_next_rx; 1938 } 1939 1940 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 1941 memcpy(skb->data, rx_data, pkt_len); 1942 skb_put(skb, pkt_len); 1943 skb->protocol = eth_type_trans(skb, netdev); 1944 rtl_rx_vlan_tag(rx_desc, skb); 1945 if (work_done < budget) { 1946 napi_gro_receive(napi, skb); 1947 work_done++; 1948 stats->rx_packets++; 1949 stats->rx_bytes += pkt_len; 1950 } else { 1951 __skb_queue_tail(&tp->rx_queue, skb); 1952 } 1953 1954 find_next_rx: 1955 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN); 1956 rx_desc = (struct rx_desc *)rx_data; 1957 len_used = (int)(rx_data - (u8 *)agg->head); 1958 len_used += sizeof(struct rx_desc); 1959 } 1960 1961 submit: 1962 if (!ret) { 1963 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1964 } else { 1965 urb->actual_length = 0; 1966 list_add_tail(&agg->list, next); 1967 } 1968 } 1969 1970 if (!list_empty(&rx_queue)) { 1971 spin_lock_irqsave(&tp->rx_lock, flags); 1972 list_splice_tail(&rx_queue, &tp->rx_done); 1973 spin_unlock_irqrestore(&tp->rx_lock, flags); 1974 } 1975 1976 out1: 1977 return work_done; 1978 } 1979 1980 static void tx_bottom(struct r8152 *tp) 1981 { 1982 int res; 1983 1984 do { 1985 struct tx_agg *agg; 1986 1987 if (skb_queue_empty(&tp->tx_queue)) 1988 break; 1989 1990 agg = r8152_get_tx_agg(tp); 1991 if (!agg) 1992 break; 1993 1994 res = r8152_tx_agg_fill(tp, agg); 1995 if (res) { 1996 struct net_device *netdev = tp->netdev; 1997 1998 if (res == -ENODEV) { 1999 set_bit(RTL8152_UNPLUG, &tp->flags); 2000 netif_device_detach(netdev); 2001 } else { 2002 struct net_device_stats *stats = &netdev->stats; 2003 unsigned long flags; 2004 2005 netif_warn(tp, tx_err, netdev, 2006 "failed tx_urb %d\n", res); 2007 stats->tx_dropped += agg->skb_num; 2008 2009 spin_lock_irqsave(&tp->tx_lock, flags); 2010 list_add_tail(&agg->list, &tp->tx_free); 2011 spin_unlock_irqrestore(&tp->tx_lock, flags); 2012 } 2013 } 2014 } while (res == 0); 2015 } 2016 2017 static void bottom_half(struct r8152 *tp) 2018 { 2019 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2020 return; 2021 2022 if (!test_bit(WORK_ENABLE, &tp->flags)) 2023 return; 2024 2025 /* When link down, the driver would cancel all bulks. */ 2026 /* This avoid the re-submitting bulk */ 2027 if (!netif_carrier_ok(tp->netdev)) 2028 return; 2029 2030 clear_bit(SCHEDULE_NAPI, &tp->flags); 2031 2032 tx_bottom(tp); 2033 } 2034 2035 static int r8152_poll(struct napi_struct *napi, int budget) 2036 { 2037 struct r8152 *tp = container_of(napi, struct r8152, napi); 2038 int work_done; 2039 2040 work_done = rx_bottom(tp, budget); 2041 bottom_half(tp); 2042 2043 if (work_done < budget) { 2044 if (!napi_complete_done(napi, work_done)) 2045 goto out; 2046 if (!list_empty(&tp->rx_done)) 2047 napi_schedule(napi); 2048 else if (!skb_queue_empty(&tp->tx_queue) && 2049 !list_empty(&tp->tx_free)) 2050 napi_schedule(napi); 2051 } 2052 2053 out: 2054 return work_done; 2055 } 2056 2057 static 2058 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 2059 { 2060 int ret; 2061 2062 /* The rx would be stopped, so skip submitting */ 2063 if (test_bit(RTL8152_UNPLUG, &tp->flags) || 2064 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) 2065 return 0; 2066 2067 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 2068 agg->head, agg_buf_sz, 2069 (usb_complete_t)read_bulk_callback, agg); 2070 2071 ret = usb_submit_urb(agg->urb, mem_flags); 2072 if (ret == -ENODEV) { 2073 set_bit(RTL8152_UNPLUG, &tp->flags); 2074 netif_device_detach(tp->netdev); 2075 } else if (ret) { 2076 struct urb *urb = agg->urb; 2077 unsigned long flags; 2078 2079 urb->actual_length = 0; 2080 spin_lock_irqsave(&tp->rx_lock, flags); 2081 list_add_tail(&agg->list, &tp->rx_done); 2082 spin_unlock_irqrestore(&tp->rx_lock, flags); 2083 2084 netif_err(tp, rx_err, tp->netdev, 2085 "Couldn't submit rx[%p], ret = %d\n", agg, ret); 2086 2087 napi_schedule(&tp->napi); 2088 } 2089 2090 return ret; 2091 } 2092 2093 static void rtl_drop_queued_tx(struct r8152 *tp) 2094 { 2095 struct net_device_stats *stats = &tp->netdev->stats; 2096 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 2097 struct sk_buff *skb; 2098 2099 if (skb_queue_empty(tx_queue)) 2100 return; 2101 2102 __skb_queue_head_init(&skb_head); 2103 spin_lock_bh(&tx_queue->lock); 2104 skb_queue_splice_init(tx_queue, &skb_head); 2105 spin_unlock_bh(&tx_queue->lock); 2106 2107 while ((skb = __skb_dequeue(&skb_head))) { 2108 dev_kfree_skb(skb); 2109 stats->tx_dropped++; 2110 } 2111 } 2112 2113 static void rtl8152_tx_timeout(struct net_device *netdev) 2114 { 2115 struct r8152 *tp = netdev_priv(netdev); 2116 2117 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 2118 2119 usb_queue_reset_device(tp->intf); 2120 } 2121 2122 static void rtl8152_set_rx_mode(struct net_device *netdev) 2123 { 2124 struct r8152 *tp = netdev_priv(netdev); 2125 2126 if (netif_carrier_ok(netdev)) { 2127 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2128 schedule_delayed_work(&tp->schedule, 0); 2129 } 2130 } 2131 2132 static void _rtl8152_set_rx_mode(struct net_device *netdev) 2133 { 2134 struct r8152 *tp = netdev_priv(netdev); 2135 u32 mc_filter[2]; /* Multicast hash filter */ 2136 __le32 tmp[2]; 2137 u32 ocp_data; 2138 2139 netif_stop_queue(netdev); 2140 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2141 ocp_data &= ~RCR_ACPT_ALL; 2142 ocp_data |= RCR_AB | RCR_APM; 2143 2144 if (netdev->flags & IFF_PROMISC) { 2145 /* Unconditionally log net taps. */ 2146 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 2147 ocp_data |= RCR_AM | RCR_AAP; 2148 mc_filter[1] = 0xffffffff; 2149 mc_filter[0] = 0xffffffff; 2150 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 2151 (netdev->flags & IFF_ALLMULTI)) { 2152 /* Too many to filter perfectly -- accept all multicasts. */ 2153 ocp_data |= RCR_AM; 2154 mc_filter[1] = 0xffffffff; 2155 mc_filter[0] = 0xffffffff; 2156 } else { 2157 struct netdev_hw_addr *ha; 2158 2159 mc_filter[1] = 0; 2160 mc_filter[0] = 0; 2161 netdev_for_each_mc_addr(ha, netdev) { 2162 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2163 2164 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2165 ocp_data |= RCR_AM; 2166 } 2167 } 2168 2169 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 2170 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 2171 2172 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 2173 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2174 netif_wake_queue(netdev); 2175 } 2176 2177 static netdev_features_t 2178 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 2179 netdev_features_t features) 2180 { 2181 u32 mss = skb_shinfo(skb)->gso_size; 2182 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 2183 int offset = skb_transport_offset(skb); 2184 2185 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) 2186 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2187 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 2188 features &= ~NETIF_F_GSO_MASK; 2189 2190 return features; 2191 } 2192 2193 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 2194 struct net_device *netdev) 2195 { 2196 struct r8152 *tp = netdev_priv(netdev); 2197 2198 skb_tx_timestamp(skb); 2199 2200 skb_queue_tail(&tp->tx_queue, skb); 2201 2202 if (!list_empty(&tp->tx_free)) { 2203 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2204 set_bit(SCHEDULE_NAPI, &tp->flags); 2205 schedule_delayed_work(&tp->schedule, 0); 2206 } else { 2207 usb_mark_last_busy(tp->udev); 2208 napi_schedule(&tp->napi); 2209 } 2210 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 2211 netif_stop_queue(netdev); 2212 } 2213 2214 return NETDEV_TX_OK; 2215 } 2216 2217 static void r8152b_reset_packet_filter(struct r8152 *tp) 2218 { 2219 u32 ocp_data; 2220 2221 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 2222 ocp_data &= ~FMC_FCR_MCU_EN; 2223 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2224 ocp_data |= FMC_FCR_MCU_EN; 2225 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2226 } 2227 2228 static void rtl8152_nic_reset(struct r8152 *tp) 2229 { 2230 int i; 2231 2232 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 2233 2234 for (i = 0; i < 1000; i++) { 2235 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 2236 break; 2237 usleep_range(100, 400); 2238 } 2239 } 2240 2241 static void set_tx_qlen(struct r8152 *tp) 2242 { 2243 struct net_device *netdev = tp->netdev; 2244 2245 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN + 2246 sizeof(struct tx_desc)); 2247 } 2248 2249 static inline u8 rtl8152_get_speed(struct r8152 *tp) 2250 { 2251 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 2252 } 2253 2254 static void rtl_set_eee_plus(struct r8152 *tp) 2255 { 2256 u32 ocp_data; 2257 u8 speed; 2258 2259 speed = rtl8152_get_speed(tp); 2260 if (speed & _10bps) { 2261 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2262 ocp_data |= EEEP_CR_EEEP_TX; 2263 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2264 } else { 2265 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2266 ocp_data &= ~EEEP_CR_EEEP_TX; 2267 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2268 } 2269 } 2270 2271 static void rxdy_gated_en(struct r8152 *tp, bool enable) 2272 { 2273 u32 ocp_data; 2274 2275 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 2276 if (enable) 2277 ocp_data |= RXDY_GATED_EN; 2278 else 2279 ocp_data &= ~RXDY_GATED_EN; 2280 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 2281 } 2282 2283 static int rtl_start_rx(struct r8152 *tp) 2284 { 2285 int i, ret = 0; 2286 2287 INIT_LIST_HEAD(&tp->rx_done); 2288 for (i = 0; i < RTL8152_MAX_RX; i++) { 2289 INIT_LIST_HEAD(&tp->rx_info[i].list); 2290 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 2291 if (ret) 2292 break; 2293 } 2294 2295 if (ret && ++i < RTL8152_MAX_RX) { 2296 struct list_head rx_queue; 2297 unsigned long flags; 2298 2299 INIT_LIST_HEAD(&rx_queue); 2300 2301 do { 2302 struct rx_agg *agg = &tp->rx_info[i++]; 2303 struct urb *urb = agg->urb; 2304 2305 urb->actual_length = 0; 2306 list_add_tail(&agg->list, &rx_queue); 2307 } while (i < RTL8152_MAX_RX); 2308 2309 spin_lock_irqsave(&tp->rx_lock, flags); 2310 list_splice_tail(&rx_queue, &tp->rx_done); 2311 spin_unlock_irqrestore(&tp->rx_lock, flags); 2312 } 2313 2314 return ret; 2315 } 2316 2317 static int rtl_stop_rx(struct r8152 *tp) 2318 { 2319 int i; 2320 2321 for (i = 0; i < RTL8152_MAX_RX; i++) 2322 usb_kill_urb(tp->rx_info[i].urb); 2323 2324 while (!skb_queue_empty(&tp->rx_queue)) 2325 dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); 2326 2327 return 0; 2328 } 2329 2330 static int rtl_enable(struct r8152 *tp) 2331 { 2332 u32 ocp_data; 2333 2334 r8152b_reset_packet_filter(tp); 2335 2336 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2337 ocp_data |= CR_RE | CR_TE; 2338 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2339 2340 rxdy_gated_en(tp, false); 2341 2342 return 0; 2343 } 2344 2345 static int rtl8152_enable(struct r8152 *tp) 2346 { 2347 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2348 return -ENODEV; 2349 2350 set_tx_qlen(tp); 2351 rtl_set_eee_plus(tp); 2352 2353 return rtl_enable(tp); 2354 } 2355 2356 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) 2357 { 2358 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, 2359 OWN_UPDATE | OWN_CLEAR); 2360 } 2361 2362 static void r8153_set_rx_early_timeout(struct r8152 *tp) 2363 { 2364 u32 ocp_data = tp->coalesce / 8; 2365 2366 switch (tp->version) { 2367 case RTL_VER_03: 2368 case RTL_VER_04: 2369 case RTL_VER_05: 2370 case RTL_VER_06: 2371 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2372 ocp_data); 2373 break; 2374 2375 case RTL_VER_08: 2376 case RTL_VER_09: 2377 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout 2378 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns. 2379 */ 2380 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2381 128 / 8); 2382 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, 2383 ocp_data); 2384 r8153b_rx_agg_chg_indicate(tp); 2385 break; 2386 2387 default: 2388 break; 2389 } 2390 } 2391 2392 static void r8153_set_rx_early_size(struct r8152 *tp) 2393 { 2394 u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu); 2395 2396 switch (tp->version) { 2397 case RTL_VER_03: 2398 case RTL_VER_04: 2399 case RTL_VER_05: 2400 case RTL_VER_06: 2401 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2402 ocp_data / 4); 2403 break; 2404 case RTL_VER_08: 2405 case RTL_VER_09: 2406 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2407 ocp_data / 8); 2408 r8153b_rx_agg_chg_indicate(tp); 2409 break; 2410 default: 2411 WARN_ON_ONCE(1); 2412 break; 2413 } 2414 } 2415 2416 static int rtl8153_enable(struct r8152 *tp) 2417 { 2418 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2419 return -ENODEV; 2420 2421 set_tx_qlen(tp); 2422 rtl_set_eee_plus(tp); 2423 r8153_set_rx_early_timeout(tp); 2424 r8153_set_rx_early_size(tp); 2425 2426 return rtl_enable(tp); 2427 } 2428 2429 static void rtl_disable(struct r8152 *tp) 2430 { 2431 u32 ocp_data; 2432 int i; 2433 2434 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2435 rtl_drop_queued_tx(tp); 2436 return; 2437 } 2438 2439 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2440 ocp_data &= ~RCR_ACPT_ALL; 2441 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2442 2443 rtl_drop_queued_tx(tp); 2444 2445 for (i = 0; i < RTL8152_MAX_TX; i++) 2446 usb_kill_urb(tp->tx_info[i].urb); 2447 2448 rxdy_gated_en(tp, true); 2449 2450 for (i = 0; i < 1000; i++) { 2451 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2452 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2453 break; 2454 usleep_range(1000, 2000); 2455 } 2456 2457 for (i = 0; i < 1000; i++) { 2458 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2459 break; 2460 usleep_range(1000, 2000); 2461 } 2462 2463 rtl_stop_rx(tp); 2464 2465 rtl8152_nic_reset(tp); 2466 } 2467 2468 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2469 { 2470 u32 ocp_data; 2471 2472 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2473 if (enable) 2474 ocp_data |= POWER_CUT; 2475 else 2476 ocp_data &= ~POWER_CUT; 2477 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2478 2479 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2480 ocp_data &= ~RESUME_INDICATE; 2481 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2482 } 2483 2484 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 2485 { 2486 u32 ocp_data; 2487 2488 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2489 if (enable) 2490 ocp_data |= CPCR_RX_VLAN; 2491 else 2492 ocp_data &= ~CPCR_RX_VLAN; 2493 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2494 } 2495 2496 static int rtl8152_set_features(struct net_device *dev, 2497 netdev_features_t features) 2498 { 2499 netdev_features_t changed = features ^ dev->features; 2500 struct r8152 *tp = netdev_priv(dev); 2501 int ret; 2502 2503 ret = usb_autopm_get_interface(tp->intf); 2504 if (ret < 0) 2505 goto out; 2506 2507 mutex_lock(&tp->control); 2508 2509 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 2510 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2511 rtl_rx_vlan_en(tp, true); 2512 else 2513 rtl_rx_vlan_en(tp, false); 2514 } 2515 2516 mutex_unlock(&tp->control); 2517 2518 usb_autopm_put_interface(tp->intf); 2519 2520 out: 2521 return ret; 2522 } 2523 2524 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2525 2526 static u32 __rtl_get_wol(struct r8152 *tp) 2527 { 2528 u32 ocp_data; 2529 u32 wolopts = 0; 2530 2531 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2532 if (ocp_data & LINK_ON_WAKE_EN) 2533 wolopts |= WAKE_PHY; 2534 2535 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2536 if (ocp_data & UWF_EN) 2537 wolopts |= WAKE_UCAST; 2538 if (ocp_data & BWF_EN) 2539 wolopts |= WAKE_BCAST; 2540 if (ocp_data & MWF_EN) 2541 wolopts |= WAKE_MCAST; 2542 2543 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2544 if (ocp_data & MAGIC_EN) 2545 wolopts |= WAKE_MAGIC; 2546 2547 return wolopts; 2548 } 2549 2550 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2551 { 2552 u32 ocp_data; 2553 2554 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2555 2556 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2557 ocp_data &= ~LINK_ON_WAKE_EN; 2558 if (wolopts & WAKE_PHY) 2559 ocp_data |= LINK_ON_WAKE_EN; 2560 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2561 2562 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2563 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); 2564 if (wolopts & WAKE_UCAST) 2565 ocp_data |= UWF_EN; 2566 if (wolopts & WAKE_BCAST) 2567 ocp_data |= BWF_EN; 2568 if (wolopts & WAKE_MCAST) 2569 ocp_data |= MWF_EN; 2570 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2571 2572 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2573 2574 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2575 ocp_data &= ~MAGIC_EN; 2576 if (wolopts & WAKE_MAGIC) 2577 ocp_data |= MAGIC_EN; 2578 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2579 2580 if (wolopts & WAKE_ANY) 2581 device_set_wakeup_enable(&tp->udev->dev, true); 2582 else 2583 device_set_wakeup_enable(&tp->udev->dev, false); 2584 } 2585 2586 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable) 2587 { 2588 /* MAC clock speed down */ 2589 if (enable) { 2590 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 2591 ALDPS_SPDWN_RATIO); 2592 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 2593 EEE_SPDWN_RATIO); 2594 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 2595 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | 2596 U1U2_SPDWN_EN | L1_SPDWN_EN); 2597 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 2598 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | 2599 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN | 2600 TP1000_SPDWN_EN); 2601 } else { 2602 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); 2603 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); 2604 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); 2605 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); 2606 } 2607 } 2608 2609 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2610 { 2611 u8 u1u2[8]; 2612 2613 if (enable) 2614 memset(u1u2, 0xff, sizeof(u1u2)); 2615 else 2616 memset(u1u2, 0x00, sizeof(u1u2)); 2617 2618 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2619 } 2620 2621 static void r8153b_u1u2en(struct r8152 *tp, bool enable) 2622 { 2623 u32 ocp_data; 2624 2625 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); 2626 if (enable) 2627 ocp_data |= LPM_U1U2_EN; 2628 else 2629 ocp_data &= ~LPM_U1U2_EN; 2630 2631 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); 2632 } 2633 2634 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2635 { 2636 u32 ocp_data; 2637 2638 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2639 if (enable) 2640 ocp_data |= U2P3_ENABLE; 2641 else 2642 ocp_data &= ~U2P3_ENABLE; 2643 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2644 } 2645 2646 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear) 2647 { 2648 u32 ocp_data; 2649 2650 ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS); 2651 ocp_data &= ~clear; 2652 ocp_data |= set; 2653 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data); 2654 } 2655 2656 static void r8153b_green_en(struct r8152 *tp, bool enable) 2657 { 2658 u16 data; 2659 2660 if (enable) { 2661 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ 2662 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ 2663 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ 2664 } else { 2665 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ 2666 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ 2667 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ 2668 } 2669 2670 data = sram_read(tp, SRAM_GREEN_CFG); 2671 data |= GREEN_ETH_EN; 2672 sram_write(tp, SRAM_GREEN_CFG, data); 2673 2674 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0); 2675 } 2676 2677 static u16 r8153_phy_status(struct r8152 *tp, u16 desired) 2678 { 2679 u16 data; 2680 int i; 2681 2682 for (i = 0; i < 500; i++) { 2683 data = ocp_reg_read(tp, OCP_PHY_STATUS); 2684 data &= PHY_STAT_MASK; 2685 if (desired) { 2686 if (data == desired) 2687 break; 2688 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN || 2689 data == PHY_STAT_EXT_INIT) { 2690 break; 2691 } 2692 2693 msleep(20); 2694 } 2695 2696 return data; 2697 } 2698 2699 static void r8153b_ups_en(struct r8152 *tp, bool enable) 2700 { 2701 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); 2702 2703 if (enable) { 2704 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; 2705 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2706 2707 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 2708 ocp_data |= BIT(0); 2709 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 2710 } else { 2711 u16 data; 2712 2713 ocp_data &= ~(UPS_EN | USP_PREWAKE); 2714 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2715 2716 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 2717 ocp_data &= ~BIT(0); 2718 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 2719 2720 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2721 ocp_data &= ~PCUT_STATUS; 2722 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2723 2724 data = r8153_phy_status(tp, 0); 2725 2726 switch (data) { 2727 case PHY_STAT_PWRDN: 2728 case PHY_STAT_EXT_INIT: 2729 r8153b_green_en(tp, 2730 test_bit(GREEN_ETHERNET, &tp->flags)); 2731 2732 data = r8152_mdio_read(tp, MII_BMCR); 2733 data &= ~BMCR_PDOWN; 2734 data |= BMCR_RESET; 2735 r8152_mdio_write(tp, MII_BMCR, data); 2736 2737 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 2738 2739 default: 2740 if (data != PHY_STAT_LAN_ON) 2741 netif_warn(tp, link, tp->netdev, 2742 "PHY not ready"); 2743 break; 2744 } 2745 } 2746 } 2747 2748 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2749 { 2750 u32 ocp_data; 2751 2752 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2753 if (enable) 2754 ocp_data |= PWR_EN | PHASE2_EN; 2755 else 2756 ocp_data &= ~(PWR_EN | PHASE2_EN); 2757 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2758 2759 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2760 ocp_data &= ~PCUT_STATUS; 2761 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2762 } 2763 2764 static void r8153b_power_cut_en(struct r8152 *tp, bool enable) 2765 { 2766 u32 ocp_data; 2767 2768 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2769 if (enable) 2770 ocp_data |= PWR_EN | PHASE2_EN; 2771 else 2772 ocp_data &= ~PWR_EN; 2773 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2774 2775 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2776 ocp_data &= ~PCUT_STATUS; 2777 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2778 } 2779 2780 static void r8153b_queue_wake(struct r8152 *tp, bool enable) 2781 { 2782 u32 ocp_data; 2783 2784 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a); 2785 if (enable) 2786 ocp_data |= BIT(0); 2787 else 2788 ocp_data &= ~BIT(0); 2789 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data); 2790 2791 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c); 2792 ocp_data &= ~BIT(0); 2793 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data); 2794 } 2795 2796 static bool rtl_can_wakeup(struct r8152 *tp) 2797 { 2798 struct usb_device *udev = tp->udev; 2799 2800 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); 2801 } 2802 2803 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 2804 { 2805 if (enable) { 2806 u32 ocp_data; 2807 2808 __rtl_set_wol(tp, WAKE_ANY); 2809 2810 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2811 2812 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2813 ocp_data |= LINK_OFF_WAKE_EN; 2814 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2815 2816 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2817 } else { 2818 u32 ocp_data; 2819 2820 __rtl_set_wol(tp, tp->saved_wolopts); 2821 2822 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2823 2824 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2825 ocp_data &= ~LINK_OFF_WAKE_EN; 2826 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2827 2828 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2829 } 2830 } 2831 2832 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) 2833 { 2834 if (enable) { 2835 r8153_u1u2en(tp, false); 2836 r8153_u2p3en(tp, false); 2837 r8153_mac_clk_spd(tp, true); 2838 rtl_runtime_suspend_enable(tp, true); 2839 } else { 2840 rtl_runtime_suspend_enable(tp, false); 2841 r8153_mac_clk_spd(tp, false); 2842 2843 switch (tp->version) { 2844 case RTL_VER_03: 2845 case RTL_VER_04: 2846 break; 2847 case RTL_VER_05: 2848 case RTL_VER_06: 2849 default: 2850 r8153_u2p3en(tp, true); 2851 break; 2852 } 2853 2854 r8153_u1u2en(tp, true); 2855 } 2856 } 2857 2858 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable) 2859 { 2860 if (enable) { 2861 r8153b_queue_wake(tp, true); 2862 r8153b_u1u2en(tp, false); 2863 r8153_u2p3en(tp, false); 2864 rtl_runtime_suspend_enable(tp, true); 2865 r8153b_ups_en(tp, true); 2866 } else { 2867 r8153b_ups_en(tp, false); 2868 r8153b_queue_wake(tp, false); 2869 rtl_runtime_suspend_enable(tp, false); 2870 r8153_u2p3en(tp, true); 2871 r8153b_u1u2en(tp, true); 2872 } 2873 } 2874 2875 static void r8153_teredo_off(struct r8152 *tp) 2876 { 2877 u32 ocp_data; 2878 2879 switch (tp->version) { 2880 case RTL_VER_01: 2881 case RTL_VER_02: 2882 case RTL_VER_03: 2883 case RTL_VER_04: 2884 case RTL_VER_05: 2885 case RTL_VER_06: 2886 case RTL_VER_07: 2887 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2888 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | 2889 OOB_TEREDO_EN); 2890 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2891 break; 2892 2893 case RTL_VER_08: 2894 case RTL_VER_09: 2895 /* The bit 0 ~ 7 are relative with teredo settings. They are 2896 * W1C (write 1 to clear), so set all 1 to disable it. 2897 */ 2898 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); 2899 break; 2900 2901 default: 2902 break; 2903 } 2904 2905 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 2906 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 2907 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 2908 } 2909 2910 static void rtl_reset_bmu(struct r8152 *tp) 2911 { 2912 u32 ocp_data; 2913 2914 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); 2915 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 2916 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2917 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 2918 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2919 } 2920 2921 static void r8152_aldps_en(struct r8152 *tp, bool enable) 2922 { 2923 if (enable) { 2924 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 2925 LINKENA | DIS_SDSAVE); 2926 } else { 2927 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | 2928 DIS_SDSAVE); 2929 msleep(20); 2930 } 2931 } 2932 2933 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 2934 { 2935 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 2936 ocp_reg_write(tp, OCP_EEE_DATA, reg); 2937 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 2938 } 2939 2940 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 2941 { 2942 u16 data; 2943 2944 r8152_mmd_indirect(tp, dev, reg); 2945 data = ocp_reg_read(tp, OCP_EEE_DATA); 2946 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 2947 2948 return data; 2949 } 2950 2951 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 2952 { 2953 r8152_mmd_indirect(tp, dev, reg); 2954 ocp_reg_write(tp, OCP_EEE_DATA, data); 2955 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 2956 } 2957 2958 static void r8152_eee_en(struct r8152 *tp, bool enable) 2959 { 2960 u16 config1, config2, config3; 2961 u32 ocp_data; 2962 2963 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 2964 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 2965 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 2966 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 2967 2968 if (enable) { 2969 ocp_data |= EEE_RX_EN | EEE_TX_EN; 2970 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 2971 config1 |= sd_rise_time(1); 2972 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 2973 config3 |= fast_snr(42); 2974 } else { 2975 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 2976 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 2977 RX_QUIET_EN); 2978 config1 |= sd_rise_time(7); 2979 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 2980 config3 |= fast_snr(511); 2981 } 2982 2983 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 2984 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 2985 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 2986 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 2987 } 2988 2989 static void r8152b_enable_eee(struct r8152 *tp) 2990 { 2991 r8152_eee_en(tp, true); 2992 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); 2993 } 2994 2995 static void r8152b_enable_fc(struct r8152 *tp) 2996 { 2997 u16 anar; 2998 2999 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3000 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 3001 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3002 } 3003 3004 static void rtl8152_disable(struct r8152 *tp) 3005 { 3006 r8152_aldps_en(tp, false); 3007 rtl_disable(tp); 3008 r8152_aldps_en(tp, true); 3009 } 3010 3011 static void r8152b_hw_phy_cfg(struct r8152 *tp) 3012 { 3013 r8152b_enable_eee(tp); 3014 r8152_aldps_en(tp, true); 3015 r8152b_enable_fc(tp); 3016 3017 set_bit(PHY_RESET, &tp->flags); 3018 } 3019 3020 static void r8152b_exit_oob(struct r8152 *tp) 3021 { 3022 u32 ocp_data; 3023 int i; 3024 3025 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3026 ocp_data &= ~RCR_ACPT_ALL; 3027 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3028 3029 rxdy_gated_en(tp, true); 3030 r8153_teredo_off(tp); 3031 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3032 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 3033 3034 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3035 ocp_data &= ~NOW_IS_OOB; 3036 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3037 3038 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3039 ocp_data &= ~MCU_BORW_EN; 3040 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3041 3042 for (i = 0; i < 1000; i++) { 3043 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3044 if (ocp_data & LINK_LIST_READY) 3045 break; 3046 usleep_range(1000, 2000); 3047 } 3048 3049 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3050 ocp_data |= RE_INIT_LL; 3051 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3052 3053 for (i = 0; i < 1000; i++) { 3054 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3055 if (ocp_data & LINK_LIST_READY) 3056 break; 3057 usleep_range(1000, 2000); 3058 } 3059 3060 rtl8152_nic_reset(tp); 3061 3062 /* rx share fifo credit full threshold */ 3063 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3064 3065 if (tp->udev->speed == USB_SPEED_FULL || 3066 tp->udev->speed == USB_SPEED_LOW) { 3067 /* rx share fifo credit near full threshold */ 3068 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3069 RXFIFO_THR2_FULL); 3070 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3071 RXFIFO_THR3_FULL); 3072 } else { 3073 /* rx share fifo credit near full threshold */ 3074 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3075 RXFIFO_THR2_HIGH); 3076 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3077 RXFIFO_THR3_HIGH); 3078 } 3079 3080 /* TX share fifo free credit full threshold */ 3081 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 3082 3083 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 3084 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 3085 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 3086 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 3087 3088 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3089 3090 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3091 3092 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3093 ocp_data |= TCR0_AUTO_FIFO; 3094 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3095 } 3096 3097 static void r8152b_enter_oob(struct r8152 *tp) 3098 { 3099 u32 ocp_data; 3100 int i; 3101 3102 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3103 ocp_data &= ~NOW_IS_OOB; 3104 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3105 3106 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 3107 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 3108 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 3109 3110 rtl_disable(tp); 3111 3112 for (i = 0; i < 1000; i++) { 3113 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3114 if (ocp_data & LINK_LIST_READY) 3115 break; 3116 usleep_range(1000, 2000); 3117 } 3118 3119 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3120 ocp_data |= RE_INIT_LL; 3121 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3122 3123 for (i = 0; i < 1000; i++) { 3124 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3125 if (ocp_data & LINK_LIST_READY) 3126 break; 3127 usleep_range(1000, 2000); 3128 } 3129 3130 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3131 3132 rtl_rx_vlan_en(tp, true); 3133 3134 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 3135 ocp_data |= ALDPS_PROXY_MODE; 3136 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 3137 3138 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3139 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3140 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3141 3142 rxdy_gated_en(tp, false); 3143 3144 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3145 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3146 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3147 } 3148 3149 static int r8153_patch_request(struct r8152 *tp, bool request) 3150 { 3151 u16 data; 3152 int i; 3153 3154 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD); 3155 if (request) 3156 data |= PATCH_REQUEST; 3157 else 3158 data &= ~PATCH_REQUEST; 3159 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); 3160 3161 for (i = 0; request && i < 5000; i++) { 3162 usleep_range(1000, 2000); 3163 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY) 3164 break; 3165 } 3166 3167 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) { 3168 netif_err(tp, drv, tp->netdev, "patch request fail\n"); 3169 r8153_patch_request(tp, false); 3170 return -ETIME; 3171 } else { 3172 return 0; 3173 } 3174 } 3175 3176 static void r8153_aldps_en(struct r8152 *tp, bool enable) 3177 { 3178 u16 data; 3179 3180 data = ocp_reg_read(tp, OCP_POWER_CFG); 3181 if (enable) { 3182 data |= EN_ALDPS; 3183 ocp_reg_write(tp, OCP_POWER_CFG, data); 3184 } else { 3185 int i; 3186 3187 data &= ~EN_ALDPS; 3188 ocp_reg_write(tp, OCP_POWER_CFG, data); 3189 for (i = 0; i < 20; i++) { 3190 usleep_range(1000, 2000); 3191 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) 3192 break; 3193 } 3194 } 3195 } 3196 3197 static void r8153b_aldps_en(struct r8152 *tp, bool enable) 3198 { 3199 r8153_aldps_en(tp, enable); 3200 3201 if (enable) 3202 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0); 3203 else 3204 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS); 3205 } 3206 3207 static void r8153_eee_en(struct r8152 *tp, bool enable) 3208 { 3209 u32 ocp_data; 3210 u16 config; 3211 3212 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3213 config = ocp_reg_read(tp, OCP_EEE_CFG); 3214 3215 if (enable) { 3216 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3217 config |= EEE10_EN; 3218 } else { 3219 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3220 config &= ~EEE10_EN; 3221 } 3222 3223 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3224 ocp_reg_write(tp, OCP_EEE_CFG, config); 3225 } 3226 3227 static void r8153b_eee_en(struct r8152 *tp, bool enable) 3228 { 3229 r8153_eee_en(tp, enable); 3230 3231 if (enable) 3232 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0); 3233 else 3234 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE); 3235 } 3236 3237 static void r8153b_enable_fc(struct r8152 *tp) 3238 { 3239 r8152b_enable_fc(tp); 3240 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0); 3241 } 3242 3243 static void r8153_hw_phy_cfg(struct r8152 *tp) 3244 { 3245 u32 ocp_data; 3246 u16 data; 3247 3248 /* disable ALDPS before updating the PHY parameters */ 3249 r8153_aldps_en(tp, false); 3250 3251 /* disable EEE before updating the PHY parameters */ 3252 r8153_eee_en(tp, false); 3253 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3254 3255 if (tp->version == RTL_VER_03) { 3256 data = ocp_reg_read(tp, OCP_EEE_CFG); 3257 data &= ~CTAP_SHORT_EN; 3258 ocp_reg_write(tp, OCP_EEE_CFG, data); 3259 } 3260 3261 data = ocp_reg_read(tp, OCP_POWER_CFG); 3262 data |= EEE_CLKDIV_EN; 3263 ocp_reg_write(tp, OCP_POWER_CFG, data); 3264 3265 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3266 data |= EN_10M_BGOFF; 3267 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3268 data = ocp_reg_read(tp, OCP_POWER_CFG); 3269 data |= EN_10M_PLLOFF; 3270 ocp_reg_write(tp, OCP_POWER_CFG, data); 3271 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 3272 3273 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3274 ocp_data |= PFM_PWM_SWITCH; 3275 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3276 3277 /* Enable LPF corner auto tune */ 3278 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 3279 3280 /* Adjust 10M Amplitude */ 3281 sram_write(tp, SRAM_10M_AMP1, 0x00af); 3282 sram_write(tp, SRAM_10M_AMP2, 0x0208); 3283 3284 r8153_eee_en(tp, true); 3285 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3286 3287 r8153_aldps_en(tp, true); 3288 r8152b_enable_fc(tp); 3289 3290 switch (tp->version) { 3291 case RTL_VER_03: 3292 case RTL_VER_04: 3293 break; 3294 case RTL_VER_05: 3295 case RTL_VER_06: 3296 default: 3297 r8153_u2p3en(tp, true); 3298 break; 3299 } 3300 3301 set_bit(PHY_RESET, &tp->flags); 3302 } 3303 3304 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) 3305 { 3306 u32 ocp_data; 3307 3308 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr); 3309 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD); 3310 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */ 3311 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA); 3312 3313 return ocp_data; 3314 } 3315 3316 static void r8153b_hw_phy_cfg(struct r8152 *tp) 3317 { 3318 u32 ocp_data, ups_flags = 0; 3319 u16 data; 3320 3321 /* disable ALDPS before updating the PHY parameters */ 3322 r8153b_aldps_en(tp, false); 3323 3324 /* disable EEE before updating the PHY parameters */ 3325 r8153b_eee_en(tp, false); 3326 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3327 3328 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); 3329 3330 data = sram_read(tp, SRAM_GREEN_CFG); 3331 data |= R_TUNE_EN; 3332 sram_write(tp, SRAM_GREEN_CFG, data); 3333 data = ocp_reg_read(tp, OCP_NCTL_CFG); 3334 data |= PGA_RETURN_EN; 3335 ocp_reg_write(tp, OCP_NCTL_CFG, data); 3336 3337 /* ADC Bias Calibration: 3338 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake 3339 * bit (bit3) to rebuild the real 16-bit data. Write the data to the 3340 * ADC ioffset. 3341 */ 3342 ocp_data = r8152_efuse_read(tp, 0x7d); 3343 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); 3344 if (data != 0xffff) 3345 ocp_reg_write(tp, OCP_ADC_IOFFSET, data); 3346 3347 /* ups mode tx-link-pulse timing adjustment: 3348 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] 3349 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt 3350 */ 3351 ocp_data = ocp_reg_read(tp, 0xc426); 3352 ocp_data &= 0x3fff; 3353 if (ocp_data) { 3354 u32 swr_cnt_1ms_ini; 3355 3356 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; 3357 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); 3358 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; 3359 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); 3360 } 3361 3362 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3363 ocp_data |= PFM_PWM_SWITCH; 3364 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3365 3366 /* Advnace EEE */ 3367 if (!r8153_patch_request(tp, true)) { 3368 data = ocp_reg_read(tp, OCP_POWER_CFG); 3369 data |= EEE_CLKDIV_EN; 3370 ocp_reg_write(tp, OCP_POWER_CFG, data); 3371 3372 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3373 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV; 3374 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3375 3376 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); 3377 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5)); 3378 3379 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV | 3380 UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN | 3381 UPS_FLAGS_EEE_PLLOFF_GIGA; 3382 3383 r8153_patch_request(tp, false); 3384 } 3385 3386 r8153b_ups_flags_w1w0(tp, ups_flags, 0); 3387 3388 r8153b_eee_en(tp, true); 3389 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3390 3391 r8153b_aldps_en(tp, true); 3392 r8153b_enable_fc(tp); 3393 r8153_u2p3en(tp, true); 3394 3395 set_bit(PHY_RESET, &tp->flags); 3396 } 3397 3398 static void r8153_first_init(struct r8152 *tp) 3399 { 3400 u32 ocp_data; 3401 int i; 3402 3403 r8153_mac_clk_spd(tp, false); 3404 rxdy_gated_en(tp, true); 3405 r8153_teredo_off(tp); 3406 3407 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3408 ocp_data &= ~RCR_ACPT_ALL; 3409 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3410 3411 rtl8152_nic_reset(tp); 3412 rtl_reset_bmu(tp); 3413 3414 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3415 ocp_data &= ~NOW_IS_OOB; 3416 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3417 3418 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3419 ocp_data &= ~MCU_BORW_EN; 3420 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3421 3422 for (i = 0; i < 1000; i++) { 3423 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3424 if (ocp_data & LINK_LIST_READY) 3425 break; 3426 usleep_range(1000, 2000); 3427 } 3428 3429 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3430 ocp_data |= RE_INIT_LL; 3431 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3432 3433 for (i = 0; i < 1000; i++) { 3434 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3435 if (ocp_data & LINK_LIST_READY) 3436 break; 3437 usleep_range(1000, 2000); 3438 } 3439 3440 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3441 3442 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3443 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3444 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 3445 3446 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3447 ocp_data |= TCR0_AUTO_FIFO; 3448 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3449 3450 rtl8152_nic_reset(tp); 3451 3452 /* rx share fifo credit full threshold */ 3453 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3454 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 3455 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 3456 /* TX share fifo free credit full threshold */ 3457 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 3458 } 3459 3460 static void r8153_enter_oob(struct r8152 *tp) 3461 { 3462 u32 ocp_data; 3463 int i; 3464 3465 r8153_mac_clk_spd(tp, true); 3466 3467 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3468 ocp_data &= ~NOW_IS_OOB; 3469 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3470 3471 rtl_disable(tp); 3472 rtl_reset_bmu(tp); 3473 3474 for (i = 0; i < 1000; i++) { 3475 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3476 if (ocp_data & LINK_LIST_READY) 3477 break; 3478 usleep_range(1000, 2000); 3479 } 3480 3481 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3482 ocp_data |= RE_INIT_LL; 3483 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3484 3485 for (i = 0; i < 1000; i++) { 3486 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3487 if (ocp_data & LINK_LIST_READY) 3488 break; 3489 usleep_range(1000, 2000); 3490 } 3491 3492 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3493 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3494 3495 switch (tp->version) { 3496 case RTL_VER_03: 3497 case RTL_VER_04: 3498 case RTL_VER_05: 3499 case RTL_VER_06: 3500 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 3501 ocp_data &= ~TEREDO_WAKE_MASK; 3502 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 3503 break; 3504 3505 case RTL_VER_08: 3506 case RTL_VER_09: 3507 /* Clear teredo wake event. bit[15:8] is the teredo wakeup 3508 * type. Set it to zero. bits[7:0] are the W1C bits about 3509 * the events. Set them to all 1 to clear them. 3510 */ 3511 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); 3512 break; 3513 3514 default: 3515 break; 3516 } 3517 3518 rtl_rx_vlan_en(tp, true); 3519 3520 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 3521 ocp_data |= ALDPS_PROXY_MODE; 3522 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 3523 3524 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3525 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3526 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3527 3528 rxdy_gated_en(tp, false); 3529 3530 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3531 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3532 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3533 } 3534 3535 static void rtl8153_disable(struct r8152 *tp) 3536 { 3537 r8153_aldps_en(tp, false); 3538 rtl_disable(tp); 3539 rtl_reset_bmu(tp); 3540 r8153_aldps_en(tp, true); 3541 } 3542 3543 static void rtl8153b_disable(struct r8152 *tp) 3544 { 3545 r8153b_aldps_en(tp, false); 3546 rtl_disable(tp); 3547 rtl_reset_bmu(tp); 3548 r8153b_aldps_en(tp, true); 3549 } 3550 3551 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 3552 { 3553 u16 bmcr, anar, gbcr; 3554 enum spd_duplex speed_duplex; 3555 int ret = 0; 3556 3557 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3558 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 3559 ADVERTISE_100HALF | ADVERTISE_100FULL); 3560 if (tp->mii.supports_gmii) { 3561 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 3562 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 3563 } else { 3564 gbcr = 0; 3565 } 3566 3567 if (autoneg == AUTONEG_DISABLE) { 3568 if (speed == SPEED_10) { 3569 bmcr = 0; 3570 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3571 speed_duplex = FORCE_10M_HALF; 3572 } else if (speed == SPEED_100) { 3573 bmcr = BMCR_SPEED100; 3574 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3575 speed_duplex = FORCE_100M_HALF; 3576 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3577 bmcr = BMCR_SPEED1000; 3578 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3579 speed_duplex = NWAY_1000M_FULL; 3580 } else { 3581 ret = -EINVAL; 3582 goto out; 3583 } 3584 3585 if (duplex == DUPLEX_FULL) { 3586 bmcr |= BMCR_FULLDPLX; 3587 if (speed != SPEED_1000) 3588 speed_duplex++; 3589 } 3590 } else { 3591 if (speed == SPEED_10) { 3592 if (duplex == DUPLEX_FULL) { 3593 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3594 speed_duplex = NWAY_10M_FULL; 3595 } else { 3596 anar |= ADVERTISE_10HALF; 3597 speed_duplex = NWAY_10M_HALF; 3598 } 3599 } else if (speed == SPEED_100) { 3600 if (duplex == DUPLEX_FULL) { 3601 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3602 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3603 speed_duplex = NWAY_100M_FULL; 3604 } else { 3605 anar |= ADVERTISE_10HALF; 3606 anar |= ADVERTISE_100HALF; 3607 speed_duplex = NWAY_100M_HALF; 3608 } 3609 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3610 if (duplex == DUPLEX_FULL) { 3611 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3612 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3613 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3614 } else { 3615 anar |= ADVERTISE_10HALF; 3616 anar |= ADVERTISE_100HALF; 3617 gbcr |= ADVERTISE_1000HALF; 3618 } 3619 speed_duplex = NWAY_1000M_FULL; 3620 } else { 3621 ret = -EINVAL; 3622 goto out; 3623 } 3624 3625 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 3626 } 3627 3628 if (test_and_clear_bit(PHY_RESET, &tp->flags)) 3629 bmcr |= BMCR_RESET; 3630 3631 if (tp->mii.supports_gmii) 3632 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 3633 3634 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3635 r8152_mdio_write(tp, MII_BMCR, bmcr); 3636 3637 switch (tp->version) { 3638 case RTL_VER_08: 3639 case RTL_VER_09: 3640 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex), 3641 UPS_FLAGS_SPEED_MASK); 3642 break; 3643 3644 default: 3645 break; 3646 } 3647 3648 if (bmcr & BMCR_RESET) { 3649 int i; 3650 3651 for (i = 0; i < 50; i++) { 3652 msleep(20); 3653 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 3654 break; 3655 } 3656 } 3657 3658 out: 3659 return ret; 3660 } 3661 3662 static void rtl8152_up(struct r8152 *tp) 3663 { 3664 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3665 return; 3666 3667 r8152_aldps_en(tp, false); 3668 r8152b_exit_oob(tp); 3669 r8152_aldps_en(tp, true); 3670 } 3671 3672 static void rtl8152_down(struct r8152 *tp) 3673 { 3674 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3675 rtl_drop_queued_tx(tp); 3676 return; 3677 } 3678 3679 r8152_power_cut_en(tp, false); 3680 r8152_aldps_en(tp, false); 3681 r8152b_enter_oob(tp); 3682 r8152_aldps_en(tp, true); 3683 } 3684 3685 static void rtl8153_up(struct r8152 *tp) 3686 { 3687 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3688 return; 3689 3690 r8153_u1u2en(tp, false); 3691 r8153_u2p3en(tp, false); 3692 r8153_aldps_en(tp, false); 3693 r8153_first_init(tp); 3694 r8153_aldps_en(tp, true); 3695 3696 switch (tp->version) { 3697 case RTL_VER_03: 3698 case RTL_VER_04: 3699 break; 3700 case RTL_VER_05: 3701 case RTL_VER_06: 3702 default: 3703 r8153_u2p3en(tp, true); 3704 break; 3705 } 3706 3707 r8153_u1u2en(tp, true); 3708 } 3709 3710 static void rtl8153_down(struct r8152 *tp) 3711 { 3712 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3713 rtl_drop_queued_tx(tp); 3714 return; 3715 } 3716 3717 r8153_u1u2en(tp, false); 3718 r8153_u2p3en(tp, false); 3719 r8153_power_cut_en(tp, false); 3720 r8153_aldps_en(tp, false); 3721 r8153_enter_oob(tp); 3722 r8153_aldps_en(tp, true); 3723 } 3724 3725 static void rtl8153b_up(struct r8152 *tp) 3726 { 3727 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3728 return; 3729 3730 r8153b_u1u2en(tp, false); 3731 r8153_u2p3en(tp, false); 3732 r8153b_aldps_en(tp, false); 3733 3734 r8153_first_init(tp); 3735 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); 3736 3737 r8153b_aldps_en(tp, true); 3738 r8153_u2p3en(tp, true); 3739 r8153b_u1u2en(tp, true); 3740 } 3741 3742 static void rtl8153b_down(struct r8152 *tp) 3743 { 3744 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3745 rtl_drop_queued_tx(tp); 3746 return; 3747 } 3748 3749 r8153b_u1u2en(tp, false); 3750 r8153_u2p3en(tp, false); 3751 r8153b_power_cut_en(tp, false); 3752 r8153b_aldps_en(tp, false); 3753 r8153_enter_oob(tp); 3754 r8153b_aldps_en(tp, true); 3755 } 3756 3757 static bool rtl8152_in_nway(struct r8152 *tp) 3758 { 3759 u16 nway_state; 3760 3761 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); 3762 tp->ocp_base = 0x2000; 3763 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ 3764 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); 3765 3766 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ 3767 if (nway_state & 0xc000) 3768 return false; 3769 else 3770 return true; 3771 } 3772 3773 static bool rtl8153_in_nway(struct r8152 *tp) 3774 { 3775 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; 3776 3777 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) 3778 return false; 3779 else 3780 return true; 3781 } 3782 3783 static void set_carrier(struct r8152 *tp) 3784 { 3785 struct net_device *netdev = tp->netdev; 3786 struct napi_struct *napi = &tp->napi; 3787 u8 speed; 3788 3789 speed = rtl8152_get_speed(tp); 3790 3791 if (speed & LINK_STATUS) { 3792 if (!netif_carrier_ok(netdev)) { 3793 tp->rtl_ops.enable(tp); 3794 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 3795 netif_stop_queue(netdev); 3796 napi_disable(napi); 3797 netif_carrier_on(netdev); 3798 rtl_start_rx(tp); 3799 napi_enable(&tp->napi); 3800 netif_wake_queue(netdev); 3801 netif_info(tp, link, netdev, "carrier on\n"); 3802 } else if (netif_queue_stopped(netdev) && 3803 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) { 3804 netif_wake_queue(netdev); 3805 } 3806 } else { 3807 if (netif_carrier_ok(netdev)) { 3808 netif_carrier_off(netdev); 3809 napi_disable(napi); 3810 tp->rtl_ops.disable(tp); 3811 napi_enable(napi); 3812 netif_info(tp, link, netdev, "carrier off\n"); 3813 } 3814 } 3815 } 3816 3817 static void rtl_work_func_t(struct work_struct *work) 3818 { 3819 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 3820 3821 /* If the device is unplugged or !netif_running(), the workqueue 3822 * doesn't need to wake the device, and could return directly. 3823 */ 3824 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) 3825 return; 3826 3827 if (usb_autopm_get_interface(tp->intf) < 0) 3828 return; 3829 3830 if (!test_bit(WORK_ENABLE, &tp->flags)) 3831 goto out1; 3832 3833 if (!mutex_trylock(&tp->control)) { 3834 schedule_delayed_work(&tp->schedule, 0); 3835 goto out1; 3836 } 3837 3838 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) 3839 set_carrier(tp); 3840 3841 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) 3842 _rtl8152_set_rx_mode(tp->netdev); 3843 3844 /* don't schedule napi before linking */ 3845 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) && 3846 netif_carrier_ok(tp->netdev)) 3847 napi_schedule(&tp->napi); 3848 3849 mutex_unlock(&tp->control); 3850 3851 out1: 3852 usb_autopm_put_interface(tp->intf); 3853 } 3854 3855 static void rtl_hw_phy_work_func_t(struct work_struct *work) 3856 { 3857 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); 3858 3859 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3860 return; 3861 3862 if (usb_autopm_get_interface(tp->intf) < 0) 3863 return; 3864 3865 mutex_lock(&tp->control); 3866 3867 tp->rtl_ops.hw_phy_cfg(tp); 3868 3869 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex); 3870 3871 mutex_unlock(&tp->control); 3872 3873 usb_autopm_put_interface(tp->intf); 3874 } 3875 3876 #ifdef CONFIG_PM_SLEEP 3877 static int rtl_notifier(struct notifier_block *nb, unsigned long action, 3878 void *data) 3879 { 3880 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); 3881 3882 switch (action) { 3883 case PM_HIBERNATION_PREPARE: 3884 case PM_SUSPEND_PREPARE: 3885 usb_autopm_get_interface(tp->intf); 3886 break; 3887 3888 case PM_POST_HIBERNATION: 3889 case PM_POST_SUSPEND: 3890 usb_autopm_put_interface(tp->intf); 3891 break; 3892 3893 case PM_POST_RESTORE: 3894 case PM_RESTORE_PREPARE: 3895 default: 3896 break; 3897 } 3898 3899 return NOTIFY_DONE; 3900 } 3901 #endif 3902 3903 static int rtl8152_open(struct net_device *netdev) 3904 { 3905 struct r8152 *tp = netdev_priv(netdev); 3906 int res = 0; 3907 3908 res = alloc_all_mem(tp); 3909 if (res) 3910 goto out; 3911 3912 res = usb_autopm_get_interface(tp->intf); 3913 if (res < 0) 3914 goto out_free; 3915 3916 mutex_lock(&tp->control); 3917 3918 tp->rtl_ops.up(tp); 3919 3920 netif_carrier_off(netdev); 3921 netif_start_queue(netdev); 3922 set_bit(WORK_ENABLE, &tp->flags); 3923 3924 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3925 if (res) { 3926 if (res == -ENODEV) 3927 netif_device_detach(tp->netdev); 3928 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 3929 res); 3930 goto out_unlock; 3931 } 3932 napi_enable(&tp->napi); 3933 3934 mutex_unlock(&tp->control); 3935 3936 usb_autopm_put_interface(tp->intf); 3937 #ifdef CONFIG_PM_SLEEP 3938 tp->pm_notifier.notifier_call = rtl_notifier; 3939 register_pm_notifier(&tp->pm_notifier); 3940 #endif 3941 return 0; 3942 3943 out_unlock: 3944 mutex_unlock(&tp->control); 3945 usb_autopm_put_interface(tp->intf); 3946 out_free: 3947 free_all_mem(tp); 3948 out: 3949 return res; 3950 } 3951 3952 static int rtl8152_close(struct net_device *netdev) 3953 { 3954 struct r8152 *tp = netdev_priv(netdev); 3955 int res = 0; 3956 3957 #ifdef CONFIG_PM_SLEEP 3958 unregister_pm_notifier(&tp->pm_notifier); 3959 #endif 3960 napi_disable(&tp->napi); 3961 clear_bit(WORK_ENABLE, &tp->flags); 3962 usb_kill_urb(tp->intr_urb); 3963 cancel_delayed_work_sync(&tp->schedule); 3964 netif_stop_queue(netdev); 3965 3966 res = usb_autopm_get_interface(tp->intf); 3967 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { 3968 rtl_drop_queued_tx(tp); 3969 rtl_stop_rx(tp); 3970 } else { 3971 mutex_lock(&tp->control); 3972 3973 tp->rtl_ops.down(tp); 3974 3975 mutex_unlock(&tp->control); 3976 3977 usb_autopm_put_interface(tp->intf); 3978 } 3979 3980 free_all_mem(tp); 3981 3982 return res; 3983 } 3984 3985 static void rtl_tally_reset(struct r8152 *tp) 3986 { 3987 u32 ocp_data; 3988 3989 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 3990 ocp_data |= TALLY_RESET; 3991 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 3992 } 3993 3994 static void r8152b_init(struct r8152 *tp) 3995 { 3996 u32 ocp_data; 3997 u16 data; 3998 3999 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4000 return; 4001 4002 data = r8152_mdio_read(tp, MII_BMCR); 4003 if (data & BMCR_PDOWN) { 4004 data &= ~BMCR_PDOWN; 4005 r8152_mdio_write(tp, MII_BMCR, data); 4006 } 4007 4008 r8152_aldps_en(tp, false); 4009 4010 if (tp->version == RTL_VER_01) { 4011 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4012 ocp_data &= ~LED_MODE_MASK; 4013 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4014 } 4015 4016 r8152_power_cut_en(tp, false); 4017 4018 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 4019 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 4020 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 4021 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 4022 ocp_data &= ~MCU_CLK_RATIO_MASK; 4023 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 4024 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 4025 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 4026 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 4027 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 4028 4029 rtl_tally_reset(tp); 4030 4031 /* enable rx aggregation */ 4032 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4033 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4034 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4035 } 4036 4037 static void r8153_init(struct r8152 *tp) 4038 { 4039 u32 ocp_data; 4040 u16 data; 4041 int i; 4042 4043 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4044 return; 4045 4046 r8153_u1u2en(tp, false); 4047 4048 for (i = 0; i < 500; i++) { 4049 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4050 AUTOLOAD_DONE) 4051 break; 4052 msleep(20); 4053 } 4054 4055 data = r8153_phy_status(tp, 0); 4056 4057 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 4058 tp->version == RTL_VER_05) 4059 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 4060 4061 data = r8152_mdio_read(tp, MII_BMCR); 4062 if (data & BMCR_PDOWN) { 4063 data &= ~BMCR_PDOWN; 4064 r8152_mdio_write(tp, MII_BMCR, data); 4065 } 4066 4067 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4068 4069 r8153_u2p3en(tp, false); 4070 4071 if (tp->version == RTL_VER_04) { 4072 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 4073 ocp_data &= ~pwd_dn_scale_mask; 4074 ocp_data |= pwd_dn_scale(96); 4075 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 4076 4077 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 4078 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 4079 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 4080 } else if (tp->version == RTL_VER_05) { 4081 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 4082 ocp_data &= ~ECM_ALDPS; 4083 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 4084 4085 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4086 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4087 ocp_data &= ~DYNAMIC_BURST; 4088 else 4089 ocp_data |= DYNAMIC_BURST; 4090 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4091 } else if (tp->version == RTL_VER_06) { 4092 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4093 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4094 ocp_data &= ~DYNAMIC_BURST; 4095 else 4096 ocp_data |= DYNAMIC_BURST; 4097 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4098 } 4099 4100 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 4101 ocp_data |= EP4_FULL_FC; 4102 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 4103 4104 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 4105 ocp_data &= ~TIMER11_EN; 4106 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 4107 4108 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4109 ocp_data &= ~LED_MODE_MASK; 4110 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4111 4112 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 4113 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) 4114 ocp_data |= LPM_TIMER_500MS; 4115 else 4116 ocp_data |= LPM_TIMER_500US; 4117 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 4118 4119 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 4120 ocp_data &= ~SEN_VAL_MASK; 4121 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 4122 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 4123 4124 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 4125 4126 r8153_power_cut_en(tp, false); 4127 r8153_u1u2en(tp, true); 4128 r8153_mac_clk_spd(tp, false); 4129 usb_enable_lpm(tp->udev); 4130 4131 /* rx aggregation */ 4132 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4133 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4134 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4135 4136 rtl_tally_reset(tp); 4137 4138 switch (tp->udev->speed) { 4139 case USB_SPEED_SUPER: 4140 case USB_SPEED_SUPER_PLUS: 4141 tp->coalesce = COALESCE_SUPER; 4142 break; 4143 case USB_SPEED_HIGH: 4144 tp->coalesce = COALESCE_HIGH; 4145 break; 4146 default: 4147 tp->coalesce = COALESCE_SLOW; 4148 break; 4149 } 4150 } 4151 4152 static void r8153b_init(struct r8152 *tp) 4153 { 4154 u32 ocp_data; 4155 u16 data; 4156 int i; 4157 4158 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4159 return; 4160 4161 r8153b_u1u2en(tp, false); 4162 4163 for (i = 0; i < 500; i++) { 4164 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4165 AUTOLOAD_DONE) 4166 break; 4167 msleep(20); 4168 } 4169 4170 data = r8153_phy_status(tp, 0); 4171 4172 data = r8152_mdio_read(tp, MII_BMCR); 4173 if (data & BMCR_PDOWN) { 4174 data &= ~BMCR_PDOWN; 4175 r8152_mdio_write(tp, MII_BMCR, data); 4176 } 4177 4178 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4179 4180 r8153_u2p3en(tp, false); 4181 4182 /* MSC timer = 0xfff * 8ms = 32760 ms */ 4183 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 4184 4185 /* U1/U2/L1 idle timer. 500 us */ 4186 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 4187 4188 r8153b_power_cut_en(tp, false); 4189 r8153b_ups_en(tp, false); 4190 r8153b_queue_wake(tp, false); 4191 rtl_runtime_suspend_enable(tp, false); 4192 r8153b_u1u2en(tp, true); 4193 usb_enable_lpm(tp->udev); 4194 4195 /* MAC clock speed down */ 4196 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); 4197 ocp_data |= MAC_CLK_SPDWN_EN; 4198 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); 4199 4200 set_bit(GREEN_ETHERNET, &tp->flags); 4201 4202 /* rx aggregation */ 4203 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4204 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4205 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4206 4207 rtl_tally_reset(tp); 4208 4209 tp->coalesce = 15000; /* 15 us */ 4210 } 4211 4212 static int rtl8152_pre_reset(struct usb_interface *intf) 4213 { 4214 struct r8152 *tp = usb_get_intfdata(intf); 4215 struct net_device *netdev; 4216 4217 if (!tp) 4218 return 0; 4219 4220 netdev = tp->netdev; 4221 if (!netif_running(netdev)) 4222 return 0; 4223 4224 netif_stop_queue(netdev); 4225 napi_disable(&tp->napi); 4226 clear_bit(WORK_ENABLE, &tp->flags); 4227 usb_kill_urb(tp->intr_urb); 4228 cancel_delayed_work_sync(&tp->schedule); 4229 if (netif_carrier_ok(netdev)) { 4230 mutex_lock(&tp->control); 4231 tp->rtl_ops.disable(tp); 4232 mutex_unlock(&tp->control); 4233 } 4234 4235 return 0; 4236 } 4237 4238 static int rtl8152_post_reset(struct usb_interface *intf) 4239 { 4240 struct r8152 *tp = usb_get_intfdata(intf); 4241 struct net_device *netdev; 4242 4243 if (!tp) 4244 return 0; 4245 4246 netdev = tp->netdev; 4247 if (!netif_running(netdev)) 4248 return 0; 4249 4250 set_bit(WORK_ENABLE, &tp->flags); 4251 if (netif_carrier_ok(netdev)) { 4252 mutex_lock(&tp->control); 4253 tp->rtl_ops.enable(tp); 4254 rtl_start_rx(tp); 4255 rtl8152_set_rx_mode(netdev); 4256 mutex_unlock(&tp->control); 4257 } 4258 4259 napi_enable(&tp->napi); 4260 netif_wake_queue(netdev); 4261 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 4262 4263 if (!list_empty(&tp->rx_done)) 4264 napi_schedule(&tp->napi); 4265 4266 return 0; 4267 } 4268 4269 static bool delay_autosuspend(struct r8152 *tp) 4270 { 4271 bool sw_linking = !!netif_carrier_ok(tp->netdev); 4272 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); 4273 4274 /* This means a linking change occurs and the driver doesn't detect it, 4275 * yet. If the driver has disabled tx/rx and hw is linking on, the 4276 * device wouldn't wake up by receiving any packet. 4277 */ 4278 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) 4279 return true; 4280 4281 /* If the linking down is occurred by nway, the device may miss the 4282 * linking change event. And it wouldn't wake when linking on. 4283 */ 4284 if (!sw_linking && tp->rtl_ops.in_nway(tp)) 4285 return true; 4286 else if (!skb_queue_empty(&tp->tx_queue)) 4287 return true; 4288 else 4289 return false; 4290 } 4291 4292 static int rtl8152_runtime_resume(struct r8152 *tp) 4293 { 4294 struct net_device *netdev = tp->netdev; 4295 4296 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4297 struct napi_struct *napi = &tp->napi; 4298 4299 tp->rtl_ops.autosuspend_en(tp, false); 4300 napi_disable(napi); 4301 set_bit(WORK_ENABLE, &tp->flags); 4302 4303 if (netif_carrier_ok(netdev)) { 4304 if (rtl8152_get_speed(tp) & LINK_STATUS) { 4305 rtl_start_rx(tp); 4306 } else { 4307 netif_carrier_off(netdev); 4308 tp->rtl_ops.disable(tp); 4309 netif_info(tp, link, netdev, "linking down\n"); 4310 } 4311 } 4312 4313 napi_enable(napi); 4314 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4315 smp_mb__after_atomic(); 4316 4317 if (!list_empty(&tp->rx_done)) 4318 napi_schedule(&tp->napi); 4319 4320 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4321 } else { 4322 if (netdev->flags & IFF_UP) 4323 tp->rtl_ops.autosuspend_en(tp, false); 4324 4325 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4326 } 4327 4328 return 0; 4329 } 4330 4331 static int rtl8152_system_resume(struct r8152 *tp) 4332 { 4333 struct net_device *netdev = tp->netdev; 4334 4335 netif_device_attach(netdev); 4336 4337 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4338 tp->rtl_ops.up(tp); 4339 netif_carrier_off(netdev); 4340 set_bit(WORK_ENABLE, &tp->flags); 4341 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4342 } 4343 4344 return 0; 4345 } 4346 4347 static int rtl8152_runtime_suspend(struct r8152 *tp) 4348 { 4349 struct net_device *netdev = tp->netdev; 4350 int ret = 0; 4351 4352 set_bit(SELECTIVE_SUSPEND, &tp->flags); 4353 smp_mb__after_atomic(); 4354 4355 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4356 u32 rcr = 0; 4357 4358 if (netif_carrier_ok(netdev)) { 4359 u32 ocp_data; 4360 4361 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 4362 ocp_data = rcr & ~RCR_ACPT_ALL; 4363 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 4364 rxdy_gated_en(tp, true); 4365 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 4366 PLA_OOB_CTRL); 4367 if (!(ocp_data & RXFIFO_EMPTY)) { 4368 rxdy_gated_en(tp, false); 4369 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4370 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4371 smp_mb__after_atomic(); 4372 ret = -EBUSY; 4373 goto out1; 4374 } 4375 } 4376 4377 clear_bit(WORK_ENABLE, &tp->flags); 4378 usb_kill_urb(tp->intr_urb); 4379 4380 tp->rtl_ops.autosuspend_en(tp, true); 4381 4382 if (netif_carrier_ok(netdev)) { 4383 struct napi_struct *napi = &tp->napi; 4384 4385 napi_disable(napi); 4386 rtl_stop_rx(tp); 4387 rxdy_gated_en(tp, false); 4388 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4389 napi_enable(napi); 4390 } 4391 4392 if (delay_autosuspend(tp)) { 4393 rtl8152_runtime_resume(tp); 4394 ret = -EBUSY; 4395 } 4396 } 4397 4398 out1: 4399 return ret; 4400 } 4401 4402 static int rtl8152_system_suspend(struct r8152 *tp) 4403 { 4404 struct net_device *netdev = tp->netdev; 4405 int ret = 0; 4406 4407 netif_device_detach(netdev); 4408 4409 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4410 struct napi_struct *napi = &tp->napi; 4411 4412 clear_bit(WORK_ENABLE, &tp->flags); 4413 usb_kill_urb(tp->intr_urb); 4414 napi_disable(napi); 4415 cancel_delayed_work_sync(&tp->schedule); 4416 tp->rtl_ops.down(tp); 4417 napi_enable(napi); 4418 } 4419 4420 return ret; 4421 } 4422 4423 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 4424 { 4425 struct r8152 *tp = usb_get_intfdata(intf); 4426 int ret; 4427 4428 mutex_lock(&tp->control); 4429 4430 if (PMSG_IS_AUTO(message)) 4431 ret = rtl8152_runtime_suspend(tp); 4432 else 4433 ret = rtl8152_system_suspend(tp); 4434 4435 mutex_unlock(&tp->control); 4436 4437 return ret; 4438 } 4439 4440 static int rtl8152_resume(struct usb_interface *intf) 4441 { 4442 struct r8152 *tp = usb_get_intfdata(intf); 4443 int ret; 4444 4445 mutex_lock(&tp->control); 4446 4447 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) 4448 ret = rtl8152_runtime_resume(tp); 4449 else 4450 ret = rtl8152_system_resume(tp); 4451 4452 mutex_unlock(&tp->control); 4453 4454 return ret; 4455 } 4456 4457 static int rtl8152_reset_resume(struct usb_interface *intf) 4458 { 4459 struct r8152 *tp = usb_get_intfdata(intf); 4460 4461 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4462 mutex_lock(&tp->control); 4463 tp->rtl_ops.init(tp); 4464 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 4465 mutex_unlock(&tp->control); 4466 return rtl8152_resume(intf); 4467 } 4468 4469 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4470 { 4471 struct r8152 *tp = netdev_priv(dev); 4472 4473 if (usb_autopm_get_interface(tp->intf) < 0) 4474 return; 4475 4476 if (!rtl_can_wakeup(tp)) { 4477 wol->supported = 0; 4478 wol->wolopts = 0; 4479 } else { 4480 mutex_lock(&tp->control); 4481 wol->supported = WAKE_ANY; 4482 wol->wolopts = __rtl_get_wol(tp); 4483 mutex_unlock(&tp->control); 4484 } 4485 4486 usb_autopm_put_interface(tp->intf); 4487 } 4488 4489 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4490 { 4491 struct r8152 *tp = netdev_priv(dev); 4492 int ret; 4493 4494 if (!rtl_can_wakeup(tp)) 4495 return -EOPNOTSUPP; 4496 4497 ret = usb_autopm_get_interface(tp->intf); 4498 if (ret < 0) 4499 goto out_set_wol; 4500 4501 mutex_lock(&tp->control); 4502 4503 __rtl_set_wol(tp, wol->wolopts); 4504 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 4505 4506 mutex_unlock(&tp->control); 4507 4508 usb_autopm_put_interface(tp->intf); 4509 4510 out_set_wol: 4511 return ret; 4512 } 4513 4514 static u32 rtl8152_get_msglevel(struct net_device *dev) 4515 { 4516 struct r8152 *tp = netdev_priv(dev); 4517 4518 return tp->msg_enable; 4519 } 4520 4521 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 4522 { 4523 struct r8152 *tp = netdev_priv(dev); 4524 4525 tp->msg_enable = value; 4526 } 4527 4528 static void rtl8152_get_drvinfo(struct net_device *netdev, 4529 struct ethtool_drvinfo *info) 4530 { 4531 struct r8152 *tp = netdev_priv(netdev); 4532 4533 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 4534 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 4535 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 4536 } 4537 4538 static 4539 int rtl8152_get_link_ksettings(struct net_device *netdev, 4540 struct ethtool_link_ksettings *cmd) 4541 { 4542 struct r8152 *tp = netdev_priv(netdev); 4543 int ret; 4544 4545 if (!tp->mii.mdio_read) 4546 return -EOPNOTSUPP; 4547 4548 ret = usb_autopm_get_interface(tp->intf); 4549 if (ret < 0) 4550 goto out; 4551 4552 mutex_lock(&tp->control); 4553 4554 mii_ethtool_get_link_ksettings(&tp->mii, cmd); 4555 4556 mutex_unlock(&tp->control); 4557 4558 usb_autopm_put_interface(tp->intf); 4559 4560 out: 4561 return ret; 4562 } 4563 4564 static int rtl8152_set_link_ksettings(struct net_device *dev, 4565 const struct ethtool_link_ksettings *cmd) 4566 { 4567 struct r8152 *tp = netdev_priv(dev); 4568 int ret; 4569 4570 ret = usb_autopm_get_interface(tp->intf); 4571 if (ret < 0) 4572 goto out; 4573 4574 mutex_lock(&tp->control); 4575 4576 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, 4577 cmd->base.duplex); 4578 if (!ret) { 4579 tp->autoneg = cmd->base.autoneg; 4580 tp->speed = cmd->base.speed; 4581 tp->duplex = cmd->base.duplex; 4582 } 4583 4584 mutex_unlock(&tp->control); 4585 4586 usb_autopm_put_interface(tp->intf); 4587 4588 out: 4589 return ret; 4590 } 4591 4592 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 4593 "tx_packets", 4594 "rx_packets", 4595 "tx_errors", 4596 "rx_errors", 4597 "rx_missed", 4598 "align_errors", 4599 "tx_single_collisions", 4600 "tx_multi_collisions", 4601 "rx_unicast", 4602 "rx_broadcast", 4603 "rx_multicast", 4604 "tx_aborted", 4605 "tx_underrun", 4606 }; 4607 4608 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 4609 { 4610 switch (sset) { 4611 case ETH_SS_STATS: 4612 return ARRAY_SIZE(rtl8152_gstrings); 4613 default: 4614 return -EOPNOTSUPP; 4615 } 4616 } 4617 4618 static void rtl8152_get_ethtool_stats(struct net_device *dev, 4619 struct ethtool_stats *stats, u64 *data) 4620 { 4621 struct r8152 *tp = netdev_priv(dev); 4622 struct tally_counter tally; 4623 4624 if (usb_autopm_get_interface(tp->intf) < 0) 4625 return; 4626 4627 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 4628 4629 usb_autopm_put_interface(tp->intf); 4630 4631 data[0] = le64_to_cpu(tally.tx_packets); 4632 data[1] = le64_to_cpu(tally.rx_packets); 4633 data[2] = le64_to_cpu(tally.tx_errors); 4634 data[3] = le32_to_cpu(tally.rx_errors); 4635 data[4] = le16_to_cpu(tally.rx_missed); 4636 data[5] = le16_to_cpu(tally.align_errors); 4637 data[6] = le32_to_cpu(tally.tx_one_collision); 4638 data[7] = le32_to_cpu(tally.tx_multi_collision); 4639 data[8] = le64_to_cpu(tally.rx_unicast); 4640 data[9] = le64_to_cpu(tally.rx_broadcast); 4641 data[10] = le32_to_cpu(tally.rx_multicast); 4642 data[11] = le16_to_cpu(tally.tx_aborted); 4643 data[12] = le16_to_cpu(tally.tx_underrun); 4644 } 4645 4646 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4647 { 4648 switch (stringset) { 4649 case ETH_SS_STATS: 4650 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 4651 break; 4652 } 4653 } 4654 4655 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 4656 { 4657 u32 ocp_data, lp, adv, supported = 0; 4658 u16 val; 4659 4660 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 4661 supported = mmd_eee_cap_to_ethtool_sup_t(val); 4662 4663 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 4664 adv = mmd_eee_adv_to_ethtool_adv_t(val); 4665 4666 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 4667 lp = mmd_eee_adv_to_ethtool_adv_t(val); 4668 4669 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 4670 ocp_data &= EEE_RX_EN | EEE_TX_EN; 4671 4672 eee->eee_enabled = !!ocp_data; 4673 eee->eee_active = !!(supported & adv & lp); 4674 eee->supported = supported; 4675 eee->advertised = adv; 4676 eee->lp_advertised = lp; 4677 4678 return 0; 4679 } 4680 4681 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4682 { 4683 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4684 4685 r8152_eee_en(tp, eee->eee_enabled); 4686 4687 if (!eee->eee_enabled) 4688 val = 0; 4689 4690 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); 4691 4692 return 0; 4693 } 4694 4695 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 4696 { 4697 u32 ocp_data, lp, adv, supported = 0; 4698 u16 val; 4699 4700 val = ocp_reg_read(tp, OCP_EEE_ABLE); 4701 supported = mmd_eee_cap_to_ethtool_sup_t(val); 4702 4703 val = ocp_reg_read(tp, OCP_EEE_ADV); 4704 adv = mmd_eee_adv_to_ethtool_adv_t(val); 4705 4706 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 4707 lp = mmd_eee_adv_to_ethtool_adv_t(val); 4708 4709 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 4710 ocp_data &= EEE_RX_EN | EEE_TX_EN; 4711 4712 eee->eee_enabled = !!ocp_data; 4713 eee->eee_active = !!(supported & adv & lp); 4714 eee->supported = supported; 4715 eee->advertised = adv; 4716 eee->lp_advertised = lp; 4717 4718 return 0; 4719 } 4720 4721 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4722 { 4723 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4724 4725 r8153_eee_en(tp, eee->eee_enabled); 4726 4727 if (!eee->eee_enabled) 4728 val = 0; 4729 4730 ocp_reg_write(tp, OCP_EEE_ADV, val); 4731 4732 return 0; 4733 } 4734 4735 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4736 { 4737 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4738 4739 r8153b_eee_en(tp, eee->eee_enabled); 4740 4741 if (!eee->eee_enabled) 4742 val = 0; 4743 4744 ocp_reg_write(tp, OCP_EEE_ADV, val); 4745 4746 return 0; 4747 } 4748 4749 static int 4750 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) 4751 { 4752 struct r8152 *tp = netdev_priv(net); 4753 int ret; 4754 4755 ret = usb_autopm_get_interface(tp->intf); 4756 if (ret < 0) 4757 goto out; 4758 4759 mutex_lock(&tp->control); 4760 4761 ret = tp->rtl_ops.eee_get(tp, edata); 4762 4763 mutex_unlock(&tp->control); 4764 4765 usb_autopm_put_interface(tp->intf); 4766 4767 out: 4768 return ret; 4769 } 4770 4771 static int 4772 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) 4773 { 4774 struct r8152 *tp = netdev_priv(net); 4775 int ret; 4776 4777 ret = usb_autopm_get_interface(tp->intf); 4778 if (ret < 0) 4779 goto out; 4780 4781 mutex_lock(&tp->control); 4782 4783 ret = tp->rtl_ops.eee_set(tp, edata); 4784 if (!ret) 4785 ret = mii_nway_restart(&tp->mii); 4786 4787 mutex_unlock(&tp->control); 4788 4789 usb_autopm_put_interface(tp->intf); 4790 4791 out: 4792 return ret; 4793 } 4794 4795 static int rtl8152_nway_reset(struct net_device *dev) 4796 { 4797 struct r8152 *tp = netdev_priv(dev); 4798 int ret; 4799 4800 ret = usb_autopm_get_interface(tp->intf); 4801 if (ret < 0) 4802 goto out; 4803 4804 mutex_lock(&tp->control); 4805 4806 ret = mii_nway_restart(&tp->mii); 4807 4808 mutex_unlock(&tp->control); 4809 4810 usb_autopm_put_interface(tp->intf); 4811 4812 out: 4813 return ret; 4814 } 4815 4816 static int rtl8152_get_coalesce(struct net_device *netdev, 4817 struct ethtool_coalesce *coalesce) 4818 { 4819 struct r8152 *tp = netdev_priv(netdev); 4820 4821 switch (tp->version) { 4822 case RTL_VER_01: 4823 case RTL_VER_02: 4824 case RTL_VER_07: 4825 return -EOPNOTSUPP; 4826 default: 4827 break; 4828 } 4829 4830 coalesce->rx_coalesce_usecs = tp->coalesce; 4831 4832 return 0; 4833 } 4834 4835 static int rtl8152_set_coalesce(struct net_device *netdev, 4836 struct ethtool_coalesce *coalesce) 4837 { 4838 struct r8152 *tp = netdev_priv(netdev); 4839 int ret; 4840 4841 switch (tp->version) { 4842 case RTL_VER_01: 4843 case RTL_VER_02: 4844 case RTL_VER_07: 4845 return -EOPNOTSUPP; 4846 default: 4847 break; 4848 } 4849 4850 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) 4851 return -EINVAL; 4852 4853 ret = usb_autopm_get_interface(tp->intf); 4854 if (ret < 0) 4855 return ret; 4856 4857 mutex_lock(&tp->control); 4858 4859 if (tp->coalesce != coalesce->rx_coalesce_usecs) { 4860 tp->coalesce = coalesce->rx_coalesce_usecs; 4861 4862 if (netif_running(tp->netdev) && netif_carrier_ok(netdev)) 4863 r8153_set_rx_early_timeout(tp); 4864 } 4865 4866 mutex_unlock(&tp->control); 4867 4868 usb_autopm_put_interface(tp->intf); 4869 4870 return ret; 4871 } 4872 4873 static const struct ethtool_ops ops = { 4874 .get_drvinfo = rtl8152_get_drvinfo, 4875 .get_link = ethtool_op_get_link, 4876 .nway_reset = rtl8152_nway_reset, 4877 .get_msglevel = rtl8152_get_msglevel, 4878 .set_msglevel = rtl8152_set_msglevel, 4879 .get_wol = rtl8152_get_wol, 4880 .set_wol = rtl8152_set_wol, 4881 .get_strings = rtl8152_get_strings, 4882 .get_sset_count = rtl8152_get_sset_count, 4883 .get_ethtool_stats = rtl8152_get_ethtool_stats, 4884 .get_coalesce = rtl8152_get_coalesce, 4885 .set_coalesce = rtl8152_set_coalesce, 4886 .get_eee = rtl_ethtool_get_eee, 4887 .set_eee = rtl_ethtool_set_eee, 4888 .get_link_ksettings = rtl8152_get_link_ksettings, 4889 .set_link_ksettings = rtl8152_set_link_ksettings, 4890 }; 4891 4892 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 4893 { 4894 struct r8152 *tp = netdev_priv(netdev); 4895 struct mii_ioctl_data *data = if_mii(rq); 4896 int res; 4897 4898 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4899 return -ENODEV; 4900 4901 res = usb_autopm_get_interface(tp->intf); 4902 if (res < 0) 4903 goto out; 4904 4905 switch (cmd) { 4906 case SIOCGMIIPHY: 4907 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 4908 break; 4909 4910 case SIOCGMIIREG: 4911 mutex_lock(&tp->control); 4912 data->val_out = r8152_mdio_read(tp, data->reg_num); 4913 mutex_unlock(&tp->control); 4914 break; 4915 4916 case SIOCSMIIREG: 4917 if (!capable(CAP_NET_ADMIN)) { 4918 res = -EPERM; 4919 break; 4920 } 4921 mutex_lock(&tp->control); 4922 r8152_mdio_write(tp, data->reg_num, data->val_in); 4923 mutex_unlock(&tp->control); 4924 break; 4925 4926 default: 4927 res = -EOPNOTSUPP; 4928 } 4929 4930 usb_autopm_put_interface(tp->intf); 4931 4932 out: 4933 return res; 4934 } 4935 4936 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 4937 { 4938 struct r8152 *tp = netdev_priv(dev); 4939 int ret; 4940 4941 switch (tp->version) { 4942 case RTL_VER_01: 4943 case RTL_VER_02: 4944 case RTL_VER_07: 4945 dev->mtu = new_mtu; 4946 return 0; 4947 default: 4948 break; 4949 } 4950 4951 ret = usb_autopm_get_interface(tp->intf); 4952 if (ret < 0) 4953 return ret; 4954 4955 mutex_lock(&tp->control); 4956 4957 dev->mtu = new_mtu; 4958 4959 if (netif_running(dev)) { 4960 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 4961 4962 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms); 4963 4964 if (netif_carrier_ok(dev)) 4965 r8153_set_rx_early_size(tp); 4966 } 4967 4968 mutex_unlock(&tp->control); 4969 4970 usb_autopm_put_interface(tp->intf); 4971 4972 return ret; 4973 } 4974 4975 static const struct net_device_ops rtl8152_netdev_ops = { 4976 .ndo_open = rtl8152_open, 4977 .ndo_stop = rtl8152_close, 4978 .ndo_do_ioctl = rtl8152_ioctl, 4979 .ndo_start_xmit = rtl8152_start_xmit, 4980 .ndo_tx_timeout = rtl8152_tx_timeout, 4981 .ndo_set_features = rtl8152_set_features, 4982 .ndo_set_rx_mode = rtl8152_set_rx_mode, 4983 .ndo_set_mac_address = rtl8152_set_mac_address, 4984 .ndo_change_mtu = rtl8152_change_mtu, 4985 .ndo_validate_addr = eth_validate_addr, 4986 .ndo_features_check = rtl8152_features_check, 4987 }; 4988 4989 static void rtl8152_unload(struct r8152 *tp) 4990 { 4991 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4992 return; 4993 4994 if (tp->version != RTL_VER_01) 4995 r8152_power_cut_en(tp, true); 4996 } 4997 4998 static void rtl8153_unload(struct r8152 *tp) 4999 { 5000 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5001 return; 5002 5003 r8153_power_cut_en(tp, false); 5004 } 5005 5006 static void rtl8153b_unload(struct r8152 *tp) 5007 { 5008 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5009 return; 5010 5011 r8153b_power_cut_en(tp, false); 5012 } 5013 5014 static int rtl_ops_init(struct r8152 *tp) 5015 { 5016 struct rtl_ops *ops = &tp->rtl_ops; 5017 int ret = 0; 5018 5019 switch (tp->version) { 5020 case RTL_VER_01: 5021 case RTL_VER_02: 5022 case RTL_VER_07: 5023 ops->init = r8152b_init; 5024 ops->enable = rtl8152_enable; 5025 ops->disable = rtl8152_disable; 5026 ops->up = rtl8152_up; 5027 ops->down = rtl8152_down; 5028 ops->unload = rtl8152_unload; 5029 ops->eee_get = r8152_get_eee; 5030 ops->eee_set = r8152_set_eee; 5031 ops->in_nway = rtl8152_in_nway; 5032 ops->hw_phy_cfg = r8152b_hw_phy_cfg; 5033 ops->autosuspend_en = rtl_runtime_suspend_enable; 5034 break; 5035 5036 case RTL_VER_03: 5037 case RTL_VER_04: 5038 case RTL_VER_05: 5039 case RTL_VER_06: 5040 ops->init = r8153_init; 5041 ops->enable = rtl8153_enable; 5042 ops->disable = rtl8153_disable; 5043 ops->up = rtl8153_up; 5044 ops->down = rtl8153_down; 5045 ops->unload = rtl8153_unload; 5046 ops->eee_get = r8153_get_eee; 5047 ops->eee_set = r8153_set_eee; 5048 ops->in_nway = rtl8153_in_nway; 5049 ops->hw_phy_cfg = r8153_hw_phy_cfg; 5050 ops->autosuspend_en = rtl8153_runtime_enable; 5051 break; 5052 5053 case RTL_VER_08: 5054 case RTL_VER_09: 5055 ops->init = r8153b_init; 5056 ops->enable = rtl8153_enable; 5057 ops->disable = rtl8153b_disable; 5058 ops->up = rtl8153b_up; 5059 ops->down = rtl8153b_down; 5060 ops->unload = rtl8153b_unload; 5061 ops->eee_get = r8153_get_eee; 5062 ops->eee_set = r8153b_set_eee; 5063 ops->in_nway = rtl8153_in_nway; 5064 ops->hw_phy_cfg = r8153b_hw_phy_cfg; 5065 ops->autosuspend_en = rtl8153b_runtime_enable; 5066 break; 5067 5068 default: 5069 ret = -ENODEV; 5070 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 5071 break; 5072 } 5073 5074 return ret; 5075 } 5076 5077 static u8 rtl_get_version(struct usb_interface *intf) 5078 { 5079 struct usb_device *udev = interface_to_usbdev(intf); 5080 u32 ocp_data = 0; 5081 __le32 *tmp; 5082 u8 version; 5083 int ret; 5084 5085 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); 5086 if (!tmp) 5087 return 0; 5088 5089 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 5090 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 5091 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500); 5092 if (ret > 0) 5093 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK; 5094 5095 kfree(tmp); 5096 5097 switch (ocp_data) { 5098 case 0x4c00: 5099 version = RTL_VER_01; 5100 break; 5101 case 0x4c10: 5102 version = RTL_VER_02; 5103 break; 5104 case 0x5c00: 5105 version = RTL_VER_03; 5106 break; 5107 case 0x5c10: 5108 version = RTL_VER_04; 5109 break; 5110 case 0x5c20: 5111 version = RTL_VER_05; 5112 break; 5113 case 0x5c30: 5114 version = RTL_VER_06; 5115 break; 5116 case 0x4800: 5117 version = RTL_VER_07; 5118 break; 5119 case 0x6000: 5120 version = RTL_VER_08; 5121 break; 5122 case 0x6010: 5123 version = RTL_VER_09; 5124 break; 5125 default: 5126 version = RTL_VER_UNKNOWN; 5127 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); 5128 break; 5129 } 5130 5131 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); 5132 5133 return version; 5134 } 5135 5136 static int rtl8152_probe(struct usb_interface *intf, 5137 const struct usb_device_id *id) 5138 { 5139 struct usb_device *udev = interface_to_usbdev(intf); 5140 u8 version = rtl_get_version(intf); 5141 struct r8152 *tp; 5142 struct net_device *netdev; 5143 int ret; 5144 5145 if (version == RTL_VER_UNKNOWN) 5146 return -ENODEV; 5147 5148 if (udev->actconfig->desc.bConfigurationValue != 1) { 5149 usb_driver_set_configuration(udev, 1); 5150 return -ENODEV; 5151 } 5152 5153 usb_reset_device(udev); 5154 netdev = alloc_etherdev(sizeof(struct r8152)); 5155 if (!netdev) { 5156 dev_err(&intf->dev, "Out of memory\n"); 5157 return -ENOMEM; 5158 } 5159 5160 SET_NETDEV_DEV(netdev, &intf->dev); 5161 tp = netdev_priv(netdev); 5162 tp->msg_enable = 0x7FFF; 5163 5164 tp->udev = udev; 5165 tp->netdev = netdev; 5166 tp->intf = intf; 5167 tp->version = version; 5168 5169 switch (version) { 5170 case RTL_VER_01: 5171 case RTL_VER_02: 5172 case RTL_VER_07: 5173 tp->mii.supports_gmii = 0; 5174 break; 5175 default: 5176 tp->mii.supports_gmii = 1; 5177 break; 5178 } 5179 5180 ret = rtl_ops_init(tp); 5181 if (ret) 5182 goto out; 5183 5184 mutex_init(&tp->control); 5185 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 5186 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); 5187 5188 netdev->netdev_ops = &rtl8152_netdev_ops; 5189 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 5190 5191 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5192 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 5193 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 5194 NETIF_F_HW_VLAN_CTAG_TX; 5195 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5196 NETIF_F_TSO | NETIF_F_FRAGLIST | 5197 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 5198 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; 5199 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 5200 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 5201 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 5202 5203 if (tp->version == RTL_VER_01) { 5204 netdev->features &= ~NETIF_F_RXCSUM; 5205 netdev->hw_features &= ~NETIF_F_RXCSUM; 5206 } 5207 5208 netdev->ethtool_ops = &ops; 5209 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 5210 5211 /* MTU range: 68 - 1500 or 9194 */ 5212 netdev->min_mtu = ETH_MIN_MTU; 5213 switch (tp->version) { 5214 case RTL_VER_01: 5215 case RTL_VER_02: 5216 netdev->max_mtu = ETH_DATA_LEN; 5217 break; 5218 default: 5219 netdev->max_mtu = RTL8153_MAX_MTU; 5220 break; 5221 } 5222 5223 tp->mii.dev = netdev; 5224 tp->mii.mdio_read = read_mii_word; 5225 tp->mii.mdio_write = write_mii_word; 5226 tp->mii.phy_id_mask = 0x3f; 5227 tp->mii.reg_num_mask = 0x1f; 5228 tp->mii.phy_id = R8152_PHY_ID; 5229 5230 tp->autoneg = AUTONEG_ENABLE; 5231 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100; 5232 tp->duplex = DUPLEX_FULL; 5233 5234 intf->needs_remote_wakeup = 1; 5235 5236 tp->rtl_ops.init(tp); 5237 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 5238 set_ethernet_addr(tp); 5239 5240 usb_set_intfdata(intf, tp); 5241 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); 5242 5243 ret = register_netdev(netdev); 5244 if (ret != 0) { 5245 netif_err(tp, probe, netdev, "couldn't register the device\n"); 5246 goto out1; 5247 } 5248 5249 if (!rtl_can_wakeup(tp)) 5250 __rtl_set_wol(tp, 0); 5251 5252 tp->saved_wolopts = __rtl_get_wol(tp); 5253 if (tp->saved_wolopts) 5254 device_set_wakeup_enable(&udev->dev, true); 5255 else 5256 device_set_wakeup_enable(&udev->dev, false); 5257 5258 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 5259 5260 return 0; 5261 5262 out1: 5263 netif_napi_del(&tp->napi); 5264 usb_set_intfdata(intf, NULL); 5265 out: 5266 free_netdev(netdev); 5267 return ret; 5268 } 5269 5270 static void rtl8152_disconnect(struct usb_interface *intf) 5271 { 5272 struct r8152 *tp = usb_get_intfdata(intf); 5273 5274 usb_set_intfdata(intf, NULL); 5275 if (tp) { 5276 struct usb_device *udev = tp->udev; 5277 5278 if (udev->state == USB_STATE_NOTATTACHED) 5279 set_bit(RTL8152_UNPLUG, &tp->flags); 5280 5281 netif_napi_del(&tp->napi); 5282 unregister_netdev(tp->netdev); 5283 cancel_delayed_work_sync(&tp->hw_phy_work); 5284 tp->rtl_ops.unload(tp); 5285 free_netdev(tp->netdev); 5286 } 5287 } 5288 5289 #define REALTEK_USB_DEVICE(vend, prod) \ 5290 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ 5291 USB_DEVICE_ID_MATCH_INT_CLASS, \ 5292 .idVendor = (vend), \ 5293 .idProduct = (prod), \ 5294 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ 5295 }, \ 5296 { \ 5297 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ 5298 USB_DEVICE_ID_MATCH_DEVICE, \ 5299 .idVendor = (vend), \ 5300 .idProduct = (prod), \ 5301 .bInterfaceClass = USB_CLASS_COMM, \ 5302 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ 5303 .bInterfaceProtocol = USB_CDC_PROTO_NONE 5304 5305 /* table of devices that work with this driver */ 5306 static const struct usb_device_id rtl8152_table[] = { 5307 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)}, 5308 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, 5309 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, 5310 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)}, 5311 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)}, 5312 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, 5313 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, 5314 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)}, 5315 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)}, 5316 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, 5317 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)}, 5318 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)}, 5319 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, 5320 {} 5321 }; 5322 5323 MODULE_DEVICE_TABLE(usb, rtl8152_table); 5324 5325 static struct usb_driver rtl8152_driver = { 5326 .name = MODULENAME, 5327 .id_table = rtl8152_table, 5328 .probe = rtl8152_probe, 5329 .disconnect = rtl8152_disconnect, 5330 .suspend = rtl8152_suspend, 5331 .resume = rtl8152_resume, 5332 .reset_resume = rtl8152_reset_resume, 5333 .pre_reset = rtl8152_pre_reset, 5334 .post_reset = rtl8152_post_reset, 5335 .supports_autosuspend = 1, 5336 .disable_hub_initiated_lpm = 1, 5337 }; 5338 5339 module_usb_driver(rtl8152_driver); 5340 5341 MODULE_AUTHOR(DRIVER_AUTHOR); 5342 MODULE_DESCRIPTION(DRIVER_DESC); 5343 MODULE_LICENSE("GPL"); 5344 MODULE_VERSION(DRIVER_VERSION); 5345