1 /* 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2 as published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/signal.h> 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/usb.h> 18 #include <linux/crc32.h> 19 #include <linux/if_vlan.h> 20 #include <linux/uaccess.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include <net/ip6_checksum.h> 25 #include <uapi/linux/mdio.h> 26 #include <linux/mdio.h> 27 #include <linux/usb/cdc.h> 28 #include <linux/suspend.h> 29 #include <linux/acpi.h> 30 31 /* Information for net-next */ 32 #define NETNEXT_VERSION "09" 33 34 /* Information for net */ 35 #define NET_VERSION "9" 36 37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION 38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 40 #define MODULENAME "r8152" 41 42 #define R8152_PHY_ID 32 43 44 #define PLA_IDR 0xc000 45 #define PLA_RCR 0xc010 46 #define PLA_RMS 0xc016 47 #define PLA_RXFIFO_CTRL0 0xc0a0 48 #define PLA_RXFIFO_CTRL1 0xc0a4 49 #define PLA_RXFIFO_CTRL2 0xc0a8 50 #define PLA_DMY_REG0 0xc0b0 51 #define PLA_FMC 0xc0b4 52 #define PLA_CFG_WOL 0xc0b6 53 #define PLA_TEREDO_CFG 0xc0bc 54 #define PLA_TEREDO_WAKE_BASE 0xc0c4 55 #define PLA_MAR 0xcd00 56 #define PLA_BACKUP 0xd000 57 #define PAL_BDC_CR 0xd1a0 58 #define PLA_TEREDO_TIMER 0xd2cc 59 #define PLA_REALWOW_TIMER 0xd2e8 60 #define PLA_EFUSE_DATA 0xdd00 61 #define PLA_EFUSE_CMD 0xdd02 62 #define PLA_LEDSEL 0xdd90 63 #define PLA_LED_FEATURE 0xdd92 64 #define PLA_PHYAR 0xde00 65 #define PLA_BOOT_CTRL 0xe004 66 #define PLA_GPHY_INTR_IMR 0xe022 67 #define PLA_EEE_CR 0xe040 68 #define PLA_EEEP_CR 0xe080 69 #define PLA_MAC_PWR_CTRL 0xe0c0 70 #define PLA_MAC_PWR_CTRL2 0xe0ca 71 #define PLA_MAC_PWR_CTRL3 0xe0cc 72 #define PLA_MAC_PWR_CTRL4 0xe0ce 73 #define PLA_WDT6_CTRL 0xe428 74 #define PLA_TCR0 0xe610 75 #define PLA_TCR1 0xe612 76 #define PLA_MTPS 0xe615 77 #define PLA_TXFIFO_CTRL 0xe618 78 #define PLA_RSTTALLY 0xe800 79 #define PLA_CR 0xe813 80 #define PLA_CRWECR 0xe81c 81 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 82 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 83 #define PLA_CONFIG5 0xe822 84 #define PLA_PHY_PWR 0xe84c 85 #define PLA_OOB_CTRL 0xe84f 86 #define PLA_CPCR 0xe854 87 #define PLA_MISC_0 0xe858 88 #define PLA_MISC_1 0xe85a 89 #define PLA_OCP_GPHY_BASE 0xe86c 90 #define PLA_TALLYCNT 0xe890 91 #define PLA_SFF_STS_7 0xe8de 92 #define PLA_PHYSTATUS 0xe908 93 #define PLA_BP_BA 0xfc26 94 #define PLA_BP_0 0xfc28 95 #define PLA_BP_1 0xfc2a 96 #define PLA_BP_2 0xfc2c 97 #define PLA_BP_3 0xfc2e 98 #define PLA_BP_4 0xfc30 99 #define PLA_BP_5 0xfc32 100 #define PLA_BP_6 0xfc34 101 #define PLA_BP_7 0xfc36 102 #define PLA_BP_EN 0xfc38 103 104 #define USB_USB2PHY 0xb41e 105 #define USB_SSPHYLINK2 0xb428 106 #define USB_U2P3_CTRL 0xb460 107 #define USB_CSR_DUMMY1 0xb464 108 #define USB_CSR_DUMMY2 0xb466 109 #define USB_DEV_STAT 0xb808 110 #define USB_CONNECT_TIMER 0xcbf8 111 #define USB_MSC_TIMER 0xcbfc 112 #define USB_BURST_SIZE 0xcfc0 113 #define USB_LPM_CONFIG 0xcfd8 114 #define USB_USB_CTRL 0xd406 115 #define USB_PHY_CTRL 0xd408 116 #define USB_TX_AGG 0xd40a 117 #define USB_RX_BUF_TH 0xd40c 118 #define USB_USB_TIMER 0xd428 119 #define USB_RX_EARLY_TIMEOUT 0xd42c 120 #define USB_RX_EARLY_SIZE 0xd42e 121 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ 122 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ 123 #define USB_TX_DMA 0xd434 124 #define USB_UPT_RXDMA_OWN 0xd437 125 #define USB_TOLERANCE 0xd490 126 #define USB_LPM_CTRL 0xd41a 127 #define USB_BMU_RESET 0xd4b0 128 #define USB_U1U2_TIMER 0xd4da 129 #define USB_UPS_CTRL 0xd800 130 #define USB_POWER_CUT 0xd80a 131 #define USB_MISC_0 0xd81a 132 #define USB_AFE_CTRL2 0xd824 133 #define USB_UPS_CFG 0xd842 134 #define USB_UPS_FLAGS 0xd848 135 #define USB_WDT11_CTRL 0xe43c 136 #define USB_BP_BA 0xfc26 137 #define USB_BP_0 0xfc28 138 #define USB_BP_1 0xfc2a 139 #define USB_BP_2 0xfc2c 140 #define USB_BP_3 0xfc2e 141 #define USB_BP_4 0xfc30 142 #define USB_BP_5 0xfc32 143 #define USB_BP_6 0xfc34 144 #define USB_BP_7 0xfc36 145 #define USB_BP_EN 0xfc38 146 #define USB_BP_8 0xfc38 147 #define USB_BP_9 0xfc3a 148 #define USB_BP_10 0xfc3c 149 #define USB_BP_11 0xfc3e 150 #define USB_BP_12 0xfc40 151 #define USB_BP_13 0xfc42 152 #define USB_BP_14 0xfc44 153 #define USB_BP_15 0xfc46 154 #define USB_BP2_EN 0xfc48 155 156 /* OCP Registers */ 157 #define OCP_ALDPS_CONFIG 0x2010 158 #define OCP_EEE_CONFIG1 0x2080 159 #define OCP_EEE_CONFIG2 0x2092 160 #define OCP_EEE_CONFIG3 0x2094 161 #define OCP_BASE_MII 0xa400 162 #define OCP_EEE_AR 0xa41a 163 #define OCP_EEE_DATA 0xa41c 164 #define OCP_PHY_STATUS 0xa420 165 #define OCP_NCTL_CFG 0xa42c 166 #define OCP_POWER_CFG 0xa430 167 #define OCP_EEE_CFG 0xa432 168 #define OCP_SRAM_ADDR 0xa436 169 #define OCP_SRAM_DATA 0xa438 170 #define OCP_DOWN_SPEED 0xa442 171 #define OCP_EEE_ABLE 0xa5c4 172 #define OCP_EEE_ADV 0xa5d0 173 #define OCP_EEE_LPABLE 0xa5d2 174 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ 175 #define OCP_PHY_PATCH_STAT 0xb800 176 #define OCP_PHY_PATCH_CMD 0xb820 177 #define OCP_ADC_IOFFSET 0xbcfc 178 #define OCP_ADC_CFG 0xbc06 179 #define OCP_SYSCLK_CFG 0xc416 180 181 /* SRAM Register */ 182 #define SRAM_GREEN_CFG 0x8011 183 #define SRAM_LPF_CFG 0x8012 184 #define SRAM_10M_AMP1 0x8080 185 #define SRAM_10M_AMP2 0x8082 186 #define SRAM_IMPEDANCE 0x8084 187 188 /* PLA_RCR */ 189 #define RCR_AAP 0x00000001 190 #define RCR_APM 0x00000002 191 #define RCR_AM 0x00000004 192 #define RCR_AB 0x00000008 193 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 194 195 /* PLA_RXFIFO_CTRL0 */ 196 #define RXFIFO_THR1_NORMAL 0x00080002 197 #define RXFIFO_THR1_OOB 0x01800003 198 199 /* PLA_RXFIFO_CTRL1 */ 200 #define RXFIFO_THR2_FULL 0x00000060 201 #define RXFIFO_THR2_HIGH 0x00000038 202 #define RXFIFO_THR2_OOB 0x0000004a 203 #define RXFIFO_THR2_NORMAL 0x00a0 204 205 /* PLA_RXFIFO_CTRL2 */ 206 #define RXFIFO_THR3_FULL 0x00000078 207 #define RXFIFO_THR3_HIGH 0x00000048 208 #define RXFIFO_THR3_OOB 0x0000005a 209 #define RXFIFO_THR3_NORMAL 0x0110 210 211 /* PLA_TXFIFO_CTRL */ 212 #define TXFIFO_THR_NORMAL 0x00400008 213 #define TXFIFO_THR_NORMAL2 0x01000008 214 215 /* PLA_DMY_REG0 */ 216 #define ECM_ALDPS 0x0002 217 218 /* PLA_FMC */ 219 #define FMC_FCR_MCU_EN 0x0001 220 221 /* PLA_EEEP_CR */ 222 #define EEEP_CR_EEEP_TX 0x0002 223 224 /* PLA_WDT6_CTRL */ 225 #define WDT6_SET_MODE 0x0010 226 227 /* PLA_TCR0 */ 228 #define TCR0_TX_EMPTY 0x0800 229 #define TCR0_AUTO_FIFO 0x0080 230 231 /* PLA_TCR1 */ 232 #define VERSION_MASK 0x7cf0 233 234 /* PLA_MTPS */ 235 #define MTPS_JUMBO (12 * 1024 / 64) 236 #define MTPS_DEFAULT (6 * 1024 / 64) 237 238 /* PLA_RSTTALLY */ 239 #define TALLY_RESET 0x0001 240 241 /* PLA_CR */ 242 #define CR_RST 0x10 243 #define CR_RE 0x08 244 #define CR_TE 0x04 245 246 /* PLA_CRWECR */ 247 #define CRWECR_NORAML 0x00 248 #define CRWECR_CONFIG 0xc0 249 250 /* PLA_OOB_CTRL */ 251 #define NOW_IS_OOB 0x80 252 #define TXFIFO_EMPTY 0x20 253 #define RXFIFO_EMPTY 0x10 254 #define LINK_LIST_READY 0x02 255 #define DIS_MCU_CLROOB 0x01 256 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 257 258 /* PLA_MISC_1 */ 259 #define RXDY_GATED_EN 0x0008 260 261 /* PLA_SFF_STS_7 */ 262 #define RE_INIT_LL 0x8000 263 #define MCU_BORW_EN 0x4000 264 265 /* PLA_CPCR */ 266 #define CPCR_RX_VLAN 0x0040 267 268 /* PLA_CFG_WOL */ 269 #define MAGIC_EN 0x0001 270 271 /* PLA_TEREDO_CFG */ 272 #define TEREDO_SEL 0x8000 273 #define TEREDO_WAKE_MASK 0x7f00 274 #define TEREDO_RS_EVENT_MASK 0x00fe 275 #define OOB_TEREDO_EN 0x0001 276 277 /* PAL_BDC_CR */ 278 #define ALDPS_PROXY_MODE 0x0001 279 280 /* PLA_EFUSE_CMD */ 281 #define EFUSE_READ_CMD BIT(15) 282 #define EFUSE_DATA_BIT16 BIT(7) 283 284 /* PLA_CONFIG34 */ 285 #define LINK_ON_WAKE_EN 0x0010 286 #define LINK_OFF_WAKE_EN 0x0008 287 288 /* PLA_CONFIG5 */ 289 #define BWF_EN 0x0040 290 #define MWF_EN 0x0020 291 #define UWF_EN 0x0010 292 #define LAN_WAKE_EN 0x0002 293 294 /* PLA_LED_FEATURE */ 295 #define LED_MODE_MASK 0x0700 296 297 /* PLA_PHY_PWR */ 298 #define TX_10M_IDLE_EN 0x0080 299 #define PFM_PWM_SWITCH 0x0040 300 301 /* PLA_MAC_PWR_CTRL */ 302 #define D3_CLK_GATED_EN 0x00004000 303 #define MCU_CLK_RATIO 0x07010f07 304 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 305 #define ALDPS_SPDWN_RATIO 0x0f87 306 307 /* PLA_MAC_PWR_CTRL2 */ 308 #define EEE_SPDWN_RATIO 0x8007 309 #define MAC_CLK_SPDWN_EN BIT(15) 310 311 /* PLA_MAC_PWR_CTRL3 */ 312 #define PKT_AVAIL_SPDWN_EN 0x0100 313 #define SUSPEND_SPDWN_EN 0x0004 314 #define U1U2_SPDWN_EN 0x0002 315 #define L1_SPDWN_EN 0x0001 316 317 /* PLA_MAC_PWR_CTRL4 */ 318 #define PWRSAVE_SPDWN_EN 0x1000 319 #define RXDV_SPDWN_EN 0x0800 320 #define TX10MIDLE_EN 0x0100 321 #define TP100_SPDWN_EN 0x0020 322 #define TP500_SPDWN_EN 0x0010 323 #define TP1000_SPDWN_EN 0x0008 324 #define EEE_SPDWN_EN 0x0001 325 326 /* PLA_GPHY_INTR_IMR */ 327 #define GPHY_STS_MSK 0x0001 328 #define SPEED_DOWN_MSK 0x0002 329 #define SPDWN_RXDV_MSK 0x0004 330 #define SPDWN_LINKCHG_MSK 0x0008 331 332 /* PLA_PHYAR */ 333 #define PHYAR_FLAG 0x80000000 334 335 /* PLA_EEE_CR */ 336 #define EEE_RX_EN 0x0001 337 #define EEE_TX_EN 0x0002 338 339 /* PLA_BOOT_CTRL */ 340 #define AUTOLOAD_DONE 0x0002 341 342 /* USB_USB2PHY */ 343 #define USB2PHY_SUSPEND 0x0001 344 #define USB2PHY_L1 0x0002 345 346 /* USB_SSPHYLINK2 */ 347 #define pwd_dn_scale_mask 0x3ffe 348 #define pwd_dn_scale(x) ((x) << 1) 349 350 /* USB_CSR_DUMMY1 */ 351 #define DYNAMIC_BURST 0x0001 352 353 /* USB_CSR_DUMMY2 */ 354 #define EP4_FULL_FC 0x0001 355 356 /* USB_DEV_STAT */ 357 #define STAT_SPEED_MASK 0x0006 358 #define STAT_SPEED_HIGH 0x0000 359 #define STAT_SPEED_FULL 0x0002 360 361 /* USB_LPM_CONFIG */ 362 #define LPM_U1U2_EN BIT(0) 363 364 /* USB_TX_AGG */ 365 #define TX_AGG_MAX_THRESHOLD 0x03 366 367 /* USB_RX_BUF_TH */ 368 #define RX_THR_SUPPER 0x0c350180 369 #define RX_THR_HIGH 0x7a120180 370 #define RX_THR_SLOW 0xffff0180 371 #define RX_THR_B 0x00010001 372 373 /* USB_TX_DMA */ 374 #define TEST_MODE_DISABLE 0x00000001 375 #define TX_SIZE_ADJUST1 0x00000100 376 377 /* USB_BMU_RESET */ 378 #define BMU_RESET_EP_IN 0x01 379 #define BMU_RESET_EP_OUT 0x02 380 381 /* USB_UPT_RXDMA_OWN */ 382 #define OWN_UPDATE BIT(0) 383 #define OWN_CLEAR BIT(1) 384 385 /* USB_UPS_CTRL */ 386 #define POWER_CUT 0x0100 387 388 /* USB_PM_CTRL_STATUS */ 389 #define RESUME_INDICATE 0x0001 390 391 /* USB_USB_CTRL */ 392 #define RX_AGG_DISABLE 0x0010 393 #define RX_ZERO_EN 0x0080 394 395 /* USB_U2P3_CTRL */ 396 #define U2P3_ENABLE 0x0001 397 398 /* USB_POWER_CUT */ 399 #define PWR_EN 0x0001 400 #define PHASE2_EN 0x0008 401 #define UPS_EN BIT(4) 402 #define USP_PREWAKE BIT(5) 403 404 /* USB_MISC_0 */ 405 #define PCUT_STATUS 0x0001 406 407 /* USB_RX_EARLY_TIMEOUT */ 408 #define COALESCE_SUPER 85000U 409 #define COALESCE_HIGH 250000U 410 #define COALESCE_SLOW 524280U 411 412 /* USB_WDT11_CTRL */ 413 #define TIMER11_EN 0x0001 414 415 /* USB_LPM_CTRL */ 416 /* bit 4 ~ 5: fifo empty boundary */ 417 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 418 /* bit 2 ~ 3: LMP timer */ 419 #define LPM_TIMER_MASK 0x0c 420 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 421 #define LPM_TIMER_500US 0x0c /* 500 us */ 422 #define ROK_EXIT_LPM 0x02 423 424 /* USB_AFE_CTRL2 */ 425 #define SEN_VAL_MASK 0xf800 426 #define SEN_VAL_NORMAL 0xa000 427 #define SEL_RXIDLE 0x0100 428 429 /* USB_UPS_CFG */ 430 #define SAW_CNT_1MS_MASK 0x0fff 431 432 /* USB_UPS_FLAGS */ 433 #define UPS_FLAGS_R_TUNE BIT(0) 434 #define UPS_FLAGS_EN_10M_CKDIV BIT(1) 435 #define UPS_FLAGS_250M_CKDIV BIT(2) 436 #define UPS_FLAGS_EN_ALDPS BIT(3) 437 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) 438 #define UPS_FLAGS_SPEED_MASK (0xf << 16) 439 #define ups_flags_speed(x) ((x) << 16) 440 #define UPS_FLAGS_EN_EEE BIT(20) 441 #define UPS_FLAGS_EN_500M_EEE BIT(21) 442 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22) 443 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) 444 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) 445 #define UPS_FLAGS_EN_GREEN BIT(26) 446 #define UPS_FLAGS_EN_FLOW_CTR BIT(27) 447 448 enum spd_duplex { 449 NWAY_10M_HALF = 1, 450 NWAY_10M_FULL, 451 NWAY_100M_HALF, 452 NWAY_100M_FULL, 453 NWAY_1000M_FULL, 454 FORCE_10M_HALF, 455 FORCE_10M_FULL, 456 FORCE_100M_HALF, 457 FORCE_100M_FULL, 458 }; 459 460 /* OCP_ALDPS_CONFIG */ 461 #define ENPWRSAVE 0x8000 462 #define ENPDNPS 0x0200 463 #define LINKENA 0x0100 464 #define DIS_SDSAVE 0x0010 465 466 /* OCP_PHY_STATUS */ 467 #define PHY_STAT_MASK 0x0007 468 #define PHY_STAT_EXT_INIT 2 469 #define PHY_STAT_LAN_ON 3 470 #define PHY_STAT_PWRDN 5 471 472 /* OCP_NCTL_CFG */ 473 #define PGA_RETURN_EN BIT(1) 474 475 /* OCP_POWER_CFG */ 476 #define EEE_CLKDIV_EN 0x8000 477 #define EN_ALDPS 0x0004 478 #define EN_10M_PLLOFF 0x0001 479 480 /* OCP_EEE_CONFIG1 */ 481 #define RG_TXLPI_MSK_HFDUP 0x8000 482 #define RG_MATCLR_EN 0x4000 483 #define EEE_10_CAP 0x2000 484 #define EEE_NWAY_EN 0x1000 485 #define TX_QUIET_EN 0x0200 486 #define RX_QUIET_EN 0x0100 487 #define sd_rise_time_mask 0x0070 488 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 489 #define RG_RXLPI_MSK_HFDUP 0x0008 490 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 491 492 /* OCP_EEE_CONFIG2 */ 493 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 494 #define RG_DACQUIET_EN 0x0400 495 #define RG_LDVQUIET_EN 0x0200 496 #define RG_CKRSEL 0x0020 497 #define RG_EEEPRG_EN 0x0010 498 499 /* OCP_EEE_CONFIG3 */ 500 #define fast_snr_mask 0xff80 501 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 502 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 503 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 504 505 /* OCP_EEE_AR */ 506 /* bit[15:14] function */ 507 #define FUN_ADDR 0x0000 508 #define FUN_DATA 0x4000 509 /* bit[4:0] device addr */ 510 511 /* OCP_EEE_CFG */ 512 #define CTAP_SHORT_EN 0x0040 513 #define EEE10_EN 0x0010 514 515 /* OCP_DOWN_SPEED */ 516 #define EN_EEE_CMODE BIT(14) 517 #define EN_EEE_1000 BIT(13) 518 #define EN_EEE_100 BIT(12) 519 #define EN_10M_CLKDIV BIT(11) 520 #define EN_10M_BGOFF 0x0080 521 522 /* OCP_PHY_STATE */ 523 #define TXDIS_STATE 0x01 524 #define ABD_STATE 0x02 525 526 /* OCP_PHY_PATCH_STAT */ 527 #define PATCH_READY BIT(6) 528 529 /* OCP_PHY_PATCH_CMD */ 530 #define PATCH_REQUEST BIT(4) 531 532 /* OCP_ADC_CFG */ 533 #define CKADSEL_L 0x0100 534 #define ADC_EN 0x0080 535 #define EN_EMI_L 0x0040 536 537 /* OCP_SYSCLK_CFG */ 538 #define clk_div_expo(x) (min(x, 5) << 8) 539 540 /* SRAM_GREEN_CFG */ 541 #define GREEN_ETH_EN BIT(15) 542 #define R_TUNE_EN BIT(11) 543 544 /* SRAM_LPF_CFG */ 545 #define LPF_AUTO_TUNE 0x8000 546 547 /* SRAM_10M_AMP1 */ 548 #define GDAC_IB_UPALL 0x0008 549 550 /* SRAM_10M_AMP2 */ 551 #define AMP_DN 0x0200 552 553 /* SRAM_IMPEDANCE */ 554 #define RX_DRIVING_MASK 0x6000 555 556 /* MAC PASSTHRU */ 557 #define AD_MASK 0xfee0 558 #define EFUSE 0xcfdb 559 #define PASS_THRU_MASK 0x1 560 561 enum rtl_register_content { 562 _1000bps = 0x10, 563 _100bps = 0x08, 564 _10bps = 0x04, 565 LINK_STATUS = 0x02, 566 FULL_DUP = 0x01, 567 }; 568 569 #define RTL8152_MAX_TX 4 570 #define RTL8152_MAX_RX 10 571 #define INTBUFSIZE 2 572 #define TX_ALIGN 4 573 #define RX_ALIGN 8 574 575 #define INTR_LINK 0x0004 576 577 #define RTL8152_REQT_READ 0xc0 578 #define RTL8152_REQT_WRITE 0x40 579 #define RTL8152_REQ_GET_REGS 0x05 580 #define RTL8152_REQ_SET_REGS 0x05 581 582 #define BYTE_EN_DWORD 0xff 583 #define BYTE_EN_WORD 0x33 584 #define BYTE_EN_BYTE 0x11 585 #define BYTE_EN_SIX_BYTES 0x3f 586 #define BYTE_EN_START_MASK 0x0f 587 #define BYTE_EN_END_MASK 0xf0 588 589 #define RTL8153_MAX_PACKET 9216 /* 9K */ 590 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \ 591 ETH_FCS_LEN) 592 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 593 #define RTL8153_RMS RTL8153_MAX_PACKET 594 #define RTL8152_TX_TIMEOUT (5 * HZ) 595 #define RTL8152_NAPI_WEIGHT 64 596 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \ 597 sizeof(struct rx_desc) + RX_ALIGN) 598 599 /* rtl8152 flags */ 600 enum rtl8152_flags { 601 RTL8152_UNPLUG = 0, 602 RTL8152_SET_RX_MODE, 603 WORK_ENABLE, 604 RTL8152_LINK_CHG, 605 SELECTIVE_SUSPEND, 606 PHY_RESET, 607 SCHEDULE_NAPI, 608 GREEN_ETHERNET, 609 }; 610 611 /* Define these values to match your device */ 612 #define VENDOR_ID_REALTEK 0x0bda 613 #define VENDOR_ID_MICROSOFT 0x045e 614 #define VENDOR_ID_SAMSUNG 0x04e8 615 #define VENDOR_ID_LENOVO 0x17ef 616 #define VENDOR_ID_LINKSYS 0x13b1 617 #define VENDOR_ID_NVIDIA 0x0955 618 619 #define MCU_TYPE_PLA 0x0100 620 #define MCU_TYPE_USB 0x0000 621 622 struct tally_counter { 623 __le64 tx_packets; 624 __le64 rx_packets; 625 __le64 tx_errors; 626 __le32 rx_errors; 627 __le16 rx_missed; 628 __le16 align_errors; 629 __le32 tx_one_collision; 630 __le32 tx_multi_collision; 631 __le64 rx_unicast; 632 __le64 rx_broadcast; 633 __le32 rx_multicast; 634 __le16 tx_aborted; 635 __le16 tx_underrun; 636 }; 637 638 struct rx_desc { 639 __le32 opts1; 640 #define RX_LEN_MASK 0x7fff 641 642 __le32 opts2; 643 #define RD_UDP_CS BIT(23) 644 #define RD_TCP_CS BIT(22) 645 #define RD_IPV6_CS BIT(20) 646 #define RD_IPV4_CS BIT(19) 647 648 __le32 opts3; 649 #define IPF BIT(23) /* IP checksum fail */ 650 #define UDPF BIT(22) /* UDP checksum fail */ 651 #define TCPF BIT(21) /* TCP checksum fail */ 652 #define RX_VLAN_TAG BIT(16) 653 654 __le32 opts4; 655 __le32 opts5; 656 __le32 opts6; 657 }; 658 659 struct tx_desc { 660 __le32 opts1; 661 #define TX_FS BIT(31) /* First segment of a packet */ 662 #define TX_LS BIT(30) /* Final segment of a packet */ 663 #define GTSENDV4 BIT(28) 664 #define GTSENDV6 BIT(27) 665 #define GTTCPHO_SHIFT 18 666 #define GTTCPHO_MAX 0x7fU 667 #define TX_LEN_MAX 0x3ffffU 668 669 __le32 opts2; 670 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 671 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 672 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 673 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 674 #define MSS_SHIFT 17 675 #define MSS_MAX 0x7ffU 676 #define TCPHO_SHIFT 17 677 #define TCPHO_MAX 0x7ffU 678 #define TX_VLAN_TAG BIT(16) 679 }; 680 681 struct r8152; 682 683 struct rx_agg { 684 struct list_head list; 685 struct urb *urb; 686 struct r8152 *context; 687 void *buffer; 688 void *head; 689 }; 690 691 struct tx_agg { 692 struct list_head list; 693 struct urb *urb; 694 struct r8152 *context; 695 void *buffer; 696 void *head; 697 u32 skb_num; 698 u32 skb_len; 699 }; 700 701 struct r8152 { 702 unsigned long flags; 703 struct usb_device *udev; 704 struct napi_struct napi; 705 struct usb_interface *intf; 706 struct net_device *netdev; 707 struct urb *intr_urb; 708 struct tx_agg tx_info[RTL8152_MAX_TX]; 709 struct rx_agg rx_info[RTL8152_MAX_RX]; 710 struct list_head rx_done, tx_free; 711 struct sk_buff_head tx_queue, rx_queue; 712 spinlock_t rx_lock, tx_lock; 713 struct delayed_work schedule, hw_phy_work; 714 struct mii_if_info mii; 715 struct mutex control; /* use for hw setting */ 716 #ifdef CONFIG_PM_SLEEP 717 struct notifier_block pm_notifier; 718 #endif 719 720 struct rtl_ops { 721 void (*init)(struct r8152 *); 722 int (*enable)(struct r8152 *); 723 void (*disable)(struct r8152 *); 724 void (*up)(struct r8152 *); 725 void (*down)(struct r8152 *); 726 void (*unload)(struct r8152 *); 727 int (*eee_get)(struct r8152 *, struct ethtool_eee *); 728 int (*eee_set)(struct r8152 *, struct ethtool_eee *); 729 bool (*in_nway)(struct r8152 *); 730 void (*hw_phy_cfg)(struct r8152 *); 731 void (*autosuspend_en)(struct r8152 *tp, bool enable); 732 } rtl_ops; 733 734 int intr_interval; 735 u32 saved_wolopts; 736 u32 msg_enable; 737 u32 tx_qlen; 738 u32 coalesce; 739 u16 ocp_base; 740 u16 speed; 741 u8 *intr_buff; 742 u8 version; 743 u8 duplex; 744 u8 autoneg; 745 }; 746 747 enum rtl_version { 748 RTL_VER_UNKNOWN = 0, 749 RTL_VER_01, 750 RTL_VER_02, 751 RTL_VER_03, 752 RTL_VER_04, 753 RTL_VER_05, 754 RTL_VER_06, 755 RTL_VER_07, 756 RTL_VER_08, 757 RTL_VER_09, 758 RTL_VER_MAX 759 }; 760 761 enum tx_csum_stat { 762 TX_CSUM_SUCCESS = 0, 763 TX_CSUM_TSO, 764 TX_CSUM_NONE 765 }; 766 767 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 768 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 769 */ 770 static const int multicast_filter_limit = 32; 771 static unsigned int agg_buf_sz = 16384; 772 773 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ 774 VLAN_ETH_HLEN - ETH_FCS_LEN) 775 776 static 777 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 778 { 779 int ret; 780 void *tmp; 781 782 tmp = kmalloc(size, GFP_KERNEL); 783 if (!tmp) 784 return -ENOMEM; 785 786 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 787 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 788 value, index, tmp, size, 500); 789 790 memcpy(data, tmp, size); 791 kfree(tmp); 792 793 return ret; 794 } 795 796 static 797 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 798 { 799 int ret; 800 void *tmp; 801 802 tmp = kmemdup(data, size, GFP_KERNEL); 803 if (!tmp) 804 return -ENOMEM; 805 806 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 807 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 808 value, index, tmp, size, 500); 809 810 kfree(tmp); 811 812 return ret; 813 } 814 815 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 816 void *data, u16 type) 817 { 818 u16 limit = 64; 819 int ret = 0; 820 821 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 822 return -ENODEV; 823 824 /* both size and indix must be 4 bytes align */ 825 if ((size & 3) || !size || (index & 3) || !data) 826 return -EPERM; 827 828 if ((u32)index + (u32)size > 0xffff) 829 return -EPERM; 830 831 while (size) { 832 if (size > limit) { 833 ret = get_registers(tp, index, type, limit, data); 834 if (ret < 0) 835 break; 836 837 index += limit; 838 data += limit; 839 size -= limit; 840 } else { 841 ret = get_registers(tp, index, type, size, data); 842 if (ret < 0) 843 break; 844 845 index += size; 846 data += size; 847 size = 0; 848 break; 849 } 850 } 851 852 if (ret == -ENODEV) 853 set_bit(RTL8152_UNPLUG, &tp->flags); 854 855 return ret; 856 } 857 858 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 859 u16 size, void *data, u16 type) 860 { 861 int ret; 862 u16 byteen_start, byteen_end, byen; 863 u16 limit = 512; 864 865 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 866 return -ENODEV; 867 868 /* both size and indix must be 4 bytes align */ 869 if ((size & 3) || !size || (index & 3) || !data) 870 return -EPERM; 871 872 if ((u32)index + (u32)size > 0xffff) 873 return -EPERM; 874 875 byteen_start = byteen & BYTE_EN_START_MASK; 876 byteen_end = byteen & BYTE_EN_END_MASK; 877 878 byen = byteen_start | (byteen_start << 4); 879 ret = set_registers(tp, index, type | byen, 4, data); 880 if (ret < 0) 881 goto error1; 882 883 index += 4; 884 data += 4; 885 size -= 4; 886 887 if (size) { 888 size -= 4; 889 890 while (size) { 891 if (size > limit) { 892 ret = set_registers(tp, index, 893 type | BYTE_EN_DWORD, 894 limit, data); 895 if (ret < 0) 896 goto error1; 897 898 index += limit; 899 data += limit; 900 size -= limit; 901 } else { 902 ret = set_registers(tp, index, 903 type | BYTE_EN_DWORD, 904 size, data); 905 if (ret < 0) 906 goto error1; 907 908 index += size; 909 data += size; 910 size = 0; 911 break; 912 } 913 } 914 915 byen = byteen_end | (byteen_end >> 4); 916 ret = set_registers(tp, index, type | byen, 4, data); 917 if (ret < 0) 918 goto error1; 919 } 920 921 error1: 922 if (ret == -ENODEV) 923 set_bit(RTL8152_UNPLUG, &tp->flags); 924 925 return ret; 926 } 927 928 static inline 929 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 930 { 931 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 932 } 933 934 static inline 935 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 936 { 937 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 938 } 939 940 static inline 941 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 942 { 943 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 944 } 945 946 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 947 { 948 __le32 data; 949 950 generic_ocp_read(tp, index, sizeof(data), &data, type); 951 952 return __le32_to_cpu(data); 953 } 954 955 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 956 { 957 __le32 tmp = __cpu_to_le32(data); 958 959 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 960 } 961 962 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 963 { 964 u32 data; 965 __le32 tmp; 966 u16 byen = BYTE_EN_WORD; 967 u8 shift = index & 2; 968 969 index &= ~3; 970 byen <<= shift; 971 972 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen); 973 974 data = __le32_to_cpu(tmp); 975 data >>= (shift * 8); 976 data &= 0xffff; 977 978 return (u16)data; 979 } 980 981 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 982 { 983 u32 mask = 0xffff; 984 __le32 tmp; 985 u16 byen = BYTE_EN_WORD; 986 u8 shift = index & 2; 987 988 data &= mask; 989 990 if (index & 2) { 991 byen <<= shift; 992 mask <<= (shift * 8); 993 data <<= (shift * 8); 994 index &= ~3; 995 } 996 997 tmp = __cpu_to_le32(data); 998 999 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1000 } 1001 1002 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 1003 { 1004 u32 data; 1005 __le32 tmp; 1006 u8 shift = index & 3; 1007 1008 index &= ~3; 1009 1010 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 1011 1012 data = __le32_to_cpu(tmp); 1013 data >>= (shift * 8); 1014 data &= 0xff; 1015 1016 return (u8)data; 1017 } 1018 1019 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 1020 { 1021 u32 mask = 0xff; 1022 __le32 tmp; 1023 u16 byen = BYTE_EN_BYTE; 1024 u8 shift = index & 3; 1025 1026 data &= mask; 1027 1028 if (index & 3) { 1029 byen <<= shift; 1030 mask <<= (shift * 8); 1031 data <<= (shift * 8); 1032 index &= ~3; 1033 } 1034 1035 tmp = __cpu_to_le32(data); 1036 1037 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1038 } 1039 1040 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 1041 { 1042 u16 ocp_base, ocp_index; 1043 1044 ocp_base = addr & 0xf000; 1045 if (ocp_base != tp->ocp_base) { 1046 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1047 tp->ocp_base = ocp_base; 1048 } 1049 1050 ocp_index = (addr & 0x0fff) | 0xb000; 1051 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 1052 } 1053 1054 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 1055 { 1056 u16 ocp_base, ocp_index; 1057 1058 ocp_base = addr & 0xf000; 1059 if (ocp_base != tp->ocp_base) { 1060 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1061 tp->ocp_base = ocp_base; 1062 } 1063 1064 ocp_index = (addr & 0x0fff) | 0xb000; 1065 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 1066 } 1067 1068 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 1069 { 1070 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 1071 } 1072 1073 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 1074 { 1075 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 1076 } 1077 1078 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 1079 { 1080 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1081 ocp_reg_write(tp, OCP_SRAM_DATA, data); 1082 } 1083 1084 static u16 sram_read(struct r8152 *tp, u16 addr) 1085 { 1086 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1087 return ocp_reg_read(tp, OCP_SRAM_DATA); 1088 } 1089 1090 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 1091 { 1092 struct r8152 *tp = netdev_priv(netdev); 1093 int ret; 1094 1095 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1096 return -ENODEV; 1097 1098 if (phy_id != R8152_PHY_ID) 1099 return -EINVAL; 1100 1101 ret = r8152_mdio_read(tp, reg); 1102 1103 return ret; 1104 } 1105 1106 static 1107 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 1108 { 1109 struct r8152 *tp = netdev_priv(netdev); 1110 1111 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1112 return; 1113 1114 if (phy_id != R8152_PHY_ID) 1115 return; 1116 1117 r8152_mdio_write(tp, reg, val); 1118 } 1119 1120 static int 1121 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 1122 1123 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1124 { 1125 struct r8152 *tp = netdev_priv(netdev); 1126 struct sockaddr *addr = p; 1127 int ret = -EADDRNOTAVAIL; 1128 1129 if (!is_valid_ether_addr(addr->sa_data)) 1130 goto out1; 1131 1132 ret = usb_autopm_get_interface(tp->intf); 1133 if (ret < 0) 1134 goto out1; 1135 1136 mutex_lock(&tp->control); 1137 1138 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1139 1140 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1141 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1142 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1143 1144 mutex_unlock(&tp->control); 1145 1146 usb_autopm_put_interface(tp->intf); 1147 out1: 1148 return ret; 1149 } 1150 1151 /* Devices containing RTL8153-AD can support a persistent 1152 * host system provided MAC address. 1153 * Examples of this are Dell TB15 and Dell WD15 docks 1154 */ 1155 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) 1156 { 1157 acpi_status status; 1158 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1159 union acpi_object *obj; 1160 int ret = -EINVAL; 1161 u32 ocp_data; 1162 unsigned char buf[6]; 1163 1164 /* test for -AD variant of RTL8153 */ 1165 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 1166 if ((ocp_data & AD_MASK) != 0x1000) 1167 return -ENODEV; 1168 1169 /* test for MAC address pass-through bit */ 1170 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); 1171 if ((ocp_data & PASS_THRU_MASK) != 1) 1172 return -ENODEV; 1173 1174 /* returns _AUXMAC_#AABBCCDDEEFF# */ 1175 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer); 1176 obj = (union acpi_object *)buffer.pointer; 1177 if (!ACPI_SUCCESS(status)) 1178 return -ENODEV; 1179 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) { 1180 netif_warn(tp, probe, tp->netdev, 1181 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", 1182 obj->type, obj->string.length); 1183 goto amacout; 1184 } 1185 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || 1186 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { 1187 netif_warn(tp, probe, tp->netdev, 1188 "Invalid header when reading pass-thru MAC addr\n"); 1189 goto amacout; 1190 } 1191 ret = hex2bin(buf, obj->string.pointer + 9, 6); 1192 if (!(ret == 0 && is_valid_ether_addr(buf))) { 1193 netif_warn(tp, probe, tp->netdev, 1194 "Invalid MAC for pass-thru MAC addr: %d, %pM\n", 1195 ret, buf); 1196 ret = -EINVAL; 1197 goto amacout; 1198 } 1199 memcpy(sa->sa_data, buf, 6); 1200 ether_addr_copy(tp->netdev->dev_addr, sa->sa_data); 1201 netif_info(tp, probe, tp->netdev, 1202 "Using pass-thru MAC addr %pM\n", sa->sa_data); 1203 1204 amacout: 1205 kfree(obj); 1206 return ret; 1207 } 1208 1209 static int set_ethernet_addr(struct r8152 *tp) 1210 { 1211 struct net_device *dev = tp->netdev; 1212 struct sockaddr sa; 1213 int ret; 1214 1215 if (tp->version == RTL_VER_01) { 1216 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); 1217 } else { 1218 /* if this is not an RTL8153-AD, no eFuse mac pass thru set, 1219 * or system doesn't provide valid _SB.AMAC this will be 1220 * be expected to non-zero 1221 */ 1222 ret = vendor_mac_passthru_addr_read(tp, &sa); 1223 if (ret < 0) 1224 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); 1225 } 1226 1227 if (ret < 0) { 1228 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1229 } else if (!is_valid_ether_addr(sa.sa_data)) { 1230 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1231 sa.sa_data); 1232 eth_hw_addr_random(dev); 1233 ether_addr_copy(sa.sa_data, dev->dev_addr); 1234 ret = rtl8152_set_mac_address(dev, &sa); 1235 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1236 sa.sa_data); 1237 } else { 1238 if (tp->version == RTL_VER_01) 1239 ether_addr_copy(dev->dev_addr, sa.sa_data); 1240 else 1241 ret = rtl8152_set_mac_address(dev, &sa); 1242 } 1243 1244 return ret; 1245 } 1246 1247 static void read_bulk_callback(struct urb *urb) 1248 { 1249 struct net_device *netdev; 1250 int status = urb->status; 1251 struct rx_agg *agg; 1252 struct r8152 *tp; 1253 1254 agg = urb->context; 1255 if (!agg) 1256 return; 1257 1258 tp = agg->context; 1259 if (!tp) 1260 return; 1261 1262 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1263 return; 1264 1265 if (!test_bit(WORK_ENABLE, &tp->flags)) 1266 return; 1267 1268 netdev = tp->netdev; 1269 1270 /* When link down, the driver would cancel all bulks. */ 1271 /* This avoid the re-submitting bulk */ 1272 if (!netif_carrier_ok(netdev)) 1273 return; 1274 1275 usb_mark_last_busy(tp->udev); 1276 1277 switch (status) { 1278 case 0: 1279 if (urb->actual_length < ETH_ZLEN) 1280 break; 1281 1282 spin_lock(&tp->rx_lock); 1283 list_add_tail(&agg->list, &tp->rx_done); 1284 spin_unlock(&tp->rx_lock); 1285 napi_schedule(&tp->napi); 1286 return; 1287 case -ESHUTDOWN: 1288 set_bit(RTL8152_UNPLUG, &tp->flags); 1289 netif_device_detach(tp->netdev); 1290 return; 1291 case -ENOENT: 1292 return; /* the urb is in unlink state */ 1293 case -ETIME: 1294 if (net_ratelimit()) 1295 netdev_warn(netdev, "maybe reset is needed?\n"); 1296 break; 1297 default: 1298 if (net_ratelimit()) 1299 netdev_warn(netdev, "Rx status %d\n", status); 1300 break; 1301 } 1302 1303 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1304 } 1305 1306 static void write_bulk_callback(struct urb *urb) 1307 { 1308 struct net_device_stats *stats; 1309 struct net_device *netdev; 1310 struct tx_agg *agg; 1311 struct r8152 *tp; 1312 int status = urb->status; 1313 1314 agg = urb->context; 1315 if (!agg) 1316 return; 1317 1318 tp = agg->context; 1319 if (!tp) 1320 return; 1321 1322 netdev = tp->netdev; 1323 stats = &netdev->stats; 1324 if (status) { 1325 if (net_ratelimit()) 1326 netdev_warn(netdev, "Tx status %d\n", status); 1327 stats->tx_errors += agg->skb_num; 1328 } else { 1329 stats->tx_packets += agg->skb_num; 1330 stats->tx_bytes += agg->skb_len; 1331 } 1332 1333 spin_lock(&tp->tx_lock); 1334 list_add_tail(&agg->list, &tp->tx_free); 1335 spin_unlock(&tp->tx_lock); 1336 1337 usb_autopm_put_interface_async(tp->intf); 1338 1339 if (!netif_carrier_ok(netdev)) 1340 return; 1341 1342 if (!test_bit(WORK_ENABLE, &tp->flags)) 1343 return; 1344 1345 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1346 return; 1347 1348 if (!skb_queue_empty(&tp->tx_queue)) 1349 napi_schedule(&tp->napi); 1350 } 1351 1352 static void intr_callback(struct urb *urb) 1353 { 1354 struct r8152 *tp; 1355 __le16 *d; 1356 int status = urb->status; 1357 int res; 1358 1359 tp = urb->context; 1360 if (!tp) 1361 return; 1362 1363 if (!test_bit(WORK_ENABLE, &tp->flags)) 1364 return; 1365 1366 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1367 return; 1368 1369 switch (status) { 1370 case 0: /* success */ 1371 break; 1372 case -ECONNRESET: /* unlink */ 1373 case -ESHUTDOWN: 1374 netif_device_detach(tp->netdev); 1375 case -ENOENT: 1376 case -EPROTO: 1377 netif_info(tp, intr, tp->netdev, 1378 "Stop submitting intr, status %d\n", status); 1379 return; 1380 case -EOVERFLOW: 1381 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1382 goto resubmit; 1383 /* -EPIPE: should clear the halt */ 1384 default: 1385 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1386 goto resubmit; 1387 } 1388 1389 d = urb->transfer_buffer; 1390 if (INTR_LINK & __le16_to_cpu(d[0])) { 1391 if (!netif_carrier_ok(tp->netdev)) { 1392 set_bit(RTL8152_LINK_CHG, &tp->flags); 1393 schedule_delayed_work(&tp->schedule, 0); 1394 } 1395 } else { 1396 if (netif_carrier_ok(tp->netdev)) { 1397 netif_stop_queue(tp->netdev); 1398 set_bit(RTL8152_LINK_CHG, &tp->flags); 1399 schedule_delayed_work(&tp->schedule, 0); 1400 } 1401 } 1402 1403 resubmit: 1404 res = usb_submit_urb(urb, GFP_ATOMIC); 1405 if (res == -ENODEV) { 1406 set_bit(RTL8152_UNPLUG, &tp->flags); 1407 netif_device_detach(tp->netdev); 1408 } else if (res) { 1409 netif_err(tp, intr, tp->netdev, 1410 "can't resubmit intr, status %d\n", res); 1411 } 1412 } 1413 1414 static inline void *rx_agg_align(void *data) 1415 { 1416 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1417 } 1418 1419 static inline void *tx_agg_align(void *data) 1420 { 1421 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1422 } 1423 1424 static void free_all_mem(struct r8152 *tp) 1425 { 1426 int i; 1427 1428 for (i = 0; i < RTL8152_MAX_RX; i++) { 1429 usb_free_urb(tp->rx_info[i].urb); 1430 tp->rx_info[i].urb = NULL; 1431 1432 kfree(tp->rx_info[i].buffer); 1433 tp->rx_info[i].buffer = NULL; 1434 tp->rx_info[i].head = NULL; 1435 } 1436 1437 for (i = 0; i < RTL8152_MAX_TX; i++) { 1438 usb_free_urb(tp->tx_info[i].urb); 1439 tp->tx_info[i].urb = NULL; 1440 1441 kfree(tp->tx_info[i].buffer); 1442 tp->tx_info[i].buffer = NULL; 1443 tp->tx_info[i].head = NULL; 1444 } 1445 1446 usb_free_urb(tp->intr_urb); 1447 tp->intr_urb = NULL; 1448 1449 kfree(tp->intr_buff); 1450 tp->intr_buff = NULL; 1451 } 1452 1453 static int alloc_all_mem(struct r8152 *tp) 1454 { 1455 struct net_device *netdev = tp->netdev; 1456 struct usb_interface *intf = tp->intf; 1457 struct usb_host_interface *alt = intf->cur_altsetting; 1458 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1459 struct urb *urb; 1460 int node, i; 1461 u8 *buf; 1462 1463 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1464 1465 spin_lock_init(&tp->rx_lock); 1466 spin_lock_init(&tp->tx_lock); 1467 INIT_LIST_HEAD(&tp->tx_free); 1468 INIT_LIST_HEAD(&tp->rx_done); 1469 skb_queue_head_init(&tp->tx_queue); 1470 skb_queue_head_init(&tp->rx_queue); 1471 1472 for (i = 0; i < RTL8152_MAX_RX; i++) { 1473 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1474 if (!buf) 1475 goto err1; 1476 1477 if (buf != rx_agg_align(buf)) { 1478 kfree(buf); 1479 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, 1480 node); 1481 if (!buf) 1482 goto err1; 1483 } 1484 1485 urb = usb_alloc_urb(0, GFP_KERNEL); 1486 if (!urb) { 1487 kfree(buf); 1488 goto err1; 1489 } 1490 1491 INIT_LIST_HEAD(&tp->rx_info[i].list); 1492 tp->rx_info[i].context = tp; 1493 tp->rx_info[i].urb = urb; 1494 tp->rx_info[i].buffer = buf; 1495 tp->rx_info[i].head = rx_agg_align(buf); 1496 } 1497 1498 for (i = 0; i < RTL8152_MAX_TX; i++) { 1499 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1500 if (!buf) 1501 goto err1; 1502 1503 if (buf != tx_agg_align(buf)) { 1504 kfree(buf); 1505 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 1506 node); 1507 if (!buf) 1508 goto err1; 1509 } 1510 1511 urb = usb_alloc_urb(0, GFP_KERNEL); 1512 if (!urb) { 1513 kfree(buf); 1514 goto err1; 1515 } 1516 1517 INIT_LIST_HEAD(&tp->tx_info[i].list); 1518 tp->tx_info[i].context = tp; 1519 tp->tx_info[i].urb = urb; 1520 tp->tx_info[i].buffer = buf; 1521 tp->tx_info[i].head = tx_agg_align(buf); 1522 1523 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1524 } 1525 1526 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1527 if (!tp->intr_urb) 1528 goto err1; 1529 1530 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1531 if (!tp->intr_buff) 1532 goto err1; 1533 1534 tp->intr_interval = (int)ep_intr->desc.bInterval; 1535 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1536 tp->intr_buff, INTBUFSIZE, intr_callback, 1537 tp, tp->intr_interval); 1538 1539 return 0; 1540 1541 err1: 1542 free_all_mem(tp); 1543 return -ENOMEM; 1544 } 1545 1546 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1547 { 1548 struct tx_agg *agg = NULL; 1549 unsigned long flags; 1550 1551 if (list_empty(&tp->tx_free)) 1552 return NULL; 1553 1554 spin_lock_irqsave(&tp->tx_lock, flags); 1555 if (!list_empty(&tp->tx_free)) { 1556 struct list_head *cursor; 1557 1558 cursor = tp->tx_free.next; 1559 list_del_init(cursor); 1560 agg = list_entry(cursor, struct tx_agg, list); 1561 } 1562 spin_unlock_irqrestore(&tp->tx_lock, flags); 1563 1564 return agg; 1565 } 1566 1567 /* r8152_csum_workaround() 1568 * The hw limites the value the transport offset. When the offset is out of the 1569 * range, calculate the checksum by sw. 1570 */ 1571 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1572 struct sk_buff_head *list) 1573 { 1574 if (skb_shinfo(skb)->gso_size) { 1575 netdev_features_t features = tp->netdev->features; 1576 struct sk_buff_head seg_list; 1577 struct sk_buff *segs, *nskb; 1578 1579 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 1580 segs = skb_gso_segment(skb, features); 1581 if (IS_ERR(segs) || !segs) 1582 goto drop; 1583 1584 __skb_queue_head_init(&seg_list); 1585 1586 do { 1587 nskb = segs; 1588 segs = segs->next; 1589 nskb->next = NULL; 1590 __skb_queue_tail(&seg_list, nskb); 1591 } while (segs); 1592 1593 skb_queue_splice(&seg_list, list); 1594 dev_kfree_skb(skb); 1595 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1596 if (skb_checksum_help(skb) < 0) 1597 goto drop; 1598 1599 __skb_queue_head(list, skb); 1600 } else { 1601 struct net_device_stats *stats; 1602 1603 drop: 1604 stats = &tp->netdev->stats; 1605 stats->tx_dropped++; 1606 dev_kfree_skb(skb); 1607 } 1608 } 1609 1610 /* msdn_giant_send_check() 1611 * According to the document of microsoft, the TCP Pseudo Header excludes the 1612 * packet length for IPv6 TCP large packets. 1613 */ 1614 static int msdn_giant_send_check(struct sk_buff *skb) 1615 { 1616 const struct ipv6hdr *ipv6h; 1617 struct tcphdr *th; 1618 int ret; 1619 1620 ret = skb_cow_head(skb, 0); 1621 if (ret) 1622 return ret; 1623 1624 ipv6h = ipv6_hdr(skb); 1625 th = tcp_hdr(skb); 1626 1627 th->check = 0; 1628 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1629 1630 return ret; 1631 } 1632 1633 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 1634 { 1635 if (skb_vlan_tag_present(skb)) { 1636 u32 opts2; 1637 1638 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); 1639 desc->opts2 |= cpu_to_le32(opts2); 1640 } 1641 } 1642 1643 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 1644 { 1645 u32 opts2 = le32_to_cpu(desc->opts2); 1646 1647 if (opts2 & RX_VLAN_TAG) 1648 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1649 swab16(opts2 & 0xffff)); 1650 } 1651 1652 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1653 struct sk_buff *skb, u32 len, u32 transport_offset) 1654 { 1655 u32 mss = skb_shinfo(skb)->gso_size; 1656 u32 opts1, opts2 = 0; 1657 int ret = TX_CSUM_SUCCESS; 1658 1659 WARN_ON_ONCE(len > TX_LEN_MAX); 1660 1661 opts1 = len | TX_FS | TX_LS; 1662 1663 if (mss) { 1664 if (transport_offset > GTTCPHO_MAX) { 1665 netif_warn(tp, tx_err, tp->netdev, 1666 "Invalid transport offset 0x%x for TSO\n", 1667 transport_offset); 1668 ret = TX_CSUM_TSO; 1669 goto unavailable; 1670 } 1671 1672 switch (vlan_get_protocol(skb)) { 1673 case htons(ETH_P_IP): 1674 opts1 |= GTSENDV4; 1675 break; 1676 1677 case htons(ETH_P_IPV6): 1678 if (msdn_giant_send_check(skb)) { 1679 ret = TX_CSUM_TSO; 1680 goto unavailable; 1681 } 1682 opts1 |= GTSENDV6; 1683 break; 1684 1685 default: 1686 WARN_ON_ONCE(1); 1687 break; 1688 } 1689 1690 opts1 |= transport_offset << GTTCPHO_SHIFT; 1691 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1692 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1693 u8 ip_protocol; 1694 1695 if (transport_offset > TCPHO_MAX) { 1696 netif_warn(tp, tx_err, tp->netdev, 1697 "Invalid transport offset 0x%x\n", 1698 transport_offset); 1699 ret = TX_CSUM_NONE; 1700 goto unavailable; 1701 } 1702 1703 switch (vlan_get_protocol(skb)) { 1704 case htons(ETH_P_IP): 1705 opts2 |= IPV4_CS; 1706 ip_protocol = ip_hdr(skb)->protocol; 1707 break; 1708 1709 case htons(ETH_P_IPV6): 1710 opts2 |= IPV6_CS; 1711 ip_protocol = ipv6_hdr(skb)->nexthdr; 1712 break; 1713 1714 default: 1715 ip_protocol = IPPROTO_RAW; 1716 break; 1717 } 1718 1719 if (ip_protocol == IPPROTO_TCP) 1720 opts2 |= TCP_CS; 1721 else if (ip_protocol == IPPROTO_UDP) 1722 opts2 |= UDP_CS; 1723 else 1724 WARN_ON_ONCE(1); 1725 1726 opts2 |= transport_offset << TCPHO_SHIFT; 1727 } 1728 1729 desc->opts2 = cpu_to_le32(opts2); 1730 desc->opts1 = cpu_to_le32(opts1); 1731 1732 unavailable: 1733 return ret; 1734 } 1735 1736 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1737 { 1738 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1739 int remain, ret; 1740 u8 *tx_data; 1741 1742 __skb_queue_head_init(&skb_head); 1743 spin_lock(&tx_queue->lock); 1744 skb_queue_splice_init(tx_queue, &skb_head); 1745 spin_unlock(&tx_queue->lock); 1746 1747 tx_data = agg->head; 1748 agg->skb_num = 0; 1749 agg->skb_len = 0; 1750 remain = agg_buf_sz; 1751 1752 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1753 struct tx_desc *tx_desc; 1754 struct sk_buff *skb; 1755 unsigned int len; 1756 u32 offset; 1757 1758 skb = __skb_dequeue(&skb_head); 1759 if (!skb) 1760 break; 1761 1762 len = skb->len + sizeof(*tx_desc); 1763 1764 if (len > remain) { 1765 __skb_queue_head(&skb_head, skb); 1766 break; 1767 } 1768 1769 tx_data = tx_agg_align(tx_data); 1770 tx_desc = (struct tx_desc *)tx_data; 1771 1772 offset = (u32)skb_transport_offset(skb); 1773 1774 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1775 r8152_csum_workaround(tp, skb, &skb_head); 1776 continue; 1777 } 1778 1779 rtl_tx_vlan_tag(tx_desc, skb); 1780 1781 tx_data += sizeof(*tx_desc); 1782 1783 len = skb->len; 1784 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1785 struct net_device_stats *stats = &tp->netdev->stats; 1786 1787 stats->tx_dropped++; 1788 dev_kfree_skb_any(skb); 1789 tx_data -= sizeof(*tx_desc); 1790 continue; 1791 } 1792 1793 tx_data += len; 1794 agg->skb_len += len; 1795 agg->skb_num++; 1796 1797 dev_kfree_skb_any(skb); 1798 1799 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1800 } 1801 1802 if (!skb_queue_empty(&skb_head)) { 1803 spin_lock(&tx_queue->lock); 1804 skb_queue_splice(&skb_head, tx_queue); 1805 spin_unlock(&tx_queue->lock); 1806 } 1807 1808 netif_tx_lock(tp->netdev); 1809 1810 if (netif_queue_stopped(tp->netdev) && 1811 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1812 netif_wake_queue(tp->netdev); 1813 1814 netif_tx_unlock(tp->netdev); 1815 1816 ret = usb_autopm_get_interface_async(tp->intf); 1817 if (ret < 0) 1818 goto out_tx_fill; 1819 1820 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1821 agg->head, (int)(tx_data - (u8 *)agg->head), 1822 (usb_complete_t)write_bulk_callback, agg); 1823 1824 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1825 if (ret < 0) 1826 usb_autopm_put_interface_async(tp->intf); 1827 1828 out_tx_fill: 1829 return ret; 1830 } 1831 1832 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1833 { 1834 u8 checksum = CHECKSUM_NONE; 1835 u32 opts2, opts3; 1836 1837 if (!(tp->netdev->features & NETIF_F_RXCSUM)) 1838 goto return_result; 1839 1840 opts2 = le32_to_cpu(rx_desc->opts2); 1841 opts3 = le32_to_cpu(rx_desc->opts3); 1842 1843 if (opts2 & RD_IPV4_CS) { 1844 if (opts3 & IPF) 1845 checksum = CHECKSUM_NONE; 1846 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) 1847 checksum = CHECKSUM_NONE; 1848 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) 1849 checksum = CHECKSUM_NONE; 1850 else 1851 checksum = CHECKSUM_UNNECESSARY; 1852 } else if (opts2 & RD_IPV6_CS) { 1853 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1854 checksum = CHECKSUM_UNNECESSARY; 1855 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1856 checksum = CHECKSUM_UNNECESSARY; 1857 } 1858 1859 return_result: 1860 return checksum; 1861 } 1862 1863 static int rx_bottom(struct r8152 *tp, int budget) 1864 { 1865 unsigned long flags; 1866 struct list_head *cursor, *next, rx_queue; 1867 int ret = 0, work_done = 0; 1868 struct napi_struct *napi = &tp->napi; 1869 1870 if (!skb_queue_empty(&tp->rx_queue)) { 1871 while (work_done < budget) { 1872 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); 1873 struct net_device *netdev = tp->netdev; 1874 struct net_device_stats *stats = &netdev->stats; 1875 unsigned int pkt_len; 1876 1877 if (!skb) 1878 break; 1879 1880 pkt_len = skb->len; 1881 napi_gro_receive(napi, skb); 1882 work_done++; 1883 stats->rx_packets++; 1884 stats->rx_bytes += pkt_len; 1885 } 1886 } 1887 1888 if (list_empty(&tp->rx_done)) 1889 goto out1; 1890 1891 INIT_LIST_HEAD(&rx_queue); 1892 spin_lock_irqsave(&tp->rx_lock, flags); 1893 list_splice_init(&tp->rx_done, &rx_queue); 1894 spin_unlock_irqrestore(&tp->rx_lock, flags); 1895 1896 list_for_each_safe(cursor, next, &rx_queue) { 1897 struct rx_desc *rx_desc; 1898 struct rx_agg *agg; 1899 int len_used = 0; 1900 struct urb *urb; 1901 u8 *rx_data; 1902 1903 list_del_init(cursor); 1904 1905 agg = list_entry(cursor, struct rx_agg, list); 1906 urb = agg->urb; 1907 if (urb->actual_length < ETH_ZLEN) 1908 goto submit; 1909 1910 rx_desc = agg->head; 1911 rx_data = agg->head; 1912 len_used += sizeof(struct rx_desc); 1913 1914 while (urb->actual_length > len_used) { 1915 struct net_device *netdev = tp->netdev; 1916 struct net_device_stats *stats = &netdev->stats; 1917 unsigned int pkt_len; 1918 struct sk_buff *skb; 1919 1920 /* limite the skb numbers for rx_queue */ 1921 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000)) 1922 break; 1923 1924 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1925 if (pkt_len < ETH_ZLEN) 1926 break; 1927 1928 len_used += pkt_len; 1929 if (urb->actual_length < len_used) 1930 break; 1931 1932 pkt_len -= ETH_FCS_LEN; 1933 rx_data += sizeof(struct rx_desc); 1934 1935 skb = napi_alloc_skb(napi, pkt_len); 1936 if (!skb) { 1937 stats->rx_dropped++; 1938 goto find_next_rx; 1939 } 1940 1941 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 1942 memcpy(skb->data, rx_data, pkt_len); 1943 skb_put(skb, pkt_len); 1944 skb->protocol = eth_type_trans(skb, netdev); 1945 rtl_rx_vlan_tag(rx_desc, skb); 1946 if (work_done < budget) { 1947 napi_gro_receive(napi, skb); 1948 work_done++; 1949 stats->rx_packets++; 1950 stats->rx_bytes += pkt_len; 1951 } else { 1952 __skb_queue_tail(&tp->rx_queue, skb); 1953 } 1954 1955 find_next_rx: 1956 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN); 1957 rx_desc = (struct rx_desc *)rx_data; 1958 len_used = (int)(rx_data - (u8 *)agg->head); 1959 len_used += sizeof(struct rx_desc); 1960 } 1961 1962 submit: 1963 if (!ret) { 1964 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1965 } else { 1966 urb->actual_length = 0; 1967 list_add_tail(&agg->list, next); 1968 } 1969 } 1970 1971 if (!list_empty(&rx_queue)) { 1972 spin_lock_irqsave(&tp->rx_lock, flags); 1973 list_splice_tail(&rx_queue, &tp->rx_done); 1974 spin_unlock_irqrestore(&tp->rx_lock, flags); 1975 } 1976 1977 out1: 1978 return work_done; 1979 } 1980 1981 static void tx_bottom(struct r8152 *tp) 1982 { 1983 int res; 1984 1985 do { 1986 struct tx_agg *agg; 1987 1988 if (skb_queue_empty(&tp->tx_queue)) 1989 break; 1990 1991 agg = r8152_get_tx_agg(tp); 1992 if (!agg) 1993 break; 1994 1995 res = r8152_tx_agg_fill(tp, agg); 1996 if (res) { 1997 struct net_device *netdev = tp->netdev; 1998 1999 if (res == -ENODEV) { 2000 set_bit(RTL8152_UNPLUG, &tp->flags); 2001 netif_device_detach(netdev); 2002 } else { 2003 struct net_device_stats *stats = &netdev->stats; 2004 unsigned long flags; 2005 2006 netif_warn(tp, tx_err, netdev, 2007 "failed tx_urb %d\n", res); 2008 stats->tx_dropped += agg->skb_num; 2009 2010 spin_lock_irqsave(&tp->tx_lock, flags); 2011 list_add_tail(&agg->list, &tp->tx_free); 2012 spin_unlock_irqrestore(&tp->tx_lock, flags); 2013 } 2014 } 2015 } while (res == 0); 2016 } 2017 2018 static void bottom_half(struct r8152 *tp) 2019 { 2020 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2021 return; 2022 2023 if (!test_bit(WORK_ENABLE, &tp->flags)) 2024 return; 2025 2026 /* When link down, the driver would cancel all bulks. */ 2027 /* This avoid the re-submitting bulk */ 2028 if (!netif_carrier_ok(tp->netdev)) 2029 return; 2030 2031 clear_bit(SCHEDULE_NAPI, &tp->flags); 2032 2033 tx_bottom(tp); 2034 } 2035 2036 static int r8152_poll(struct napi_struct *napi, int budget) 2037 { 2038 struct r8152 *tp = container_of(napi, struct r8152, napi); 2039 int work_done; 2040 2041 work_done = rx_bottom(tp, budget); 2042 bottom_half(tp); 2043 2044 if (work_done < budget) { 2045 if (!napi_complete_done(napi, work_done)) 2046 goto out; 2047 if (!list_empty(&tp->rx_done)) 2048 napi_schedule(napi); 2049 else if (!skb_queue_empty(&tp->tx_queue) && 2050 !list_empty(&tp->tx_free)) 2051 napi_schedule(napi); 2052 } 2053 2054 out: 2055 return work_done; 2056 } 2057 2058 static 2059 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 2060 { 2061 int ret; 2062 2063 /* The rx would be stopped, so skip submitting */ 2064 if (test_bit(RTL8152_UNPLUG, &tp->flags) || 2065 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) 2066 return 0; 2067 2068 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 2069 agg->head, agg_buf_sz, 2070 (usb_complete_t)read_bulk_callback, agg); 2071 2072 ret = usb_submit_urb(agg->urb, mem_flags); 2073 if (ret == -ENODEV) { 2074 set_bit(RTL8152_UNPLUG, &tp->flags); 2075 netif_device_detach(tp->netdev); 2076 } else if (ret) { 2077 struct urb *urb = agg->urb; 2078 unsigned long flags; 2079 2080 urb->actual_length = 0; 2081 spin_lock_irqsave(&tp->rx_lock, flags); 2082 list_add_tail(&agg->list, &tp->rx_done); 2083 spin_unlock_irqrestore(&tp->rx_lock, flags); 2084 2085 netif_err(tp, rx_err, tp->netdev, 2086 "Couldn't submit rx[%p], ret = %d\n", agg, ret); 2087 2088 napi_schedule(&tp->napi); 2089 } 2090 2091 return ret; 2092 } 2093 2094 static void rtl_drop_queued_tx(struct r8152 *tp) 2095 { 2096 struct net_device_stats *stats = &tp->netdev->stats; 2097 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 2098 struct sk_buff *skb; 2099 2100 if (skb_queue_empty(tx_queue)) 2101 return; 2102 2103 __skb_queue_head_init(&skb_head); 2104 spin_lock_bh(&tx_queue->lock); 2105 skb_queue_splice_init(tx_queue, &skb_head); 2106 spin_unlock_bh(&tx_queue->lock); 2107 2108 while ((skb = __skb_dequeue(&skb_head))) { 2109 dev_kfree_skb(skb); 2110 stats->tx_dropped++; 2111 } 2112 } 2113 2114 static void rtl8152_tx_timeout(struct net_device *netdev) 2115 { 2116 struct r8152 *tp = netdev_priv(netdev); 2117 2118 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 2119 2120 usb_queue_reset_device(tp->intf); 2121 } 2122 2123 static void rtl8152_set_rx_mode(struct net_device *netdev) 2124 { 2125 struct r8152 *tp = netdev_priv(netdev); 2126 2127 if (netif_carrier_ok(netdev)) { 2128 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2129 schedule_delayed_work(&tp->schedule, 0); 2130 } 2131 } 2132 2133 static void _rtl8152_set_rx_mode(struct net_device *netdev) 2134 { 2135 struct r8152 *tp = netdev_priv(netdev); 2136 u32 mc_filter[2]; /* Multicast hash filter */ 2137 __le32 tmp[2]; 2138 u32 ocp_data; 2139 2140 netif_stop_queue(netdev); 2141 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2142 ocp_data &= ~RCR_ACPT_ALL; 2143 ocp_data |= RCR_AB | RCR_APM; 2144 2145 if (netdev->flags & IFF_PROMISC) { 2146 /* Unconditionally log net taps. */ 2147 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 2148 ocp_data |= RCR_AM | RCR_AAP; 2149 mc_filter[1] = 0xffffffff; 2150 mc_filter[0] = 0xffffffff; 2151 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 2152 (netdev->flags & IFF_ALLMULTI)) { 2153 /* Too many to filter perfectly -- accept all multicasts. */ 2154 ocp_data |= RCR_AM; 2155 mc_filter[1] = 0xffffffff; 2156 mc_filter[0] = 0xffffffff; 2157 } else { 2158 struct netdev_hw_addr *ha; 2159 2160 mc_filter[1] = 0; 2161 mc_filter[0] = 0; 2162 netdev_for_each_mc_addr(ha, netdev) { 2163 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2164 2165 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2166 ocp_data |= RCR_AM; 2167 } 2168 } 2169 2170 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 2171 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 2172 2173 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 2174 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2175 netif_wake_queue(netdev); 2176 } 2177 2178 static netdev_features_t 2179 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 2180 netdev_features_t features) 2181 { 2182 u32 mss = skb_shinfo(skb)->gso_size; 2183 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 2184 int offset = skb_transport_offset(skb); 2185 2186 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) 2187 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2188 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 2189 features &= ~NETIF_F_GSO_MASK; 2190 2191 return features; 2192 } 2193 2194 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 2195 struct net_device *netdev) 2196 { 2197 struct r8152 *tp = netdev_priv(netdev); 2198 2199 skb_tx_timestamp(skb); 2200 2201 skb_queue_tail(&tp->tx_queue, skb); 2202 2203 if (!list_empty(&tp->tx_free)) { 2204 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2205 set_bit(SCHEDULE_NAPI, &tp->flags); 2206 schedule_delayed_work(&tp->schedule, 0); 2207 } else { 2208 usb_mark_last_busy(tp->udev); 2209 napi_schedule(&tp->napi); 2210 } 2211 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 2212 netif_stop_queue(netdev); 2213 } 2214 2215 return NETDEV_TX_OK; 2216 } 2217 2218 static void r8152b_reset_packet_filter(struct r8152 *tp) 2219 { 2220 u32 ocp_data; 2221 2222 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 2223 ocp_data &= ~FMC_FCR_MCU_EN; 2224 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2225 ocp_data |= FMC_FCR_MCU_EN; 2226 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2227 } 2228 2229 static void rtl8152_nic_reset(struct r8152 *tp) 2230 { 2231 int i; 2232 2233 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 2234 2235 for (i = 0; i < 1000; i++) { 2236 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 2237 break; 2238 usleep_range(100, 400); 2239 } 2240 } 2241 2242 static void set_tx_qlen(struct r8152 *tp) 2243 { 2244 struct net_device *netdev = tp->netdev; 2245 2246 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN + 2247 sizeof(struct tx_desc)); 2248 } 2249 2250 static inline u8 rtl8152_get_speed(struct r8152 *tp) 2251 { 2252 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 2253 } 2254 2255 static void rtl_set_eee_plus(struct r8152 *tp) 2256 { 2257 u32 ocp_data; 2258 u8 speed; 2259 2260 speed = rtl8152_get_speed(tp); 2261 if (speed & _10bps) { 2262 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2263 ocp_data |= EEEP_CR_EEEP_TX; 2264 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2265 } else { 2266 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2267 ocp_data &= ~EEEP_CR_EEEP_TX; 2268 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2269 } 2270 } 2271 2272 static void rxdy_gated_en(struct r8152 *tp, bool enable) 2273 { 2274 u32 ocp_data; 2275 2276 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 2277 if (enable) 2278 ocp_data |= RXDY_GATED_EN; 2279 else 2280 ocp_data &= ~RXDY_GATED_EN; 2281 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 2282 } 2283 2284 static int rtl_start_rx(struct r8152 *tp) 2285 { 2286 int i, ret = 0; 2287 2288 INIT_LIST_HEAD(&tp->rx_done); 2289 for (i = 0; i < RTL8152_MAX_RX; i++) { 2290 INIT_LIST_HEAD(&tp->rx_info[i].list); 2291 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 2292 if (ret) 2293 break; 2294 } 2295 2296 if (ret && ++i < RTL8152_MAX_RX) { 2297 struct list_head rx_queue; 2298 unsigned long flags; 2299 2300 INIT_LIST_HEAD(&rx_queue); 2301 2302 do { 2303 struct rx_agg *agg = &tp->rx_info[i++]; 2304 struct urb *urb = agg->urb; 2305 2306 urb->actual_length = 0; 2307 list_add_tail(&agg->list, &rx_queue); 2308 } while (i < RTL8152_MAX_RX); 2309 2310 spin_lock_irqsave(&tp->rx_lock, flags); 2311 list_splice_tail(&rx_queue, &tp->rx_done); 2312 spin_unlock_irqrestore(&tp->rx_lock, flags); 2313 } 2314 2315 return ret; 2316 } 2317 2318 static int rtl_stop_rx(struct r8152 *tp) 2319 { 2320 int i; 2321 2322 for (i = 0; i < RTL8152_MAX_RX; i++) 2323 usb_kill_urb(tp->rx_info[i].urb); 2324 2325 while (!skb_queue_empty(&tp->rx_queue)) 2326 dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); 2327 2328 return 0; 2329 } 2330 2331 static int rtl_enable(struct r8152 *tp) 2332 { 2333 u32 ocp_data; 2334 2335 r8152b_reset_packet_filter(tp); 2336 2337 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2338 ocp_data |= CR_RE | CR_TE; 2339 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2340 2341 rxdy_gated_en(tp, false); 2342 2343 return 0; 2344 } 2345 2346 static int rtl8152_enable(struct r8152 *tp) 2347 { 2348 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2349 return -ENODEV; 2350 2351 set_tx_qlen(tp); 2352 rtl_set_eee_plus(tp); 2353 2354 return rtl_enable(tp); 2355 } 2356 2357 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) 2358 { 2359 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, 2360 OWN_UPDATE | OWN_CLEAR); 2361 } 2362 2363 static void r8153_set_rx_early_timeout(struct r8152 *tp) 2364 { 2365 u32 ocp_data = tp->coalesce / 8; 2366 2367 switch (tp->version) { 2368 case RTL_VER_03: 2369 case RTL_VER_04: 2370 case RTL_VER_05: 2371 case RTL_VER_06: 2372 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2373 ocp_data); 2374 break; 2375 2376 case RTL_VER_08: 2377 case RTL_VER_09: 2378 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout 2379 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns. 2380 */ 2381 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2382 128 / 8); 2383 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, 2384 ocp_data); 2385 r8153b_rx_agg_chg_indicate(tp); 2386 break; 2387 2388 default: 2389 break; 2390 } 2391 } 2392 2393 static void r8153_set_rx_early_size(struct r8152 *tp) 2394 { 2395 u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu); 2396 2397 switch (tp->version) { 2398 case RTL_VER_03: 2399 case RTL_VER_04: 2400 case RTL_VER_05: 2401 case RTL_VER_06: 2402 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2403 ocp_data / 4); 2404 break; 2405 case RTL_VER_08: 2406 case RTL_VER_09: 2407 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2408 ocp_data / 8); 2409 r8153b_rx_agg_chg_indicate(tp); 2410 break; 2411 default: 2412 WARN_ON_ONCE(1); 2413 break; 2414 } 2415 } 2416 2417 static int rtl8153_enable(struct r8152 *tp) 2418 { 2419 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2420 return -ENODEV; 2421 2422 set_tx_qlen(tp); 2423 rtl_set_eee_plus(tp); 2424 r8153_set_rx_early_timeout(tp); 2425 r8153_set_rx_early_size(tp); 2426 2427 return rtl_enable(tp); 2428 } 2429 2430 static void rtl_disable(struct r8152 *tp) 2431 { 2432 u32 ocp_data; 2433 int i; 2434 2435 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2436 rtl_drop_queued_tx(tp); 2437 return; 2438 } 2439 2440 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2441 ocp_data &= ~RCR_ACPT_ALL; 2442 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2443 2444 rtl_drop_queued_tx(tp); 2445 2446 for (i = 0; i < RTL8152_MAX_TX; i++) 2447 usb_kill_urb(tp->tx_info[i].urb); 2448 2449 rxdy_gated_en(tp, true); 2450 2451 for (i = 0; i < 1000; i++) { 2452 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2453 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2454 break; 2455 usleep_range(1000, 2000); 2456 } 2457 2458 for (i = 0; i < 1000; i++) { 2459 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2460 break; 2461 usleep_range(1000, 2000); 2462 } 2463 2464 rtl_stop_rx(tp); 2465 2466 rtl8152_nic_reset(tp); 2467 } 2468 2469 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2470 { 2471 u32 ocp_data; 2472 2473 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2474 if (enable) 2475 ocp_data |= POWER_CUT; 2476 else 2477 ocp_data &= ~POWER_CUT; 2478 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2479 2480 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2481 ocp_data &= ~RESUME_INDICATE; 2482 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2483 } 2484 2485 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 2486 { 2487 u32 ocp_data; 2488 2489 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2490 if (enable) 2491 ocp_data |= CPCR_RX_VLAN; 2492 else 2493 ocp_data &= ~CPCR_RX_VLAN; 2494 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2495 } 2496 2497 static int rtl8152_set_features(struct net_device *dev, 2498 netdev_features_t features) 2499 { 2500 netdev_features_t changed = features ^ dev->features; 2501 struct r8152 *tp = netdev_priv(dev); 2502 int ret; 2503 2504 ret = usb_autopm_get_interface(tp->intf); 2505 if (ret < 0) 2506 goto out; 2507 2508 mutex_lock(&tp->control); 2509 2510 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 2511 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2512 rtl_rx_vlan_en(tp, true); 2513 else 2514 rtl_rx_vlan_en(tp, false); 2515 } 2516 2517 mutex_unlock(&tp->control); 2518 2519 usb_autopm_put_interface(tp->intf); 2520 2521 out: 2522 return ret; 2523 } 2524 2525 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2526 2527 static u32 __rtl_get_wol(struct r8152 *tp) 2528 { 2529 u32 ocp_data; 2530 u32 wolopts = 0; 2531 2532 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2533 if (ocp_data & LINK_ON_WAKE_EN) 2534 wolopts |= WAKE_PHY; 2535 2536 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2537 if (ocp_data & UWF_EN) 2538 wolopts |= WAKE_UCAST; 2539 if (ocp_data & BWF_EN) 2540 wolopts |= WAKE_BCAST; 2541 if (ocp_data & MWF_EN) 2542 wolopts |= WAKE_MCAST; 2543 2544 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2545 if (ocp_data & MAGIC_EN) 2546 wolopts |= WAKE_MAGIC; 2547 2548 return wolopts; 2549 } 2550 2551 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2552 { 2553 u32 ocp_data; 2554 2555 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2556 2557 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2558 ocp_data &= ~LINK_ON_WAKE_EN; 2559 if (wolopts & WAKE_PHY) 2560 ocp_data |= LINK_ON_WAKE_EN; 2561 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2562 2563 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2564 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); 2565 if (wolopts & WAKE_UCAST) 2566 ocp_data |= UWF_EN; 2567 if (wolopts & WAKE_BCAST) 2568 ocp_data |= BWF_EN; 2569 if (wolopts & WAKE_MCAST) 2570 ocp_data |= MWF_EN; 2571 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2572 2573 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2574 2575 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2576 ocp_data &= ~MAGIC_EN; 2577 if (wolopts & WAKE_MAGIC) 2578 ocp_data |= MAGIC_EN; 2579 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2580 2581 if (wolopts & WAKE_ANY) 2582 device_set_wakeup_enable(&tp->udev->dev, true); 2583 else 2584 device_set_wakeup_enable(&tp->udev->dev, false); 2585 } 2586 2587 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable) 2588 { 2589 /* MAC clock speed down */ 2590 if (enable) { 2591 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 2592 ALDPS_SPDWN_RATIO); 2593 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 2594 EEE_SPDWN_RATIO); 2595 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 2596 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | 2597 U1U2_SPDWN_EN | L1_SPDWN_EN); 2598 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 2599 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | 2600 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN | 2601 TP1000_SPDWN_EN); 2602 } else { 2603 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); 2604 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); 2605 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); 2606 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); 2607 } 2608 } 2609 2610 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2611 { 2612 u8 u1u2[8]; 2613 2614 if (enable) 2615 memset(u1u2, 0xff, sizeof(u1u2)); 2616 else 2617 memset(u1u2, 0x00, sizeof(u1u2)); 2618 2619 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2620 } 2621 2622 static void r8153b_u1u2en(struct r8152 *tp, bool enable) 2623 { 2624 u32 ocp_data; 2625 2626 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); 2627 if (enable) 2628 ocp_data |= LPM_U1U2_EN; 2629 else 2630 ocp_data &= ~LPM_U1U2_EN; 2631 2632 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); 2633 } 2634 2635 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2636 { 2637 u32 ocp_data; 2638 2639 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2640 if (enable) 2641 ocp_data |= U2P3_ENABLE; 2642 else 2643 ocp_data &= ~U2P3_ENABLE; 2644 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2645 } 2646 2647 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear) 2648 { 2649 u32 ocp_data; 2650 2651 ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS); 2652 ocp_data &= ~clear; 2653 ocp_data |= set; 2654 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data); 2655 } 2656 2657 static void r8153b_green_en(struct r8152 *tp, bool enable) 2658 { 2659 u16 data; 2660 2661 if (enable) { 2662 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ 2663 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ 2664 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ 2665 } else { 2666 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ 2667 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ 2668 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ 2669 } 2670 2671 data = sram_read(tp, SRAM_GREEN_CFG); 2672 data |= GREEN_ETH_EN; 2673 sram_write(tp, SRAM_GREEN_CFG, data); 2674 2675 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0); 2676 } 2677 2678 static u16 r8153_phy_status(struct r8152 *tp, u16 desired) 2679 { 2680 u16 data; 2681 int i; 2682 2683 for (i = 0; i < 500; i++) { 2684 data = ocp_reg_read(tp, OCP_PHY_STATUS); 2685 data &= PHY_STAT_MASK; 2686 if (desired) { 2687 if (data == desired) 2688 break; 2689 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN || 2690 data == PHY_STAT_EXT_INIT) { 2691 break; 2692 } 2693 2694 msleep(20); 2695 } 2696 2697 return data; 2698 } 2699 2700 static void r8153b_ups_en(struct r8152 *tp, bool enable) 2701 { 2702 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); 2703 2704 if (enable) { 2705 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; 2706 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2707 2708 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 2709 ocp_data |= BIT(0); 2710 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 2711 } else { 2712 u16 data; 2713 2714 ocp_data &= ~(UPS_EN | USP_PREWAKE); 2715 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2716 2717 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 2718 ocp_data &= ~BIT(0); 2719 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 2720 2721 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2722 ocp_data &= ~PCUT_STATUS; 2723 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2724 2725 data = r8153_phy_status(tp, 0); 2726 2727 switch (data) { 2728 case PHY_STAT_PWRDN: 2729 case PHY_STAT_EXT_INIT: 2730 r8153b_green_en(tp, 2731 test_bit(GREEN_ETHERNET, &tp->flags)); 2732 2733 data = r8152_mdio_read(tp, MII_BMCR); 2734 data &= ~BMCR_PDOWN; 2735 data |= BMCR_RESET; 2736 r8152_mdio_write(tp, MII_BMCR, data); 2737 2738 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 2739 2740 default: 2741 if (data != PHY_STAT_LAN_ON) 2742 netif_warn(tp, link, tp->netdev, 2743 "PHY not ready"); 2744 break; 2745 } 2746 } 2747 } 2748 2749 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2750 { 2751 u32 ocp_data; 2752 2753 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2754 if (enable) 2755 ocp_data |= PWR_EN | PHASE2_EN; 2756 else 2757 ocp_data &= ~(PWR_EN | PHASE2_EN); 2758 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2759 2760 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2761 ocp_data &= ~PCUT_STATUS; 2762 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2763 } 2764 2765 static void r8153b_power_cut_en(struct r8152 *tp, bool enable) 2766 { 2767 u32 ocp_data; 2768 2769 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2770 if (enable) 2771 ocp_data |= PWR_EN | PHASE2_EN; 2772 else 2773 ocp_data &= ~PWR_EN; 2774 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2775 2776 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2777 ocp_data &= ~PCUT_STATUS; 2778 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2779 } 2780 2781 static void r8153b_queue_wake(struct r8152 *tp, bool enable) 2782 { 2783 u32 ocp_data; 2784 2785 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a); 2786 if (enable) 2787 ocp_data |= BIT(0); 2788 else 2789 ocp_data &= ~BIT(0); 2790 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data); 2791 2792 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c); 2793 ocp_data &= ~BIT(0); 2794 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data); 2795 } 2796 2797 static bool rtl_can_wakeup(struct r8152 *tp) 2798 { 2799 struct usb_device *udev = tp->udev; 2800 2801 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); 2802 } 2803 2804 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 2805 { 2806 if (enable) { 2807 u32 ocp_data; 2808 2809 __rtl_set_wol(tp, WAKE_ANY); 2810 2811 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2812 2813 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2814 ocp_data |= LINK_OFF_WAKE_EN; 2815 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2816 2817 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2818 } else { 2819 u32 ocp_data; 2820 2821 __rtl_set_wol(tp, tp->saved_wolopts); 2822 2823 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2824 2825 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2826 ocp_data &= ~LINK_OFF_WAKE_EN; 2827 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2828 2829 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2830 } 2831 } 2832 2833 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) 2834 { 2835 if (enable) { 2836 r8153_u1u2en(tp, false); 2837 r8153_u2p3en(tp, false); 2838 r8153_mac_clk_spd(tp, true); 2839 rtl_runtime_suspend_enable(tp, true); 2840 } else { 2841 rtl_runtime_suspend_enable(tp, false); 2842 r8153_mac_clk_spd(tp, false); 2843 2844 switch (tp->version) { 2845 case RTL_VER_03: 2846 case RTL_VER_04: 2847 break; 2848 case RTL_VER_05: 2849 case RTL_VER_06: 2850 default: 2851 r8153_u2p3en(tp, true); 2852 break; 2853 } 2854 2855 r8153_u1u2en(tp, true); 2856 } 2857 } 2858 2859 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable) 2860 { 2861 if (enable) { 2862 r8153b_queue_wake(tp, true); 2863 r8153b_u1u2en(tp, false); 2864 r8153_u2p3en(tp, false); 2865 rtl_runtime_suspend_enable(tp, true); 2866 r8153b_ups_en(tp, true); 2867 } else { 2868 r8153b_ups_en(tp, false); 2869 r8153b_queue_wake(tp, false); 2870 rtl_runtime_suspend_enable(tp, false); 2871 r8153_u2p3en(tp, true); 2872 r8153b_u1u2en(tp, true); 2873 } 2874 } 2875 2876 static void r8153_teredo_off(struct r8152 *tp) 2877 { 2878 u32 ocp_data; 2879 2880 switch (tp->version) { 2881 case RTL_VER_01: 2882 case RTL_VER_02: 2883 case RTL_VER_03: 2884 case RTL_VER_04: 2885 case RTL_VER_05: 2886 case RTL_VER_06: 2887 case RTL_VER_07: 2888 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2889 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | 2890 OOB_TEREDO_EN); 2891 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2892 break; 2893 2894 case RTL_VER_08: 2895 case RTL_VER_09: 2896 /* The bit 0 ~ 7 are relative with teredo settings. They are 2897 * W1C (write 1 to clear), so set all 1 to disable it. 2898 */ 2899 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); 2900 break; 2901 2902 default: 2903 break; 2904 } 2905 2906 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 2907 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 2908 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 2909 } 2910 2911 static void rtl_reset_bmu(struct r8152 *tp) 2912 { 2913 u32 ocp_data; 2914 2915 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); 2916 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 2917 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2918 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 2919 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2920 } 2921 2922 static void r8152_aldps_en(struct r8152 *tp, bool enable) 2923 { 2924 if (enable) { 2925 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 2926 LINKENA | DIS_SDSAVE); 2927 } else { 2928 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | 2929 DIS_SDSAVE); 2930 msleep(20); 2931 } 2932 } 2933 2934 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 2935 { 2936 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 2937 ocp_reg_write(tp, OCP_EEE_DATA, reg); 2938 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 2939 } 2940 2941 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 2942 { 2943 u16 data; 2944 2945 r8152_mmd_indirect(tp, dev, reg); 2946 data = ocp_reg_read(tp, OCP_EEE_DATA); 2947 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 2948 2949 return data; 2950 } 2951 2952 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 2953 { 2954 r8152_mmd_indirect(tp, dev, reg); 2955 ocp_reg_write(tp, OCP_EEE_DATA, data); 2956 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 2957 } 2958 2959 static void r8152_eee_en(struct r8152 *tp, bool enable) 2960 { 2961 u16 config1, config2, config3; 2962 u32 ocp_data; 2963 2964 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 2965 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 2966 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 2967 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 2968 2969 if (enable) { 2970 ocp_data |= EEE_RX_EN | EEE_TX_EN; 2971 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 2972 config1 |= sd_rise_time(1); 2973 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 2974 config3 |= fast_snr(42); 2975 } else { 2976 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 2977 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 2978 RX_QUIET_EN); 2979 config1 |= sd_rise_time(7); 2980 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 2981 config3 |= fast_snr(511); 2982 } 2983 2984 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 2985 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 2986 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 2987 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 2988 } 2989 2990 static void r8152b_enable_eee(struct r8152 *tp) 2991 { 2992 r8152_eee_en(tp, true); 2993 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); 2994 } 2995 2996 static void r8152b_enable_fc(struct r8152 *tp) 2997 { 2998 u16 anar; 2999 3000 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3001 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 3002 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3003 } 3004 3005 static void rtl8152_disable(struct r8152 *tp) 3006 { 3007 r8152_aldps_en(tp, false); 3008 rtl_disable(tp); 3009 r8152_aldps_en(tp, true); 3010 } 3011 3012 static void r8152b_hw_phy_cfg(struct r8152 *tp) 3013 { 3014 r8152b_enable_eee(tp); 3015 r8152_aldps_en(tp, true); 3016 r8152b_enable_fc(tp); 3017 3018 set_bit(PHY_RESET, &tp->flags); 3019 } 3020 3021 static void r8152b_exit_oob(struct r8152 *tp) 3022 { 3023 u32 ocp_data; 3024 int i; 3025 3026 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3027 ocp_data &= ~RCR_ACPT_ALL; 3028 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3029 3030 rxdy_gated_en(tp, true); 3031 r8153_teredo_off(tp); 3032 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3033 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 3034 3035 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3036 ocp_data &= ~NOW_IS_OOB; 3037 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3038 3039 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3040 ocp_data &= ~MCU_BORW_EN; 3041 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3042 3043 for (i = 0; i < 1000; i++) { 3044 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3045 if (ocp_data & LINK_LIST_READY) 3046 break; 3047 usleep_range(1000, 2000); 3048 } 3049 3050 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3051 ocp_data |= RE_INIT_LL; 3052 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3053 3054 for (i = 0; i < 1000; i++) { 3055 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3056 if (ocp_data & LINK_LIST_READY) 3057 break; 3058 usleep_range(1000, 2000); 3059 } 3060 3061 rtl8152_nic_reset(tp); 3062 3063 /* rx share fifo credit full threshold */ 3064 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3065 3066 if (tp->udev->speed == USB_SPEED_FULL || 3067 tp->udev->speed == USB_SPEED_LOW) { 3068 /* rx share fifo credit near full threshold */ 3069 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3070 RXFIFO_THR2_FULL); 3071 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3072 RXFIFO_THR3_FULL); 3073 } else { 3074 /* rx share fifo credit near full threshold */ 3075 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3076 RXFIFO_THR2_HIGH); 3077 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3078 RXFIFO_THR3_HIGH); 3079 } 3080 3081 /* TX share fifo free credit full threshold */ 3082 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 3083 3084 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 3085 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 3086 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 3087 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 3088 3089 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3090 3091 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3092 3093 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3094 ocp_data |= TCR0_AUTO_FIFO; 3095 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3096 } 3097 3098 static void r8152b_enter_oob(struct r8152 *tp) 3099 { 3100 u32 ocp_data; 3101 int i; 3102 3103 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3104 ocp_data &= ~NOW_IS_OOB; 3105 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3106 3107 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 3108 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 3109 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 3110 3111 rtl_disable(tp); 3112 3113 for (i = 0; i < 1000; i++) { 3114 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3115 if (ocp_data & LINK_LIST_READY) 3116 break; 3117 usleep_range(1000, 2000); 3118 } 3119 3120 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3121 ocp_data |= RE_INIT_LL; 3122 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3123 3124 for (i = 0; i < 1000; i++) { 3125 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3126 if (ocp_data & LINK_LIST_READY) 3127 break; 3128 usleep_range(1000, 2000); 3129 } 3130 3131 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3132 3133 rtl_rx_vlan_en(tp, true); 3134 3135 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 3136 ocp_data |= ALDPS_PROXY_MODE; 3137 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 3138 3139 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3140 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3141 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3142 3143 rxdy_gated_en(tp, false); 3144 3145 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3146 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3147 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3148 } 3149 3150 static int r8153_patch_request(struct r8152 *tp, bool request) 3151 { 3152 u16 data; 3153 int i; 3154 3155 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD); 3156 if (request) 3157 data |= PATCH_REQUEST; 3158 else 3159 data &= ~PATCH_REQUEST; 3160 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); 3161 3162 for (i = 0; request && i < 5000; i++) { 3163 usleep_range(1000, 2000); 3164 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY) 3165 break; 3166 } 3167 3168 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) { 3169 netif_err(tp, drv, tp->netdev, "patch request fail\n"); 3170 r8153_patch_request(tp, false); 3171 return -ETIME; 3172 } else { 3173 return 0; 3174 } 3175 } 3176 3177 static void r8153_aldps_en(struct r8152 *tp, bool enable) 3178 { 3179 u16 data; 3180 3181 data = ocp_reg_read(tp, OCP_POWER_CFG); 3182 if (enable) { 3183 data |= EN_ALDPS; 3184 ocp_reg_write(tp, OCP_POWER_CFG, data); 3185 } else { 3186 int i; 3187 3188 data &= ~EN_ALDPS; 3189 ocp_reg_write(tp, OCP_POWER_CFG, data); 3190 for (i = 0; i < 20; i++) { 3191 usleep_range(1000, 2000); 3192 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) 3193 break; 3194 } 3195 } 3196 } 3197 3198 static void r8153b_aldps_en(struct r8152 *tp, bool enable) 3199 { 3200 r8153_aldps_en(tp, enable); 3201 3202 if (enable) 3203 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0); 3204 else 3205 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS); 3206 } 3207 3208 static void r8153_eee_en(struct r8152 *tp, bool enable) 3209 { 3210 u32 ocp_data; 3211 u16 config; 3212 3213 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3214 config = ocp_reg_read(tp, OCP_EEE_CFG); 3215 3216 if (enable) { 3217 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3218 config |= EEE10_EN; 3219 } else { 3220 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3221 config &= ~EEE10_EN; 3222 } 3223 3224 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3225 ocp_reg_write(tp, OCP_EEE_CFG, config); 3226 } 3227 3228 static void r8153b_eee_en(struct r8152 *tp, bool enable) 3229 { 3230 r8153_eee_en(tp, enable); 3231 3232 if (enable) 3233 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0); 3234 else 3235 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE); 3236 } 3237 3238 static void r8153b_enable_fc(struct r8152 *tp) 3239 { 3240 r8152b_enable_fc(tp); 3241 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0); 3242 } 3243 3244 static void r8153_hw_phy_cfg(struct r8152 *tp) 3245 { 3246 u32 ocp_data; 3247 u16 data; 3248 3249 /* disable ALDPS before updating the PHY parameters */ 3250 r8153_aldps_en(tp, false); 3251 3252 /* disable EEE before updating the PHY parameters */ 3253 r8153_eee_en(tp, false); 3254 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3255 3256 if (tp->version == RTL_VER_03) { 3257 data = ocp_reg_read(tp, OCP_EEE_CFG); 3258 data &= ~CTAP_SHORT_EN; 3259 ocp_reg_write(tp, OCP_EEE_CFG, data); 3260 } 3261 3262 data = ocp_reg_read(tp, OCP_POWER_CFG); 3263 data |= EEE_CLKDIV_EN; 3264 ocp_reg_write(tp, OCP_POWER_CFG, data); 3265 3266 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3267 data |= EN_10M_BGOFF; 3268 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3269 data = ocp_reg_read(tp, OCP_POWER_CFG); 3270 data |= EN_10M_PLLOFF; 3271 ocp_reg_write(tp, OCP_POWER_CFG, data); 3272 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 3273 3274 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3275 ocp_data |= PFM_PWM_SWITCH; 3276 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3277 3278 /* Enable LPF corner auto tune */ 3279 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 3280 3281 /* Adjust 10M Amplitude */ 3282 sram_write(tp, SRAM_10M_AMP1, 0x00af); 3283 sram_write(tp, SRAM_10M_AMP2, 0x0208); 3284 3285 r8153_eee_en(tp, true); 3286 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3287 3288 r8153_aldps_en(tp, true); 3289 r8152b_enable_fc(tp); 3290 3291 switch (tp->version) { 3292 case RTL_VER_03: 3293 case RTL_VER_04: 3294 break; 3295 case RTL_VER_05: 3296 case RTL_VER_06: 3297 default: 3298 r8153_u2p3en(tp, true); 3299 break; 3300 } 3301 3302 set_bit(PHY_RESET, &tp->flags); 3303 } 3304 3305 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) 3306 { 3307 u32 ocp_data; 3308 3309 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr); 3310 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD); 3311 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */ 3312 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA); 3313 3314 return ocp_data; 3315 } 3316 3317 static void r8153b_hw_phy_cfg(struct r8152 *tp) 3318 { 3319 u32 ocp_data, ups_flags = 0; 3320 u16 data; 3321 3322 /* disable ALDPS before updating the PHY parameters */ 3323 r8153b_aldps_en(tp, false); 3324 3325 /* disable EEE before updating the PHY parameters */ 3326 r8153b_eee_en(tp, false); 3327 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3328 3329 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); 3330 3331 data = sram_read(tp, SRAM_GREEN_CFG); 3332 data |= R_TUNE_EN; 3333 sram_write(tp, SRAM_GREEN_CFG, data); 3334 data = ocp_reg_read(tp, OCP_NCTL_CFG); 3335 data |= PGA_RETURN_EN; 3336 ocp_reg_write(tp, OCP_NCTL_CFG, data); 3337 3338 /* ADC Bias Calibration: 3339 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake 3340 * bit (bit3) to rebuild the real 16-bit data. Write the data to the 3341 * ADC ioffset. 3342 */ 3343 ocp_data = r8152_efuse_read(tp, 0x7d); 3344 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); 3345 if (data != 0xffff) 3346 ocp_reg_write(tp, OCP_ADC_IOFFSET, data); 3347 3348 /* ups mode tx-link-pulse timing adjustment: 3349 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] 3350 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt 3351 */ 3352 ocp_data = ocp_reg_read(tp, 0xc426); 3353 ocp_data &= 0x3fff; 3354 if (ocp_data) { 3355 u32 swr_cnt_1ms_ini; 3356 3357 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; 3358 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); 3359 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; 3360 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); 3361 } 3362 3363 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3364 ocp_data |= PFM_PWM_SWITCH; 3365 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3366 3367 /* Advnace EEE */ 3368 if (!r8153_patch_request(tp, true)) { 3369 data = ocp_reg_read(tp, OCP_POWER_CFG); 3370 data |= EEE_CLKDIV_EN; 3371 ocp_reg_write(tp, OCP_POWER_CFG, data); 3372 3373 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3374 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV; 3375 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3376 3377 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); 3378 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5)); 3379 3380 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV | 3381 UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN | 3382 UPS_FLAGS_EEE_PLLOFF_GIGA; 3383 3384 r8153_patch_request(tp, false); 3385 } 3386 3387 r8153b_ups_flags_w1w0(tp, ups_flags, 0); 3388 3389 r8153b_eee_en(tp, true); 3390 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3391 3392 r8153b_aldps_en(tp, true); 3393 r8153b_enable_fc(tp); 3394 r8153_u2p3en(tp, true); 3395 3396 set_bit(PHY_RESET, &tp->flags); 3397 } 3398 3399 static void r8153_first_init(struct r8152 *tp) 3400 { 3401 u32 ocp_data; 3402 int i; 3403 3404 r8153_mac_clk_spd(tp, false); 3405 rxdy_gated_en(tp, true); 3406 r8153_teredo_off(tp); 3407 3408 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3409 ocp_data &= ~RCR_ACPT_ALL; 3410 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3411 3412 rtl8152_nic_reset(tp); 3413 rtl_reset_bmu(tp); 3414 3415 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3416 ocp_data &= ~NOW_IS_OOB; 3417 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3418 3419 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3420 ocp_data &= ~MCU_BORW_EN; 3421 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3422 3423 for (i = 0; i < 1000; i++) { 3424 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3425 if (ocp_data & LINK_LIST_READY) 3426 break; 3427 usleep_range(1000, 2000); 3428 } 3429 3430 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3431 ocp_data |= RE_INIT_LL; 3432 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3433 3434 for (i = 0; i < 1000; i++) { 3435 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3436 if (ocp_data & LINK_LIST_READY) 3437 break; 3438 usleep_range(1000, 2000); 3439 } 3440 3441 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3442 3443 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3444 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3445 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 3446 3447 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3448 ocp_data |= TCR0_AUTO_FIFO; 3449 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3450 3451 rtl8152_nic_reset(tp); 3452 3453 /* rx share fifo credit full threshold */ 3454 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3455 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 3456 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 3457 /* TX share fifo free credit full threshold */ 3458 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 3459 } 3460 3461 static void r8153_enter_oob(struct r8152 *tp) 3462 { 3463 u32 ocp_data; 3464 int i; 3465 3466 r8153_mac_clk_spd(tp, true); 3467 3468 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3469 ocp_data &= ~NOW_IS_OOB; 3470 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3471 3472 rtl_disable(tp); 3473 rtl_reset_bmu(tp); 3474 3475 for (i = 0; i < 1000; i++) { 3476 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3477 if (ocp_data & LINK_LIST_READY) 3478 break; 3479 usleep_range(1000, 2000); 3480 } 3481 3482 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3483 ocp_data |= RE_INIT_LL; 3484 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3485 3486 for (i = 0; i < 1000; i++) { 3487 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3488 if (ocp_data & LINK_LIST_READY) 3489 break; 3490 usleep_range(1000, 2000); 3491 } 3492 3493 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3494 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3495 3496 switch (tp->version) { 3497 case RTL_VER_03: 3498 case RTL_VER_04: 3499 case RTL_VER_05: 3500 case RTL_VER_06: 3501 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 3502 ocp_data &= ~TEREDO_WAKE_MASK; 3503 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 3504 break; 3505 3506 case RTL_VER_08: 3507 case RTL_VER_09: 3508 /* Clear teredo wake event. bit[15:8] is the teredo wakeup 3509 * type. Set it to zero. bits[7:0] are the W1C bits about 3510 * the events. Set them to all 1 to clear them. 3511 */ 3512 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); 3513 break; 3514 3515 default: 3516 break; 3517 } 3518 3519 rtl_rx_vlan_en(tp, true); 3520 3521 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 3522 ocp_data |= ALDPS_PROXY_MODE; 3523 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 3524 3525 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3526 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3527 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3528 3529 rxdy_gated_en(tp, false); 3530 3531 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3532 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3533 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3534 } 3535 3536 static void rtl8153_disable(struct r8152 *tp) 3537 { 3538 r8153_aldps_en(tp, false); 3539 rtl_disable(tp); 3540 rtl_reset_bmu(tp); 3541 r8153_aldps_en(tp, true); 3542 } 3543 3544 static void rtl8153b_disable(struct r8152 *tp) 3545 { 3546 r8153b_aldps_en(tp, false); 3547 rtl_disable(tp); 3548 rtl_reset_bmu(tp); 3549 r8153b_aldps_en(tp, true); 3550 } 3551 3552 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 3553 { 3554 u16 bmcr, anar, gbcr; 3555 enum spd_duplex speed_duplex; 3556 int ret = 0; 3557 3558 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3559 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 3560 ADVERTISE_100HALF | ADVERTISE_100FULL); 3561 if (tp->mii.supports_gmii) { 3562 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 3563 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 3564 } else { 3565 gbcr = 0; 3566 } 3567 3568 if (autoneg == AUTONEG_DISABLE) { 3569 if (speed == SPEED_10) { 3570 bmcr = 0; 3571 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3572 speed_duplex = FORCE_10M_HALF; 3573 } else if (speed == SPEED_100) { 3574 bmcr = BMCR_SPEED100; 3575 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3576 speed_duplex = FORCE_100M_HALF; 3577 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3578 bmcr = BMCR_SPEED1000; 3579 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3580 speed_duplex = NWAY_1000M_FULL; 3581 } else { 3582 ret = -EINVAL; 3583 goto out; 3584 } 3585 3586 if (duplex == DUPLEX_FULL) { 3587 bmcr |= BMCR_FULLDPLX; 3588 if (speed != SPEED_1000) 3589 speed_duplex++; 3590 } 3591 } else { 3592 if (speed == SPEED_10) { 3593 if (duplex == DUPLEX_FULL) { 3594 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3595 speed_duplex = NWAY_10M_FULL; 3596 } else { 3597 anar |= ADVERTISE_10HALF; 3598 speed_duplex = NWAY_10M_HALF; 3599 } 3600 } else if (speed == SPEED_100) { 3601 if (duplex == DUPLEX_FULL) { 3602 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3603 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3604 speed_duplex = NWAY_100M_FULL; 3605 } else { 3606 anar |= ADVERTISE_10HALF; 3607 anar |= ADVERTISE_100HALF; 3608 speed_duplex = NWAY_100M_HALF; 3609 } 3610 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 3611 if (duplex == DUPLEX_FULL) { 3612 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 3613 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 3614 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 3615 } else { 3616 anar |= ADVERTISE_10HALF; 3617 anar |= ADVERTISE_100HALF; 3618 gbcr |= ADVERTISE_1000HALF; 3619 } 3620 speed_duplex = NWAY_1000M_FULL; 3621 } else { 3622 ret = -EINVAL; 3623 goto out; 3624 } 3625 3626 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 3627 } 3628 3629 if (test_and_clear_bit(PHY_RESET, &tp->flags)) 3630 bmcr |= BMCR_RESET; 3631 3632 if (tp->mii.supports_gmii) 3633 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 3634 3635 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3636 r8152_mdio_write(tp, MII_BMCR, bmcr); 3637 3638 switch (tp->version) { 3639 case RTL_VER_08: 3640 case RTL_VER_09: 3641 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex), 3642 UPS_FLAGS_SPEED_MASK); 3643 break; 3644 3645 default: 3646 break; 3647 } 3648 3649 if (bmcr & BMCR_RESET) { 3650 int i; 3651 3652 for (i = 0; i < 50; i++) { 3653 msleep(20); 3654 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 3655 break; 3656 } 3657 } 3658 3659 out: 3660 return ret; 3661 } 3662 3663 static void rtl8152_up(struct r8152 *tp) 3664 { 3665 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3666 return; 3667 3668 r8152_aldps_en(tp, false); 3669 r8152b_exit_oob(tp); 3670 r8152_aldps_en(tp, true); 3671 } 3672 3673 static void rtl8152_down(struct r8152 *tp) 3674 { 3675 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3676 rtl_drop_queued_tx(tp); 3677 return; 3678 } 3679 3680 r8152_power_cut_en(tp, false); 3681 r8152_aldps_en(tp, false); 3682 r8152b_enter_oob(tp); 3683 r8152_aldps_en(tp, true); 3684 } 3685 3686 static void rtl8153_up(struct r8152 *tp) 3687 { 3688 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3689 return; 3690 3691 r8153_u1u2en(tp, false); 3692 r8153_u2p3en(tp, false); 3693 r8153_aldps_en(tp, false); 3694 r8153_first_init(tp); 3695 r8153_aldps_en(tp, true); 3696 3697 switch (tp->version) { 3698 case RTL_VER_03: 3699 case RTL_VER_04: 3700 break; 3701 case RTL_VER_05: 3702 case RTL_VER_06: 3703 default: 3704 r8153_u2p3en(tp, true); 3705 break; 3706 } 3707 3708 r8153_u1u2en(tp, true); 3709 } 3710 3711 static void rtl8153_down(struct r8152 *tp) 3712 { 3713 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3714 rtl_drop_queued_tx(tp); 3715 return; 3716 } 3717 3718 r8153_u1u2en(tp, false); 3719 r8153_u2p3en(tp, false); 3720 r8153_power_cut_en(tp, false); 3721 r8153_aldps_en(tp, false); 3722 r8153_enter_oob(tp); 3723 r8153_aldps_en(tp, true); 3724 } 3725 3726 static void rtl8153b_up(struct r8152 *tp) 3727 { 3728 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3729 return; 3730 3731 r8153b_u1u2en(tp, false); 3732 r8153_u2p3en(tp, false); 3733 r8153b_aldps_en(tp, false); 3734 3735 r8153_first_init(tp); 3736 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); 3737 3738 r8153b_aldps_en(tp, true); 3739 r8153_u2p3en(tp, true); 3740 r8153b_u1u2en(tp, true); 3741 } 3742 3743 static void rtl8153b_down(struct r8152 *tp) 3744 { 3745 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3746 rtl_drop_queued_tx(tp); 3747 return; 3748 } 3749 3750 r8153b_u1u2en(tp, false); 3751 r8153_u2p3en(tp, false); 3752 r8153b_power_cut_en(tp, false); 3753 r8153b_aldps_en(tp, false); 3754 r8153_enter_oob(tp); 3755 r8153b_aldps_en(tp, true); 3756 } 3757 3758 static bool rtl8152_in_nway(struct r8152 *tp) 3759 { 3760 u16 nway_state; 3761 3762 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); 3763 tp->ocp_base = 0x2000; 3764 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ 3765 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); 3766 3767 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ 3768 if (nway_state & 0xc000) 3769 return false; 3770 else 3771 return true; 3772 } 3773 3774 static bool rtl8153_in_nway(struct r8152 *tp) 3775 { 3776 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; 3777 3778 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) 3779 return false; 3780 else 3781 return true; 3782 } 3783 3784 static void set_carrier(struct r8152 *tp) 3785 { 3786 struct net_device *netdev = tp->netdev; 3787 struct napi_struct *napi = &tp->napi; 3788 u8 speed; 3789 3790 speed = rtl8152_get_speed(tp); 3791 3792 if (speed & LINK_STATUS) { 3793 if (!netif_carrier_ok(netdev)) { 3794 tp->rtl_ops.enable(tp); 3795 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 3796 netif_stop_queue(netdev); 3797 napi_disable(napi); 3798 netif_carrier_on(netdev); 3799 rtl_start_rx(tp); 3800 napi_enable(&tp->napi); 3801 netif_wake_queue(netdev); 3802 netif_info(tp, link, netdev, "carrier on\n"); 3803 } else if (netif_queue_stopped(netdev) && 3804 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) { 3805 netif_wake_queue(netdev); 3806 } 3807 } else { 3808 if (netif_carrier_ok(netdev)) { 3809 netif_carrier_off(netdev); 3810 napi_disable(napi); 3811 tp->rtl_ops.disable(tp); 3812 napi_enable(napi); 3813 netif_info(tp, link, netdev, "carrier off\n"); 3814 } 3815 } 3816 } 3817 3818 static void rtl_work_func_t(struct work_struct *work) 3819 { 3820 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 3821 3822 /* If the device is unplugged or !netif_running(), the workqueue 3823 * doesn't need to wake the device, and could return directly. 3824 */ 3825 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) 3826 return; 3827 3828 if (usb_autopm_get_interface(tp->intf) < 0) 3829 return; 3830 3831 if (!test_bit(WORK_ENABLE, &tp->flags)) 3832 goto out1; 3833 3834 if (!mutex_trylock(&tp->control)) { 3835 schedule_delayed_work(&tp->schedule, 0); 3836 goto out1; 3837 } 3838 3839 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) 3840 set_carrier(tp); 3841 3842 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) 3843 _rtl8152_set_rx_mode(tp->netdev); 3844 3845 /* don't schedule napi before linking */ 3846 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) && 3847 netif_carrier_ok(tp->netdev)) 3848 napi_schedule(&tp->napi); 3849 3850 mutex_unlock(&tp->control); 3851 3852 out1: 3853 usb_autopm_put_interface(tp->intf); 3854 } 3855 3856 static void rtl_hw_phy_work_func_t(struct work_struct *work) 3857 { 3858 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); 3859 3860 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3861 return; 3862 3863 if (usb_autopm_get_interface(tp->intf) < 0) 3864 return; 3865 3866 mutex_lock(&tp->control); 3867 3868 tp->rtl_ops.hw_phy_cfg(tp); 3869 3870 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex); 3871 3872 mutex_unlock(&tp->control); 3873 3874 usb_autopm_put_interface(tp->intf); 3875 } 3876 3877 #ifdef CONFIG_PM_SLEEP 3878 static int rtl_notifier(struct notifier_block *nb, unsigned long action, 3879 void *data) 3880 { 3881 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); 3882 3883 switch (action) { 3884 case PM_HIBERNATION_PREPARE: 3885 case PM_SUSPEND_PREPARE: 3886 usb_autopm_get_interface(tp->intf); 3887 break; 3888 3889 case PM_POST_HIBERNATION: 3890 case PM_POST_SUSPEND: 3891 usb_autopm_put_interface(tp->intf); 3892 break; 3893 3894 case PM_POST_RESTORE: 3895 case PM_RESTORE_PREPARE: 3896 default: 3897 break; 3898 } 3899 3900 return NOTIFY_DONE; 3901 } 3902 #endif 3903 3904 static int rtl8152_open(struct net_device *netdev) 3905 { 3906 struct r8152 *tp = netdev_priv(netdev); 3907 int res = 0; 3908 3909 res = alloc_all_mem(tp); 3910 if (res) 3911 goto out; 3912 3913 res = usb_autopm_get_interface(tp->intf); 3914 if (res < 0) 3915 goto out_free; 3916 3917 mutex_lock(&tp->control); 3918 3919 tp->rtl_ops.up(tp); 3920 3921 netif_carrier_off(netdev); 3922 netif_start_queue(netdev); 3923 set_bit(WORK_ENABLE, &tp->flags); 3924 3925 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3926 if (res) { 3927 if (res == -ENODEV) 3928 netif_device_detach(tp->netdev); 3929 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 3930 res); 3931 goto out_unlock; 3932 } 3933 napi_enable(&tp->napi); 3934 3935 mutex_unlock(&tp->control); 3936 3937 usb_autopm_put_interface(tp->intf); 3938 #ifdef CONFIG_PM_SLEEP 3939 tp->pm_notifier.notifier_call = rtl_notifier; 3940 register_pm_notifier(&tp->pm_notifier); 3941 #endif 3942 return 0; 3943 3944 out_unlock: 3945 mutex_unlock(&tp->control); 3946 usb_autopm_put_interface(tp->intf); 3947 out_free: 3948 free_all_mem(tp); 3949 out: 3950 return res; 3951 } 3952 3953 static int rtl8152_close(struct net_device *netdev) 3954 { 3955 struct r8152 *tp = netdev_priv(netdev); 3956 int res = 0; 3957 3958 #ifdef CONFIG_PM_SLEEP 3959 unregister_pm_notifier(&tp->pm_notifier); 3960 #endif 3961 napi_disable(&tp->napi); 3962 clear_bit(WORK_ENABLE, &tp->flags); 3963 usb_kill_urb(tp->intr_urb); 3964 cancel_delayed_work_sync(&tp->schedule); 3965 netif_stop_queue(netdev); 3966 3967 res = usb_autopm_get_interface(tp->intf); 3968 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { 3969 rtl_drop_queued_tx(tp); 3970 rtl_stop_rx(tp); 3971 } else { 3972 mutex_lock(&tp->control); 3973 3974 tp->rtl_ops.down(tp); 3975 3976 mutex_unlock(&tp->control); 3977 3978 usb_autopm_put_interface(tp->intf); 3979 } 3980 3981 free_all_mem(tp); 3982 3983 return res; 3984 } 3985 3986 static void rtl_tally_reset(struct r8152 *tp) 3987 { 3988 u32 ocp_data; 3989 3990 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 3991 ocp_data |= TALLY_RESET; 3992 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 3993 } 3994 3995 static void r8152b_init(struct r8152 *tp) 3996 { 3997 u32 ocp_data; 3998 u16 data; 3999 4000 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4001 return; 4002 4003 data = r8152_mdio_read(tp, MII_BMCR); 4004 if (data & BMCR_PDOWN) { 4005 data &= ~BMCR_PDOWN; 4006 r8152_mdio_write(tp, MII_BMCR, data); 4007 } 4008 4009 r8152_aldps_en(tp, false); 4010 4011 if (tp->version == RTL_VER_01) { 4012 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4013 ocp_data &= ~LED_MODE_MASK; 4014 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4015 } 4016 4017 r8152_power_cut_en(tp, false); 4018 4019 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 4020 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 4021 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 4022 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 4023 ocp_data &= ~MCU_CLK_RATIO_MASK; 4024 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 4025 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 4026 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 4027 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 4028 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 4029 4030 rtl_tally_reset(tp); 4031 4032 /* enable rx aggregation */ 4033 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4034 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4035 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4036 } 4037 4038 static void r8153_init(struct r8152 *tp) 4039 { 4040 u32 ocp_data; 4041 u16 data; 4042 int i; 4043 4044 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4045 return; 4046 4047 r8153_u1u2en(tp, false); 4048 4049 for (i = 0; i < 500; i++) { 4050 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4051 AUTOLOAD_DONE) 4052 break; 4053 msleep(20); 4054 } 4055 4056 data = r8153_phy_status(tp, 0); 4057 4058 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 4059 tp->version == RTL_VER_05) 4060 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 4061 4062 data = r8152_mdio_read(tp, MII_BMCR); 4063 if (data & BMCR_PDOWN) { 4064 data &= ~BMCR_PDOWN; 4065 r8152_mdio_write(tp, MII_BMCR, data); 4066 } 4067 4068 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4069 4070 r8153_u2p3en(tp, false); 4071 4072 if (tp->version == RTL_VER_04) { 4073 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 4074 ocp_data &= ~pwd_dn_scale_mask; 4075 ocp_data |= pwd_dn_scale(96); 4076 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 4077 4078 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 4079 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 4080 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 4081 } else if (tp->version == RTL_VER_05) { 4082 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 4083 ocp_data &= ~ECM_ALDPS; 4084 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 4085 4086 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4087 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4088 ocp_data &= ~DYNAMIC_BURST; 4089 else 4090 ocp_data |= DYNAMIC_BURST; 4091 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4092 } else if (tp->version == RTL_VER_06) { 4093 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4094 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4095 ocp_data &= ~DYNAMIC_BURST; 4096 else 4097 ocp_data |= DYNAMIC_BURST; 4098 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4099 } 4100 4101 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 4102 ocp_data |= EP4_FULL_FC; 4103 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 4104 4105 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 4106 ocp_data &= ~TIMER11_EN; 4107 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 4108 4109 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4110 ocp_data &= ~LED_MODE_MASK; 4111 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4112 4113 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 4114 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) 4115 ocp_data |= LPM_TIMER_500MS; 4116 else 4117 ocp_data |= LPM_TIMER_500US; 4118 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 4119 4120 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 4121 ocp_data &= ~SEN_VAL_MASK; 4122 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 4123 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 4124 4125 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 4126 4127 r8153_power_cut_en(tp, false); 4128 r8153_u1u2en(tp, true); 4129 r8153_mac_clk_spd(tp, false); 4130 usb_enable_lpm(tp->udev); 4131 4132 /* rx aggregation */ 4133 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4134 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4135 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4136 4137 rtl_tally_reset(tp); 4138 4139 switch (tp->udev->speed) { 4140 case USB_SPEED_SUPER: 4141 case USB_SPEED_SUPER_PLUS: 4142 tp->coalesce = COALESCE_SUPER; 4143 break; 4144 case USB_SPEED_HIGH: 4145 tp->coalesce = COALESCE_HIGH; 4146 break; 4147 default: 4148 tp->coalesce = COALESCE_SLOW; 4149 break; 4150 } 4151 } 4152 4153 static void r8153b_init(struct r8152 *tp) 4154 { 4155 u32 ocp_data; 4156 u16 data; 4157 int i; 4158 4159 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4160 return; 4161 4162 r8153b_u1u2en(tp, false); 4163 4164 for (i = 0; i < 500; i++) { 4165 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4166 AUTOLOAD_DONE) 4167 break; 4168 msleep(20); 4169 } 4170 4171 data = r8153_phy_status(tp, 0); 4172 4173 data = r8152_mdio_read(tp, MII_BMCR); 4174 if (data & BMCR_PDOWN) { 4175 data &= ~BMCR_PDOWN; 4176 r8152_mdio_write(tp, MII_BMCR, data); 4177 } 4178 4179 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4180 4181 r8153_u2p3en(tp, false); 4182 4183 /* MSC timer = 0xfff * 8ms = 32760 ms */ 4184 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 4185 4186 /* U1/U2/L1 idle timer. 500 us */ 4187 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 4188 4189 r8153b_power_cut_en(tp, false); 4190 r8153b_ups_en(tp, false); 4191 r8153b_queue_wake(tp, false); 4192 rtl_runtime_suspend_enable(tp, false); 4193 r8153b_u1u2en(tp, true); 4194 usb_enable_lpm(tp->udev); 4195 4196 /* MAC clock speed down */ 4197 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); 4198 ocp_data |= MAC_CLK_SPDWN_EN; 4199 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); 4200 4201 set_bit(GREEN_ETHERNET, &tp->flags); 4202 4203 /* rx aggregation */ 4204 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4205 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4206 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4207 4208 rtl_tally_reset(tp); 4209 4210 tp->coalesce = 15000; /* 15 us */ 4211 } 4212 4213 static int rtl8152_pre_reset(struct usb_interface *intf) 4214 { 4215 struct r8152 *tp = usb_get_intfdata(intf); 4216 struct net_device *netdev; 4217 4218 if (!tp) 4219 return 0; 4220 4221 netdev = tp->netdev; 4222 if (!netif_running(netdev)) 4223 return 0; 4224 4225 netif_stop_queue(netdev); 4226 napi_disable(&tp->napi); 4227 clear_bit(WORK_ENABLE, &tp->flags); 4228 usb_kill_urb(tp->intr_urb); 4229 cancel_delayed_work_sync(&tp->schedule); 4230 if (netif_carrier_ok(netdev)) { 4231 mutex_lock(&tp->control); 4232 tp->rtl_ops.disable(tp); 4233 mutex_unlock(&tp->control); 4234 } 4235 4236 return 0; 4237 } 4238 4239 static int rtl8152_post_reset(struct usb_interface *intf) 4240 { 4241 struct r8152 *tp = usb_get_intfdata(intf); 4242 struct net_device *netdev; 4243 4244 if (!tp) 4245 return 0; 4246 4247 netdev = tp->netdev; 4248 if (!netif_running(netdev)) 4249 return 0; 4250 4251 set_bit(WORK_ENABLE, &tp->flags); 4252 if (netif_carrier_ok(netdev)) { 4253 mutex_lock(&tp->control); 4254 tp->rtl_ops.enable(tp); 4255 rtl_start_rx(tp); 4256 rtl8152_set_rx_mode(netdev); 4257 mutex_unlock(&tp->control); 4258 } 4259 4260 napi_enable(&tp->napi); 4261 netif_wake_queue(netdev); 4262 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 4263 4264 if (!list_empty(&tp->rx_done)) 4265 napi_schedule(&tp->napi); 4266 4267 return 0; 4268 } 4269 4270 static bool delay_autosuspend(struct r8152 *tp) 4271 { 4272 bool sw_linking = !!netif_carrier_ok(tp->netdev); 4273 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); 4274 4275 /* This means a linking change occurs and the driver doesn't detect it, 4276 * yet. If the driver has disabled tx/rx and hw is linking on, the 4277 * device wouldn't wake up by receiving any packet. 4278 */ 4279 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) 4280 return true; 4281 4282 /* If the linking down is occurred by nway, the device may miss the 4283 * linking change event. And it wouldn't wake when linking on. 4284 */ 4285 if (!sw_linking && tp->rtl_ops.in_nway(tp)) 4286 return true; 4287 else if (!skb_queue_empty(&tp->tx_queue)) 4288 return true; 4289 else 4290 return false; 4291 } 4292 4293 static int rtl8152_runtime_resume(struct r8152 *tp) 4294 { 4295 struct net_device *netdev = tp->netdev; 4296 4297 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4298 struct napi_struct *napi = &tp->napi; 4299 4300 tp->rtl_ops.autosuspend_en(tp, false); 4301 napi_disable(napi); 4302 set_bit(WORK_ENABLE, &tp->flags); 4303 4304 if (netif_carrier_ok(netdev)) { 4305 if (rtl8152_get_speed(tp) & LINK_STATUS) { 4306 rtl_start_rx(tp); 4307 } else { 4308 netif_carrier_off(netdev); 4309 tp->rtl_ops.disable(tp); 4310 netif_info(tp, link, netdev, "linking down\n"); 4311 } 4312 } 4313 4314 napi_enable(napi); 4315 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4316 smp_mb__after_atomic(); 4317 4318 if (!list_empty(&tp->rx_done)) 4319 napi_schedule(&tp->napi); 4320 4321 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4322 } else { 4323 if (netdev->flags & IFF_UP) 4324 tp->rtl_ops.autosuspend_en(tp, false); 4325 4326 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4327 } 4328 4329 return 0; 4330 } 4331 4332 static int rtl8152_system_resume(struct r8152 *tp) 4333 { 4334 struct net_device *netdev = tp->netdev; 4335 4336 netif_device_attach(netdev); 4337 4338 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4339 tp->rtl_ops.up(tp); 4340 netif_carrier_off(netdev); 4341 set_bit(WORK_ENABLE, &tp->flags); 4342 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4343 } 4344 4345 return 0; 4346 } 4347 4348 static int rtl8152_runtime_suspend(struct r8152 *tp) 4349 { 4350 struct net_device *netdev = tp->netdev; 4351 int ret = 0; 4352 4353 set_bit(SELECTIVE_SUSPEND, &tp->flags); 4354 smp_mb__after_atomic(); 4355 4356 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4357 u32 rcr = 0; 4358 4359 if (netif_carrier_ok(netdev)) { 4360 u32 ocp_data; 4361 4362 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 4363 ocp_data = rcr & ~RCR_ACPT_ALL; 4364 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 4365 rxdy_gated_en(tp, true); 4366 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 4367 PLA_OOB_CTRL); 4368 if (!(ocp_data & RXFIFO_EMPTY)) { 4369 rxdy_gated_en(tp, false); 4370 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4371 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4372 smp_mb__after_atomic(); 4373 ret = -EBUSY; 4374 goto out1; 4375 } 4376 } 4377 4378 clear_bit(WORK_ENABLE, &tp->flags); 4379 usb_kill_urb(tp->intr_urb); 4380 4381 tp->rtl_ops.autosuspend_en(tp, true); 4382 4383 if (netif_carrier_ok(netdev)) { 4384 struct napi_struct *napi = &tp->napi; 4385 4386 napi_disable(napi); 4387 rtl_stop_rx(tp); 4388 rxdy_gated_en(tp, false); 4389 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4390 napi_enable(napi); 4391 } 4392 4393 if (delay_autosuspend(tp)) { 4394 rtl8152_runtime_resume(tp); 4395 ret = -EBUSY; 4396 } 4397 } 4398 4399 out1: 4400 return ret; 4401 } 4402 4403 static int rtl8152_system_suspend(struct r8152 *tp) 4404 { 4405 struct net_device *netdev = tp->netdev; 4406 int ret = 0; 4407 4408 netif_device_detach(netdev); 4409 4410 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4411 struct napi_struct *napi = &tp->napi; 4412 4413 clear_bit(WORK_ENABLE, &tp->flags); 4414 usb_kill_urb(tp->intr_urb); 4415 napi_disable(napi); 4416 cancel_delayed_work_sync(&tp->schedule); 4417 tp->rtl_ops.down(tp); 4418 napi_enable(napi); 4419 } 4420 4421 return ret; 4422 } 4423 4424 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 4425 { 4426 struct r8152 *tp = usb_get_intfdata(intf); 4427 int ret; 4428 4429 mutex_lock(&tp->control); 4430 4431 if (PMSG_IS_AUTO(message)) 4432 ret = rtl8152_runtime_suspend(tp); 4433 else 4434 ret = rtl8152_system_suspend(tp); 4435 4436 mutex_unlock(&tp->control); 4437 4438 return ret; 4439 } 4440 4441 static int rtl8152_resume(struct usb_interface *intf) 4442 { 4443 struct r8152 *tp = usb_get_intfdata(intf); 4444 int ret; 4445 4446 mutex_lock(&tp->control); 4447 4448 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) 4449 ret = rtl8152_runtime_resume(tp); 4450 else 4451 ret = rtl8152_system_resume(tp); 4452 4453 mutex_unlock(&tp->control); 4454 4455 return ret; 4456 } 4457 4458 static int rtl8152_reset_resume(struct usb_interface *intf) 4459 { 4460 struct r8152 *tp = usb_get_intfdata(intf); 4461 4462 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4463 mutex_lock(&tp->control); 4464 tp->rtl_ops.init(tp); 4465 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 4466 mutex_unlock(&tp->control); 4467 return rtl8152_resume(intf); 4468 } 4469 4470 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4471 { 4472 struct r8152 *tp = netdev_priv(dev); 4473 4474 if (usb_autopm_get_interface(tp->intf) < 0) 4475 return; 4476 4477 if (!rtl_can_wakeup(tp)) { 4478 wol->supported = 0; 4479 wol->wolopts = 0; 4480 } else { 4481 mutex_lock(&tp->control); 4482 wol->supported = WAKE_ANY; 4483 wol->wolopts = __rtl_get_wol(tp); 4484 mutex_unlock(&tp->control); 4485 } 4486 4487 usb_autopm_put_interface(tp->intf); 4488 } 4489 4490 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4491 { 4492 struct r8152 *tp = netdev_priv(dev); 4493 int ret; 4494 4495 if (!rtl_can_wakeup(tp)) 4496 return -EOPNOTSUPP; 4497 4498 ret = usb_autopm_get_interface(tp->intf); 4499 if (ret < 0) 4500 goto out_set_wol; 4501 4502 mutex_lock(&tp->control); 4503 4504 __rtl_set_wol(tp, wol->wolopts); 4505 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 4506 4507 mutex_unlock(&tp->control); 4508 4509 usb_autopm_put_interface(tp->intf); 4510 4511 out_set_wol: 4512 return ret; 4513 } 4514 4515 static u32 rtl8152_get_msglevel(struct net_device *dev) 4516 { 4517 struct r8152 *tp = netdev_priv(dev); 4518 4519 return tp->msg_enable; 4520 } 4521 4522 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 4523 { 4524 struct r8152 *tp = netdev_priv(dev); 4525 4526 tp->msg_enable = value; 4527 } 4528 4529 static void rtl8152_get_drvinfo(struct net_device *netdev, 4530 struct ethtool_drvinfo *info) 4531 { 4532 struct r8152 *tp = netdev_priv(netdev); 4533 4534 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 4535 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 4536 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 4537 } 4538 4539 static 4540 int rtl8152_get_link_ksettings(struct net_device *netdev, 4541 struct ethtool_link_ksettings *cmd) 4542 { 4543 struct r8152 *tp = netdev_priv(netdev); 4544 int ret; 4545 4546 if (!tp->mii.mdio_read) 4547 return -EOPNOTSUPP; 4548 4549 ret = usb_autopm_get_interface(tp->intf); 4550 if (ret < 0) 4551 goto out; 4552 4553 mutex_lock(&tp->control); 4554 4555 mii_ethtool_get_link_ksettings(&tp->mii, cmd); 4556 4557 mutex_unlock(&tp->control); 4558 4559 usb_autopm_put_interface(tp->intf); 4560 4561 out: 4562 return ret; 4563 } 4564 4565 static int rtl8152_set_link_ksettings(struct net_device *dev, 4566 const struct ethtool_link_ksettings *cmd) 4567 { 4568 struct r8152 *tp = netdev_priv(dev); 4569 int ret; 4570 4571 ret = usb_autopm_get_interface(tp->intf); 4572 if (ret < 0) 4573 goto out; 4574 4575 mutex_lock(&tp->control); 4576 4577 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, 4578 cmd->base.duplex); 4579 if (!ret) { 4580 tp->autoneg = cmd->base.autoneg; 4581 tp->speed = cmd->base.speed; 4582 tp->duplex = cmd->base.duplex; 4583 } 4584 4585 mutex_unlock(&tp->control); 4586 4587 usb_autopm_put_interface(tp->intf); 4588 4589 out: 4590 return ret; 4591 } 4592 4593 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 4594 "tx_packets", 4595 "rx_packets", 4596 "tx_errors", 4597 "rx_errors", 4598 "rx_missed", 4599 "align_errors", 4600 "tx_single_collisions", 4601 "tx_multi_collisions", 4602 "rx_unicast", 4603 "rx_broadcast", 4604 "rx_multicast", 4605 "tx_aborted", 4606 "tx_underrun", 4607 }; 4608 4609 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 4610 { 4611 switch (sset) { 4612 case ETH_SS_STATS: 4613 return ARRAY_SIZE(rtl8152_gstrings); 4614 default: 4615 return -EOPNOTSUPP; 4616 } 4617 } 4618 4619 static void rtl8152_get_ethtool_stats(struct net_device *dev, 4620 struct ethtool_stats *stats, u64 *data) 4621 { 4622 struct r8152 *tp = netdev_priv(dev); 4623 struct tally_counter tally; 4624 4625 if (usb_autopm_get_interface(tp->intf) < 0) 4626 return; 4627 4628 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 4629 4630 usb_autopm_put_interface(tp->intf); 4631 4632 data[0] = le64_to_cpu(tally.tx_packets); 4633 data[1] = le64_to_cpu(tally.rx_packets); 4634 data[2] = le64_to_cpu(tally.tx_errors); 4635 data[3] = le32_to_cpu(tally.rx_errors); 4636 data[4] = le16_to_cpu(tally.rx_missed); 4637 data[5] = le16_to_cpu(tally.align_errors); 4638 data[6] = le32_to_cpu(tally.tx_one_collision); 4639 data[7] = le32_to_cpu(tally.tx_multi_collision); 4640 data[8] = le64_to_cpu(tally.rx_unicast); 4641 data[9] = le64_to_cpu(tally.rx_broadcast); 4642 data[10] = le32_to_cpu(tally.rx_multicast); 4643 data[11] = le16_to_cpu(tally.tx_aborted); 4644 data[12] = le16_to_cpu(tally.tx_underrun); 4645 } 4646 4647 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4648 { 4649 switch (stringset) { 4650 case ETH_SS_STATS: 4651 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 4652 break; 4653 } 4654 } 4655 4656 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 4657 { 4658 u32 ocp_data, lp, adv, supported = 0; 4659 u16 val; 4660 4661 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 4662 supported = mmd_eee_cap_to_ethtool_sup_t(val); 4663 4664 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 4665 adv = mmd_eee_adv_to_ethtool_adv_t(val); 4666 4667 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 4668 lp = mmd_eee_adv_to_ethtool_adv_t(val); 4669 4670 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 4671 ocp_data &= EEE_RX_EN | EEE_TX_EN; 4672 4673 eee->eee_enabled = !!ocp_data; 4674 eee->eee_active = !!(supported & adv & lp); 4675 eee->supported = supported; 4676 eee->advertised = adv; 4677 eee->lp_advertised = lp; 4678 4679 return 0; 4680 } 4681 4682 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4683 { 4684 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4685 4686 r8152_eee_en(tp, eee->eee_enabled); 4687 4688 if (!eee->eee_enabled) 4689 val = 0; 4690 4691 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); 4692 4693 return 0; 4694 } 4695 4696 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 4697 { 4698 u32 ocp_data, lp, adv, supported = 0; 4699 u16 val; 4700 4701 val = ocp_reg_read(tp, OCP_EEE_ABLE); 4702 supported = mmd_eee_cap_to_ethtool_sup_t(val); 4703 4704 val = ocp_reg_read(tp, OCP_EEE_ADV); 4705 adv = mmd_eee_adv_to_ethtool_adv_t(val); 4706 4707 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 4708 lp = mmd_eee_adv_to_ethtool_adv_t(val); 4709 4710 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 4711 ocp_data &= EEE_RX_EN | EEE_TX_EN; 4712 4713 eee->eee_enabled = !!ocp_data; 4714 eee->eee_active = !!(supported & adv & lp); 4715 eee->supported = supported; 4716 eee->advertised = adv; 4717 eee->lp_advertised = lp; 4718 4719 return 0; 4720 } 4721 4722 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4723 { 4724 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4725 4726 r8153_eee_en(tp, eee->eee_enabled); 4727 4728 if (!eee->eee_enabled) 4729 val = 0; 4730 4731 ocp_reg_write(tp, OCP_EEE_ADV, val); 4732 4733 return 0; 4734 } 4735 4736 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 4737 { 4738 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 4739 4740 r8153b_eee_en(tp, eee->eee_enabled); 4741 4742 if (!eee->eee_enabled) 4743 val = 0; 4744 4745 ocp_reg_write(tp, OCP_EEE_ADV, val); 4746 4747 return 0; 4748 } 4749 4750 static int 4751 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) 4752 { 4753 struct r8152 *tp = netdev_priv(net); 4754 int ret; 4755 4756 ret = usb_autopm_get_interface(tp->intf); 4757 if (ret < 0) 4758 goto out; 4759 4760 mutex_lock(&tp->control); 4761 4762 ret = tp->rtl_ops.eee_get(tp, edata); 4763 4764 mutex_unlock(&tp->control); 4765 4766 usb_autopm_put_interface(tp->intf); 4767 4768 out: 4769 return ret; 4770 } 4771 4772 static int 4773 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) 4774 { 4775 struct r8152 *tp = netdev_priv(net); 4776 int ret; 4777 4778 ret = usb_autopm_get_interface(tp->intf); 4779 if (ret < 0) 4780 goto out; 4781 4782 mutex_lock(&tp->control); 4783 4784 ret = tp->rtl_ops.eee_set(tp, edata); 4785 if (!ret) 4786 ret = mii_nway_restart(&tp->mii); 4787 4788 mutex_unlock(&tp->control); 4789 4790 usb_autopm_put_interface(tp->intf); 4791 4792 out: 4793 return ret; 4794 } 4795 4796 static int rtl8152_nway_reset(struct net_device *dev) 4797 { 4798 struct r8152 *tp = netdev_priv(dev); 4799 int ret; 4800 4801 ret = usb_autopm_get_interface(tp->intf); 4802 if (ret < 0) 4803 goto out; 4804 4805 mutex_lock(&tp->control); 4806 4807 ret = mii_nway_restart(&tp->mii); 4808 4809 mutex_unlock(&tp->control); 4810 4811 usb_autopm_put_interface(tp->intf); 4812 4813 out: 4814 return ret; 4815 } 4816 4817 static int rtl8152_get_coalesce(struct net_device *netdev, 4818 struct ethtool_coalesce *coalesce) 4819 { 4820 struct r8152 *tp = netdev_priv(netdev); 4821 4822 switch (tp->version) { 4823 case RTL_VER_01: 4824 case RTL_VER_02: 4825 case RTL_VER_07: 4826 return -EOPNOTSUPP; 4827 default: 4828 break; 4829 } 4830 4831 coalesce->rx_coalesce_usecs = tp->coalesce; 4832 4833 return 0; 4834 } 4835 4836 static int rtl8152_set_coalesce(struct net_device *netdev, 4837 struct ethtool_coalesce *coalesce) 4838 { 4839 struct r8152 *tp = netdev_priv(netdev); 4840 int ret; 4841 4842 switch (tp->version) { 4843 case RTL_VER_01: 4844 case RTL_VER_02: 4845 case RTL_VER_07: 4846 return -EOPNOTSUPP; 4847 default: 4848 break; 4849 } 4850 4851 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) 4852 return -EINVAL; 4853 4854 ret = usb_autopm_get_interface(tp->intf); 4855 if (ret < 0) 4856 return ret; 4857 4858 mutex_lock(&tp->control); 4859 4860 if (tp->coalesce != coalesce->rx_coalesce_usecs) { 4861 tp->coalesce = coalesce->rx_coalesce_usecs; 4862 4863 if (netif_running(tp->netdev) && netif_carrier_ok(netdev)) 4864 r8153_set_rx_early_timeout(tp); 4865 } 4866 4867 mutex_unlock(&tp->control); 4868 4869 usb_autopm_put_interface(tp->intf); 4870 4871 return ret; 4872 } 4873 4874 static const struct ethtool_ops ops = { 4875 .get_drvinfo = rtl8152_get_drvinfo, 4876 .get_link = ethtool_op_get_link, 4877 .nway_reset = rtl8152_nway_reset, 4878 .get_msglevel = rtl8152_get_msglevel, 4879 .set_msglevel = rtl8152_set_msglevel, 4880 .get_wol = rtl8152_get_wol, 4881 .set_wol = rtl8152_set_wol, 4882 .get_strings = rtl8152_get_strings, 4883 .get_sset_count = rtl8152_get_sset_count, 4884 .get_ethtool_stats = rtl8152_get_ethtool_stats, 4885 .get_coalesce = rtl8152_get_coalesce, 4886 .set_coalesce = rtl8152_set_coalesce, 4887 .get_eee = rtl_ethtool_get_eee, 4888 .set_eee = rtl_ethtool_set_eee, 4889 .get_link_ksettings = rtl8152_get_link_ksettings, 4890 .set_link_ksettings = rtl8152_set_link_ksettings, 4891 }; 4892 4893 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 4894 { 4895 struct r8152 *tp = netdev_priv(netdev); 4896 struct mii_ioctl_data *data = if_mii(rq); 4897 int res; 4898 4899 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4900 return -ENODEV; 4901 4902 res = usb_autopm_get_interface(tp->intf); 4903 if (res < 0) 4904 goto out; 4905 4906 switch (cmd) { 4907 case SIOCGMIIPHY: 4908 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 4909 break; 4910 4911 case SIOCGMIIREG: 4912 mutex_lock(&tp->control); 4913 data->val_out = r8152_mdio_read(tp, data->reg_num); 4914 mutex_unlock(&tp->control); 4915 break; 4916 4917 case SIOCSMIIREG: 4918 if (!capable(CAP_NET_ADMIN)) { 4919 res = -EPERM; 4920 break; 4921 } 4922 mutex_lock(&tp->control); 4923 r8152_mdio_write(tp, data->reg_num, data->val_in); 4924 mutex_unlock(&tp->control); 4925 break; 4926 4927 default: 4928 res = -EOPNOTSUPP; 4929 } 4930 4931 usb_autopm_put_interface(tp->intf); 4932 4933 out: 4934 return res; 4935 } 4936 4937 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 4938 { 4939 struct r8152 *tp = netdev_priv(dev); 4940 int ret; 4941 4942 switch (tp->version) { 4943 case RTL_VER_01: 4944 case RTL_VER_02: 4945 case RTL_VER_07: 4946 dev->mtu = new_mtu; 4947 return 0; 4948 default: 4949 break; 4950 } 4951 4952 ret = usb_autopm_get_interface(tp->intf); 4953 if (ret < 0) 4954 return ret; 4955 4956 mutex_lock(&tp->control); 4957 4958 dev->mtu = new_mtu; 4959 4960 if (netif_running(dev)) { 4961 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 4962 4963 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms); 4964 4965 if (netif_carrier_ok(dev)) 4966 r8153_set_rx_early_size(tp); 4967 } 4968 4969 mutex_unlock(&tp->control); 4970 4971 usb_autopm_put_interface(tp->intf); 4972 4973 return ret; 4974 } 4975 4976 static const struct net_device_ops rtl8152_netdev_ops = { 4977 .ndo_open = rtl8152_open, 4978 .ndo_stop = rtl8152_close, 4979 .ndo_do_ioctl = rtl8152_ioctl, 4980 .ndo_start_xmit = rtl8152_start_xmit, 4981 .ndo_tx_timeout = rtl8152_tx_timeout, 4982 .ndo_set_features = rtl8152_set_features, 4983 .ndo_set_rx_mode = rtl8152_set_rx_mode, 4984 .ndo_set_mac_address = rtl8152_set_mac_address, 4985 .ndo_change_mtu = rtl8152_change_mtu, 4986 .ndo_validate_addr = eth_validate_addr, 4987 .ndo_features_check = rtl8152_features_check, 4988 }; 4989 4990 static void rtl8152_unload(struct r8152 *tp) 4991 { 4992 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4993 return; 4994 4995 if (tp->version != RTL_VER_01) 4996 r8152_power_cut_en(tp, true); 4997 } 4998 4999 static void rtl8153_unload(struct r8152 *tp) 5000 { 5001 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5002 return; 5003 5004 r8153_power_cut_en(tp, false); 5005 } 5006 5007 static void rtl8153b_unload(struct r8152 *tp) 5008 { 5009 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5010 return; 5011 5012 r8153b_power_cut_en(tp, false); 5013 } 5014 5015 static int rtl_ops_init(struct r8152 *tp) 5016 { 5017 struct rtl_ops *ops = &tp->rtl_ops; 5018 int ret = 0; 5019 5020 switch (tp->version) { 5021 case RTL_VER_01: 5022 case RTL_VER_02: 5023 case RTL_VER_07: 5024 ops->init = r8152b_init; 5025 ops->enable = rtl8152_enable; 5026 ops->disable = rtl8152_disable; 5027 ops->up = rtl8152_up; 5028 ops->down = rtl8152_down; 5029 ops->unload = rtl8152_unload; 5030 ops->eee_get = r8152_get_eee; 5031 ops->eee_set = r8152_set_eee; 5032 ops->in_nway = rtl8152_in_nway; 5033 ops->hw_phy_cfg = r8152b_hw_phy_cfg; 5034 ops->autosuspend_en = rtl_runtime_suspend_enable; 5035 break; 5036 5037 case RTL_VER_03: 5038 case RTL_VER_04: 5039 case RTL_VER_05: 5040 case RTL_VER_06: 5041 ops->init = r8153_init; 5042 ops->enable = rtl8153_enable; 5043 ops->disable = rtl8153_disable; 5044 ops->up = rtl8153_up; 5045 ops->down = rtl8153_down; 5046 ops->unload = rtl8153_unload; 5047 ops->eee_get = r8153_get_eee; 5048 ops->eee_set = r8153_set_eee; 5049 ops->in_nway = rtl8153_in_nway; 5050 ops->hw_phy_cfg = r8153_hw_phy_cfg; 5051 ops->autosuspend_en = rtl8153_runtime_enable; 5052 break; 5053 5054 case RTL_VER_08: 5055 case RTL_VER_09: 5056 ops->init = r8153b_init; 5057 ops->enable = rtl8153_enable; 5058 ops->disable = rtl8153b_disable; 5059 ops->up = rtl8153b_up; 5060 ops->down = rtl8153b_down; 5061 ops->unload = rtl8153b_unload; 5062 ops->eee_get = r8153_get_eee; 5063 ops->eee_set = r8153b_set_eee; 5064 ops->in_nway = rtl8153_in_nway; 5065 ops->hw_phy_cfg = r8153b_hw_phy_cfg; 5066 ops->autosuspend_en = rtl8153b_runtime_enable; 5067 break; 5068 5069 default: 5070 ret = -ENODEV; 5071 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 5072 break; 5073 } 5074 5075 return ret; 5076 } 5077 5078 static u8 rtl_get_version(struct usb_interface *intf) 5079 { 5080 struct usb_device *udev = interface_to_usbdev(intf); 5081 u32 ocp_data = 0; 5082 __le32 *tmp; 5083 u8 version; 5084 int ret; 5085 5086 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); 5087 if (!tmp) 5088 return 0; 5089 5090 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 5091 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 5092 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500); 5093 if (ret > 0) 5094 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK; 5095 5096 kfree(tmp); 5097 5098 switch (ocp_data) { 5099 case 0x4c00: 5100 version = RTL_VER_01; 5101 break; 5102 case 0x4c10: 5103 version = RTL_VER_02; 5104 break; 5105 case 0x5c00: 5106 version = RTL_VER_03; 5107 break; 5108 case 0x5c10: 5109 version = RTL_VER_04; 5110 break; 5111 case 0x5c20: 5112 version = RTL_VER_05; 5113 break; 5114 case 0x5c30: 5115 version = RTL_VER_06; 5116 break; 5117 case 0x4800: 5118 version = RTL_VER_07; 5119 break; 5120 case 0x6000: 5121 version = RTL_VER_08; 5122 break; 5123 case 0x6010: 5124 version = RTL_VER_09; 5125 break; 5126 default: 5127 version = RTL_VER_UNKNOWN; 5128 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); 5129 break; 5130 } 5131 5132 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); 5133 5134 return version; 5135 } 5136 5137 static int rtl8152_probe(struct usb_interface *intf, 5138 const struct usb_device_id *id) 5139 { 5140 struct usb_device *udev = interface_to_usbdev(intf); 5141 u8 version = rtl_get_version(intf); 5142 struct r8152 *tp; 5143 struct net_device *netdev; 5144 int ret; 5145 5146 if (version == RTL_VER_UNKNOWN) 5147 return -ENODEV; 5148 5149 if (udev->actconfig->desc.bConfigurationValue != 1) { 5150 usb_driver_set_configuration(udev, 1); 5151 return -ENODEV; 5152 } 5153 5154 usb_reset_device(udev); 5155 netdev = alloc_etherdev(sizeof(struct r8152)); 5156 if (!netdev) { 5157 dev_err(&intf->dev, "Out of memory\n"); 5158 return -ENOMEM; 5159 } 5160 5161 SET_NETDEV_DEV(netdev, &intf->dev); 5162 tp = netdev_priv(netdev); 5163 tp->msg_enable = 0x7FFF; 5164 5165 tp->udev = udev; 5166 tp->netdev = netdev; 5167 tp->intf = intf; 5168 tp->version = version; 5169 5170 switch (version) { 5171 case RTL_VER_01: 5172 case RTL_VER_02: 5173 case RTL_VER_07: 5174 tp->mii.supports_gmii = 0; 5175 break; 5176 default: 5177 tp->mii.supports_gmii = 1; 5178 break; 5179 } 5180 5181 ret = rtl_ops_init(tp); 5182 if (ret) 5183 goto out; 5184 5185 mutex_init(&tp->control); 5186 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 5187 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); 5188 5189 netdev->netdev_ops = &rtl8152_netdev_ops; 5190 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 5191 5192 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5193 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 5194 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 5195 NETIF_F_HW_VLAN_CTAG_TX; 5196 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5197 NETIF_F_TSO | NETIF_F_FRAGLIST | 5198 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 5199 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; 5200 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 5201 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 5202 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 5203 5204 if (tp->version == RTL_VER_01) { 5205 netdev->features &= ~NETIF_F_RXCSUM; 5206 netdev->hw_features &= ~NETIF_F_RXCSUM; 5207 } 5208 5209 netdev->ethtool_ops = &ops; 5210 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 5211 5212 /* MTU range: 68 - 1500 or 9194 */ 5213 netdev->min_mtu = ETH_MIN_MTU; 5214 switch (tp->version) { 5215 case RTL_VER_01: 5216 case RTL_VER_02: 5217 netdev->max_mtu = ETH_DATA_LEN; 5218 break; 5219 default: 5220 netdev->max_mtu = RTL8153_MAX_MTU; 5221 break; 5222 } 5223 5224 tp->mii.dev = netdev; 5225 tp->mii.mdio_read = read_mii_word; 5226 tp->mii.mdio_write = write_mii_word; 5227 tp->mii.phy_id_mask = 0x3f; 5228 tp->mii.reg_num_mask = 0x1f; 5229 tp->mii.phy_id = R8152_PHY_ID; 5230 5231 tp->autoneg = AUTONEG_ENABLE; 5232 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100; 5233 tp->duplex = DUPLEX_FULL; 5234 5235 intf->needs_remote_wakeup = 1; 5236 5237 tp->rtl_ops.init(tp); 5238 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 5239 set_ethernet_addr(tp); 5240 5241 usb_set_intfdata(intf, tp); 5242 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); 5243 5244 ret = register_netdev(netdev); 5245 if (ret != 0) { 5246 netif_err(tp, probe, netdev, "couldn't register the device\n"); 5247 goto out1; 5248 } 5249 5250 if (!rtl_can_wakeup(tp)) 5251 __rtl_set_wol(tp, 0); 5252 5253 tp->saved_wolopts = __rtl_get_wol(tp); 5254 if (tp->saved_wolopts) 5255 device_set_wakeup_enable(&udev->dev, true); 5256 else 5257 device_set_wakeup_enable(&udev->dev, false); 5258 5259 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 5260 5261 return 0; 5262 5263 out1: 5264 netif_napi_del(&tp->napi); 5265 usb_set_intfdata(intf, NULL); 5266 out: 5267 free_netdev(netdev); 5268 return ret; 5269 } 5270 5271 static void rtl8152_disconnect(struct usb_interface *intf) 5272 { 5273 struct r8152 *tp = usb_get_intfdata(intf); 5274 5275 usb_set_intfdata(intf, NULL); 5276 if (tp) { 5277 struct usb_device *udev = tp->udev; 5278 5279 if (udev->state == USB_STATE_NOTATTACHED) 5280 set_bit(RTL8152_UNPLUG, &tp->flags); 5281 5282 netif_napi_del(&tp->napi); 5283 unregister_netdev(tp->netdev); 5284 cancel_delayed_work_sync(&tp->hw_phy_work); 5285 tp->rtl_ops.unload(tp); 5286 free_netdev(tp->netdev); 5287 } 5288 } 5289 5290 #define REALTEK_USB_DEVICE(vend, prod) \ 5291 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ 5292 USB_DEVICE_ID_MATCH_INT_CLASS, \ 5293 .idVendor = (vend), \ 5294 .idProduct = (prod), \ 5295 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ 5296 }, \ 5297 { \ 5298 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ 5299 USB_DEVICE_ID_MATCH_DEVICE, \ 5300 .idVendor = (vend), \ 5301 .idProduct = (prod), \ 5302 .bInterfaceClass = USB_CLASS_COMM, \ 5303 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ 5304 .bInterfaceProtocol = USB_CDC_PROTO_NONE 5305 5306 /* table of devices that work with this driver */ 5307 static const struct usb_device_id rtl8152_table[] = { 5308 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)}, 5309 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, 5310 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, 5311 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)}, 5312 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)}, 5313 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, 5314 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, 5315 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)}, 5316 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)}, 5317 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, 5318 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)}, 5319 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)}, 5320 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)}, 5321 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, 5322 {} 5323 }; 5324 5325 MODULE_DEVICE_TABLE(usb, rtl8152_table); 5326 5327 static struct usb_driver rtl8152_driver = { 5328 .name = MODULENAME, 5329 .id_table = rtl8152_table, 5330 .probe = rtl8152_probe, 5331 .disconnect = rtl8152_disconnect, 5332 .suspend = rtl8152_suspend, 5333 .resume = rtl8152_resume, 5334 .reset_resume = rtl8152_reset_resume, 5335 .pre_reset = rtl8152_pre_reset, 5336 .post_reset = rtl8152_post_reset, 5337 .supports_autosuspend = 1, 5338 .disable_hub_initiated_lpm = 1, 5339 }; 5340 5341 module_usb_driver(rtl8152_driver); 5342 5343 MODULE_AUTHOR(DRIVER_AUTHOR); 5344 MODULE_DESCRIPTION(DRIVER_DESC); 5345 MODULE_LICENSE("GPL"); 5346 MODULE_VERSION(DRIVER_VERSION); 5347