1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 4 */ 5 6 #include <linux/signal.h> 7 #include <linux/slab.h> 8 #include <linux/module.h> 9 #include <linux/netdevice.h> 10 #include <linux/etherdevice.h> 11 #include <linux/mii.h> 12 #include <linux/ethtool.h> 13 #include <linux/usb.h> 14 #include <linux/crc32.h> 15 #include <linux/if_vlan.h> 16 #include <linux/uaccess.h> 17 #include <linux/list.h> 18 #include <linux/ip.h> 19 #include <linux/ipv6.h> 20 #include <net/ip6_checksum.h> 21 #include <uapi/linux/mdio.h> 22 #include <linux/mdio.h> 23 #include <linux/usb/cdc.h> 24 #include <linux/suspend.h> 25 #include <linux/atomic.h> 26 #include <linux/acpi.h> 27 28 /* Information for net-next */ 29 #define NETNEXT_VERSION "10" 30 31 /* Information for net */ 32 #define NET_VERSION "10" 33 34 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION 35 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 36 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 37 #define MODULENAME "r8152" 38 39 #define R8152_PHY_ID 32 40 41 #define PLA_IDR 0xc000 42 #define PLA_RCR 0xc010 43 #define PLA_RMS 0xc016 44 #define PLA_RXFIFO_CTRL0 0xc0a0 45 #define PLA_RXFIFO_CTRL1 0xc0a4 46 #define PLA_RXFIFO_CTRL2 0xc0a8 47 #define PLA_DMY_REG0 0xc0b0 48 #define PLA_FMC 0xc0b4 49 #define PLA_CFG_WOL 0xc0b6 50 #define PLA_TEREDO_CFG 0xc0bc 51 #define PLA_TEREDO_WAKE_BASE 0xc0c4 52 #define PLA_MAR 0xcd00 53 #define PLA_BACKUP 0xd000 54 #define PLA_BDC_CR 0xd1a0 55 #define PLA_TEREDO_TIMER 0xd2cc 56 #define PLA_REALWOW_TIMER 0xd2e8 57 #define PLA_SUSPEND_FLAG 0xd38a 58 #define PLA_INDICATE_FALG 0xd38c 59 #define PLA_EXTRA_STATUS 0xd398 60 #define PLA_EFUSE_DATA 0xdd00 61 #define PLA_EFUSE_CMD 0xdd02 62 #define PLA_LEDSEL 0xdd90 63 #define PLA_LED_FEATURE 0xdd92 64 #define PLA_PHYAR 0xde00 65 #define PLA_BOOT_CTRL 0xe004 66 #define PLA_GPHY_INTR_IMR 0xe022 67 #define PLA_EEE_CR 0xe040 68 #define PLA_EEEP_CR 0xe080 69 #define PLA_MAC_PWR_CTRL 0xe0c0 70 #define PLA_MAC_PWR_CTRL2 0xe0ca 71 #define PLA_MAC_PWR_CTRL3 0xe0cc 72 #define PLA_MAC_PWR_CTRL4 0xe0ce 73 #define PLA_WDT6_CTRL 0xe428 74 #define PLA_TCR0 0xe610 75 #define PLA_TCR1 0xe612 76 #define PLA_MTPS 0xe615 77 #define PLA_TXFIFO_CTRL 0xe618 78 #define PLA_RSTTALLY 0xe800 79 #define PLA_CR 0xe813 80 #define PLA_CRWECR 0xe81c 81 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 82 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 83 #define PLA_CONFIG5 0xe822 84 #define PLA_PHY_PWR 0xe84c 85 #define PLA_OOB_CTRL 0xe84f 86 #define PLA_CPCR 0xe854 87 #define PLA_MISC_0 0xe858 88 #define PLA_MISC_1 0xe85a 89 #define PLA_OCP_GPHY_BASE 0xe86c 90 #define PLA_TALLYCNT 0xe890 91 #define PLA_SFF_STS_7 0xe8de 92 #define PLA_PHYSTATUS 0xe908 93 #define PLA_BP_BA 0xfc26 94 #define PLA_BP_0 0xfc28 95 #define PLA_BP_1 0xfc2a 96 #define PLA_BP_2 0xfc2c 97 #define PLA_BP_3 0xfc2e 98 #define PLA_BP_4 0xfc30 99 #define PLA_BP_5 0xfc32 100 #define PLA_BP_6 0xfc34 101 #define PLA_BP_7 0xfc36 102 #define PLA_BP_EN 0xfc38 103 104 #define USB_USB2PHY 0xb41e 105 #define USB_SSPHYLINK2 0xb428 106 #define USB_U2P3_CTRL 0xb460 107 #define USB_CSR_DUMMY1 0xb464 108 #define USB_CSR_DUMMY2 0xb466 109 #define USB_DEV_STAT 0xb808 110 #define USB_CONNECT_TIMER 0xcbf8 111 #define USB_MSC_TIMER 0xcbfc 112 #define USB_BURST_SIZE 0xcfc0 113 #define USB_LPM_CONFIG 0xcfd8 114 #define USB_USB_CTRL 0xd406 115 #define USB_PHY_CTRL 0xd408 116 #define USB_TX_AGG 0xd40a 117 #define USB_RX_BUF_TH 0xd40c 118 #define USB_USB_TIMER 0xd428 119 #define USB_RX_EARLY_TIMEOUT 0xd42c 120 #define USB_RX_EARLY_SIZE 0xd42e 121 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ 122 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ 123 #define USB_TX_DMA 0xd434 124 #define USB_UPT_RXDMA_OWN 0xd437 125 #define USB_TOLERANCE 0xd490 126 #define USB_LPM_CTRL 0xd41a 127 #define USB_BMU_RESET 0xd4b0 128 #define USB_U1U2_TIMER 0xd4da 129 #define USB_UPS_CTRL 0xd800 130 #define USB_POWER_CUT 0xd80a 131 #define USB_MISC_0 0xd81a 132 #define USB_MISC_1 0xd81f 133 #define USB_AFE_CTRL2 0xd824 134 #define USB_UPS_CFG 0xd842 135 #define USB_UPS_FLAGS 0xd848 136 #define USB_WDT11_CTRL 0xe43c 137 #define USB_BP_BA 0xfc26 138 #define USB_BP_0 0xfc28 139 #define USB_BP_1 0xfc2a 140 #define USB_BP_2 0xfc2c 141 #define USB_BP_3 0xfc2e 142 #define USB_BP_4 0xfc30 143 #define USB_BP_5 0xfc32 144 #define USB_BP_6 0xfc34 145 #define USB_BP_7 0xfc36 146 #define USB_BP_EN 0xfc38 147 #define USB_BP_8 0xfc38 148 #define USB_BP_9 0xfc3a 149 #define USB_BP_10 0xfc3c 150 #define USB_BP_11 0xfc3e 151 #define USB_BP_12 0xfc40 152 #define USB_BP_13 0xfc42 153 #define USB_BP_14 0xfc44 154 #define USB_BP_15 0xfc46 155 #define USB_BP2_EN 0xfc48 156 157 /* OCP Registers */ 158 #define OCP_ALDPS_CONFIG 0x2010 159 #define OCP_EEE_CONFIG1 0x2080 160 #define OCP_EEE_CONFIG2 0x2092 161 #define OCP_EEE_CONFIG3 0x2094 162 #define OCP_BASE_MII 0xa400 163 #define OCP_EEE_AR 0xa41a 164 #define OCP_EEE_DATA 0xa41c 165 #define OCP_PHY_STATUS 0xa420 166 #define OCP_NCTL_CFG 0xa42c 167 #define OCP_POWER_CFG 0xa430 168 #define OCP_EEE_CFG 0xa432 169 #define OCP_SRAM_ADDR 0xa436 170 #define OCP_SRAM_DATA 0xa438 171 #define OCP_DOWN_SPEED 0xa442 172 #define OCP_EEE_ABLE 0xa5c4 173 #define OCP_EEE_ADV 0xa5d0 174 #define OCP_EEE_LPABLE 0xa5d2 175 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ 176 #define OCP_PHY_PATCH_STAT 0xb800 177 #define OCP_PHY_PATCH_CMD 0xb820 178 #define OCP_ADC_IOFFSET 0xbcfc 179 #define OCP_ADC_CFG 0xbc06 180 #define OCP_SYSCLK_CFG 0xc416 181 182 /* SRAM Register */ 183 #define SRAM_GREEN_CFG 0x8011 184 #define SRAM_LPF_CFG 0x8012 185 #define SRAM_10M_AMP1 0x8080 186 #define SRAM_10M_AMP2 0x8082 187 #define SRAM_IMPEDANCE 0x8084 188 189 /* PLA_RCR */ 190 #define RCR_AAP 0x00000001 191 #define RCR_APM 0x00000002 192 #define RCR_AM 0x00000004 193 #define RCR_AB 0x00000008 194 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 195 196 /* PLA_RXFIFO_CTRL0 */ 197 #define RXFIFO_THR1_NORMAL 0x00080002 198 #define RXFIFO_THR1_OOB 0x01800003 199 200 /* PLA_RXFIFO_CTRL1 */ 201 #define RXFIFO_THR2_FULL 0x00000060 202 #define RXFIFO_THR2_HIGH 0x00000038 203 #define RXFIFO_THR2_OOB 0x0000004a 204 #define RXFIFO_THR2_NORMAL 0x00a0 205 206 /* PLA_RXFIFO_CTRL2 */ 207 #define RXFIFO_THR3_FULL 0x00000078 208 #define RXFIFO_THR3_HIGH 0x00000048 209 #define RXFIFO_THR3_OOB 0x0000005a 210 #define RXFIFO_THR3_NORMAL 0x0110 211 212 /* PLA_TXFIFO_CTRL */ 213 #define TXFIFO_THR_NORMAL 0x00400008 214 #define TXFIFO_THR_NORMAL2 0x01000008 215 216 /* PLA_DMY_REG0 */ 217 #define ECM_ALDPS 0x0002 218 219 /* PLA_FMC */ 220 #define FMC_FCR_MCU_EN 0x0001 221 222 /* PLA_EEEP_CR */ 223 #define EEEP_CR_EEEP_TX 0x0002 224 225 /* PLA_WDT6_CTRL */ 226 #define WDT6_SET_MODE 0x0010 227 228 /* PLA_TCR0 */ 229 #define TCR0_TX_EMPTY 0x0800 230 #define TCR0_AUTO_FIFO 0x0080 231 232 /* PLA_TCR1 */ 233 #define VERSION_MASK 0x7cf0 234 235 /* PLA_MTPS */ 236 #define MTPS_JUMBO (12 * 1024 / 64) 237 #define MTPS_DEFAULT (6 * 1024 / 64) 238 239 /* PLA_RSTTALLY */ 240 #define TALLY_RESET 0x0001 241 242 /* PLA_CR */ 243 #define CR_RST 0x10 244 #define CR_RE 0x08 245 #define CR_TE 0x04 246 247 /* PLA_CRWECR */ 248 #define CRWECR_NORAML 0x00 249 #define CRWECR_CONFIG 0xc0 250 251 /* PLA_OOB_CTRL */ 252 #define NOW_IS_OOB 0x80 253 #define TXFIFO_EMPTY 0x20 254 #define RXFIFO_EMPTY 0x10 255 #define LINK_LIST_READY 0x02 256 #define DIS_MCU_CLROOB 0x01 257 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 258 259 /* PLA_MISC_1 */ 260 #define RXDY_GATED_EN 0x0008 261 262 /* PLA_SFF_STS_7 */ 263 #define RE_INIT_LL 0x8000 264 #define MCU_BORW_EN 0x4000 265 266 /* PLA_CPCR */ 267 #define CPCR_RX_VLAN 0x0040 268 269 /* PLA_CFG_WOL */ 270 #define MAGIC_EN 0x0001 271 272 /* PLA_TEREDO_CFG */ 273 #define TEREDO_SEL 0x8000 274 #define TEREDO_WAKE_MASK 0x7f00 275 #define TEREDO_RS_EVENT_MASK 0x00fe 276 #define OOB_TEREDO_EN 0x0001 277 278 /* PLA_BDC_CR */ 279 #define ALDPS_PROXY_MODE 0x0001 280 281 /* PLA_EFUSE_CMD */ 282 #define EFUSE_READ_CMD BIT(15) 283 #define EFUSE_DATA_BIT16 BIT(7) 284 285 /* PLA_CONFIG34 */ 286 #define LINK_ON_WAKE_EN 0x0010 287 #define LINK_OFF_WAKE_EN 0x0008 288 289 /* PLA_CONFIG5 */ 290 #define BWF_EN 0x0040 291 #define MWF_EN 0x0020 292 #define UWF_EN 0x0010 293 #define LAN_WAKE_EN 0x0002 294 295 /* PLA_LED_FEATURE */ 296 #define LED_MODE_MASK 0x0700 297 298 /* PLA_PHY_PWR */ 299 #define TX_10M_IDLE_EN 0x0080 300 #define PFM_PWM_SWITCH 0x0040 301 302 /* PLA_MAC_PWR_CTRL */ 303 #define D3_CLK_GATED_EN 0x00004000 304 #define MCU_CLK_RATIO 0x07010f07 305 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 306 #define ALDPS_SPDWN_RATIO 0x0f87 307 308 /* PLA_MAC_PWR_CTRL2 */ 309 #define EEE_SPDWN_RATIO 0x8007 310 #define MAC_CLK_SPDWN_EN BIT(15) 311 312 /* PLA_MAC_PWR_CTRL3 */ 313 #define PKT_AVAIL_SPDWN_EN 0x0100 314 #define SUSPEND_SPDWN_EN 0x0004 315 #define U1U2_SPDWN_EN 0x0002 316 #define L1_SPDWN_EN 0x0001 317 318 /* PLA_MAC_PWR_CTRL4 */ 319 #define PWRSAVE_SPDWN_EN 0x1000 320 #define RXDV_SPDWN_EN 0x0800 321 #define TX10MIDLE_EN 0x0100 322 #define TP100_SPDWN_EN 0x0020 323 #define TP500_SPDWN_EN 0x0010 324 #define TP1000_SPDWN_EN 0x0008 325 #define EEE_SPDWN_EN 0x0001 326 327 /* PLA_GPHY_INTR_IMR */ 328 #define GPHY_STS_MSK 0x0001 329 #define SPEED_DOWN_MSK 0x0002 330 #define SPDWN_RXDV_MSK 0x0004 331 #define SPDWN_LINKCHG_MSK 0x0008 332 333 /* PLA_PHYAR */ 334 #define PHYAR_FLAG 0x80000000 335 336 /* PLA_EEE_CR */ 337 #define EEE_RX_EN 0x0001 338 #define EEE_TX_EN 0x0002 339 340 /* PLA_BOOT_CTRL */ 341 #define AUTOLOAD_DONE 0x0002 342 343 /* PLA_SUSPEND_FLAG */ 344 #define LINK_CHG_EVENT BIT(0) 345 346 /* PLA_INDICATE_FALG */ 347 #define UPCOMING_RUNTIME_D3 BIT(0) 348 349 /* PLA_EXTRA_STATUS */ 350 #define LINK_CHANGE_FLAG BIT(8) 351 352 /* USB_USB2PHY */ 353 #define USB2PHY_SUSPEND 0x0001 354 #define USB2PHY_L1 0x0002 355 356 /* USB_SSPHYLINK2 */ 357 #define pwd_dn_scale_mask 0x3ffe 358 #define pwd_dn_scale(x) ((x) << 1) 359 360 /* USB_CSR_DUMMY1 */ 361 #define DYNAMIC_BURST 0x0001 362 363 /* USB_CSR_DUMMY2 */ 364 #define EP4_FULL_FC 0x0001 365 366 /* USB_DEV_STAT */ 367 #define STAT_SPEED_MASK 0x0006 368 #define STAT_SPEED_HIGH 0x0000 369 #define STAT_SPEED_FULL 0x0002 370 371 /* USB_LPM_CONFIG */ 372 #define LPM_U1U2_EN BIT(0) 373 374 /* USB_TX_AGG */ 375 #define TX_AGG_MAX_THRESHOLD 0x03 376 377 /* USB_RX_BUF_TH */ 378 #define RX_THR_SUPPER 0x0c350180 379 #define RX_THR_HIGH 0x7a120180 380 #define RX_THR_SLOW 0xffff0180 381 #define RX_THR_B 0x00010001 382 383 /* USB_TX_DMA */ 384 #define TEST_MODE_DISABLE 0x00000001 385 #define TX_SIZE_ADJUST1 0x00000100 386 387 /* USB_BMU_RESET */ 388 #define BMU_RESET_EP_IN 0x01 389 #define BMU_RESET_EP_OUT 0x02 390 391 /* USB_UPT_RXDMA_OWN */ 392 #define OWN_UPDATE BIT(0) 393 #define OWN_CLEAR BIT(1) 394 395 /* USB_UPS_CTRL */ 396 #define POWER_CUT 0x0100 397 398 /* USB_PM_CTRL_STATUS */ 399 #define RESUME_INDICATE 0x0001 400 401 /* USB_USB_CTRL */ 402 #define RX_AGG_DISABLE 0x0010 403 #define RX_ZERO_EN 0x0080 404 405 /* USB_U2P3_CTRL */ 406 #define U2P3_ENABLE 0x0001 407 408 /* USB_POWER_CUT */ 409 #define PWR_EN 0x0001 410 #define PHASE2_EN 0x0008 411 #define UPS_EN BIT(4) 412 #define USP_PREWAKE BIT(5) 413 414 /* USB_MISC_0 */ 415 #define PCUT_STATUS 0x0001 416 417 /* USB_RX_EARLY_TIMEOUT */ 418 #define COALESCE_SUPER 85000U 419 #define COALESCE_HIGH 250000U 420 #define COALESCE_SLOW 524280U 421 422 /* USB_WDT11_CTRL */ 423 #define TIMER11_EN 0x0001 424 425 /* USB_LPM_CTRL */ 426 /* bit 4 ~ 5: fifo empty boundary */ 427 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 428 /* bit 2 ~ 3: LMP timer */ 429 #define LPM_TIMER_MASK 0x0c 430 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 431 #define LPM_TIMER_500US 0x0c /* 500 us */ 432 #define ROK_EXIT_LPM 0x02 433 434 /* USB_AFE_CTRL2 */ 435 #define SEN_VAL_MASK 0xf800 436 #define SEN_VAL_NORMAL 0xa000 437 #define SEL_RXIDLE 0x0100 438 439 /* USB_UPS_CFG */ 440 #define SAW_CNT_1MS_MASK 0x0fff 441 442 /* USB_UPS_FLAGS */ 443 #define UPS_FLAGS_R_TUNE BIT(0) 444 #define UPS_FLAGS_EN_10M_CKDIV BIT(1) 445 #define UPS_FLAGS_250M_CKDIV BIT(2) 446 #define UPS_FLAGS_EN_ALDPS BIT(3) 447 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) 448 #define ups_flags_speed(x) ((x) << 16) 449 #define UPS_FLAGS_EN_EEE BIT(20) 450 #define UPS_FLAGS_EN_500M_EEE BIT(21) 451 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22) 452 #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23) 453 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) 454 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) 455 #define UPS_FLAGS_EN_GREEN BIT(26) 456 #define UPS_FLAGS_EN_FLOW_CTR BIT(27) 457 458 enum spd_duplex { 459 NWAY_10M_HALF, 460 NWAY_10M_FULL, 461 NWAY_100M_HALF, 462 NWAY_100M_FULL, 463 NWAY_1000M_FULL, 464 FORCE_10M_HALF, 465 FORCE_10M_FULL, 466 FORCE_100M_HALF, 467 FORCE_100M_FULL, 468 }; 469 470 /* OCP_ALDPS_CONFIG */ 471 #define ENPWRSAVE 0x8000 472 #define ENPDNPS 0x0200 473 #define LINKENA 0x0100 474 #define DIS_SDSAVE 0x0010 475 476 /* OCP_PHY_STATUS */ 477 #define PHY_STAT_MASK 0x0007 478 #define PHY_STAT_EXT_INIT 2 479 #define PHY_STAT_LAN_ON 3 480 #define PHY_STAT_PWRDN 5 481 482 /* OCP_NCTL_CFG */ 483 #define PGA_RETURN_EN BIT(1) 484 485 /* OCP_POWER_CFG */ 486 #define EEE_CLKDIV_EN 0x8000 487 #define EN_ALDPS 0x0004 488 #define EN_10M_PLLOFF 0x0001 489 490 /* OCP_EEE_CONFIG1 */ 491 #define RG_TXLPI_MSK_HFDUP 0x8000 492 #define RG_MATCLR_EN 0x4000 493 #define EEE_10_CAP 0x2000 494 #define EEE_NWAY_EN 0x1000 495 #define TX_QUIET_EN 0x0200 496 #define RX_QUIET_EN 0x0100 497 #define sd_rise_time_mask 0x0070 498 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 499 #define RG_RXLPI_MSK_HFDUP 0x0008 500 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 501 502 /* OCP_EEE_CONFIG2 */ 503 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 504 #define RG_DACQUIET_EN 0x0400 505 #define RG_LDVQUIET_EN 0x0200 506 #define RG_CKRSEL 0x0020 507 #define RG_EEEPRG_EN 0x0010 508 509 /* OCP_EEE_CONFIG3 */ 510 #define fast_snr_mask 0xff80 511 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 512 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 513 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 514 515 /* OCP_EEE_AR */ 516 /* bit[15:14] function */ 517 #define FUN_ADDR 0x0000 518 #define FUN_DATA 0x4000 519 /* bit[4:0] device addr */ 520 521 /* OCP_EEE_CFG */ 522 #define CTAP_SHORT_EN 0x0040 523 #define EEE10_EN 0x0010 524 525 /* OCP_DOWN_SPEED */ 526 #define EN_EEE_CMODE BIT(14) 527 #define EN_EEE_1000 BIT(13) 528 #define EN_EEE_100 BIT(12) 529 #define EN_10M_CLKDIV BIT(11) 530 #define EN_10M_BGOFF 0x0080 531 532 /* OCP_PHY_STATE */ 533 #define TXDIS_STATE 0x01 534 #define ABD_STATE 0x02 535 536 /* OCP_PHY_PATCH_STAT */ 537 #define PATCH_READY BIT(6) 538 539 /* OCP_PHY_PATCH_CMD */ 540 #define PATCH_REQUEST BIT(4) 541 542 /* OCP_ADC_CFG */ 543 #define CKADSEL_L 0x0100 544 #define ADC_EN 0x0080 545 #define EN_EMI_L 0x0040 546 547 /* OCP_SYSCLK_CFG */ 548 #define clk_div_expo(x) (min(x, 5) << 8) 549 550 /* SRAM_GREEN_CFG */ 551 #define GREEN_ETH_EN BIT(15) 552 #define R_TUNE_EN BIT(11) 553 554 /* SRAM_LPF_CFG */ 555 #define LPF_AUTO_TUNE 0x8000 556 557 /* SRAM_10M_AMP1 */ 558 #define GDAC_IB_UPALL 0x0008 559 560 /* SRAM_10M_AMP2 */ 561 #define AMP_DN 0x0200 562 563 /* SRAM_IMPEDANCE */ 564 #define RX_DRIVING_MASK 0x6000 565 566 /* MAC PASSTHRU */ 567 #define AD_MASK 0xfee0 568 #define BND_MASK 0x0004 569 #define BD_MASK 0x0001 570 #define EFUSE 0xcfdb 571 #define PASS_THRU_MASK 0x1 572 573 enum rtl_register_content { 574 _1000bps = 0x10, 575 _100bps = 0x08, 576 _10bps = 0x04, 577 LINK_STATUS = 0x02, 578 FULL_DUP = 0x01, 579 }; 580 581 #define RTL8152_MAX_TX 4 582 #define RTL8152_MAX_RX 10 583 #define INTBUFSIZE 2 584 #define TX_ALIGN 4 585 #define RX_ALIGN 8 586 587 #define RTL8152_RX_MAX_PENDING 4096 588 #define RTL8152_RXFG_HEADSZ 256 589 590 #define INTR_LINK 0x0004 591 592 #define RTL8152_REQT_READ 0xc0 593 #define RTL8152_REQT_WRITE 0x40 594 #define RTL8152_REQ_GET_REGS 0x05 595 #define RTL8152_REQ_SET_REGS 0x05 596 597 #define BYTE_EN_DWORD 0xff 598 #define BYTE_EN_WORD 0x33 599 #define BYTE_EN_BYTE 0x11 600 #define BYTE_EN_SIX_BYTES 0x3f 601 #define BYTE_EN_START_MASK 0x0f 602 #define BYTE_EN_END_MASK 0xf0 603 604 #define RTL8153_MAX_PACKET 9216 /* 9K */ 605 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \ 606 ETH_FCS_LEN) 607 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 608 #define RTL8153_RMS RTL8153_MAX_PACKET 609 #define RTL8152_TX_TIMEOUT (5 * HZ) 610 #define RTL8152_NAPI_WEIGHT 64 611 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \ 612 sizeof(struct rx_desc) + RX_ALIGN) 613 614 /* rtl8152 flags */ 615 enum rtl8152_flags { 616 RTL8152_UNPLUG = 0, 617 RTL8152_SET_RX_MODE, 618 WORK_ENABLE, 619 RTL8152_LINK_CHG, 620 SELECTIVE_SUSPEND, 621 PHY_RESET, 622 SCHEDULE_TASKLET, 623 GREEN_ETHERNET, 624 DELL_TB_RX_AGG_BUG, 625 }; 626 627 /* Define these values to match your device */ 628 #define VENDOR_ID_REALTEK 0x0bda 629 #define VENDOR_ID_MICROSOFT 0x045e 630 #define VENDOR_ID_SAMSUNG 0x04e8 631 #define VENDOR_ID_LENOVO 0x17ef 632 #define VENDOR_ID_LINKSYS 0x13b1 633 #define VENDOR_ID_NVIDIA 0x0955 634 #define VENDOR_ID_TPLINK 0x2357 635 636 #define MCU_TYPE_PLA 0x0100 637 #define MCU_TYPE_USB 0x0000 638 639 struct tally_counter { 640 __le64 tx_packets; 641 __le64 rx_packets; 642 __le64 tx_errors; 643 __le32 rx_errors; 644 __le16 rx_missed; 645 __le16 align_errors; 646 __le32 tx_one_collision; 647 __le32 tx_multi_collision; 648 __le64 rx_unicast; 649 __le64 rx_broadcast; 650 __le32 rx_multicast; 651 __le16 tx_aborted; 652 __le16 tx_underrun; 653 }; 654 655 struct rx_desc { 656 __le32 opts1; 657 #define RX_LEN_MASK 0x7fff 658 659 __le32 opts2; 660 #define RD_UDP_CS BIT(23) 661 #define RD_TCP_CS BIT(22) 662 #define RD_IPV6_CS BIT(20) 663 #define RD_IPV4_CS BIT(19) 664 665 __le32 opts3; 666 #define IPF BIT(23) /* IP checksum fail */ 667 #define UDPF BIT(22) /* UDP checksum fail */ 668 #define TCPF BIT(21) /* TCP checksum fail */ 669 #define RX_VLAN_TAG BIT(16) 670 671 __le32 opts4; 672 __le32 opts5; 673 __le32 opts6; 674 }; 675 676 struct tx_desc { 677 __le32 opts1; 678 #define TX_FS BIT(31) /* First segment of a packet */ 679 #define TX_LS BIT(30) /* Final segment of a packet */ 680 #define GTSENDV4 BIT(28) 681 #define GTSENDV6 BIT(27) 682 #define GTTCPHO_SHIFT 18 683 #define GTTCPHO_MAX 0x7fU 684 #define TX_LEN_MAX 0x3ffffU 685 686 __le32 opts2; 687 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 688 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 689 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 690 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 691 #define MSS_SHIFT 17 692 #define MSS_MAX 0x7ffU 693 #define TCPHO_SHIFT 17 694 #define TCPHO_MAX 0x7ffU 695 #define TX_VLAN_TAG BIT(16) 696 }; 697 698 struct r8152; 699 700 struct rx_agg { 701 struct list_head list, info_list; 702 struct urb *urb; 703 struct r8152 *context; 704 struct page *page; 705 void *buffer; 706 }; 707 708 struct tx_agg { 709 struct list_head list; 710 struct urb *urb; 711 struct r8152 *context; 712 void *buffer; 713 void *head; 714 u32 skb_num; 715 u32 skb_len; 716 }; 717 718 struct r8152 { 719 unsigned long flags; 720 struct usb_device *udev; 721 struct napi_struct napi; 722 struct usb_interface *intf; 723 struct net_device *netdev; 724 struct urb *intr_urb; 725 struct tx_agg tx_info[RTL8152_MAX_TX]; 726 struct list_head rx_info, rx_used; 727 struct list_head rx_done, tx_free; 728 struct sk_buff_head tx_queue, rx_queue; 729 spinlock_t rx_lock, tx_lock; 730 struct delayed_work schedule, hw_phy_work; 731 struct mii_if_info mii; 732 struct mutex control; /* use for hw setting */ 733 #ifdef CONFIG_PM_SLEEP 734 struct notifier_block pm_notifier; 735 #endif 736 struct tasklet_struct tx_tl; 737 738 struct rtl_ops { 739 void (*init)(struct r8152 *); 740 int (*enable)(struct r8152 *); 741 void (*disable)(struct r8152 *); 742 void (*up)(struct r8152 *); 743 void (*down)(struct r8152 *); 744 void (*unload)(struct r8152 *); 745 int (*eee_get)(struct r8152 *, struct ethtool_eee *); 746 int (*eee_set)(struct r8152 *, struct ethtool_eee *); 747 bool (*in_nway)(struct r8152 *); 748 void (*hw_phy_cfg)(struct r8152 *); 749 void (*autosuspend_en)(struct r8152 *tp, bool enable); 750 } rtl_ops; 751 752 struct ups_info { 753 u32 _10m_ckdiv:1; 754 u32 _250m_ckdiv:1; 755 u32 aldps:1; 756 u32 lite_mode:2; 757 u32 speed_duplex:4; 758 u32 eee:1; 759 u32 eee_lite:1; 760 u32 eee_ckdiv:1; 761 u32 eee_plloff_100:1; 762 u32 eee_plloff_giga:1; 763 u32 eee_cmod_lv:1; 764 u32 green:1; 765 u32 flow_control:1; 766 u32 ctap_short_off:1; 767 } ups_info; 768 769 atomic_t rx_count; 770 771 bool eee_en; 772 int intr_interval; 773 u32 saved_wolopts; 774 u32 msg_enable; 775 u32 tx_qlen; 776 u32 coalesce; 777 u32 advertising; 778 u32 rx_buf_sz; 779 u32 rx_copybreak; 780 u32 rx_pending; 781 782 u16 ocp_base; 783 u16 speed; 784 u16 eee_adv; 785 u8 *intr_buff; 786 u8 version; 787 u8 duplex; 788 u8 autoneg; 789 }; 790 791 enum rtl_version { 792 RTL_VER_UNKNOWN = 0, 793 RTL_VER_01, 794 RTL_VER_02, 795 RTL_VER_03, 796 RTL_VER_04, 797 RTL_VER_05, 798 RTL_VER_06, 799 RTL_VER_07, 800 RTL_VER_08, 801 RTL_VER_09, 802 RTL_VER_MAX 803 }; 804 805 enum tx_csum_stat { 806 TX_CSUM_SUCCESS = 0, 807 TX_CSUM_TSO, 808 TX_CSUM_NONE 809 }; 810 811 #define RTL_ADVERTISED_10_HALF BIT(0) 812 #define RTL_ADVERTISED_10_FULL BIT(1) 813 #define RTL_ADVERTISED_100_HALF BIT(2) 814 #define RTL_ADVERTISED_100_FULL BIT(3) 815 #define RTL_ADVERTISED_1000_HALF BIT(4) 816 #define RTL_ADVERTISED_1000_FULL BIT(5) 817 818 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 819 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 820 */ 821 static const int multicast_filter_limit = 32; 822 static unsigned int agg_buf_sz = 16384; 823 824 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ 825 VLAN_ETH_HLEN - ETH_FCS_LEN) 826 827 static 828 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 829 { 830 int ret; 831 void *tmp; 832 833 tmp = kmalloc(size, GFP_KERNEL); 834 if (!tmp) 835 return -ENOMEM; 836 837 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 838 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 839 value, index, tmp, size, 500); 840 if (ret < 0) 841 memset(data, 0xff, size); 842 else 843 memcpy(data, tmp, size); 844 845 kfree(tmp); 846 847 return ret; 848 } 849 850 static 851 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 852 { 853 int ret; 854 void *tmp; 855 856 tmp = kmemdup(data, size, GFP_KERNEL); 857 if (!tmp) 858 return -ENOMEM; 859 860 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 861 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 862 value, index, tmp, size, 500); 863 864 kfree(tmp); 865 866 return ret; 867 } 868 869 static void rtl_set_unplug(struct r8152 *tp) 870 { 871 if (tp->udev->state == USB_STATE_NOTATTACHED) { 872 set_bit(RTL8152_UNPLUG, &tp->flags); 873 smp_mb__after_atomic(); 874 } 875 } 876 877 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 878 void *data, u16 type) 879 { 880 u16 limit = 64; 881 int ret = 0; 882 883 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 884 return -ENODEV; 885 886 /* both size and indix must be 4 bytes align */ 887 if ((size & 3) || !size || (index & 3) || !data) 888 return -EPERM; 889 890 if ((u32)index + (u32)size > 0xffff) 891 return -EPERM; 892 893 while (size) { 894 if (size > limit) { 895 ret = get_registers(tp, index, type, limit, data); 896 if (ret < 0) 897 break; 898 899 index += limit; 900 data += limit; 901 size -= limit; 902 } else { 903 ret = get_registers(tp, index, type, size, data); 904 if (ret < 0) 905 break; 906 907 index += size; 908 data += size; 909 size = 0; 910 break; 911 } 912 } 913 914 if (ret == -ENODEV) 915 rtl_set_unplug(tp); 916 917 return ret; 918 } 919 920 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 921 u16 size, void *data, u16 type) 922 { 923 int ret; 924 u16 byteen_start, byteen_end, byen; 925 u16 limit = 512; 926 927 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 928 return -ENODEV; 929 930 /* both size and indix must be 4 bytes align */ 931 if ((size & 3) || !size || (index & 3) || !data) 932 return -EPERM; 933 934 if ((u32)index + (u32)size > 0xffff) 935 return -EPERM; 936 937 byteen_start = byteen & BYTE_EN_START_MASK; 938 byteen_end = byteen & BYTE_EN_END_MASK; 939 940 byen = byteen_start | (byteen_start << 4); 941 ret = set_registers(tp, index, type | byen, 4, data); 942 if (ret < 0) 943 goto error1; 944 945 index += 4; 946 data += 4; 947 size -= 4; 948 949 if (size) { 950 size -= 4; 951 952 while (size) { 953 if (size > limit) { 954 ret = set_registers(tp, index, 955 type | BYTE_EN_DWORD, 956 limit, data); 957 if (ret < 0) 958 goto error1; 959 960 index += limit; 961 data += limit; 962 size -= limit; 963 } else { 964 ret = set_registers(tp, index, 965 type | BYTE_EN_DWORD, 966 size, data); 967 if (ret < 0) 968 goto error1; 969 970 index += size; 971 data += size; 972 size = 0; 973 break; 974 } 975 } 976 977 byen = byteen_end | (byteen_end >> 4); 978 ret = set_registers(tp, index, type | byen, 4, data); 979 if (ret < 0) 980 goto error1; 981 } 982 983 error1: 984 if (ret == -ENODEV) 985 rtl_set_unplug(tp); 986 987 return ret; 988 } 989 990 static inline 991 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 992 { 993 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 994 } 995 996 static inline 997 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 998 { 999 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 1000 } 1001 1002 static inline 1003 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 1004 { 1005 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 1006 } 1007 1008 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 1009 { 1010 __le32 data; 1011 1012 generic_ocp_read(tp, index, sizeof(data), &data, type); 1013 1014 return __le32_to_cpu(data); 1015 } 1016 1017 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 1018 { 1019 __le32 tmp = __cpu_to_le32(data); 1020 1021 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 1022 } 1023 1024 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 1025 { 1026 u32 data; 1027 __le32 tmp; 1028 u16 byen = BYTE_EN_WORD; 1029 u8 shift = index & 2; 1030 1031 index &= ~3; 1032 byen <<= shift; 1033 1034 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen); 1035 1036 data = __le32_to_cpu(tmp); 1037 data >>= (shift * 8); 1038 data &= 0xffff; 1039 1040 return (u16)data; 1041 } 1042 1043 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 1044 { 1045 u32 mask = 0xffff; 1046 __le32 tmp; 1047 u16 byen = BYTE_EN_WORD; 1048 u8 shift = index & 2; 1049 1050 data &= mask; 1051 1052 if (index & 2) { 1053 byen <<= shift; 1054 mask <<= (shift * 8); 1055 data <<= (shift * 8); 1056 index &= ~3; 1057 } 1058 1059 tmp = __cpu_to_le32(data); 1060 1061 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1062 } 1063 1064 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 1065 { 1066 u32 data; 1067 __le32 tmp; 1068 u8 shift = index & 3; 1069 1070 index &= ~3; 1071 1072 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 1073 1074 data = __le32_to_cpu(tmp); 1075 data >>= (shift * 8); 1076 data &= 0xff; 1077 1078 return (u8)data; 1079 } 1080 1081 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 1082 { 1083 u32 mask = 0xff; 1084 __le32 tmp; 1085 u16 byen = BYTE_EN_BYTE; 1086 u8 shift = index & 3; 1087 1088 data &= mask; 1089 1090 if (index & 3) { 1091 byen <<= shift; 1092 mask <<= (shift * 8); 1093 data <<= (shift * 8); 1094 index &= ~3; 1095 } 1096 1097 tmp = __cpu_to_le32(data); 1098 1099 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1100 } 1101 1102 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 1103 { 1104 u16 ocp_base, ocp_index; 1105 1106 ocp_base = addr & 0xf000; 1107 if (ocp_base != tp->ocp_base) { 1108 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1109 tp->ocp_base = ocp_base; 1110 } 1111 1112 ocp_index = (addr & 0x0fff) | 0xb000; 1113 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 1114 } 1115 1116 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 1117 { 1118 u16 ocp_base, ocp_index; 1119 1120 ocp_base = addr & 0xf000; 1121 if (ocp_base != tp->ocp_base) { 1122 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1123 tp->ocp_base = ocp_base; 1124 } 1125 1126 ocp_index = (addr & 0x0fff) | 0xb000; 1127 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 1128 } 1129 1130 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 1131 { 1132 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 1133 } 1134 1135 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 1136 { 1137 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 1138 } 1139 1140 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 1141 { 1142 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1143 ocp_reg_write(tp, OCP_SRAM_DATA, data); 1144 } 1145 1146 static u16 sram_read(struct r8152 *tp, u16 addr) 1147 { 1148 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1149 return ocp_reg_read(tp, OCP_SRAM_DATA); 1150 } 1151 1152 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 1153 { 1154 struct r8152 *tp = netdev_priv(netdev); 1155 int ret; 1156 1157 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1158 return -ENODEV; 1159 1160 if (phy_id != R8152_PHY_ID) 1161 return -EINVAL; 1162 1163 ret = r8152_mdio_read(tp, reg); 1164 1165 return ret; 1166 } 1167 1168 static 1169 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 1170 { 1171 struct r8152 *tp = netdev_priv(netdev); 1172 1173 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1174 return; 1175 1176 if (phy_id != R8152_PHY_ID) 1177 return; 1178 1179 r8152_mdio_write(tp, reg, val); 1180 } 1181 1182 static int 1183 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 1184 1185 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1186 { 1187 struct r8152 *tp = netdev_priv(netdev); 1188 struct sockaddr *addr = p; 1189 int ret = -EADDRNOTAVAIL; 1190 1191 if (!is_valid_ether_addr(addr->sa_data)) 1192 goto out1; 1193 1194 ret = usb_autopm_get_interface(tp->intf); 1195 if (ret < 0) 1196 goto out1; 1197 1198 mutex_lock(&tp->control); 1199 1200 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1201 1202 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1203 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1204 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1205 1206 mutex_unlock(&tp->control); 1207 1208 usb_autopm_put_interface(tp->intf); 1209 out1: 1210 return ret; 1211 } 1212 1213 /* Devices containing proper chips can support a persistent 1214 * host system provided MAC address. 1215 * Examples of this are Dell TB15 and Dell WD15 docks 1216 */ 1217 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) 1218 { 1219 acpi_status status; 1220 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1221 union acpi_object *obj; 1222 int ret = -EINVAL; 1223 u32 ocp_data; 1224 unsigned char buf[6]; 1225 1226 /* test for -AD variant of RTL8153 */ 1227 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 1228 if ((ocp_data & AD_MASK) == 0x1000) { 1229 /* test for MAC address pass-through bit */ 1230 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); 1231 if ((ocp_data & PASS_THRU_MASK) != 1) { 1232 netif_dbg(tp, probe, tp->netdev, 1233 "No efuse for RTL8153-AD MAC pass through\n"); 1234 return -ENODEV; 1235 } 1236 } else { 1237 /* test for RTL8153-BND and RTL8153-BD */ 1238 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); 1239 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) { 1240 netif_dbg(tp, probe, tp->netdev, 1241 "Invalid variant for MAC pass through\n"); 1242 return -ENODEV; 1243 } 1244 } 1245 1246 /* returns _AUXMAC_#AABBCCDDEEFF# */ 1247 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer); 1248 obj = (union acpi_object *)buffer.pointer; 1249 if (!ACPI_SUCCESS(status)) 1250 return -ENODEV; 1251 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) { 1252 netif_warn(tp, probe, tp->netdev, 1253 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", 1254 obj->type, obj->string.length); 1255 goto amacout; 1256 } 1257 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || 1258 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { 1259 netif_warn(tp, probe, tp->netdev, 1260 "Invalid header when reading pass-thru MAC addr\n"); 1261 goto amacout; 1262 } 1263 ret = hex2bin(buf, obj->string.pointer + 9, 6); 1264 if (!(ret == 0 && is_valid_ether_addr(buf))) { 1265 netif_warn(tp, probe, tp->netdev, 1266 "Invalid MAC for pass-thru MAC addr: %d, %pM\n", 1267 ret, buf); 1268 ret = -EINVAL; 1269 goto amacout; 1270 } 1271 memcpy(sa->sa_data, buf, 6); 1272 netif_info(tp, probe, tp->netdev, 1273 "Using pass-thru MAC addr %pM\n", sa->sa_data); 1274 1275 amacout: 1276 kfree(obj); 1277 return ret; 1278 } 1279 1280 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa) 1281 { 1282 struct net_device *dev = tp->netdev; 1283 int ret; 1284 1285 sa->sa_family = dev->type; 1286 1287 if (tp->version == RTL_VER_01) { 1288 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data); 1289 } else { 1290 /* if device doesn't support MAC pass through this will 1291 * be expected to be non-zero 1292 */ 1293 ret = vendor_mac_passthru_addr_read(tp, sa); 1294 if (ret < 0) 1295 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa->sa_data); 1296 } 1297 1298 if (ret < 0) { 1299 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1300 } else if (!is_valid_ether_addr(sa->sa_data)) { 1301 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1302 sa->sa_data); 1303 eth_hw_addr_random(dev); 1304 ether_addr_copy(sa->sa_data, dev->dev_addr); 1305 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1306 sa->sa_data); 1307 return 0; 1308 } 1309 1310 return ret; 1311 } 1312 1313 static int set_ethernet_addr(struct r8152 *tp) 1314 { 1315 struct net_device *dev = tp->netdev; 1316 struct sockaddr sa; 1317 int ret; 1318 1319 ret = determine_ethernet_addr(tp, &sa); 1320 if (ret < 0) 1321 return ret; 1322 1323 if (tp->version == RTL_VER_01) 1324 ether_addr_copy(dev->dev_addr, sa.sa_data); 1325 else 1326 ret = rtl8152_set_mac_address(dev, &sa); 1327 1328 return ret; 1329 } 1330 1331 static void read_bulk_callback(struct urb *urb) 1332 { 1333 struct net_device *netdev; 1334 int status = urb->status; 1335 struct rx_agg *agg; 1336 struct r8152 *tp; 1337 unsigned long flags; 1338 1339 agg = urb->context; 1340 if (!agg) 1341 return; 1342 1343 tp = agg->context; 1344 if (!tp) 1345 return; 1346 1347 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1348 return; 1349 1350 if (!test_bit(WORK_ENABLE, &tp->flags)) 1351 return; 1352 1353 netdev = tp->netdev; 1354 1355 /* When link down, the driver would cancel all bulks. */ 1356 /* This avoid the re-submitting bulk */ 1357 if (!netif_carrier_ok(netdev)) 1358 return; 1359 1360 usb_mark_last_busy(tp->udev); 1361 1362 switch (status) { 1363 case 0: 1364 if (urb->actual_length < ETH_ZLEN) 1365 break; 1366 1367 spin_lock_irqsave(&tp->rx_lock, flags); 1368 list_add_tail(&agg->list, &tp->rx_done); 1369 spin_unlock_irqrestore(&tp->rx_lock, flags); 1370 napi_schedule(&tp->napi); 1371 return; 1372 case -ESHUTDOWN: 1373 rtl_set_unplug(tp); 1374 netif_device_detach(tp->netdev); 1375 return; 1376 case -ENOENT: 1377 return; /* the urb is in unlink state */ 1378 case -ETIME: 1379 if (net_ratelimit()) 1380 netdev_warn(netdev, "maybe reset is needed?\n"); 1381 break; 1382 default: 1383 if (net_ratelimit()) 1384 netdev_warn(netdev, "Rx status %d\n", status); 1385 break; 1386 } 1387 1388 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1389 } 1390 1391 static void write_bulk_callback(struct urb *urb) 1392 { 1393 struct net_device_stats *stats; 1394 struct net_device *netdev; 1395 struct tx_agg *agg; 1396 struct r8152 *tp; 1397 unsigned long flags; 1398 int status = urb->status; 1399 1400 agg = urb->context; 1401 if (!agg) 1402 return; 1403 1404 tp = agg->context; 1405 if (!tp) 1406 return; 1407 1408 netdev = tp->netdev; 1409 stats = &netdev->stats; 1410 if (status) { 1411 if (net_ratelimit()) 1412 netdev_warn(netdev, "Tx status %d\n", status); 1413 stats->tx_errors += agg->skb_num; 1414 } else { 1415 stats->tx_packets += agg->skb_num; 1416 stats->tx_bytes += agg->skb_len; 1417 } 1418 1419 spin_lock_irqsave(&tp->tx_lock, flags); 1420 list_add_tail(&agg->list, &tp->tx_free); 1421 spin_unlock_irqrestore(&tp->tx_lock, flags); 1422 1423 usb_autopm_put_interface_async(tp->intf); 1424 1425 if (!netif_carrier_ok(netdev)) 1426 return; 1427 1428 if (!test_bit(WORK_ENABLE, &tp->flags)) 1429 return; 1430 1431 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1432 return; 1433 1434 if (!skb_queue_empty(&tp->tx_queue)) 1435 tasklet_schedule(&tp->tx_tl); 1436 } 1437 1438 static void intr_callback(struct urb *urb) 1439 { 1440 struct r8152 *tp; 1441 __le16 *d; 1442 int status = urb->status; 1443 int res; 1444 1445 tp = urb->context; 1446 if (!tp) 1447 return; 1448 1449 if (!test_bit(WORK_ENABLE, &tp->flags)) 1450 return; 1451 1452 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1453 return; 1454 1455 switch (status) { 1456 case 0: /* success */ 1457 break; 1458 case -ECONNRESET: /* unlink */ 1459 case -ESHUTDOWN: 1460 netif_device_detach(tp->netdev); 1461 /* fall through */ 1462 case -ENOENT: 1463 case -EPROTO: 1464 netif_info(tp, intr, tp->netdev, 1465 "Stop submitting intr, status %d\n", status); 1466 return; 1467 case -EOVERFLOW: 1468 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1469 goto resubmit; 1470 /* -EPIPE: should clear the halt */ 1471 default: 1472 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1473 goto resubmit; 1474 } 1475 1476 d = urb->transfer_buffer; 1477 if (INTR_LINK & __le16_to_cpu(d[0])) { 1478 if (!netif_carrier_ok(tp->netdev)) { 1479 set_bit(RTL8152_LINK_CHG, &tp->flags); 1480 schedule_delayed_work(&tp->schedule, 0); 1481 } 1482 } else { 1483 if (netif_carrier_ok(tp->netdev)) { 1484 netif_stop_queue(tp->netdev); 1485 set_bit(RTL8152_LINK_CHG, &tp->flags); 1486 schedule_delayed_work(&tp->schedule, 0); 1487 } 1488 } 1489 1490 resubmit: 1491 res = usb_submit_urb(urb, GFP_ATOMIC); 1492 if (res == -ENODEV) { 1493 rtl_set_unplug(tp); 1494 netif_device_detach(tp->netdev); 1495 } else if (res) { 1496 netif_err(tp, intr, tp->netdev, 1497 "can't resubmit intr, status %d\n", res); 1498 } 1499 } 1500 1501 static inline void *rx_agg_align(void *data) 1502 { 1503 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1504 } 1505 1506 static inline void *tx_agg_align(void *data) 1507 { 1508 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1509 } 1510 1511 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg) 1512 { 1513 list_del(&agg->info_list); 1514 1515 usb_free_urb(agg->urb); 1516 put_page(agg->page); 1517 kfree(agg); 1518 1519 atomic_dec(&tp->rx_count); 1520 } 1521 1522 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags) 1523 { 1524 struct net_device *netdev = tp->netdev; 1525 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1526 unsigned int order = get_order(tp->rx_buf_sz); 1527 struct rx_agg *rx_agg; 1528 unsigned long flags; 1529 1530 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node); 1531 if (!rx_agg) 1532 return NULL; 1533 1534 rx_agg->page = alloc_pages(mflags | __GFP_COMP, order); 1535 if (!rx_agg->page) 1536 goto free_rx; 1537 1538 rx_agg->buffer = page_address(rx_agg->page); 1539 1540 rx_agg->urb = usb_alloc_urb(0, mflags); 1541 if (!rx_agg->urb) 1542 goto free_buf; 1543 1544 rx_agg->context = tp; 1545 1546 INIT_LIST_HEAD(&rx_agg->list); 1547 INIT_LIST_HEAD(&rx_agg->info_list); 1548 spin_lock_irqsave(&tp->rx_lock, flags); 1549 list_add_tail(&rx_agg->info_list, &tp->rx_info); 1550 spin_unlock_irqrestore(&tp->rx_lock, flags); 1551 1552 atomic_inc(&tp->rx_count); 1553 1554 return rx_agg; 1555 1556 free_buf: 1557 __free_pages(rx_agg->page, order); 1558 free_rx: 1559 kfree(rx_agg); 1560 return NULL; 1561 } 1562 1563 static void free_all_mem(struct r8152 *tp) 1564 { 1565 struct rx_agg *agg, *agg_next; 1566 unsigned long flags; 1567 int i; 1568 1569 spin_lock_irqsave(&tp->rx_lock, flags); 1570 1571 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list) 1572 free_rx_agg(tp, agg); 1573 1574 spin_unlock_irqrestore(&tp->rx_lock, flags); 1575 1576 WARN_ON(atomic_read(&tp->rx_count)); 1577 1578 for (i = 0; i < RTL8152_MAX_TX; i++) { 1579 usb_free_urb(tp->tx_info[i].urb); 1580 tp->tx_info[i].urb = NULL; 1581 1582 kfree(tp->tx_info[i].buffer); 1583 tp->tx_info[i].buffer = NULL; 1584 tp->tx_info[i].head = NULL; 1585 } 1586 1587 usb_free_urb(tp->intr_urb); 1588 tp->intr_urb = NULL; 1589 1590 kfree(tp->intr_buff); 1591 tp->intr_buff = NULL; 1592 } 1593 1594 static int alloc_all_mem(struct r8152 *tp) 1595 { 1596 struct net_device *netdev = tp->netdev; 1597 struct usb_interface *intf = tp->intf; 1598 struct usb_host_interface *alt = intf->cur_altsetting; 1599 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1600 int node, i; 1601 1602 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1603 1604 spin_lock_init(&tp->rx_lock); 1605 spin_lock_init(&tp->tx_lock); 1606 INIT_LIST_HEAD(&tp->rx_info); 1607 INIT_LIST_HEAD(&tp->tx_free); 1608 INIT_LIST_HEAD(&tp->rx_done); 1609 skb_queue_head_init(&tp->tx_queue); 1610 skb_queue_head_init(&tp->rx_queue); 1611 atomic_set(&tp->rx_count, 0); 1612 1613 for (i = 0; i < RTL8152_MAX_RX; i++) { 1614 if (!alloc_rx_agg(tp, GFP_KERNEL)) 1615 goto err1; 1616 } 1617 1618 for (i = 0; i < RTL8152_MAX_TX; i++) { 1619 struct urb *urb; 1620 u8 *buf; 1621 1622 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1623 if (!buf) 1624 goto err1; 1625 1626 if (buf != tx_agg_align(buf)) { 1627 kfree(buf); 1628 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 1629 node); 1630 if (!buf) 1631 goto err1; 1632 } 1633 1634 urb = usb_alloc_urb(0, GFP_KERNEL); 1635 if (!urb) { 1636 kfree(buf); 1637 goto err1; 1638 } 1639 1640 INIT_LIST_HEAD(&tp->tx_info[i].list); 1641 tp->tx_info[i].context = tp; 1642 tp->tx_info[i].urb = urb; 1643 tp->tx_info[i].buffer = buf; 1644 tp->tx_info[i].head = tx_agg_align(buf); 1645 1646 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1647 } 1648 1649 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1650 if (!tp->intr_urb) 1651 goto err1; 1652 1653 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1654 if (!tp->intr_buff) 1655 goto err1; 1656 1657 tp->intr_interval = (int)ep_intr->desc.bInterval; 1658 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1659 tp->intr_buff, INTBUFSIZE, intr_callback, 1660 tp, tp->intr_interval); 1661 1662 return 0; 1663 1664 err1: 1665 free_all_mem(tp); 1666 return -ENOMEM; 1667 } 1668 1669 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1670 { 1671 struct tx_agg *agg = NULL; 1672 unsigned long flags; 1673 1674 if (list_empty(&tp->tx_free)) 1675 return NULL; 1676 1677 spin_lock_irqsave(&tp->tx_lock, flags); 1678 if (!list_empty(&tp->tx_free)) { 1679 struct list_head *cursor; 1680 1681 cursor = tp->tx_free.next; 1682 list_del_init(cursor); 1683 agg = list_entry(cursor, struct tx_agg, list); 1684 } 1685 spin_unlock_irqrestore(&tp->tx_lock, flags); 1686 1687 return agg; 1688 } 1689 1690 /* r8152_csum_workaround() 1691 * The hw limites the value the transport offset. When the offset is out of the 1692 * range, calculate the checksum by sw. 1693 */ 1694 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1695 struct sk_buff_head *list) 1696 { 1697 if (skb_shinfo(skb)->gso_size) { 1698 netdev_features_t features = tp->netdev->features; 1699 struct sk_buff_head seg_list; 1700 struct sk_buff *segs, *nskb; 1701 1702 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 1703 segs = skb_gso_segment(skb, features); 1704 if (IS_ERR(segs) || !segs) 1705 goto drop; 1706 1707 __skb_queue_head_init(&seg_list); 1708 1709 do { 1710 nskb = segs; 1711 segs = segs->next; 1712 nskb->next = NULL; 1713 __skb_queue_tail(&seg_list, nskb); 1714 } while (segs); 1715 1716 skb_queue_splice(&seg_list, list); 1717 dev_kfree_skb(skb); 1718 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1719 if (skb_checksum_help(skb) < 0) 1720 goto drop; 1721 1722 __skb_queue_head(list, skb); 1723 } else { 1724 struct net_device_stats *stats; 1725 1726 drop: 1727 stats = &tp->netdev->stats; 1728 stats->tx_dropped++; 1729 dev_kfree_skb(skb); 1730 } 1731 } 1732 1733 /* msdn_giant_send_check() 1734 * According to the document of microsoft, the TCP Pseudo Header excludes the 1735 * packet length for IPv6 TCP large packets. 1736 */ 1737 static int msdn_giant_send_check(struct sk_buff *skb) 1738 { 1739 const struct ipv6hdr *ipv6h; 1740 struct tcphdr *th; 1741 int ret; 1742 1743 ret = skb_cow_head(skb, 0); 1744 if (ret) 1745 return ret; 1746 1747 ipv6h = ipv6_hdr(skb); 1748 th = tcp_hdr(skb); 1749 1750 th->check = 0; 1751 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1752 1753 return ret; 1754 } 1755 1756 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 1757 { 1758 if (skb_vlan_tag_present(skb)) { 1759 u32 opts2; 1760 1761 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); 1762 desc->opts2 |= cpu_to_le32(opts2); 1763 } 1764 } 1765 1766 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 1767 { 1768 u32 opts2 = le32_to_cpu(desc->opts2); 1769 1770 if (opts2 & RX_VLAN_TAG) 1771 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1772 swab16(opts2 & 0xffff)); 1773 } 1774 1775 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1776 struct sk_buff *skb, u32 len, u32 transport_offset) 1777 { 1778 u32 mss = skb_shinfo(skb)->gso_size; 1779 u32 opts1, opts2 = 0; 1780 int ret = TX_CSUM_SUCCESS; 1781 1782 WARN_ON_ONCE(len > TX_LEN_MAX); 1783 1784 opts1 = len | TX_FS | TX_LS; 1785 1786 if (mss) { 1787 if (transport_offset > GTTCPHO_MAX) { 1788 netif_warn(tp, tx_err, tp->netdev, 1789 "Invalid transport offset 0x%x for TSO\n", 1790 transport_offset); 1791 ret = TX_CSUM_TSO; 1792 goto unavailable; 1793 } 1794 1795 switch (vlan_get_protocol(skb)) { 1796 case htons(ETH_P_IP): 1797 opts1 |= GTSENDV4; 1798 break; 1799 1800 case htons(ETH_P_IPV6): 1801 if (msdn_giant_send_check(skb)) { 1802 ret = TX_CSUM_TSO; 1803 goto unavailable; 1804 } 1805 opts1 |= GTSENDV6; 1806 break; 1807 1808 default: 1809 WARN_ON_ONCE(1); 1810 break; 1811 } 1812 1813 opts1 |= transport_offset << GTTCPHO_SHIFT; 1814 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1815 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1816 u8 ip_protocol; 1817 1818 if (transport_offset > TCPHO_MAX) { 1819 netif_warn(tp, tx_err, tp->netdev, 1820 "Invalid transport offset 0x%x\n", 1821 transport_offset); 1822 ret = TX_CSUM_NONE; 1823 goto unavailable; 1824 } 1825 1826 switch (vlan_get_protocol(skb)) { 1827 case htons(ETH_P_IP): 1828 opts2 |= IPV4_CS; 1829 ip_protocol = ip_hdr(skb)->protocol; 1830 break; 1831 1832 case htons(ETH_P_IPV6): 1833 opts2 |= IPV6_CS; 1834 ip_protocol = ipv6_hdr(skb)->nexthdr; 1835 break; 1836 1837 default: 1838 ip_protocol = IPPROTO_RAW; 1839 break; 1840 } 1841 1842 if (ip_protocol == IPPROTO_TCP) 1843 opts2 |= TCP_CS; 1844 else if (ip_protocol == IPPROTO_UDP) 1845 opts2 |= UDP_CS; 1846 else 1847 WARN_ON_ONCE(1); 1848 1849 opts2 |= transport_offset << TCPHO_SHIFT; 1850 } 1851 1852 desc->opts2 = cpu_to_le32(opts2); 1853 desc->opts1 = cpu_to_le32(opts1); 1854 1855 unavailable: 1856 return ret; 1857 } 1858 1859 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1860 { 1861 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1862 int remain, ret; 1863 u8 *tx_data; 1864 1865 __skb_queue_head_init(&skb_head); 1866 spin_lock(&tx_queue->lock); 1867 skb_queue_splice_init(tx_queue, &skb_head); 1868 spin_unlock(&tx_queue->lock); 1869 1870 tx_data = agg->head; 1871 agg->skb_num = 0; 1872 agg->skb_len = 0; 1873 remain = agg_buf_sz; 1874 1875 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1876 struct tx_desc *tx_desc; 1877 struct sk_buff *skb; 1878 unsigned int len; 1879 u32 offset; 1880 1881 skb = __skb_dequeue(&skb_head); 1882 if (!skb) 1883 break; 1884 1885 len = skb->len + sizeof(*tx_desc); 1886 1887 if (len > remain) { 1888 __skb_queue_head(&skb_head, skb); 1889 break; 1890 } 1891 1892 tx_data = tx_agg_align(tx_data); 1893 tx_desc = (struct tx_desc *)tx_data; 1894 1895 offset = (u32)skb_transport_offset(skb); 1896 1897 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1898 r8152_csum_workaround(tp, skb, &skb_head); 1899 continue; 1900 } 1901 1902 rtl_tx_vlan_tag(tx_desc, skb); 1903 1904 tx_data += sizeof(*tx_desc); 1905 1906 len = skb->len; 1907 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1908 struct net_device_stats *stats = &tp->netdev->stats; 1909 1910 stats->tx_dropped++; 1911 dev_kfree_skb_any(skb); 1912 tx_data -= sizeof(*tx_desc); 1913 continue; 1914 } 1915 1916 tx_data += len; 1917 agg->skb_len += len; 1918 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1; 1919 1920 dev_kfree_skb_any(skb); 1921 1922 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1923 1924 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags)) 1925 break; 1926 } 1927 1928 if (!skb_queue_empty(&skb_head)) { 1929 spin_lock(&tx_queue->lock); 1930 skb_queue_splice(&skb_head, tx_queue); 1931 spin_unlock(&tx_queue->lock); 1932 } 1933 1934 netif_tx_lock(tp->netdev); 1935 1936 if (netif_queue_stopped(tp->netdev) && 1937 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1938 netif_wake_queue(tp->netdev); 1939 1940 netif_tx_unlock(tp->netdev); 1941 1942 ret = usb_autopm_get_interface_async(tp->intf); 1943 if (ret < 0) 1944 goto out_tx_fill; 1945 1946 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1947 agg->head, (int)(tx_data - (u8 *)agg->head), 1948 (usb_complete_t)write_bulk_callback, agg); 1949 1950 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1951 if (ret < 0) 1952 usb_autopm_put_interface_async(tp->intf); 1953 1954 out_tx_fill: 1955 return ret; 1956 } 1957 1958 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1959 { 1960 u8 checksum = CHECKSUM_NONE; 1961 u32 opts2, opts3; 1962 1963 if (!(tp->netdev->features & NETIF_F_RXCSUM)) 1964 goto return_result; 1965 1966 opts2 = le32_to_cpu(rx_desc->opts2); 1967 opts3 = le32_to_cpu(rx_desc->opts3); 1968 1969 if (opts2 & RD_IPV4_CS) { 1970 if (opts3 & IPF) 1971 checksum = CHECKSUM_NONE; 1972 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1973 checksum = CHECKSUM_UNNECESSARY; 1974 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1975 checksum = CHECKSUM_UNNECESSARY; 1976 } else if (opts2 & RD_IPV6_CS) { 1977 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1978 checksum = CHECKSUM_UNNECESSARY; 1979 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1980 checksum = CHECKSUM_UNNECESSARY; 1981 } 1982 1983 return_result: 1984 return checksum; 1985 } 1986 1987 static inline bool rx_count_exceed(struct r8152 *tp) 1988 { 1989 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX; 1990 } 1991 1992 static inline int agg_offset(struct rx_agg *agg, void *addr) 1993 { 1994 return (int)(addr - agg->buffer); 1995 } 1996 1997 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags) 1998 { 1999 struct rx_agg *agg, *agg_next, *agg_free = NULL; 2000 unsigned long flags; 2001 2002 spin_lock_irqsave(&tp->rx_lock, flags); 2003 2004 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) { 2005 if (page_count(agg->page) == 1) { 2006 if (!agg_free) { 2007 list_del_init(&agg->list); 2008 agg_free = agg; 2009 continue; 2010 } 2011 if (rx_count_exceed(tp)) { 2012 list_del_init(&agg->list); 2013 free_rx_agg(tp, agg); 2014 } 2015 break; 2016 } 2017 } 2018 2019 spin_unlock_irqrestore(&tp->rx_lock, flags); 2020 2021 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending) 2022 agg_free = alloc_rx_agg(tp, mflags); 2023 2024 return agg_free; 2025 } 2026 2027 static int rx_bottom(struct r8152 *tp, int budget) 2028 { 2029 unsigned long flags; 2030 struct list_head *cursor, *next, rx_queue; 2031 int ret = 0, work_done = 0; 2032 struct napi_struct *napi = &tp->napi; 2033 2034 if (!skb_queue_empty(&tp->rx_queue)) { 2035 while (work_done < budget) { 2036 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); 2037 struct net_device *netdev = tp->netdev; 2038 struct net_device_stats *stats = &netdev->stats; 2039 unsigned int pkt_len; 2040 2041 if (!skb) 2042 break; 2043 2044 pkt_len = skb->len; 2045 napi_gro_receive(napi, skb); 2046 work_done++; 2047 stats->rx_packets++; 2048 stats->rx_bytes += pkt_len; 2049 } 2050 } 2051 2052 if (list_empty(&tp->rx_done)) 2053 goto out1; 2054 2055 INIT_LIST_HEAD(&rx_queue); 2056 spin_lock_irqsave(&tp->rx_lock, flags); 2057 list_splice_init(&tp->rx_done, &rx_queue); 2058 spin_unlock_irqrestore(&tp->rx_lock, flags); 2059 2060 list_for_each_safe(cursor, next, &rx_queue) { 2061 struct rx_desc *rx_desc; 2062 struct rx_agg *agg, *agg_free; 2063 int len_used = 0; 2064 struct urb *urb; 2065 u8 *rx_data; 2066 2067 list_del_init(cursor); 2068 2069 agg = list_entry(cursor, struct rx_agg, list); 2070 urb = agg->urb; 2071 if (urb->actual_length < ETH_ZLEN) 2072 goto submit; 2073 2074 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC); 2075 2076 rx_desc = agg->buffer; 2077 rx_data = agg->buffer; 2078 len_used += sizeof(struct rx_desc); 2079 2080 while (urb->actual_length > len_used) { 2081 struct net_device *netdev = tp->netdev; 2082 struct net_device_stats *stats = &netdev->stats; 2083 unsigned int pkt_len, rx_frag_head_sz; 2084 struct sk_buff *skb; 2085 2086 /* limite the skb numbers for rx_queue */ 2087 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000)) 2088 break; 2089 2090 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 2091 if (pkt_len < ETH_ZLEN) 2092 break; 2093 2094 len_used += pkt_len; 2095 if (urb->actual_length < len_used) 2096 break; 2097 2098 pkt_len -= ETH_FCS_LEN; 2099 rx_data += sizeof(struct rx_desc); 2100 2101 if (!agg_free || tp->rx_copybreak > pkt_len) 2102 rx_frag_head_sz = pkt_len; 2103 else 2104 rx_frag_head_sz = tp->rx_copybreak; 2105 2106 skb = napi_alloc_skb(napi, rx_frag_head_sz); 2107 if (!skb) { 2108 stats->rx_dropped++; 2109 goto find_next_rx; 2110 } 2111 2112 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 2113 memcpy(skb->data, rx_data, rx_frag_head_sz); 2114 skb_put(skb, rx_frag_head_sz); 2115 pkt_len -= rx_frag_head_sz; 2116 rx_data += rx_frag_head_sz; 2117 if (pkt_len) { 2118 skb_add_rx_frag(skb, 0, agg->page, 2119 agg_offset(agg, rx_data), 2120 pkt_len, 2121 SKB_DATA_ALIGN(pkt_len)); 2122 get_page(agg->page); 2123 } 2124 2125 skb->protocol = eth_type_trans(skb, netdev); 2126 rtl_rx_vlan_tag(rx_desc, skb); 2127 if (work_done < budget) { 2128 work_done++; 2129 stats->rx_packets++; 2130 stats->rx_bytes += skb->len; 2131 napi_gro_receive(napi, skb); 2132 } else { 2133 __skb_queue_tail(&tp->rx_queue, skb); 2134 } 2135 2136 find_next_rx: 2137 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN); 2138 rx_desc = (struct rx_desc *)rx_data; 2139 len_used = agg_offset(agg, rx_data); 2140 len_used += sizeof(struct rx_desc); 2141 } 2142 2143 WARN_ON(!agg_free && page_count(agg->page) > 1); 2144 2145 if (agg_free) { 2146 spin_lock_irqsave(&tp->rx_lock, flags); 2147 if (page_count(agg->page) == 1) { 2148 list_add(&agg_free->list, &tp->rx_used); 2149 } else { 2150 list_add_tail(&agg->list, &tp->rx_used); 2151 agg = agg_free; 2152 urb = agg->urb; 2153 } 2154 spin_unlock_irqrestore(&tp->rx_lock, flags); 2155 } 2156 2157 submit: 2158 if (!ret) { 2159 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 2160 } else { 2161 urb->actual_length = 0; 2162 list_add_tail(&agg->list, next); 2163 } 2164 } 2165 2166 if (!list_empty(&rx_queue)) { 2167 spin_lock_irqsave(&tp->rx_lock, flags); 2168 list_splice_tail(&rx_queue, &tp->rx_done); 2169 spin_unlock_irqrestore(&tp->rx_lock, flags); 2170 } 2171 2172 out1: 2173 return work_done; 2174 } 2175 2176 static void tx_bottom(struct r8152 *tp) 2177 { 2178 int res; 2179 2180 do { 2181 struct tx_agg *agg; 2182 2183 if (skb_queue_empty(&tp->tx_queue)) 2184 break; 2185 2186 agg = r8152_get_tx_agg(tp); 2187 if (!agg) 2188 break; 2189 2190 res = r8152_tx_agg_fill(tp, agg); 2191 if (res) { 2192 struct net_device *netdev = tp->netdev; 2193 2194 if (res == -ENODEV) { 2195 rtl_set_unplug(tp); 2196 netif_device_detach(netdev); 2197 } else { 2198 struct net_device_stats *stats = &netdev->stats; 2199 unsigned long flags; 2200 2201 netif_warn(tp, tx_err, netdev, 2202 "failed tx_urb %d\n", res); 2203 stats->tx_dropped += agg->skb_num; 2204 2205 spin_lock_irqsave(&tp->tx_lock, flags); 2206 list_add_tail(&agg->list, &tp->tx_free); 2207 spin_unlock_irqrestore(&tp->tx_lock, flags); 2208 } 2209 } 2210 } while (res == 0); 2211 } 2212 2213 static void bottom_half(unsigned long data) 2214 { 2215 struct r8152 *tp; 2216 2217 tp = (struct r8152 *)data; 2218 2219 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2220 return; 2221 2222 if (!test_bit(WORK_ENABLE, &tp->flags)) 2223 return; 2224 2225 /* When link down, the driver would cancel all bulks. */ 2226 /* This avoid the re-submitting bulk */ 2227 if (!netif_carrier_ok(tp->netdev)) 2228 return; 2229 2230 clear_bit(SCHEDULE_TASKLET, &tp->flags); 2231 2232 tx_bottom(tp); 2233 } 2234 2235 static int r8152_poll(struct napi_struct *napi, int budget) 2236 { 2237 struct r8152 *tp = container_of(napi, struct r8152, napi); 2238 int work_done; 2239 2240 work_done = rx_bottom(tp, budget); 2241 2242 if (work_done < budget) { 2243 if (!napi_complete_done(napi, work_done)) 2244 goto out; 2245 if (!list_empty(&tp->rx_done)) 2246 napi_schedule(napi); 2247 } 2248 2249 out: 2250 return work_done; 2251 } 2252 2253 static 2254 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 2255 { 2256 int ret; 2257 2258 /* The rx would be stopped, so skip submitting */ 2259 if (test_bit(RTL8152_UNPLUG, &tp->flags) || 2260 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) 2261 return 0; 2262 2263 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 2264 agg->buffer, tp->rx_buf_sz, 2265 (usb_complete_t)read_bulk_callback, agg); 2266 2267 ret = usb_submit_urb(agg->urb, mem_flags); 2268 if (ret == -ENODEV) { 2269 rtl_set_unplug(tp); 2270 netif_device_detach(tp->netdev); 2271 } else if (ret) { 2272 struct urb *urb = agg->urb; 2273 unsigned long flags; 2274 2275 urb->actual_length = 0; 2276 spin_lock_irqsave(&tp->rx_lock, flags); 2277 list_add_tail(&agg->list, &tp->rx_done); 2278 spin_unlock_irqrestore(&tp->rx_lock, flags); 2279 2280 netif_err(tp, rx_err, tp->netdev, 2281 "Couldn't submit rx[%p], ret = %d\n", agg, ret); 2282 2283 napi_schedule(&tp->napi); 2284 } 2285 2286 return ret; 2287 } 2288 2289 static void rtl_drop_queued_tx(struct r8152 *tp) 2290 { 2291 struct net_device_stats *stats = &tp->netdev->stats; 2292 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 2293 struct sk_buff *skb; 2294 2295 if (skb_queue_empty(tx_queue)) 2296 return; 2297 2298 __skb_queue_head_init(&skb_head); 2299 spin_lock_bh(&tx_queue->lock); 2300 skb_queue_splice_init(tx_queue, &skb_head); 2301 spin_unlock_bh(&tx_queue->lock); 2302 2303 while ((skb = __skb_dequeue(&skb_head))) { 2304 dev_kfree_skb(skb); 2305 stats->tx_dropped++; 2306 } 2307 } 2308 2309 static void rtl8152_tx_timeout(struct net_device *netdev) 2310 { 2311 struct r8152 *tp = netdev_priv(netdev); 2312 2313 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 2314 2315 usb_queue_reset_device(tp->intf); 2316 } 2317 2318 static void rtl8152_set_rx_mode(struct net_device *netdev) 2319 { 2320 struct r8152 *tp = netdev_priv(netdev); 2321 2322 if (netif_carrier_ok(netdev)) { 2323 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2324 schedule_delayed_work(&tp->schedule, 0); 2325 } 2326 } 2327 2328 static void _rtl8152_set_rx_mode(struct net_device *netdev) 2329 { 2330 struct r8152 *tp = netdev_priv(netdev); 2331 u32 mc_filter[2]; /* Multicast hash filter */ 2332 __le32 tmp[2]; 2333 u32 ocp_data; 2334 2335 netif_stop_queue(netdev); 2336 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2337 ocp_data &= ~RCR_ACPT_ALL; 2338 ocp_data |= RCR_AB | RCR_APM; 2339 2340 if (netdev->flags & IFF_PROMISC) { 2341 /* Unconditionally log net taps. */ 2342 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 2343 ocp_data |= RCR_AM | RCR_AAP; 2344 mc_filter[1] = 0xffffffff; 2345 mc_filter[0] = 0xffffffff; 2346 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 2347 (netdev->flags & IFF_ALLMULTI)) { 2348 /* Too many to filter perfectly -- accept all multicasts. */ 2349 ocp_data |= RCR_AM; 2350 mc_filter[1] = 0xffffffff; 2351 mc_filter[0] = 0xffffffff; 2352 } else { 2353 struct netdev_hw_addr *ha; 2354 2355 mc_filter[1] = 0; 2356 mc_filter[0] = 0; 2357 netdev_for_each_mc_addr(ha, netdev) { 2358 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2359 2360 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2361 ocp_data |= RCR_AM; 2362 } 2363 } 2364 2365 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 2366 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 2367 2368 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 2369 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2370 netif_wake_queue(netdev); 2371 } 2372 2373 static netdev_features_t 2374 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 2375 netdev_features_t features) 2376 { 2377 u32 mss = skb_shinfo(skb)->gso_size; 2378 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 2379 int offset = skb_transport_offset(skb); 2380 2381 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) 2382 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2383 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 2384 features &= ~NETIF_F_GSO_MASK; 2385 2386 return features; 2387 } 2388 2389 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 2390 struct net_device *netdev) 2391 { 2392 struct r8152 *tp = netdev_priv(netdev); 2393 2394 skb_tx_timestamp(skb); 2395 2396 skb_queue_tail(&tp->tx_queue, skb); 2397 2398 if (!list_empty(&tp->tx_free)) { 2399 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2400 set_bit(SCHEDULE_TASKLET, &tp->flags); 2401 schedule_delayed_work(&tp->schedule, 0); 2402 } else { 2403 usb_mark_last_busy(tp->udev); 2404 tasklet_schedule(&tp->tx_tl); 2405 } 2406 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 2407 netif_stop_queue(netdev); 2408 } 2409 2410 return NETDEV_TX_OK; 2411 } 2412 2413 static void r8152b_reset_packet_filter(struct r8152 *tp) 2414 { 2415 u32 ocp_data; 2416 2417 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 2418 ocp_data &= ~FMC_FCR_MCU_EN; 2419 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2420 ocp_data |= FMC_FCR_MCU_EN; 2421 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2422 } 2423 2424 static void rtl8152_nic_reset(struct r8152 *tp) 2425 { 2426 int i; 2427 2428 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 2429 2430 for (i = 0; i < 1000; i++) { 2431 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 2432 break; 2433 usleep_range(100, 400); 2434 } 2435 } 2436 2437 static void set_tx_qlen(struct r8152 *tp) 2438 { 2439 struct net_device *netdev = tp->netdev; 2440 2441 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN + 2442 sizeof(struct tx_desc)); 2443 } 2444 2445 static inline u8 rtl8152_get_speed(struct r8152 *tp) 2446 { 2447 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 2448 } 2449 2450 static void rtl_set_eee_plus(struct r8152 *tp) 2451 { 2452 u32 ocp_data; 2453 u8 speed; 2454 2455 speed = rtl8152_get_speed(tp); 2456 if (speed & _10bps) { 2457 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2458 ocp_data |= EEEP_CR_EEEP_TX; 2459 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2460 } else { 2461 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2462 ocp_data &= ~EEEP_CR_EEEP_TX; 2463 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2464 } 2465 } 2466 2467 static void rxdy_gated_en(struct r8152 *tp, bool enable) 2468 { 2469 u32 ocp_data; 2470 2471 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 2472 if (enable) 2473 ocp_data |= RXDY_GATED_EN; 2474 else 2475 ocp_data &= ~RXDY_GATED_EN; 2476 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 2477 } 2478 2479 static int rtl_start_rx(struct r8152 *tp) 2480 { 2481 struct rx_agg *agg, *agg_next; 2482 struct list_head tmp_list; 2483 unsigned long flags; 2484 int ret = 0, i = 0; 2485 2486 INIT_LIST_HEAD(&tmp_list); 2487 2488 spin_lock_irqsave(&tp->rx_lock, flags); 2489 2490 INIT_LIST_HEAD(&tp->rx_done); 2491 INIT_LIST_HEAD(&tp->rx_used); 2492 2493 list_splice_init(&tp->rx_info, &tmp_list); 2494 2495 spin_unlock_irqrestore(&tp->rx_lock, flags); 2496 2497 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) { 2498 INIT_LIST_HEAD(&agg->list); 2499 2500 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */ 2501 if (++i > RTL8152_MAX_RX) { 2502 spin_lock_irqsave(&tp->rx_lock, flags); 2503 list_add_tail(&agg->list, &tp->rx_used); 2504 spin_unlock_irqrestore(&tp->rx_lock, flags); 2505 } else if (unlikely(ret < 0)) { 2506 spin_lock_irqsave(&tp->rx_lock, flags); 2507 list_add_tail(&agg->list, &tp->rx_done); 2508 spin_unlock_irqrestore(&tp->rx_lock, flags); 2509 } else { 2510 ret = r8152_submit_rx(tp, agg, GFP_KERNEL); 2511 } 2512 } 2513 2514 spin_lock_irqsave(&tp->rx_lock, flags); 2515 WARN_ON(!list_empty(&tp->rx_info)); 2516 list_splice(&tmp_list, &tp->rx_info); 2517 spin_unlock_irqrestore(&tp->rx_lock, flags); 2518 2519 return ret; 2520 } 2521 2522 static int rtl_stop_rx(struct r8152 *tp) 2523 { 2524 struct rx_agg *agg, *agg_next; 2525 struct list_head tmp_list; 2526 unsigned long flags; 2527 2528 INIT_LIST_HEAD(&tmp_list); 2529 2530 /* The usb_kill_urb() couldn't be used in atomic. 2531 * Therefore, move the list of rx_info to a tmp one. 2532 * Then, list_for_each_entry_safe could be used without 2533 * spin lock. 2534 */ 2535 2536 spin_lock_irqsave(&tp->rx_lock, flags); 2537 list_splice_init(&tp->rx_info, &tmp_list); 2538 spin_unlock_irqrestore(&tp->rx_lock, flags); 2539 2540 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) { 2541 /* At least RTL8152_MAX_RX rx_agg have the page_count being 2542 * equal to 1, so the other ones could be freed safely. 2543 */ 2544 if (page_count(agg->page) > 1) 2545 free_rx_agg(tp, agg); 2546 else 2547 usb_kill_urb(agg->urb); 2548 } 2549 2550 /* Move back the list of temp to the rx_info */ 2551 spin_lock_irqsave(&tp->rx_lock, flags); 2552 WARN_ON(!list_empty(&tp->rx_info)); 2553 list_splice(&tmp_list, &tp->rx_info); 2554 spin_unlock_irqrestore(&tp->rx_lock, flags); 2555 2556 while (!skb_queue_empty(&tp->rx_queue)) 2557 dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); 2558 2559 return 0; 2560 } 2561 2562 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) 2563 { 2564 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, 2565 OWN_UPDATE | OWN_CLEAR); 2566 } 2567 2568 static int rtl_enable(struct r8152 *tp) 2569 { 2570 u32 ocp_data; 2571 2572 r8152b_reset_packet_filter(tp); 2573 2574 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2575 ocp_data |= CR_RE | CR_TE; 2576 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2577 2578 switch (tp->version) { 2579 case RTL_VER_08: 2580 case RTL_VER_09: 2581 r8153b_rx_agg_chg_indicate(tp); 2582 break; 2583 default: 2584 break; 2585 } 2586 2587 rxdy_gated_en(tp, false); 2588 2589 return 0; 2590 } 2591 2592 static int rtl8152_enable(struct r8152 *tp) 2593 { 2594 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2595 return -ENODEV; 2596 2597 set_tx_qlen(tp); 2598 rtl_set_eee_plus(tp); 2599 2600 return rtl_enable(tp); 2601 } 2602 2603 static void r8153_set_rx_early_timeout(struct r8152 *tp) 2604 { 2605 u32 ocp_data = tp->coalesce / 8; 2606 2607 switch (tp->version) { 2608 case RTL_VER_03: 2609 case RTL_VER_04: 2610 case RTL_VER_05: 2611 case RTL_VER_06: 2612 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2613 ocp_data); 2614 break; 2615 2616 case RTL_VER_08: 2617 case RTL_VER_09: 2618 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout 2619 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns. 2620 */ 2621 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 2622 128 / 8); 2623 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, 2624 ocp_data); 2625 break; 2626 2627 default: 2628 break; 2629 } 2630 } 2631 2632 static void r8153_set_rx_early_size(struct r8152 *tp) 2633 { 2634 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu); 2635 2636 switch (tp->version) { 2637 case RTL_VER_03: 2638 case RTL_VER_04: 2639 case RTL_VER_05: 2640 case RTL_VER_06: 2641 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2642 ocp_data / 4); 2643 break; 2644 case RTL_VER_08: 2645 case RTL_VER_09: 2646 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 2647 ocp_data / 8); 2648 break; 2649 default: 2650 WARN_ON_ONCE(1); 2651 break; 2652 } 2653 } 2654 2655 static int rtl8153_enable(struct r8152 *tp) 2656 { 2657 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2658 return -ENODEV; 2659 2660 set_tx_qlen(tp); 2661 rtl_set_eee_plus(tp); 2662 r8153_set_rx_early_timeout(tp); 2663 r8153_set_rx_early_size(tp); 2664 2665 return rtl_enable(tp); 2666 } 2667 2668 static void rtl_disable(struct r8152 *tp) 2669 { 2670 u32 ocp_data; 2671 int i; 2672 2673 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2674 rtl_drop_queued_tx(tp); 2675 return; 2676 } 2677 2678 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2679 ocp_data &= ~RCR_ACPT_ALL; 2680 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2681 2682 rtl_drop_queued_tx(tp); 2683 2684 for (i = 0; i < RTL8152_MAX_TX; i++) 2685 usb_kill_urb(tp->tx_info[i].urb); 2686 2687 rxdy_gated_en(tp, true); 2688 2689 for (i = 0; i < 1000; i++) { 2690 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2691 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2692 break; 2693 usleep_range(1000, 2000); 2694 } 2695 2696 for (i = 0; i < 1000; i++) { 2697 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2698 break; 2699 usleep_range(1000, 2000); 2700 } 2701 2702 rtl_stop_rx(tp); 2703 2704 rtl8152_nic_reset(tp); 2705 } 2706 2707 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2708 { 2709 u32 ocp_data; 2710 2711 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2712 if (enable) 2713 ocp_data |= POWER_CUT; 2714 else 2715 ocp_data &= ~POWER_CUT; 2716 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2717 2718 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2719 ocp_data &= ~RESUME_INDICATE; 2720 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2721 } 2722 2723 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 2724 { 2725 u32 ocp_data; 2726 2727 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2728 if (enable) 2729 ocp_data |= CPCR_RX_VLAN; 2730 else 2731 ocp_data &= ~CPCR_RX_VLAN; 2732 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2733 } 2734 2735 static int rtl8152_set_features(struct net_device *dev, 2736 netdev_features_t features) 2737 { 2738 netdev_features_t changed = features ^ dev->features; 2739 struct r8152 *tp = netdev_priv(dev); 2740 int ret; 2741 2742 ret = usb_autopm_get_interface(tp->intf); 2743 if (ret < 0) 2744 goto out; 2745 2746 mutex_lock(&tp->control); 2747 2748 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 2749 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2750 rtl_rx_vlan_en(tp, true); 2751 else 2752 rtl_rx_vlan_en(tp, false); 2753 } 2754 2755 mutex_unlock(&tp->control); 2756 2757 usb_autopm_put_interface(tp->intf); 2758 2759 out: 2760 return ret; 2761 } 2762 2763 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2764 2765 static u32 __rtl_get_wol(struct r8152 *tp) 2766 { 2767 u32 ocp_data; 2768 u32 wolopts = 0; 2769 2770 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2771 if (ocp_data & LINK_ON_WAKE_EN) 2772 wolopts |= WAKE_PHY; 2773 2774 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2775 if (ocp_data & UWF_EN) 2776 wolopts |= WAKE_UCAST; 2777 if (ocp_data & BWF_EN) 2778 wolopts |= WAKE_BCAST; 2779 if (ocp_data & MWF_EN) 2780 wolopts |= WAKE_MCAST; 2781 2782 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2783 if (ocp_data & MAGIC_EN) 2784 wolopts |= WAKE_MAGIC; 2785 2786 return wolopts; 2787 } 2788 2789 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2790 { 2791 u32 ocp_data; 2792 2793 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2794 2795 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2796 ocp_data &= ~LINK_ON_WAKE_EN; 2797 if (wolopts & WAKE_PHY) 2798 ocp_data |= LINK_ON_WAKE_EN; 2799 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2800 2801 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2802 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); 2803 if (wolopts & WAKE_UCAST) 2804 ocp_data |= UWF_EN; 2805 if (wolopts & WAKE_BCAST) 2806 ocp_data |= BWF_EN; 2807 if (wolopts & WAKE_MCAST) 2808 ocp_data |= MWF_EN; 2809 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2810 2811 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2812 2813 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2814 ocp_data &= ~MAGIC_EN; 2815 if (wolopts & WAKE_MAGIC) 2816 ocp_data |= MAGIC_EN; 2817 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2818 2819 if (wolopts & WAKE_ANY) 2820 device_set_wakeup_enable(&tp->udev->dev, true); 2821 else 2822 device_set_wakeup_enable(&tp->udev->dev, false); 2823 } 2824 2825 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable) 2826 { 2827 /* MAC clock speed down */ 2828 if (enable) { 2829 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 2830 ALDPS_SPDWN_RATIO); 2831 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 2832 EEE_SPDWN_RATIO); 2833 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 2834 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | 2835 U1U2_SPDWN_EN | L1_SPDWN_EN); 2836 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 2837 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | 2838 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN | 2839 TP1000_SPDWN_EN); 2840 } else { 2841 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); 2842 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); 2843 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); 2844 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); 2845 } 2846 } 2847 2848 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2849 { 2850 u8 u1u2[8]; 2851 2852 if (enable) 2853 memset(u1u2, 0xff, sizeof(u1u2)); 2854 else 2855 memset(u1u2, 0x00, sizeof(u1u2)); 2856 2857 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2858 } 2859 2860 static void r8153b_u1u2en(struct r8152 *tp, bool enable) 2861 { 2862 u32 ocp_data; 2863 2864 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); 2865 if (enable) 2866 ocp_data |= LPM_U1U2_EN; 2867 else 2868 ocp_data &= ~LPM_U1U2_EN; 2869 2870 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); 2871 } 2872 2873 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2874 { 2875 u32 ocp_data; 2876 2877 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2878 if (enable) 2879 ocp_data |= U2P3_ENABLE; 2880 else 2881 ocp_data &= ~U2P3_ENABLE; 2882 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2883 } 2884 2885 static void r8153b_ups_flags(struct r8152 *tp) 2886 { 2887 u32 ups_flags = 0; 2888 2889 if (tp->ups_info.green) 2890 ups_flags |= UPS_FLAGS_EN_GREEN; 2891 2892 if (tp->ups_info.aldps) 2893 ups_flags |= UPS_FLAGS_EN_ALDPS; 2894 2895 if (tp->ups_info.eee) 2896 ups_flags |= UPS_FLAGS_EN_EEE; 2897 2898 if (tp->ups_info.flow_control) 2899 ups_flags |= UPS_FLAGS_EN_FLOW_CTR; 2900 2901 if (tp->ups_info.eee_ckdiv) 2902 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV; 2903 2904 if (tp->ups_info.eee_cmod_lv) 2905 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN; 2906 2907 if (tp->ups_info._10m_ckdiv) 2908 ups_flags |= UPS_FLAGS_EN_10M_CKDIV; 2909 2910 if (tp->ups_info.eee_plloff_100) 2911 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100; 2912 2913 if (tp->ups_info.eee_plloff_giga) 2914 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA; 2915 2916 if (tp->ups_info._250m_ckdiv) 2917 ups_flags |= UPS_FLAGS_250M_CKDIV; 2918 2919 if (tp->ups_info.ctap_short_off) 2920 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS; 2921 2922 switch (tp->ups_info.speed_duplex) { 2923 case NWAY_10M_HALF: 2924 ups_flags |= ups_flags_speed(1); 2925 break; 2926 case NWAY_10M_FULL: 2927 ups_flags |= ups_flags_speed(2); 2928 break; 2929 case NWAY_100M_HALF: 2930 ups_flags |= ups_flags_speed(3); 2931 break; 2932 case NWAY_100M_FULL: 2933 ups_flags |= ups_flags_speed(4); 2934 break; 2935 case NWAY_1000M_FULL: 2936 ups_flags |= ups_flags_speed(5); 2937 break; 2938 case FORCE_10M_HALF: 2939 ups_flags |= ups_flags_speed(6); 2940 break; 2941 case FORCE_10M_FULL: 2942 ups_flags |= ups_flags_speed(7); 2943 break; 2944 case FORCE_100M_HALF: 2945 ups_flags |= ups_flags_speed(8); 2946 break; 2947 case FORCE_100M_FULL: 2948 ups_flags |= ups_flags_speed(9); 2949 break; 2950 default: 2951 break; 2952 } 2953 2954 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags); 2955 } 2956 2957 static void r8153b_green_en(struct r8152 *tp, bool enable) 2958 { 2959 u16 data; 2960 2961 if (enable) { 2962 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ 2963 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ 2964 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ 2965 } else { 2966 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ 2967 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ 2968 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ 2969 } 2970 2971 data = sram_read(tp, SRAM_GREEN_CFG); 2972 data |= GREEN_ETH_EN; 2973 sram_write(tp, SRAM_GREEN_CFG, data); 2974 2975 tp->ups_info.green = enable; 2976 } 2977 2978 static u16 r8153_phy_status(struct r8152 *tp, u16 desired) 2979 { 2980 u16 data; 2981 int i; 2982 2983 for (i = 0; i < 500; i++) { 2984 data = ocp_reg_read(tp, OCP_PHY_STATUS); 2985 data &= PHY_STAT_MASK; 2986 if (desired) { 2987 if (data == desired) 2988 break; 2989 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN || 2990 data == PHY_STAT_EXT_INIT) { 2991 break; 2992 } 2993 2994 msleep(20); 2995 } 2996 2997 return data; 2998 } 2999 3000 static void r8153b_ups_en(struct r8152 *tp, bool enable) 3001 { 3002 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); 3003 3004 if (enable) { 3005 r8153b_ups_flags(tp); 3006 3007 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; 3008 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3009 3010 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 3011 ocp_data |= BIT(0); 3012 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 3013 } else { 3014 u16 data; 3015 3016 ocp_data &= ~(UPS_EN | USP_PREWAKE); 3017 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3018 3019 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); 3020 ocp_data &= ~BIT(0); 3021 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); 3022 3023 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 3024 ocp_data &= ~PCUT_STATUS; 3025 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 3026 3027 data = r8153_phy_status(tp, 0); 3028 3029 switch (data) { 3030 case PHY_STAT_PWRDN: 3031 case PHY_STAT_EXT_INIT: 3032 r8153b_green_en(tp, 3033 test_bit(GREEN_ETHERNET, &tp->flags)); 3034 3035 data = r8152_mdio_read(tp, MII_BMCR); 3036 data &= ~BMCR_PDOWN; 3037 data |= BMCR_RESET; 3038 r8152_mdio_write(tp, MII_BMCR, data); 3039 3040 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 3041 /* fall through */ 3042 3043 default: 3044 if (data != PHY_STAT_LAN_ON) 3045 netif_warn(tp, link, tp->netdev, 3046 "PHY not ready"); 3047 break; 3048 } 3049 } 3050 } 3051 3052 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 3053 { 3054 u32 ocp_data; 3055 3056 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 3057 if (enable) 3058 ocp_data |= PWR_EN | PHASE2_EN; 3059 else 3060 ocp_data &= ~(PWR_EN | PHASE2_EN); 3061 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3062 3063 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 3064 ocp_data &= ~PCUT_STATUS; 3065 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 3066 } 3067 3068 static void r8153b_power_cut_en(struct r8152 *tp, bool enable) 3069 { 3070 u32 ocp_data; 3071 3072 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 3073 if (enable) 3074 ocp_data |= PWR_EN | PHASE2_EN; 3075 else 3076 ocp_data &= ~PWR_EN; 3077 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3078 3079 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 3080 ocp_data &= ~PCUT_STATUS; 3081 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 3082 } 3083 3084 static void r8153_queue_wake(struct r8152 *tp, bool enable) 3085 { 3086 u32 ocp_data; 3087 3088 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG); 3089 if (enable) 3090 ocp_data |= UPCOMING_RUNTIME_D3; 3091 else 3092 ocp_data &= ~UPCOMING_RUNTIME_D3; 3093 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data); 3094 3095 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG); 3096 ocp_data &= ~LINK_CHG_EVENT; 3097 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data); 3098 3099 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); 3100 ocp_data &= ~LINK_CHANGE_FLAG; 3101 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); 3102 } 3103 3104 static bool rtl_can_wakeup(struct r8152 *tp) 3105 { 3106 struct usb_device *udev = tp->udev; 3107 3108 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); 3109 } 3110 3111 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 3112 { 3113 if (enable) { 3114 u32 ocp_data; 3115 3116 __rtl_set_wol(tp, WAKE_ANY); 3117 3118 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 3119 3120 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 3121 ocp_data |= LINK_OFF_WAKE_EN; 3122 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 3123 3124 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3125 } else { 3126 u32 ocp_data; 3127 3128 __rtl_set_wol(tp, tp->saved_wolopts); 3129 3130 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 3131 3132 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 3133 ocp_data &= ~LINK_OFF_WAKE_EN; 3134 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 3135 3136 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3137 } 3138 } 3139 3140 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) 3141 { 3142 if (enable) { 3143 r8153_u1u2en(tp, false); 3144 r8153_u2p3en(tp, false); 3145 r8153_mac_clk_spd(tp, true); 3146 rtl_runtime_suspend_enable(tp, true); 3147 } else { 3148 rtl_runtime_suspend_enable(tp, false); 3149 r8153_mac_clk_spd(tp, false); 3150 3151 switch (tp->version) { 3152 case RTL_VER_03: 3153 case RTL_VER_04: 3154 break; 3155 case RTL_VER_05: 3156 case RTL_VER_06: 3157 default: 3158 r8153_u2p3en(tp, true); 3159 break; 3160 } 3161 3162 r8153_u1u2en(tp, true); 3163 } 3164 } 3165 3166 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable) 3167 { 3168 if (enable) { 3169 r8153_queue_wake(tp, true); 3170 r8153b_u1u2en(tp, false); 3171 r8153_u2p3en(tp, false); 3172 rtl_runtime_suspend_enable(tp, true); 3173 r8153b_ups_en(tp, true); 3174 } else { 3175 r8153b_ups_en(tp, false); 3176 r8153_queue_wake(tp, false); 3177 rtl_runtime_suspend_enable(tp, false); 3178 r8153_u2p3en(tp, true); 3179 r8153b_u1u2en(tp, true); 3180 } 3181 } 3182 3183 static void r8153_teredo_off(struct r8152 *tp) 3184 { 3185 u32 ocp_data; 3186 3187 switch (tp->version) { 3188 case RTL_VER_01: 3189 case RTL_VER_02: 3190 case RTL_VER_03: 3191 case RTL_VER_04: 3192 case RTL_VER_05: 3193 case RTL_VER_06: 3194 case RTL_VER_07: 3195 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 3196 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | 3197 OOB_TEREDO_EN); 3198 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 3199 break; 3200 3201 case RTL_VER_08: 3202 case RTL_VER_09: 3203 /* The bit 0 ~ 7 are relative with teredo settings. They are 3204 * W1C (write 1 to clear), so set all 1 to disable it. 3205 */ 3206 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); 3207 break; 3208 3209 default: 3210 break; 3211 } 3212 3213 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 3214 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 3215 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 3216 } 3217 3218 static void rtl_reset_bmu(struct r8152 *tp) 3219 { 3220 u32 ocp_data; 3221 3222 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); 3223 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 3224 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 3225 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 3226 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 3227 } 3228 3229 static void r8152_aldps_en(struct r8152 *tp, bool enable) 3230 { 3231 if (enable) { 3232 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 3233 LINKENA | DIS_SDSAVE); 3234 } else { 3235 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | 3236 DIS_SDSAVE); 3237 msleep(20); 3238 } 3239 } 3240 3241 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 3242 { 3243 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 3244 ocp_reg_write(tp, OCP_EEE_DATA, reg); 3245 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 3246 } 3247 3248 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 3249 { 3250 u16 data; 3251 3252 r8152_mmd_indirect(tp, dev, reg); 3253 data = ocp_reg_read(tp, OCP_EEE_DATA); 3254 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3255 3256 return data; 3257 } 3258 3259 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 3260 { 3261 r8152_mmd_indirect(tp, dev, reg); 3262 ocp_reg_write(tp, OCP_EEE_DATA, data); 3263 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3264 } 3265 3266 static void r8152_eee_en(struct r8152 *tp, bool enable) 3267 { 3268 u16 config1, config2, config3; 3269 u32 ocp_data; 3270 3271 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3272 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 3273 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 3274 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 3275 3276 if (enable) { 3277 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3278 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 3279 config1 |= sd_rise_time(1); 3280 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 3281 config3 |= fast_snr(42); 3282 } else { 3283 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3284 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 3285 RX_QUIET_EN); 3286 config1 |= sd_rise_time(7); 3287 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 3288 config3 |= fast_snr(511); 3289 } 3290 3291 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3292 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 3293 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 3294 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 3295 } 3296 3297 static void r8153_eee_en(struct r8152 *tp, bool enable) 3298 { 3299 u32 ocp_data; 3300 u16 config; 3301 3302 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3303 config = ocp_reg_read(tp, OCP_EEE_CFG); 3304 3305 if (enable) { 3306 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3307 config |= EEE10_EN; 3308 } else { 3309 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3310 config &= ~EEE10_EN; 3311 } 3312 3313 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3314 ocp_reg_write(tp, OCP_EEE_CFG, config); 3315 3316 tp->ups_info.eee = enable; 3317 } 3318 3319 static void rtl_eee_enable(struct r8152 *tp, bool enable) 3320 { 3321 switch (tp->version) { 3322 case RTL_VER_01: 3323 case RTL_VER_02: 3324 case RTL_VER_07: 3325 if (enable) { 3326 r8152_eee_en(tp, true); 3327 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 3328 tp->eee_adv); 3329 } else { 3330 r8152_eee_en(tp, false); 3331 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); 3332 } 3333 break; 3334 case RTL_VER_03: 3335 case RTL_VER_04: 3336 case RTL_VER_05: 3337 case RTL_VER_06: 3338 case RTL_VER_08: 3339 case RTL_VER_09: 3340 if (enable) { 3341 r8153_eee_en(tp, true); 3342 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); 3343 } else { 3344 r8153_eee_en(tp, false); 3345 ocp_reg_write(tp, OCP_EEE_ADV, 0); 3346 } 3347 break; 3348 default: 3349 break; 3350 } 3351 } 3352 3353 static void r8152b_enable_fc(struct r8152 *tp) 3354 { 3355 u16 anar; 3356 3357 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3358 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 3359 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3360 3361 tp->ups_info.flow_control = true; 3362 } 3363 3364 static void rtl8152_disable(struct r8152 *tp) 3365 { 3366 r8152_aldps_en(tp, false); 3367 rtl_disable(tp); 3368 r8152_aldps_en(tp, true); 3369 } 3370 3371 static void r8152b_hw_phy_cfg(struct r8152 *tp) 3372 { 3373 rtl_eee_enable(tp, tp->eee_en); 3374 r8152_aldps_en(tp, true); 3375 r8152b_enable_fc(tp); 3376 3377 set_bit(PHY_RESET, &tp->flags); 3378 } 3379 3380 static void r8152b_exit_oob(struct r8152 *tp) 3381 { 3382 u32 ocp_data; 3383 int i; 3384 3385 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3386 ocp_data &= ~RCR_ACPT_ALL; 3387 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3388 3389 rxdy_gated_en(tp, true); 3390 r8153_teredo_off(tp); 3391 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3392 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 3393 3394 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3395 ocp_data &= ~NOW_IS_OOB; 3396 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3397 3398 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3399 ocp_data &= ~MCU_BORW_EN; 3400 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3401 3402 for (i = 0; i < 1000; i++) { 3403 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3404 if (ocp_data & LINK_LIST_READY) 3405 break; 3406 usleep_range(1000, 2000); 3407 } 3408 3409 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3410 ocp_data |= RE_INIT_LL; 3411 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3412 3413 for (i = 0; i < 1000; i++) { 3414 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3415 if (ocp_data & LINK_LIST_READY) 3416 break; 3417 usleep_range(1000, 2000); 3418 } 3419 3420 rtl8152_nic_reset(tp); 3421 3422 /* rx share fifo credit full threshold */ 3423 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3424 3425 if (tp->udev->speed == USB_SPEED_FULL || 3426 tp->udev->speed == USB_SPEED_LOW) { 3427 /* rx share fifo credit near full threshold */ 3428 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3429 RXFIFO_THR2_FULL); 3430 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3431 RXFIFO_THR3_FULL); 3432 } else { 3433 /* rx share fifo credit near full threshold */ 3434 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 3435 RXFIFO_THR2_HIGH); 3436 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 3437 RXFIFO_THR3_HIGH); 3438 } 3439 3440 /* TX share fifo free credit full threshold */ 3441 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 3442 3443 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 3444 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 3445 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 3446 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 3447 3448 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3449 3450 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3451 3452 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3453 ocp_data |= TCR0_AUTO_FIFO; 3454 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3455 } 3456 3457 static void r8152b_enter_oob(struct r8152 *tp) 3458 { 3459 u32 ocp_data; 3460 int i; 3461 3462 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3463 ocp_data &= ~NOW_IS_OOB; 3464 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3465 3466 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 3467 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 3468 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 3469 3470 rtl_disable(tp); 3471 3472 for (i = 0; i < 1000; i++) { 3473 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3474 if (ocp_data & LINK_LIST_READY) 3475 break; 3476 usleep_range(1000, 2000); 3477 } 3478 3479 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3480 ocp_data |= RE_INIT_LL; 3481 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3482 3483 for (i = 0; i < 1000; i++) { 3484 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3485 if (ocp_data & LINK_LIST_READY) 3486 break; 3487 usleep_range(1000, 2000); 3488 } 3489 3490 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 3491 3492 rtl_rx_vlan_en(tp, true); 3493 3494 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); 3495 ocp_data |= ALDPS_PROXY_MODE; 3496 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); 3497 3498 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3499 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3500 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3501 3502 rxdy_gated_en(tp, false); 3503 3504 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3505 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3506 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3507 } 3508 3509 static int r8153_patch_request(struct r8152 *tp, bool request) 3510 { 3511 u16 data; 3512 int i; 3513 3514 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD); 3515 if (request) 3516 data |= PATCH_REQUEST; 3517 else 3518 data &= ~PATCH_REQUEST; 3519 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); 3520 3521 for (i = 0; request && i < 5000; i++) { 3522 usleep_range(1000, 2000); 3523 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY) 3524 break; 3525 } 3526 3527 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) { 3528 netif_err(tp, drv, tp->netdev, "patch request fail\n"); 3529 r8153_patch_request(tp, false); 3530 return -ETIME; 3531 } else { 3532 return 0; 3533 } 3534 } 3535 3536 static void r8153_aldps_en(struct r8152 *tp, bool enable) 3537 { 3538 u16 data; 3539 3540 data = ocp_reg_read(tp, OCP_POWER_CFG); 3541 if (enable) { 3542 data |= EN_ALDPS; 3543 ocp_reg_write(tp, OCP_POWER_CFG, data); 3544 } else { 3545 int i; 3546 3547 data &= ~EN_ALDPS; 3548 ocp_reg_write(tp, OCP_POWER_CFG, data); 3549 for (i = 0; i < 20; i++) { 3550 usleep_range(1000, 2000); 3551 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) 3552 break; 3553 } 3554 } 3555 3556 tp->ups_info.aldps = enable; 3557 } 3558 3559 static void r8153_hw_phy_cfg(struct r8152 *tp) 3560 { 3561 u32 ocp_data; 3562 u16 data; 3563 3564 /* disable ALDPS before updating the PHY parameters */ 3565 r8153_aldps_en(tp, false); 3566 3567 /* disable EEE before updating the PHY parameters */ 3568 rtl_eee_enable(tp, false); 3569 3570 if (tp->version == RTL_VER_03) { 3571 data = ocp_reg_read(tp, OCP_EEE_CFG); 3572 data &= ~CTAP_SHORT_EN; 3573 ocp_reg_write(tp, OCP_EEE_CFG, data); 3574 } 3575 3576 data = ocp_reg_read(tp, OCP_POWER_CFG); 3577 data |= EEE_CLKDIV_EN; 3578 ocp_reg_write(tp, OCP_POWER_CFG, data); 3579 3580 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3581 data |= EN_10M_BGOFF; 3582 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3583 data = ocp_reg_read(tp, OCP_POWER_CFG); 3584 data |= EN_10M_PLLOFF; 3585 ocp_reg_write(tp, OCP_POWER_CFG, data); 3586 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 3587 3588 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3589 ocp_data |= PFM_PWM_SWITCH; 3590 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3591 3592 /* Enable LPF corner auto tune */ 3593 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 3594 3595 /* Adjust 10M Amplitude */ 3596 sram_write(tp, SRAM_10M_AMP1, 0x00af); 3597 sram_write(tp, SRAM_10M_AMP2, 0x0208); 3598 3599 if (tp->eee_en) 3600 rtl_eee_enable(tp, true); 3601 3602 r8153_aldps_en(tp, true); 3603 r8152b_enable_fc(tp); 3604 3605 switch (tp->version) { 3606 case RTL_VER_03: 3607 case RTL_VER_04: 3608 break; 3609 case RTL_VER_05: 3610 case RTL_VER_06: 3611 default: 3612 r8153_u2p3en(tp, true); 3613 break; 3614 } 3615 3616 set_bit(PHY_RESET, &tp->flags); 3617 } 3618 3619 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) 3620 { 3621 u32 ocp_data; 3622 3623 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr); 3624 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD); 3625 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */ 3626 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA); 3627 3628 return ocp_data; 3629 } 3630 3631 static void r8153b_hw_phy_cfg(struct r8152 *tp) 3632 { 3633 u32 ocp_data; 3634 u16 data; 3635 3636 /* disable ALDPS before updating the PHY parameters */ 3637 r8153_aldps_en(tp, false); 3638 3639 /* disable EEE before updating the PHY parameters */ 3640 rtl_eee_enable(tp, false); 3641 3642 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); 3643 3644 data = sram_read(tp, SRAM_GREEN_CFG); 3645 data |= R_TUNE_EN; 3646 sram_write(tp, SRAM_GREEN_CFG, data); 3647 data = ocp_reg_read(tp, OCP_NCTL_CFG); 3648 data |= PGA_RETURN_EN; 3649 ocp_reg_write(tp, OCP_NCTL_CFG, data); 3650 3651 /* ADC Bias Calibration: 3652 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake 3653 * bit (bit3) to rebuild the real 16-bit data. Write the data to the 3654 * ADC ioffset. 3655 */ 3656 ocp_data = r8152_efuse_read(tp, 0x7d); 3657 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); 3658 if (data != 0xffff) 3659 ocp_reg_write(tp, OCP_ADC_IOFFSET, data); 3660 3661 /* ups mode tx-link-pulse timing adjustment: 3662 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] 3663 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt 3664 */ 3665 ocp_data = ocp_reg_read(tp, 0xc426); 3666 ocp_data &= 0x3fff; 3667 if (ocp_data) { 3668 u32 swr_cnt_1ms_ini; 3669 3670 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; 3671 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); 3672 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; 3673 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); 3674 } 3675 3676 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3677 ocp_data |= PFM_PWM_SWITCH; 3678 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3679 3680 /* Advnace EEE */ 3681 if (!r8153_patch_request(tp, true)) { 3682 data = ocp_reg_read(tp, OCP_POWER_CFG); 3683 data |= EEE_CLKDIV_EN; 3684 ocp_reg_write(tp, OCP_POWER_CFG, data); 3685 tp->ups_info.eee_ckdiv = true; 3686 3687 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 3688 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV; 3689 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 3690 tp->ups_info.eee_cmod_lv = true; 3691 tp->ups_info._10m_ckdiv = true; 3692 tp->ups_info.eee_plloff_giga = true; 3693 3694 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); 3695 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5)); 3696 tp->ups_info._250m_ckdiv = true; 3697 3698 r8153_patch_request(tp, false); 3699 } 3700 3701 if (tp->eee_en) 3702 rtl_eee_enable(tp, true); 3703 3704 r8153_aldps_en(tp, true); 3705 r8152b_enable_fc(tp); 3706 r8153_u2p3en(tp, true); 3707 3708 set_bit(PHY_RESET, &tp->flags); 3709 } 3710 3711 static void r8153_first_init(struct r8152 *tp) 3712 { 3713 u32 ocp_data; 3714 int i; 3715 3716 r8153_mac_clk_spd(tp, false); 3717 rxdy_gated_en(tp, true); 3718 r8153_teredo_off(tp); 3719 3720 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3721 ocp_data &= ~RCR_ACPT_ALL; 3722 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3723 3724 rtl8152_nic_reset(tp); 3725 rtl_reset_bmu(tp); 3726 3727 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3728 ocp_data &= ~NOW_IS_OOB; 3729 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3730 3731 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3732 ocp_data &= ~MCU_BORW_EN; 3733 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3734 3735 for (i = 0; i < 1000; i++) { 3736 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3737 if (ocp_data & LINK_LIST_READY) 3738 break; 3739 usleep_range(1000, 2000); 3740 } 3741 3742 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3743 ocp_data |= RE_INIT_LL; 3744 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3745 3746 for (i = 0; i < 1000; i++) { 3747 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3748 if (ocp_data & LINK_LIST_READY) 3749 break; 3750 usleep_range(1000, 2000); 3751 } 3752 3753 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 3754 3755 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3756 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3757 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 3758 3759 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 3760 ocp_data |= TCR0_AUTO_FIFO; 3761 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 3762 3763 rtl8152_nic_reset(tp); 3764 3765 /* rx share fifo credit full threshold */ 3766 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 3767 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 3768 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 3769 /* TX share fifo free credit full threshold */ 3770 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 3771 } 3772 3773 static void r8153_enter_oob(struct r8152 *tp) 3774 { 3775 u32 ocp_data; 3776 int i; 3777 3778 r8153_mac_clk_spd(tp, true); 3779 3780 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3781 ocp_data &= ~NOW_IS_OOB; 3782 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3783 3784 rtl_disable(tp); 3785 rtl_reset_bmu(tp); 3786 3787 for (i = 0; i < 1000; i++) { 3788 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3789 if (ocp_data & LINK_LIST_READY) 3790 break; 3791 usleep_range(1000, 2000); 3792 } 3793 3794 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 3795 ocp_data |= RE_INIT_LL; 3796 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 3797 3798 for (i = 0; i < 1000; i++) { 3799 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3800 if (ocp_data & LINK_LIST_READY) 3801 break; 3802 usleep_range(1000, 2000); 3803 } 3804 3805 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 3806 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 3807 3808 switch (tp->version) { 3809 case RTL_VER_03: 3810 case RTL_VER_04: 3811 case RTL_VER_05: 3812 case RTL_VER_06: 3813 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 3814 ocp_data &= ~TEREDO_WAKE_MASK; 3815 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 3816 break; 3817 3818 case RTL_VER_08: 3819 case RTL_VER_09: 3820 /* Clear teredo wake event. bit[15:8] is the teredo wakeup 3821 * type. Set it to zero. bits[7:0] are the W1C bits about 3822 * the events. Set them to all 1 to clear them. 3823 */ 3824 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); 3825 break; 3826 3827 default: 3828 break; 3829 } 3830 3831 rtl_rx_vlan_en(tp, true); 3832 3833 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); 3834 ocp_data |= ALDPS_PROXY_MODE; 3835 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); 3836 3837 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3838 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 3839 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 3840 3841 rxdy_gated_en(tp, false); 3842 3843 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3844 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 3845 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3846 } 3847 3848 static void rtl8153_disable(struct r8152 *tp) 3849 { 3850 r8153_aldps_en(tp, false); 3851 rtl_disable(tp); 3852 rtl_reset_bmu(tp); 3853 r8153_aldps_en(tp, true); 3854 } 3855 3856 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex, 3857 u32 advertising) 3858 { 3859 u16 bmcr; 3860 int ret = 0; 3861 3862 if (autoneg == AUTONEG_DISABLE) { 3863 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL) 3864 return -EINVAL; 3865 3866 switch (speed) { 3867 case SPEED_10: 3868 bmcr = BMCR_SPEED10; 3869 if (duplex == DUPLEX_FULL) { 3870 bmcr |= BMCR_FULLDPLX; 3871 tp->ups_info.speed_duplex = FORCE_10M_FULL; 3872 } else { 3873 tp->ups_info.speed_duplex = FORCE_10M_HALF; 3874 } 3875 break; 3876 case SPEED_100: 3877 bmcr = BMCR_SPEED100; 3878 if (duplex == DUPLEX_FULL) { 3879 bmcr |= BMCR_FULLDPLX; 3880 tp->ups_info.speed_duplex = FORCE_100M_FULL; 3881 } else { 3882 tp->ups_info.speed_duplex = FORCE_100M_HALF; 3883 } 3884 break; 3885 case SPEED_1000: 3886 if (tp->mii.supports_gmii) { 3887 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX; 3888 tp->ups_info.speed_duplex = NWAY_1000M_FULL; 3889 break; 3890 } 3891 /* fall through */ 3892 default: 3893 ret = -EINVAL; 3894 goto out; 3895 } 3896 3897 if (duplex == DUPLEX_FULL) 3898 tp->mii.full_duplex = 1; 3899 else 3900 tp->mii.full_duplex = 0; 3901 3902 tp->mii.force_media = 1; 3903 } else { 3904 u16 anar, tmp1; 3905 u32 support; 3906 3907 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL | 3908 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL; 3909 3910 if (tp->mii.supports_gmii) 3911 support |= RTL_ADVERTISED_1000_FULL; 3912 3913 if (!(advertising & support)) 3914 return -EINVAL; 3915 3916 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3917 tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 3918 ADVERTISE_100HALF | ADVERTISE_100FULL); 3919 if (advertising & RTL_ADVERTISED_10_HALF) { 3920 tmp1 |= ADVERTISE_10HALF; 3921 tp->ups_info.speed_duplex = NWAY_10M_HALF; 3922 } 3923 if (advertising & RTL_ADVERTISED_10_FULL) { 3924 tmp1 |= ADVERTISE_10FULL; 3925 tp->ups_info.speed_duplex = NWAY_10M_FULL; 3926 } 3927 3928 if (advertising & RTL_ADVERTISED_100_HALF) { 3929 tmp1 |= ADVERTISE_100HALF; 3930 tp->ups_info.speed_duplex = NWAY_100M_HALF; 3931 } 3932 if (advertising & RTL_ADVERTISED_100_FULL) { 3933 tmp1 |= ADVERTISE_100FULL; 3934 tp->ups_info.speed_duplex = NWAY_100M_FULL; 3935 } 3936 3937 if (anar != tmp1) { 3938 r8152_mdio_write(tp, MII_ADVERTISE, tmp1); 3939 tp->mii.advertising = tmp1; 3940 } 3941 3942 if (tp->mii.supports_gmii) { 3943 u16 gbcr; 3944 3945 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 3946 tmp1 = gbcr & ~(ADVERTISE_1000FULL | 3947 ADVERTISE_1000HALF); 3948 3949 if (advertising & RTL_ADVERTISED_1000_FULL) { 3950 tmp1 |= ADVERTISE_1000FULL; 3951 tp->ups_info.speed_duplex = NWAY_1000M_FULL; 3952 } 3953 3954 if (gbcr != tmp1) 3955 r8152_mdio_write(tp, MII_CTRL1000, tmp1); 3956 } 3957 3958 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 3959 3960 tp->mii.force_media = 0; 3961 } 3962 3963 if (test_and_clear_bit(PHY_RESET, &tp->flags)) 3964 bmcr |= BMCR_RESET; 3965 3966 r8152_mdio_write(tp, MII_BMCR, bmcr); 3967 3968 if (bmcr & BMCR_RESET) { 3969 int i; 3970 3971 for (i = 0; i < 50; i++) { 3972 msleep(20); 3973 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 3974 break; 3975 } 3976 } 3977 3978 out: 3979 return ret; 3980 } 3981 3982 static void rtl8152_up(struct r8152 *tp) 3983 { 3984 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3985 return; 3986 3987 r8152_aldps_en(tp, false); 3988 r8152b_exit_oob(tp); 3989 r8152_aldps_en(tp, true); 3990 } 3991 3992 static void rtl8152_down(struct r8152 *tp) 3993 { 3994 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3995 rtl_drop_queued_tx(tp); 3996 return; 3997 } 3998 3999 r8152_power_cut_en(tp, false); 4000 r8152_aldps_en(tp, false); 4001 r8152b_enter_oob(tp); 4002 r8152_aldps_en(tp, true); 4003 } 4004 4005 static void rtl8153_up(struct r8152 *tp) 4006 { 4007 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4008 return; 4009 4010 r8153_u1u2en(tp, false); 4011 r8153_u2p3en(tp, false); 4012 r8153_aldps_en(tp, false); 4013 r8153_first_init(tp); 4014 r8153_aldps_en(tp, true); 4015 4016 switch (tp->version) { 4017 case RTL_VER_03: 4018 case RTL_VER_04: 4019 break; 4020 case RTL_VER_05: 4021 case RTL_VER_06: 4022 default: 4023 r8153_u2p3en(tp, true); 4024 break; 4025 } 4026 4027 r8153_u1u2en(tp, true); 4028 } 4029 4030 static void rtl8153_down(struct r8152 *tp) 4031 { 4032 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 4033 rtl_drop_queued_tx(tp); 4034 return; 4035 } 4036 4037 r8153_u1u2en(tp, false); 4038 r8153_u2p3en(tp, false); 4039 r8153_power_cut_en(tp, false); 4040 r8153_aldps_en(tp, false); 4041 r8153_enter_oob(tp); 4042 r8153_aldps_en(tp, true); 4043 } 4044 4045 static void rtl8153b_up(struct r8152 *tp) 4046 { 4047 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4048 return; 4049 4050 r8153b_u1u2en(tp, false); 4051 r8153_u2p3en(tp, false); 4052 r8153_aldps_en(tp, false); 4053 4054 r8153_first_init(tp); 4055 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); 4056 4057 r8153_aldps_en(tp, true); 4058 r8153_u2p3en(tp, true); 4059 r8153b_u1u2en(tp, true); 4060 } 4061 4062 static void rtl8153b_down(struct r8152 *tp) 4063 { 4064 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 4065 rtl_drop_queued_tx(tp); 4066 return; 4067 } 4068 4069 r8153b_u1u2en(tp, false); 4070 r8153_u2p3en(tp, false); 4071 r8153b_power_cut_en(tp, false); 4072 r8153_aldps_en(tp, false); 4073 r8153_enter_oob(tp); 4074 r8153_aldps_en(tp, true); 4075 } 4076 4077 static bool rtl8152_in_nway(struct r8152 *tp) 4078 { 4079 u16 nway_state; 4080 4081 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); 4082 tp->ocp_base = 0x2000; 4083 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ 4084 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); 4085 4086 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ 4087 if (nway_state & 0xc000) 4088 return false; 4089 else 4090 return true; 4091 } 4092 4093 static bool rtl8153_in_nway(struct r8152 *tp) 4094 { 4095 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; 4096 4097 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) 4098 return false; 4099 else 4100 return true; 4101 } 4102 4103 static void set_carrier(struct r8152 *tp) 4104 { 4105 struct net_device *netdev = tp->netdev; 4106 struct napi_struct *napi = &tp->napi; 4107 u8 speed; 4108 4109 speed = rtl8152_get_speed(tp); 4110 4111 if (speed & LINK_STATUS) { 4112 if (!netif_carrier_ok(netdev)) { 4113 tp->rtl_ops.enable(tp); 4114 netif_stop_queue(netdev); 4115 napi_disable(napi); 4116 netif_carrier_on(netdev); 4117 rtl_start_rx(tp); 4118 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 4119 _rtl8152_set_rx_mode(netdev); 4120 napi_enable(&tp->napi); 4121 netif_wake_queue(netdev); 4122 netif_info(tp, link, netdev, "carrier on\n"); 4123 } else if (netif_queue_stopped(netdev) && 4124 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) { 4125 netif_wake_queue(netdev); 4126 } 4127 } else { 4128 if (netif_carrier_ok(netdev)) { 4129 netif_carrier_off(netdev); 4130 tasklet_disable(&tp->tx_tl); 4131 napi_disable(napi); 4132 tp->rtl_ops.disable(tp); 4133 napi_enable(napi); 4134 tasklet_enable(&tp->tx_tl); 4135 netif_info(tp, link, netdev, "carrier off\n"); 4136 } 4137 } 4138 } 4139 4140 static void rtl_work_func_t(struct work_struct *work) 4141 { 4142 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 4143 4144 /* If the device is unplugged or !netif_running(), the workqueue 4145 * doesn't need to wake the device, and could return directly. 4146 */ 4147 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) 4148 return; 4149 4150 if (usb_autopm_get_interface(tp->intf) < 0) 4151 return; 4152 4153 if (!test_bit(WORK_ENABLE, &tp->flags)) 4154 goto out1; 4155 4156 if (!mutex_trylock(&tp->control)) { 4157 schedule_delayed_work(&tp->schedule, 0); 4158 goto out1; 4159 } 4160 4161 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) 4162 set_carrier(tp); 4163 4164 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) 4165 _rtl8152_set_rx_mode(tp->netdev); 4166 4167 /* don't schedule tasket before linking */ 4168 if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) && 4169 netif_carrier_ok(tp->netdev)) 4170 tasklet_schedule(&tp->tx_tl); 4171 4172 mutex_unlock(&tp->control); 4173 4174 out1: 4175 usb_autopm_put_interface(tp->intf); 4176 } 4177 4178 static void rtl_hw_phy_work_func_t(struct work_struct *work) 4179 { 4180 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); 4181 4182 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4183 return; 4184 4185 if (usb_autopm_get_interface(tp->intf) < 0) 4186 return; 4187 4188 mutex_lock(&tp->control); 4189 4190 tp->rtl_ops.hw_phy_cfg(tp); 4191 4192 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex, 4193 tp->advertising); 4194 4195 mutex_unlock(&tp->control); 4196 4197 usb_autopm_put_interface(tp->intf); 4198 } 4199 4200 #ifdef CONFIG_PM_SLEEP 4201 static int rtl_notifier(struct notifier_block *nb, unsigned long action, 4202 void *data) 4203 { 4204 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); 4205 4206 switch (action) { 4207 case PM_HIBERNATION_PREPARE: 4208 case PM_SUSPEND_PREPARE: 4209 usb_autopm_get_interface(tp->intf); 4210 break; 4211 4212 case PM_POST_HIBERNATION: 4213 case PM_POST_SUSPEND: 4214 usb_autopm_put_interface(tp->intf); 4215 break; 4216 4217 case PM_POST_RESTORE: 4218 case PM_RESTORE_PREPARE: 4219 default: 4220 break; 4221 } 4222 4223 return NOTIFY_DONE; 4224 } 4225 #endif 4226 4227 static int rtl8152_open(struct net_device *netdev) 4228 { 4229 struct r8152 *tp = netdev_priv(netdev); 4230 int res = 0; 4231 4232 res = alloc_all_mem(tp); 4233 if (res) 4234 goto out; 4235 4236 res = usb_autopm_get_interface(tp->intf); 4237 if (res < 0) 4238 goto out_free; 4239 4240 mutex_lock(&tp->control); 4241 4242 tp->rtl_ops.up(tp); 4243 4244 netif_carrier_off(netdev); 4245 netif_start_queue(netdev); 4246 set_bit(WORK_ENABLE, &tp->flags); 4247 4248 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 4249 if (res) { 4250 if (res == -ENODEV) 4251 netif_device_detach(tp->netdev); 4252 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 4253 res); 4254 goto out_unlock; 4255 } 4256 napi_enable(&tp->napi); 4257 tasklet_enable(&tp->tx_tl); 4258 4259 mutex_unlock(&tp->control); 4260 4261 usb_autopm_put_interface(tp->intf); 4262 #ifdef CONFIG_PM_SLEEP 4263 tp->pm_notifier.notifier_call = rtl_notifier; 4264 register_pm_notifier(&tp->pm_notifier); 4265 #endif 4266 return 0; 4267 4268 out_unlock: 4269 mutex_unlock(&tp->control); 4270 usb_autopm_put_interface(tp->intf); 4271 out_free: 4272 free_all_mem(tp); 4273 out: 4274 return res; 4275 } 4276 4277 static int rtl8152_close(struct net_device *netdev) 4278 { 4279 struct r8152 *tp = netdev_priv(netdev); 4280 int res = 0; 4281 4282 #ifdef CONFIG_PM_SLEEP 4283 unregister_pm_notifier(&tp->pm_notifier); 4284 #endif 4285 tasklet_disable(&tp->tx_tl); 4286 napi_disable(&tp->napi); 4287 clear_bit(WORK_ENABLE, &tp->flags); 4288 usb_kill_urb(tp->intr_urb); 4289 cancel_delayed_work_sync(&tp->schedule); 4290 netif_stop_queue(netdev); 4291 4292 res = usb_autopm_get_interface(tp->intf); 4293 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { 4294 rtl_drop_queued_tx(tp); 4295 rtl_stop_rx(tp); 4296 } else { 4297 mutex_lock(&tp->control); 4298 4299 tp->rtl_ops.down(tp); 4300 4301 mutex_unlock(&tp->control); 4302 4303 usb_autopm_put_interface(tp->intf); 4304 } 4305 4306 free_all_mem(tp); 4307 4308 return res; 4309 } 4310 4311 static void rtl_tally_reset(struct r8152 *tp) 4312 { 4313 u32 ocp_data; 4314 4315 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 4316 ocp_data |= TALLY_RESET; 4317 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 4318 } 4319 4320 static void r8152b_init(struct r8152 *tp) 4321 { 4322 u32 ocp_data; 4323 u16 data; 4324 4325 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4326 return; 4327 4328 data = r8152_mdio_read(tp, MII_BMCR); 4329 if (data & BMCR_PDOWN) { 4330 data &= ~BMCR_PDOWN; 4331 r8152_mdio_write(tp, MII_BMCR, data); 4332 } 4333 4334 r8152_aldps_en(tp, false); 4335 4336 if (tp->version == RTL_VER_01) { 4337 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4338 ocp_data &= ~LED_MODE_MASK; 4339 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4340 } 4341 4342 r8152_power_cut_en(tp, false); 4343 4344 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 4345 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 4346 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 4347 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 4348 ocp_data &= ~MCU_CLK_RATIO_MASK; 4349 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 4350 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 4351 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 4352 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 4353 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 4354 4355 rtl_tally_reset(tp); 4356 4357 /* enable rx aggregation */ 4358 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4359 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4360 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4361 } 4362 4363 static void r8153_init(struct r8152 *tp) 4364 { 4365 u32 ocp_data; 4366 u16 data; 4367 int i; 4368 4369 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4370 return; 4371 4372 r8153_u1u2en(tp, false); 4373 4374 for (i = 0; i < 500; i++) { 4375 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4376 AUTOLOAD_DONE) 4377 break; 4378 msleep(20); 4379 } 4380 4381 data = r8153_phy_status(tp, 0); 4382 4383 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 4384 tp->version == RTL_VER_05) 4385 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 4386 4387 data = r8152_mdio_read(tp, MII_BMCR); 4388 if (data & BMCR_PDOWN) { 4389 data &= ~BMCR_PDOWN; 4390 r8152_mdio_write(tp, MII_BMCR, data); 4391 } 4392 4393 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4394 4395 r8153_u2p3en(tp, false); 4396 4397 if (tp->version == RTL_VER_04) { 4398 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 4399 ocp_data &= ~pwd_dn_scale_mask; 4400 ocp_data |= pwd_dn_scale(96); 4401 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 4402 4403 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 4404 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 4405 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 4406 } else if (tp->version == RTL_VER_05) { 4407 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 4408 ocp_data &= ~ECM_ALDPS; 4409 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 4410 4411 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4412 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4413 ocp_data &= ~DYNAMIC_BURST; 4414 else 4415 ocp_data |= DYNAMIC_BURST; 4416 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4417 } else if (tp->version == RTL_VER_06) { 4418 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 4419 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 4420 ocp_data &= ~DYNAMIC_BURST; 4421 else 4422 ocp_data |= DYNAMIC_BURST; 4423 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 4424 } 4425 4426 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 4427 ocp_data |= EP4_FULL_FC; 4428 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 4429 4430 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 4431 ocp_data &= ~TIMER11_EN; 4432 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 4433 4434 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 4435 ocp_data &= ~LED_MODE_MASK; 4436 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 4437 4438 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 4439 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) 4440 ocp_data |= LPM_TIMER_500MS; 4441 else 4442 ocp_data |= LPM_TIMER_500US; 4443 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 4444 4445 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 4446 ocp_data &= ~SEN_VAL_MASK; 4447 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 4448 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 4449 4450 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 4451 4452 r8153_power_cut_en(tp, false); 4453 r8153_u1u2en(tp, true); 4454 r8153_mac_clk_spd(tp, false); 4455 usb_enable_lpm(tp->udev); 4456 4457 /* rx aggregation */ 4458 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4459 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4460 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags)) 4461 ocp_data |= RX_AGG_DISABLE; 4462 4463 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4464 4465 rtl_tally_reset(tp); 4466 4467 switch (tp->udev->speed) { 4468 case USB_SPEED_SUPER: 4469 case USB_SPEED_SUPER_PLUS: 4470 tp->coalesce = COALESCE_SUPER; 4471 break; 4472 case USB_SPEED_HIGH: 4473 tp->coalesce = COALESCE_HIGH; 4474 break; 4475 default: 4476 tp->coalesce = COALESCE_SLOW; 4477 break; 4478 } 4479 } 4480 4481 static void r8153b_init(struct r8152 *tp) 4482 { 4483 u32 ocp_data; 4484 u16 data; 4485 int i; 4486 4487 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4488 return; 4489 4490 r8153b_u1u2en(tp, false); 4491 4492 for (i = 0; i < 500; i++) { 4493 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 4494 AUTOLOAD_DONE) 4495 break; 4496 msleep(20); 4497 } 4498 4499 data = r8153_phy_status(tp, 0); 4500 4501 data = r8152_mdio_read(tp, MII_BMCR); 4502 if (data & BMCR_PDOWN) { 4503 data &= ~BMCR_PDOWN; 4504 r8152_mdio_write(tp, MII_BMCR, data); 4505 } 4506 4507 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 4508 4509 r8153_u2p3en(tp, false); 4510 4511 /* MSC timer = 0xfff * 8ms = 32760 ms */ 4512 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 4513 4514 /* U1/U2/L1 idle timer. 500 us */ 4515 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 4516 4517 r8153b_power_cut_en(tp, false); 4518 r8153b_ups_en(tp, false); 4519 r8153_queue_wake(tp, false); 4520 rtl_runtime_suspend_enable(tp, false); 4521 r8153b_u1u2en(tp, true); 4522 usb_enable_lpm(tp->udev); 4523 4524 /* MAC clock speed down */ 4525 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); 4526 ocp_data |= MAC_CLK_SPDWN_EN; 4527 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); 4528 4529 set_bit(GREEN_ETHERNET, &tp->flags); 4530 4531 /* rx aggregation */ 4532 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 4533 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 4534 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 4535 4536 rtl_tally_reset(tp); 4537 4538 tp->coalesce = 15000; /* 15 us */ 4539 } 4540 4541 static int rtl8152_pre_reset(struct usb_interface *intf) 4542 { 4543 struct r8152 *tp = usb_get_intfdata(intf); 4544 struct net_device *netdev; 4545 4546 if (!tp) 4547 return 0; 4548 4549 netdev = tp->netdev; 4550 if (!netif_running(netdev)) 4551 return 0; 4552 4553 netif_stop_queue(netdev); 4554 tasklet_disable(&tp->tx_tl); 4555 napi_disable(&tp->napi); 4556 clear_bit(WORK_ENABLE, &tp->flags); 4557 usb_kill_urb(tp->intr_urb); 4558 cancel_delayed_work_sync(&tp->schedule); 4559 if (netif_carrier_ok(netdev)) { 4560 mutex_lock(&tp->control); 4561 tp->rtl_ops.disable(tp); 4562 mutex_unlock(&tp->control); 4563 } 4564 4565 return 0; 4566 } 4567 4568 static int rtl8152_post_reset(struct usb_interface *intf) 4569 { 4570 struct r8152 *tp = usb_get_intfdata(intf); 4571 struct net_device *netdev; 4572 struct sockaddr sa; 4573 4574 if (!tp) 4575 return 0; 4576 4577 /* reset the MAC adddress in case of policy change */ 4578 if (determine_ethernet_addr(tp, &sa) >= 0) { 4579 rtnl_lock(); 4580 dev_set_mac_address (tp->netdev, &sa, NULL); 4581 rtnl_unlock(); 4582 } 4583 4584 netdev = tp->netdev; 4585 if (!netif_running(netdev)) 4586 return 0; 4587 4588 set_bit(WORK_ENABLE, &tp->flags); 4589 if (netif_carrier_ok(netdev)) { 4590 mutex_lock(&tp->control); 4591 tp->rtl_ops.enable(tp); 4592 rtl_start_rx(tp); 4593 _rtl8152_set_rx_mode(netdev); 4594 mutex_unlock(&tp->control); 4595 } 4596 4597 napi_enable(&tp->napi); 4598 tasklet_enable(&tp->tx_tl); 4599 netif_wake_queue(netdev); 4600 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 4601 4602 if (!list_empty(&tp->rx_done)) 4603 napi_schedule(&tp->napi); 4604 4605 return 0; 4606 } 4607 4608 static bool delay_autosuspend(struct r8152 *tp) 4609 { 4610 bool sw_linking = !!netif_carrier_ok(tp->netdev); 4611 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); 4612 4613 /* This means a linking change occurs and the driver doesn't detect it, 4614 * yet. If the driver has disabled tx/rx and hw is linking on, the 4615 * device wouldn't wake up by receiving any packet. 4616 */ 4617 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) 4618 return true; 4619 4620 /* If the linking down is occurred by nway, the device may miss the 4621 * linking change event. And it wouldn't wake when linking on. 4622 */ 4623 if (!sw_linking && tp->rtl_ops.in_nway(tp)) 4624 return true; 4625 else if (!skb_queue_empty(&tp->tx_queue)) 4626 return true; 4627 else 4628 return false; 4629 } 4630 4631 static int rtl8152_runtime_resume(struct r8152 *tp) 4632 { 4633 struct net_device *netdev = tp->netdev; 4634 4635 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4636 struct napi_struct *napi = &tp->napi; 4637 4638 tp->rtl_ops.autosuspend_en(tp, false); 4639 napi_disable(napi); 4640 set_bit(WORK_ENABLE, &tp->flags); 4641 4642 if (netif_carrier_ok(netdev)) { 4643 if (rtl8152_get_speed(tp) & LINK_STATUS) { 4644 rtl_start_rx(tp); 4645 } else { 4646 netif_carrier_off(netdev); 4647 tp->rtl_ops.disable(tp); 4648 netif_info(tp, link, netdev, "linking down\n"); 4649 } 4650 } 4651 4652 napi_enable(napi); 4653 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4654 smp_mb__after_atomic(); 4655 4656 if (!list_empty(&tp->rx_done)) 4657 napi_schedule(&tp->napi); 4658 4659 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4660 } else { 4661 if (netdev->flags & IFF_UP) 4662 tp->rtl_ops.autosuspend_en(tp, false); 4663 4664 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4665 } 4666 4667 return 0; 4668 } 4669 4670 static int rtl8152_system_resume(struct r8152 *tp) 4671 { 4672 struct net_device *netdev = tp->netdev; 4673 4674 netif_device_attach(netdev); 4675 4676 if (netif_running(netdev) && netdev->flags & IFF_UP) { 4677 tp->rtl_ops.up(tp); 4678 netif_carrier_off(netdev); 4679 set_bit(WORK_ENABLE, &tp->flags); 4680 usb_submit_urb(tp->intr_urb, GFP_NOIO); 4681 } 4682 4683 return 0; 4684 } 4685 4686 static int rtl8152_runtime_suspend(struct r8152 *tp) 4687 { 4688 struct net_device *netdev = tp->netdev; 4689 int ret = 0; 4690 4691 set_bit(SELECTIVE_SUSPEND, &tp->flags); 4692 smp_mb__after_atomic(); 4693 4694 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4695 u32 rcr = 0; 4696 4697 if (netif_carrier_ok(netdev)) { 4698 u32 ocp_data; 4699 4700 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 4701 ocp_data = rcr & ~RCR_ACPT_ALL; 4702 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 4703 rxdy_gated_en(tp, true); 4704 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 4705 PLA_OOB_CTRL); 4706 if (!(ocp_data & RXFIFO_EMPTY)) { 4707 rxdy_gated_en(tp, false); 4708 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4709 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4710 smp_mb__after_atomic(); 4711 ret = -EBUSY; 4712 goto out1; 4713 } 4714 } 4715 4716 clear_bit(WORK_ENABLE, &tp->flags); 4717 usb_kill_urb(tp->intr_urb); 4718 4719 tp->rtl_ops.autosuspend_en(tp, true); 4720 4721 if (netif_carrier_ok(netdev)) { 4722 struct napi_struct *napi = &tp->napi; 4723 4724 napi_disable(napi); 4725 rtl_stop_rx(tp); 4726 rxdy_gated_en(tp, false); 4727 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 4728 napi_enable(napi); 4729 } 4730 4731 if (delay_autosuspend(tp)) { 4732 rtl8152_runtime_resume(tp); 4733 ret = -EBUSY; 4734 } 4735 } 4736 4737 out1: 4738 return ret; 4739 } 4740 4741 static int rtl8152_system_suspend(struct r8152 *tp) 4742 { 4743 struct net_device *netdev = tp->netdev; 4744 4745 netif_device_detach(netdev); 4746 4747 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 4748 struct napi_struct *napi = &tp->napi; 4749 4750 clear_bit(WORK_ENABLE, &tp->flags); 4751 usb_kill_urb(tp->intr_urb); 4752 tasklet_disable(&tp->tx_tl); 4753 napi_disable(napi); 4754 cancel_delayed_work_sync(&tp->schedule); 4755 tp->rtl_ops.down(tp); 4756 napi_enable(napi); 4757 tasklet_enable(&tp->tx_tl); 4758 } 4759 4760 return 0; 4761 } 4762 4763 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 4764 { 4765 struct r8152 *tp = usb_get_intfdata(intf); 4766 int ret; 4767 4768 mutex_lock(&tp->control); 4769 4770 if (PMSG_IS_AUTO(message)) 4771 ret = rtl8152_runtime_suspend(tp); 4772 else 4773 ret = rtl8152_system_suspend(tp); 4774 4775 mutex_unlock(&tp->control); 4776 4777 return ret; 4778 } 4779 4780 static int rtl8152_resume(struct usb_interface *intf) 4781 { 4782 struct r8152 *tp = usb_get_intfdata(intf); 4783 int ret; 4784 4785 mutex_lock(&tp->control); 4786 4787 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) 4788 ret = rtl8152_runtime_resume(tp); 4789 else 4790 ret = rtl8152_system_resume(tp); 4791 4792 mutex_unlock(&tp->control); 4793 4794 return ret; 4795 } 4796 4797 static int rtl8152_reset_resume(struct usb_interface *intf) 4798 { 4799 struct r8152 *tp = usb_get_intfdata(intf); 4800 4801 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 4802 mutex_lock(&tp->control); 4803 tp->rtl_ops.init(tp); 4804 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 4805 mutex_unlock(&tp->control); 4806 return rtl8152_resume(intf); 4807 } 4808 4809 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4810 { 4811 struct r8152 *tp = netdev_priv(dev); 4812 4813 if (usb_autopm_get_interface(tp->intf) < 0) 4814 return; 4815 4816 if (!rtl_can_wakeup(tp)) { 4817 wol->supported = 0; 4818 wol->wolopts = 0; 4819 } else { 4820 mutex_lock(&tp->control); 4821 wol->supported = WAKE_ANY; 4822 wol->wolopts = __rtl_get_wol(tp); 4823 mutex_unlock(&tp->control); 4824 } 4825 4826 usb_autopm_put_interface(tp->intf); 4827 } 4828 4829 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 4830 { 4831 struct r8152 *tp = netdev_priv(dev); 4832 int ret; 4833 4834 if (!rtl_can_wakeup(tp)) 4835 return -EOPNOTSUPP; 4836 4837 if (wol->wolopts & ~WAKE_ANY) 4838 return -EINVAL; 4839 4840 ret = usb_autopm_get_interface(tp->intf); 4841 if (ret < 0) 4842 goto out_set_wol; 4843 4844 mutex_lock(&tp->control); 4845 4846 __rtl_set_wol(tp, wol->wolopts); 4847 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 4848 4849 mutex_unlock(&tp->control); 4850 4851 usb_autopm_put_interface(tp->intf); 4852 4853 out_set_wol: 4854 return ret; 4855 } 4856 4857 static u32 rtl8152_get_msglevel(struct net_device *dev) 4858 { 4859 struct r8152 *tp = netdev_priv(dev); 4860 4861 return tp->msg_enable; 4862 } 4863 4864 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 4865 { 4866 struct r8152 *tp = netdev_priv(dev); 4867 4868 tp->msg_enable = value; 4869 } 4870 4871 static void rtl8152_get_drvinfo(struct net_device *netdev, 4872 struct ethtool_drvinfo *info) 4873 { 4874 struct r8152 *tp = netdev_priv(netdev); 4875 4876 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 4877 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 4878 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 4879 } 4880 4881 static 4882 int rtl8152_get_link_ksettings(struct net_device *netdev, 4883 struct ethtool_link_ksettings *cmd) 4884 { 4885 struct r8152 *tp = netdev_priv(netdev); 4886 int ret; 4887 4888 if (!tp->mii.mdio_read) 4889 return -EOPNOTSUPP; 4890 4891 ret = usb_autopm_get_interface(tp->intf); 4892 if (ret < 0) 4893 goto out; 4894 4895 mutex_lock(&tp->control); 4896 4897 mii_ethtool_get_link_ksettings(&tp->mii, cmd); 4898 4899 mutex_unlock(&tp->control); 4900 4901 usb_autopm_put_interface(tp->intf); 4902 4903 out: 4904 return ret; 4905 } 4906 4907 static int rtl8152_set_link_ksettings(struct net_device *dev, 4908 const struct ethtool_link_ksettings *cmd) 4909 { 4910 struct r8152 *tp = netdev_priv(dev); 4911 u32 advertising = 0; 4912 int ret; 4913 4914 ret = usb_autopm_get_interface(tp->intf); 4915 if (ret < 0) 4916 goto out; 4917 4918 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 4919 cmd->link_modes.advertising)) 4920 advertising |= RTL_ADVERTISED_10_HALF; 4921 4922 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 4923 cmd->link_modes.advertising)) 4924 advertising |= RTL_ADVERTISED_10_FULL; 4925 4926 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 4927 cmd->link_modes.advertising)) 4928 advertising |= RTL_ADVERTISED_100_HALF; 4929 4930 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 4931 cmd->link_modes.advertising)) 4932 advertising |= RTL_ADVERTISED_100_FULL; 4933 4934 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 4935 cmd->link_modes.advertising)) 4936 advertising |= RTL_ADVERTISED_1000_HALF; 4937 4938 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 4939 cmd->link_modes.advertising)) 4940 advertising |= RTL_ADVERTISED_1000_FULL; 4941 4942 mutex_lock(&tp->control); 4943 4944 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, 4945 cmd->base.duplex, advertising); 4946 if (!ret) { 4947 tp->autoneg = cmd->base.autoneg; 4948 tp->speed = cmd->base.speed; 4949 tp->duplex = cmd->base.duplex; 4950 tp->advertising = advertising; 4951 } 4952 4953 mutex_unlock(&tp->control); 4954 4955 usb_autopm_put_interface(tp->intf); 4956 4957 out: 4958 return ret; 4959 } 4960 4961 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 4962 "tx_packets", 4963 "rx_packets", 4964 "tx_errors", 4965 "rx_errors", 4966 "rx_missed", 4967 "align_errors", 4968 "tx_single_collisions", 4969 "tx_multi_collisions", 4970 "rx_unicast", 4971 "rx_broadcast", 4972 "rx_multicast", 4973 "tx_aborted", 4974 "tx_underrun", 4975 }; 4976 4977 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 4978 { 4979 switch (sset) { 4980 case ETH_SS_STATS: 4981 return ARRAY_SIZE(rtl8152_gstrings); 4982 default: 4983 return -EOPNOTSUPP; 4984 } 4985 } 4986 4987 static void rtl8152_get_ethtool_stats(struct net_device *dev, 4988 struct ethtool_stats *stats, u64 *data) 4989 { 4990 struct r8152 *tp = netdev_priv(dev); 4991 struct tally_counter tally; 4992 4993 if (usb_autopm_get_interface(tp->intf) < 0) 4994 return; 4995 4996 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 4997 4998 usb_autopm_put_interface(tp->intf); 4999 5000 data[0] = le64_to_cpu(tally.tx_packets); 5001 data[1] = le64_to_cpu(tally.rx_packets); 5002 data[2] = le64_to_cpu(tally.tx_errors); 5003 data[3] = le32_to_cpu(tally.rx_errors); 5004 data[4] = le16_to_cpu(tally.rx_missed); 5005 data[5] = le16_to_cpu(tally.align_errors); 5006 data[6] = le32_to_cpu(tally.tx_one_collision); 5007 data[7] = le32_to_cpu(tally.tx_multi_collision); 5008 data[8] = le64_to_cpu(tally.rx_unicast); 5009 data[9] = le64_to_cpu(tally.rx_broadcast); 5010 data[10] = le32_to_cpu(tally.rx_multicast); 5011 data[11] = le16_to_cpu(tally.tx_aborted); 5012 data[12] = le16_to_cpu(tally.tx_underrun); 5013 } 5014 5015 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 5016 { 5017 switch (stringset) { 5018 case ETH_SS_STATS: 5019 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 5020 break; 5021 } 5022 } 5023 5024 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 5025 { 5026 u32 lp, adv, supported = 0; 5027 u16 val; 5028 5029 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 5030 supported = mmd_eee_cap_to_ethtool_sup_t(val); 5031 5032 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 5033 adv = mmd_eee_adv_to_ethtool_adv_t(val); 5034 5035 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 5036 lp = mmd_eee_adv_to_ethtool_adv_t(val); 5037 5038 eee->eee_enabled = tp->eee_en; 5039 eee->eee_active = !!(supported & adv & lp); 5040 eee->supported = supported; 5041 eee->advertised = tp->eee_adv; 5042 eee->lp_advertised = lp; 5043 5044 return 0; 5045 } 5046 5047 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 5048 { 5049 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 5050 5051 tp->eee_en = eee->eee_enabled; 5052 tp->eee_adv = val; 5053 5054 rtl_eee_enable(tp, tp->eee_en); 5055 5056 return 0; 5057 } 5058 5059 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 5060 { 5061 u32 lp, adv, supported = 0; 5062 u16 val; 5063 5064 val = ocp_reg_read(tp, OCP_EEE_ABLE); 5065 supported = mmd_eee_cap_to_ethtool_sup_t(val); 5066 5067 val = ocp_reg_read(tp, OCP_EEE_ADV); 5068 adv = mmd_eee_adv_to_ethtool_adv_t(val); 5069 5070 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 5071 lp = mmd_eee_adv_to_ethtool_adv_t(val); 5072 5073 eee->eee_enabled = tp->eee_en; 5074 eee->eee_active = !!(supported & adv & lp); 5075 eee->supported = supported; 5076 eee->advertised = tp->eee_adv; 5077 eee->lp_advertised = lp; 5078 5079 return 0; 5080 } 5081 5082 static int 5083 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) 5084 { 5085 struct r8152 *tp = netdev_priv(net); 5086 int ret; 5087 5088 ret = usb_autopm_get_interface(tp->intf); 5089 if (ret < 0) 5090 goto out; 5091 5092 mutex_lock(&tp->control); 5093 5094 ret = tp->rtl_ops.eee_get(tp, edata); 5095 5096 mutex_unlock(&tp->control); 5097 5098 usb_autopm_put_interface(tp->intf); 5099 5100 out: 5101 return ret; 5102 } 5103 5104 static int 5105 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) 5106 { 5107 struct r8152 *tp = netdev_priv(net); 5108 int ret; 5109 5110 ret = usb_autopm_get_interface(tp->intf); 5111 if (ret < 0) 5112 goto out; 5113 5114 mutex_lock(&tp->control); 5115 5116 ret = tp->rtl_ops.eee_set(tp, edata); 5117 if (!ret) 5118 ret = mii_nway_restart(&tp->mii); 5119 5120 mutex_unlock(&tp->control); 5121 5122 usb_autopm_put_interface(tp->intf); 5123 5124 out: 5125 return ret; 5126 } 5127 5128 static int rtl8152_nway_reset(struct net_device *dev) 5129 { 5130 struct r8152 *tp = netdev_priv(dev); 5131 int ret; 5132 5133 ret = usb_autopm_get_interface(tp->intf); 5134 if (ret < 0) 5135 goto out; 5136 5137 mutex_lock(&tp->control); 5138 5139 ret = mii_nway_restart(&tp->mii); 5140 5141 mutex_unlock(&tp->control); 5142 5143 usb_autopm_put_interface(tp->intf); 5144 5145 out: 5146 return ret; 5147 } 5148 5149 static int rtl8152_get_coalesce(struct net_device *netdev, 5150 struct ethtool_coalesce *coalesce) 5151 { 5152 struct r8152 *tp = netdev_priv(netdev); 5153 5154 switch (tp->version) { 5155 case RTL_VER_01: 5156 case RTL_VER_02: 5157 case RTL_VER_07: 5158 return -EOPNOTSUPP; 5159 default: 5160 break; 5161 } 5162 5163 coalesce->rx_coalesce_usecs = tp->coalesce; 5164 5165 return 0; 5166 } 5167 5168 static int rtl8152_set_coalesce(struct net_device *netdev, 5169 struct ethtool_coalesce *coalesce) 5170 { 5171 struct r8152 *tp = netdev_priv(netdev); 5172 int ret; 5173 5174 switch (tp->version) { 5175 case RTL_VER_01: 5176 case RTL_VER_02: 5177 case RTL_VER_07: 5178 return -EOPNOTSUPP; 5179 default: 5180 break; 5181 } 5182 5183 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) 5184 return -EINVAL; 5185 5186 ret = usb_autopm_get_interface(tp->intf); 5187 if (ret < 0) 5188 return ret; 5189 5190 mutex_lock(&tp->control); 5191 5192 if (tp->coalesce != coalesce->rx_coalesce_usecs) { 5193 tp->coalesce = coalesce->rx_coalesce_usecs; 5194 5195 if (netif_running(netdev) && netif_carrier_ok(netdev)) { 5196 netif_stop_queue(netdev); 5197 napi_disable(&tp->napi); 5198 tp->rtl_ops.disable(tp); 5199 tp->rtl_ops.enable(tp); 5200 rtl_start_rx(tp); 5201 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 5202 _rtl8152_set_rx_mode(netdev); 5203 napi_enable(&tp->napi); 5204 netif_wake_queue(netdev); 5205 } 5206 } 5207 5208 mutex_unlock(&tp->control); 5209 5210 usb_autopm_put_interface(tp->intf); 5211 5212 return ret; 5213 } 5214 5215 static int rtl8152_get_tunable(struct net_device *netdev, 5216 const struct ethtool_tunable *tunable, void *d) 5217 { 5218 struct r8152 *tp = netdev_priv(netdev); 5219 5220 switch (tunable->id) { 5221 case ETHTOOL_RX_COPYBREAK: 5222 *(u32 *)d = tp->rx_copybreak; 5223 break; 5224 default: 5225 return -EOPNOTSUPP; 5226 } 5227 5228 return 0; 5229 } 5230 5231 static int rtl8152_set_tunable(struct net_device *netdev, 5232 const struct ethtool_tunable *tunable, 5233 const void *d) 5234 { 5235 struct r8152 *tp = netdev_priv(netdev); 5236 u32 val; 5237 5238 switch (tunable->id) { 5239 case ETHTOOL_RX_COPYBREAK: 5240 val = *(u32 *)d; 5241 if (val < ETH_ZLEN) { 5242 netif_err(tp, rx_err, netdev, 5243 "Invalid rx copy break value\n"); 5244 return -EINVAL; 5245 } 5246 5247 if (tp->rx_copybreak != val) { 5248 napi_disable(&tp->napi); 5249 tp->rx_copybreak = val; 5250 napi_enable(&tp->napi); 5251 } 5252 break; 5253 default: 5254 return -EOPNOTSUPP; 5255 } 5256 5257 return 0; 5258 } 5259 5260 static void rtl8152_get_ringparam(struct net_device *netdev, 5261 struct ethtool_ringparam *ring) 5262 { 5263 struct r8152 *tp = netdev_priv(netdev); 5264 5265 ring->rx_max_pending = RTL8152_RX_MAX_PENDING; 5266 ring->rx_pending = tp->rx_pending; 5267 } 5268 5269 static int rtl8152_set_ringparam(struct net_device *netdev, 5270 struct ethtool_ringparam *ring) 5271 { 5272 struct r8152 *tp = netdev_priv(netdev); 5273 5274 if (ring->rx_pending < (RTL8152_MAX_RX * 2)) 5275 return -EINVAL; 5276 5277 if (tp->rx_pending != ring->rx_pending) { 5278 napi_disable(&tp->napi); 5279 tp->rx_pending = ring->rx_pending; 5280 napi_enable(&tp->napi); 5281 } 5282 5283 return 0; 5284 } 5285 5286 static const struct ethtool_ops ops = { 5287 .get_drvinfo = rtl8152_get_drvinfo, 5288 .get_link = ethtool_op_get_link, 5289 .nway_reset = rtl8152_nway_reset, 5290 .get_msglevel = rtl8152_get_msglevel, 5291 .set_msglevel = rtl8152_set_msglevel, 5292 .get_wol = rtl8152_get_wol, 5293 .set_wol = rtl8152_set_wol, 5294 .get_strings = rtl8152_get_strings, 5295 .get_sset_count = rtl8152_get_sset_count, 5296 .get_ethtool_stats = rtl8152_get_ethtool_stats, 5297 .get_coalesce = rtl8152_get_coalesce, 5298 .set_coalesce = rtl8152_set_coalesce, 5299 .get_eee = rtl_ethtool_get_eee, 5300 .set_eee = rtl_ethtool_set_eee, 5301 .get_link_ksettings = rtl8152_get_link_ksettings, 5302 .set_link_ksettings = rtl8152_set_link_ksettings, 5303 .get_tunable = rtl8152_get_tunable, 5304 .set_tunable = rtl8152_set_tunable, 5305 .get_ringparam = rtl8152_get_ringparam, 5306 .set_ringparam = rtl8152_set_ringparam, 5307 }; 5308 5309 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 5310 { 5311 struct r8152 *tp = netdev_priv(netdev); 5312 struct mii_ioctl_data *data = if_mii(rq); 5313 int res; 5314 5315 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5316 return -ENODEV; 5317 5318 res = usb_autopm_get_interface(tp->intf); 5319 if (res < 0) 5320 goto out; 5321 5322 switch (cmd) { 5323 case SIOCGMIIPHY: 5324 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 5325 break; 5326 5327 case SIOCGMIIREG: 5328 mutex_lock(&tp->control); 5329 data->val_out = r8152_mdio_read(tp, data->reg_num); 5330 mutex_unlock(&tp->control); 5331 break; 5332 5333 case SIOCSMIIREG: 5334 if (!capable(CAP_NET_ADMIN)) { 5335 res = -EPERM; 5336 break; 5337 } 5338 mutex_lock(&tp->control); 5339 r8152_mdio_write(tp, data->reg_num, data->val_in); 5340 mutex_unlock(&tp->control); 5341 break; 5342 5343 default: 5344 res = -EOPNOTSUPP; 5345 } 5346 5347 usb_autopm_put_interface(tp->intf); 5348 5349 out: 5350 return res; 5351 } 5352 5353 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 5354 { 5355 struct r8152 *tp = netdev_priv(dev); 5356 int ret; 5357 5358 switch (tp->version) { 5359 case RTL_VER_01: 5360 case RTL_VER_02: 5361 case RTL_VER_07: 5362 dev->mtu = new_mtu; 5363 return 0; 5364 default: 5365 break; 5366 } 5367 5368 ret = usb_autopm_get_interface(tp->intf); 5369 if (ret < 0) 5370 return ret; 5371 5372 mutex_lock(&tp->control); 5373 5374 dev->mtu = new_mtu; 5375 5376 if (netif_running(dev)) { 5377 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 5378 5379 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms); 5380 5381 if (netif_carrier_ok(dev)) 5382 r8153_set_rx_early_size(tp); 5383 } 5384 5385 mutex_unlock(&tp->control); 5386 5387 usb_autopm_put_interface(tp->intf); 5388 5389 return ret; 5390 } 5391 5392 static const struct net_device_ops rtl8152_netdev_ops = { 5393 .ndo_open = rtl8152_open, 5394 .ndo_stop = rtl8152_close, 5395 .ndo_do_ioctl = rtl8152_ioctl, 5396 .ndo_start_xmit = rtl8152_start_xmit, 5397 .ndo_tx_timeout = rtl8152_tx_timeout, 5398 .ndo_set_features = rtl8152_set_features, 5399 .ndo_set_rx_mode = rtl8152_set_rx_mode, 5400 .ndo_set_mac_address = rtl8152_set_mac_address, 5401 .ndo_change_mtu = rtl8152_change_mtu, 5402 .ndo_validate_addr = eth_validate_addr, 5403 .ndo_features_check = rtl8152_features_check, 5404 }; 5405 5406 static void rtl8152_unload(struct r8152 *tp) 5407 { 5408 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5409 return; 5410 5411 if (tp->version != RTL_VER_01) 5412 r8152_power_cut_en(tp, true); 5413 } 5414 5415 static void rtl8153_unload(struct r8152 *tp) 5416 { 5417 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5418 return; 5419 5420 r8153_power_cut_en(tp, false); 5421 } 5422 5423 static void rtl8153b_unload(struct r8152 *tp) 5424 { 5425 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 5426 return; 5427 5428 r8153b_power_cut_en(tp, false); 5429 } 5430 5431 static int rtl_ops_init(struct r8152 *tp) 5432 { 5433 struct rtl_ops *ops = &tp->rtl_ops; 5434 int ret = 0; 5435 5436 switch (tp->version) { 5437 case RTL_VER_01: 5438 case RTL_VER_02: 5439 case RTL_VER_07: 5440 ops->init = r8152b_init; 5441 ops->enable = rtl8152_enable; 5442 ops->disable = rtl8152_disable; 5443 ops->up = rtl8152_up; 5444 ops->down = rtl8152_down; 5445 ops->unload = rtl8152_unload; 5446 ops->eee_get = r8152_get_eee; 5447 ops->eee_set = r8152_set_eee; 5448 ops->in_nway = rtl8152_in_nway; 5449 ops->hw_phy_cfg = r8152b_hw_phy_cfg; 5450 ops->autosuspend_en = rtl_runtime_suspend_enable; 5451 tp->rx_buf_sz = 16 * 1024; 5452 tp->eee_en = true; 5453 tp->eee_adv = MDIO_EEE_100TX; 5454 break; 5455 5456 case RTL_VER_03: 5457 case RTL_VER_04: 5458 case RTL_VER_05: 5459 case RTL_VER_06: 5460 ops->init = r8153_init; 5461 ops->enable = rtl8153_enable; 5462 ops->disable = rtl8153_disable; 5463 ops->up = rtl8153_up; 5464 ops->down = rtl8153_down; 5465 ops->unload = rtl8153_unload; 5466 ops->eee_get = r8153_get_eee; 5467 ops->eee_set = r8152_set_eee; 5468 ops->in_nway = rtl8153_in_nway; 5469 ops->hw_phy_cfg = r8153_hw_phy_cfg; 5470 ops->autosuspend_en = rtl8153_runtime_enable; 5471 tp->rx_buf_sz = 32 * 1024; 5472 tp->eee_en = true; 5473 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 5474 break; 5475 5476 case RTL_VER_08: 5477 case RTL_VER_09: 5478 ops->init = r8153b_init; 5479 ops->enable = rtl8153_enable; 5480 ops->disable = rtl8153_disable; 5481 ops->up = rtl8153b_up; 5482 ops->down = rtl8153b_down; 5483 ops->unload = rtl8153b_unload; 5484 ops->eee_get = r8153_get_eee; 5485 ops->eee_set = r8152_set_eee; 5486 ops->in_nway = rtl8153_in_nway; 5487 ops->hw_phy_cfg = r8153b_hw_phy_cfg; 5488 ops->autosuspend_en = rtl8153b_runtime_enable; 5489 tp->rx_buf_sz = 32 * 1024; 5490 tp->eee_en = true; 5491 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 5492 break; 5493 5494 default: 5495 ret = -ENODEV; 5496 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 5497 break; 5498 } 5499 5500 return ret; 5501 } 5502 5503 static u8 rtl_get_version(struct usb_interface *intf) 5504 { 5505 struct usb_device *udev = interface_to_usbdev(intf); 5506 u32 ocp_data = 0; 5507 __le32 *tmp; 5508 u8 version; 5509 int ret; 5510 5511 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); 5512 if (!tmp) 5513 return 0; 5514 5515 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 5516 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 5517 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500); 5518 if (ret > 0) 5519 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK; 5520 5521 kfree(tmp); 5522 5523 switch (ocp_data) { 5524 case 0x4c00: 5525 version = RTL_VER_01; 5526 break; 5527 case 0x4c10: 5528 version = RTL_VER_02; 5529 break; 5530 case 0x5c00: 5531 version = RTL_VER_03; 5532 break; 5533 case 0x5c10: 5534 version = RTL_VER_04; 5535 break; 5536 case 0x5c20: 5537 version = RTL_VER_05; 5538 break; 5539 case 0x5c30: 5540 version = RTL_VER_06; 5541 break; 5542 case 0x4800: 5543 version = RTL_VER_07; 5544 break; 5545 case 0x6000: 5546 version = RTL_VER_08; 5547 break; 5548 case 0x6010: 5549 version = RTL_VER_09; 5550 break; 5551 default: 5552 version = RTL_VER_UNKNOWN; 5553 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); 5554 break; 5555 } 5556 5557 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); 5558 5559 return version; 5560 } 5561 5562 static int rtl8152_probe(struct usb_interface *intf, 5563 const struct usb_device_id *id) 5564 { 5565 struct usb_device *udev = interface_to_usbdev(intf); 5566 u8 version = rtl_get_version(intf); 5567 struct r8152 *tp; 5568 struct net_device *netdev; 5569 int ret; 5570 5571 if (version == RTL_VER_UNKNOWN) 5572 return -ENODEV; 5573 5574 if (udev->actconfig->desc.bConfigurationValue != 1) { 5575 usb_driver_set_configuration(udev, 1); 5576 return -ENODEV; 5577 } 5578 5579 usb_reset_device(udev); 5580 netdev = alloc_etherdev(sizeof(struct r8152)); 5581 if (!netdev) { 5582 dev_err(&intf->dev, "Out of memory\n"); 5583 return -ENOMEM; 5584 } 5585 5586 SET_NETDEV_DEV(netdev, &intf->dev); 5587 tp = netdev_priv(netdev); 5588 tp->msg_enable = 0x7FFF; 5589 5590 tp->udev = udev; 5591 tp->netdev = netdev; 5592 tp->intf = intf; 5593 tp->version = version; 5594 5595 switch (version) { 5596 case RTL_VER_01: 5597 case RTL_VER_02: 5598 case RTL_VER_07: 5599 tp->mii.supports_gmii = 0; 5600 break; 5601 default: 5602 tp->mii.supports_gmii = 1; 5603 break; 5604 } 5605 5606 ret = rtl_ops_init(tp); 5607 if (ret) 5608 goto out; 5609 5610 mutex_init(&tp->control); 5611 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 5612 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); 5613 tasklet_init(&tp->tx_tl, bottom_half, (unsigned long)tp); 5614 tasklet_disable(&tp->tx_tl); 5615 5616 netdev->netdev_ops = &rtl8152_netdev_ops; 5617 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 5618 5619 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5620 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 5621 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 5622 NETIF_F_HW_VLAN_CTAG_TX; 5623 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 5624 NETIF_F_TSO | NETIF_F_FRAGLIST | 5625 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 5626 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; 5627 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 5628 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 5629 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 5630 5631 if (tp->version == RTL_VER_01) { 5632 netdev->features &= ~NETIF_F_RXCSUM; 5633 netdev->hw_features &= ~NETIF_F_RXCSUM; 5634 } 5635 5636 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial && 5637 (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) { 5638 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation"); 5639 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags); 5640 } 5641 5642 netdev->ethtool_ops = &ops; 5643 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 5644 5645 /* MTU range: 68 - 1500 or 9194 */ 5646 netdev->min_mtu = ETH_MIN_MTU; 5647 switch (tp->version) { 5648 case RTL_VER_01: 5649 case RTL_VER_02: 5650 netdev->max_mtu = ETH_DATA_LEN; 5651 break; 5652 default: 5653 netdev->max_mtu = RTL8153_MAX_MTU; 5654 break; 5655 } 5656 5657 tp->mii.dev = netdev; 5658 tp->mii.mdio_read = read_mii_word; 5659 tp->mii.mdio_write = write_mii_word; 5660 tp->mii.phy_id_mask = 0x3f; 5661 tp->mii.reg_num_mask = 0x1f; 5662 tp->mii.phy_id = R8152_PHY_ID; 5663 5664 tp->autoneg = AUTONEG_ENABLE; 5665 tp->speed = SPEED_100; 5666 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL | 5667 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL; 5668 if (tp->mii.supports_gmii) { 5669 tp->speed = SPEED_1000; 5670 tp->advertising |= RTL_ADVERTISED_1000_FULL; 5671 } 5672 tp->duplex = DUPLEX_FULL; 5673 5674 tp->rx_copybreak = RTL8152_RXFG_HEADSZ; 5675 tp->rx_pending = 10 * RTL8152_MAX_RX; 5676 5677 intf->needs_remote_wakeup = 1; 5678 5679 tp->rtl_ops.init(tp); 5680 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 5681 set_ethernet_addr(tp); 5682 5683 usb_set_intfdata(intf, tp); 5684 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); 5685 5686 ret = register_netdev(netdev); 5687 if (ret != 0) { 5688 netif_err(tp, probe, netdev, "couldn't register the device\n"); 5689 goto out1; 5690 } 5691 5692 if (!rtl_can_wakeup(tp)) 5693 __rtl_set_wol(tp, 0); 5694 5695 tp->saved_wolopts = __rtl_get_wol(tp); 5696 if (tp->saved_wolopts) 5697 device_set_wakeup_enable(&udev->dev, true); 5698 else 5699 device_set_wakeup_enable(&udev->dev, false); 5700 5701 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 5702 5703 return 0; 5704 5705 out1: 5706 tasklet_kill(&tp->tx_tl); 5707 usb_set_intfdata(intf, NULL); 5708 out: 5709 free_netdev(netdev); 5710 return ret; 5711 } 5712 5713 static void rtl8152_disconnect(struct usb_interface *intf) 5714 { 5715 struct r8152 *tp = usb_get_intfdata(intf); 5716 5717 usb_set_intfdata(intf, NULL); 5718 if (tp) { 5719 rtl_set_unplug(tp); 5720 5721 unregister_netdev(tp->netdev); 5722 tasklet_kill(&tp->tx_tl); 5723 cancel_delayed_work_sync(&tp->hw_phy_work); 5724 tp->rtl_ops.unload(tp); 5725 free_netdev(tp->netdev); 5726 } 5727 } 5728 5729 #define REALTEK_USB_DEVICE(vend, prod) \ 5730 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ 5731 USB_DEVICE_ID_MATCH_INT_CLASS, \ 5732 .idVendor = (vend), \ 5733 .idProduct = (prod), \ 5734 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ 5735 }, \ 5736 { \ 5737 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ 5738 USB_DEVICE_ID_MATCH_DEVICE, \ 5739 .idVendor = (vend), \ 5740 .idProduct = (prod), \ 5741 .bInterfaceClass = USB_CLASS_COMM, \ 5742 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ 5743 .bInterfaceProtocol = USB_CDC_PROTO_NONE 5744 5745 /* table of devices that work with this driver */ 5746 static const struct usb_device_id rtl8152_table[] = { 5747 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)}, 5748 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, 5749 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, 5750 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)}, 5751 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)}, 5752 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, 5753 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, 5754 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)}, 5755 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)}, 5756 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, 5757 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)}, 5758 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)}, 5759 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)}, 5760 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, 5761 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)}, 5762 {} 5763 }; 5764 5765 MODULE_DEVICE_TABLE(usb, rtl8152_table); 5766 5767 static struct usb_driver rtl8152_driver = { 5768 .name = MODULENAME, 5769 .id_table = rtl8152_table, 5770 .probe = rtl8152_probe, 5771 .disconnect = rtl8152_disconnect, 5772 .suspend = rtl8152_suspend, 5773 .resume = rtl8152_resume, 5774 .reset_resume = rtl8152_reset_resume, 5775 .pre_reset = rtl8152_pre_reset, 5776 .post_reset = rtl8152_post_reset, 5777 .supports_autosuspend = 1, 5778 .disable_hub_initiated_lpm = 1, 5779 }; 5780 5781 module_usb_driver(rtl8152_driver); 5782 5783 MODULE_AUTHOR(DRIVER_AUTHOR); 5784 MODULE_DESCRIPTION(DRIVER_DESC); 5785 MODULE_LICENSE("GPL"); 5786 MODULE_VERSION(DRIVER_VERSION); 5787