1 /* 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2 as published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/signal.h> 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/usb.h> 18 #include <linux/crc32.h> 19 #include <linux/if_vlan.h> 20 #include <linux/uaccess.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include <net/ip6_checksum.h> 25 #include <uapi/linux/mdio.h> 26 #include <linux/mdio.h> 27 #include <linux/usb/cdc.h> 28 29 /* Information for net-next */ 30 #define NETNEXT_VERSION "08" 31 32 /* Information for net */ 33 #define NET_VERSION "2" 34 35 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION 36 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 37 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 38 #define MODULENAME "r8152" 39 40 #define R8152_PHY_ID 32 41 42 #define PLA_IDR 0xc000 43 #define PLA_RCR 0xc010 44 #define PLA_RMS 0xc016 45 #define PLA_RXFIFO_CTRL0 0xc0a0 46 #define PLA_RXFIFO_CTRL1 0xc0a4 47 #define PLA_RXFIFO_CTRL2 0xc0a8 48 #define PLA_DMY_REG0 0xc0b0 49 #define PLA_FMC 0xc0b4 50 #define PLA_CFG_WOL 0xc0b6 51 #define PLA_TEREDO_CFG 0xc0bc 52 #define PLA_MAR 0xcd00 53 #define PLA_BACKUP 0xd000 54 #define PAL_BDC_CR 0xd1a0 55 #define PLA_TEREDO_TIMER 0xd2cc 56 #define PLA_REALWOW_TIMER 0xd2e8 57 #define PLA_LEDSEL 0xdd90 58 #define PLA_LED_FEATURE 0xdd92 59 #define PLA_PHYAR 0xde00 60 #define PLA_BOOT_CTRL 0xe004 61 #define PLA_GPHY_INTR_IMR 0xe022 62 #define PLA_EEE_CR 0xe040 63 #define PLA_EEEP_CR 0xe080 64 #define PLA_MAC_PWR_CTRL 0xe0c0 65 #define PLA_MAC_PWR_CTRL2 0xe0ca 66 #define PLA_MAC_PWR_CTRL3 0xe0cc 67 #define PLA_MAC_PWR_CTRL4 0xe0ce 68 #define PLA_WDT6_CTRL 0xe428 69 #define PLA_TCR0 0xe610 70 #define PLA_TCR1 0xe612 71 #define PLA_MTPS 0xe615 72 #define PLA_TXFIFO_CTRL 0xe618 73 #define PLA_RSTTALLY 0xe800 74 #define PLA_CR 0xe813 75 #define PLA_CRWECR 0xe81c 76 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 77 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 78 #define PLA_CONFIG5 0xe822 79 #define PLA_PHY_PWR 0xe84c 80 #define PLA_OOB_CTRL 0xe84f 81 #define PLA_CPCR 0xe854 82 #define PLA_MISC_0 0xe858 83 #define PLA_MISC_1 0xe85a 84 #define PLA_OCP_GPHY_BASE 0xe86c 85 #define PLA_TALLYCNT 0xe890 86 #define PLA_SFF_STS_7 0xe8de 87 #define PLA_PHYSTATUS 0xe908 88 #define PLA_BP_BA 0xfc26 89 #define PLA_BP_0 0xfc28 90 #define PLA_BP_1 0xfc2a 91 #define PLA_BP_2 0xfc2c 92 #define PLA_BP_3 0xfc2e 93 #define PLA_BP_4 0xfc30 94 #define PLA_BP_5 0xfc32 95 #define PLA_BP_6 0xfc34 96 #define PLA_BP_7 0xfc36 97 #define PLA_BP_EN 0xfc38 98 99 #define USB_USB2PHY 0xb41e 100 #define USB_SSPHYLINK2 0xb428 101 #define USB_U2P3_CTRL 0xb460 102 #define USB_CSR_DUMMY1 0xb464 103 #define USB_CSR_DUMMY2 0xb466 104 #define USB_DEV_STAT 0xb808 105 #define USB_CONNECT_TIMER 0xcbf8 106 #define USB_BURST_SIZE 0xcfc0 107 #define USB_USB_CTRL 0xd406 108 #define USB_PHY_CTRL 0xd408 109 #define USB_TX_AGG 0xd40a 110 #define USB_RX_BUF_TH 0xd40c 111 #define USB_USB_TIMER 0xd428 112 #define USB_RX_EARLY_TIMEOUT 0xd42c 113 #define USB_RX_EARLY_SIZE 0xd42e 114 #define USB_PM_CTRL_STATUS 0xd432 115 #define USB_TX_DMA 0xd434 116 #define USB_TOLERANCE 0xd490 117 #define USB_LPM_CTRL 0xd41a 118 #define USB_UPS_CTRL 0xd800 119 #define USB_MISC_0 0xd81a 120 #define USB_POWER_CUT 0xd80a 121 #define USB_AFE_CTRL2 0xd824 122 #define USB_WDT11_CTRL 0xe43c 123 #define USB_BP_BA 0xfc26 124 #define USB_BP_0 0xfc28 125 #define USB_BP_1 0xfc2a 126 #define USB_BP_2 0xfc2c 127 #define USB_BP_3 0xfc2e 128 #define USB_BP_4 0xfc30 129 #define USB_BP_5 0xfc32 130 #define USB_BP_6 0xfc34 131 #define USB_BP_7 0xfc36 132 #define USB_BP_EN 0xfc38 133 134 /* OCP Registers */ 135 #define OCP_ALDPS_CONFIG 0x2010 136 #define OCP_EEE_CONFIG1 0x2080 137 #define OCP_EEE_CONFIG2 0x2092 138 #define OCP_EEE_CONFIG3 0x2094 139 #define OCP_BASE_MII 0xa400 140 #define OCP_EEE_AR 0xa41a 141 #define OCP_EEE_DATA 0xa41c 142 #define OCP_PHY_STATUS 0xa420 143 #define OCP_POWER_CFG 0xa430 144 #define OCP_EEE_CFG 0xa432 145 #define OCP_SRAM_ADDR 0xa436 146 #define OCP_SRAM_DATA 0xa438 147 #define OCP_DOWN_SPEED 0xa442 148 #define OCP_EEE_ABLE 0xa5c4 149 #define OCP_EEE_ADV 0xa5d0 150 #define OCP_EEE_LPABLE 0xa5d2 151 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ 152 #define OCP_ADC_CFG 0xbc06 153 154 /* SRAM Register */ 155 #define SRAM_LPF_CFG 0x8012 156 #define SRAM_10M_AMP1 0x8080 157 #define SRAM_10M_AMP2 0x8082 158 #define SRAM_IMPEDANCE 0x8084 159 160 /* PLA_RCR */ 161 #define RCR_AAP 0x00000001 162 #define RCR_APM 0x00000002 163 #define RCR_AM 0x00000004 164 #define RCR_AB 0x00000008 165 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 166 167 /* PLA_RXFIFO_CTRL0 */ 168 #define RXFIFO_THR1_NORMAL 0x00080002 169 #define RXFIFO_THR1_OOB 0x01800003 170 171 /* PLA_RXFIFO_CTRL1 */ 172 #define RXFIFO_THR2_FULL 0x00000060 173 #define RXFIFO_THR2_HIGH 0x00000038 174 #define RXFIFO_THR2_OOB 0x0000004a 175 #define RXFIFO_THR2_NORMAL 0x00a0 176 177 /* PLA_RXFIFO_CTRL2 */ 178 #define RXFIFO_THR3_FULL 0x00000078 179 #define RXFIFO_THR3_HIGH 0x00000048 180 #define RXFIFO_THR3_OOB 0x0000005a 181 #define RXFIFO_THR3_NORMAL 0x0110 182 183 /* PLA_TXFIFO_CTRL */ 184 #define TXFIFO_THR_NORMAL 0x00400008 185 #define TXFIFO_THR_NORMAL2 0x01000008 186 187 /* PLA_DMY_REG0 */ 188 #define ECM_ALDPS 0x0002 189 190 /* PLA_FMC */ 191 #define FMC_FCR_MCU_EN 0x0001 192 193 /* PLA_EEEP_CR */ 194 #define EEEP_CR_EEEP_TX 0x0002 195 196 /* PLA_WDT6_CTRL */ 197 #define WDT6_SET_MODE 0x0010 198 199 /* PLA_TCR0 */ 200 #define TCR0_TX_EMPTY 0x0800 201 #define TCR0_AUTO_FIFO 0x0080 202 203 /* PLA_TCR1 */ 204 #define VERSION_MASK 0x7cf0 205 206 /* PLA_MTPS */ 207 #define MTPS_JUMBO (12 * 1024 / 64) 208 #define MTPS_DEFAULT (6 * 1024 / 64) 209 210 /* PLA_RSTTALLY */ 211 #define TALLY_RESET 0x0001 212 213 /* PLA_CR */ 214 #define CR_RST 0x10 215 #define CR_RE 0x08 216 #define CR_TE 0x04 217 218 /* PLA_CRWECR */ 219 #define CRWECR_NORAML 0x00 220 #define CRWECR_CONFIG 0xc0 221 222 /* PLA_OOB_CTRL */ 223 #define NOW_IS_OOB 0x80 224 #define TXFIFO_EMPTY 0x20 225 #define RXFIFO_EMPTY 0x10 226 #define LINK_LIST_READY 0x02 227 #define DIS_MCU_CLROOB 0x01 228 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 229 230 /* PLA_MISC_1 */ 231 #define RXDY_GATED_EN 0x0008 232 233 /* PLA_SFF_STS_7 */ 234 #define RE_INIT_LL 0x8000 235 #define MCU_BORW_EN 0x4000 236 237 /* PLA_CPCR */ 238 #define CPCR_RX_VLAN 0x0040 239 240 /* PLA_CFG_WOL */ 241 #define MAGIC_EN 0x0001 242 243 /* PLA_TEREDO_CFG */ 244 #define TEREDO_SEL 0x8000 245 #define TEREDO_WAKE_MASK 0x7f00 246 #define TEREDO_RS_EVENT_MASK 0x00fe 247 #define OOB_TEREDO_EN 0x0001 248 249 /* PAL_BDC_CR */ 250 #define ALDPS_PROXY_MODE 0x0001 251 252 /* PLA_CONFIG34 */ 253 #define LINK_ON_WAKE_EN 0x0010 254 #define LINK_OFF_WAKE_EN 0x0008 255 256 /* PLA_CONFIG5 */ 257 #define BWF_EN 0x0040 258 #define MWF_EN 0x0020 259 #define UWF_EN 0x0010 260 #define LAN_WAKE_EN 0x0002 261 262 /* PLA_LED_FEATURE */ 263 #define LED_MODE_MASK 0x0700 264 265 /* PLA_PHY_PWR */ 266 #define TX_10M_IDLE_EN 0x0080 267 #define PFM_PWM_SWITCH 0x0040 268 269 /* PLA_MAC_PWR_CTRL */ 270 #define D3_CLK_GATED_EN 0x00004000 271 #define MCU_CLK_RATIO 0x07010f07 272 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 273 #define ALDPS_SPDWN_RATIO 0x0f87 274 275 /* PLA_MAC_PWR_CTRL2 */ 276 #define EEE_SPDWN_RATIO 0x8007 277 278 /* PLA_MAC_PWR_CTRL3 */ 279 #define PKT_AVAIL_SPDWN_EN 0x0100 280 #define SUSPEND_SPDWN_EN 0x0004 281 #define U1U2_SPDWN_EN 0x0002 282 #define L1_SPDWN_EN 0x0001 283 284 /* PLA_MAC_PWR_CTRL4 */ 285 #define PWRSAVE_SPDWN_EN 0x1000 286 #define RXDV_SPDWN_EN 0x0800 287 #define TX10MIDLE_EN 0x0100 288 #define TP100_SPDWN_EN 0x0020 289 #define TP500_SPDWN_EN 0x0010 290 #define TP1000_SPDWN_EN 0x0008 291 #define EEE_SPDWN_EN 0x0001 292 293 /* PLA_GPHY_INTR_IMR */ 294 #define GPHY_STS_MSK 0x0001 295 #define SPEED_DOWN_MSK 0x0002 296 #define SPDWN_RXDV_MSK 0x0004 297 #define SPDWN_LINKCHG_MSK 0x0008 298 299 /* PLA_PHYAR */ 300 #define PHYAR_FLAG 0x80000000 301 302 /* PLA_EEE_CR */ 303 #define EEE_RX_EN 0x0001 304 #define EEE_TX_EN 0x0002 305 306 /* PLA_BOOT_CTRL */ 307 #define AUTOLOAD_DONE 0x0002 308 309 /* USB_USB2PHY */ 310 #define USB2PHY_SUSPEND 0x0001 311 #define USB2PHY_L1 0x0002 312 313 /* USB_SSPHYLINK2 */ 314 #define pwd_dn_scale_mask 0x3ffe 315 #define pwd_dn_scale(x) ((x) << 1) 316 317 /* USB_CSR_DUMMY1 */ 318 #define DYNAMIC_BURST 0x0001 319 320 /* USB_CSR_DUMMY2 */ 321 #define EP4_FULL_FC 0x0001 322 323 /* USB_DEV_STAT */ 324 #define STAT_SPEED_MASK 0x0006 325 #define STAT_SPEED_HIGH 0x0000 326 #define STAT_SPEED_FULL 0x0002 327 328 /* USB_TX_AGG */ 329 #define TX_AGG_MAX_THRESHOLD 0x03 330 331 /* USB_RX_BUF_TH */ 332 #define RX_THR_SUPPER 0x0c350180 333 #define RX_THR_HIGH 0x7a120180 334 #define RX_THR_SLOW 0xffff0180 335 336 /* USB_TX_DMA */ 337 #define TEST_MODE_DISABLE 0x00000001 338 #define TX_SIZE_ADJUST1 0x00000100 339 340 /* USB_UPS_CTRL */ 341 #define POWER_CUT 0x0100 342 343 /* USB_PM_CTRL_STATUS */ 344 #define RESUME_INDICATE 0x0001 345 346 /* USB_USB_CTRL */ 347 #define RX_AGG_DISABLE 0x0010 348 #define RX_ZERO_EN 0x0080 349 350 /* USB_U2P3_CTRL */ 351 #define U2P3_ENABLE 0x0001 352 353 /* USB_POWER_CUT */ 354 #define PWR_EN 0x0001 355 #define PHASE2_EN 0x0008 356 357 /* USB_MISC_0 */ 358 #define PCUT_STATUS 0x0001 359 360 /* USB_RX_EARLY_TIMEOUT */ 361 #define COALESCE_SUPER 85000U 362 #define COALESCE_HIGH 250000U 363 #define COALESCE_SLOW 524280U 364 365 /* USB_WDT11_CTRL */ 366 #define TIMER11_EN 0x0001 367 368 /* USB_LPM_CTRL */ 369 /* bit 4 ~ 5: fifo empty boundary */ 370 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 371 /* bit 2 ~ 3: LMP timer */ 372 #define LPM_TIMER_MASK 0x0c 373 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 374 #define LPM_TIMER_500US 0x0c /* 500 us */ 375 #define ROK_EXIT_LPM 0x02 376 377 /* USB_AFE_CTRL2 */ 378 #define SEN_VAL_MASK 0xf800 379 #define SEN_VAL_NORMAL 0xa000 380 #define SEL_RXIDLE 0x0100 381 382 /* OCP_ALDPS_CONFIG */ 383 #define ENPWRSAVE 0x8000 384 #define ENPDNPS 0x0200 385 #define LINKENA 0x0100 386 #define DIS_SDSAVE 0x0010 387 388 /* OCP_PHY_STATUS */ 389 #define PHY_STAT_MASK 0x0007 390 #define PHY_STAT_LAN_ON 3 391 #define PHY_STAT_PWRDN 5 392 393 /* OCP_POWER_CFG */ 394 #define EEE_CLKDIV_EN 0x8000 395 #define EN_ALDPS 0x0004 396 #define EN_10M_PLLOFF 0x0001 397 398 /* OCP_EEE_CONFIG1 */ 399 #define RG_TXLPI_MSK_HFDUP 0x8000 400 #define RG_MATCLR_EN 0x4000 401 #define EEE_10_CAP 0x2000 402 #define EEE_NWAY_EN 0x1000 403 #define TX_QUIET_EN 0x0200 404 #define RX_QUIET_EN 0x0100 405 #define sd_rise_time_mask 0x0070 406 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 407 #define RG_RXLPI_MSK_HFDUP 0x0008 408 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 409 410 /* OCP_EEE_CONFIG2 */ 411 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 412 #define RG_DACQUIET_EN 0x0400 413 #define RG_LDVQUIET_EN 0x0200 414 #define RG_CKRSEL 0x0020 415 #define RG_EEEPRG_EN 0x0010 416 417 /* OCP_EEE_CONFIG3 */ 418 #define fast_snr_mask 0xff80 419 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 420 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 421 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 422 423 /* OCP_EEE_AR */ 424 /* bit[15:14] function */ 425 #define FUN_ADDR 0x0000 426 #define FUN_DATA 0x4000 427 /* bit[4:0] device addr */ 428 429 /* OCP_EEE_CFG */ 430 #define CTAP_SHORT_EN 0x0040 431 #define EEE10_EN 0x0010 432 433 /* OCP_DOWN_SPEED */ 434 #define EN_10M_BGOFF 0x0080 435 436 /* OCP_PHY_STATE */ 437 #define TXDIS_STATE 0x01 438 #define ABD_STATE 0x02 439 440 /* OCP_ADC_CFG */ 441 #define CKADSEL_L 0x0100 442 #define ADC_EN 0x0080 443 #define EN_EMI_L 0x0040 444 445 /* SRAM_LPF_CFG */ 446 #define LPF_AUTO_TUNE 0x8000 447 448 /* SRAM_10M_AMP1 */ 449 #define GDAC_IB_UPALL 0x0008 450 451 /* SRAM_10M_AMP2 */ 452 #define AMP_DN 0x0200 453 454 /* SRAM_IMPEDANCE */ 455 #define RX_DRIVING_MASK 0x6000 456 457 enum rtl_register_content { 458 _1000bps = 0x10, 459 _100bps = 0x08, 460 _10bps = 0x04, 461 LINK_STATUS = 0x02, 462 FULL_DUP = 0x01, 463 }; 464 465 #define RTL8152_MAX_TX 4 466 #define RTL8152_MAX_RX 10 467 #define INTBUFSIZE 2 468 #define CRC_SIZE 4 469 #define TX_ALIGN 4 470 #define RX_ALIGN 8 471 472 #define INTR_LINK 0x0004 473 474 #define RTL8152_REQT_READ 0xc0 475 #define RTL8152_REQT_WRITE 0x40 476 #define RTL8152_REQ_GET_REGS 0x05 477 #define RTL8152_REQ_SET_REGS 0x05 478 479 #define BYTE_EN_DWORD 0xff 480 #define BYTE_EN_WORD 0x33 481 #define BYTE_EN_BYTE 0x11 482 #define BYTE_EN_SIX_BYTES 0x3f 483 #define BYTE_EN_START_MASK 0x0f 484 #define BYTE_EN_END_MASK 0xf0 485 486 #define RTL8153_MAX_PACKET 9216 /* 9K */ 487 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN) 488 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) 489 #define RTL8153_RMS RTL8153_MAX_PACKET 490 #define RTL8152_TX_TIMEOUT (5 * HZ) 491 #define RTL8152_NAPI_WEIGHT 64 492 493 /* rtl8152 flags */ 494 enum rtl8152_flags { 495 RTL8152_UNPLUG = 0, 496 RTL8152_SET_RX_MODE, 497 WORK_ENABLE, 498 RTL8152_LINK_CHG, 499 SELECTIVE_SUSPEND, 500 PHY_RESET, 501 SCHEDULE_NAPI, 502 }; 503 504 /* Define these values to match your device */ 505 #define VENDOR_ID_REALTEK 0x0bda 506 #define VENDOR_ID_SAMSUNG 0x04e8 507 #define VENDOR_ID_LENOVO 0x17ef 508 #define VENDOR_ID_NVIDIA 0x0955 509 510 #define MCU_TYPE_PLA 0x0100 511 #define MCU_TYPE_USB 0x0000 512 513 struct tally_counter { 514 __le64 tx_packets; 515 __le64 rx_packets; 516 __le64 tx_errors; 517 __le32 rx_errors; 518 __le16 rx_missed; 519 __le16 align_errors; 520 __le32 tx_one_collision; 521 __le32 tx_multi_collision; 522 __le64 rx_unicast; 523 __le64 rx_broadcast; 524 __le32 rx_multicast; 525 __le16 tx_aborted; 526 __le16 tx_underrun; 527 }; 528 529 struct rx_desc { 530 __le32 opts1; 531 #define RX_LEN_MASK 0x7fff 532 533 __le32 opts2; 534 #define RD_UDP_CS BIT(23) 535 #define RD_TCP_CS BIT(22) 536 #define RD_IPV6_CS BIT(20) 537 #define RD_IPV4_CS BIT(19) 538 539 __le32 opts3; 540 #define IPF BIT(23) /* IP checksum fail */ 541 #define UDPF BIT(22) /* UDP checksum fail */ 542 #define TCPF BIT(21) /* TCP checksum fail */ 543 #define RX_VLAN_TAG BIT(16) 544 545 __le32 opts4; 546 __le32 opts5; 547 __le32 opts6; 548 }; 549 550 struct tx_desc { 551 __le32 opts1; 552 #define TX_FS BIT(31) /* First segment of a packet */ 553 #define TX_LS BIT(30) /* Final segment of a packet */ 554 #define GTSENDV4 BIT(28) 555 #define GTSENDV6 BIT(27) 556 #define GTTCPHO_SHIFT 18 557 #define GTTCPHO_MAX 0x7fU 558 #define TX_LEN_MAX 0x3ffffU 559 560 __le32 opts2; 561 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 562 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 563 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 564 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 565 #define MSS_SHIFT 17 566 #define MSS_MAX 0x7ffU 567 #define TCPHO_SHIFT 17 568 #define TCPHO_MAX 0x7ffU 569 #define TX_VLAN_TAG BIT(16) 570 }; 571 572 struct r8152; 573 574 struct rx_agg { 575 struct list_head list; 576 struct urb *urb; 577 struct r8152 *context; 578 void *buffer; 579 void *head; 580 }; 581 582 struct tx_agg { 583 struct list_head list; 584 struct urb *urb; 585 struct r8152 *context; 586 void *buffer; 587 void *head; 588 u32 skb_num; 589 u32 skb_len; 590 }; 591 592 struct r8152 { 593 unsigned long flags; 594 struct usb_device *udev; 595 struct napi_struct napi; 596 struct usb_interface *intf; 597 struct net_device *netdev; 598 struct urb *intr_urb; 599 struct tx_agg tx_info[RTL8152_MAX_TX]; 600 struct rx_agg rx_info[RTL8152_MAX_RX]; 601 struct list_head rx_done, tx_free; 602 struct sk_buff_head tx_queue, rx_queue; 603 spinlock_t rx_lock, tx_lock; 604 struct delayed_work schedule; 605 struct mii_if_info mii; 606 struct mutex control; /* use for hw setting */ 607 608 struct rtl_ops { 609 void (*init)(struct r8152 *); 610 int (*enable)(struct r8152 *); 611 void (*disable)(struct r8152 *); 612 void (*up)(struct r8152 *); 613 void (*down)(struct r8152 *); 614 void (*unload)(struct r8152 *); 615 int (*eee_get)(struct r8152 *, struct ethtool_eee *); 616 int (*eee_set)(struct r8152 *, struct ethtool_eee *); 617 bool (*in_nway)(struct r8152 *); 618 } rtl_ops; 619 620 int intr_interval; 621 u32 saved_wolopts; 622 u32 msg_enable; 623 u32 tx_qlen; 624 u32 coalesce; 625 u16 ocp_base; 626 u8 *intr_buff; 627 u8 version; 628 }; 629 630 enum rtl_version { 631 RTL_VER_UNKNOWN = 0, 632 RTL_VER_01, 633 RTL_VER_02, 634 RTL_VER_03, 635 RTL_VER_04, 636 RTL_VER_05, 637 RTL_VER_06, 638 RTL_VER_MAX 639 }; 640 641 enum tx_csum_stat { 642 TX_CSUM_SUCCESS = 0, 643 TX_CSUM_TSO, 644 TX_CSUM_NONE 645 }; 646 647 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 648 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 649 */ 650 static const int multicast_filter_limit = 32; 651 static unsigned int agg_buf_sz = 16384; 652 653 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ 654 VLAN_ETH_HLEN - VLAN_HLEN) 655 656 static 657 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 658 { 659 int ret; 660 void *tmp; 661 662 tmp = kmalloc(size, GFP_KERNEL); 663 if (!tmp) 664 return -ENOMEM; 665 666 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 667 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 668 value, index, tmp, size, 500); 669 670 memcpy(data, tmp, size); 671 kfree(tmp); 672 673 return ret; 674 } 675 676 static 677 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 678 { 679 int ret; 680 void *tmp; 681 682 tmp = kmemdup(data, size, GFP_KERNEL); 683 if (!tmp) 684 return -ENOMEM; 685 686 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 687 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 688 value, index, tmp, size, 500); 689 690 kfree(tmp); 691 692 return ret; 693 } 694 695 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 696 void *data, u16 type) 697 { 698 u16 limit = 64; 699 int ret = 0; 700 701 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 702 return -ENODEV; 703 704 /* both size and indix must be 4 bytes align */ 705 if ((size & 3) || !size || (index & 3) || !data) 706 return -EPERM; 707 708 if ((u32)index + (u32)size > 0xffff) 709 return -EPERM; 710 711 while (size) { 712 if (size > limit) { 713 ret = get_registers(tp, index, type, limit, data); 714 if (ret < 0) 715 break; 716 717 index += limit; 718 data += limit; 719 size -= limit; 720 } else { 721 ret = get_registers(tp, index, type, size, data); 722 if (ret < 0) 723 break; 724 725 index += size; 726 data += size; 727 size = 0; 728 break; 729 } 730 } 731 732 if (ret == -ENODEV) 733 set_bit(RTL8152_UNPLUG, &tp->flags); 734 735 return ret; 736 } 737 738 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 739 u16 size, void *data, u16 type) 740 { 741 int ret; 742 u16 byteen_start, byteen_end, byen; 743 u16 limit = 512; 744 745 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 746 return -ENODEV; 747 748 /* both size and indix must be 4 bytes align */ 749 if ((size & 3) || !size || (index & 3) || !data) 750 return -EPERM; 751 752 if ((u32)index + (u32)size > 0xffff) 753 return -EPERM; 754 755 byteen_start = byteen & BYTE_EN_START_MASK; 756 byteen_end = byteen & BYTE_EN_END_MASK; 757 758 byen = byteen_start | (byteen_start << 4); 759 ret = set_registers(tp, index, type | byen, 4, data); 760 if (ret < 0) 761 goto error1; 762 763 index += 4; 764 data += 4; 765 size -= 4; 766 767 if (size) { 768 size -= 4; 769 770 while (size) { 771 if (size > limit) { 772 ret = set_registers(tp, index, 773 type | BYTE_EN_DWORD, 774 limit, data); 775 if (ret < 0) 776 goto error1; 777 778 index += limit; 779 data += limit; 780 size -= limit; 781 } else { 782 ret = set_registers(tp, index, 783 type | BYTE_EN_DWORD, 784 size, data); 785 if (ret < 0) 786 goto error1; 787 788 index += size; 789 data += size; 790 size = 0; 791 break; 792 } 793 } 794 795 byen = byteen_end | (byteen_end >> 4); 796 ret = set_registers(tp, index, type | byen, 4, data); 797 if (ret < 0) 798 goto error1; 799 } 800 801 error1: 802 if (ret == -ENODEV) 803 set_bit(RTL8152_UNPLUG, &tp->flags); 804 805 return ret; 806 } 807 808 static inline 809 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 810 { 811 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 812 } 813 814 static inline 815 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 816 { 817 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 818 } 819 820 static inline 821 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 822 { 823 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); 824 } 825 826 static inline 827 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 828 { 829 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 830 } 831 832 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 833 { 834 __le32 data; 835 836 generic_ocp_read(tp, index, sizeof(data), &data, type); 837 838 return __le32_to_cpu(data); 839 } 840 841 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 842 { 843 __le32 tmp = __cpu_to_le32(data); 844 845 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 846 } 847 848 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 849 { 850 u32 data; 851 __le32 tmp; 852 u8 shift = index & 2; 853 854 index &= ~3; 855 856 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 857 858 data = __le32_to_cpu(tmp); 859 data >>= (shift * 8); 860 data &= 0xffff; 861 862 return (u16)data; 863 } 864 865 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 866 { 867 u32 mask = 0xffff; 868 __le32 tmp; 869 u16 byen = BYTE_EN_WORD; 870 u8 shift = index & 2; 871 872 data &= mask; 873 874 if (index & 2) { 875 byen <<= shift; 876 mask <<= (shift * 8); 877 data <<= (shift * 8); 878 index &= ~3; 879 } 880 881 tmp = __cpu_to_le32(data); 882 883 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 884 } 885 886 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 887 { 888 u32 data; 889 __le32 tmp; 890 u8 shift = index & 3; 891 892 index &= ~3; 893 894 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 895 896 data = __le32_to_cpu(tmp); 897 data >>= (shift * 8); 898 data &= 0xff; 899 900 return (u8)data; 901 } 902 903 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 904 { 905 u32 mask = 0xff; 906 __le32 tmp; 907 u16 byen = BYTE_EN_BYTE; 908 u8 shift = index & 3; 909 910 data &= mask; 911 912 if (index & 3) { 913 byen <<= shift; 914 mask <<= (shift * 8); 915 data <<= (shift * 8); 916 index &= ~3; 917 } 918 919 tmp = __cpu_to_le32(data); 920 921 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 922 } 923 924 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 925 { 926 u16 ocp_base, ocp_index; 927 928 ocp_base = addr & 0xf000; 929 if (ocp_base != tp->ocp_base) { 930 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 931 tp->ocp_base = ocp_base; 932 } 933 934 ocp_index = (addr & 0x0fff) | 0xb000; 935 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 936 } 937 938 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 939 { 940 u16 ocp_base, ocp_index; 941 942 ocp_base = addr & 0xf000; 943 if (ocp_base != tp->ocp_base) { 944 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 945 tp->ocp_base = ocp_base; 946 } 947 948 ocp_index = (addr & 0x0fff) | 0xb000; 949 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 950 } 951 952 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 953 { 954 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 955 } 956 957 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 958 { 959 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 960 } 961 962 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 963 { 964 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 965 ocp_reg_write(tp, OCP_SRAM_DATA, data); 966 } 967 968 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 969 { 970 struct r8152 *tp = netdev_priv(netdev); 971 int ret; 972 973 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 974 return -ENODEV; 975 976 if (phy_id != R8152_PHY_ID) 977 return -EINVAL; 978 979 ret = r8152_mdio_read(tp, reg); 980 981 return ret; 982 } 983 984 static 985 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 986 { 987 struct r8152 *tp = netdev_priv(netdev); 988 989 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 990 return; 991 992 if (phy_id != R8152_PHY_ID) 993 return; 994 995 r8152_mdio_write(tp, reg, val); 996 } 997 998 static int 999 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 1000 1001 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1002 { 1003 struct r8152 *tp = netdev_priv(netdev); 1004 struct sockaddr *addr = p; 1005 int ret = -EADDRNOTAVAIL; 1006 1007 if (!is_valid_ether_addr(addr->sa_data)) 1008 goto out1; 1009 1010 ret = usb_autopm_get_interface(tp->intf); 1011 if (ret < 0) 1012 goto out1; 1013 1014 mutex_lock(&tp->control); 1015 1016 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1017 1018 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1019 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1020 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1021 1022 mutex_unlock(&tp->control); 1023 1024 usb_autopm_put_interface(tp->intf); 1025 out1: 1026 return ret; 1027 } 1028 1029 static int set_ethernet_addr(struct r8152 *tp) 1030 { 1031 struct net_device *dev = tp->netdev; 1032 struct sockaddr sa; 1033 int ret; 1034 1035 if (tp->version == RTL_VER_01) 1036 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); 1037 else 1038 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); 1039 1040 if (ret < 0) { 1041 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1042 } else if (!is_valid_ether_addr(sa.sa_data)) { 1043 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1044 sa.sa_data); 1045 eth_hw_addr_random(dev); 1046 ether_addr_copy(sa.sa_data, dev->dev_addr); 1047 ret = rtl8152_set_mac_address(dev, &sa); 1048 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1049 sa.sa_data); 1050 } else { 1051 if (tp->version == RTL_VER_01) 1052 ether_addr_copy(dev->dev_addr, sa.sa_data); 1053 else 1054 ret = rtl8152_set_mac_address(dev, &sa); 1055 } 1056 1057 return ret; 1058 } 1059 1060 static void read_bulk_callback(struct urb *urb) 1061 { 1062 struct net_device *netdev; 1063 int status = urb->status; 1064 struct rx_agg *agg; 1065 struct r8152 *tp; 1066 1067 agg = urb->context; 1068 if (!agg) 1069 return; 1070 1071 tp = agg->context; 1072 if (!tp) 1073 return; 1074 1075 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1076 return; 1077 1078 if (!test_bit(WORK_ENABLE, &tp->flags)) 1079 return; 1080 1081 netdev = tp->netdev; 1082 1083 /* When link down, the driver would cancel all bulks. */ 1084 /* This avoid the re-submitting bulk */ 1085 if (!netif_carrier_ok(netdev)) 1086 return; 1087 1088 usb_mark_last_busy(tp->udev); 1089 1090 switch (status) { 1091 case 0: 1092 if (urb->actual_length < ETH_ZLEN) 1093 break; 1094 1095 spin_lock(&tp->rx_lock); 1096 list_add_tail(&agg->list, &tp->rx_done); 1097 spin_unlock(&tp->rx_lock); 1098 napi_schedule(&tp->napi); 1099 return; 1100 case -ESHUTDOWN: 1101 set_bit(RTL8152_UNPLUG, &tp->flags); 1102 netif_device_detach(tp->netdev); 1103 return; 1104 case -ENOENT: 1105 return; /* the urb is in unlink state */ 1106 case -ETIME: 1107 if (net_ratelimit()) 1108 netdev_warn(netdev, "maybe reset is needed?\n"); 1109 break; 1110 default: 1111 if (net_ratelimit()) 1112 netdev_warn(netdev, "Rx status %d\n", status); 1113 break; 1114 } 1115 1116 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1117 } 1118 1119 static void write_bulk_callback(struct urb *urb) 1120 { 1121 struct net_device_stats *stats; 1122 struct net_device *netdev; 1123 struct tx_agg *agg; 1124 struct r8152 *tp; 1125 int status = urb->status; 1126 1127 agg = urb->context; 1128 if (!agg) 1129 return; 1130 1131 tp = agg->context; 1132 if (!tp) 1133 return; 1134 1135 netdev = tp->netdev; 1136 stats = &netdev->stats; 1137 if (status) { 1138 if (net_ratelimit()) 1139 netdev_warn(netdev, "Tx status %d\n", status); 1140 stats->tx_errors += agg->skb_num; 1141 } else { 1142 stats->tx_packets += agg->skb_num; 1143 stats->tx_bytes += agg->skb_len; 1144 } 1145 1146 spin_lock(&tp->tx_lock); 1147 list_add_tail(&agg->list, &tp->tx_free); 1148 spin_unlock(&tp->tx_lock); 1149 1150 usb_autopm_put_interface_async(tp->intf); 1151 1152 if (!netif_carrier_ok(netdev)) 1153 return; 1154 1155 if (!test_bit(WORK_ENABLE, &tp->flags)) 1156 return; 1157 1158 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1159 return; 1160 1161 if (!skb_queue_empty(&tp->tx_queue)) 1162 napi_schedule(&tp->napi); 1163 } 1164 1165 static void intr_callback(struct urb *urb) 1166 { 1167 struct r8152 *tp; 1168 __le16 *d; 1169 int status = urb->status; 1170 int res; 1171 1172 tp = urb->context; 1173 if (!tp) 1174 return; 1175 1176 if (!test_bit(WORK_ENABLE, &tp->flags)) 1177 return; 1178 1179 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1180 return; 1181 1182 switch (status) { 1183 case 0: /* success */ 1184 break; 1185 case -ECONNRESET: /* unlink */ 1186 case -ESHUTDOWN: 1187 netif_device_detach(tp->netdev); 1188 case -ENOENT: 1189 case -EPROTO: 1190 netif_info(tp, intr, tp->netdev, 1191 "Stop submitting intr, status %d\n", status); 1192 return; 1193 case -EOVERFLOW: 1194 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1195 goto resubmit; 1196 /* -EPIPE: should clear the halt */ 1197 default: 1198 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1199 goto resubmit; 1200 } 1201 1202 d = urb->transfer_buffer; 1203 if (INTR_LINK & __le16_to_cpu(d[0])) { 1204 if (!netif_carrier_ok(tp->netdev)) { 1205 set_bit(RTL8152_LINK_CHG, &tp->flags); 1206 schedule_delayed_work(&tp->schedule, 0); 1207 } 1208 } else { 1209 if (netif_carrier_ok(tp->netdev)) { 1210 set_bit(RTL8152_LINK_CHG, &tp->flags); 1211 schedule_delayed_work(&tp->schedule, 0); 1212 } 1213 } 1214 1215 resubmit: 1216 res = usb_submit_urb(urb, GFP_ATOMIC); 1217 if (res == -ENODEV) { 1218 set_bit(RTL8152_UNPLUG, &tp->flags); 1219 netif_device_detach(tp->netdev); 1220 } else if (res) { 1221 netif_err(tp, intr, tp->netdev, 1222 "can't resubmit intr, status %d\n", res); 1223 } 1224 } 1225 1226 static inline void *rx_agg_align(void *data) 1227 { 1228 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1229 } 1230 1231 static inline void *tx_agg_align(void *data) 1232 { 1233 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1234 } 1235 1236 static void free_all_mem(struct r8152 *tp) 1237 { 1238 int i; 1239 1240 for (i = 0; i < RTL8152_MAX_RX; i++) { 1241 usb_free_urb(tp->rx_info[i].urb); 1242 tp->rx_info[i].urb = NULL; 1243 1244 kfree(tp->rx_info[i].buffer); 1245 tp->rx_info[i].buffer = NULL; 1246 tp->rx_info[i].head = NULL; 1247 } 1248 1249 for (i = 0; i < RTL8152_MAX_TX; i++) { 1250 usb_free_urb(tp->tx_info[i].urb); 1251 tp->tx_info[i].urb = NULL; 1252 1253 kfree(tp->tx_info[i].buffer); 1254 tp->tx_info[i].buffer = NULL; 1255 tp->tx_info[i].head = NULL; 1256 } 1257 1258 usb_free_urb(tp->intr_urb); 1259 tp->intr_urb = NULL; 1260 1261 kfree(tp->intr_buff); 1262 tp->intr_buff = NULL; 1263 } 1264 1265 static int alloc_all_mem(struct r8152 *tp) 1266 { 1267 struct net_device *netdev = tp->netdev; 1268 struct usb_interface *intf = tp->intf; 1269 struct usb_host_interface *alt = intf->cur_altsetting; 1270 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1271 struct urb *urb; 1272 int node, i; 1273 u8 *buf; 1274 1275 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1276 1277 spin_lock_init(&tp->rx_lock); 1278 spin_lock_init(&tp->tx_lock); 1279 INIT_LIST_HEAD(&tp->tx_free); 1280 skb_queue_head_init(&tp->tx_queue); 1281 skb_queue_head_init(&tp->rx_queue); 1282 1283 for (i = 0; i < RTL8152_MAX_RX; i++) { 1284 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1285 if (!buf) 1286 goto err1; 1287 1288 if (buf != rx_agg_align(buf)) { 1289 kfree(buf); 1290 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, 1291 node); 1292 if (!buf) 1293 goto err1; 1294 } 1295 1296 urb = usb_alloc_urb(0, GFP_KERNEL); 1297 if (!urb) { 1298 kfree(buf); 1299 goto err1; 1300 } 1301 1302 INIT_LIST_HEAD(&tp->rx_info[i].list); 1303 tp->rx_info[i].context = tp; 1304 tp->rx_info[i].urb = urb; 1305 tp->rx_info[i].buffer = buf; 1306 tp->rx_info[i].head = rx_agg_align(buf); 1307 } 1308 1309 for (i = 0; i < RTL8152_MAX_TX; i++) { 1310 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1311 if (!buf) 1312 goto err1; 1313 1314 if (buf != tx_agg_align(buf)) { 1315 kfree(buf); 1316 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 1317 node); 1318 if (!buf) 1319 goto err1; 1320 } 1321 1322 urb = usb_alloc_urb(0, GFP_KERNEL); 1323 if (!urb) { 1324 kfree(buf); 1325 goto err1; 1326 } 1327 1328 INIT_LIST_HEAD(&tp->tx_info[i].list); 1329 tp->tx_info[i].context = tp; 1330 tp->tx_info[i].urb = urb; 1331 tp->tx_info[i].buffer = buf; 1332 tp->tx_info[i].head = tx_agg_align(buf); 1333 1334 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1335 } 1336 1337 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1338 if (!tp->intr_urb) 1339 goto err1; 1340 1341 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1342 if (!tp->intr_buff) 1343 goto err1; 1344 1345 tp->intr_interval = (int)ep_intr->desc.bInterval; 1346 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1347 tp->intr_buff, INTBUFSIZE, intr_callback, 1348 tp, tp->intr_interval); 1349 1350 return 0; 1351 1352 err1: 1353 free_all_mem(tp); 1354 return -ENOMEM; 1355 } 1356 1357 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1358 { 1359 struct tx_agg *agg = NULL; 1360 unsigned long flags; 1361 1362 if (list_empty(&tp->tx_free)) 1363 return NULL; 1364 1365 spin_lock_irqsave(&tp->tx_lock, flags); 1366 if (!list_empty(&tp->tx_free)) { 1367 struct list_head *cursor; 1368 1369 cursor = tp->tx_free.next; 1370 list_del_init(cursor); 1371 agg = list_entry(cursor, struct tx_agg, list); 1372 } 1373 spin_unlock_irqrestore(&tp->tx_lock, flags); 1374 1375 return agg; 1376 } 1377 1378 /* r8152_csum_workaround() 1379 * The hw limites the value the transport offset. When the offset is out of the 1380 * range, calculate the checksum by sw. 1381 */ 1382 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1383 struct sk_buff_head *list) 1384 { 1385 if (skb_shinfo(skb)->gso_size) { 1386 netdev_features_t features = tp->netdev->features; 1387 struct sk_buff_head seg_list; 1388 struct sk_buff *segs, *nskb; 1389 1390 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 1391 segs = skb_gso_segment(skb, features); 1392 if (IS_ERR(segs) || !segs) 1393 goto drop; 1394 1395 __skb_queue_head_init(&seg_list); 1396 1397 do { 1398 nskb = segs; 1399 segs = segs->next; 1400 nskb->next = NULL; 1401 __skb_queue_tail(&seg_list, nskb); 1402 } while (segs); 1403 1404 skb_queue_splice(&seg_list, list); 1405 dev_kfree_skb(skb); 1406 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1407 if (skb_checksum_help(skb) < 0) 1408 goto drop; 1409 1410 __skb_queue_head(list, skb); 1411 } else { 1412 struct net_device_stats *stats; 1413 1414 drop: 1415 stats = &tp->netdev->stats; 1416 stats->tx_dropped++; 1417 dev_kfree_skb(skb); 1418 } 1419 } 1420 1421 /* msdn_giant_send_check() 1422 * According to the document of microsoft, the TCP Pseudo Header excludes the 1423 * packet length for IPv6 TCP large packets. 1424 */ 1425 static int msdn_giant_send_check(struct sk_buff *skb) 1426 { 1427 const struct ipv6hdr *ipv6h; 1428 struct tcphdr *th; 1429 int ret; 1430 1431 ret = skb_cow_head(skb, 0); 1432 if (ret) 1433 return ret; 1434 1435 ipv6h = ipv6_hdr(skb); 1436 th = tcp_hdr(skb); 1437 1438 th->check = 0; 1439 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1440 1441 return ret; 1442 } 1443 1444 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 1445 { 1446 if (skb_vlan_tag_present(skb)) { 1447 u32 opts2; 1448 1449 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); 1450 desc->opts2 |= cpu_to_le32(opts2); 1451 } 1452 } 1453 1454 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 1455 { 1456 u32 opts2 = le32_to_cpu(desc->opts2); 1457 1458 if (opts2 & RX_VLAN_TAG) 1459 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1460 swab16(opts2 & 0xffff)); 1461 } 1462 1463 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1464 struct sk_buff *skb, u32 len, u32 transport_offset) 1465 { 1466 u32 mss = skb_shinfo(skb)->gso_size; 1467 u32 opts1, opts2 = 0; 1468 int ret = TX_CSUM_SUCCESS; 1469 1470 WARN_ON_ONCE(len > TX_LEN_MAX); 1471 1472 opts1 = len | TX_FS | TX_LS; 1473 1474 if (mss) { 1475 if (transport_offset > GTTCPHO_MAX) { 1476 netif_warn(tp, tx_err, tp->netdev, 1477 "Invalid transport offset 0x%x for TSO\n", 1478 transport_offset); 1479 ret = TX_CSUM_TSO; 1480 goto unavailable; 1481 } 1482 1483 switch (vlan_get_protocol(skb)) { 1484 case htons(ETH_P_IP): 1485 opts1 |= GTSENDV4; 1486 break; 1487 1488 case htons(ETH_P_IPV6): 1489 if (msdn_giant_send_check(skb)) { 1490 ret = TX_CSUM_TSO; 1491 goto unavailable; 1492 } 1493 opts1 |= GTSENDV6; 1494 break; 1495 1496 default: 1497 WARN_ON_ONCE(1); 1498 break; 1499 } 1500 1501 opts1 |= transport_offset << GTTCPHO_SHIFT; 1502 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1503 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1504 u8 ip_protocol; 1505 1506 if (transport_offset > TCPHO_MAX) { 1507 netif_warn(tp, tx_err, tp->netdev, 1508 "Invalid transport offset 0x%x\n", 1509 transport_offset); 1510 ret = TX_CSUM_NONE; 1511 goto unavailable; 1512 } 1513 1514 switch (vlan_get_protocol(skb)) { 1515 case htons(ETH_P_IP): 1516 opts2 |= IPV4_CS; 1517 ip_protocol = ip_hdr(skb)->protocol; 1518 break; 1519 1520 case htons(ETH_P_IPV6): 1521 opts2 |= IPV6_CS; 1522 ip_protocol = ipv6_hdr(skb)->nexthdr; 1523 break; 1524 1525 default: 1526 ip_protocol = IPPROTO_RAW; 1527 break; 1528 } 1529 1530 if (ip_protocol == IPPROTO_TCP) 1531 opts2 |= TCP_CS; 1532 else if (ip_protocol == IPPROTO_UDP) 1533 opts2 |= UDP_CS; 1534 else 1535 WARN_ON_ONCE(1); 1536 1537 opts2 |= transport_offset << TCPHO_SHIFT; 1538 } 1539 1540 desc->opts2 = cpu_to_le32(opts2); 1541 desc->opts1 = cpu_to_le32(opts1); 1542 1543 unavailable: 1544 return ret; 1545 } 1546 1547 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1548 { 1549 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1550 int remain, ret; 1551 u8 *tx_data; 1552 1553 __skb_queue_head_init(&skb_head); 1554 spin_lock(&tx_queue->lock); 1555 skb_queue_splice_init(tx_queue, &skb_head); 1556 spin_unlock(&tx_queue->lock); 1557 1558 tx_data = agg->head; 1559 agg->skb_num = 0; 1560 agg->skb_len = 0; 1561 remain = agg_buf_sz; 1562 1563 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1564 struct tx_desc *tx_desc; 1565 struct sk_buff *skb; 1566 unsigned int len; 1567 u32 offset; 1568 1569 skb = __skb_dequeue(&skb_head); 1570 if (!skb) 1571 break; 1572 1573 len = skb->len + sizeof(*tx_desc); 1574 1575 if (len > remain) { 1576 __skb_queue_head(&skb_head, skb); 1577 break; 1578 } 1579 1580 tx_data = tx_agg_align(tx_data); 1581 tx_desc = (struct tx_desc *)tx_data; 1582 1583 offset = (u32)skb_transport_offset(skb); 1584 1585 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1586 r8152_csum_workaround(tp, skb, &skb_head); 1587 continue; 1588 } 1589 1590 rtl_tx_vlan_tag(tx_desc, skb); 1591 1592 tx_data += sizeof(*tx_desc); 1593 1594 len = skb->len; 1595 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1596 struct net_device_stats *stats = &tp->netdev->stats; 1597 1598 stats->tx_dropped++; 1599 dev_kfree_skb_any(skb); 1600 tx_data -= sizeof(*tx_desc); 1601 continue; 1602 } 1603 1604 tx_data += len; 1605 agg->skb_len += len; 1606 agg->skb_num++; 1607 1608 dev_kfree_skb_any(skb); 1609 1610 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1611 } 1612 1613 if (!skb_queue_empty(&skb_head)) { 1614 spin_lock(&tx_queue->lock); 1615 skb_queue_splice(&skb_head, tx_queue); 1616 spin_unlock(&tx_queue->lock); 1617 } 1618 1619 netif_tx_lock(tp->netdev); 1620 1621 if (netif_queue_stopped(tp->netdev) && 1622 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1623 netif_wake_queue(tp->netdev); 1624 1625 netif_tx_unlock(tp->netdev); 1626 1627 ret = usb_autopm_get_interface_async(tp->intf); 1628 if (ret < 0) 1629 goto out_tx_fill; 1630 1631 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1632 agg->head, (int)(tx_data - (u8 *)agg->head), 1633 (usb_complete_t)write_bulk_callback, agg); 1634 1635 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1636 if (ret < 0) 1637 usb_autopm_put_interface_async(tp->intf); 1638 1639 out_tx_fill: 1640 return ret; 1641 } 1642 1643 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1644 { 1645 u8 checksum = CHECKSUM_NONE; 1646 u32 opts2, opts3; 1647 1648 if (tp->version == RTL_VER_01) 1649 goto return_result; 1650 1651 opts2 = le32_to_cpu(rx_desc->opts2); 1652 opts3 = le32_to_cpu(rx_desc->opts3); 1653 1654 if (opts2 & RD_IPV4_CS) { 1655 if (opts3 & IPF) 1656 checksum = CHECKSUM_NONE; 1657 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) 1658 checksum = CHECKSUM_NONE; 1659 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) 1660 checksum = CHECKSUM_NONE; 1661 else 1662 checksum = CHECKSUM_UNNECESSARY; 1663 } else if (RD_IPV6_CS) { 1664 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1665 checksum = CHECKSUM_UNNECESSARY; 1666 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1667 checksum = CHECKSUM_UNNECESSARY; 1668 } 1669 1670 return_result: 1671 return checksum; 1672 } 1673 1674 static int rx_bottom(struct r8152 *tp, int budget) 1675 { 1676 unsigned long flags; 1677 struct list_head *cursor, *next, rx_queue; 1678 int ret = 0, work_done = 0; 1679 1680 if (!skb_queue_empty(&tp->rx_queue)) { 1681 while (work_done < budget) { 1682 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); 1683 struct net_device *netdev = tp->netdev; 1684 struct net_device_stats *stats = &netdev->stats; 1685 unsigned int pkt_len; 1686 1687 if (!skb) 1688 break; 1689 1690 pkt_len = skb->len; 1691 napi_gro_receive(&tp->napi, skb); 1692 work_done++; 1693 stats->rx_packets++; 1694 stats->rx_bytes += pkt_len; 1695 } 1696 } 1697 1698 if (list_empty(&tp->rx_done)) 1699 goto out1; 1700 1701 INIT_LIST_HEAD(&rx_queue); 1702 spin_lock_irqsave(&tp->rx_lock, flags); 1703 list_splice_init(&tp->rx_done, &rx_queue); 1704 spin_unlock_irqrestore(&tp->rx_lock, flags); 1705 1706 list_for_each_safe(cursor, next, &rx_queue) { 1707 struct rx_desc *rx_desc; 1708 struct rx_agg *agg; 1709 int len_used = 0; 1710 struct urb *urb; 1711 u8 *rx_data; 1712 1713 list_del_init(cursor); 1714 1715 agg = list_entry(cursor, struct rx_agg, list); 1716 urb = agg->urb; 1717 if (urb->actual_length < ETH_ZLEN) 1718 goto submit; 1719 1720 rx_desc = agg->head; 1721 rx_data = agg->head; 1722 len_used += sizeof(struct rx_desc); 1723 1724 while (urb->actual_length > len_used) { 1725 struct net_device *netdev = tp->netdev; 1726 struct net_device_stats *stats = &netdev->stats; 1727 unsigned int pkt_len; 1728 struct sk_buff *skb; 1729 1730 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1731 if (pkt_len < ETH_ZLEN) 1732 break; 1733 1734 len_used += pkt_len; 1735 if (urb->actual_length < len_used) 1736 break; 1737 1738 pkt_len -= CRC_SIZE; 1739 rx_data += sizeof(struct rx_desc); 1740 1741 skb = netdev_alloc_skb_ip_align(netdev, pkt_len); 1742 if (!skb) { 1743 stats->rx_dropped++; 1744 goto find_next_rx; 1745 } 1746 1747 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 1748 memcpy(skb->data, rx_data, pkt_len); 1749 skb_put(skb, pkt_len); 1750 skb->protocol = eth_type_trans(skb, netdev); 1751 rtl_rx_vlan_tag(rx_desc, skb); 1752 if (work_done < budget) { 1753 napi_gro_receive(&tp->napi, skb); 1754 work_done++; 1755 stats->rx_packets++; 1756 stats->rx_bytes += pkt_len; 1757 } else { 1758 __skb_queue_tail(&tp->rx_queue, skb); 1759 } 1760 1761 find_next_rx: 1762 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); 1763 rx_desc = (struct rx_desc *)rx_data; 1764 len_used = (int)(rx_data - (u8 *)agg->head); 1765 len_used += sizeof(struct rx_desc); 1766 } 1767 1768 submit: 1769 if (!ret) { 1770 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1771 } else { 1772 urb->actual_length = 0; 1773 list_add_tail(&agg->list, next); 1774 } 1775 } 1776 1777 if (!list_empty(&rx_queue)) { 1778 spin_lock_irqsave(&tp->rx_lock, flags); 1779 list_splice_tail(&rx_queue, &tp->rx_done); 1780 spin_unlock_irqrestore(&tp->rx_lock, flags); 1781 } 1782 1783 out1: 1784 return work_done; 1785 } 1786 1787 static void tx_bottom(struct r8152 *tp) 1788 { 1789 int res; 1790 1791 do { 1792 struct tx_agg *agg; 1793 1794 if (skb_queue_empty(&tp->tx_queue)) 1795 break; 1796 1797 agg = r8152_get_tx_agg(tp); 1798 if (!agg) 1799 break; 1800 1801 res = r8152_tx_agg_fill(tp, agg); 1802 if (res) { 1803 struct net_device *netdev = tp->netdev; 1804 1805 if (res == -ENODEV) { 1806 set_bit(RTL8152_UNPLUG, &tp->flags); 1807 netif_device_detach(netdev); 1808 } else { 1809 struct net_device_stats *stats = &netdev->stats; 1810 unsigned long flags; 1811 1812 netif_warn(tp, tx_err, netdev, 1813 "failed tx_urb %d\n", res); 1814 stats->tx_dropped += agg->skb_num; 1815 1816 spin_lock_irqsave(&tp->tx_lock, flags); 1817 list_add_tail(&agg->list, &tp->tx_free); 1818 spin_unlock_irqrestore(&tp->tx_lock, flags); 1819 } 1820 } 1821 } while (res == 0); 1822 } 1823 1824 static void bottom_half(struct r8152 *tp) 1825 { 1826 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1827 return; 1828 1829 if (!test_bit(WORK_ENABLE, &tp->flags)) 1830 return; 1831 1832 /* When link down, the driver would cancel all bulks. */ 1833 /* This avoid the re-submitting bulk */ 1834 if (!netif_carrier_ok(tp->netdev)) 1835 return; 1836 1837 clear_bit(SCHEDULE_NAPI, &tp->flags); 1838 1839 tx_bottom(tp); 1840 } 1841 1842 static int r8152_poll(struct napi_struct *napi, int budget) 1843 { 1844 struct r8152 *tp = container_of(napi, struct r8152, napi); 1845 int work_done; 1846 1847 work_done = rx_bottom(tp, budget); 1848 bottom_half(tp); 1849 1850 if (work_done < budget) { 1851 napi_complete(napi); 1852 if (!list_empty(&tp->rx_done)) 1853 napi_schedule(napi); 1854 } 1855 1856 return work_done; 1857 } 1858 1859 static 1860 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 1861 { 1862 int ret; 1863 1864 /* The rx would be stopped, so skip submitting */ 1865 if (test_bit(RTL8152_UNPLUG, &tp->flags) || 1866 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) 1867 return 0; 1868 1869 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 1870 agg->head, agg_buf_sz, 1871 (usb_complete_t)read_bulk_callback, agg); 1872 1873 ret = usb_submit_urb(agg->urb, mem_flags); 1874 if (ret == -ENODEV) { 1875 set_bit(RTL8152_UNPLUG, &tp->flags); 1876 netif_device_detach(tp->netdev); 1877 } else if (ret) { 1878 struct urb *urb = agg->urb; 1879 unsigned long flags; 1880 1881 urb->actual_length = 0; 1882 spin_lock_irqsave(&tp->rx_lock, flags); 1883 list_add_tail(&agg->list, &tp->rx_done); 1884 spin_unlock_irqrestore(&tp->rx_lock, flags); 1885 1886 netif_err(tp, rx_err, tp->netdev, 1887 "Couldn't submit rx[%p], ret = %d\n", agg, ret); 1888 1889 napi_schedule(&tp->napi); 1890 } 1891 1892 return ret; 1893 } 1894 1895 static void rtl_drop_queued_tx(struct r8152 *tp) 1896 { 1897 struct net_device_stats *stats = &tp->netdev->stats; 1898 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1899 struct sk_buff *skb; 1900 1901 if (skb_queue_empty(tx_queue)) 1902 return; 1903 1904 __skb_queue_head_init(&skb_head); 1905 spin_lock_bh(&tx_queue->lock); 1906 skb_queue_splice_init(tx_queue, &skb_head); 1907 spin_unlock_bh(&tx_queue->lock); 1908 1909 while ((skb = __skb_dequeue(&skb_head))) { 1910 dev_kfree_skb(skb); 1911 stats->tx_dropped++; 1912 } 1913 } 1914 1915 static void rtl8152_tx_timeout(struct net_device *netdev) 1916 { 1917 struct r8152 *tp = netdev_priv(netdev); 1918 1919 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 1920 1921 usb_queue_reset_device(tp->intf); 1922 } 1923 1924 static void rtl8152_set_rx_mode(struct net_device *netdev) 1925 { 1926 struct r8152 *tp = netdev_priv(netdev); 1927 1928 if (netif_carrier_ok(netdev)) { 1929 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 1930 schedule_delayed_work(&tp->schedule, 0); 1931 } 1932 } 1933 1934 static void _rtl8152_set_rx_mode(struct net_device *netdev) 1935 { 1936 struct r8152 *tp = netdev_priv(netdev); 1937 u32 mc_filter[2]; /* Multicast hash filter */ 1938 __le32 tmp[2]; 1939 u32 ocp_data; 1940 1941 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 1942 netif_stop_queue(netdev); 1943 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 1944 ocp_data &= ~RCR_ACPT_ALL; 1945 ocp_data |= RCR_AB | RCR_APM; 1946 1947 if (netdev->flags & IFF_PROMISC) { 1948 /* Unconditionally log net taps. */ 1949 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 1950 ocp_data |= RCR_AM | RCR_AAP; 1951 mc_filter[1] = 0xffffffff; 1952 mc_filter[0] = 0xffffffff; 1953 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 1954 (netdev->flags & IFF_ALLMULTI)) { 1955 /* Too many to filter perfectly -- accept all multicasts. */ 1956 ocp_data |= RCR_AM; 1957 mc_filter[1] = 0xffffffff; 1958 mc_filter[0] = 0xffffffff; 1959 } else { 1960 struct netdev_hw_addr *ha; 1961 1962 mc_filter[1] = 0; 1963 mc_filter[0] = 0; 1964 netdev_for_each_mc_addr(ha, netdev) { 1965 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 1966 1967 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 1968 ocp_data |= RCR_AM; 1969 } 1970 } 1971 1972 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 1973 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 1974 1975 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 1976 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 1977 netif_wake_queue(netdev); 1978 } 1979 1980 static netdev_features_t 1981 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 1982 netdev_features_t features) 1983 { 1984 u32 mss = skb_shinfo(skb)->gso_size; 1985 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 1986 int offset = skb_transport_offset(skb); 1987 1988 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) 1989 features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK); 1990 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 1991 features &= ~NETIF_F_GSO_MASK; 1992 1993 return features; 1994 } 1995 1996 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 1997 struct net_device *netdev) 1998 { 1999 struct r8152 *tp = netdev_priv(netdev); 2000 2001 skb_tx_timestamp(skb); 2002 2003 skb_queue_tail(&tp->tx_queue, skb); 2004 2005 if (!list_empty(&tp->tx_free)) { 2006 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2007 set_bit(SCHEDULE_NAPI, &tp->flags); 2008 schedule_delayed_work(&tp->schedule, 0); 2009 } else { 2010 usb_mark_last_busy(tp->udev); 2011 napi_schedule(&tp->napi); 2012 } 2013 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 2014 netif_stop_queue(netdev); 2015 } 2016 2017 return NETDEV_TX_OK; 2018 } 2019 2020 static void r8152b_reset_packet_filter(struct r8152 *tp) 2021 { 2022 u32 ocp_data; 2023 2024 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 2025 ocp_data &= ~FMC_FCR_MCU_EN; 2026 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2027 ocp_data |= FMC_FCR_MCU_EN; 2028 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2029 } 2030 2031 static void rtl8152_nic_reset(struct r8152 *tp) 2032 { 2033 int i; 2034 2035 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 2036 2037 for (i = 0; i < 1000; i++) { 2038 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 2039 break; 2040 usleep_range(100, 400); 2041 } 2042 } 2043 2044 static void set_tx_qlen(struct r8152 *tp) 2045 { 2046 struct net_device *netdev = tp->netdev; 2047 2048 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + 2049 sizeof(struct tx_desc)); 2050 } 2051 2052 static inline u8 rtl8152_get_speed(struct r8152 *tp) 2053 { 2054 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 2055 } 2056 2057 static void rtl_set_eee_plus(struct r8152 *tp) 2058 { 2059 u32 ocp_data; 2060 u8 speed; 2061 2062 speed = rtl8152_get_speed(tp); 2063 if (speed & _10bps) { 2064 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2065 ocp_data |= EEEP_CR_EEEP_TX; 2066 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2067 } else { 2068 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2069 ocp_data &= ~EEEP_CR_EEEP_TX; 2070 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2071 } 2072 } 2073 2074 static void rxdy_gated_en(struct r8152 *tp, bool enable) 2075 { 2076 u32 ocp_data; 2077 2078 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 2079 if (enable) 2080 ocp_data |= RXDY_GATED_EN; 2081 else 2082 ocp_data &= ~RXDY_GATED_EN; 2083 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 2084 } 2085 2086 static int rtl_start_rx(struct r8152 *tp) 2087 { 2088 int i, ret = 0; 2089 2090 INIT_LIST_HEAD(&tp->rx_done); 2091 for (i = 0; i < RTL8152_MAX_RX; i++) { 2092 INIT_LIST_HEAD(&tp->rx_info[i].list); 2093 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 2094 if (ret) 2095 break; 2096 } 2097 2098 if (ret && ++i < RTL8152_MAX_RX) { 2099 struct list_head rx_queue; 2100 unsigned long flags; 2101 2102 INIT_LIST_HEAD(&rx_queue); 2103 2104 do { 2105 struct rx_agg *agg = &tp->rx_info[i++]; 2106 struct urb *urb = agg->urb; 2107 2108 urb->actual_length = 0; 2109 list_add_tail(&agg->list, &rx_queue); 2110 } while (i < RTL8152_MAX_RX); 2111 2112 spin_lock_irqsave(&tp->rx_lock, flags); 2113 list_splice_tail(&rx_queue, &tp->rx_done); 2114 spin_unlock_irqrestore(&tp->rx_lock, flags); 2115 } 2116 2117 return ret; 2118 } 2119 2120 static int rtl_stop_rx(struct r8152 *tp) 2121 { 2122 int i; 2123 2124 for (i = 0; i < RTL8152_MAX_RX; i++) 2125 usb_kill_urb(tp->rx_info[i].urb); 2126 2127 while (!skb_queue_empty(&tp->rx_queue)) 2128 dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); 2129 2130 return 0; 2131 } 2132 2133 static int rtl_enable(struct r8152 *tp) 2134 { 2135 u32 ocp_data; 2136 2137 r8152b_reset_packet_filter(tp); 2138 2139 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2140 ocp_data |= CR_RE | CR_TE; 2141 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2142 2143 rxdy_gated_en(tp, false); 2144 2145 return 0; 2146 } 2147 2148 static int rtl8152_enable(struct r8152 *tp) 2149 { 2150 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2151 return -ENODEV; 2152 2153 set_tx_qlen(tp); 2154 rtl_set_eee_plus(tp); 2155 2156 return rtl_enable(tp); 2157 } 2158 2159 static void r8153_set_rx_early_timeout(struct r8152 *tp) 2160 { 2161 u32 ocp_data = tp->coalesce / 8; 2162 2163 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data); 2164 } 2165 2166 static void r8153_set_rx_early_size(struct r8152 *tp) 2167 { 2168 u32 mtu = tp->netdev->mtu; 2169 u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 4; 2170 2171 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data); 2172 } 2173 2174 static int rtl8153_enable(struct r8152 *tp) 2175 { 2176 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2177 return -ENODEV; 2178 2179 usb_disable_lpm(tp->udev); 2180 set_tx_qlen(tp); 2181 rtl_set_eee_plus(tp); 2182 r8153_set_rx_early_timeout(tp); 2183 r8153_set_rx_early_size(tp); 2184 2185 return rtl_enable(tp); 2186 } 2187 2188 static void rtl_disable(struct r8152 *tp) 2189 { 2190 u32 ocp_data; 2191 int i; 2192 2193 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2194 rtl_drop_queued_tx(tp); 2195 return; 2196 } 2197 2198 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2199 ocp_data &= ~RCR_ACPT_ALL; 2200 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2201 2202 rtl_drop_queued_tx(tp); 2203 2204 for (i = 0; i < RTL8152_MAX_TX; i++) 2205 usb_kill_urb(tp->tx_info[i].urb); 2206 2207 rxdy_gated_en(tp, true); 2208 2209 for (i = 0; i < 1000; i++) { 2210 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2211 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2212 break; 2213 usleep_range(1000, 2000); 2214 } 2215 2216 for (i = 0; i < 1000; i++) { 2217 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2218 break; 2219 usleep_range(1000, 2000); 2220 } 2221 2222 rtl_stop_rx(tp); 2223 2224 rtl8152_nic_reset(tp); 2225 } 2226 2227 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2228 { 2229 u32 ocp_data; 2230 2231 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2232 if (enable) 2233 ocp_data |= POWER_CUT; 2234 else 2235 ocp_data &= ~POWER_CUT; 2236 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2237 2238 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2239 ocp_data &= ~RESUME_INDICATE; 2240 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2241 } 2242 2243 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 2244 { 2245 u32 ocp_data; 2246 2247 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2248 if (enable) 2249 ocp_data |= CPCR_RX_VLAN; 2250 else 2251 ocp_data &= ~CPCR_RX_VLAN; 2252 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2253 } 2254 2255 static int rtl8152_set_features(struct net_device *dev, 2256 netdev_features_t features) 2257 { 2258 netdev_features_t changed = features ^ dev->features; 2259 struct r8152 *tp = netdev_priv(dev); 2260 int ret; 2261 2262 ret = usb_autopm_get_interface(tp->intf); 2263 if (ret < 0) 2264 goto out; 2265 2266 mutex_lock(&tp->control); 2267 2268 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 2269 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2270 rtl_rx_vlan_en(tp, true); 2271 else 2272 rtl_rx_vlan_en(tp, false); 2273 } 2274 2275 mutex_unlock(&tp->control); 2276 2277 usb_autopm_put_interface(tp->intf); 2278 2279 out: 2280 return ret; 2281 } 2282 2283 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2284 2285 static u32 __rtl_get_wol(struct r8152 *tp) 2286 { 2287 u32 ocp_data; 2288 u32 wolopts = 0; 2289 2290 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2291 if (!(ocp_data & LAN_WAKE_EN)) 2292 return 0; 2293 2294 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2295 if (ocp_data & LINK_ON_WAKE_EN) 2296 wolopts |= WAKE_PHY; 2297 2298 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2299 if (ocp_data & UWF_EN) 2300 wolopts |= WAKE_UCAST; 2301 if (ocp_data & BWF_EN) 2302 wolopts |= WAKE_BCAST; 2303 if (ocp_data & MWF_EN) 2304 wolopts |= WAKE_MCAST; 2305 2306 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2307 if (ocp_data & MAGIC_EN) 2308 wolopts |= WAKE_MAGIC; 2309 2310 return wolopts; 2311 } 2312 2313 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2314 { 2315 u32 ocp_data; 2316 2317 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2318 2319 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2320 ocp_data &= ~LINK_ON_WAKE_EN; 2321 if (wolopts & WAKE_PHY) 2322 ocp_data |= LINK_ON_WAKE_EN; 2323 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2324 2325 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2326 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN); 2327 if (wolopts & WAKE_UCAST) 2328 ocp_data |= UWF_EN; 2329 if (wolopts & WAKE_BCAST) 2330 ocp_data |= BWF_EN; 2331 if (wolopts & WAKE_MCAST) 2332 ocp_data |= MWF_EN; 2333 if (wolopts & WAKE_ANY) 2334 ocp_data |= LAN_WAKE_EN; 2335 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2336 2337 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2338 2339 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2340 ocp_data &= ~MAGIC_EN; 2341 if (wolopts & WAKE_MAGIC) 2342 ocp_data |= MAGIC_EN; 2343 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2344 2345 if (wolopts & WAKE_ANY) 2346 device_set_wakeup_enable(&tp->udev->dev, true); 2347 else 2348 device_set_wakeup_enable(&tp->udev->dev, false); 2349 } 2350 2351 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2352 { 2353 u8 u1u2[8]; 2354 2355 if (enable) 2356 memset(u1u2, 0xff, sizeof(u1u2)); 2357 else 2358 memset(u1u2, 0x00, sizeof(u1u2)); 2359 2360 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2361 } 2362 2363 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2364 { 2365 u32 ocp_data; 2366 2367 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2368 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04) 2369 ocp_data |= U2P3_ENABLE; 2370 else 2371 ocp_data &= ~U2P3_ENABLE; 2372 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2373 } 2374 2375 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2376 { 2377 u32 ocp_data; 2378 2379 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2380 if (enable) 2381 ocp_data |= PWR_EN | PHASE2_EN; 2382 else 2383 ocp_data &= ~(PWR_EN | PHASE2_EN); 2384 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2385 2386 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2387 ocp_data &= ~PCUT_STATUS; 2388 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2389 } 2390 2391 static bool rtl_can_wakeup(struct r8152 *tp) 2392 { 2393 struct usb_device *udev = tp->udev; 2394 2395 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); 2396 } 2397 2398 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 2399 { 2400 if (enable) { 2401 u32 ocp_data; 2402 2403 r8153_u1u2en(tp, false); 2404 r8153_u2p3en(tp, false); 2405 2406 __rtl_set_wol(tp, WAKE_ANY); 2407 2408 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2409 2410 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2411 ocp_data |= LINK_OFF_WAKE_EN; 2412 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2413 2414 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2415 } else { 2416 __rtl_set_wol(tp, tp->saved_wolopts); 2417 r8153_u2p3en(tp, true); 2418 r8153_u1u2en(tp, true); 2419 } 2420 } 2421 2422 static void rtl_phy_reset(struct r8152 *tp) 2423 { 2424 u16 data; 2425 int i; 2426 2427 clear_bit(PHY_RESET, &tp->flags); 2428 2429 data = r8152_mdio_read(tp, MII_BMCR); 2430 2431 /* don't reset again before the previous one complete */ 2432 if (data & BMCR_RESET) 2433 return; 2434 2435 data |= BMCR_RESET; 2436 r8152_mdio_write(tp, MII_BMCR, data); 2437 2438 for (i = 0; i < 50; i++) { 2439 msleep(20); 2440 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 2441 break; 2442 } 2443 } 2444 2445 static void r8153_teredo_off(struct r8152 *tp) 2446 { 2447 u32 ocp_data; 2448 2449 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2450 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); 2451 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2452 2453 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 2454 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 2455 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 2456 } 2457 2458 static void r8152b_disable_aldps(struct r8152 *tp) 2459 { 2460 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); 2461 msleep(20); 2462 } 2463 2464 static inline void r8152b_enable_aldps(struct r8152 *tp) 2465 { 2466 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 2467 LINKENA | DIS_SDSAVE); 2468 } 2469 2470 static void rtl8152_disable(struct r8152 *tp) 2471 { 2472 r8152b_disable_aldps(tp); 2473 rtl_disable(tp); 2474 r8152b_enable_aldps(tp); 2475 } 2476 2477 static void r8152b_hw_phy_cfg(struct r8152 *tp) 2478 { 2479 u16 data; 2480 2481 data = r8152_mdio_read(tp, MII_BMCR); 2482 if (data & BMCR_PDOWN) { 2483 data &= ~BMCR_PDOWN; 2484 r8152_mdio_write(tp, MII_BMCR, data); 2485 } 2486 2487 set_bit(PHY_RESET, &tp->flags); 2488 } 2489 2490 static void r8152b_exit_oob(struct r8152 *tp) 2491 { 2492 u32 ocp_data; 2493 int i; 2494 2495 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2496 ocp_data &= ~RCR_ACPT_ALL; 2497 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2498 2499 rxdy_gated_en(tp, true); 2500 r8153_teredo_off(tp); 2501 r8152b_hw_phy_cfg(tp); 2502 2503 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2504 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 2505 2506 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2507 ocp_data &= ~NOW_IS_OOB; 2508 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2509 2510 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2511 ocp_data &= ~MCU_BORW_EN; 2512 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2513 2514 for (i = 0; i < 1000; i++) { 2515 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2516 if (ocp_data & LINK_LIST_READY) 2517 break; 2518 usleep_range(1000, 2000); 2519 } 2520 2521 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2522 ocp_data |= RE_INIT_LL; 2523 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2524 2525 for (i = 0; i < 1000; i++) { 2526 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2527 if (ocp_data & LINK_LIST_READY) 2528 break; 2529 usleep_range(1000, 2000); 2530 } 2531 2532 rtl8152_nic_reset(tp); 2533 2534 /* rx share fifo credit full threshold */ 2535 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2536 2537 if (tp->udev->speed == USB_SPEED_FULL || 2538 tp->udev->speed == USB_SPEED_LOW) { 2539 /* rx share fifo credit near full threshold */ 2540 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2541 RXFIFO_THR2_FULL); 2542 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2543 RXFIFO_THR3_FULL); 2544 } else { 2545 /* rx share fifo credit near full threshold */ 2546 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2547 RXFIFO_THR2_HIGH); 2548 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2549 RXFIFO_THR3_HIGH); 2550 } 2551 2552 /* TX share fifo free credit full threshold */ 2553 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 2554 2555 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 2556 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 2557 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 2558 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 2559 2560 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 2561 2562 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2563 2564 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2565 ocp_data |= TCR0_AUTO_FIFO; 2566 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2567 } 2568 2569 static void r8152b_enter_oob(struct r8152 *tp) 2570 { 2571 u32 ocp_data; 2572 int i; 2573 2574 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2575 ocp_data &= ~NOW_IS_OOB; 2576 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2577 2578 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 2579 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 2580 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 2581 2582 rtl_disable(tp); 2583 2584 for (i = 0; i < 1000; i++) { 2585 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2586 if (ocp_data & LINK_LIST_READY) 2587 break; 2588 usleep_range(1000, 2000); 2589 } 2590 2591 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2592 ocp_data |= RE_INIT_LL; 2593 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2594 2595 for (i = 0; i < 1000; i++) { 2596 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2597 if (ocp_data & LINK_LIST_READY) 2598 break; 2599 usleep_range(1000, 2000); 2600 } 2601 2602 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2603 2604 rtl_rx_vlan_en(tp, true); 2605 2606 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2607 ocp_data |= ALDPS_PROXY_MODE; 2608 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2609 2610 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2611 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2612 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2613 2614 rxdy_gated_en(tp, false); 2615 2616 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2617 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2618 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2619 } 2620 2621 static void r8153_hw_phy_cfg(struct r8152 *tp) 2622 { 2623 u32 ocp_data; 2624 u16 data; 2625 2626 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 2627 tp->version == RTL_VER_05) 2628 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 2629 2630 data = r8152_mdio_read(tp, MII_BMCR); 2631 if (data & BMCR_PDOWN) { 2632 data &= ~BMCR_PDOWN; 2633 r8152_mdio_write(tp, MII_BMCR, data); 2634 } 2635 2636 if (tp->version == RTL_VER_03) { 2637 data = ocp_reg_read(tp, OCP_EEE_CFG); 2638 data &= ~CTAP_SHORT_EN; 2639 ocp_reg_write(tp, OCP_EEE_CFG, data); 2640 } 2641 2642 data = ocp_reg_read(tp, OCP_POWER_CFG); 2643 data |= EEE_CLKDIV_EN; 2644 ocp_reg_write(tp, OCP_POWER_CFG, data); 2645 2646 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 2647 data |= EN_10M_BGOFF; 2648 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 2649 data = ocp_reg_read(tp, OCP_POWER_CFG); 2650 data |= EN_10M_PLLOFF; 2651 ocp_reg_write(tp, OCP_POWER_CFG, data); 2652 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 2653 2654 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 2655 ocp_data |= PFM_PWM_SWITCH; 2656 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 2657 2658 /* Enable LPF corner auto tune */ 2659 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 2660 2661 /* Adjust 10M Amplitude */ 2662 sram_write(tp, SRAM_10M_AMP1, 0x00af); 2663 sram_write(tp, SRAM_10M_AMP2, 0x0208); 2664 2665 set_bit(PHY_RESET, &tp->flags); 2666 } 2667 2668 static void r8153_first_init(struct r8152 *tp) 2669 { 2670 u32 ocp_data; 2671 int i; 2672 2673 rxdy_gated_en(tp, true); 2674 r8153_teredo_off(tp); 2675 2676 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2677 ocp_data &= ~RCR_ACPT_ALL; 2678 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2679 2680 r8153_hw_phy_cfg(tp); 2681 2682 rtl8152_nic_reset(tp); 2683 2684 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2685 ocp_data &= ~NOW_IS_OOB; 2686 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2687 2688 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2689 ocp_data &= ~MCU_BORW_EN; 2690 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2691 2692 for (i = 0; i < 1000; i++) { 2693 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2694 if (ocp_data & LINK_LIST_READY) 2695 break; 2696 usleep_range(1000, 2000); 2697 } 2698 2699 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2700 ocp_data |= RE_INIT_LL; 2701 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2702 2703 for (i = 0; i < 1000; i++) { 2704 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2705 if (ocp_data & LINK_LIST_READY) 2706 break; 2707 usleep_range(1000, 2000); 2708 } 2709 2710 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 2711 2712 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); 2713 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 2714 2715 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2716 ocp_data |= TCR0_AUTO_FIFO; 2717 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2718 2719 rtl8152_nic_reset(tp); 2720 2721 /* rx share fifo credit full threshold */ 2722 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2723 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 2724 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 2725 /* TX share fifo free credit full threshold */ 2726 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 2727 2728 /* rx aggregation */ 2729 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 2730 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 2731 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 2732 } 2733 2734 static void r8153_enter_oob(struct r8152 *tp) 2735 { 2736 u32 ocp_data; 2737 int i; 2738 2739 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2740 ocp_data &= ~NOW_IS_OOB; 2741 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2742 2743 rtl_disable(tp); 2744 2745 for (i = 0; i < 1000; i++) { 2746 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2747 if (ocp_data & LINK_LIST_READY) 2748 break; 2749 usleep_range(1000, 2000); 2750 } 2751 2752 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2753 ocp_data |= RE_INIT_LL; 2754 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2755 2756 for (i = 0; i < 1000; i++) { 2757 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2758 if (ocp_data & LINK_LIST_READY) 2759 break; 2760 usleep_range(1000, 2000); 2761 } 2762 2763 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); 2764 2765 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2766 ocp_data &= ~TEREDO_WAKE_MASK; 2767 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2768 2769 rtl_rx_vlan_en(tp, true); 2770 2771 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2772 ocp_data |= ALDPS_PROXY_MODE; 2773 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2774 2775 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2776 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2777 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2778 2779 rxdy_gated_en(tp, false); 2780 2781 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2782 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2783 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2784 } 2785 2786 static void r8153_disable_aldps(struct r8152 *tp) 2787 { 2788 u16 data; 2789 2790 data = ocp_reg_read(tp, OCP_POWER_CFG); 2791 data &= ~EN_ALDPS; 2792 ocp_reg_write(tp, OCP_POWER_CFG, data); 2793 msleep(20); 2794 } 2795 2796 static void r8153_enable_aldps(struct r8152 *tp) 2797 { 2798 u16 data; 2799 2800 data = ocp_reg_read(tp, OCP_POWER_CFG); 2801 data |= EN_ALDPS; 2802 ocp_reg_write(tp, OCP_POWER_CFG, data); 2803 } 2804 2805 static void rtl8153_disable(struct r8152 *tp) 2806 { 2807 r8153_disable_aldps(tp); 2808 rtl_disable(tp); 2809 r8153_enable_aldps(tp); 2810 usb_enable_lpm(tp->udev); 2811 } 2812 2813 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 2814 { 2815 u16 bmcr, anar, gbcr; 2816 int ret = 0; 2817 2818 cancel_delayed_work_sync(&tp->schedule); 2819 anar = r8152_mdio_read(tp, MII_ADVERTISE); 2820 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 2821 ADVERTISE_100HALF | ADVERTISE_100FULL); 2822 if (tp->mii.supports_gmii) { 2823 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 2824 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 2825 } else { 2826 gbcr = 0; 2827 } 2828 2829 if (autoneg == AUTONEG_DISABLE) { 2830 if (speed == SPEED_10) { 2831 bmcr = 0; 2832 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2833 } else if (speed == SPEED_100) { 2834 bmcr = BMCR_SPEED100; 2835 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2836 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 2837 bmcr = BMCR_SPEED1000; 2838 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 2839 } else { 2840 ret = -EINVAL; 2841 goto out; 2842 } 2843 2844 if (duplex == DUPLEX_FULL) 2845 bmcr |= BMCR_FULLDPLX; 2846 } else { 2847 if (speed == SPEED_10) { 2848 if (duplex == DUPLEX_FULL) 2849 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2850 else 2851 anar |= ADVERTISE_10HALF; 2852 } else if (speed == SPEED_100) { 2853 if (duplex == DUPLEX_FULL) { 2854 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2855 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2856 } else { 2857 anar |= ADVERTISE_10HALF; 2858 anar |= ADVERTISE_100HALF; 2859 } 2860 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 2861 if (duplex == DUPLEX_FULL) { 2862 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2863 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2864 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 2865 } else { 2866 anar |= ADVERTISE_10HALF; 2867 anar |= ADVERTISE_100HALF; 2868 gbcr |= ADVERTISE_1000HALF; 2869 } 2870 } else { 2871 ret = -EINVAL; 2872 goto out; 2873 } 2874 2875 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 2876 } 2877 2878 if (test_bit(PHY_RESET, &tp->flags)) 2879 bmcr |= BMCR_RESET; 2880 2881 if (tp->mii.supports_gmii) 2882 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 2883 2884 r8152_mdio_write(tp, MII_ADVERTISE, anar); 2885 r8152_mdio_write(tp, MII_BMCR, bmcr); 2886 2887 if (test_bit(PHY_RESET, &tp->flags)) { 2888 int i; 2889 2890 clear_bit(PHY_RESET, &tp->flags); 2891 for (i = 0; i < 50; i++) { 2892 msleep(20); 2893 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 2894 break; 2895 } 2896 } 2897 2898 out: 2899 2900 return ret; 2901 } 2902 2903 static void rtl8152_up(struct r8152 *tp) 2904 { 2905 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2906 return; 2907 2908 r8152b_disable_aldps(tp); 2909 r8152b_exit_oob(tp); 2910 r8152b_enable_aldps(tp); 2911 } 2912 2913 static void rtl8152_down(struct r8152 *tp) 2914 { 2915 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2916 rtl_drop_queued_tx(tp); 2917 return; 2918 } 2919 2920 r8152_power_cut_en(tp, false); 2921 r8152b_disable_aldps(tp); 2922 r8152b_enter_oob(tp); 2923 r8152b_enable_aldps(tp); 2924 } 2925 2926 static void rtl8153_up(struct r8152 *tp) 2927 { 2928 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2929 return; 2930 2931 r8153_u1u2en(tp, false); 2932 r8153_disable_aldps(tp); 2933 r8153_first_init(tp); 2934 r8153_enable_aldps(tp); 2935 r8153_u2p3en(tp, true); 2936 r8153_u1u2en(tp, true); 2937 usb_enable_lpm(tp->udev); 2938 } 2939 2940 static void rtl8153_down(struct r8152 *tp) 2941 { 2942 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2943 rtl_drop_queued_tx(tp); 2944 return; 2945 } 2946 2947 r8153_u1u2en(tp, false); 2948 r8153_u2p3en(tp, false); 2949 r8153_power_cut_en(tp, false); 2950 r8153_disable_aldps(tp); 2951 r8153_enter_oob(tp); 2952 r8153_enable_aldps(tp); 2953 } 2954 2955 static bool rtl8152_in_nway(struct r8152 *tp) 2956 { 2957 u16 nway_state; 2958 2959 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); 2960 tp->ocp_base = 0x2000; 2961 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ 2962 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); 2963 2964 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ 2965 if (nway_state & 0xc000) 2966 return false; 2967 else 2968 return true; 2969 } 2970 2971 static bool rtl8153_in_nway(struct r8152 *tp) 2972 { 2973 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; 2974 2975 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) 2976 return false; 2977 else 2978 return true; 2979 } 2980 2981 static void set_carrier(struct r8152 *tp) 2982 { 2983 struct net_device *netdev = tp->netdev; 2984 u8 speed; 2985 2986 clear_bit(RTL8152_LINK_CHG, &tp->flags); 2987 speed = rtl8152_get_speed(tp); 2988 2989 if (speed & LINK_STATUS) { 2990 if (!netif_carrier_ok(netdev)) { 2991 tp->rtl_ops.enable(tp); 2992 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2993 napi_disable(&tp->napi); 2994 netif_carrier_on(netdev); 2995 rtl_start_rx(tp); 2996 napi_enable(&tp->napi); 2997 } 2998 } else { 2999 if (netif_carrier_ok(netdev)) { 3000 netif_carrier_off(netdev); 3001 napi_disable(&tp->napi); 3002 tp->rtl_ops.disable(tp); 3003 napi_enable(&tp->napi); 3004 } 3005 } 3006 } 3007 3008 static void rtl_work_func_t(struct work_struct *work) 3009 { 3010 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 3011 3012 /* If the device is unplugged or !netif_running(), the workqueue 3013 * doesn't need to wake the device, and could return directly. 3014 */ 3015 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) 3016 return; 3017 3018 if (usb_autopm_get_interface(tp->intf) < 0) 3019 return; 3020 3021 if (!test_bit(WORK_ENABLE, &tp->flags)) 3022 goto out1; 3023 3024 if (!mutex_trylock(&tp->control)) { 3025 schedule_delayed_work(&tp->schedule, 0); 3026 goto out1; 3027 } 3028 3029 if (test_bit(RTL8152_LINK_CHG, &tp->flags)) 3030 set_carrier(tp); 3031 3032 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) 3033 _rtl8152_set_rx_mode(tp->netdev); 3034 3035 /* don't schedule napi before linking */ 3036 if (test_bit(SCHEDULE_NAPI, &tp->flags) && 3037 netif_carrier_ok(tp->netdev)) { 3038 clear_bit(SCHEDULE_NAPI, &tp->flags); 3039 napi_schedule(&tp->napi); 3040 } 3041 3042 if (test_bit(PHY_RESET, &tp->flags)) 3043 rtl_phy_reset(tp); 3044 3045 mutex_unlock(&tp->control); 3046 3047 out1: 3048 usb_autopm_put_interface(tp->intf); 3049 } 3050 3051 static int rtl8152_open(struct net_device *netdev) 3052 { 3053 struct r8152 *tp = netdev_priv(netdev); 3054 int res = 0; 3055 3056 res = alloc_all_mem(tp); 3057 if (res) 3058 goto out; 3059 3060 netif_carrier_off(netdev); 3061 3062 res = usb_autopm_get_interface(tp->intf); 3063 if (res < 0) { 3064 free_all_mem(tp); 3065 goto out; 3066 } 3067 3068 mutex_lock(&tp->control); 3069 3070 tp->rtl_ops.up(tp); 3071 3072 rtl8152_set_speed(tp, AUTONEG_ENABLE, 3073 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, 3074 DUPLEX_FULL); 3075 netif_carrier_off(netdev); 3076 netif_start_queue(netdev); 3077 set_bit(WORK_ENABLE, &tp->flags); 3078 3079 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3080 if (res) { 3081 if (res == -ENODEV) 3082 netif_device_detach(tp->netdev); 3083 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 3084 res); 3085 free_all_mem(tp); 3086 } else { 3087 napi_enable(&tp->napi); 3088 } 3089 3090 mutex_unlock(&tp->control); 3091 3092 usb_autopm_put_interface(tp->intf); 3093 3094 out: 3095 return res; 3096 } 3097 3098 static int rtl8152_close(struct net_device *netdev) 3099 { 3100 struct r8152 *tp = netdev_priv(netdev); 3101 int res = 0; 3102 3103 napi_disable(&tp->napi); 3104 clear_bit(WORK_ENABLE, &tp->flags); 3105 usb_kill_urb(tp->intr_urb); 3106 cancel_delayed_work_sync(&tp->schedule); 3107 netif_stop_queue(netdev); 3108 3109 res = usb_autopm_get_interface(tp->intf); 3110 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { 3111 rtl_drop_queued_tx(tp); 3112 rtl_stop_rx(tp); 3113 } else { 3114 mutex_lock(&tp->control); 3115 3116 tp->rtl_ops.down(tp); 3117 3118 mutex_unlock(&tp->control); 3119 3120 usb_autopm_put_interface(tp->intf); 3121 } 3122 3123 free_all_mem(tp); 3124 3125 return res; 3126 } 3127 3128 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 3129 { 3130 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 3131 ocp_reg_write(tp, OCP_EEE_DATA, reg); 3132 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 3133 } 3134 3135 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 3136 { 3137 u16 data; 3138 3139 r8152_mmd_indirect(tp, dev, reg); 3140 data = ocp_reg_read(tp, OCP_EEE_DATA); 3141 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3142 3143 return data; 3144 } 3145 3146 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 3147 { 3148 r8152_mmd_indirect(tp, dev, reg); 3149 ocp_reg_write(tp, OCP_EEE_DATA, data); 3150 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3151 } 3152 3153 static void r8152_eee_en(struct r8152 *tp, bool enable) 3154 { 3155 u16 config1, config2, config3; 3156 u32 ocp_data; 3157 3158 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3159 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 3160 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 3161 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 3162 3163 if (enable) { 3164 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3165 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 3166 config1 |= sd_rise_time(1); 3167 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 3168 config3 |= fast_snr(42); 3169 } else { 3170 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3171 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 3172 RX_QUIET_EN); 3173 config1 |= sd_rise_time(7); 3174 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 3175 config3 |= fast_snr(511); 3176 } 3177 3178 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3179 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 3180 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 3181 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 3182 } 3183 3184 static void r8152b_enable_eee(struct r8152 *tp) 3185 { 3186 r8152_eee_en(tp, true); 3187 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); 3188 } 3189 3190 static void r8153_eee_en(struct r8152 *tp, bool enable) 3191 { 3192 u32 ocp_data; 3193 u16 config; 3194 3195 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3196 config = ocp_reg_read(tp, OCP_EEE_CFG); 3197 3198 if (enable) { 3199 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3200 config |= EEE10_EN; 3201 } else { 3202 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3203 config &= ~EEE10_EN; 3204 } 3205 3206 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3207 ocp_reg_write(tp, OCP_EEE_CFG, config); 3208 } 3209 3210 static void r8153_enable_eee(struct r8152 *tp) 3211 { 3212 r8153_eee_en(tp, true); 3213 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3214 } 3215 3216 static void r8152b_enable_fc(struct r8152 *tp) 3217 { 3218 u16 anar; 3219 3220 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3221 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 3222 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3223 } 3224 3225 static void rtl_tally_reset(struct r8152 *tp) 3226 { 3227 u32 ocp_data; 3228 3229 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 3230 ocp_data |= TALLY_RESET; 3231 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 3232 } 3233 3234 static void r8152b_init(struct r8152 *tp) 3235 { 3236 u32 ocp_data; 3237 3238 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3239 return; 3240 3241 r8152b_disable_aldps(tp); 3242 3243 if (tp->version == RTL_VER_01) { 3244 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 3245 ocp_data &= ~LED_MODE_MASK; 3246 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 3247 } 3248 3249 r8152_power_cut_en(tp, false); 3250 3251 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3252 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 3253 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3254 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 3255 ocp_data &= ~MCU_CLK_RATIO_MASK; 3256 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 3257 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 3258 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 3259 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 3260 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 3261 3262 r8152b_enable_eee(tp); 3263 r8152b_enable_aldps(tp); 3264 r8152b_enable_fc(tp); 3265 rtl_tally_reset(tp); 3266 3267 /* enable rx aggregation */ 3268 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 3269 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 3270 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 3271 } 3272 3273 static void r8153_init(struct r8152 *tp) 3274 { 3275 u32 ocp_data; 3276 int i; 3277 3278 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3279 return; 3280 3281 r8153_disable_aldps(tp); 3282 r8153_u1u2en(tp, false); 3283 3284 for (i = 0; i < 500; i++) { 3285 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 3286 AUTOLOAD_DONE) 3287 break; 3288 msleep(20); 3289 } 3290 3291 for (i = 0; i < 500; i++) { 3292 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; 3293 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) 3294 break; 3295 msleep(20); 3296 } 3297 3298 usb_disable_lpm(tp->udev); 3299 r8153_u2p3en(tp, false); 3300 3301 if (tp->version == RTL_VER_04) { 3302 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 3303 ocp_data &= ~pwd_dn_scale_mask; 3304 ocp_data |= pwd_dn_scale(96); 3305 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 3306 3307 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 3308 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 3309 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 3310 } else if (tp->version == RTL_VER_05) { 3311 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 3312 ocp_data &= ~ECM_ALDPS; 3313 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 3314 3315 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 3316 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 3317 ocp_data &= ~DYNAMIC_BURST; 3318 else 3319 ocp_data |= DYNAMIC_BURST; 3320 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 3321 } else if (tp->version == RTL_VER_06) { 3322 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 3323 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 3324 ocp_data &= ~DYNAMIC_BURST; 3325 else 3326 ocp_data |= DYNAMIC_BURST; 3327 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 3328 } 3329 3330 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 3331 ocp_data |= EP4_FULL_FC; 3332 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 3333 3334 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 3335 ocp_data &= ~TIMER11_EN; 3336 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 3337 3338 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 3339 ocp_data &= ~LED_MODE_MASK; 3340 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 3341 3342 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 3343 if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER) 3344 ocp_data |= LPM_TIMER_500MS; 3345 else 3346 ocp_data |= LPM_TIMER_500US; 3347 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 3348 3349 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 3350 ocp_data &= ~SEN_VAL_MASK; 3351 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 3352 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 3353 3354 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 3355 3356 r8153_power_cut_en(tp, false); 3357 r8153_u1u2en(tp, true); 3358 3359 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); 3360 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); 3361 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 3362 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | 3363 U1U2_SPDWN_EN | L1_SPDWN_EN); 3364 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 3365 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | 3366 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | 3367 EEE_SPDWN_EN); 3368 3369 r8153_enable_eee(tp); 3370 r8153_enable_aldps(tp); 3371 r8152b_enable_fc(tp); 3372 rtl_tally_reset(tp); 3373 r8153_u2p3en(tp, true); 3374 } 3375 3376 static int rtl8152_pre_reset(struct usb_interface *intf) 3377 { 3378 struct r8152 *tp = usb_get_intfdata(intf); 3379 struct net_device *netdev; 3380 3381 if (!tp) 3382 return 0; 3383 3384 netdev = tp->netdev; 3385 if (!netif_running(netdev)) 3386 return 0; 3387 3388 napi_disable(&tp->napi); 3389 clear_bit(WORK_ENABLE, &tp->flags); 3390 usb_kill_urb(tp->intr_urb); 3391 cancel_delayed_work_sync(&tp->schedule); 3392 if (netif_carrier_ok(netdev)) { 3393 netif_stop_queue(netdev); 3394 mutex_lock(&tp->control); 3395 tp->rtl_ops.disable(tp); 3396 mutex_unlock(&tp->control); 3397 } 3398 3399 return 0; 3400 } 3401 3402 static int rtl8152_post_reset(struct usb_interface *intf) 3403 { 3404 struct r8152 *tp = usb_get_intfdata(intf); 3405 struct net_device *netdev; 3406 3407 if (!tp) 3408 return 0; 3409 3410 netdev = tp->netdev; 3411 if (!netif_running(netdev)) 3412 return 0; 3413 3414 set_bit(WORK_ENABLE, &tp->flags); 3415 if (netif_carrier_ok(netdev)) { 3416 mutex_lock(&tp->control); 3417 tp->rtl_ops.enable(tp); 3418 rtl8152_set_rx_mode(netdev); 3419 mutex_unlock(&tp->control); 3420 netif_wake_queue(netdev); 3421 } 3422 3423 napi_enable(&tp->napi); 3424 3425 return 0; 3426 } 3427 3428 static bool delay_autosuspend(struct r8152 *tp) 3429 { 3430 bool sw_linking = !!netif_carrier_ok(tp->netdev); 3431 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); 3432 3433 /* This means a linking change occurs and the driver doesn't detect it, 3434 * yet. If the driver has disabled tx/rx and hw is linking on, the 3435 * device wouldn't wake up by receiving any packet. 3436 */ 3437 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) 3438 return true; 3439 3440 /* If the linking down is occurred by nway, the device may miss the 3441 * linking change event. And it wouldn't wake when linking on. 3442 */ 3443 if (!sw_linking && tp->rtl_ops.in_nway(tp)) 3444 return true; 3445 else 3446 return false; 3447 } 3448 3449 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 3450 { 3451 struct r8152 *tp = usb_get_intfdata(intf); 3452 struct net_device *netdev = tp->netdev; 3453 int ret = 0; 3454 3455 mutex_lock(&tp->control); 3456 3457 if (PMSG_IS_AUTO(message)) { 3458 if (netif_running(netdev) && delay_autosuspend(tp)) { 3459 ret = -EBUSY; 3460 goto out1; 3461 } 3462 3463 set_bit(SELECTIVE_SUSPEND, &tp->flags); 3464 } else { 3465 netif_device_detach(netdev); 3466 } 3467 3468 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 3469 clear_bit(WORK_ENABLE, &tp->flags); 3470 usb_kill_urb(tp->intr_urb); 3471 napi_disable(&tp->napi); 3472 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3473 rtl_stop_rx(tp); 3474 rtl_runtime_suspend_enable(tp, true); 3475 } else { 3476 cancel_delayed_work_sync(&tp->schedule); 3477 tp->rtl_ops.down(tp); 3478 } 3479 napi_enable(&tp->napi); 3480 } 3481 out1: 3482 mutex_unlock(&tp->control); 3483 3484 return ret; 3485 } 3486 3487 static int rtl8152_resume(struct usb_interface *intf) 3488 { 3489 struct r8152 *tp = usb_get_intfdata(intf); 3490 3491 mutex_lock(&tp->control); 3492 3493 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3494 tp->rtl_ops.init(tp); 3495 netif_device_attach(tp->netdev); 3496 } 3497 3498 if (netif_running(tp->netdev) && tp->netdev->flags & IFF_UP) { 3499 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3500 rtl_runtime_suspend_enable(tp, false); 3501 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3502 napi_disable(&tp->napi); 3503 set_bit(WORK_ENABLE, &tp->flags); 3504 if (netif_carrier_ok(tp->netdev)) 3505 rtl_start_rx(tp); 3506 napi_enable(&tp->napi); 3507 } else { 3508 tp->rtl_ops.up(tp); 3509 rtl8152_set_speed(tp, AUTONEG_ENABLE, 3510 tp->mii.supports_gmii ? 3511 SPEED_1000 : SPEED_100, 3512 DUPLEX_FULL); 3513 netif_carrier_off(tp->netdev); 3514 set_bit(WORK_ENABLE, &tp->flags); 3515 } 3516 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3517 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3518 if (tp->netdev->flags & IFF_UP) 3519 rtl_runtime_suspend_enable(tp, false); 3520 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3521 } 3522 3523 mutex_unlock(&tp->control); 3524 3525 return 0; 3526 } 3527 3528 static int rtl8152_reset_resume(struct usb_interface *intf) 3529 { 3530 struct r8152 *tp = usb_get_intfdata(intf); 3531 3532 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3533 return rtl8152_resume(intf); 3534 } 3535 3536 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3537 { 3538 struct r8152 *tp = netdev_priv(dev); 3539 3540 if (usb_autopm_get_interface(tp->intf) < 0) 3541 return; 3542 3543 if (!rtl_can_wakeup(tp)) { 3544 wol->supported = 0; 3545 wol->wolopts = 0; 3546 } else { 3547 mutex_lock(&tp->control); 3548 wol->supported = WAKE_ANY; 3549 wol->wolopts = __rtl_get_wol(tp); 3550 mutex_unlock(&tp->control); 3551 } 3552 3553 usb_autopm_put_interface(tp->intf); 3554 } 3555 3556 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3557 { 3558 struct r8152 *tp = netdev_priv(dev); 3559 int ret; 3560 3561 if (!rtl_can_wakeup(tp)) 3562 return -EOPNOTSUPP; 3563 3564 ret = usb_autopm_get_interface(tp->intf); 3565 if (ret < 0) 3566 goto out_set_wol; 3567 3568 mutex_lock(&tp->control); 3569 3570 __rtl_set_wol(tp, wol->wolopts); 3571 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 3572 3573 mutex_unlock(&tp->control); 3574 3575 usb_autopm_put_interface(tp->intf); 3576 3577 out_set_wol: 3578 return ret; 3579 } 3580 3581 static u32 rtl8152_get_msglevel(struct net_device *dev) 3582 { 3583 struct r8152 *tp = netdev_priv(dev); 3584 3585 return tp->msg_enable; 3586 } 3587 3588 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 3589 { 3590 struct r8152 *tp = netdev_priv(dev); 3591 3592 tp->msg_enable = value; 3593 } 3594 3595 static void rtl8152_get_drvinfo(struct net_device *netdev, 3596 struct ethtool_drvinfo *info) 3597 { 3598 struct r8152 *tp = netdev_priv(netdev); 3599 3600 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 3601 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 3602 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 3603 } 3604 3605 static 3606 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) 3607 { 3608 struct r8152 *tp = netdev_priv(netdev); 3609 int ret; 3610 3611 if (!tp->mii.mdio_read) 3612 return -EOPNOTSUPP; 3613 3614 ret = usb_autopm_get_interface(tp->intf); 3615 if (ret < 0) 3616 goto out; 3617 3618 mutex_lock(&tp->control); 3619 3620 ret = mii_ethtool_gset(&tp->mii, cmd); 3621 3622 mutex_unlock(&tp->control); 3623 3624 usb_autopm_put_interface(tp->intf); 3625 3626 out: 3627 return ret; 3628 } 3629 3630 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 3631 { 3632 struct r8152 *tp = netdev_priv(dev); 3633 int ret; 3634 3635 ret = usb_autopm_get_interface(tp->intf); 3636 if (ret < 0) 3637 goto out; 3638 3639 mutex_lock(&tp->control); 3640 3641 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); 3642 3643 mutex_unlock(&tp->control); 3644 3645 usb_autopm_put_interface(tp->intf); 3646 3647 out: 3648 return ret; 3649 } 3650 3651 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 3652 "tx_packets", 3653 "rx_packets", 3654 "tx_errors", 3655 "rx_errors", 3656 "rx_missed", 3657 "align_errors", 3658 "tx_single_collisions", 3659 "tx_multi_collisions", 3660 "rx_unicast", 3661 "rx_broadcast", 3662 "rx_multicast", 3663 "tx_aborted", 3664 "tx_underrun", 3665 }; 3666 3667 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 3668 { 3669 switch (sset) { 3670 case ETH_SS_STATS: 3671 return ARRAY_SIZE(rtl8152_gstrings); 3672 default: 3673 return -EOPNOTSUPP; 3674 } 3675 } 3676 3677 static void rtl8152_get_ethtool_stats(struct net_device *dev, 3678 struct ethtool_stats *stats, u64 *data) 3679 { 3680 struct r8152 *tp = netdev_priv(dev); 3681 struct tally_counter tally; 3682 3683 if (usb_autopm_get_interface(tp->intf) < 0) 3684 return; 3685 3686 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 3687 3688 usb_autopm_put_interface(tp->intf); 3689 3690 data[0] = le64_to_cpu(tally.tx_packets); 3691 data[1] = le64_to_cpu(tally.rx_packets); 3692 data[2] = le64_to_cpu(tally.tx_errors); 3693 data[3] = le32_to_cpu(tally.rx_errors); 3694 data[4] = le16_to_cpu(tally.rx_missed); 3695 data[5] = le16_to_cpu(tally.align_errors); 3696 data[6] = le32_to_cpu(tally.tx_one_collision); 3697 data[7] = le32_to_cpu(tally.tx_multi_collision); 3698 data[8] = le64_to_cpu(tally.rx_unicast); 3699 data[9] = le64_to_cpu(tally.rx_broadcast); 3700 data[10] = le32_to_cpu(tally.rx_multicast); 3701 data[11] = le16_to_cpu(tally.tx_aborted); 3702 data[12] = le16_to_cpu(tally.tx_underrun); 3703 } 3704 3705 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 3706 { 3707 switch (stringset) { 3708 case ETH_SS_STATS: 3709 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 3710 break; 3711 } 3712 } 3713 3714 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 3715 { 3716 u32 ocp_data, lp, adv, supported = 0; 3717 u16 val; 3718 3719 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 3720 supported = mmd_eee_cap_to_ethtool_sup_t(val); 3721 3722 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 3723 adv = mmd_eee_adv_to_ethtool_adv_t(val); 3724 3725 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 3726 lp = mmd_eee_adv_to_ethtool_adv_t(val); 3727 3728 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3729 ocp_data &= EEE_RX_EN | EEE_TX_EN; 3730 3731 eee->eee_enabled = !!ocp_data; 3732 eee->eee_active = !!(supported & adv & lp); 3733 eee->supported = supported; 3734 eee->advertised = adv; 3735 eee->lp_advertised = lp; 3736 3737 return 0; 3738 } 3739 3740 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 3741 { 3742 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 3743 3744 r8152_eee_en(tp, eee->eee_enabled); 3745 3746 if (!eee->eee_enabled) 3747 val = 0; 3748 3749 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); 3750 3751 return 0; 3752 } 3753 3754 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 3755 { 3756 u32 ocp_data, lp, adv, supported = 0; 3757 u16 val; 3758 3759 val = ocp_reg_read(tp, OCP_EEE_ABLE); 3760 supported = mmd_eee_cap_to_ethtool_sup_t(val); 3761 3762 val = ocp_reg_read(tp, OCP_EEE_ADV); 3763 adv = mmd_eee_adv_to_ethtool_adv_t(val); 3764 3765 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 3766 lp = mmd_eee_adv_to_ethtool_adv_t(val); 3767 3768 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3769 ocp_data &= EEE_RX_EN | EEE_TX_EN; 3770 3771 eee->eee_enabled = !!ocp_data; 3772 eee->eee_active = !!(supported & adv & lp); 3773 eee->supported = supported; 3774 eee->advertised = adv; 3775 eee->lp_advertised = lp; 3776 3777 return 0; 3778 } 3779 3780 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 3781 { 3782 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 3783 3784 r8153_eee_en(tp, eee->eee_enabled); 3785 3786 if (!eee->eee_enabled) 3787 val = 0; 3788 3789 ocp_reg_write(tp, OCP_EEE_ADV, val); 3790 3791 return 0; 3792 } 3793 3794 static int 3795 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) 3796 { 3797 struct r8152 *tp = netdev_priv(net); 3798 int ret; 3799 3800 ret = usb_autopm_get_interface(tp->intf); 3801 if (ret < 0) 3802 goto out; 3803 3804 mutex_lock(&tp->control); 3805 3806 ret = tp->rtl_ops.eee_get(tp, edata); 3807 3808 mutex_unlock(&tp->control); 3809 3810 usb_autopm_put_interface(tp->intf); 3811 3812 out: 3813 return ret; 3814 } 3815 3816 static int 3817 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) 3818 { 3819 struct r8152 *tp = netdev_priv(net); 3820 int ret; 3821 3822 ret = usb_autopm_get_interface(tp->intf); 3823 if (ret < 0) 3824 goto out; 3825 3826 mutex_lock(&tp->control); 3827 3828 ret = tp->rtl_ops.eee_set(tp, edata); 3829 if (!ret) 3830 ret = mii_nway_restart(&tp->mii); 3831 3832 mutex_unlock(&tp->control); 3833 3834 usb_autopm_put_interface(tp->intf); 3835 3836 out: 3837 return ret; 3838 } 3839 3840 static int rtl8152_nway_reset(struct net_device *dev) 3841 { 3842 struct r8152 *tp = netdev_priv(dev); 3843 int ret; 3844 3845 ret = usb_autopm_get_interface(tp->intf); 3846 if (ret < 0) 3847 goto out; 3848 3849 mutex_lock(&tp->control); 3850 3851 ret = mii_nway_restart(&tp->mii); 3852 3853 mutex_unlock(&tp->control); 3854 3855 usb_autopm_put_interface(tp->intf); 3856 3857 out: 3858 return ret; 3859 } 3860 3861 static int rtl8152_get_coalesce(struct net_device *netdev, 3862 struct ethtool_coalesce *coalesce) 3863 { 3864 struct r8152 *tp = netdev_priv(netdev); 3865 3866 switch (tp->version) { 3867 case RTL_VER_01: 3868 case RTL_VER_02: 3869 return -EOPNOTSUPP; 3870 default: 3871 break; 3872 } 3873 3874 coalesce->rx_coalesce_usecs = tp->coalesce; 3875 3876 return 0; 3877 } 3878 3879 static int rtl8152_set_coalesce(struct net_device *netdev, 3880 struct ethtool_coalesce *coalesce) 3881 { 3882 struct r8152 *tp = netdev_priv(netdev); 3883 int ret; 3884 3885 switch (tp->version) { 3886 case RTL_VER_01: 3887 case RTL_VER_02: 3888 return -EOPNOTSUPP; 3889 default: 3890 break; 3891 } 3892 3893 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) 3894 return -EINVAL; 3895 3896 ret = usb_autopm_get_interface(tp->intf); 3897 if (ret < 0) 3898 return ret; 3899 3900 mutex_lock(&tp->control); 3901 3902 if (tp->coalesce != coalesce->rx_coalesce_usecs) { 3903 tp->coalesce = coalesce->rx_coalesce_usecs; 3904 3905 if (netif_running(tp->netdev) && netif_carrier_ok(netdev)) 3906 r8153_set_rx_early_timeout(tp); 3907 } 3908 3909 mutex_unlock(&tp->control); 3910 3911 usb_autopm_put_interface(tp->intf); 3912 3913 return ret; 3914 } 3915 3916 static struct ethtool_ops ops = { 3917 .get_drvinfo = rtl8152_get_drvinfo, 3918 .get_settings = rtl8152_get_settings, 3919 .set_settings = rtl8152_set_settings, 3920 .get_link = ethtool_op_get_link, 3921 .nway_reset = rtl8152_nway_reset, 3922 .get_msglevel = rtl8152_get_msglevel, 3923 .set_msglevel = rtl8152_set_msglevel, 3924 .get_wol = rtl8152_get_wol, 3925 .set_wol = rtl8152_set_wol, 3926 .get_strings = rtl8152_get_strings, 3927 .get_sset_count = rtl8152_get_sset_count, 3928 .get_ethtool_stats = rtl8152_get_ethtool_stats, 3929 .get_coalesce = rtl8152_get_coalesce, 3930 .set_coalesce = rtl8152_set_coalesce, 3931 .get_eee = rtl_ethtool_get_eee, 3932 .set_eee = rtl_ethtool_set_eee, 3933 }; 3934 3935 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 3936 { 3937 struct r8152 *tp = netdev_priv(netdev); 3938 struct mii_ioctl_data *data = if_mii(rq); 3939 int res; 3940 3941 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3942 return -ENODEV; 3943 3944 res = usb_autopm_get_interface(tp->intf); 3945 if (res < 0) 3946 goto out; 3947 3948 switch (cmd) { 3949 case SIOCGMIIPHY: 3950 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 3951 break; 3952 3953 case SIOCGMIIREG: 3954 mutex_lock(&tp->control); 3955 data->val_out = r8152_mdio_read(tp, data->reg_num); 3956 mutex_unlock(&tp->control); 3957 break; 3958 3959 case SIOCSMIIREG: 3960 if (!capable(CAP_NET_ADMIN)) { 3961 res = -EPERM; 3962 break; 3963 } 3964 mutex_lock(&tp->control); 3965 r8152_mdio_write(tp, data->reg_num, data->val_in); 3966 mutex_unlock(&tp->control); 3967 break; 3968 3969 default: 3970 res = -EOPNOTSUPP; 3971 } 3972 3973 usb_autopm_put_interface(tp->intf); 3974 3975 out: 3976 return res; 3977 } 3978 3979 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 3980 { 3981 struct r8152 *tp = netdev_priv(dev); 3982 int ret; 3983 3984 switch (tp->version) { 3985 case RTL_VER_01: 3986 case RTL_VER_02: 3987 return eth_change_mtu(dev, new_mtu); 3988 default: 3989 break; 3990 } 3991 3992 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU) 3993 return -EINVAL; 3994 3995 ret = usb_autopm_get_interface(tp->intf); 3996 if (ret < 0) 3997 return ret; 3998 3999 mutex_lock(&tp->control); 4000 4001 dev->mtu = new_mtu; 4002 4003 if (netif_running(dev) && netif_carrier_ok(dev)) 4004 r8153_set_rx_early_size(tp); 4005 4006 mutex_unlock(&tp->control); 4007 4008 usb_autopm_put_interface(tp->intf); 4009 4010 return ret; 4011 } 4012 4013 static const struct net_device_ops rtl8152_netdev_ops = { 4014 .ndo_open = rtl8152_open, 4015 .ndo_stop = rtl8152_close, 4016 .ndo_do_ioctl = rtl8152_ioctl, 4017 .ndo_start_xmit = rtl8152_start_xmit, 4018 .ndo_tx_timeout = rtl8152_tx_timeout, 4019 .ndo_set_features = rtl8152_set_features, 4020 .ndo_set_rx_mode = rtl8152_set_rx_mode, 4021 .ndo_set_mac_address = rtl8152_set_mac_address, 4022 .ndo_change_mtu = rtl8152_change_mtu, 4023 .ndo_validate_addr = eth_validate_addr, 4024 .ndo_features_check = rtl8152_features_check, 4025 }; 4026 4027 static void r8152b_get_version(struct r8152 *tp) 4028 { 4029 u32 ocp_data; 4030 u16 version; 4031 4032 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); 4033 version = (u16)(ocp_data & VERSION_MASK); 4034 4035 switch (version) { 4036 case 0x4c00: 4037 tp->version = RTL_VER_01; 4038 break; 4039 case 0x4c10: 4040 tp->version = RTL_VER_02; 4041 break; 4042 case 0x5c00: 4043 tp->version = RTL_VER_03; 4044 tp->mii.supports_gmii = 1; 4045 break; 4046 case 0x5c10: 4047 tp->version = RTL_VER_04; 4048 tp->mii.supports_gmii = 1; 4049 break; 4050 case 0x5c20: 4051 tp->version = RTL_VER_05; 4052 tp->mii.supports_gmii = 1; 4053 break; 4054 case 0x5c30: 4055 tp->version = RTL_VER_06; 4056 tp->mii.supports_gmii = 1; 4057 break; 4058 default: 4059 netif_info(tp, probe, tp->netdev, 4060 "Unknown version 0x%04x\n", version); 4061 break; 4062 } 4063 } 4064 4065 static void rtl8152_unload(struct r8152 *tp) 4066 { 4067 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4068 return; 4069 4070 if (tp->version != RTL_VER_01) 4071 r8152_power_cut_en(tp, true); 4072 } 4073 4074 static void rtl8153_unload(struct r8152 *tp) 4075 { 4076 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4077 return; 4078 4079 r8153_power_cut_en(tp, false); 4080 } 4081 4082 static int rtl_ops_init(struct r8152 *tp) 4083 { 4084 struct rtl_ops *ops = &tp->rtl_ops; 4085 int ret = 0; 4086 4087 switch (tp->version) { 4088 case RTL_VER_01: 4089 case RTL_VER_02: 4090 ops->init = r8152b_init; 4091 ops->enable = rtl8152_enable; 4092 ops->disable = rtl8152_disable; 4093 ops->up = rtl8152_up; 4094 ops->down = rtl8152_down; 4095 ops->unload = rtl8152_unload; 4096 ops->eee_get = r8152_get_eee; 4097 ops->eee_set = r8152_set_eee; 4098 ops->in_nway = rtl8152_in_nway; 4099 break; 4100 4101 case RTL_VER_03: 4102 case RTL_VER_04: 4103 case RTL_VER_05: 4104 case RTL_VER_06: 4105 ops->init = r8153_init; 4106 ops->enable = rtl8153_enable; 4107 ops->disable = rtl8153_disable; 4108 ops->up = rtl8153_up; 4109 ops->down = rtl8153_down; 4110 ops->unload = rtl8153_unload; 4111 ops->eee_get = r8153_get_eee; 4112 ops->eee_set = r8153_set_eee; 4113 ops->in_nway = rtl8153_in_nway; 4114 break; 4115 4116 default: 4117 ret = -ENODEV; 4118 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 4119 break; 4120 } 4121 4122 return ret; 4123 } 4124 4125 static int rtl8152_probe(struct usb_interface *intf, 4126 const struct usb_device_id *id) 4127 { 4128 struct usb_device *udev = interface_to_usbdev(intf); 4129 struct r8152 *tp; 4130 struct net_device *netdev; 4131 int ret; 4132 4133 if (udev->actconfig->desc.bConfigurationValue != 1) { 4134 usb_driver_set_configuration(udev, 1); 4135 return -ENODEV; 4136 } 4137 4138 usb_reset_device(udev); 4139 netdev = alloc_etherdev(sizeof(struct r8152)); 4140 if (!netdev) { 4141 dev_err(&intf->dev, "Out of memory\n"); 4142 return -ENOMEM; 4143 } 4144 4145 SET_NETDEV_DEV(netdev, &intf->dev); 4146 tp = netdev_priv(netdev); 4147 tp->msg_enable = 0x7FFF; 4148 4149 tp->udev = udev; 4150 tp->netdev = netdev; 4151 tp->intf = intf; 4152 4153 r8152b_get_version(tp); 4154 ret = rtl_ops_init(tp); 4155 if (ret) 4156 goto out; 4157 4158 mutex_init(&tp->control); 4159 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 4160 4161 netdev->netdev_ops = &rtl8152_netdev_ops; 4162 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 4163 4164 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 4165 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 4166 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 4167 NETIF_F_HW_VLAN_CTAG_TX; 4168 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 4169 NETIF_F_TSO | NETIF_F_FRAGLIST | 4170 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 4171 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; 4172 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 4173 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 4174 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 4175 4176 netdev->ethtool_ops = &ops; 4177 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 4178 4179 tp->mii.dev = netdev; 4180 tp->mii.mdio_read = read_mii_word; 4181 tp->mii.mdio_write = write_mii_word; 4182 tp->mii.phy_id_mask = 0x3f; 4183 tp->mii.reg_num_mask = 0x1f; 4184 tp->mii.phy_id = R8152_PHY_ID; 4185 4186 switch (udev->speed) { 4187 case USB_SPEED_SUPER: 4188 tp->coalesce = COALESCE_SUPER; 4189 break; 4190 case USB_SPEED_HIGH: 4191 tp->coalesce = COALESCE_HIGH; 4192 break; 4193 default: 4194 tp->coalesce = COALESCE_SLOW; 4195 break; 4196 } 4197 4198 intf->needs_remote_wakeup = 1; 4199 4200 tp->rtl_ops.init(tp); 4201 set_ethernet_addr(tp); 4202 4203 usb_set_intfdata(intf, tp); 4204 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); 4205 4206 ret = register_netdev(netdev); 4207 if (ret != 0) { 4208 netif_err(tp, probe, netdev, "couldn't register the device\n"); 4209 goto out1; 4210 } 4211 4212 if (!rtl_can_wakeup(tp)) 4213 __rtl_set_wol(tp, 0); 4214 4215 tp->saved_wolopts = __rtl_get_wol(tp); 4216 if (tp->saved_wolopts) 4217 device_set_wakeup_enable(&udev->dev, true); 4218 else 4219 device_set_wakeup_enable(&udev->dev, false); 4220 4221 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 4222 4223 return 0; 4224 4225 out1: 4226 netif_napi_del(&tp->napi); 4227 usb_set_intfdata(intf, NULL); 4228 out: 4229 free_netdev(netdev); 4230 return ret; 4231 } 4232 4233 static void rtl8152_disconnect(struct usb_interface *intf) 4234 { 4235 struct r8152 *tp = usb_get_intfdata(intf); 4236 4237 usb_set_intfdata(intf, NULL); 4238 if (tp) { 4239 struct usb_device *udev = tp->udev; 4240 4241 if (udev->state == USB_STATE_NOTATTACHED) 4242 set_bit(RTL8152_UNPLUG, &tp->flags); 4243 4244 netif_napi_del(&tp->napi); 4245 unregister_netdev(tp->netdev); 4246 tp->rtl_ops.unload(tp); 4247 free_netdev(tp->netdev); 4248 } 4249 } 4250 4251 #define REALTEK_USB_DEVICE(vend, prod) \ 4252 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ 4253 USB_DEVICE_ID_MATCH_INT_CLASS, \ 4254 .idVendor = (vend), \ 4255 .idProduct = (prod), \ 4256 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ 4257 }, \ 4258 { \ 4259 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ 4260 USB_DEVICE_ID_MATCH_DEVICE, \ 4261 .idVendor = (vend), \ 4262 .idProduct = (prod), \ 4263 .bInterfaceClass = USB_CLASS_COMM, \ 4264 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ 4265 .bInterfaceProtocol = USB_CDC_PROTO_NONE 4266 4267 /* table of devices that work with this driver */ 4268 static struct usb_device_id rtl8152_table[] = { 4269 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, 4270 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, 4271 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, 4272 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, 4273 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, 4274 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, 4275 {} 4276 }; 4277 4278 MODULE_DEVICE_TABLE(usb, rtl8152_table); 4279 4280 static struct usb_driver rtl8152_driver = { 4281 .name = MODULENAME, 4282 .id_table = rtl8152_table, 4283 .probe = rtl8152_probe, 4284 .disconnect = rtl8152_disconnect, 4285 .suspend = rtl8152_suspend, 4286 .resume = rtl8152_resume, 4287 .reset_resume = rtl8152_reset_resume, 4288 .pre_reset = rtl8152_pre_reset, 4289 .post_reset = rtl8152_post_reset, 4290 .supports_autosuspend = 1, 4291 .disable_hub_initiated_lpm = 1, 4292 }; 4293 4294 module_usb_driver(rtl8152_driver); 4295 4296 MODULE_AUTHOR(DRIVER_AUTHOR); 4297 MODULE_DESCRIPTION(DRIVER_DESC); 4298 MODULE_LICENSE("GPL"); 4299