1 /* 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2 as published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/signal.h> 11 #include <linux/slab.h> 12 #include <linux/module.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/usb.h> 18 #include <linux/crc32.h> 19 #include <linux/if_vlan.h> 20 #include <linux/uaccess.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include <net/ip6_checksum.h> 25 #include <uapi/linux/mdio.h> 26 #include <linux/mdio.h> 27 #include <linux/usb/cdc.h> 28 #include <linux/suspend.h> 29 #include <linux/acpi.h> 30 31 /* Information for net-next */ 32 #define NETNEXT_VERSION "08" 33 34 /* Information for net */ 35 #define NET_VERSION "5" 36 37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION 38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 40 #define MODULENAME "r8152" 41 42 #define R8152_PHY_ID 32 43 44 #define PLA_IDR 0xc000 45 #define PLA_RCR 0xc010 46 #define PLA_RMS 0xc016 47 #define PLA_RXFIFO_CTRL0 0xc0a0 48 #define PLA_RXFIFO_CTRL1 0xc0a4 49 #define PLA_RXFIFO_CTRL2 0xc0a8 50 #define PLA_DMY_REG0 0xc0b0 51 #define PLA_FMC 0xc0b4 52 #define PLA_CFG_WOL 0xc0b6 53 #define PLA_TEREDO_CFG 0xc0bc 54 #define PLA_MAR 0xcd00 55 #define PLA_BACKUP 0xd000 56 #define PAL_BDC_CR 0xd1a0 57 #define PLA_TEREDO_TIMER 0xd2cc 58 #define PLA_REALWOW_TIMER 0xd2e8 59 #define PLA_LEDSEL 0xdd90 60 #define PLA_LED_FEATURE 0xdd92 61 #define PLA_PHYAR 0xde00 62 #define PLA_BOOT_CTRL 0xe004 63 #define PLA_GPHY_INTR_IMR 0xe022 64 #define PLA_EEE_CR 0xe040 65 #define PLA_EEEP_CR 0xe080 66 #define PLA_MAC_PWR_CTRL 0xe0c0 67 #define PLA_MAC_PWR_CTRL2 0xe0ca 68 #define PLA_MAC_PWR_CTRL3 0xe0cc 69 #define PLA_MAC_PWR_CTRL4 0xe0ce 70 #define PLA_WDT6_CTRL 0xe428 71 #define PLA_TCR0 0xe610 72 #define PLA_TCR1 0xe612 73 #define PLA_MTPS 0xe615 74 #define PLA_TXFIFO_CTRL 0xe618 75 #define PLA_RSTTALLY 0xe800 76 #define PLA_CR 0xe813 77 #define PLA_CRWECR 0xe81c 78 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 79 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 80 #define PLA_CONFIG5 0xe822 81 #define PLA_PHY_PWR 0xe84c 82 #define PLA_OOB_CTRL 0xe84f 83 #define PLA_CPCR 0xe854 84 #define PLA_MISC_0 0xe858 85 #define PLA_MISC_1 0xe85a 86 #define PLA_OCP_GPHY_BASE 0xe86c 87 #define PLA_TALLYCNT 0xe890 88 #define PLA_SFF_STS_7 0xe8de 89 #define PLA_PHYSTATUS 0xe908 90 #define PLA_BP_BA 0xfc26 91 #define PLA_BP_0 0xfc28 92 #define PLA_BP_1 0xfc2a 93 #define PLA_BP_2 0xfc2c 94 #define PLA_BP_3 0xfc2e 95 #define PLA_BP_4 0xfc30 96 #define PLA_BP_5 0xfc32 97 #define PLA_BP_6 0xfc34 98 #define PLA_BP_7 0xfc36 99 #define PLA_BP_EN 0xfc38 100 101 #define USB_USB2PHY 0xb41e 102 #define USB_SSPHYLINK2 0xb428 103 #define USB_U2P3_CTRL 0xb460 104 #define USB_CSR_DUMMY1 0xb464 105 #define USB_CSR_DUMMY2 0xb466 106 #define USB_DEV_STAT 0xb808 107 #define USB_CONNECT_TIMER 0xcbf8 108 #define USB_BURST_SIZE 0xcfc0 109 #define USB_USB_CTRL 0xd406 110 #define USB_PHY_CTRL 0xd408 111 #define USB_TX_AGG 0xd40a 112 #define USB_RX_BUF_TH 0xd40c 113 #define USB_USB_TIMER 0xd428 114 #define USB_RX_EARLY_TIMEOUT 0xd42c 115 #define USB_RX_EARLY_SIZE 0xd42e 116 #define USB_PM_CTRL_STATUS 0xd432 117 #define USB_TX_DMA 0xd434 118 #define USB_TOLERANCE 0xd490 119 #define USB_LPM_CTRL 0xd41a 120 #define USB_BMU_RESET 0xd4b0 121 #define USB_UPS_CTRL 0xd800 122 #define USB_MISC_0 0xd81a 123 #define USB_POWER_CUT 0xd80a 124 #define USB_AFE_CTRL2 0xd824 125 #define USB_WDT11_CTRL 0xe43c 126 #define USB_BP_BA 0xfc26 127 #define USB_BP_0 0xfc28 128 #define USB_BP_1 0xfc2a 129 #define USB_BP_2 0xfc2c 130 #define USB_BP_3 0xfc2e 131 #define USB_BP_4 0xfc30 132 #define USB_BP_5 0xfc32 133 #define USB_BP_6 0xfc34 134 #define USB_BP_7 0xfc36 135 #define USB_BP_EN 0xfc38 136 137 /* OCP Registers */ 138 #define OCP_ALDPS_CONFIG 0x2010 139 #define OCP_EEE_CONFIG1 0x2080 140 #define OCP_EEE_CONFIG2 0x2092 141 #define OCP_EEE_CONFIG3 0x2094 142 #define OCP_BASE_MII 0xa400 143 #define OCP_EEE_AR 0xa41a 144 #define OCP_EEE_DATA 0xa41c 145 #define OCP_PHY_STATUS 0xa420 146 #define OCP_POWER_CFG 0xa430 147 #define OCP_EEE_CFG 0xa432 148 #define OCP_SRAM_ADDR 0xa436 149 #define OCP_SRAM_DATA 0xa438 150 #define OCP_DOWN_SPEED 0xa442 151 #define OCP_EEE_ABLE 0xa5c4 152 #define OCP_EEE_ADV 0xa5d0 153 #define OCP_EEE_LPABLE 0xa5d2 154 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ 155 #define OCP_ADC_CFG 0xbc06 156 157 /* SRAM Register */ 158 #define SRAM_LPF_CFG 0x8012 159 #define SRAM_10M_AMP1 0x8080 160 #define SRAM_10M_AMP2 0x8082 161 #define SRAM_IMPEDANCE 0x8084 162 163 /* PLA_RCR */ 164 #define RCR_AAP 0x00000001 165 #define RCR_APM 0x00000002 166 #define RCR_AM 0x00000004 167 #define RCR_AB 0x00000008 168 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 169 170 /* PLA_RXFIFO_CTRL0 */ 171 #define RXFIFO_THR1_NORMAL 0x00080002 172 #define RXFIFO_THR1_OOB 0x01800003 173 174 /* PLA_RXFIFO_CTRL1 */ 175 #define RXFIFO_THR2_FULL 0x00000060 176 #define RXFIFO_THR2_HIGH 0x00000038 177 #define RXFIFO_THR2_OOB 0x0000004a 178 #define RXFIFO_THR2_NORMAL 0x00a0 179 180 /* PLA_RXFIFO_CTRL2 */ 181 #define RXFIFO_THR3_FULL 0x00000078 182 #define RXFIFO_THR3_HIGH 0x00000048 183 #define RXFIFO_THR3_OOB 0x0000005a 184 #define RXFIFO_THR3_NORMAL 0x0110 185 186 /* PLA_TXFIFO_CTRL */ 187 #define TXFIFO_THR_NORMAL 0x00400008 188 #define TXFIFO_THR_NORMAL2 0x01000008 189 190 /* PLA_DMY_REG0 */ 191 #define ECM_ALDPS 0x0002 192 193 /* PLA_FMC */ 194 #define FMC_FCR_MCU_EN 0x0001 195 196 /* PLA_EEEP_CR */ 197 #define EEEP_CR_EEEP_TX 0x0002 198 199 /* PLA_WDT6_CTRL */ 200 #define WDT6_SET_MODE 0x0010 201 202 /* PLA_TCR0 */ 203 #define TCR0_TX_EMPTY 0x0800 204 #define TCR0_AUTO_FIFO 0x0080 205 206 /* PLA_TCR1 */ 207 #define VERSION_MASK 0x7cf0 208 209 /* PLA_MTPS */ 210 #define MTPS_JUMBO (12 * 1024 / 64) 211 #define MTPS_DEFAULT (6 * 1024 / 64) 212 213 /* PLA_RSTTALLY */ 214 #define TALLY_RESET 0x0001 215 216 /* PLA_CR */ 217 #define CR_RST 0x10 218 #define CR_RE 0x08 219 #define CR_TE 0x04 220 221 /* PLA_CRWECR */ 222 #define CRWECR_NORAML 0x00 223 #define CRWECR_CONFIG 0xc0 224 225 /* PLA_OOB_CTRL */ 226 #define NOW_IS_OOB 0x80 227 #define TXFIFO_EMPTY 0x20 228 #define RXFIFO_EMPTY 0x10 229 #define LINK_LIST_READY 0x02 230 #define DIS_MCU_CLROOB 0x01 231 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 232 233 /* PLA_MISC_1 */ 234 #define RXDY_GATED_EN 0x0008 235 236 /* PLA_SFF_STS_7 */ 237 #define RE_INIT_LL 0x8000 238 #define MCU_BORW_EN 0x4000 239 240 /* PLA_CPCR */ 241 #define CPCR_RX_VLAN 0x0040 242 243 /* PLA_CFG_WOL */ 244 #define MAGIC_EN 0x0001 245 246 /* PLA_TEREDO_CFG */ 247 #define TEREDO_SEL 0x8000 248 #define TEREDO_WAKE_MASK 0x7f00 249 #define TEREDO_RS_EVENT_MASK 0x00fe 250 #define OOB_TEREDO_EN 0x0001 251 252 /* PAL_BDC_CR */ 253 #define ALDPS_PROXY_MODE 0x0001 254 255 /* PLA_CONFIG34 */ 256 #define LINK_ON_WAKE_EN 0x0010 257 #define LINK_OFF_WAKE_EN 0x0008 258 259 /* PLA_CONFIG5 */ 260 #define BWF_EN 0x0040 261 #define MWF_EN 0x0020 262 #define UWF_EN 0x0010 263 #define LAN_WAKE_EN 0x0002 264 265 /* PLA_LED_FEATURE */ 266 #define LED_MODE_MASK 0x0700 267 268 /* PLA_PHY_PWR */ 269 #define TX_10M_IDLE_EN 0x0080 270 #define PFM_PWM_SWITCH 0x0040 271 272 /* PLA_MAC_PWR_CTRL */ 273 #define D3_CLK_GATED_EN 0x00004000 274 #define MCU_CLK_RATIO 0x07010f07 275 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f 276 #define ALDPS_SPDWN_RATIO 0x0f87 277 278 /* PLA_MAC_PWR_CTRL2 */ 279 #define EEE_SPDWN_RATIO 0x8007 280 281 /* PLA_MAC_PWR_CTRL3 */ 282 #define PKT_AVAIL_SPDWN_EN 0x0100 283 #define SUSPEND_SPDWN_EN 0x0004 284 #define U1U2_SPDWN_EN 0x0002 285 #define L1_SPDWN_EN 0x0001 286 287 /* PLA_MAC_PWR_CTRL4 */ 288 #define PWRSAVE_SPDWN_EN 0x1000 289 #define RXDV_SPDWN_EN 0x0800 290 #define TX10MIDLE_EN 0x0100 291 #define TP100_SPDWN_EN 0x0020 292 #define TP500_SPDWN_EN 0x0010 293 #define TP1000_SPDWN_EN 0x0008 294 #define EEE_SPDWN_EN 0x0001 295 296 /* PLA_GPHY_INTR_IMR */ 297 #define GPHY_STS_MSK 0x0001 298 #define SPEED_DOWN_MSK 0x0002 299 #define SPDWN_RXDV_MSK 0x0004 300 #define SPDWN_LINKCHG_MSK 0x0008 301 302 /* PLA_PHYAR */ 303 #define PHYAR_FLAG 0x80000000 304 305 /* PLA_EEE_CR */ 306 #define EEE_RX_EN 0x0001 307 #define EEE_TX_EN 0x0002 308 309 /* PLA_BOOT_CTRL */ 310 #define AUTOLOAD_DONE 0x0002 311 312 /* USB_USB2PHY */ 313 #define USB2PHY_SUSPEND 0x0001 314 #define USB2PHY_L1 0x0002 315 316 /* USB_SSPHYLINK2 */ 317 #define pwd_dn_scale_mask 0x3ffe 318 #define pwd_dn_scale(x) ((x) << 1) 319 320 /* USB_CSR_DUMMY1 */ 321 #define DYNAMIC_BURST 0x0001 322 323 /* USB_CSR_DUMMY2 */ 324 #define EP4_FULL_FC 0x0001 325 326 /* USB_DEV_STAT */ 327 #define STAT_SPEED_MASK 0x0006 328 #define STAT_SPEED_HIGH 0x0000 329 #define STAT_SPEED_FULL 0x0002 330 331 /* USB_TX_AGG */ 332 #define TX_AGG_MAX_THRESHOLD 0x03 333 334 /* USB_RX_BUF_TH */ 335 #define RX_THR_SUPPER 0x0c350180 336 #define RX_THR_HIGH 0x7a120180 337 #define RX_THR_SLOW 0xffff0180 338 339 /* USB_TX_DMA */ 340 #define TEST_MODE_DISABLE 0x00000001 341 #define TX_SIZE_ADJUST1 0x00000100 342 343 /* USB_BMU_RESET */ 344 #define BMU_RESET_EP_IN 0x01 345 #define BMU_RESET_EP_OUT 0x02 346 347 /* USB_UPS_CTRL */ 348 #define POWER_CUT 0x0100 349 350 /* USB_PM_CTRL_STATUS */ 351 #define RESUME_INDICATE 0x0001 352 353 /* USB_USB_CTRL */ 354 #define RX_AGG_DISABLE 0x0010 355 #define RX_ZERO_EN 0x0080 356 357 /* USB_U2P3_CTRL */ 358 #define U2P3_ENABLE 0x0001 359 360 /* USB_POWER_CUT */ 361 #define PWR_EN 0x0001 362 #define PHASE2_EN 0x0008 363 364 /* USB_MISC_0 */ 365 #define PCUT_STATUS 0x0001 366 367 /* USB_RX_EARLY_TIMEOUT */ 368 #define COALESCE_SUPER 85000U 369 #define COALESCE_HIGH 250000U 370 #define COALESCE_SLOW 524280U 371 372 /* USB_WDT11_CTRL */ 373 #define TIMER11_EN 0x0001 374 375 /* USB_LPM_CTRL */ 376 /* bit 4 ~ 5: fifo empty boundary */ 377 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 378 /* bit 2 ~ 3: LMP timer */ 379 #define LPM_TIMER_MASK 0x0c 380 #define LPM_TIMER_500MS 0x04 /* 500 ms */ 381 #define LPM_TIMER_500US 0x0c /* 500 us */ 382 #define ROK_EXIT_LPM 0x02 383 384 /* USB_AFE_CTRL2 */ 385 #define SEN_VAL_MASK 0xf800 386 #define SEN_VAL_NORMAL 0xa000 387 #define SEL_RXIDLE 0x0100 388 389 /* OCP_ALDPS_CONFIG */ 390 #define ENPWRSAVE 0x8000 391 #define ENPDNPS 0x0200 392 #define LINKENA 0x0100 393 #define DIS_SDSAVE 0x0010 394 395 /* OCP_PHY_STATUS */ 396 #define PHY_STAT_MASK 0x0007 397 #define PHY_STAT_LAN_ON 3 398 #define PHY_STAT_PWRDN 5 399 400 /* OCP_POWER_CFG */ 401 #define EEE_CLKDIV_EN 0x8000 402 #define EN_ALDPS 0x0004 403 #define EN_10M_PLLOFF 0x0001 404 405 /* OCP_EEE_CONFIG1 */ 406 #define RG_TXLPI_MSK_HFDUP 0x8000 407 #define RG_MATCLR_EN 0x4000 408 #define EEE_10_CAP 0x2000 409 #define EEE_NWAY_EN 0x1000 410 #define TX_QUIET_EN 0x0200 411 #define RX_QUIET_EN 0x0100 412 #define sd_rise_time_mask 0x0070 413 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 414 #define RG_RXLPI_MSK_HFDUP 0x0008 415 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 416 417 /* OCP_EEE_CONFIG2 */ 418 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 419 #define RG_DACQUIET_EN 0x0400 420 #define RG_LDVQUIET_EN 0x0200 421 #define RG_CKRSEL 0x0020 422 #define RG_EEEPRG_EN 0x0010 423 424 /* OCP_EEE_CONFIG3 */ 425 #define fast_snr_mask 0xff80 426 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 427 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 428 #define MSK_PH 0x0006 /* bit 0 ~ 3 */ 429 430 /* OCP_EEE_AR */ 431 /* bit[15:14] function */ 432 #define FUN_ADDR 0x0000 433 #define FUN_DATA 0x4000 434 /* bit[4:0] device addr */ 435 436 /* OCP_EEE_CFG */ 437 #define CTAP_SHORT_EN 0x0040 438 #define EEE10_EN 0x0010 439 440 /* OCP_DOWN_SPEED */ 441 #define EN_10M_BGOFF 0x0080 442 443 /* OCP_PHY_STATE */ 444 #define TXDIS_STATE 0x01 445 #define ABD_STATE 0x02 446 447 /* OCP_ADC_CFG */ 448 #define CKADSEL_L 0x0100 449 #define ADC_EN 0x0080 450 #define EN_EMI_L 0x0040 451 452 /* SRAM_LPF_CFG */ 453 #define LPF_AUTO_TUNE 0x8000 454 455 /* SRAM_10M_AMP1 */ 456 #define GDAC_IB_UPALL 0x0008 457 458 /* SRAM_10M_AMP2 */ 459 #define AMP_DN 0x0200 460 461 /* SRAM_IMPEDANCE */ 462 #define RX_DRIVING_MASK 0x6000 463 464 /* MAC PASSTHRU */ 465 #define AD_MASK 0xfee0 466 #define EFUSE 0xcfdb 467 #define PASS_THRU_MASK 0x1 468 469 enum rtl_register_content { 470 _1000bps = 0x10, 471 _100bps = 0x08, 472 _10bps = 0x04, 473 LINK_STATUS = 0x02, 474 FULL_DUP = 0x01, 475 }; 476 477 #define RTL8152_MAX_TX 4 478 #define RTL8152_MAX_RX 10 479 #define INTBUFSIZE 2 480 #define CRC_SIZE 4 481 #define TX_ALIGN 4 482 #define RX_ALIGN 8 483 484 #define INTR_LINK 0x0004 485 486 #define RTL8152_REQT_READ 0xc0 487 #define RTL8152_REQT_WRITE 0x40 488 #define RTL8152_REQ_GET_REGS 0x05 489 #define RTL8152_REQ_SET_REGS 0x05 490 491 #define BYTE_EN_DWORD 0xff 492 #define BYTE_EN_WORD 0x33 493 #define BYTE_EN_BYTE 0x11 494 #define BYTE_EN_SIX_BYTES 0x3f 495 #define BYTE_EN_START_MASK 0x0f 496 #define BYTE_EN_END_MASK 0xf0 497 498 #define RTL8153_MAX_PACKET 9216 /* 9K */ 499 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN) 500 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) 501 #define RTL8153_RMS RTL8153_MAX_PACKET 502 #define RTL8152_TX_TIMEOUT (5 * HZ) 503 #define RTL8152_NAPI_WEIGHT 64 504 505 /* rtl8152 flags */ 506 enum rtl8152_flags { 507 RTL8152_UNPLUG = 0, 508 RTL8152_SET_RX_MODE, 509 WORK_ENABLE, 510 RTL8152_LINK_CHG, 511 SELECTIVE_SUSPEND, 512 PHY_RESET, 513 SCHEDULE_NAPI, 514 }; 515 516 /* Define these values to match your device */ 517 #define VENDOR_ID_REALTEK 0x0bda 518 #define VENDOR_ID_SAMSUNG 0x04e8 519 #define VENDOR_ID_LENOVO 0x17ef 520 #define VENDOR_ID_NVIDIA 0x0955 521 522 #define MCU_TYPE_PLA 0x0100 523 #define MCU_TYPE_USB 0x0000 524 525 struct tally_counter { 526 __le64 tx_packets; 527 __le64 rx_packets; 528 __le64 tx_errors; 529 __le32 rx_errors; 530 __le16 rx_missed; 531 __le16 align_errors; 532 __le32 tx_one_collision; 533 __le32 tx_multi_collision; 534 __le64 rx_unicast; 535 __le64 rx_broadcast; 536 __le32 rx_multicast; 537 __le16 tx_aborted; 538 __le16 tx_underrun; 539 }; 540 541 struct rx_desc { 542 __le32 opts1; 543 #define RX_LEN_MASK 0x7fff 544 545 __le32 opts2; 546 #define RD_UDP_CS BIT(23) 547 #define RD_TCP_CS BIT(22) 548 #define RD_IPV6_CS BIT(20) 549 #define RD_IPV4_CS BIT(19) 550 551 __le32 opts3; 552 #define IPF BIT(23) /* IP checksum fail */ 553 #define UDPF BIT(22) /* UDP checksum fail */ 554 #define TCPF BIT(21) /* TCP checksum fail */ 555 #define RX_VLAN_TAG BIT(16) 556 557 __le32 opts4; 558 __le32 opts5; 559 __le32 opts6; 560 }; 561 562 struct tx_desc { 563 __le32 opts1; 564 #define TX_FS BIT(31) /* First segment of a packet */ 565 #define TX_LS BIT(30) /* Final segment of a packet */ 566 #define GTSENDV4 BIT(28) 567 #define GTSENDV6 BIT(27) 568 #define GTTCPHO_SHIFT 18 569 #define GTTCPHO_MAX 0x7fU 570 #define TX_LEN_MAX 0x3ffffU 571 572 __le32 opts2; 573 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 574 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 575 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 576 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 577 #define MSS_SHIFT 17 578 #define MSS_MAX 0x7ffU 579 #define TCPHO_SHIFT 17 580 #define TCPHO_MAX 0x7ffU 581 #define TX_VLAN_TAG BIT(16) 582 }; 583 584 struct r8152; 585 586 struct rx_agg { 587 struct list_head list; 588 struct urb *urb; 589 struct r8152 *context; 590 void *buffer; 591 void *head; 592 }; 593 594 struct tx_agg { 595 struct list_head list; 596 struct urb *urb; 597 struct r8152 *context; 598 void *buffer; 599 void *head; 600 u32 skb_num; 601 u32 skb_len; 602 }; 603 604 struct r8152 { 605 unsigned long flags; 606 struct usb_device *udev; 607 struct napi_struct napi; 608 struct usb_interface *intf; 609 struct net_device *netdev; 610 struct urb *intr_urb; 611 struct tx_agg tx_info[RTL8152_MAX_TX]; 612 struct rx_agg rx_info[RTL8152_MAX_RX]; 613 struct list_head rx_done, tx_free; 614 struct sk_buff_head tx_queue, rx_queue; 615 spinlock_t rx_lock, tx_lock; 616 struct delayed_work schedule; 617 struct mii_if_info mii; 618 struct mutex control; /* use for hw setting */ 619 #ifdef CONFIG_PM_SLEEP 620 struct notifier_block pm_notifier; 621 #endif 622 623 struct rtl_ops { 624 void (*init)(struct r8152 *); 625 int (*enable)(struct r8152 *); 626 void (*disable)(struct r8152 *); 627 void (*up)(struct r8152 *); 628 void (*down)(struct r8152 *); 629 void (*unload)(struct r8152 *); 630 int (*eee_get)(struct r8152 *, struct ethtool_eee *); 631 int (*eee_set)(struct r8152 *, struct ethtool_eee *); 632 bool (*in_nway)(struct r8152 *); 633 void (*autosuspend_en)(struct r8152 *tp, bool enable); 634 } rtl_ops; 635 636 int intr_interval; 637 u32 saved_wolopts; 638 u32 msg_enable; 639 u32 tx_qlen; 640 u32 coalesce; 641 u16 ocp_base; 642 u8 *intr_buff; 643 u8 version; 644 }; 645 646 enum rtl_version { 647 RTL_VER_UNKNOWN = 0, 648 RTL_VER_01, 649 RTL_VER_02, 650 RTL_VER_03, 651 RTL_VER_04, 652 RTL_VER_05, 653 RTL_VER_06, 654 RTL_VER_MAX 655 }; 656 657 enum tx_csum_stat { 658 TX_CSUM_SUCCESS = 0, 659 TX_CSUM_TSO, 660 TX_CSUM_NONE 661 }; 662 663 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 664 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 665 */ 666 static const int multicast_filter_limit = 32; 667 static unsigned int agg_buf_sz = 16384; 668 669 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ 670 VLAN_ETH_HLEN - VLAN_HLEN) 671 672 static 673 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 674 { 675 int ret; 676 void *tmp; 677 678 tmp = kmalloc(size, GFP_KERNEL); 679 if (!tmp) 680 return -ENOMEM; 681 682 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 683 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 684 value, index, tmp, size, 500); 685 686 memcpy(data, tmp, size); 687 kfree(tmp); 688 689 return ret; 690 } 691 692 static 693 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 694 { 695 int ret; 696 void *tmp; 697 698 tmp = kmemdup(data, size, GFP_KERNEL); 699 if (!tmp) 700 return -ENOMEM; 701 702 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 703 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 704 value, index, tmp, size, 500); 705 706 kfree(tmp); 707 708 return ret; 709 } 710 711 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 712 void *data, u16 type) 713 { 714 u16 limit = 64; 715 int ret = 0; 716 717 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 718 return -ENODEV; 719 720 /* both size and indix must be 4 bytes align */ 721 if ((size & 3) || !size || (index & 3) || !data) 722 return -EPERM; 723 724 if ((u32)index + (u32)size > 0xffff) 725 return -EPERM; 726 727 while (size) { 728 if (size > limit) { 729 ret = get_registers(tp, index, type, limit, data); 730 if (ret < 0) 731 break; 732 733 index += limit; 734 data += limit; 735 size -= limit; 736 } else { 737 ret = get_registers(tp, index, type, size, data); 738 if (ret < 0) 739 break; 740 741 index += size; 742 data += size; 743 size = 0; 744 break; 745 } 746 } 747 748 if (ret == -ENODEV) 749 set_bit(RTL8152_UNPLUG, &tp->flags); 750 751 return ret; 752 } 753 754 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 755 u16 size, void *data, u16 type) 756 { 757 int ret; 758 u16 byteen_start, byteen_end, byen; 759 u16 limit = 512; 760 761 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 762 return -ENODEV; 763 764 /* both size and indix must be 4 bytes align */ 765 if ((size & 3) || !size || (index & 3) || !data) 766 return -EPERM; 767 768 if ((u32)index + (u32)size > 0xffff) 769 return -EPERM; 770 771 byteen_start = byteen & BYTE_EN_START_MASK; 772 byteen_end = byteen & BYTE_EN_END_MASK; 773 774 byen = byteen_start | (byteen_start << 4); 775 ret = set_registers(tp, index, type | byen, 4, data); 776 if (ret < 0) 777 goto error1; 778 779 index += 4; 780 data += 4; 781 size -= 4; 782 783 if (size) { 784 size -= 4; 785 786 while (size) { 787 if (size > limit) { 788 ret = set_registers(tp, index, 789 type | BYTE_EN_DWORD, 790 limit, data); 791 if (ret < 0) 792 goto error1; 793 794 index += limit; 795 data += limit; 796 size -= limit; 797 } else { 798 ret = set_registers(tp, index, 799 type | BYTE_EN_DWORD, 800 size, data); 801 if (ret < 0) 802 goto error1; 803 804 index += size; 805 data += size; 806 size = 0; 807 break; 808 } 809 } 810 811 byen = byteen_end | (byteen_end >> 4); 812 ret = set_registers(tp, index, type | byen, 4, data); 813 if (ret < 0) 814 goto error1; 815 } 816 817 error1: 818 if (ret == -ENODEV) 819 set_bit(RTL8152_UNPLUG, &tp->flags); 820 821 return ret; 822 } 823 824 static inline 825 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 826 { 827 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 828 } 829 830 static inline 831 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 832 { 833 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 834 } 835 836 static inline 837 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 838 { 839 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); 840 } 841 842 static inline 843 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 844 { 845 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 846 } 847 848 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 849 { 850 __le32 data; 851 852 generic_ocp_read(tp, index, sizeof(data), &data, type); 853 854 return __le32_to_cpu(data); 855 } 856 857 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 858 { 859 __le32 tmp = __cpu_to_le32(data); 860 861 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 862 } 863 864 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 865 { 866 u32 data; 867 __le32 tmp; 868 u8 shift = index & 2; 869 870 index &= ~3; 871 872 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 873 874 data = __le32_to_cpu(tmp); 875 data >>= (shift * 8); 876 data &= 0xffff; 877 878 return (u16)data; 879 } 880 881 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 882 { 883 u32 mask = 0xffff; 884 __le32 tmp; 885 u16 byen = BYTE_EN_WORD; 886 u8 shift = index & 2; 887 888 data &= mask; 889 890 if (index & 2) { 891 byen <<= shift; 892 mask <<= (shift * 8); 893 data <<= (shift * 8); 894 index &= ~3; 895 } 896 897 tmp = __cpu_to_le32(data); 898 899 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 900 } 901 902 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 903 { 904 u32 data; 905 __le32 tmp; 906 u8 shift = index & 3; 907 908 index &= ~3; 909 910 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 911 912 data = __le32_to_cpu(tmp); 913 data >>= (shift * 8); 914 data &= 0xff; 915 916 return (u8)data; 917 } 918 919 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 920 { 921 u32 mask = 0xff; 922 __le32 tmp; 923 u16 byen = BYTE_EN_BYTE; 924 u8 shift = index & 3; 925 926 data &= mask; 927 928 if (index & 3) { 929 byen <<= shift; 930 mask <<= (shift * 8); 931 data <<= (shift * 8); 932 index &= ~3; 933 } 934 935 tmp = __cpu_to_le32(data); 936 937 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 938 } 939 940 static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 941 { 942 u16 ocp_base, ocp_index; 943 944 ocp_base = addr & 0xf000; 945 if (ocp_base != tp->ocp_base) { 946 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 947 tp->ocp_base = ocp_base; 948 } 949 950 ocp_index = (addr & 0x0fff) | 0xb000; 951 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 952 } 953 954 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 955 { 956 u16 ocp_base, ocp_index; 957 958 ocp_base = addr & 0xf000; 959 if (ocp_base != tp->ocp_base) { 960 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 961 tp->ocp_base = ocp_base; 962 } 963 964 ocp_index = (addr & 0x0fff) | 0xb000; 965 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 966 } 967 968 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 969 { 970 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 971 } 972 973 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 974 { 975 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 976 } 977 978 static void sram_write(struct r8152 *tp, u16 addr, u16 data) 979 { 980 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 981 ocp_reg_write(tp, OCP_SRAM_DATA, data); 982 } 983 984 static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 985 { 986 struct r8152 *tp = netdev_priv(netdev); 987 int ret; 988 989 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 990 return -ENODEV; 991 992 if (phy_id != R8152_PHY_ID) 993 return -EINVAL; 994 995 ret = r8152_mdio_read(tp, reg); 996 997 return ret; 998 } 999 1000 static 1001 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 1002 { 1003 struct r8152 *tp = netdev_priv(netdev); 1004 1005 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1006 return; 1007 1008 if (phy_id != R8152_PHY_ID) 1009 return; 1010 1011 r8152_mdio_write(tp, reg, val); 1012 } 1013 1014 static int 1015 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 1016 1017 static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1018 { 1019 struct r8152 *tp = netdev_priv(netdev); 1020 struct sockaddr *addr = p; 1021 int ret = -EADDRNOTAVAIL; 1022 1023 if (!is_valid_ether_addr(addr->sa_data)) 1024 goto out1; 1025 1026 ret = usb_autopm_get_interface(tp->intf); 1027 if (ret < 0) 1028 goto out1; 1029 1030 mutex_lock(&tp->control); 1031 1032 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1033 1034 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1035 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); 1036 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1037 1038 mutex_unlock(&tp->control); 1039 1040 usb_autopm_put_interface(tp->intf); 1041 out1: 1042 return ret; 1043 } 1044 1045 /* Devices containing RTL8153-AD can support a persistent 1046 * host system provided MAC address. 1047 * Examples of this are Dell TB15 and Dell WD15 docks 1048 */ 1049 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) 1050 { 1051 acpi_status status; 1052 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1053 union acpi_object *obj; 1054 int ret = -EINVAL; 1055 u32 ocp_data; 1056 unsigned char buf[6]; 1057 1058 /* test for -AD variant of RTL8153 */ 1059 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 1060 if ((ocp_data & AD_MASK) != 0x1000) 1061 return -ENODEV; 1062 1063 /* test for MAC address pass-through bit */ 1064 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); 1065 if ((ocp_data & PASS_THRU_MASK) != 1) 1066 return -ENODEV; 1067 1068 /* returns _AUXMAC_#AABBCCDDEEFF# */ 1069 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer); 1070 obj = (union acpi_object *)buffer.pointer; 1071 if (!ACPI_SUCCESS(status)) 1072 return -ENODEV; 1073 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) { 1074 netif_warn(tp, probe, tp->netdev, 1075 "Invalid buffer when reading pass-thru MAC addr: " 1076 "(%d, %d)\n", 1077 obj->type, obj->string.length); 1078 goto amacout; 1079 } 1080 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || 1081 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { 1082 netif_warn(tp, probe, tp->netdev, 1083 "Invalid header when reading pass-thru MAC addr\n"); 1084 goto amacout; 1085 } 1086 ret = hex2bin(buf, obj->string.pointer + 9, 6); 1087 if (!(ret == 0 && is_valid_ether_addr(buf))) { 1088 netif_warn(tp, probe, tp->netdev, 1089 "Invalid MAC when reading pass-thru MAC addr: " 1090 "%d, %pM\n", ret, buf); 1091 ret = -EINVAL; 1092 goto amacout; 1093 } 1094 memcpy(sa->sa_data, buf, 6); 1095 ether_addr_copy(tp->netdev->dev_addr, sa->sa_data); 1096 netif_info(tp, probe, tp->netdev, 1097 "Using pass-thru MAC addr %pM\n", sa->sa_data); 1098 1099 amacout: 1100 kfree(obj); 1101 return ret; 1102 } 1103 1104 static int set_ethernet_addr(struct r8152 *tp) 1105 { 1106 struct net_device *dev = tp->netdev; 1107 struct sockaddr sa; 1108 int ret; 1109 1110 if (tp->version == RTL_VER_01) 1111 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); 1112 else { 1113 /* if this is not an RTL8153-AD, no eFuse mac pass thru set, 1114 * or system doesn't provide valid _SB.AMAC this will be 1115 * be expected to non-zero 1116 */ 1117 ret = vendor_mac_passthru_addr_read(tp, &sa); 1118 if (ret < 0) 1119 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); 1120 } 1121 1122 if (ret < 0) { 1123 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1124 } else if (!is_valid_ether_addr(sa.sa_data)) { 1125 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1126 sa.sa_data); 1127 eth_hw_addr_random(dev); 1128 ether_addr_copy(sa.sa_data, dev->dev_addr); 1129 ret = rtl8152_set_mac_address(dev, &sa); 1130 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1131 sa.sa_data); 1132 } else { 1133 if (tp->version == RTL_VER_01) 1134 ether_addr_copy(dev->dev_addr, sa.sa_data); 1135 else 1136 ret = rtl8152_set_mac_address(dev, &sa); 1137 } 1138 1139 return ret; 1140 } 1141 1142 static void read_bulk_callback(struct urb *urb) 1143 { 1144 struct net_device *netdev; 1145 int status = urb->status; 1146 struct rx_agg *agg; 1147 struct r8152 *tp; 1148 1149 agg = urb->context; 1150 if (!agg) 1151 return; 1152 1153 tp = agg->context; 1154 if (!tp) 1155 return; 1156 1157 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1158 return; 1159 1160 if (!test_bit(WORK_ENABLE, &tp->flags)) 1161 return; 1162 1163 netdev = tp->netdev; 1164 1165 /* When link down, the driver would cancel all bulks. */ 1166 /* This avoid the re-submitting bulk */ 1167 if (!netif_carrier_ok(netdev)) 1168 return; 1169 1170 usb_mark_last_busy(tp->udev); 1171 1172 switch (status) { 1173 case 0: 1174 if (urb->actual_length < ETH_ZLEN) 1175 break; 1176 1177 spin_lock(&tp->rx_lock); 1178 list_add_tail(&agg->list, &tp->rx_done); 1179 spin_unlock(&tp->rx_lock); 1180 napi_schedule(&tp->napi); 1181 return; 1182 case -ESHUTDOWN: 1183 set_bit(RTL8152_UNPLUG, &tp->flags); 1184 netif_device_detach(tp->netdev); 1185 return; 1186 case -ENOENT: 1187 return; /* the urb is in unlink state */ 1188 case -ETIME: 1189 if (net_ratelimit()) 1190 netdev_warn(netdev, "maybe reset is needed?\n"); 1191 break; 1192 default: 1193 if (net_ratelimit()) 1194 netdev_warn(netdev, "Rx status %d\n", status); 1195 break; 1196 } 1197 1198 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1199 } 1200 1201 static void write_bulk_callback(struct urb *urb) 1202 { 1203 struct net_device_stats *stats; 1204 struct net_device *netdev; 1205 struct tx_agg *agg; 1206 struct r8152 *tp; 1207 int status = urb->status; 1208 1209 agg = urb->context; 1210 if (!agg) 1211 return; 1212 1213 tp = agg->context; 1214 if (!tp) 1215 return; 1216 1217 netdev = tp->netdev; 1218 stats = &netdev->stats; 1219 if (status) { 1220 if (net_ratelimit()) 1221 netdev_warn(netdev, "Tx status %d\n", status); 1222 stats->tx_errors += agg->skb_num; 1223 } else { 1224 stats->tx_packets += agg->skb_num; 1225 stats->tx_bytes += agg->skb_len; 1226 } 1227 1228 spin_lock(&tp->tx_lock); 1229 list_add_tail(&agg->list, &tp->tx_free); 1230 spin_unlock(&tp->tx_lock); 1231 1232 usb_autopm_put_interface_async(tp->intf); 1233 1234 if (!netif_carrier_ok(netdev)) 1235 return; 1236 1237 if (!test_bit(WORK_ENABLE, &tp->flags)) 1238 return; 1239 1240 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1241 return; 1242 1243 if (!skb_queue_empty(&tp->tx_queue)) 1244 napi_schedule(&tp->napi); 1245 } 1246 1247 static void intr_callback(struct urb *urb) 1248 { 1249 struct r8152 *tp; 1250 __le16 *d; 1251 int status = urb->status; 1252 int res; 1253 1254 tp = urb->context; 1255 if (!tp) 1256 return; 1257 1258 if (!test_bit(WORK_ENABLE, &tp->flags)) 1259 return; 1260 1261 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1262 return; 1263 1264 switch (status) { 1265 case 0: /* success */ 1266 break; 1267 case -ECONNRESET: /* unlink */ 1268 case -ESHUTDOWN: 1269 netif_device_detach(tp->netdev); 1270 case -ENOENT: 1271 case -EPROTO: 1272 netif_info(tp, intr, tp->netdev, 1273 "Stop submitting intr, status %d\n", status); 1274 return; 1275 case -EOVERFLOW: 1276 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); 1277 goto resubmit; 1278 /* -EPIPE: should clear the halt */ 1279 default: 1280 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1281 goto resubmit; 1282 } 1283 1284 d = urb->transfer_buffer; 1285 if (INTR_LINK & __le16_to_cpu(d[0])) { 1286 if (!netif_carrier_ok(tp->netdev)) { 1287 set_bit(RTL8152_LINK_CHG, &tp->flags); 1288 schedule_delayed_work(&tp->schedule, 0); 1289 } 1290 } else { 1291 if (netif_carrier_ok(tp->netdev)) { 1292 set_bit(RTL8152_LINK_CHG, &tp->flags); 1293 schedule_delayed_work(&tp->schedule, 0); 1294 } 1295 } 1296 1297 resubmit: 1298 res = usb_submit_urb(urb, GFP_ATOMIC); 1299 if (res == -ENODEV) { 1300 set_bit(RTL8152_UNPLUG, &tp->flags); 1301 netif_device_detach(tp->netdev); 1302 } else if (res) { 1303 netif_err(tp, intr, tp->netdev, 1304 "can't resubmit intr, status %d\n", res); 1305 } 1306 } 1307 1308 static inline void *rx_agg_align(void *data) 1309 { 1310 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 1311 } 1312 1313 static inline void *tx_agg_align(void *data) 1314 { 1315 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 1316 } 1317 1318 static void free_all_mem(struct r8152 *tp) 1319 { 1320 int i; 1321 1322 for (i = 0; i < RTL8152_MAX_RX; i++) { 1323 usb_free_urb(tp->rx_info[i].urb); 1324 tp->rx_info[i].urb = NULL; 1325 1326 kfree(tp->rx_info[i].buffer); 1327 tp->rx_info[i].buffer = NULL; 1328 tp->rx_info[i].head = NULL; 1329 } 1330 1331 for (i = 0; i < RTL8152_MAX_TX; i++) { 1332 usb_free_urb(tp->tx_info[i].urb); 1333 tp->tx_info[i].urb = NULL; 1334 1335 kfree(tp->tx_info[i].buffer); 1336 tp->tx_info[i].buffer = NULL; 1337 tp->tx_info[i].head = NULL; 1338 } 1339 1340 usb_free_urb(tp->intr_urb); 1341 tp->intr_urb = NULL; 1342 1343 kfree(tp->intr_buff); 1344 tp->intr_buff = NULL; 1345 } 1346 1347 static int alloc_all_mem(struct r8152 *tp) 1348 { 1349 struct net_device *netdev = tp->netdev; 1350 struct usb_interface *intf = tp->intf; 1351 struct usb_host_interface *alt = intf->cur_altsetting; 1352 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 1353 struct urb *urb; 1354 int node, i; 1355 u8 *buf; 1356 1357 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 1358 1359 spin_lock_init(&tp->rx_lock); 1360 spin_lock_init(&tp->tx_lock); 1361 INIT_LIST_HEAD(&tp->tx_free); 1362 skb_queue_head_init(&tp->tx_queue); 1363 skb_queue_head_init(&tp->rx_queue); 1364 1365 for (i = 0; i < RTL8152_MAX_RX; i++) { 1366 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1367 if (!buf) 1368 goto err1; 1369 1370 if (buf != rx_agg_align(buf)) { 1371 kfree(buf); 1372 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, 1373 node); 1374 if (!buf) 1375 goto err1; 1376 } 1377 1378 urb = usb_alloc_urb(0, GFP_KERNEL); 1379 if (!urb) { 1380 kfree(buf); 1381 goto err1; 1382 } 1383 1384 INIT_LIST_HEAD(&tp->rx_info[i].list); 1385 tp->rx_info[i].context = tp; 1386 tp->rx_info[i].urb = urb; 1387 tp->rx_info[i].buffer = buf; 1388 tp->rx_info[i].head = rx_agg_align(buf); 1389 } 1390 1391 for (i = 0; i < RTL8152_MAX_TX; i++) { 1392 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 1393 if (!buf) 1394 goto err1; 1395 1396 if (buf != tx_agg_align(buf)) { 1397 kfree(buf); 1398 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 1399 node); 1400 if (!buf) 1401 goto err1; 1402 } 1403 1404 urb = usb_alloc_urb(0, GFP_KERNEL); 1405 if (!urb) { 1406 kfree(buf); 1407 goto err1; 1408 } 1409 1410 INIT_LIST_HEAD(&tp->tx_info[i].list); 1411 tp->tx_info[i].context = tp; 1412 tp->tx_info[i].urb = urb; 1413 tp->tx_info[i].buffer = buf; 1414 tp->tx_info[i].head = tx_agg_align(buf); 1415 1416 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 1417 } 1418 1419 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 1420 if (!tp->intr_urb) 1421 goto err1; 1422 1423 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 1424 if (!tp->intr_buff) 1425 goto err1; 1426 1427 tp->intr_interval = (int)ep_intr->desc.bInterval; 1428 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), 1429 tp->intr_buff, INTBUFSIZE, intr_callback, 1430 tp, tp->intr_interval); 1431 1432 return 0; 1433 1434 err1: 1435 free_all_mem(tp); 1436 return -ENOMEM; 1437 } 1438 1439 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 1440 { 1441 struct tx_agg *agg = NULL; 1442 unsigned long flags; 1443 1444 if (list_empty(&tp->tx_free)) 1445 return NULL; 1446 1447 spin_lock_irqsave(&tp->tx_lock, flags); 1448 if (!list_empty(&tp->tx_free)) { 1449 struct list_head *cursor; 1450 1451 cursor = tp->tx_free.next; 1452 list_del_init(cursor); 1453 agg = list_entry(cursor, struct tx_agg, list); 1454 } 1455 spin_unlock_irqrestore(&tp->tx_lock, flags); 1456 1457 return agg; 1458 } 1459 1460 /* r8152_csum_workaround() 1461 * The hw limites the value the transport offset. When the offset is out of the 1462 * range, calculate the checksum by sw. 1463 */ 1464 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 1465 struct sk_buff_head *list) 1466 { 1467 if (skb_shinfo(skb)->gso_size) { 1468 netdev_features_t features = tp->netdev->features; 1469 struct sk_buff_head seg_list; 1470 struct sk_buff *segs, *nskb; 1471 1472 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 1473 segs = skb_gso_segment(skb, features); 1474 if (IS_ERR(segs) || !segs) 1475 goto drop; 1476 1477 __skb_queue_head_init(&seg_list); 1478 1479 do { 1480 nskb = segs; 1481 segs = segs->next; 1482 nskb->next = NULL; 1483 __skb_queue_tail(&seg_list, nskb); 1484 } while (segs); 1485 1486 skb_queue_splice(&seg_list, list); 1487 dev_kfree_skb(skb); 1488 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1489 if (skb_checksum_help(skb) < 0) 1490 goto drop; 1491 1492 __skb_queue_head(list, skb); 1493 } else { 1494 struct net_device_stats *stats; 1495 1496 drop: 1497 stats = &tp->netdev->stats; 1498 stats->tx_dropped++; 1499 dev_kfree_skb(skb); 1500 } 1501 } 1502 1503 /* msdn_giant_send_check() 1504 * According to the document of microsoft, the TCP Pseudo Header excludes the 1505 * packet length for IPv6 TCP large packets. 1506 */ 1507 static int msdn_giant_send_check(struct sk_buff *skb) 1508 { 1509 const struct ipv6hdr *ipv6h; 1510 struct tcphdr *th; 1511 int ret; 1512 1513 ret = skb_cow_head(skb, 0); 1514 if (ret) 1515 return ret; 1516 1517 ipv6h = ipv6_hdr(skb); 1518 th = tcp_hdr(skb); 1519 1520 th->check = 0; 1521 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 1522 1523 return ret; 1524 } 1525 1526 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 1527 { 1528 if (skb_vlan_tag_present(skb)) { 1529 u32 opts2; 1530 1531 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); 1532 desc->opts2 |= cpu_to_le32(opts2); 1533 } 1534 } 1535 1536 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 1537 { 1538 u32 opts2 = le32_to_cpu(desc->opts2); 1539 1540 if (opts2 & RX_VLAN_TAG) 1541 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1542 swab16(opts2 & 0xffff)); 1543 } 1544 1545 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 1546 struct sk_buff *skb, u32 len, u32 transport_offset) 1547 { 1548 u32 mss = skb_shinfo(skb)->gso_size; 1549 u32 opts1, opts2 = 0; 1550 int ret = TX_CSUM_SUCCESS; 1551 1552 WARN_ON_ONCE(len > TX_LEN_MAX); 1553 1554 opts1 = len | TX_FS | TX_LS; 1555 1556 if (mss) { 1557 if (transport_offset > GTTCPHO_MAX) { 1558 netif_warn(tp, tx_err, tp->netdev, 1559 "Invalid transport offset 0x%x for TSO\n", 1560 transport_offset); 1561 ret = TX_CSUM_TSO; 1562 goto unavailable; 1563 } 1564 1565 switch (vlan_get_protocol(skb)) { 1566 case htons(ETH_P_IP): 1567 opts1 |= GTSENDV4; 1568 break; 1569 1570 case htons(ETH_P_IPV6): 1571 if (msdn_giant_send_check(skb)) { 1572 ret = TX_CSUM_TSO; 1573 goto unavailable; 1574 } 1575 opts1 |= GTSENDV6; 1576 break; 1577 1578 default: 1579 WARN_ON_ONCE(1); 1580 break; 1581 } 1582 1583 opts1 |= transport_offset << GTTCPHO_SHIFT; 1584 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 1585 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 1586 u8 ip_protocol; 1587 1588 if (transport_offset > TCPHO_MAX) { 1589 netif_warn(tp, tx_err, tp->netdev, 1590 "Invalid transport offset 0x%x\n", 1591 transport_offset); 1592 ret = TX_CSUM_NONE; 1593 goto unavailable; 1594 } 1595 1596 switch (vlan_get_protocol(skb)) { 1597 case htons(ETH_P_IP): 1598 opts2 |= IPV4_CS; 1599 ip_protocol = ip_hdr(skb)->protocol; 1600 break; 1601 1602 case htons(ETH_P_IPV6): 1603 opts2 |= IPV6_CS; 1604 ip_protocol = ipv6_hdr(skb)->nexthdr; 1605 break; 1606 1607 default: 1608 ip_protocol = IPPROTO_RAW; 1609 break; 1610 } 1611 1612 if (ip_protocol == IPPROTO_TCP) 1613 opts2 |= TCP_CS; 1614 else if (ip_protocol == IPPROTO_UDP) 1615 opts2 |= UDP_CS; 1616 else 1617 WARN_ON_ONCE(1); 1618 1619 opts2 |= transport_offset << TCPHO_SHIFT; 1620 } 1621 1622 desc->opts2 = cpu_to_le32(opts2); 1623 desc->opts1 = cpu_to_le32(opts1); 1624 1625 unavailable: 1626 return ret; 1627 } 1628 1629 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 1630 { 1631 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1632 int remain, ret; 1633 u8 *tx_data; 1634 1635 __skb_queue_head_init(&skb_head); 1636 spin_lock(&tx_queue->lock); 1637 skb_queue_splice_init(tx_queue, &skb_head); 1638 spin_unlock(&tx_queue->lock); 1639 1640 tx_data = agg->head; 1641 agg->skb_num = 0; 1642 agg->skb_len = 0; 1643 remain = agg_buf_sz; 1644 1645 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 1646 struct tx_desc *tx_desc; 1647 struct sk_buff *skb; 1648 unsigned int len; 1649 u32 offset; 1650 1651 skb = __skb_dequeue(&skb_head); 1652 if (!skb) 1653 break; 1654 1655 len = skb->len + sizeof(*tx_desc); 1656 1657 if (len > remain) { 1658 __skb_queue_head(&skb_head, skb); 1659 break; 1660 } 1661 1662 tx_data = tx_agg_align(tx_data); 1663 tx_desc = (struct tx_desc *)tx_data; 1664 1665 offset = (u32)skb_transport_offset(skb); 1666 1667 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { 1668 r8152_csum_workaround(tp, skb, &skb_head); 1669 continue; 1670 } 1671 1672 rtl_tx_vlan_tag(tx_desc, skb); 1673 1674 tx_data += sizeof(*tx_desc); 1675 1676 len = skb->len; 1677 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 1678 struct net_device_stats *stats = &tp->netdev->stats; 1679 1680 stats->tx_dropped++; 1681 dev_kfree_skb_any(skb); 1682 tx_data -= sizeof(*tx_desc); 1683 continue; 1684 } 1685 1686 tx_data += len; 1687 agg->skb_len += len; 1688 agg->skb_num++; 1689 1690 dev_kfree_skb_any(skb); 1691 1692 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 1693 } 1694 1695 if (!skb_queue_empty(&skb_head)) { 1696 spin_lock(&tx_queue->lock); 1697 skb_queue_splice(&skb_head, tx_queue); 1698 spin_unlock(&tx_queue->lock); 1699 } 1700 1701 netif_tx_lock(tp->netdev); 1702 1703 if (netif_queue_stopped(tp->netdev) && 1704 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 1705 netif_wake_queue(tp->netdev); 1706 1707 netif_tx_unlock(tp->netdev); 1708 1709 ret = usb_autopm_get_interface_async(tp->intf); 1710 if (ret < 0) 1711 goto out_tx_fill; 1712 1713 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), 1714 agg->head, (int)(tx_data - (u8 *)agg->head), 1715 (usb_complete_t)write_bulk_callback, agg); 1716 1717 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 1718 if (ret < 0) 1719 usb_autopm_put_interface_async(tp->intf); 1720 1721 out_tx_fill: 1722 return ret; 1723 } 1724 1725 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 1726 { 1727 u8 checksum = CHECKSUM_NONE; 1728 u32 opts2, opts3; 1729 1730 if (tp->version == RTL_VER_01) 1731 goto return_result; 1732 1733 opts2 = le32_to_cpu(rx_desc->opts2); 1734 opts3 = le32_to_cpu(rx_desc->opts3); 1735 1736 if (opts2 & RD_IPV4_CS) { 1737 if (opts3 & IPF) 1738 checksum = CHECKSUM_NONE; 1739 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) 1740 checksum = CHECKSUM_NONE; 1741 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) 1742 checksum = CHECKSUM_NONE; 1743 else 1744 checksum = CHECKSUM_UNNECESSARY; 1745 } else if (RD_IPV6_CS) { 1746 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 1747 checksum = CHECKSUM_UNNECESSARY; 1748 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 1749 checksum = CHECKSUM_UNNECESSARY; 1750 } 1751 1752 return_result: 1753 return checksum; 1754 } 1755 1756 static int rx_bottom(struct r8152 *tp, int budget) 1757 { 1758 unsigned long flags; 1759 struct list_head *cursor, *next, rx_queue; 1760 int ret = 0, work_done = 0; 1761 1762 if (!skb_queue_empty(&tp->rx_queue)) { 1763 while (work_done < budget) { 1764 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); 1765 struct net_device *netdev = tp->netdev; 1766 struct net_device_stats *stats = &netdev->stats; 1767 unsigned int pkt_len; 1768 1769 if (!skb) 1770 break; 1771 1772 pkt_len = skb->len; 1773 napi_gro_receive(&tp->napi, skb); 1774 work_done++; 1775 stats->rx_packets++; 1776 stats->rx_bytes += pkt_len; 1777 } 1778 } 1779 1780 if (list_empty(&tp->rx_done)) 1781 goto out1; 1782 1783 INIT_LIST_HEAD(&rx_queue); 1784 spin_lock_irqsave(&tp->rx_lock, flags); 1785 list_splice_init(&tp->rx_done, &rx_queue); 1786 spin_unlock_irqrestore(&tp->rx_lock, flags); 1787 1788 list_for_each_safe(cursor, next, &rx_queue) { 1789 struct rx_desc *rx_desc; 1790 struct rx_agg *agg; 1791 int len_used = 0; 1792 struct urb *urb; 1793 u8 *rx_data; 1794 1795 list_del_init(cursor); 1796 1797 agg = list_entry(cursor, struct rx_agg, list); 1798 urb = agg->urb; 1799 if (urb->actual_length < ETH_ZLEN) 1800 goto submit; 1801 1802 rx_desc = agg->head; 1803 rx_data = agg->head; 1804 len_used += sizeof(struct rx_desc); 1805 1806 while (urb->actual_length > len_used) { 1807 struct net_device *netdev = tp->netdev; 1808 struct net_device_stats *stats = &netdev->stats; 1809 unsigned int pkt_len; 1810 struct sk_buff *skb; 1811 1812 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1813 if (pkt_len < ETH_ZLEN) 1814 break; 1815 1816 len_used += pkt_len; 1817 if (urb->actual_length < len_used) 1818 break; 1819 1820 pkt_len -= CRC_SIZE; 1821 rx_data += sizeof(struct rx_desc); 1822 1823 skb = netdev_alloc_skb_ip_align(netdev, pkt_len); 1824 if (!skb) { 1825 stats->rx_dropped++; 1826 goto find_next_rx; 1827 } 1828 1829 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 1830 memcpy(skb->data, rx_data, pkt_len); 1831 skb_put(skb, pkt_len); 1832 skb->protocol = eth_type_trans(skb, netdev); 1833 rtl_rx_vlan_tag(rx_desc, skb); 1834 if (work_done < budget) { 1835 napi_gro_receive(&tp->napi, skb); 1836 work_done++; 1837 stats->rx_packets++; 1838 stats->rx_bytes += pkt_len; 1839 } else { 1840 __skb_queue_tail(&tp->rx_queue, skb); 1841 } 1842 1843 find_next_rx: 1844 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); 1845 rx_desc = (struct rx_desc *)rx_data; 1846 len_used = (int)(rx_data - (u8 *)agg->head); 1847 len_used += sizeof(struct rx_desc); 1848 } 1849 1850 submit: 1851 if (!ret) { 1852 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 1853 } else { 1854 urb->actual_length = 0; 1855 list_add_tail(&agg->list, next); 1856 } 1857 } 1858 1859 if (!list_empty(&rx_queue)) { 1860 spin_lock_irqsave(&tp->rx_lock, flags); 1861 list_splice_tail(&rx_queue, &tp->rx_done); 1862 spin_unlock_irqrestore(&tp->rx_lock, flags); 1863 } 1864 1865 out1: 1866 return work_done; 1867 } 1868 1869 static void tx_bottom(struct r8152 *tp) 1870 { 1871 int res; 1872 1873 do { 1874 struct tx_agg *agg; 1875 1876 if (skb_queue_empty(&tp->tx_queue)) 1877 break; 1878 1879 agg = r8152_get_tx_agg(tp); 1880 if (!agg) 1881 break; 1882 1883 res = r8152_tx_agg_fill(tp, agg); 1884 if (res) { 1885 struct net_device *netdev = tp->netdev; 1886 1887 if (res == -ENODEV) { 1888 set_bit(RTL8152_UNPLUG, &tp->flags); 1889 netif_device_detach(netdev); 1890 } else { 1891 struct net_device_stats *stats = &netdev->stats; 1892 unsigned long flags; 1893 1894 netif_warn(tp, tx_err, netdev, 1895 "failed tx_urb %d\n", res); 1896 stats->tx_dropped += agg->skb_num; 1897 1898 spin_lock_irqsave(&tp->tx_lock, flags); 1899 list_add_tail(&agg->list, &tp->tx_free); 1900 spin_unlock_irqrestore(&tp->tx_lock, flags); 1901 } 1902 } 1903 } while (res == 0); 1904 } 1905 1906 static void bottom_half(struct r8152 *tp) 1907 { 1908 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 1909 return; 1910 1911 if (!test_bit(WORK_ENABLE, &tp->flags)) 1912 return; 1913 1914 /* When link down, the driver would cancel all bulks. */ 1915 /* This avoid the re-submitting bulk */ 1916 if (!netif_carrier_ok(tp->netdev)) 1917 return; 1918 1919 clear_bit(SCHEDULE_NAPI, &tp->flags); 1920 1921 tx_bottom(tp); 1922 } 1923 1924 static int r8152_poll(struct napi_struct *napi, int budget) 1925 { 1926 struct r8152 *tp = container_of(napi, struct r8152, napi); 1927 int work_done; 1928 1929 work_done = rx_bottom(tp, budget); 1930 bottom_half(tp); 1931 1932 if (work_done < budget) { 1933 napi_complete(napi); 1934 if (!list_empty(&tp->rx_done)) 1935 napi_schedule(napi); 1936 } 1937 1938 return work_done; 1939 } 1940 1941 static 1942 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 1943 { 1944 int ret; 1945 1946 /* The rx would be stopped, so skip submitting */ 1947 if (test_bit(RTL8152_UNPLUG, &tp->flags) || 1948 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) 1949 return 0; 1950 1951 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), 1952 agg->head, agg_buf_sz, 1953 (usb_complete_t)read_bulk_callback, agg); 1954 1955 ret = usb_submit_urb(agg->urb, mem_flags); 1956 if (ret == -ENODEV) { 1957 set_bit(RTL8152_UNPLUG, &tp->flags); 1958 netif_device_detach(tp->netdev); 1959 } else if (ret) { 1960 struct urb *urb = agg->urb; 1961 unsigned long flags; 1962 1963 urb->actual_length = 0; 1964 spin_lock_irqsave(&tp->rx_lock, flags); 1965 list_add_tail(&agg->list, &tp->rx_done); 1966 spin_unlock_irqrestore(&tp->rx_lock, flags); 1967 1968 netif_err(tp, rx_err, tp->netdev, 1969 "Couldn't submit rx[%p], ret = %d\n", agg, ret); 1970 1971 napi_schedule(&tp->napi); 1972 } 1973 1974 return ret; 1975 } 1976 1977 static void rtl_drop_queued_tx(struct r8152 *tp) 1978 { 1979 struct net_device_stats *stats = &tp->netdev->stats; 1980 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 1981 struct sk_buff *skb; 1982 1983 if (skb_queue_empty(tx_queue)) 1984 return; 1985 1986 __skb_queue_head_init(&skb_head); 1987 spin_lock_bh(&tx_queue->lock); 1988 skb_queue_splice_init(tx_queue, &skb_head); 1989 spin_unlock_bh(&tx_queue->lock); 1990 1991 while ((skb = __skb_dequeue(&skb_head))) { 1992 dev_kfree_skb(skb); 1993 stats->tx_dropped++; 1994 } 1995 } 1996 1997 static void rtl8152_tx_timeout(struct net_device *netdev) 1998 { 1999 struct r8152 *tp = netdev_priv(netdev); 2000 2001 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 2002 2003 usb_queue_reset_device(tp->intf); 2004 } 2005 2006 static void rtl8152_set_rx_mode(struct net_device *netdev) 2007 { 2008 struct r8152 *tp = netdev_priv(netdev); 2009 2010 if (netif_carrier_ok(netdev)) { 2011 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2012 schedule_delayed_work(&tp->schedule, 0); 2013 } 2014 } 2015 2016 static void _rtl8152_set_rx_mode(struct net_device *netdev) 2017 { 2018 struct r8152 *tp = netdev_priv(netdev); 2019 u32 mc_filter[2]; /* Multicast hash filter */ 2020 __le32 tmp[2]; 2021 u32 ocp_data; 2022 2023 netif_stop_queue(netdev); 2024 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2025 ocp_data &= ~RCR_ACPT_ALL; 2026 ocp_data |= RCR_AB | RCR_APM; 2027 2028 if (netdev->flags & IFF_PROMISC) { 2029 /* Unconditionally log net taps. */ 2030 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 2031 ocp_data |= RCR_AM | RCR_AAP; 2032 mc_filter[1] = 0xffffffff; 2033 mc_filter[0] = 0xffffffff; 2034 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || 2035 (netdev->flags & IFF_ALLMULTI)) { 2036 /* Too many to filter perfectly -- accept all multicasts. */ 2037 ocp_data |= RCR_AM; 2038 mc_filter[1] = 0xffffffff; 2039 mc_filter[0] = 0xffffffff; 2040 } else { 2041 struct netdev_hw_addr *ha; 2042 2043 mc_filter[1] = 0; 2044 mc_filter[0] = 0; 2045 netdev_for_each_mc_addr(ha, netdev) { 2046 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2047 2048 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2049 ocp_data |= RCR_AM; 2050 } 2051 } 2052 2053 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 2054 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 2055 2056 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 2057 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2058 netif_wake_queue(netdev); 2059 } 2060 2061 static netdev_features_t 2062 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 2063 netdev_features_t features) 2064 { 2065 u32 mss = skb_shinfo(skb)->gso_size; 2066 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 2067 int offset = skb_transport_offset(skb); 2068 2069 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) 2070 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2071 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 2072 features &= ~NETIF_F_GSO_MASK; 2073 2074 return features; 2075 } 2076 2077 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 2078 struct net_device *netdev) 2079 { 2080 struct r8152 *tp = netdev_priv(netdev); 2081 2082 skb_tx_timestamp(skb); 2083 2084 skb_queue_tail(&tp->tx_queue, skb); 2085 2086 if (!list_empty(&tp->tx_free)) { 2087 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2088 set_bit(SCHEDULE_NAPI, &tp->flags); 2089 schedule_delayed_work(&tp->schedule, 0); 2090 } else { 2091 usb_mark_last_busy(tp->udev); 2092 napi_schedule(&tp->napi); 2093 } 2094 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 2095 netif_stop_queue(netdev); 2096 } 2097 2098 return NETDEV_TX_OK; 2099 } 2100 2101 static void r8152b_reset_packet_filter(struct r8152 *tp) 2102 { 2103 u32 ocp_data; 2104 2105 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 2106 ocp_data &= ~FMC_FCR_MCU_EN; 2107 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2108 ocp_data |= FMC_FCR_MCU_EN; 2109 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2110 } 2111 2112 static void rtl8152_nic_reset(struct r8152 *tp) 2113 { 2114 int i; 2115 2116 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 2117 2118 for (i = 0; i < 1000; i++) { 2119 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 2120 break; 2121 usleep_range(100, 400); 2122 } 2123 } 2124 2125 static void set_tx_qlen(struct r8152 *tp) 2126 { 2127 struct net_device *netdev = tp->netdev; 2128 2129 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + 2130 sizeof(struct tx_desc)); 2131 } 2132 2133 static inline u8 rtl8152_get_speed(struct r8152 *tp) 2134 { 2135 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 2136 } 2137 2138 static void rtl_set_eee_plus(struct r8152 *tp) 2139 { 2140 u32 ocp_data; 2141 u8 speed; 2142 2143 speed = rtl8152_get_speed(tp); 2144 if (speed & _10bps) { 2145 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2146 ocp_data |= EEEP_CR_EEEP_TX; 2147 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2148 } else { 2149 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 2150 ocp_data &= ~EEEP_CR_EEEP_TX; 2151 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 2152 } 2153 } 2154 2155 static void rxdy_gated_en(struct r8152 *tp, bool enable) 2156 { 2157 u32 ocp_data; 2158 2159 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 2160 if (enable) 2161 ocp_data |= RXDY_GATED_EN; 2162 else 2163 ocp_data &= ~RXDY_GATED_EN; 2164 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 2165 } 2166 2167 static int rtl_start_rx(struct r8152 *tp) 2168 { 2169 int i, ret = 0; 2170 2171 INIT_LIST_HEAD(&tp->rx_done); 2172 for (i = 0; i < RTL8152_MAX_RX; i++) { 2173 INIT_LIST_HEAD(&tp->rx_info[i].list); 2174 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); 2175 if (ret) 2176 break; 2177 } 2178 2179 if (ret && ++i < RTL8152_MAX_RX) { 2180 struct list_head rx_queue; 2181 unsigned long flags; 2182 2183 INIT_LIST_HEAD(&rx_queue); 2184 2185 do { 2186 struct rx_agg *agg = &tp->rx_info[i++]; 2187 struct urb *urb = agg->urb; 2188 2189 urb->actual_length = 0; 2190 list_add_tail(&agg->list, &rx_queue); 2191 } while (i < RTL8152_MAX_RX); 2192 2193 spin_lock_irqsave(&tp->rx_lock, flags); 2194 list_splice_tail(&rx_queue, &tp->rx_done); 2195 spin_unlock_irqrestore(&tp->rx_lock, flags); 2196 } 2197 2198 return ret; 2199 } 2200 2201 static int rtl_stop_rx(struct r8152 *tp) 2202 { 2203 int i; 2204 2205 for (i = 0; i < RTL8152_MAX_RX; i++) 2206 usb_kill_urb(tp->rx_info[i].urb); 2207 2208 while (!skb_queue_empty(&tp->rx_queue)) 2209 dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); 2210 2211 return 0; 2212 } 2213 2214 static int rtl_enable(struct r8152 *tp) 2215 { 2216 u32 ocp_data; 2217 2218 r8152b_reset_packet_filter(tp); 2219 2220 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2221 ocp_data |= CR_RE | CR_TE; 2222 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2223 2224 rxdy_gated_en(tp, false); 2225 2226 return 0; 2227 } 2228 2229 static int rtl8152_enable(struct r8152 *tp) 2230 { 2231 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2232 return -ENODEV; 2233 2234 set_tx_qlen(tp); 2235 rtl_set_eee_plus(tp); 2236 2237 return rtl_enable(tp); 2238 } 2239 2240 static void r8153_set_rx_early_timeout(struct r8152 *tp) 2241 { 2242 u32 ocp_data = tp->coalesce / 8; 2243 2244 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data); 2245 } 2246 2247 static void r8153_set_rx_early_size(struct r8152 *tp) 2248 { 2249 u32 mtu = tp->netdev->mtu; 2250 u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 8; 2251 2252 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data); 2253 } 2254 2255 static int rtl8153_enable(struct r8152 *tp) 2256 { 2257 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 2258 return -ENODEV; 2259 2260 usb_disable_lpm(tp->udev); 2261 set_tx_qlen(tp); 2262 rtl_set_eee_plus(tp); 2263 r8153_set_rx_early_timeout(tp); 2264 r8153_set_rx_early_size(tp); 2265 2266 return rtl_enable(tp); 2267 } 2268 2269 static void rtl_disable(struct r8152 *tp) 2270 { 2271 u32 ocp_data; 2272 int i; 2273 2274 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 2275 rtl_drop_queued_tx(tp); 2276 return; 2277 } 2278 2279 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2280 ocp_data &= ~RCR_ACPT_ALL; 2281 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2282 2283 rtl_drop_queued_tx(tp); 2284 2285 for (i = 0; i < RTL8152_MAX_TX; i++) 2286 usb_kill_urb(tp->tx_info[i].urb); 2287 2288 rxdy_gated_en(tp, true); 2289 2290 for (i = 0; i < 1000; i++) { 2291 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2292 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 2293 break; 2294 usleep_range(1000, 2000); 2295 } 2296 2297 for (i = 0; i < 1000; i++) { 2298 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 2299 break; 2300 usleep_range(1000, 2000); 2301 } 2302 2303 rtl_stop_rx(tp); 2304 2305 rtl8152_nic_reset(tp); 2306 } 2307 2308 static void r8152_power_cut_en(struct r8152 *tp, bool enable) 2309 { 2310 u32 ocp_data; 2311 2312 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 2313 if (enable) 2314 ocp_data |= POWER_CUT; 2315 else 2316 ocp_data &= ~POWER_CUT; 2317 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 2318 2319 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 2320 ocp_data &= ~RESUME_INDICATE; 2321 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 2322 } 2323 2324 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 2325 { 2326 u32 ocp_data; 2327 2328 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 2329 if (enable) 2330 ocp_data |= CPCR_RX_VLAN; 2331 else 2332 ocp_data &= ~CPCR_RX_VLAN; 2333 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2334 } 2335 2336 static int rtl8152_set_features(struct net_device *dev, 2337 netdev_features_t features) 2338 { 2339 netdev_features_t changed = features ^ dev->features; 2340 struct r8152 *tp = netdev_priv(dev); 2341 int ret; 2342 2343 ret = usb_autopm_get_interface(tp->intf); 2344 if (ret < 0) 2345 goto out; 2346 2347 mutex_lock(&tp->control); 2348 2349 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 2350 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2351 rtl_rx_vlan_en(tp, true); 2352 else 2353 rtl_rx_vlan_en(tp, false); 2354 } 2355 2356 mutex_unlock(&tp->control); 2357 2358 usb_autopm_put_interface(tp->intf); 2359 2360 out: 2361 return ret; 2362 } 2363 2364 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 2365 2366 static u32 __rtl_get_wol(struct r8152 *tp) 2367 { 2368 u32 ocp_data; 2369 u32 wolopts = 0; 2370 2371 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2372 if (ocp_data & LINK_ON_WAKE_EN) 2373 wolopts |= WAKE_PHY; 2374 2375 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2376 if (ocp_data & UWF_EN) 2377 wolopts |= WAKE_UCAST; 2378 if (ocp_data & BWF_EN) 2379 wolopts |= WAKE_BCAST; 2380 if (ocp_data & MWF_EN) 2381 wolopts |= WAKE_MCAST; 2382 2383 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2384 if (ocp_data & MAGIC_EN) 2385 wolopts |= WAKE_MAGIC; 2386 2387 return wolopts; 2388 } 2389 2390 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 2391 { 2392 u32 ocp_data; 2393 2394 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2395 2396 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2397 ocp_data &= ~LINK_ON_WAKE_EN; 2398 if (wolopts & WAKE_PHY) 2399 ocp_data |= LINK_ON_WAKE_EN; 2400 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2401 2402 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 2403 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); 2404 if (wolopts & WAKE_UCAST) 2405 ocp_data |= UWF_EN; 2406 if (wolopts & WAKE_BCAST) 2407 ocp_data |= BWF_EN; 2408 if (wolopts & WAKE_MCAST) 2409 ocp_data |= MWF_EN; 2410 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 2411 2412 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2413 2414 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 2415 ocp_data &= ~MAGIC_EN; 2416 if (wolopts & WAKE_MAGIC) 2417 ocp_data |= MAGIC_EN; 2418 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 2419 2420 if (wolopts & WAKE_ANY) 2421 device_set_wakeup_enable(&tp->udev->dev, true); 2422 else 2423 device_set_wakeup_enable(&tp->udev->dev, false); 2424 } 2425 2426 static void r8153_u1u2en(struct r8152 *tp, bool enable) 2427 { 2428 u8 u1u2[8]; 2429 2430 if (enable) 2431 memset(u1u2, 0xff, sizeof(u1u2)); 2432 else 2433 memset(u1u2, 0x00, sizeof(u1u2)); 2434 2435 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 2436 } 2437 2438 static void r8153_u2p3en(struct r8152 *tp, bool enable) 2439 { 2440 u32 ocp_data; 2441 2442 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 2443 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04) 2444 ocp_data |= U2P3_ENABLE; 2445 else 2446 ocp_data &= ~U2P3_ENABLE; 2447 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 2448 } 2449 2450 static void r8153_power_cut_en(struct r8152 *tp, bool enable) 2451 { 2452 u32 ocp_data; 2453 2454 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 2455 if (enable) 2456 ocp_data |= PWR_EN | PHASE2_EN; 2457 else 2458 ocp_data &= ~(PWR_EN | PHASE2_EN); 2459 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 2460 2461 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 2462 ocp_data &= ~PCUT_STATUS; 2463 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 2464 } 2465 2466 static bool rtl_can_wakeup(struct r8152 *tp) 2467 { 2468 struct usb_device *udev = tp->udev; 2469 2470 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); 2471 } 2472 2473 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 2474 { 2475 if (enable) { 2476 u32 ocp_data; 2477 2478 __rtl_set_wol(tp, WAKE_ANY); 2479 2480 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2481 2482 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2483 ocp_data |= LINK_OFF_WAKE_EN; 2484 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2485 2486 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2487 } else { 2488 u32 ocp_data; 2489 2490 __rtl_set_wol(tp, tp->saved_wolopts); 2491 2492 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 2493 2494 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 2495 ocp_data &= ~LINK_OFF_WAKE_EN; 2496 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 2497 2498 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2499 } 2500 } 2501 2502 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) 2503 { 2504 rtl_runtime_suspend_enable(tp, enable); 2505 2506 if (enable) { 2507 r8153_u1u2en(tp, false); 2508 r8153_u2p3en(tp, false); 2509 } else { 2510 r8153_u2p3en(tp, true); 2511 r8153_u1u2en(tp, true); 2512 } 2513 } 2514 2515 static void rtl_phy_reset(struct r8152 *tp) 2516 { 2517 u16 data; 2518 int i; 2519 2520 data = r8152_mdio_read(tp, MII_BMCR); 2521 2522 /* don't reset again before the previous one complete */ 2523 if (data & BMCR_RESET) 2524 return; 2525 2526 data |= BMCR_RESET; 2527 r8152_mdio_write(tp, MII_BMCR, data); 2528 2529 for (i = 0; i < 50; i++) { 2530 msleep(20); 2531 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 2532 break; 2533 } 2534 } 2535 2536 static void r8153_teredo_off(struct r8152 *tp) 2537 { 2538 u32 ocp_data; 2539 2540 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2541 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); 2542 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2543 2544 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 2545 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 2546 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 2547 } 2548 2549 static void rtl_reset_bmu(struct r8152 *tp) 2550 { 2551 u32 ocp_data; 2552 2553 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); 2554 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 2555 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2556 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 2557 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2558 } 2559 2560 static void r8152_aldps_en(struct r8152 *tp, bool enable) 2561 { 2562 if (enable) { 2563 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 2564 LINKENA | DIS_SDSAVE); 2565 } else { 2566 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | 2567 DIS_SDSAVE); 2568 msleep(20); 2569 } 2570 } 2571 2572 static void rtl8152_disable(struct r8152 *tp) 2573 { 2574 r8152_aldps_en(tp, false); 2575 rtl_disable(tp); 2576 r8152_aldps_en(tp, true); 2577 } 2578 2579 static void r8152b_hw_phy_cfg(struct r8152 *tp) 2580 { 2581 u16 data; 2582 2583 data = r8152_mdio_read(tp, MII_BMCR); 2584 if (data & BMCR_PDOWN) { 2585 data &= ~BMCR_PDOWN; 2586 r8152_mdio_write(tp, MII_BMCR, data); 2587 } 2588 2589 set_bit(PHY_RESET, &tp->flags); 2590 } 2591 2592 static void r8152b_exit_oob(struct r8152 *tp) 2593 { 2594 u32 ocp_data; 2595 int i; 2596 2597 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2598 ocp_data &= ~RCR_ACPT_ALL; 2599 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2600 2601 rxdy_gated_en(tp, true); 2602 r8153_teredo_off(tp); 2603 r8152b_hw_phy_cfg(tp); 2604 2605 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 2606 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 2607 2608 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2609 ocp_data &= ~NOW_IS_OOB; 2610 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2611 2612 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2613 ocp_data &= ~MCU_BORW_EN; 2614 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2615 2616 for (i = 0; i < 1000; i++) { 2617 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2618 if (ocp_data & LINK_LIST_READY) 2619 break; 2620 usleep_range(1000, 2000); 2621 } 2622 2623 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2624 ocp_data |= RE_INIT_LL; 2625 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2626 2627 for (i = 0; i < 1000; i++) { 2628 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2629 if (ocp_data & LINK_LIST_READY) 2630 break; 2631 usleep_range(1000, 2000); 2632 } 2633 2634 rtl8152_nic_reset(tp); 2635 2636 /* rx share fifo credit full threshold */ 2637 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2638 2639 if (tp->udev->speed == USB_SPEED_FULL || 2640 tp->udev->speed == USB_SPEED_LOW) { 2641 /* rx share fifo credit near full threshold */ 2642 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2643 RXFIFO_THR2_FULL); 2644 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2645 RXFIFO_THR3_FULL); 2646 } else { 2647 /* rx share fifo credit near full threshold */ 2648 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 2649 RXFIFO_THR2_HIGH); 2650 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 2651 RXFIFO_THR3_HIGH); 2652 } 2653 2654 /* TX share fifo free credit full threshold */ 2655 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 2656 2657 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 2658 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 2659 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 2660 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 2661 2662 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 2663 2664 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2665 2666 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2667 ocp_data |= TCR0_AUTO_FIFO; 2668 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2669 } 2670 2671 static void r8152b_enter_oob(struct r8152 *tp) 2672 { 2673 u32 ocp_data; 2674 int i; 2675 2676 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2677 ocp_data &= ~NOW_IS_OOB; 2678 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2679 2680 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 2681 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 2682 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 2683 2684 rtl_disable(tp); 2685 2686 for (i = 0; i < 1000; i++) { 2687 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2688 if (ocp_data & LINK_LIST_READY) 2689 break; 2690 usleep_range(1000, 2000); 2691 } 2692 2693 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2694 ocp_data |= RE_INIT_LL; 2695 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2696 2697 for (i = 0; i < 1000; i++) { 2698 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2699 if (ocp_data & LINK_LIST_READY) 2700 break; 2701 usleep_range(1000, 2000); 2702 } 2703 2704 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2705 2706 rtl_rx_vlan_en(tp, true); 2707 2708 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2709 ocp_data |= ALDPS_PROXY_MODE; 2710 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2711 2712 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2713 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2714 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2715 2716 rxdy_gated_en(tp, false); 2717 2718 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2719 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2720 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2721 } 2722 2723 static void r8153_hw_phy_cfg(struct r8152 *tp) 2724 { 2725 u32 ocp_data; 2726 u16 data; 2727 2728 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 2729 tp->version == RTL_VER_05) 2730 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 2731 2732 data = r8152_mdio_read(tp, MII_BMCR); 2733 if (data & BMCR_PDOWN) { 2734 data &= ~BMCR_PDOWN; 2735 r8152_mdio_write(tp, MII_BMCR, data); 2736 } 2737 2738 if (tp->version == RTL_VER_03) { 2739 data = ocp_reg_read(tp, OCP_EEE_CFG); 2740 data &= ~CTAP_SHORT_EN; 2741 ocp_reg_write(tp, OCP_EEE_CFG, data); 2742 } 2743 2744 data = ocp_reg_read(tp, OCP_POWER_CFG); 2745 data |= EEE_CLKDIV_EN; 2746 ocp_reg_write(tp, OCP_POWER_CFG, data); 2747 2748 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 2749 data |= EN_10M_BGOFF; 2750 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 2751 data = ocp_reg_read(tp, OCP_POWER_CFG); 2752 data |= EN_10M_PLLOFF; 2753 ocp_reg_write(tp, OCP_POWER_CFG, data); 2754 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 2755 2756 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 2757 ocp_data |= PFM_PWM_SWITCH; 2758 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 2759 2760 /* Enable LPF corner auto tune */ 2761 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 2762 2763 /* Adjust 10M Amplitude */ 2764 sram_write(tp, SRAM_10M_AMP1, 0x00af); 2765 sram_write(tp, SRAM_10M_AMP2, 0x0208); 2766 2767 set_bit(PHY_RESET, &tp->flags); 2768 } 2769 2770 static void r8153_first_init(struct r8152 *tp) 2771 { 2772 u32 ocp_data; 2773 int i; 2774 2775 rxdy_gated_en(tp, true); 2776 r8153_teredo_off(tp); 2777 2778 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2779 ocp_data &= ~RCR_ACPT_ALL; 2780 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2781 2782 r8153_hw_phy_cfg(tp); 2783 2784 rtl8152_nic_reset(tp); 2785 rtl_reset_bmu(tp); 2786 2787 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2788 ocp_data &= ~NOW_IS_OOB; 2789 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2790 2791 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2792 ocp_data &= ~MCU_BORW_EN; 2793 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2794 2795 for (i = 0; i < 1000; i++) { 2796 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2797 if (ocp_data & LINK_LIST_READY) 2798 break; 2799 usleep_range(1000, 2000); 2800 } 2801 2802 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2803 ocp_data |= RE_INIT_LL; 2804 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2805 2806 for (i = 0; i < 1000; i++) { 2807 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2808 if (ocp_data & LINK_LIST_READY) 2809 break; 2810 usleep_range(1000, 2000); 2811 } 2812 2813 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 2814 2815 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); 2816 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 2817 2818 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2819 ocp_data |= TCR0_AUTO_FIFO; 2820 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 2821 2822 rtl8152_nic_reset(tp); 2823 2824 /* rx share fifo credit full threshold */ 2825 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 2826 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 2827 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 2828 /* TX share fifo free credit full threshold */ 2829 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 2830 2831 /* rx aggregation */ 2832 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 2833 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 2834 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 2835 } 2836 2837 static void r8153_enter_oob(struct r8152 *tp) 2838 { 2839 u32 ocp_data; 2840 int i; 2841 2842 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2843 ocp_data &= ~NOW_IS_OOB; 2844 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2845 2846 rtl_disable(tp); 2847 rtl_reset_bmu(tp); 2848 2849 for (i = 0; i < 1000; i++) { 2850 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2851 if (ocp_data & LINK_LIST_READY) 2852 break; 2853 usleep_range(1000, 2000); 2854 } 2855 2856 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 2857 ocp_data |= RE_INIT_LL; 2858 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 2859 2860 for (i = 0; i < 1000; i++) { 2861 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2862 if (ocp_data & LINK_LIST_READY) 2863 break; 2864 usleep_range(1000, 2000); 2865 } 2866 2867 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); 2868 2869 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2870 ocp_data &= ~TEREDO_WAKE_MASK; 2871 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 2872 2873 rtl_rx_vlan_en(tp, true); 2874 2875 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); 2876 ocp_data |= ALDPS_PROXY_MODE; 2877 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); 2878 2879 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 2880 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 2881 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 2882 2883 rxdy_gated_en(tp, false); 2884 2885 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2886 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 2887 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2888 } 2889 2890 static void r8153_aldps_en(struct r8152 *tp, bool enable) 2891 { 2892 u16 data; 2893 2894 data = ocp_reg_read(tp, OCP_POWER_CFG); 2895 if (enable) { 2896 data |= EN_ALDPS; 2897 ocp_reg_write(tp, OCP_POWER_CFG, data); 2898 } else { 2899 data &= ~EN_ALDPS; 2900 ocp_reg_write(tp, OCP_POWER_CFG, data); 2901 msleep(20); 2902 } 2903 } 2904 2905 static void rtl8153_disable(struct r8152 *tp) 2906 { 2907 r8153_aldps_en(tp, false); 2908 rtl_disable(tp); 2909 rtl_reset_bmu(tp); 2910 r8153_aldps_en(tp, true); 2911 usb_enable_lpm(tp->udev); 2912 } 2913 2914 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 2915 { 2916 u16 bmcr, anar, gbcr; 2917 int ret = 0; 2918 2919 cancel_delayed_work_sync(&tp->schedule); 2920 anar = r8152_mdio_read(tp, MII_ADVERTISE); 2921 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 2922 ADVERTISE_100HALF | ADVERTISE_100FULL); 2923 if (tp->mii.supports_gmii) { 2924 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 2925 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 2926 } else { 2927 gbcr = 0; 2928 } 2929 2930 if (autoneg == AUTONEG_DISABLE) { 2931 if (speed == SPEED_10) { 2932 bmcr = 0; 2933 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2934 } else if (speed == SPEED_100) { 2935 bmcr = BMCR_SPEED100; 2936 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2937 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 2938 bmcr = BMCR_SPEED1000; 2939 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 2940 } else { 2941 ret = -EINVAL; 2942 goto out; 2943 } 2944 2945 if (duplex == DUPLEX_FULL) 2946 bmcr |= BMCR_FULLDPLX; 2947 } else { 2948 if (speed == SPEED_10) { 2949 if (duplex == DUPLEX_FULL) 2950 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2951 else 2952 anar |= ADVERTISE_10HALF; 2953 } else if (speed == SPEED_100) { 2954 if (duplex == DUPLEX_FULL) { 2955 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2956 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2957 } else { 2958 anar |= ADVERTISE_10HALF; 2959 anar |= ADVERTISE_100HALF; 2960 } 2961 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { 2962 if (duplex == DUPLEX_FULL) { 2963 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 2964 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 2965 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 2966 } else { 2967 anar |= ADVERTISE_10HALF; 2968 anar |= ADVERTISE_100HALF; 2969 gbcr |= ADVERTISE_1000HALF; 2970 } 2971 } else { 2972 ret = -EINVAL; 2973 goto out; 2974 } 2975 2976 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 2977 } 2978 2979 if (test_bit(PHY_RESET, &tp->flags)) 2980 bmcr |= BMCR_RESET; 2981 2982 if (tp->mii.supports_gmii) 2983 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 2984 2985 r8152_mdio_write(tp, MII_ADVERTISE, anar); 2986 r8152_mdio_write(tp, MII_BMCR, bmcr); 2987 2988 if (test_and_clear_bit(PHY_RESET, &tp->flags)) { 2989 int i; 2990 2991 for (i = 0; i < 50; i++) { 2992 msleep(20); 2993 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 2994 break; 2995 } 2996 } 2997 2998 out: 2999 return ret; 3000 } 3001 3002 static void rtl8152_up(struct r8152 *tp) 3003 { 3004 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3005 return; 3006 3007 r8152_aldps_en(tp, false); 3008 r8152b_exit_oob(tp); 3009 r8152_aldps_en(tp, true); 3010 } 3011 3012 static void rtl8152_down(struct r8152 *tp) 3013 { 3014 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3015 rtl_drop_queued_tx(tp); 3016 return; 3017 } 3018 3019 r8152_power_cut_en(tp, false); 3020 r8152_aldps_en(tp, false); 3021 r8152b_enter_oob(tp); 3022 r8152_aldps_en(tp, true); 3023 } 3024 3025 static void rtl8153_up(struct r8152 *tp) 3026 { 3027 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3028 return; 3029 3030 r8153_u1u2en(tp, false); 3031 r8153_aldps_en(tp, false); 3032 r8153_first_init(tp); 3033 r8153_aldps_en(tp, true); 3034 r8153_u2p3en(tp, true); 3035 r8153_u1u2en(tp, true); 3036 usb_enable_lpm(tp->udev); 3037 } 3038 3039 static void rtl8153_down(struct r8152 *tp) 3040 { 3041 if (test_bit(RTL8152_UNPLUG, &tp->flags)) { 3042 rtl_drop_queued_tx(tp); 3043 return; 3044 } 3045 3046 r8153_u1u2en(tp, false); 3047 r8153_u2p3en(tp, false); 3048 r8153_power_cut_en(tp, false); 3049 r8153_aldps_en(tp, false); 3050 r8153_enter_oob(tp); 3051 r8153_aldps_en(tp, true); 3052 } 3053 3054 static bool rtl8152_in_nway(struct r8152 *tp) 3055 { 3056 u16 nway_state; 3057 3058 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); 3059 tp->ocp_base = 0x2000; 3060 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ 3061 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); 3062 3063 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ 3064 if (nway_state & 0xc000) 3065 return false; 3066 else 3067 return true; 3068 } 3069 3070 static bool rtl8153_in_nway(struct r8152 *tp) 3071 { 3072 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; 3073 3074 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) 3075 return false; 3076 else 3077 return true; 3078 } 3079 3080 static void set_carrier(struct r8152 *tp) 3081 { 3082 struct net_device *netdev = tp->netdev; 3083 u8 speed; 3084 3085 speed = rtl8152_get_speed(tp); 3086 3087 if (speed & LINK_STATUS) { 3088 if (!netif_carrier_ok(netdev)) { 3089 tp->rtl_ops.enable(tp); 3090 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 3091 napi_disable(&tp->napi); 3092 netif_carrier_on(netdev); 3093 rtl_start_rx(tp); 3094 napi_enable(&tp->napi); 3095 } 3096 } else { 3097 if (netif_carrier_ok(netdev)) { 3098 netif_carrier_off(netdev); 3099 napi_disable(&tp->napi); 3100 tp->rtl_ops.disable(tp); 3101 napi_enable(&tp->napi); 3102 } 3103 } 3104 } 3105 3106 static void rtl_work_func_t(struct work_struct *work) 3107 { 3108 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 3109 3110 /* If the device is unplugged or !netif_running(), the workqueue 3111 * doesn't need to wake the device, and could return directly. 3112 */ 3113 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) 3114 return; 3115 3116 if (usb_autopm_get_interface(tp->intf) < 0) 3117 return; 3118 3119 if (!test_bit(WORK_ENABLE, &tp->flags)) 3120 goto out1; 3121 3122 if (!mutex_trylock(&tp->control)) { 3123 schedule_delayed_work(&tp->schedule, 0); 3124 goto out1; 3125 } 3126 3127 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) 3128 set_carrier(tp); 3129 3130 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) 3131 _rtl8152_set_rx_mode(tp->netdev); 3132 3133 /* don't schedule napi before linking */ 3134 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) && 3135 netif_carrier_ok(tp->netdev)) 3136 napi_schedule(&tp->napi); 3137 3138 if (test_and_clear_bit(PHY_RESET, &tp->flags)) 3139 rtl_phy_reset(tp); 3140 3141 mutex_unlock(&tp->control); 3142 3143 out1: 3144 usb_autopm_put_interface(tp->intf); 3145 } 3146 3147 #ifdef CONFIG_PM_SLEEP 3148 static int rtl_notifier(struct notifier_block *nb, unsigned long action, 3149 void *data) 3150 { 3151 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); 3152 3153 switch (action) { 3154 case PM_HIBERNATION_PREPARE: 3155 case PM_SUSPEND_PREPARE: 3156 usb_autopm_get_interface(tp->intf); 3157 break; 3158 3159 case PM_POST_HIBERNATION: 3160 case PM_POST_SUSPEND: 3161 usb_autopm_put_interface(tp->intf); 3162 break; 3163 3164 case PM_POST_RESTORE: 3165 case PM_RESTORE_PREPARE: 3166 default: 3167 break; 3168 } 3169 3170 return NOTIFY_DONE; 3171 } 3172 #endif 3173 3174 static int rtl8152_open(struct net_device *netdev) 3175 { 3176 struct r8152 *tp = netdev_priv(netdev); 3177 int res = 0; 3178 3179 res = alloc_all_mem(tp); 3180 if (res) 3181 goto out; 3182 3183 netif_carrier_off(netdev); 3184 3185 res = usb_autopm_get_interface(tp->intf); 3186 if (res < 0) { 3187 free_all_mem(tp); 3188 goto out; 3189 } 3190 3191 mutex_lock(&tp->control); 3192 3193 tp->rtl_ops.up(tp); 3194 3195 rtl8152_set_speed(tp, AUTONEG_ENABLE, 3196 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, 3197 DUPLEX_FULL); 3198 netif_carrier_off(netdev); 3199 netif_start_queue(netdev); 3200 set_bit(WORK_ENABLE, &tp->flags); 3201 3202 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3203 if (res) { 3204 if (res == -ENODEV) 3205 netif_device_detach(tp->netdev); 3206 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 3207 res); 3208 free_all_mem(tp); 3209 } else { 3210 napi_enable(&tp->napi); 3211 } 3212 3213 mutex_unlock(&tp->control); 3214 3215 usb_autopm_put_interface(tp->intf); 3216 #ifdef CONFIG_PM_SLEEP 3217 tp->pm_notifier.notifier_call = rtl_notifier; 3218 register_pm_notifier(&tp->pm_notifier); 3219 #endif 3220 3221 out: 3222 return res; 3223 } 3224 3225 static int rtl8152_close(struct net_device *netdev) 3226 { 3227 struct r8152 *tp = netdev_priv(netdev); 3228 int res = 0; 3229 3230 #ifdef CONFIG_PM_SLEEP 3231 unregister_pm_notifier(&tp->pm_notifier); 3232 #endif 3233 napi_disable(&tp->napi); 3234 clear_bit(WORK_ENABLE, &tp->flags); 3235 usb_kill_urb(tp->intr_urb); 3236 cancel_delayed_work_sync(&tp->schedule); 3237 netif_stop_queue(netdev); 3238 3239 res = usb_autopm_get_interface(tp->intf); 3240 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { 3241 rtl_drop_queued_tx(tp); 3242 rtl_stop_rx(tp); 3243 } else { 3244 mutex_lock(&tp->control); 3245 3246 tp->rtl_ops.down(tp); 3247 3248 mutex_unlock(&tp->control); 3249 3250 usb_autopm_put_interface(tp->intf); 3251 } 3252 3253 free_all_mem(tp); 3254 3255 return res; 3256 } 3257 3258 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 3259 { 3260 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 3261 ocp_reg_write(tp, OCP_EEE_DATA, reg); 3262 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 3263 } 3264 3265 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 3266 { 3267 u16 data; 3268 3269 r8152_mmd_indirect(tp, dev, reg); 3270 data = ocp_reg_read(tp, OCP_EEE_DATA); 3271 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3272 3273 return data; 3274 } 3275 3276 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 3277 { 3278 r8152_mmd_indirect(tp, dev, reg); 3279 ocp_reg_write(tp, OCP_EEE_DATA, data); 3280 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 3281 } 3282 3283 static void r8152_eee_en(struct r8152 *tp, bool enable) 3284 { 3285 u16 config1, config2, config3; 3286 u32 ocp_data; 3287 3288 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3289 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 3290 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 3291 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 3292 3293 if (enable) { 3294 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3295 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 3296 config1 |= sd_rise_time(1); 3297 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 3298 config3 |= fast_snr(42); 3299 } else { 3300 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3301 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 3302 RX_QUIET_EN); 3303 config1 |= sd_rise_time(7); 3304 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 3305 config3 |= fast_snr(511); 3306 } 3307 3308 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3309 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 3310 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 3311 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 3312 } 3313 3314 static void r8152b_enable_eee(struct r8152 *tp) 3315 { 3316 r8152_eee_en(tp, true); 3317 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); 3318 } 3319 3320 static void r8153_eee_en(struct r8152 *tp, bool enable) 3321 { 3322 u32 ocp_data; 3323 u16 config; 3324 3325 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3326 config = ocp_reg_read(tp, OCP_EEE_CFG); 3327 3328 if (enable) { 3329 ocp_data |= EEE_RX_EN | EEE_TX_EN; 3330 config |= EEE10_EN; 3331 } else { 3332 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 3333 config &= ~EEE10_EN; 3334 } 3335 3336 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 3337 ocp_reg_write(tp, OCP_EEE_CFG, config); 3338 } 3339 3340 static void r8153_enable_eee(struct r8152 *tp) 3341 { 3342 r8153_eee_en(tp, true); 3343 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); 3344 } 3345 3346 static void r8152b_enable_fc(struct r8152 *tp) 3347 { 3348 u16 anar; 3349 3350 anar = r8152_mdio_read(tp, MII_ADVERTISE); 3351 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 3352 r8152_mdio_write(tp, MII_ADVERTISE, anar); 3353 } 3354 3355 static void rtl_tally_reset(struct r8152 *tp) 3356 { 3357 u32 ocp_data; 3358 3359 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 3360 ocp_data |= TALLY_RESET; 3361 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 3362 } 3363 3364 static void r8152b_init(struct r8152 *tp) 3365 { 3366 u32 ocp_data; 3367 3368 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3369 return; 3370 3371 r8152_aldps_en(tp, false); 3372 3373 if (tp->version == RTL_VER_01) { 3374 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 3375 ocp_data &= ~LED_MODE_MASK; 3376 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 3377 } 3378 3379 r8152_power_cut_en(tp, false); 3380 3381 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 3382 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 3383 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 3384 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 3385 ocp_data &= ~MCU_CLK_RATIO_MASK; 3386 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 3387 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 3388 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 3389 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 3390 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 3391 3392 r8152b_enable_eee(tp); 3393 r8152_aldps_en(tp, true); 3394 r8152b_enable_fc(tp); 3395 rtl_tally_reset(tp); 3396 3397 /* enable rx aggregation */ 3398 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 3399 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 3400 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 3401 } 3402 3403 static void r8153_init(struct r8152 *tp) 3404 { 3405 u32 ocp_data; 3406 int i; 3407 3408 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 3409 return; 3410 3411 r8153_aldps_en(tp, false); 3412 r8153_u1u2en(tp, false); 3413 3414 for (i = 0; i < 500; i++) { 3415 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 3416 AUTOLOAD_DONE) 3417 break; 3418 msleep(20); 3419 } 3420 3421 for (i = 0; i < 500; i++) { 3422 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; 3423 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) 3424 break; 3425 msleep(20); 3426 } 3427 3428 usb_disable_lpm(tp->udev); 3429 r8153_u2p3en(tp, false); 3430 3431 if (tp->version == RTL_VER_04) { 3432 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 3433 ocp_data &= ~pwd_dn_scale_mask; 3434 ocp_data |= pwd_dn_scale(96); 3435 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 3436 3437 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 3438 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 3439 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 3440 } else if (tp->version == RTL_VER_05) { 3441 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 3442 ocp_data &= ~ECM_ALDPS; 3443 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 3444 3445 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 3446 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 3447 ocp_data &= ~DYNAMIC_BURST; 3448 else 3449 ocp_data |= DYNAMIC_BURST; 3450 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 3451 } else if (tp->version == RTL_VER_06) { 3452 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 3453 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 3454 ocp_data &= ~DYNAMIC_BURST; 3455 else 3456 ocp_data |= DYNAMIC_BURST; 3457 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 3458 } 3459 3460 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 3461 ocp_data |= EP4_FULL_FC; 3462 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 3463 3464 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 3465 ocp_data &= ~TIMER11_EN; 3466 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 3467 3468 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 3469 ocp_data &= ~LED_MODE_MASK; 3470 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 3471 3472 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 3473 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) 3474 ocp_data |= LPM_TIMER_500MS; 3475 else 3476 ocp_data |= LPM_TIMER_500US; 3477 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 3478 3479 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 3480 ocp_data &= ~SEN_VAL_MASK; 3481 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 3482 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 3483 3484 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 3485 3486 r8153_power_cut_en(tp, false); 3487 r8153_u1u2en(tp, true); 3488 3489 /* MAC clock speed down */ 3490 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); 3491 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); 3492 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); 3493 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); 3494 3495 r8153_enable_eee(tp); 3496 r8153_aldps_en(tp, true); 3497 r8152b_enable_fc(tp); 3498 rtl_tally_reset(tp); 3499 r8153_u2p3en(tp, true); 3500 } 3501 3502 static int rtl8152_pre_reset(struct usb_interface *intf) 3503 { 3504 struct r8152 *tp = usb_get_intfdata(intf); 3505 struct net_device *netdev; 3506 3507 if (!tp) 3508 return 0; 3509 3510 netdev = tp->netdev; 3511 if (!netif_running(netdev)) 3512 return 0; 3513 3514 napi_disable(&tp->napi); 3515 clear_bit(WORK_ENABLE, &tp->flags); 3516 usb_kill_urb(tp->intr_urb); 3517 cancel_delayed_work_sync(&tp->schedule); 3518 if (netif_carrier_ok(netdev)) { 3519 netif_stop_queue(netdev); 3520 mutex_lock(&tp->control); 3521 tp->rtl_ops.disable(tp); 3522 mutex_unlock(&tp->control); 3523 } 3524 3525 return 0; 3526 } 3527 3528 static int rtl8152_post_reset(struct usb_interface *intf) 3529 { 3530 struct r8152 *tp = usb_get_intfdata(intf); 3531 struct net_device *netdev; 3532 3533 if (!tp) 3534 return 0; 3535 3536 netdev = tp->netdev; 3537 if (!netif_running(netdev)) 3538 return 0; 3539 3540 set_bit(WORK_ENABLE, &tp->flags); 3541 if (netif_carrier_ok(netdev)) { 3542 mutex_lock(&tp->control); 3543 tp->rtl_ops.enable(tp); 3544 rtl8152_set_rx_mode(netdev); 3545 mutex_unlock(&tp->control); 3546 netif_wake_queue(netdev); 3547 } 3548 3549 napi_enable(&tp->napi); 3550 3551 return 0; 3552 } 3553 3554 static bool delay_autosuspend(struct r8152 *tp) 3555 { 3556 bool sw_linking = !!netif_carrier_ok(tp->netdev); 3557 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); 3558 3559 /* This means a linking change occurs and the driver doesn't detect it, 3560 * yet. If the driver has disabled tx/rx and hw is linking on, the 3561 * device wouldn't wake up by receiving any packet. 3562 */ 3563 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) 3564 return true; 3565 3566 /* If the linking down is occurred by nway, the device may miss the 3567 * linking change event. And it wouldn't wake when linking on. 3568 */ 3569 if (!sw_linking && tp->rtl_ops.in_nway(tp)) 3570 return true; 3571 else 3572 return false; 3573 } 3574 3575 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 3576 { 3577 struct r8152 *tp = usb_get_intfdata(intf); 3578 struct net_device *netdev = tp->netdev; 3579 int ret = 0; 3580 3581 mutex_lock(&tp->control); 3582 3583 if (PMSG_IS_AUTO(message)) { 3584 if (netif_running(netdev) && delay_autosuspend(tp)) { 3585 ret = -EBUSY; 3586 goto out1; 3587 } 3588 3589 set_bit(SELECTIVE_SUSPEND, &tp->flags); 3590 } else { 3591 netif_device_detach(netdev); 3592 } 3593 3594 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 3595 clear_bit(WORK_ENABLE, &tp->flags); 3596 usb_kill_urb(tp->intr_urb); 3597 napi_disable(&tp->napi); 3598 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3599 rtl_stop_rx(tp); 3600 tp->rtl_ops.autosuspend_en(tp, true); 3601 } else { 3602 cancel_delayed_work_sync(&tp->schedule); 3603 tp->rtl_ops.down(tp); 3604 } 3605 napi_enable(&tp->napi); 3606 } 3607 out1: 3608 mutex_unlock(&tp->control); 3609 3610 return ret; 3611 } 3612 3613 static int rtl8152_resume(struct usb_interface *intf) 3614 { 3615 struct r8152 *tp = usb_get_intfdata(intf); 3616 3617 mutex_lock(&tp->control); 3618 3619 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3620 tp->rtl_ops.init(tp); 3621 netif_device_attach(tp->netdev); 3622 } 3623 3624 if (netif_running(tp->netdev) && tp->netdev->flags & IFF_UP) { 3625 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3626 tp->rtl_ops.autosuspend_en(tp, false); 3627 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3628 napi_disable(&tp->napi); 3629 set_bit(WORK_ENABLE, &tp->flags); 3630 if (netif_carrier_ok(tp->netdev)) 3631 rtl_start_rx(tp); 3632 napi_enable(&tp->napi); 3633 } else { 3634 tp->rtl_ops.up(tp); 3635 rtl8152_set_speed(tp, AUTONEG_ENABLE, 3636 tp->mii.supports_gmii ? 3637 SPEED_1000 : SPEED_100, 3638 DUPLEX_FULL); 3639 netif_carrier_off(tp->netdev); 3640 set_bit(WORK_ENABLE, &tp->flags); 3641 } 3642 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 3643 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 3644 if (tp->netdev->flags & IFF_UP) 3645 tp->rtl_ops.autosuspend_en(tp, false); 3646 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3647 } 3648 3649 mutex_unlock(&tp->control); 3650 3651 return 0; 3652 } 3653 3654 static int rtl8152_reset_resume(struct usb_interface *intf) 3655 { 3656 struct r8152 *tp = usb_get_intfdata(intf); 3657 3658 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 3659 return rtl8152_resume(intf); 3660 } 3661 3662 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3663 { 3664 struct r8152 *tp = netdev_priv(dev); 3665 3666 if (usb_autopm_get_interface(tp->intf) < 0) 3667 return; 3668 3669 if (!rtl_can_wakeup(tp)) { 3670 wol->supported = 0; 3671 wol->wolopts = 0; 3672 } else { 3673 mutex_lock(&tp->control); 3674 wol->supported = WAKE_ANY; 3675 wol->wolopts = __rtl_get_wol(tp); 3676 mutex_unlock(&tp->control); 3677 } 3678 3679 usb_autopm_put_interface(tp->intf); 3680 } 3681 3682 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3683 { 3684 struct r8152 *tp = netdev_priv(dev); 3685 int ret; 3686 3687 if (!rtl_can_wakeup(tp)) 3688 return -EOPNOTSUPP; 3689 3690 ret = usb_autopm_get_interface(tp->intf); 3691 if (ret < 0) 3692 goto out_set_wol; 3693 3694 mutex_lock(&tp->control); 3695 3696 __rtl_set_wol(tp, wol->wolopts); 3697 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 3698 3699 mutex_unlock(&tp->control); 3700 3701 usb_autopm_put_interface(tp->intf); 3702 3703 out_set_wol: 3704 return ret; 3705 } 3706 3707 static u32 rtl8152_get_msglevel(struct net_device *dev) 3708 { 3709 struct r8152 *tp = netdev_priv(dev); 3710 3711 return tp->msg_enable; 3712 } 3713 3714 static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 3715 { 3716 struct r8152 *tp = netdev_priv(dev); 3717 3718 tp->msg_enable = value; 3719 } 3720 3721 static void rtl8152_get_drvinfo(struct net_device *netdev, 3722 struct ethtool_drvinfo *info) 3723 { 3724 struct r8152 *tp = netdev_priv(netdev); 3725 3726 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 3727 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 3728 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 3729 } 3730 3731 static 3732 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) 3733 { 3734 struct r8152 *tp = netdev_priv(netdev); 3735 int ret; 3736 3737 if (!tp->mii.mdio_read) 3738 return -EOPNOTSUPP; 3739 3740 ret = usb_autopm_get_interface(tp->intf); 3741 if (ret < 0) 3742 goto out; 3743 3744 mutex_lock(&tp->control); 3745 3746 ret = mii_ethtool_gset(&tp->mii, cmd); 3747 3748 mutex_unlock(&tp->control); 3749 3750 usb_autopm_put_interface(tp->intf); 3751 3752 out: 3753 return ret; 3754 } 3755 3756 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 3757 { 3758 struct r8152 *tp = netdev_priv(dev); 3759 int ret; 3760 3761 ret = usb_autopm_get_interface(tp->intf); 3762 if (ret < 0) 3763 goto out; 3764 3765 mutex_lock(&tp->control); 3766 3767 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); 3768 3769 mutex_unlock(&tp->control); 3770 3771 usb_autopm_put_interface(tp->intf); 3772 3773 out: 3774 return ret; 3775 } 3776 3777 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 3778 "tx_packets", 3779 "rx_packets", 3780 "tx_errors", 3781 "rx_errors", 3782 "rx_missed", 3783 "align_errors", 3784 "tx_single_collisions", 3785 "tx_multi_collisions", 3786 "rx_unicast", 3787 "rx_broadcast", 3788 "rx_multicast", 3789 "tx_aborted", 3790 "tx_underrun", 3791 }; 3792 3793 static int rtl8152_get_sset_count(struct net_device *dev, int sset) 3794 { 3795 switch (sset) { 3796 case ETH_SS_STATS: 3797 return ARRAY_SIZE(rtl8152_gstrings); 3798 default: 3799 return -EOPNOTSUPP; 3800 } 3801 } 3802 3803 static void rtl8152_get_ethtool_stats(struct net_device *dev, 3804 struct ethtool_stats *stats, u64 *data) 3805 { 3806 struct r8152 *tp = netdev_priv(dev); 3807 struct tally_counter tally; 3808 3809 if (usb_autopm_get_interface(tp->intf) < 0) 3810 return; 3811 3812 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 3813 3814 usb_autopm_put_interface(tp->intf); 3815 3816 data[0] = le64_to_cpu(tally.tx_packets); 3817 data[1] = le64_to_cpu(tally.rx_packets); 3818 data[2] = le64_to_cpu(tally.tx_errors); 3819 data[3] = le32_to_cpu(tally.rx_errors); 3820 data[4] = le16_to_cpu(tally.rx_missed); 3821 data[5] = le16_to_cpu(tally.align_errors); 3822 data[6] = le32_to_cpu(tally.tx_one_collision); 3823 data[7] = le32_to_cpu(tally.tx_multi_collision); 3824 data[8] = le64_to_cpu(tally.rx_unicast); 3825 data[9] = le64_to_cpu(tally.rx_broadcast); 3826 data[10] = le32_to_cpu(tally.rx_multicast); 3827 data[11] = le16_to_cpu(tally.tx_aborted); 3828 data[12] = le16_to_cpu(tally.tx_underrun); 3829 } 3830 3831 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 3832 { 3833 switch (stringset) { 3834 case ETH_SS_STATS: 3835 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); 3836 break; 3837 } 3838 } 3839 3840 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 3841 { 3842 u32 ocp_data, lp, adv, supported = 0; 3843 u16 val; 3844 3845 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 3846 supported = mmd_eee_cap_to_ethtool_sup_t(val); 3847 3848 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 3849 adv = mmd_eee_adv_to_ethtool_adv_t(val); 3850 3851 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 3852 lp = mmd_eee_adv_to_ethtool_adv_t(val); 3853 3854 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3855 ocp_data &= EEE_RX_EN | EEE_TX_EN; 3856 3857 eee->eee_enabled = !!ocp_data; 3858 eee->eee_active = !!(supported & adv & lp); 3859 eee->supported = supported; 3860 eee->advertised = adv; 3861 eee->lp_advertised = lp; 3862 3863 return 0; 3864 } 3865 3866 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 3867 { 3868 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 3869 3870 r8152_eee_en(tp, eee->eee_enabled); 3871 3872 if (!eee->eee_enabled) 3873 val = 0; 3874 3875 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); 3876 3877 return 0; 3878 } 3879 3880 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) 3881 { 3882 u32 ocp_data, lp, adv, supported = 0; 3883 u16 val; 3884 3885 val = ocp_reg_read(tp, OCP_EEE_ABLE); 3886 supported = mmd_eee_cap_to_ethtool_sup_t(val); 3887 3888 val = ocp_reg_read(tp, OCP_EEE_ADV); 3889 adv = mmd_eee_adv_to_ethtool_adv_t(val); 3890 3891 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 3892 lp = mmd_eee_adv_to_ethtool_adv_t(val); 3893 3894 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 3895 ocp_data &= EEE_RX_EN | EEE_TX_EN; 3896 3897 eee->eee_enabled = !!ocp_data; 3898 eee->eee_active = !!(supported & adv & lp); 3899 eee->supported = supported; 3900 eee->advertised = adv; 3901 eee->lp_advertised = lp; 3902 3903 return 0; 3904 } 3905 3906 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) 3907 { 3908 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); 3909 3910 r8153_eee_en(tp, eee->eee_enabled); 3911 3912 if (!eee->eee_enabled) 3913 val = 0; 3914 3915 ocp_reg_write(tp, OCP_EEE_ADV, val); 3916 3917 return 0; 3918 } 3919 3920 static int 3921 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) 3922 { 3923 struct r8152 *tp = netdev_priv(net); 3924 int ret; 3925 3926 ret = usb_autopm_get_interface(tp->intf); 3927 if (ret < 0) 3928 goto out; 3929 3930 mutex_lock(&tp->control); 3931 3932 ret = tp->rtl_ops.eee_get(tp, edata); 3933 3934 mutex_unlock(&tp->control); 3935 3936 usb_autopm_put_interface(tp->intf); 3937 3938 out: 3939 return ret; 3940 } 3941 3942 static int 3943 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) 3944 { 3945 struct r8152 *tp = netdev_priv(net); 3946 int ret; 3947 3948 ret = usb_autopm_get_interface(tp->intf); 3949 if (ret < 0) 3950 goto out; 3951 3952 mutex_lock(&tp->control); 3953 3954 ret = tp->rtl_ops.eee_set(tp, edata); 3955 if (!ret) 3956 ret = mii_nway_restart(&tp->mii); 3957 3958 mutex_unlock(&tp->control); 3959 3960 usb_autopm_put_interface(tp->intf); 3961 3962 out: 3963 return ret; 3964 } 3965 3966 static int rtl8152_nway_reset(struct net_device *dev) 3967 { 3968 struct r8152 *tp = netdev_priv(dev); 3969 int ret; 3970 3971 ret = usb_autopm_get_interface(tp->intf); 3972 if (ret < 0) 3973 goto out; 3974 3975 mutex_lock(&tp->control); 3976 3977 ret = mii_nway_restart(&tp->mii); 3978 3979 mutex_unlock(&tp->control); 3980 3981 usb_autopm_put_interface(tp->intf); 3982 3983 out: 3984 return ret; 3985 } 3986 3987 static int rtl8152_get_coalesce(struct net_device *netdev, 3988 struct ethtool_coalesce *coalesce) 3989 { 3990 struct r8152 *tp = netdev_priv(netdev); 3991 3992 switch (tp->version) { 3993 case RTL_VER_01: 3994 case RTL_VER_02: 3995 return -EOPNOTSUPP; 3996 default: 3997 break; 3998 } 3999 4000 coalesce->rx_coalesce_usecs = tp->coalesce; 4001 4002 return 0; 4003 } 4004 4005 static int rtl8152_set_coalesce(struct net_device *netdev, 4006 struct ethtool_coalesce *coalesce) 4007 { 4008 struct r8152 *tp = netdev_priv(netdev); 4009 int ret; 4010 4011 switch (tp->version) { 4012 case RTL_VER_01: 4013 case RTL_VER_02: 4014 return -EOPNOTSUPP; 4015 default: 4016 break; 4017 } 4018 4019 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) 4020 return -EINVAL; 4021 4022 ret = usb_autopm_get_interface(tp->intf); 4023 if (ret < 0) 4024 return ret; 4025 4026 mutex_lock(&tp->control); 4027 4028 if (tp->coalesce != coalesce->rx_coalesce_usecs) { 4029 tp->coalesce = coalesce->rx_coalesce_usecs; 4030 4031 if (netif_running(tp->netdev) && netif_carrier_ok(netdev)) 4032 r8153_set_rx_early_timeout(tp); 4033 } 4034 4035 mutex_unlock(&tp->control); 4036 4037 usb_autopm_put_interface(tp->intf); 4038 4039 return ret; 4040 } 4041 4042 static struct ethtool_ops ops = { 4043 .get_drvinfo = rtl8152_get_drvinfo, 4044 .get_settings = rtl8152_get_settings, 4045 .set_settings = rtl8152_set_settings, 4046 .get_link = ethtool_op_get_link, 4047 .nway_reset = rtl8152_nway_reset, 4048 .get_msglevel = rtl8152_get_msglevel, 4049 .set_msglevel = rtl8152_set_msglevel, 4050 .get_wol = rtl8152_get_wol, 4051 .set_wol = rtl8152_set_wol, 4052 .get_strings = rtl8152_get_strings, 4053 .get_sset_count = rtl8152_get_sset_count, 4054 .get_ethtool_stats = rtl8152_get_ethtool_stats, 4055 .get_coalesce = rtl8152_get_coalesce, 4056 .set_coalesce = rtl8152_set_coalesce, 4057 .get_eee = rtl_ethtool_get_eee, 4058 .set_eee = rtl_ethtool_set_eee, 4059 }; 4060 4061 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 4062 { 4063 struct r8152 *tp = netdev_priv(netdev); 4064 struct mii_ioctl_data *data = if_mii(rq); 4065 int res; 4066 4067 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4068 return -ENODEV; 4069 4070 res = usb_autopm_get_interface(tp->intf); 4071 if (res < 0) 4072 goto out; 4073 4074 switch (cmd) { 4075 case SIOCGMIIPHY: 4076 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 4077 break; 4078 4079 case SIOCGMIIREG: 4080 mutex_lock(&tp->control); 4081 data->val_out = r8152_mdio_read(tp, data->reg_num); 4082 mutex_unlock(&tp->control); 4083 break; 4084 4085 case SIOCSMIIREG: 4086 if (!capable(CAP_NET_ADMIN)) { 4087 res = -EPERM; 4088 break; 4089 } 4090 mutex_lock(&tp->control); 4091 r8152_mdio_write(tp, data->reg_num, data->val_in); 4092 mutex_unlock(&tp->control); 4093 break; 4094 4095 default: 4096 res = -EOPNOTSUPP; 4097 } 4098 4099 usb_autopm_put_interface(tp->intf); 4100 4101 out: 4102 return res; 4103 } 4104 4105 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 4106 { 4107 struct r8152 *tp = netdev_priv(dev); 4108 int ret; 4109 4110 switch (tp->version) { 4111 case RTL_VER_01: 4112 case RTL_VER_02: 4113 return eth_change_mtu(dev, new_mtu); 4114 default: 4115 break; 4116 } 4117 4118 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU) 4119 return -EINVAL; 4120 4121 ret = usb_autopm_get_interface(tp->intf); 4122 if (ret < 0) 4123 return ret; 4124 4125 mutex_lock(&tp->control); 4126 4127 dev->mtu = new_mtu; 4128 4129 if (netif_running(dev) && netif_carrier_ok(dev)) 4130 r8153_set_rx_early_size(tp); 4131 4132 mutex_unlock(&tp->control); 4133 4134 usb_autopm_put_interface(tp->intf); 4135 4136 return ret; 4137 } 4138 4139 static const struct net_device_ops rtl8152_netdev_ops = { 4140 .ndo_open = rtl8152_open, 4141 .ndo_stop = rtl8152_close, 4142 .ndo_do_ioctl = rtl8152_ioctl, 4143 .ndo_start_xmit = rtl8152_start_xmit, 4144 .ndo_tx_timeout = rtl8152_tx_timeout, 4145 .ndo_set_features = rtl8152_set_features, 4146 .ndo_set_rx_mode = rtl8152_set_rx_mode, 4147 .ndo_set_mac_address = rtl8152_set_mac_address, 4148 .ndo_change_mtu = rtl8152_change_mtu, 4149 .ndo_validate_addr = eth_validate_addr, 4150 .ndo_features_check = rtl8152_features_check, 4151 }; 4152 4153 static void r8152b_get_version(struct r8152 *tp) 4154 { 4155 u32 ocp_data; 4156 u16 version; 4157 4158 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); 4159 version = (u16)(ocp_data & VERSION_MASK); 4160 4161 switch (version) { 4162 case 0x4c00: 4163 tp->version = RTL_VER_01; 4164 break; 4165 case 0x4c10: 4166 tp->version = RTL_VER_02; 4167 break; 4168 case 0x5c00: 4169 tp->version = RTL_VER_03; 4170 tp->mii.supports_gmii = 1; 4171 break; 4172 case 0x5c10: 4173 tp->version = RTL_VER_04; 4174 tp->mii.supports_gmii = 1; 4175 break; 4176 case 0x5c20: 4177 tp->version = RTL_VER_05; 4178 tp->mii.supports_gmii = 1; 4179 break; 4180 case 0x5c30: 4181 tp->version = RTL_VER_06; 4182 tp->mii.supports_gmii = 1; 4183 break; 4184 default: 4185 netif_info(tp, probe, tp->netdev, 4186 "Unknown version 0x%04x\n", version); 4187 break; 4188 } 4189 } 4190 4191 static void rtl8152_unload(struct r8152 *tp) 4192 { 4193 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4194 return; 4195 4196 if (tp->version != RTL_VER_01) 4197 r8152_power_cut_en(tp, true); 4198 } 4199 4200 static void rtl8153_unload(struct r8152 *tp) 4201 { 4202 if (test_bit(RTL8152_UNPLUG, &tp->flags)) 4203 return; 4204 4205 r8153_power_cut_en(tp, false); 4206 } 4207 4208 static int rtl_ops_init(struct r8152 *tp) 4209 { 4210 struct rtl_ops *ops = &tp->rtl_ops; 4211 int ret = 0; 4212 4213 switch (tp->version) { 4214 case RTL_VER_01: 4215 case RTL_VER_02: 4216 ops->init = r8152b_init; 4217 ops->enable = rtl8152_enable; 4218 ops->disable = rtl8152_disable; 4219 ops->up = rtl8152_up; 4220 ops->down = rtl8152_down; 4221 ops->unload = rtl8152_unload; 4222 ops->eee_get = r8152_get_eee; 4223 ops->eee_set = r8152_set_eee; 4224 ops->in_nway = rtl8152_in_nway; 4225 ops->autosuspend_en = rtl_runtime_suspend_enable; 4226 break; 4227 4228 case RTL_VER_03: 4229 case RTL_VER_04: 4230 case RTL_VER_05: 4231 case RTL_VER_06: 4232 ops->init = r8153_init; 4233 ops->enable = rtl8153_enable; 4234 ops->disable = rtl8153_disable; 4235 ops->up = rtl8153_up; 4236 ops->down = rtl8153_down; 4237 ops->unload = rtl8153_unload; 4238 ops->eee_get = r8153_get_eee; 4239 ops->eee_set = r8153_set_eee; 4240 ops->in_nway = rtl8153_in_nway; 4241 ops->autosuspend_en = rtl8153_runtime_enable; 4242 break; 4243 4244 default: 4245 ret = -ENODEV; 4246 netif_err(tp, probe, tp->netdev, "Unknown Device\n"); 4247 break; 4248 } 4249 4250 return ret; 4251 } 4252 4253 static int rtl8152_probe(struct usb_interface *intf, 4254 const struct usb_device_id *id) 4255 { 4256 struct usb_device *udev = interface_to_usbdev(intf); 4257 struct r8152 *tp; 4258 struct net_device *netdev; 4259 int ret; 4260 4261 if (udev->actconfig->desc.bConfigurationValue != 1) { 4262 usb_driver_set_configuration(udev, 1); 4263 return -ENODEV; 4264 } 4265 4266 usb_reset_device(udev); 4267 netdev = alloc_etherdev(sizeof(struct r8152)); 4268 if (!netdev) { 4269 dev_err(&intf->dev, "Out of memory\n"); 4270 return -ENOMEM; 4271 } 4272 4273 SET_NETDEV_DEV(netdev, &intf->dev); 4274 tp = netdev_priv(netdev); 4275 tp->msg_enable = 0x7FFF; 4276 4277 tp->udev = udev; 4278 tp->netdev = netdev; 4279 tp->intf = intf; 4280 4281 r8152b_get_version(tp); 4282 ret = rtl_ops_init(tp); 4283 if (ret) 4284 goto out; 4285 4286 mutex_init(&tp->control); 4287 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 4288 4289 netdev->netdev_ops = &rtl8152_netdev_ops; 4290 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 4291 4292 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 4293 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 4294 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 4295 NETIF_F_HW_VLAN_CTAG_TX; 4296 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 4297 NETIF_F_TSO | NETIF_F_FRAGLIST | 4298 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 4299 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; 4300 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 4301 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 4302 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 4303 4304 netdev->ethtool_ops = &ops; 4305 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 4306 4307 tp->mii.dev = netdev; 4308 tp->mii.mdio_read = read_mii_word; 4309 tp->mii.mdio_write = write_mii_word; 4310 tp->mii.phy_id_mask = 0x3f; 4311 tp->mii.reg_num_mask = 0x1f; 4312 tp->mii.phy_id = R8152_PHY_ID; 4313 4314 switch (udev->speed) { 4315 case USB_SPEED_SUPER: 4316 case USB_SPEED_SUPER_PLUS: 4317 tp->coalesce = COALESCE_SUPER; 4318 break; 4319 case USB_SPEED_HIGH: 4320 tp->coalesce = COALESCE_HIGH; 4321 break; 4322 default: 4323 tp->coalesce = COALESCE_SLOW; 4324 break; 4325 } 4326 4327 intf->needs_remote_wakeup = 1; 4328 4329 tp->rtl_ops.init(tp); 4330 set_ethernet_addr(tp); 4331 4332 usb_set_intfdata(intf, tp); 4333 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); 4334 4335 ret = register_netdev(netdev); 4336 if (ret != 0) { 4337 netif_err(tp, probe, netdev, "couldn't register the device\n"); 4338 goto out1; 4339 } 4340 4341 if (!rtl_can_wakeup(tp)) 4342 __rtl_set_wol(tp, 0); 4343 4344 tp->saved_wolopts = __rtl_get_wol(tp); 4345 if (tp->saved_wolopts) 4346 device_set_wakeup_enable(&udev->dev, true); 4347 else 4348 device_set_wakeup_enable(&udev->dev, false); 4349 4350 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 4351 4352 return 0; 4353 4354 out1: 4355 netif_napi_del(&tp->napi); 4356 usb_set_intfdata(intf, NULL); 4357 out: 4358 free_netdev(netdev); 4359 return ret; 4360 } 4361 4362 static void rtl8152_disconnect(struct usb_interface *intf) 4363 { 4364 struct r8152 *tp = usb_get_intfdata(intf); 4365 4366 usb_set_intfdata(intf, NULL); 4367 if (tp) { 4368 struct usb_device *udev = tp->udev; 4369 4370 if (udev->state == USB_STATE_NOTATTACHED) 4371 set_bit(RTL8152_UNPLUG, &tp->flags); 4372 4373 netif_napi_del(&tp->napi); 4374 unregister_netdev(tp->netdev); 4375 tp->rtl_ops.unload(tp); 4376 free_netdev(tp->netdev); 4377 } 4378 } 4379 4380 #define REALTEK_USB_DEVICE(vend, prod) \ 4381 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ 4382 USB_DEVICE_ID_MATCH_INT_CLASS, \ 4383 .idVendor = (vend), \ 4384 .idProduct = (prod), \ 4385 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ 4386 }, \ 4387 { \ 4388 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ 4389 USB_DEVICE_ID_MATCH_DEVICE, \ 4390 .idVendor = (vend), \ 4391 .idProduct = (prod), \ 4392 .bInterfaceClass = USB_CLASS_COMM, \ 4393 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ 4394 .bInterfaceProtocol = USB_CDC_PROTO_NONE 4395 4396 /* table of devices that work with this driver */ 4397 static struct usb_device_id rtl8152_table[] = { 4398 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, 4399 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, 4400 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, 4401 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, 4402 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, 4403 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, 4404 {} 4405 }; 4406 4407 MODULE_DEVICE_TABLE(usb, rtl8152_table); 4408 4409 static struct usb_driver rtl8152_driver = { 4410 .name = MODULENAME, 4411 .id_table = rtl8152_table, 4412 .probe = rtl8152_probe, 4413 .disconnect = rtl8152_disconnect, 4414 .suspend = rtl8152_suspend, 4415 .resume = rtl8152_resume, 4416 .reset_resume = rtl8152_reset_resume, 4417 .pre_reset = rtl8152_pre_reset, 4418 .post_reset = rtl8152_post_reset, 4419 .supports_autosuspend = 1, 4420 .disable_hub_initiated_lpm = 1, 4421 }; 4422 4423 module_usb_driver(rtl8152_driver); 4424 4425 MODULE_AUTHOR(DRIVER_AUTHOR); 4426 MODULE_DESCRIPTION(DRIVER_DESC); 4427 MODULE_LICENSE("GPL"); 4428 MODULE_VERSION(DRIVER_VERSION); 4429