xref: /openbmc/linux/drivers/net/usb/r8152.c (revision da94fb02)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4  */
5 
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
18 #include <linux/ip.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
29 #include <linux/usb/r8152.h>
30 #include <net/gso.h>
31 
32 /* Information for net-next */
33 #define NETNEXT_VERSION		"12"
34 
35 /* Information for net */
36 #define NET_VERSION		"13"
37 
38 #define DRIVER_VERSION		"v1." NETNEXT_VERSION "." NET_VERSION
39 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
40 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
41 #define MODULENAME "r8152"
42 
43 #define R8152_PHY_ID		32
44 
45 #define PLA_IDR			0xc000
46 #define PLA_RCR			0xc010
47 #define PLA_RCR1		0xc012
48 #define PLA_RMS			0xc016
49 #define PLA_RXFIFO_CTRL0	0xc0a0
50 #define PLA_RXFIFO_FULL		0xc0a2
51 #define PLA_RXFIFO_CTRL1	0xc0a4
52 #define PLA_RX_FIFO_FULL	0xc0a6
53 #define PLA_RXFIFO_CTRL2	0xc0a8
54 #define PLA_RX_FIFO_EMPTY	0xc0aa
55 #define PLA_DMY_REG0		0xc0b0
56 #define PLA_FMC			0xc0b4
57 #define PLA_CFG_WOL		0xc0b6
58 #define PLA_TEREDO_CFG		0xc0bc
59 #define PLA_TEREDO_WAKE_BASE	0xc0c4
60 #define PLA_MAR			0xcd00
61 #define PLA_BACKUP		0xd000
62 #define PLA_BDC_CR		0xd1a0
63 #define PLA_TEREDO_TIMER	0xd2cc
64 #define PLA_REALWOW_TIMER	0xd2e8
65 #define PLA_UPHY_TIMER		0xd388
66 #define PLA_SUSPEND_FLAG	0xd38a
67 #define PLA_INDICATE_FALG	0xd38c
68 #define PLA_MACDBG_PRE		0xd38c	/* RTL_VER_04 only */
69 #define PLA_MACDBG_POST		0xd38e	/* RTL_VER_04 only */
70 #define PLA_EXTRA_STATUS	0xd398
71 #define PLA_GPHY_CTRL		0xd3ae
72 #define PLA_POL_GPIO_CTRL	0xdc6a
73 #define PLA_EFUSE_DATA		0xdd00
74 #define PLA_EFUSE_CMD		0xdd02
75 #define PLA_LEDSEL		0xdd90
76 #define PLA_LED_FEATURE		0xdd92
77 #define PLA_PHYAR		0xde00
78 #define PLA_BOOT_CTRL		0xe004
79 #define PLA_LWAKE_CTRL_REG	0xe007
80 #define PLA_GPHY_INTR_IMR	0xe022
81 #define PLA_EEE_CR		0xe040
82 #define PLA_EEE_TXTWSYS		0xe04c
83 #define PLA_EEE_TXTWSYS_2P5G	0xe058
84 #define PLA_EEEP_CR		0xe080
85 #define PLA_MAC_PWR_CTRL	0xe0c0
86 #define PLA_MAC_PWR_CTRL2	0xe0ca
87 #define PLA_MAC_PWR_CTRL3	0xe0cc
88 #define PLA_MAC_PWR_CTRL4	0xe0ce
89 #define PLA_WDT6_CTRL		0xe428
90 #define PLA_TCR0		0xe610
91 #define PLA_TCR1		0xe612
92 #define PLA_MTPS		0xe615
93 #define PLA_TXFIFO_CTRL		0xe618
94 #define PLA_TXFIFO_FULL		0xe61a
95 #define PLA_RSTTALLY		0xe800
96 #define PLA_CR			0xe813
97 #define PLA_CRWECR		0xe81c
98 #define PLA_CONFIG12		0xe81e	/* CONFIG1, CONFIG2 */
99 #define PLA_CONFIG34		0xe820	/* CONFIG3, CONFIG4 */
100 #define PLA_CONFIG5		0xe822
101 #define PLA_PHY_PWR		0xe84c
102 #define PLA_OOB_CTRL		0xe84f
103 #define PLA_CPCR		0xe854
104 #define PLA_MISC_0		0xe858
105 #define PLA_MISC_1		0xe85a
106 #define PLA_OCP_GPHY_BASE	0xe86c
107 #define PLA_TALLYCNT		0xe890
108 #define PLA_SFF_STS_7		0xe8de
109 #define PLA_PHYSTATUS		0xe908
110 #define PLA_CONFIG6		0xe90a /* CONFIG6 */
111 #define PLA_USB_CFG		0xe952
112 #define PLA_BP_BA		0xfc26
113 #define PLA_BP_0		0xfc28
114 #define PLA_BP_1		0xfc2a
115 #define PLA_BP_2		0xfc2c
116 #define PLA_BP_3		0xfc2e
117 #define PLA_BP_4		0xfc30
118 #define PLA_BP_5		0xfc32
119 #define PLA_BP_6		0xfc34
120 #define PLA_BP_7		0xfc36
121 #define PLA_BP_EN		0xfc38
122 
123 #define USB_USB2PHY		0xb41e
124 #define USB_SSPHYLINK1		0xb426
125 #define USB_SSPHYLINK2		0xb428
126 #define USB_L1_CTRL		0xb45e
127 #define USB_U2P3_CTRL		0xb460
128 #define USB_CSR_DUMMY1		0xb464
129 #define USB_CSR_DUMMY2		0xb466
130 #define USB_DEV_STAT		0xb808
131 #define USB_CONNECT_TIMER	0xcbf8
132 #define USB_MSC_TIMER		0xcbfc
133 #define USB_BURST_SIZE		0xcfc0
134 #define USB_FW_FIX_EN0		0xcfca
135 #define USB_FW_FIX_EN1		0xcfcc
136 #define USB_LPM_CONFIG		0xcfd8
137 #define USB_ECM_OPTION		0xcfee
138 #define USB_CSTMR		0xcfef	/* RTL8153A */
139 #define USB_MISC_2		0xcfff
140 #define USB_ECM_OP		0xd26b
141 #define USB_GPHY_CTRL		0xd284
142 #define USB_SPEED_OPTION	0xd32a
143 #define USB_FW_CTRL		0xd334	/* RTL8153B */
144 #define USB_FC_TIMER		0xd340
145 #define USB_USB_CTRL		0xd406
146 #define USB_PHY_CTRL		0xd408
147 #define USB_TX_AGG		0xd40a
148 #define USB_RX_BUF_TH		0xd40c
149 #define USB_USB_TIMER		0xd428
150 #define USB_RX_EARLY_TIMEOUT	0xd42c
151 #define USB_RX_EARLY_SIZE	0xd42e
152 #define USB_PM_CTRL_STATUS	0xd432	/* RTL8153A */
153 #define USB_RX_EXTRA_AGGR_TMR	0xd432	/* RTL8153B */
154 #define USB_TX_DMA		0xd434
155 #define USB_UPT_RXDMA_OWN	0xd437
156 #define USB_UPHY3_MDCMDIO	0xd480
157 #define USB_TOLERANCE		0xd490
158 #define USB_LPM_CTRL		0xd41a
159 #define USB_BMU_RESET		0xd4b0
160 #define USB_BMU_CONFIG		0xd4b4
161 #define USB_U1U2_TIMER		0xd4da
162 #define USB_FW_TASK		0xd4e8	/* RTL8153B */
163 #define USB_RX_AGGR_NUM		0xd4ee
164 #define USB_UPS_CTRL		0xd800
165 #define USB_POWER_CUT		0xd80a
166 #define USB_MISC_0		0xd81a
167 #define USB_MISC_1		0xd81f
168 #define USB_AFE_CTRL2		0xd824
169 #define USB_UPHY_XTAL		0xd826
170 #define USB_UPS_CFG		0xd842
171 #define USB_UPS_FLAGS		0xd848
172 #define USB_WDT1_CTRL		0xe404
173 #define USB_WDT11_CTRL		0xe43c
174 #define USB_BP_BA		PLA_BP_BA
175 #define USB_BP_0		PLA_BP_0
176 #define USB_BP_1		PLA_BP_1
177 #define USB_BP_2		PLA_BP_2
178 #define USB_BP_3		PLA_BP_3
179 #define USB_BP_4		PLA_BP_4
180 #define USB_BP_5		PLA_BP_5
181 #define USB_BP_6		PLA_BP_6
182 #define USB_BP_7		PLA_BP_7
183 #define USB_BP_EN		PLA_BP_EN	/* RTL8153A */
184 #define USB_BP_8		0xfc38		/* RTL8153B */
185 #define USB_BP_9		0xfc3a
186 #define USB_BP_10		0xfc3c
187 #define USB_BP_11		0xfc3e
188 #define USB_BP_12		0xfc40
189 #define USB_BP_13		0xfc42
190 #define USB_BP_14		0xfc44
191 #define USB_BP_15		0xfc46
192 #define USB_BP2_EN		0xfc48
193 
194 /* OCP Registers */
195 #define OCP_ALDPS_CONFIG	0x2010
196 #define OCP_EEE_CONFIG1		0x2080
197 #define OCP_EEE_CONFIG2		0x2092
198 #define OCP_EEE_CONFIG3		0x2094
199 #define OCP_BASE_MII		0xa400
200 #define OCP_EEE_AR		0xa41a
201 #define OCP_EEE_DATA		0xa41c
202 #define OCP_PHY_STATUS		0xa420
203 #define OCP_INTR_EN		0xa424
204 #define OCP_NCTL_CFG		0xa42c
205 #define OCP_POWER_CFG		0xa430
206 #define OCP_EEE_CFG		0xa432
207 #define OCP_SRAM_ADDR		0xa436
208 #define OCP_SRAM_DATA		0xa438
209 #define OCP_DOWN_SPEED		0xa442
210 #define OCP_EEE_ABLE		0xa5c4
211 #define OCP_EEE_ADV		0xa5d0
212 #define OCP_EEE_LPABLE		0xa5d2
213 #define OCP_10GBT_CTRL		0xa5d4
214 #define OCP_10GBT_STAT		0xa5d6
215 #define OCP_EEE_ADV2		0xa6d4
216 #define OCP_PHY_STATE		0xa708		/* nway state for 8153 */
217 #define OCP_PHY_PATCH_STAT	0xb800
218 #define OCP_PHY_PATCH_CMD	0xb820
219 #define OCP_PHY_LOCK		0xb82e
220 #define OCP_ADC_IOFFSET		0xbcfc
221 #define OCP_ADC_CFG		0xbc06
222 #define OCP_SYSCLK_CFG		0xc416
223 
224 /* SRAM Register */
225 #define SRAM_GREEN_CFG		0x8011
226 #define SRAM_LPF_CFG		0x8012
227 #define SRAM_GPHY_FW_VER	0x801e
228 #define SRAM_10M_AMP1		0x8080
229 #define SRAM_10M_AMP2		0x8082
230 #define SRAM_IMPEDANCE		0x8084
231 #define SRAM_PHY_LOCK		0xb82e
232 
233 /* PLA_RCR */
234 #define RCR_AAP			0x00000001
235 #define RCR_APM			0x00000002
236 #define RCR_AM			0x00000004
237 #define RCR_AB			0x00000008
238 #define RCR_ACPT_ALL		(RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
239 #define SLOT_EN			BIT(11)
240 
241 /* PLA_RCR1 */
242 #define OUTER_VLAN		BIT(7)
243 #define INNER_VLAN		BIT(6)
244 
245 /* PLA_RXFIFO_CTRL0 */
246 #define RXFIFO_THR1_NORMAL	0x00080002
247 #define RXFIFO_THR1_OOB		0x01800003
248 
249 /* PLA_RXFIFO_FULL */
250 #define RXFIFO_FULL_MASK	0xfff
251 
252 /* PLA_RXFIFO_CTRL1 */
253 #define RXFIFO_THR2_FULL	0x00000060
254 #define RXFIFO_THR2_HIGH	0x00000038
255 #define RXFIFO_THR2_OOB		0x0000004a
256 #define RXFIFO_THR2_NORMAL	0x00a0
257 
258 /* PLA_RXFIFO_CTRL2 */
259 #define RXFIFO_THR3_FULL	0x00000078
260 #define RXFIFO_THR3_HIGH	0x00000048
261 #define RXFIFO_THR3_OOB		0x0000005a
262 #define RXFIFO_THR3_NORMAL	0x0110
263 
264 /* PLA_TXFIFO_CTRL */
265 #define TXFIFO_THR_NORMAL	0x00400008
266 #define TXFIFO_THR_NORMAL2	0x01000008
267 
268 /* PLA_DMY_REG0 */
269 #define ECM_ALDPS		0x0002
270 
271 /* PLA_FMC */
272 #define FMC_FCR_MCU_EN		0x0001
273 
274 /* PLA_EEEP_CR */
275 #define EEEP_CR_EEEP_TX		0x0002
276 
277 /* PLA_WDT6_CTRL */
278 #define WDT6_SET_MODE		0x0010
279 
280 /* PLA_TCR0 */
281 #define TCR0_TX_EMPTY		0x0800
282 #define TCR0_AUTO_FIFO		0x0080
283 
284 /* PLA_TCR1 */
285 #define VERSION_MASK		0x7cf0
286 #define IFG_MASK		(BIT(3) | BIT(9) | BIT(8))
287 #define IFG_144NS		BIT(9)
288 #define IFG_96NS		(BIT(9) | BIT(8))
289 
290 /* PLA_MTPS */
291 #define MTPS_JUMBO		(12 * 1024 / 64)
292 #define MTPS_DEFAULT		(6 * 1024 / 64)
293 
294 /* PLA_RSTTALLY */
295 #define TALLY_RESET		0x0001
296 
297 /* PLA_CR */
298 #define CR_RST			0x10
299 #define CR_RE			0x08
300 #define CR_TE			0x04
301 
302 /* PLA_CRWECR */
303 #define CRWECR_NORAML		0x00
304 #define CRWECR_CONFIG		0xc0
305 
306 /* PLA_OOB_CTRL */
307 #define NOW_IS_OOB		0x80
308 #define TXFIFO_EMPTY		0x20
309 #define RXFIFO_EMPTY		0x10
310 #define LINK_LIST_READY		0x02
311 #define DIS_MCU_CLROOB		0x01
312 #define FIFO_EMPTY		(TXFIFO_EMPTY | RXFIFO_EMPTY)
313 
314 /* PLA_MISC_1 */
315 #define RXDY_GATED_EN		0x0008
316 
317 /* PLA_SFF_STS_7 */
318 #define RE_INIT_LL		0x8000
319 #define MCU_BORW_EN		0x4000
320 
321 /* PLA_CPCR */
322 #define FLOW_CTRL_EN		BIT(0)
323 #define CPCR_RX_VLAN		0x0040
324 
325 /* PLA_CFG_WOL */
326 #define MAGIC_EN		0x0001
327 
328 /* PLA_TEREDO_CFG */
329 #define TEREDO_SEL		0x8000
330 #define TEREDO_WAKE_MASK	0x7f00
331 #define TEREDO_RS_EVENT_MASK	0x00fe
332 #define OOB_TEREDO_EN		0x0001
333 
334 /* PLA_BDC_CR */
335 #define ALDPS_PROXY_MODE	0x0001
336 
337 /* PLA_EFUSE_CMD */
338 #define EFUSE_READ_CMD		BIT(15)
339 #define EFUSE_DATA_BIT16	BIT(7)
340 
341 /* PLA_CONFIG34 */
342 #define LINK_ON_WAKE_EN		0x0010
343 #define LINK_OFF_WAKE_EN	0x0008
344 
345 /* PLA_CONFIG6 */
346 #define LANWAKE_CLR_EN		BIT(0)
347 
348 /* PLA_USB_CFG */
349 #define EN_XG_LIP		BIT(1)
350 #define EN_G_LIP		BIT(2)
351 
352 /* PLA_CONFIG5 */
353 #define BWF_EN			0x0040
354 #define MWF_EN			0x0020
355 #define UWF_EN			0x0010
356 #define LAN_WAKE_EN		0x0002
357 
358 /* PLA_LED_FEATURE */
359 #define LED_MODE_MASK		0x0700
360 
361 /* PLA_PHY_PWR */
362 #define TX_10M_IDLE_EN		0x0080
363 #define PFM_PWM_SWITCH		0x0040
364 #define TEST_IO_OFF		BIT(4)
365 
366 /* PLA_MAC_PWR_CTRL */
367 #define D3_CLK_GATED_EN		0x00004000
368 #define MCU_CLK_RATIO		0x07010f07
369 #define MCU_CLK_RATIO_MASK	0x0f0f0f0f
370 #define ALDPS_SPDWN_RATIO	0x0f87
371 
372 /* PLA_MAC_PWR_CTRL2 */
373 #define EEE_SPDWN_RATIO		0x8007
374 #define MAC_CLK_SPDWN_EN	BIT(15)
375 #define EEE_SPDWN_RATIO_MASK	0xff
376 
377 /* PLA_MAC_PWR_CTRL3 */
378 #define PLA_MCU_SPDWN_EN	BIT(14)
379 #define PKT_AVAIL_SPDWN_EN	0x0100
380 #define SUSPEND_SPDWN_EN	0x0004
381 #define U1U2_SPDWN_EN		0x0002
382 #define L1_SPDWN_EN		0x0001
383 
384 /* PLA_MAC_PWR_CTRL4 */
385 #define PWRSAVE_SPDWN_EN	0x1000
386 #define RXDV_SPDWN_EN		0x0800
387 #define TX10MIDLE_EN		0x0100
388 #define IDLE_SPDWN_EN		BIT(6)
389 #define TP100_SPDWN_EN		0x0020
390 #define TP500_SPDWN_EN		0x0010
391 #define TP1000_SPDWN_EN		0x0008
392 #define EEE_SPDWN_EN		0x0001
393 
394 /* PLA_GPHY_INTR_IMR */
395 #define GPHY_STS_MSK		0x0001
396 #define SPEED_DOWN_MSK		0x0002
397 #define SPDWN_RXDV_MSK		0x0004
398 #define SPDWN_LINKCHG_MSK	0x0008
399 
400 /* PLA_PHYAR */
401 #define PHYAR_FLAG		0x80000000
402 
403 /* PLA_EEE_CR */
404 #define EEE_RX_EN		0x0001
405 #define EEE_TX_EN		0x0002
406 
407 /* PLA_BOOT_CTRL */
408 #define AUTOLOAD_DONE		0x0002
409 
410 /* PLA_LWAKE_CTRL_REG */
411 #define LANWAKE_PIN		BIT(7)
412 
413 /* PLA_SUSPEND_FLAG */
414 #define LINK_CHG_EVENT		BIT(0)
415 
416 /* PLA_INDICATE_FALG */
417 #define UPCOMING_RUNTIME_D3	BIT(0)
418 
419 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
420 #define DEBUG_OE		BIT(0)
421 #define DEBUG_LTSSM		0x0082
422 
423 /* PLA_EXTRA_STATUS */
424 #define CUR_LINK_OK		BIT(15)
425 #define U3P3_CHECK_EN		BIT(7)	/* RTL_VER_05 only */
426 #define LINK_CHANGE_FLAG	BIT(8)
427 #define POLL_LINK_CHG		BIT(0)
428 
429 /* PLA_GPHY_CTRL */
430 #define GPHY_FLASH		BIT(1)
431 
432 /* PLA_POL_GPIO_CTRL */
433 #define DACK_DET_EN		BIT(15)
434 #define POL_GPHY_PATCH		BIT(4)
435 
436 /* USB_USB2PHY */
437 #define USB2PHY_SUSPEND		0x0001
438 #define USB2PHY_L1		0x0002
439 
440 /* USB_SSPHYLINK1 */
441 #define DELAY_PHY_PWR_CHG	BIT(1)
442 
443 /* USB_SSPHYLINK2 */
444 #define pwd_dn_scale_mask	0x3ffe
445 #define pwd_dn_scale(x)		((x) << 1)
446 
447 /* USB_CSR_DUMMY1 */
448 #define DYNAMIC_BURST		0x0001
449 
450 /* USB_CSR_DUMMY2 */
451 #define EP4_FULL_FC		0x0001
452 
453 /* USB_DEV_STAT */
454 #define STAT_SPEED_MASK		0x0006
455 #define STAT_SPEED_HIGH		0x0000
456 #define STAT_SPEED_FULL		0x0002
457 
458 /* USB_FW_FIX_EN0 */
459 #define FW_FIX_SUSPEND		BIT(14)
460 
461 /* USB_FW_FIX_EN1 */
462 #define FW_IP_RESET_EN		BIT(9)
463 
464 /* USB_LPM_CONFIG */
465 #define LPM_U1U2_EN		BIT(0)
466 
467 /* USB_TX_AGG */
468 #define TX_AGG_MAX_THRESHOLD	0x03
469 
470 /* USB_RX_BUF_TH */
471 #define RX_THR_SUPPER		0x0c350180
472 #define RX_THR_HIGH		0x7a120180
473 #define RX_THR_SLOW		0xffff0180
474 #define RX_THR_B		0x00010001
475 
476 /* USB_TX_DMA */
477 #define TEST_MODE_DISABLE	0x00000001
478 #define TX_SIZE_ADJUST1		0x00000100
479 
480 /* USB_BMU_RESET */
481 #define BMU_RESET_EP_IN		0x01
482 #define BMU_RESET_EP_OUT	0x02
483 
484 /* USB_BMU_CONFIG */
485 #define ACT_ODMA		BIT(1)
486 
487 /* USB_UPT_RXDMA_OWN */
488 #define OWN_UPDATE		BIT(0)
489 #define OWN_CLEAR		BIT(1)
490 
491 /* USB_FW_TASK */
492 #define FC_PATCH_TASK		BIT(1)
493 
494 /* USB_RX_AGGR_NUM */
495 #define RX_AGGR_NUM_MASK	0x1ff
496 
497 /* USB_UPS_CTRL */
498 #define POWER_CUT		0x0100
499 
500 /* USB_PM_CTRL_STATUS */
501 #define RESUME_INDICATE		0x0001
502 
503 /* USB_ECM_OPTION */
504 #define BYPASS_MAC_RESET	BIT(5)
505 
506 /* USB_CSTMR */
507 #define FORCE_SUPER		BIT(0)
508 
509 /* USB_MISC_2 */
510 #define UPS_FORCE_PWR_DOWN	BIT(0)
511 
512 /* USB_ECM_OP */
513 #define	EN_ALL_SPEED		BIT(0)
514 
515 /* USB_GPHY_CTRL */
516 #define GPHY_PATCH_DONE		BIT(2)
517 #define BYPASS_FLASH		BIT(5)
518 #define BACKUP_RESTRORE		BIT(6)
519 
520 /* USB_SPEED_OPTION */
521 #define RG_PWRDN_EN		BIT(8)
522 #define ALL_SPEED_OFF		BIT(9)
523 
524 /* USB_FW_CTRL */
525 #define FLOW_CTRL_PATCH_OPT	BIT(1)
526 #define AUTO_SPEEDUP		BIT(3)
527 #define FLOW_CTRL_PATCH_2	BIT(8)
528 
529 /* USB_FC_TIMER */
530 #define CTRL_TIMER_EN		BIT(15)
531 
532 /* USB_USB_CTRL */
533 #define CDC_ECM_EN		BIT(3)
534 #define RX_AGG_DISABLE		0x0010
535 #define RX_ZERO_EN		0x0080
536 
537 /* USB_U2P3_CTRL */
538 #define U2P3_ENABLE		0x0001
539 #define RX_DETECT8		BIT(3)
540 
541 /* USB_POWER_CUT */
542 #define PWR_EN			0x0001
543 #define PHASE2_EN		0x0008
544 #define UPS_EN			BIT(4)
545 #define USP_PREWAKE		BIT(5)
546 
547 /* USB_MISC_0 */
548 #define PCUT_STATUS		0x0001
549 
550 /* USB_RX_EARLY_TIMEOUT */
551 #define COALESCE_SUPER		 85000U
552 #define COALESCE_HIGH		250000U
553 #define COALESCE_SLOW		524280U
554 
555 /* USB_WDT1_CTRL */
556 #define WTD1_EN			BIT(0)
557 
558 /* USB_WDT11_CTRL */
559 #define TIMER11_EN		0x0001
560 
561 /* USB_LPM_CTRL */
562 /* bit 4 ~ 5: fifo empty boundary */
563 #define FIFO_EMPTY_1FB		0x30	/* 0x1fb * 64 = 32448 bytes */
564 /* bit 2 ~ 3: LMP timer */
565 #define LPM_TIMER_MASK		0x0c
566 #define LPM_TIMER_500MS		0x04	/* 500 ms */
567 #define LPM_TIMER_500US		0x0c	/* 500 us */
568 #define ROK_EXIT_LPM		0x02
569 
570 /* USB_AFE_CTRL2 */
571 #define SEN_VAL_MASK		0xf800
572 #define SEN_VAL_NORMAL		0xa000
573 #define SEL_RXIDLE		0x0100
574 
575 /* USB_UPHY_XTAL */
576 #define OOBS_POLLING		BIT(8)
577 
578 /* USB_UPS_CFG */
579 #define SAW_CNT_1MS_MASK	0x0fff
580 #define MID_REVERSE		BIT(5)	/* RTL8156A */
581 
582 /* USB_UPS_FLAGS */
583 #define UPS_FLAGS_R_TUNE		BIT(0)
584 #define UPS_FLAGS_EN_10M_CKDIV		BIT(1)
585 #define UPS_FLAGS_250M_CKDIV		BIT(2)
586 #define UPS_FLAGS_EN_ALDPS		BIT(3)
587 #define UPS_FLAGS_CTAP_SHORT_DIS	BIT(4)
588 #define UPS_FLAGS_SPEED_MASK		(0xf << 16)
589 #define ups_flags_speed(x)		((x) << 16)
590 #define UPS_FLAGS_EN_EEE		BIT(20)
591 #define UPS_FLAGS_EN_500M_EEE		BIT(21)
592 #define UPS_FLAGS_EN_EEE_CKDIV		BIT(22)
593 #define UPS_FLAGS_EEE_PLLOFF_100	BIT(23)
594 #define UPS_FLAGS_EEE_PLLOFF_GIGA	BIT(24)
595 #define UPS_FLAGS_EEE_CMOD_LV_EN	BIT(25)
596 #define UPS_FLAGS_EN_GREEN		BIT(26)
597 #define UPS_FLAGS_EN_FLOW_CTR		BIT(27)
598 
599 enum spd_duplex {
600 	NWAY_10M_HALF,
601 	NWAY_10M_FULL,
602 	NWAY_100M_HALF,
603 	NWAY_100M_FULL,
604 	NWAY_1000M_FULL,
605 	FORCE_10M_HALF,
606 	FORCE_10M_FULL,
607 	FORCE_100M_HALF,
608 	FORCE_100M_FULL,
609 	FORCE_1000M_FULL,
610 	NWAY_2500M_FULL,
611 };
612 
613 /* OCP_ALDPS_CONFIG */
614 #define ENPWRSAVE		0x8000
615 #define ENPDNPS			0x0200
616 #define LINKENA			0x0100
617 #define DIS_SDSAVE		0x0010
618 
619 /* OCP_PHY_STATUS */
620 #define PHY_STAT_MASK		0x0007
621 #define PHY_STAT_EXT_INIT	2
622 #define PHY_STAT_LAN_ON		3
623 #define PHY_STAT_PWRDN		5
624 
625 /* OCP_INTR_EN */
626 #define INTR_SPEED_FORCE	BIT(3)
627 
628 /* OCP_NCTL_CFG */
629 #define PGA_RETURN_EN		BIT(1)
630 
631 /* OCP_POWER_CFG */
632 #define EEE_CLKDIV_EN		0x8000
633 #define EN_ALDPS		0x0004
634 #define EN_10M_PLLOFF		0x0001
635 
636 /* OCP_EEE_CONFIG1 */
637 #define RG_TXLPI_MSK_HFDUP	0x8000
638 #define RG_MATCLR_EN		0x4000
639 #define EEE_10_CAP		0x2000
640 #define EEE_NWAY_EN		0x1000
641 #define TX_QUIET_EN		0x0200
642 #define RX_QUIET_EN		0x0100
643 #define sd_rise_time_mask	0x0070
644 #define sd_rise_time(x)		(min(x, 7) << 4)	/* bit 4 ~ 6 */
645 #define RG_RXLPI_MSK_HFDUP	0x0008
646 #define SDFALLTIME		0x0007	/* bit 0 ~ 2 */
647 
648 /* OCP_EEE_CONFIG2 */
649 #define RG_LPIHYS_NUM		0x7000	/* bit 12 ~ 15 */
650 #define RG_DACQUIET_EN		0x0400
651 #define RG_LDVQUIET_EN		0x0200
652 #define RG_CKRSEL		0x0020
653 #define RG_EEEPRG_EN		0x0010
654 
655 /* OCP_EEE_CONFIG3 */
656 #define fast_snr_mask		0xff80
657 #define fast_snr(x)		(min(x, 0x1ff) << 7)	/* bit 7 ~ 15 */
658 #define RG_LFS_SEL		0x0060	/* bit 6 ~ 5 */
659 #define MSK_PH			0x0006	/* bit 0 ~ 3 */
660 
661 /* OCP_EEE_AR */
662 /* bit[15:14] function */
663 #define FUN_ADDR		0x0000
664 #define FUN_DATA		0x4000
665 /* bit[4:0] device addr */
666 
667 /* OCP_EEE_CFG */
668 #define CTAP_SHORT_EN		0x0040
669 #define EEE10_EN		0x0010
670 
671 /* OCP_DOWN_SPEED */
672 #define EN_EEE_CMODE		BIT(14)
673 #define EN_EEE_1000		BIT(13)
674 #define EN_EEE_100		BIT(12)
675 #define EN_10M_CLKDIV		BIT(11)
676 #define EN_10M_BGOFF		0x0080
677 
678 /* OCP_10GBT_CTRL */
679 #define RTL_ADV2_5G_F_R		BIT(5)	/* Advertise 2.5GBASE-T fast-retrain */
680 
681 /* OCP_PHY_STATE */
682 #define TXDIS_STATE		0x01
683 #define ABD_STATE		0x02
684 
685 /* OCP_PHY_PATCH_STAT */
686 #define PATCH_READY		BIT(6)
687 
688 /* OCP_PHY_PATCH_CMD */
689 #define PATCH_REQUEST		BIT(4)
690 
691 /* OCP_PHY_LOCK */
692 #define PATCH_LOCK		BIT(0)
693 
694 /* OCP_ADC_CFG */
695 #define CKADSEL_L		0x0100
696 #define ADC_EN			0x0080
697 #define EN_EMI_L		0x0040
698 
699 /* OCP_SYSCLK_CFG */
700 #define sysclk_div_expo(x)	(min(x, 5) << 8)
701 #define clk_div_expo(x)		(min(x, 5) << 4)
702 
703 /* SRAM_GREEN_CFG */
704 #define GREEN_ETH_EN		BIT(15)
705 #define R_TUNE_EN		BIT(11)
706 
707 /* SRAM_LPF_CFG */
708 #define LPF_AUTO_TUNE		0x8000
709 
710 /* SRAM_10M_AMP1 */
711 #define GDAC_IB_UPALL		0x0008
712 
713 /* SRAM_10M_AMP2 */
714 #define AMP_DN			0x0200
715 
716 /* SRAM_IMPEDANCE */
717 #define RX_DRIVING_MASK		0x6000
718 
719 /* SRAM_PHY_LOCK */
720 #define PHY_PATCH_LOCK		0x0001
721 
722 /* MAC PASSTHRU */
723 #define AD_MASK			0xfee0
724 #define BND_MASK		0x0004
725 #define BD_MASK			0x0001
726 #define EFUSE			0xcfdb
727 #define PASS_THRU_MASK		0x1
728 
729 #define BP4_SUPER_ONLY		0x1578	/* RTL_VER_04 only */
730 
731 enum rtl_register_content {
732 	_2500bps	= BIT(10),
733 	_1250bps	= BIT(9),
734 	_500bps		= BIT(8),
735 	_tx_flow	= BIT(6),
736 	_rx_flow	= BIT(5),
737 	_1000bps	= 0x10,
738 	_100bps		= 0x08,
739 	_10bps		= 0x04,
740 	LINK_STATUS	= 0x02,
741 	FULL_DUP	= 0x01,
742 };
743 
744 #define is_speed_2500(_speed)	(((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
745 #define is_flow_control(_speed)	(((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
746 
747 #define RTL8152_MAX_TX		4
748 #define RTL8152_MAX_RX		10
749 #define INTBUFSIZE		2
750 #define TX_ALIGN		4
751 #define RX_ALIGN		8
752 
753 #define RTL8152_RX_MAX_PENDING	4096
754 #define RTL8152_RXFG_HEADSZ	256
755 
756 #define INTR_LINK		0x0004
757 
758 #define RTL8152_RMS		(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
759 #define RTL8153_RMS		RTL8153_MAX_PACKET
760 #define RTL8152_TX_TIMEOUT	(5 * HZ)
761 #define mtu_to_size(m)		((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
762 #define size_to_mtu(s)		((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
763 #define rx_reserved_size(x)	(mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
764 
765 /* rtl8152 flags */
766 enum rtl8152_flags {
767 	RTL8152_INACCESSIBLE = 0,
768 	RTL8152_SET_RX_MODE,
769 	WORK_ENABLE,
770 	RTL8152_LINK_CHG,
771 	SELECTIVE_SUSPEND,
772 	PHY_RESET,
773 	SCHEDULE_TASKLET,
774 	GREEN_ETHERNET,
775 	RX_EPROTO,
776 	IN_PRE_RESET,
777 	PROBED_WITH_NO_ERRORS,
778 	PROBE_SHOULD_RETRY,
779 };
780 
781 #define DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB		0x721e
782 #define DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK		0x3054
783 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2	0x3082
784 #define DEVICE_ID_THINKPAD_USB_C_DONGLE			0x720c
785 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2		0xa387
786 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3		0x3062
787 
788 struct tally_counter {
789 	__le64	tx_packets;
790 	__le64	rx_packets;
791 	__le64	tx_errors;
792 	__le32	rx_errors;
793 	__le16	rx_missed;
794 	__le16	align_errors;
795 	__le32	tx_one_collision;
796 	__le32	tx_multi_collision;
797 	__le64	rx_unicast;
798 	__le64	rx_broadcast;
799 	__le32	rx_multicast;
800 	__le16	tx_aborted;
801 	__le16	tx_underrun;
802 };
803 
804 struct rx_desc {
805 	__le32 opts1;
806 #define RX_LEN_MASK			0x7fff
807 
808 	__le32 opts2;
809 #define RD_UDP_CS			BIT(23)
810 #define RD_TCP_CS			BIT(22)
811 #define RD_IPV6_CS			BIT(20)
812 #define RD_IPV4_CS			BIT(19)
813 
814 	__le32 opts3;
815 #define IPF				BIT(23) /* IP checksum fail */
816 #define UDPF				BIT(22) /* UDP checksum fail */
817 #define TCPF				BIT(21) /* TCP checksum fail */
818 #define RX_VLAN_TAG			BIT(16)
819 
820 	__le32 opts4;
821 	__le32 opts5;
822 	__le32 opts6;
823 };
824 
825 struct tx_desc {
826 	__le32 opts1;
827 #define TX_FS			BIT(31) /* First segment of a packet */
828 #define TX_LS			BIT(30) /* Final segment of a packet */
829 #define GTSENDV4		BIT(28)
830 #define GTSENDV6		BIT(27)
831 #define GTTCPHO_SHIFT		18
832 #define GTTCPHO_MAX		0x7fU
833 #define TX_LEN_MAX		0x3ffffU
834 
835 	__le32 opts2;
836 #define UDP_CS			BIT(31) /* Calculate UDP/IP checksum */
837 #define TCP_CS			BIT(30) /* Calculate TCP/IP checksum */
838 #define IPV4_CS			BIT(29) /* Calculate IPv4 checksum */
839 #define IPV6_CS			BIT(28) /* Calculate IPv6 checksum */
840 #define MSS_SHIFT		17
841 #define MSS_MAX			0x7ffU
842 #define TCPHO_SHIFT		17
843 #define TCPHO_MAX		0x7ffU
844 #define TX_VLAN_TAG		BIT(16)
845 };
846 
847 struct r8152;
848 
849 struct rx_agg {
850 	struct list_head list, info_list;
851 	struct urb *urb;
852 	struct r8152 *context;
853 	struct page *page;
854 	void *buffer;
855 };
856 
857 struct tx_agg {
858 	struct list_head list;
859 	struct urb *urb;
860 	struct r8152 *context;
861 	void *buffer;
862 	void *head;
863 	u32 skb_num;
864 	u32 skb_len;
865 };
866 
867 struct r8152 {
868 	unsigned long flags;
869 	struct usb_device *udev;
870 	struct napi_struct napi;
871 	struct usb_interface *intf;
872 	struct net_device *netdev;
873 	struct urb *intr_urb;
874 	struct tx_agg tx_info[RTL8152_MAX_TX];
875 	struct list_head rx_info, rx_used;
876 	struct list_head rx_done, tx_free;
877 	struct sk_buff_head tx_queue, rx_queue;
878 	spinlock_t rx_lock, tx_lock;
879 	struct delayed_work schedule, hw_phy_work;
880 	struct mii_if_info mii;
881 	struct mutex control;	/* use for hw setting */
882 #ifdef CONFIG_PM_SLEEP
883 	struct notifier_block pm_notifier;
884 #endif
885 	struct tasklet_struct tx_tl;
886 
887 	struct rtl_ops {
888 		void (*init)(struct r8152 *tp);
889 		int (*enable)(struct r8152 *tp);
890 		void (*disable)(struct r8152 *tp);
891 		void (*up)(struct r8152 *tp);
892 		void (*down)(struct r8152 *tp);
893 		void (*unload)(struct r8152 *tp);
894 		int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
895 		int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
896 		bool (*in_nway)(struct r8152 *tp);
897 		void (*hw_phy_cfg)(struct r8152 *tp);
898 		void (*autosuspend_en)(struct r8152 *tp, bool enable);
899 		void (*change_mtu)(struct r8152 *tp);
900 	} rtl_ops;
901 
902 	struct ups_info {
903 		u32 r_tune:1;
904 		u32 _10m_ckdiv:1;
905 		u32 _250m_ckdiv:1;
906 		u32 aldps:1;
907 		u32 lite_mode:2;
908 		u32 speed_duplex:4;
909 		u32 eee:1;
910 		u32 eee_lite:1;
911 		u32 eee_ckdiv:1;
912 		u32 eee_plloff_100:1;
913 		u32 eee_plloff_giga:1;
914 		u32 eee_cmod_lv:1;
915 		u32 green:1;
916 		u32 flow_control:1;
917 		u32 ctap_short_off:1;
918 	} ups_info;
919 
920 #define RTL_VER_SIZE		32
921 
922 	struct rtl_fw {
923 		const char *fw_name;
924 		const struct firmware *fw;
925 
926 		char version[RTL_VER_SIZE];
927 		int (*pre_fw)(struct r8152 *tp);
928 		int (*post_fw)(struct r8152 *tp);
929 
930 		bool retry;
931 	} rtl_fw;
932 
933 	atomic_t rx_count;
934 
935 	bool eee_en;
936 	int intr_interval;
937 	u32 saved_wolopts;
938 	u32 msg_enable;
939 	u32 tx_qlen;
940 	u32 coalesce;
941 	u32 advertising;
942 	u32 rx_buf_sz;
943 	u32 rx_copybreak;
944 	u32 rx_pending;
945 	u32 fc_pause_on, fc_pause_off;
946 
947 	unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out;
948 
949 	u32 support_2500full:1;
950 	u32 lenovo_macpassthru:1;
951 	u32 dell_tb_rx_agg_bug:1;
952 	u16 ocp_base;
953 	u16 speed;
954 	u16 eee_adv;
955 	u8 *intr_buff;
956 	u8 version;
957 	u8 duplex;
958 	u8 autoneg;
959 
960 	unsigned int reg_access_reset_count;
961 };
962 
963 /**
964  * struct fw_block - block type and total length
965  * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
966  *	RTL_FW_USB and so on.
967  * @length: total length of the current block.
968  */
969 struct fw_block {
970 	__le32 type;
971 	__le32 length;
972 } __packed;
973 
974 /**
975  * struct fw_header - header of the firmware file
976  * @checksum: checksum of sha256 which is calculated from the whole file
977  *	except the checksum field of the file. That is, calculate sha256
978  *	from the version field to the end of the file.
979  * @version: version of this firmware.
980  * @blocks: the first firmware block of the file
981  */
982 struct fw_header {
983 	u8 checksum[32];
984 	char version[RTL_VER_SIZE];
985 	struct fw_block blocks[];
986 } __packed;
987 
988 enum rtl8152_fw_flags {
989 	FW_FLAGS_USB = 0,
990 	FW_FLAGS_PLA,
991 	FW_FLAGS_START,
992 	FW_FLAGS_STOP,
993 	FW_FLAGS_NC,
994 	FW_FLAGS_NC1,
995 	FW_FLAGS_NC2,
996 	FW_FLAGS_UC2,
997 	FW_FLAGS_UC,
998 	FW_FLAGS_SPEED_UP,
999 	FW_FLAGS_VER,
1000 };
1001 
1002 enum rtl8152_fw_fixup_cmd {
1003 	FW_FIXUP_AND = 0,
1004 	FW_FIXUP_OR,
1005 	FW_FIXUP_NOT,
1006 	FW_FIXUP_XOR,
1007 };
1008 
1009 struct fw_phy_set {
1010 	__le16 addr;
1011 	__le16 data;
1012 } __packed;
1013 
1014 struct fw_phy_speed_up {
1015 	struct fw_block blk_hdr;
1016 	__le16 fw_offset;
1017 	__le16 version;
1018 	__le16 fw_reg;
1019 	__le16 reserved;
1020 	char info[];
1021 } __packed;
1022 
1023 struct fw_phy_ver {
1024 	struct fw_block blk_hdr;
1025 	struct fw_phy_set ver;
1026 	__le32 reserved;
1027 } __packed;
1028 
1029 struct fw_phy_fixup {
1030 	struct fw_block blk_hdr;
1031 	struct fw_phy_set setting;
1032 	__le16 bit_cmd;
1033 	__le16 reserved;
1034 } __packed;
1035 
1036 struct fw_phy_union {
1037 	struct fw_block blk_hdr;
1038 	__le16 fw_offset;
1039 	__le16 fw_reg;
1040 	struct fw_phy_set pre_set[2];
1041 	struct fw_phy_set bp[8];
1042 	struct fw_phy_set bp_en;
1043 	u8 pre_num;
1044 	u8 bp_num;
1045 	char info[];
1046 } __packed;
1047 
1048 /**
1049  * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
1050  *	The layout of the firmware block is:
1051  *	<struct fw_mac> + <info> + <firmware data>.
1052  * @blk_hdr: firmware descriptor (type, length)
1053  * @fw_offset: offset of the firmware binary data. The start address of
1054  *	the data would be the address of struct fw_mac + @fw_offset.
1055  * @fw_reg: the register to load the firmware. Depends on chip.
1056  * @bp_ba_addr: the register to write break point base address. Depends on
1057  *	chip.
1058  * @bp_ba_value: break point base address. Depends on chip.
1059  * @bp_en_addr: the register to write break point enabled mask. Depends
1060  *	on chip.
1061  * @bp_en_value: break point enabled mask. Depends on the firmware.
1062  * @bp_start: the start register of break points. Depends on chip.
1063  * @bp_num: the break point number which needs to be set for this firmware.
1064  *	Depends on the firmware.
1065  * @bp: break points. Depends on firmware.
1066  * @reserved: reserved space (unused)
1067  * @fw_ver_reg: the register to store the fw version.
1068  * @fw_ver_data: the firmware version of the current type.
1069  * @info: additional information for debugging, and is followed by the
1070  *	binary data of firmware.
1071  */
1072 struct fw_mac {
1073 	struct fw_block blk_hdr;
1074 	__le16 fw_offset;
1075 	__le16 fw_reg;
1076 	__le16 bp_ba_addr;
1077 	__le16 bp_ba_value;
1078 	__le16 bp_en_addr;
1079 	__le16 bp_en_value;
1080 	__le16 bp_start;
1081 	__le16 bp_num;
1082 	__le16 bp[16]; /* any value determined by firmware */
1083 	__le32 reserved;
1084 	__le16 fw_ver_reg;
1085 	u8 fw_ver_data;
1086 	char info[];
1087 } __packed;
1088 
1089 /**
1090  * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
1091  *	This is used to set patch key when loading the firmware of PHY.
1092  * @blk_hdr: firmware descriptor (type, length)
1093  * @key_reg: the register to write the patch key.
1094  * @key_data: patch key.
1095  * @reserved: reserved space (unused)
1096  */
1097 struct fw_phy_patch_key {
1098 	struct fw_block blk_hdr;
1099 	__le16 key_reg;
1100 	__le16 key_data;
1101 	__le32 reserved;
1102 } __packed;
1103 
1104 /**
1105  * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
1106  *	The layout of the firmware block is:
1107  *	<struct fw_phy_nc> + <info> + <firmware data>.
1108  * @blk_hdr: firmware descriptor (type, length)
1109  * @fw_offset: offset of the firmware binary data. The start address of
1110  *	the data would be the address of struct fw_phy_nc + @fw_offset.
1111  * @fw_reg: the register to load the firmware. Depends on chip.
1112  * @ba_reg: the register to write the base address. Depends on chip.
1113  * @ba_data: base address. Depends on chip.
1114  * @patch_en_addr: the register of enabling patch mode. Depends on chip.
1115  * @patch_en_value: patch mode enabled mask. Depends on the firmware.
1116  * @mode_reg: the regitster of switching the mode.
1117  * @mode_pre: the mode needing to be set before loading the firmware.
1118  * @mode_post: the mode to be set when finishing to load the firmware.
1119  * @reserved: reserved space (unused)
1120  * @bp_start: the start register of break points. Depends on chip.
1121  * @bp_num: the break point number which needs to be set for this firmware.
1122  *	Depends on the firmware.
1123  * @bp: break points. Depends on firmware.
1124  * @info: additional information for debugging, and is followed by the
1125  *	binary data of firmware.
1126  */
1127 struct fw_phy_nc {
1128 	struct fw_block blk_hdr;
1129 	__le16 fw_offset;
1130 	__le16 fw_reg;
1131 	__le16 ba_reg;
1132 	__le16 ba_data;
1133 	__le16 patch_en_addr;
1134 	__le16 patch_en_value;
1135 	__le16 mode_reg;
1136 	__le16 mode_pre;
1137 	__le16 mode_post;
1138 	__le16 reserved;
1139 	__le16 bp_start;
1140 	__le16 bp_num;
1141 	__le16 bp[4];
1142 	char info[];
1143 } __packed;
1144 
1145 enum rtl_fw_type {
1146 	RTL_FW_END = 0,
1147 	RTL_FW_PLA,
1148 	RTL_FW_USB,
1149 	RTL_FW_PHY_START,
1150 	RTL_FW_PHY_STOP,
1151 	RTL_FW_PHY_NC,
1152 	RTL_FW_PHY_FIXUP,
1153 	RTL_FW_PHY_UNION_NC,
1154 	RTL_FW_PHY_UNION_NC1,
1155 	RTL_FW_PHY_UNION_NC2,
1156 	RTL_FW_PHY_UNION_UC2,
1157 	RTL_FW_PHY_UNION_UC,
1158 	RTL_FW_PHY_UNION_MISC,
1159 	RTL_FW_PHY_SPEED_UP,
1160 	RTL_FW_PHY_VER,
1161 };
1162 
1163 enum rtl_version {
1164 	RTL_VER_UNKNOWN = 0,
1165 	RTL_VER_01,
1166 	RTL_VER_02,
1167 	RTL_VER_03,
1168 	RTL_VER_04,
1169 	RTL_VER_05,
1170 	RTL_VER_06,
1171 	RTL_VER_07,
1172 	RTL_VER_08,
1173 	RTL_VER_09,
1174 
1175 	RTL_TEST_01,
1176 	RTL_VER_10,
1177 	RTL_VER_11,
1178 	RTL_VER_12,
1179 	RTL_VER_13,
1180 	RTL_VER_14,
1181 	RTL_VER_15,
1182 
1183 	RTL_VER_MAX
1184 };
1185 
1186 enum tx_csum_stat {
1187 	TX_CSUM_SUCCESS = 0,
1188 	TX_CSUM_TSO,
1189 	TX_CSUM_NONE
1190 };
1191 
1192 #define RTL_ADVERTISED_10_HALF			BIT(0)
1193 #define RTL_ADVERTISED_10_FULL			BIT(1)
1194 #define RTL_ADVERTISED_100_HALF			BIT(2)
1195 #define RTL_ADVERTISED_100_FULL			BIT(3)
1196 #define RTL_ADVERTISED_1000_HALF		BIT(4)
1197 #define RTL_ADVERTISED_1000_FULL		BIT(5)
1198 #define RTL_ADVERTISED_2500_FULL		BIT(6)
1199 
1200 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1201  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1202  */
1203 static const int multicast_filter_limit = 32;
1204 static unsigned int agg_buf_sz = 16384;
1205 
1206 #define RTL_LIMITED_TSO_SIZE	(size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc))
1207 
1208 /* If register access fails then we block access and issue a reset. If this
1209  * happens too many times in a row without a successful access then we stop
1210  * trying to reset and just leave access blocked.
1211  */
1212 #define REGISTER_ACCESS_MAX_RESETS	3
1213 
1214 static void rtl_set_inaccessible(struct r8152 *tp)
1215 {
1216 	set_bit(RTL8152_INACCESSIBLE, &tp->flags);
1217 	smp_mb__after_atomic();
1218 }
1219 
1220 static void rtl_set_accessible(struct r8152 *tp)
1221 {
1222 	clear_bit(RTL8152_INACCESSIBLE, &tp->flags);
1223 	smp_mb__after_atomic();
1224 }
1225 
1226 static
1227 int r8152_control_msg(struct r8152 *tp, unsigned int pipe, __u8 request,
1228 		      __u8 requesttype, __u16 value, __u16 index, void *data,
1229 		      __u16 size, const char *msg_tag)
1230 {
1231 	struct usb_device *udev = tp->udev;
1232 	int ret;
1233 
1234 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1235 		return -ENODEV;
1236 
1237 	ret = usb_control_msg(udev, pipe, request, requesttype,
1238 			      value, index, data, size,
1239 			      USB_CTRL_GET_TIMEOUT);
1240 
1241 	/* No need to issue a reset to report an error if the USB device got
1242 	 * unplugged; just return immediately.
1243 	 */
1244 	if (ret == -ENODEV)
1245 		return ret;
1246 
1247 	/* If the write was successful then we're done */
1248 	if (ret >= 0) {
1249 		tp->reg_access_reset_count = 0;
1250 		return ret;
1251 	}
1252 
1253 	dev_err(&udev->dev,
1254 		"Failed to %s %d bytes at %#06x/%#06x (%d)\n",
1255 		msg_tag, size, value, index, ret);
1256 
1257 	/* Block all future register access until we reset. Much of the code
1258 	 * in the driver doesn't check for errors. Notably, many parts of the
1259 	 * driver do a read/modify/write of a register value without
1260 	 * confirming that the read succeeded. Writing back modified garbage
1261 	 * like this can fully wedge the adapter, requiring a power cycle.
1262 	 */
1263 	rtl_set_inaccessible(tp);
1264 
1265 	/* If probe hasn't yet finished, then we'll request a retry of the
1266 	 * whole probe routine if we get any control transfer errors. We
1267 	 * never have to clear this bit since we free/reallocate the whole "tp"
1268 	 * structure if we retry probe.
1269 	 */
1270 	if (!test_bit(PROBED_WITH_NO_ERRORS, &tp->flags)) {
1271 		set_bit(PROBE_SHOULD_RETRY, &tp->flags);
1272 		return ret;
1273 	}
1274 
1275 	/* Failing to access registers in pre-reset is not surprising since we
1276 	 * wouldn't be resetting if things were behaving normally. The register
1277 	 * access we do in pre-reset isn't truly mandatory--we're just reusing
1278 	 * the disable() function and trying to be nice by powering the
1279 	 * adapter down before resetting it. Thus, if we're in pre-reset,
1280 	 * we'll return right away and not try to queue up yet another reset.
1281 	 * We know the post-reset is already coming.
1282 	 */
1283 	if (test_bit(IN_PRE_RESET, &tp->flags))
1284 		return ret;
1285 
1286 	if (tp->reg_access_reset_count < REGISTER_ACCESS_MAX_RESETS) {
1287 		usb_queue_reset_device(tp->intf);
1288 		tp->reg_access_reset_count++;
1289 	} else if (tp->reg_access_reset_count == REGISTER_ACCESS_MAX_RESETS) {
1290 		dev_err(&udev->dev,
1291 			"Tried to reset %d times; giving up.\n",
1292 			REGISTER_ACCESS_MAX_RESETS);
1293 	}
1294 
1295 	return ret;
1296 }
1297 
1298 static
1299 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1300 {
1301 	int ret;
1302 	void *tmp;
1303 
1304 	tmp = kmalloc(size, GFP_KERNEL);
1305 	if (!tmp)
1306 		return -ENOMEM;
1307 
1308 	ret = r8152_control_msg(tp, tp->pipe_ctrl_in,
1309 				RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1310 				value, index, tmp, size, "read");
1311 
1312 	if (ret < 0)
1313 		memset(data, 0xff, size);
1314 	else
1315 		memcpy(data, tmp, size);
1316 
1317 	kfree(tmp);
1318 
1319 	return ret;
1320 }
1321 
1322 static
1323 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1324 {
1325 	int ret;
1326 	void *tmp;
1327 
1328 	tmp = kmemdup(data, size, GFP_KERNEL);
1329 	if (!tmp)
1330 		return -ENOMEM;
1331 
1332 	ret = r8152_control_msg(tp, tp->pipe_ctrl_out,
1333 				RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1334 				value, index, tmp, size, "write");
1335 
1336 	kfree(tmp);
1337 
1338 	return ret;
1339 }
1340 
1341 static void rtl_set_unplug(struct r8152 *tp)
1342 {
1343 	if (tp->udev->state == USB_STATE_NOTATTACHED)
1344 		rtl_set_inaccessible(tp);
1345 }
1346 
1347 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1348 			    void *data, u16 type)
1349 {
1350 	u16 limit = 64;
1351 	int ret = 0;
1352 
1353 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1354 		return -ENODEV;
1355 
1356 	/* both size and indix must be 4 bytes align */
1357 	if ((size & 3) || !size || (index & 3) || !data)
1358 		return -EPERM;
1359 
1360 	if ((u32)index + (u32)size > 0xffff)
1361 		return -EPERM;
1362 
1363 	while (size) {
1364 		if (size > limit) {
1365 			ret = get_registers(tp, index, type, limit, data);
1366 			if (ret < 0)
1367 				break;
1368 
1369 			index += limit;
1370 			data += limit;
1371 			size -= limit;
1372 		} else {
1373 			ret = get_registers(tp, index, type, size, data);
1374 			if (ret < 0)
1375 				break;
1376 
1377 			index += size;
1378 			data += size;
1379 			size = 0;
1380 			break;
1381 		}
1382 	}
1383 
1384 	if (ret == -ENODEV)
1385 		rtl_set_unplug(tp);
1386 
1387 	return ret;
1388 }
1389 
1390 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1391 			     u16 size, void *data, u16 type)
1392 {
1393 	int ret;
1394 	u16 byteen_start, byteen_end, byen;
1395 	u16 limit = 512;
1396 
1397 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1398 		return -ENODEV;
1399 
1400 	/* both size and indix must be 4 bytes align */
1401 	if ((size & 3) || !size || (index & 3) || !data)
1402 		return -EPERM;
1403 
1404 	if ((u32)index + (u32)size > 0xffff)
1405 		return -EPERM;
1406 
1407 	byteen_start = byteen & BYTE_EN_START_MASK;
1408 	byteen_end = byteen & BYTE_EN_END_MASK;
1409 
1410 	byen = byteen_start | (byteen_start << 4);
1411 
1412 	/* Split the first DWORD if the byte_en is not 0xff */
1413 	if (byen != BYTE_EN_DWORD) {
1414 		ret = set_registers(tp, index, type | byen, 4, data);
1415 		if (ret < 0)
1416 			goto error1;
1417 
1418 		index += 4;
1419 		data += 4;
1420 		size -= 4;
1421 	}
1422 
1423 	if (size) {
1424 		byen = byteen_end | (byteen_end >> 4);
1425 
1426 		/* Split the last DWORD if the byte_en is not 0xff */
1427 		if (byen != BYTE_EN_DWORD)
1428 			size -= 4;
1429 
1430 		while (size) {
1431 			if (size > limit) {
1432 				ret = set_registers(tp, index,
1433 						    type | BYTE_EN_DWORD,
1434 						    limit, data);
1435 				if (ret < 0)
1436 					goto error1;
1437 
1438 				index += limit;
1439 				data += limit;
1440 				size -= limit;
1441 			} else {
1442 				ret = set_registers(tp, index,
1443 						    type | BYTE_EN_DWORD,
1444 						    size, data);
1445 				if (ret < 0)
1446 					goto error1;
1447 
1448 				index += size;
1449 				data += size;
1450 				size = 0;
1451 				break;
1452 			}
1453 		}
1454 
1455 		/* Set the last DWORD */
1456 		if (byen != BYTE_EN_DWORD)
1457 			ret = set_registers(tp, index, type | byen, 4, data);
1458 	}
1459 
1460 error1:
1461 	if (ret == -ENODEV)
1462 		rtl_set_unplug(tp);
1463 
1464 	return ret;
1465 }
1466 
1467 static inline
1468 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1469 {
1470 	return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1471 }
1472 
1473 static inline
1474 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1475 {
1476 	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1477 }
1478 
1479 static inline
1480 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1481 {
1482 	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1483 }
1484 
1485 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1486 {
1487 	__le32 data;
1488 
1489 	generic_ocp_read(tp, index, sizeof(data), &data, type);
1490 
1491 	return __le32_to_cpu(data);
1492 }
1493 
1494 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1495 {
1496 	__le32 tmp = __cpu_to_le32(data);
1497 
1498 	generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1499 }
1500 
1501 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1502 {
1503 	u32 data;
1504 	__le32 tmp;
1505 	u16 byen = BYTE_EN_WORD;
1506 	u8 shift = index & 2;
1507 
1508 	index &= ~3;
1509 	byen <<= shift;
1510 
1511 	generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1512 
1513 	data = __le32_to_cpu(tmp);
1514 	data >>= (shift * 8);
1515 	data &= 0xffff;
1516 
1517 	return (u16)data;
1518 }
1519 
1520 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1521 {
1522 	u32 mask = 0xffff;
1523 	__le32 tmp;
1524 	u16 byen = BYTE_EN_WORD;
1525 	u8 shift = index & 2;
1526 
1527 	data &= mask;
1528 
1529 	if (index & 2) {
1530 		byen <<= shift;
1531 		mask <<= (shift * 8);
1532 		data <<= (shift * 8);
1533 		index &= ~3;
1534 	}
1535 
1536 	tmp = __cpu_to_le32(data);
1537 
1538 	generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1539 }
1540 
1541 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1542 {
1543 	u32 data;
1544 	__le32 tmp;
1545 	u8 shift = index & 3;
1546 
1547 	index &= ~3;
1548 
1549 	generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1550 
1551 	data = __le32_to_cpu(tmp);
1552 	data >>= (shift * 8);
1553 	data &= 0xff;
1554 
1555 	return (u8)data;
1556 }
1557 
1558 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1559 {
1560 	u32 mask = 0xff;
1561 	__le32 tmp;
1562 	u16 byen = BYTE_EN_BYTE;
1563 	u8 shift = index & 3;
1564 
1565 	data &= mask;
1566 
1567 	if (index & 3) {
1568 		byen <<= shift;
1569 		mask <<= (shift * 8);
1570 		data <<= (shift * 8);
1571 		index &= ~3;
1572 	}
1573 
1574 	tmp = __cpu_to_le32(data);
1575 
1576 	generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1577 }
1578 
1579 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1580 {
1581 	u16 ocp_base, ocp_index;
1582 
1583 	ocp_base = addr & 0xf000;
1584 	if (ocp_base != tp->ocp_base) {
1585 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1586 		tp->ocp_base = ocp_base;
1587 	}
1588 
1589 	ocp_index = (addr & 0x0fff) | 0xb000;
1590 	return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1591 }
1592 
1593 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1594 {
1595 	u16 ocp_base, ocp_index;
1596 
1597 	ocp_base = addr & 0xf000;
1598 	if (ocp_base != tp->ocp_base) {
1599 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1600 		tp->ocp_base = ocp_base;
1601 	}
1602 
1603 	ocp_index = (addr & 0x0fff) | 0xb000;
1604 	ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1605 }
1606 
1607 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1608 {
1609 	ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1610 }
1611 
1612 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1613 {
1614 	return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1615 }
1616 
1617 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1618 {
1619 	ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1620 	ocp_reg_write(tp, OCP_SRAM_DATA, data);
1621 }
1622 
1623 static u16 sram_read(struct r8152 *tp, u16 addr)
1624 {
1625 	ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1626 	return ocp_reg_read(tp, OCP_SRAM_DATA);
1627 }
1628 
1629 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1630 {
1631 	struct r8152 *tp = netdev_priv(netdev);
1632 	int ret;
1633 
1634 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1635 		return -ENODEV;
1636 
1637 	if (phy_id != R8152_PHY_ID)
1638 		return -EINVAL;
1639 
1640 	ret = r8152_mdio_read(tp, reg);
1641 
1642 	return ret;
1643 }
1644 
1645 static
1646 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1647 {
1648 	struct r8152 *tp = netdev_priv(netdev);
1649 
1650 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1651 		return;
1652 
1653 	if (phy_id != R8152_PHY_ID)
1654 		return;
1655 
1656 	r8152_mdio_write(tp, reg, val);
1657 }
1658 
1659 static int
1660 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1661 
1662 static int
1663 rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
1664 		  u32 advertising);
1665 
1666 static int __rtl8152_set_mac_address(struct net_device *netdev, void *p,
1667 				     bool in_resume)
1668 {
1669 	struct r8152 *tp = netdev_priv(netdev);
1670 	struct sockaddr *addr = p;
1671 	int ret = -EADDRNOTAVAIL;
1672 
1673 	if (!is_valid_ether_addr(addr->sa_data))
1674 		goto out1;
1675 
1676 	if (!in_resume) {
1677 		ret = usb_autopm_get_interface(tp->intf);
1678 		if (ret < 0)
1679 			goto out1;
1680 	}
1681 
1682 	mutex_lock(&tp->control);
1683 
1684 	eth_hw_addr_set(netdev, addr->sa_data);
1685 
1686 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1687 	pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1688 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1689 
1690 	mutex_unlock(&tp->control);
1691 
1692 	if (!in_resume)
1693 		usb_autopm_put_interface(tp->intf);
1694 out1:
1695 	return ret;
1696 }
1697 
1698 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1699 {
1700 	return __rtl8152_set_mac_address(netdev, p, false);
1701 }
1702 
1703 /* Devices containing proper chips can support a persistent
1704  * host system provided MAC address.
1705  * Examples of this are Dell TB15 and Dell WD15 docks
1706  */
1707 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1708 {
1709 	acpi_status status;
1710 	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1711 	union acpi_object *obj;
1712 	int ret = -EINVAL;
1713 	u32 ocp_data;
1714 	unsigned char buf[6];
1715 	char *mac_obj_name;
1716 	acpi_object_type mac_obj_type;
1717 	int mac_strlen;
1718 
1719 	if (tp->lenovo_macpassthru) {
1720 		mac_obj_name = "\\MACA";
1721 		mac_obj_type = ACPI_TYPE_STRING;
1722 		mac_strlen = 0x16;
1723 	} else {
1724 		/* test for -AD variant of RTL8153 */
1725 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1726 		if ((ocp_data & AD_MASK) == 0x1000) {
1727 			/* test for MAC address pass-through bit */
1728 			ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1729 			if ((ocp_data & PASS_THRU_MASK) != 1) {
1730 				netif_dbg(tp, probe, tp->netdev,
1731 						"No efuse for RTL8153-AD MAC pass through\n");
1732 				return -ENODEV;
1733 			}
1734 		} else {
1735 			/* test for RTL8153-BND and RTL8153-BD */
1736 			ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1737 			if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1738 				netif_dbg(tp, probe, tp->netdev,
1739 						"Invalid variant for MAC pass through\n");
1740 				return -ENODEV;
1741 			}
1742 		}
1743 
1744 		mac_obj_name = "\\_SB.AMAC";
1745 		mac_obj_type = ACPI_TYPE_BUFFER;
1746 		mac_strlen = 0x17;
1747 	}
1748 
1749 	/* returns _AUXMAC_#AABBCCDDEEFF# */
1750 	status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1751 	obj = (union acpi_object *)buffer.pointer;
1752 	if (!ACPI_SUCCESS(status))
1753 		return -ENODEV;
1754 	if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1755 		netif_warn(tp, probe, tp->netdev,
1756 			   "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1757 			   obj->type, obj->string.length);
1758 		goto amacout;
1759 	}
1760 
1761 	if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1762 	    strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1763 		netif_warn(tp, probe, tp->netdev,
1764 			   "Invalid header when reading pass-thru MAC addr\n");
1765 		goto amacout;
1766 	}
1767 	ret = hex2bin(buf, obj->string.pointer + 9, 6);
1768 	if (!(ret == 0 && is_valid_ether_addr(buf))) {
1769 		netif_warn(tp, probe, tp->netdev,
1770 			   "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1771 			   ret, buf);
1772 		ret = -EINVAL;
1773 		goto amacout;
1774 	}
1775 	memcpy(sa->sa_data, buf, 6);
1776 	netif_info(tp, probe, tp->netdev,
1777 		   "Using pass-thru MAC addr %pM\n", sa->sa_data);
1778 
1779 amacout:
1780 	kfree(obj);
1781 	return ret;
1782 }
1783 
1784 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1785 {
1786 	struct net_device *dev = tp->netdev;
1787 	int ret;
1788 
1789 	sa->sa_family = dev->type;
1790 
1791 	ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1792 	if (ret < 0) {
1793 		if (tp->version == RTL_VER_01) {
1794 			ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1795 		} else {
1796 			/* if device doesn't support MAC pass through this will
1797 			 * be expected to be non-zero
1798 			 */
1799 			ret = vendor_mac_passthru_addr_read(tp, sa);
1800 			if (ret < 0)
1801 				ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1802 						   sa->sa_data);
1803 		}
1804 	}
1805 
1806 	if (ret < 0) {
1807 		netif_err(tp, probe, dev, "Get ether addr fail\n");
1808 	} else if (!is_valid_ether_addr(sa->sa_data)) {
1809 		netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1810 			  sa->sa_data);
1811 		eth_hw_addr_random(dev);
1812 		ether_addr_copy(sa->sa_data, dev->dev_addr);
1813 		netif_info(tp, probe, dev, "Random ether addr %pM\n",
1814 			   sa->sa_data);
1815 		return 0;
1816 	}
1817 
1818 	return ret;
1819 }
1820 
1821 static int set_ethernet_addr(struct r8152 *tp, bool in_resume)
1822 {
1823 	struct net_device *dev = tp->netdev;
1824 	struct sockaddr sa;
1825 	int ret;
1826 
1827 	ret = determine_ethernet_addr(tp, &sa);
1828 	if (ret < 0)
1829 		return ret;
1830 
1831 	if (tp->version == RTL_VER_01)
1832 		eth_hw_addr_set(dev, sa.sa_data);
1833 	else
1834 		ret = __rtl8152_set_mac_address(dev, &sa, in_resume);
1835 
1836 	return ret;
1837 }
1838 
1839 static void read_bulk_callback(struct urb *urb)
1840 {
1841 	struct net_device *netdev;
1842 	int status = urb->status;
1843 	struct rx_agg *agg;
1844 	struct r8152 *tp;
1845 	unsigned long flags;
1846 
1847 	agg = urb->context;
1848 	if (!agg)
1849 		return;
1850 
1851 	tp = agg->context;
1852 	if (!tp)
1853 		return;
1854 
1855 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1856 		return;
1857 
1858 	if (!test_bit(WORK_ENABLE, &tp->flags))
1859 		return;
1860 
1861 	netdev = tp->netdev;
1862 
1863 	/* When link down, the driver would cancel all bulks. */
1864 	/* This avoid the re-submitting bulk */
1865 	if (!netif_carrier_ok(netdev))
1866 		return;
1867 
1868 	usb_mark_last_busy(tp->udev);
1869 
1870 	switch (status) {
1871 	case 0:
1872 		if (urb->actual_length < ETH_ZLEN)
1873 			break;
1874 
1875 		spin_lock_irqsave(&tp->rx_lock, flags);
1876 		list_add_tail(&agg->list, &tp->rx_done);
1877 		spin_unlock_irqrestore(&tp->rx_lock, flags);
1878 		napi_schedule(&tp->napi);
1879 		return;
1880 	case -ESHUTDOWN:
1881 		rtl_set_unplug(tp);
1882 		netif_device_detach(tp->netdev);
1883 		return;
1884 	case -EPROTO:
1885 		urb->actual_length = 0;
1886 		spin_lock_irqsave(&tp->rx_lock, flags);
1887 		list_add_tail(&agg->list, &tp->rx_done);
1888 		spin_unlock_irqrestore(&tp->rx_lock, flags);
1889 		set_bit(RX_EPROTO, &tp->flags);
1890 		schedule_delayed_work(&tp->schedule, 1);
1891 		return;
1892 	case -ENOENT:
1893 		return;	/* the urb is in unlink state */
1894 	case -ETIME:
1895 		if (net_ratelimit())
1896 			netdev_warn(netdev, "maybe reset is needed?\n");
1897 		break;
1898 	default:
1899 		if (net_ratelimit())
1900 			netdev_warn(netdev, "Rx status %d\n", status);
1901 		break;
1902 	}
1903 
1904 	r8152_submit_rx(tp, agg, GFP_ATOMIC);
1905 }
1906 
1907 static void write_bulk_callback(struct urb *urb)
1908 {
1909 	struct net_device_stats *stats;
1910 	struct net_device *netdev;
1911 	struct tx_agg *agg;
1912 	struct r8152 *tp;
1913 	unsigned long flags;
1914 	int status = urb->status;
1915 
1916 	agg = urb->context;
1917 	if (!agg)
1918 		return;
1919 
1920 	tp = agg->context;
1921 	if (!tp)
1922 		return;
1923 
1924 	netdev = tp->netdev;
1925 	stats = &netdev->stats;
1926 	if (status) {
1927 		if (net_ratelimit())
1928 			netdev_warn(netdev, "Tx status %d\n", status);
1929 		stats->tx_errors += agg->skb_num;
1930 	} else {
1931 		stats->tx_packets += agg->skb_num;
1932 		stats->tx_bytes += agg->skb_len;
1933 	}
1934 
1935 	spin_lock_irqsave(&tp->tx_lock, flags);
1936 	list_add_tail(&agg->list, &tp->tx_free);
1937 	spin_unlock_irqrestore(&tp->tx_lock, flags);
1938 
1939 	usb_autopm_put_interface_async(tp->intf);
1940 
1941 	if (!netif_carrier_ok(netdev))
1942 		return;
1943 
1944 	if (!test_bit(WORK_ENABLE, &tp->flags))
1945 		return;
1946 
1947 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1948 		return;
1949 
1950 	if (!skb_queue_empty(&tp->tx_queue))
1951 		tasklet_schedule(&tp->tx_tl);
1952 }
1953 
1954 static void intr_callback(struct urb *urb)
1955 {
1956 	struct r8152 *tp;
1957 	__le16 *d;
1958 	int status = urb->status;
1959 	int res;
1960 
1961 	tp = urb->context;
1962 	if (!tp)
1963 		return;
1964 
1965 	if (!test_bit(WORK_ENABLE, &tp->flags))
1966 		return;
1967 
1968 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1969 		return;
1970 
1971 	switch (status) {
1972 	case 0:			/* success */
1973 		break;
1974 	case -ECONNRESET:	/* unlink */
1975 	case -ESHUTDOWN:
1976 		netif_device_detach(tp->netdev);
1977 		fallthrough;
1978 	case -ENOENT:
1979 	case -EPROTO:
1980 		netif_info(tp, intr, tp->netdev,
1981 			   "Stop submitting intr, status %d\n", status);
1982 		return;
1983 	case -EOVERFLOW:
1984 		if (net_ratelimit())
1985 			netif_info(tp, intr, tp->netdev,
1986 				   "intr status -EOVERFLOW\n");
1987 		goto resubmit;
1988 	/* -EPIPE:  should clear the halt */
1989 	default:
1990 		netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1991 		goto resubmit;
1992 	}
1993 
1994 	d = urb->transfer_buffer;
1995 	if (INTR_LINK & __le16_to_cpu(d[0])) {
1996 		if (!netif_carrier_ok(tp->netdev)) {
1997 			set_bit(RTL8152_LINK_CHG, &tp->flags);
1998 			schedule_delayed_work(&tp->schedule, 0);
1999 		}
2000 	} else {
2001 		if (netif_carrier_ok(tp->netdev)) {
2002 			netif_stop_queue(tp->netdev);
2003 			set_bit(RTL8152_LINK_CHG, &tp->flags);
2004 			schedule_delayed_work(&tp->schedule, 0);
2005 		}
2006 	}
2007 
2008 resubmit:
2009 	res = usb_submit_urb(urb, GFP_ATOMIC);
2010 	if (res == -ENODEV) {
2011 		rtl_set_unplug(tp);
2012 		netif_device_detach(tp->netdev);
2013 	} else if (res) {
2014 		netif_err(tp, intr, tp->netdev,
2015 			  "can't resubmit intr, status %d\n", res);
2016 	}
2017 }
2018 
2019 static inline void *rx_agg_align(void *data)
2020 {
2021 	return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
2022 }
2023 
2024 static inline void *tx_agg_align(void *data)
2025 {
2026 	return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
2027 }
2028 
2029 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
2030 {
2031 	list_del(&agg->info_list);
2032 
2033 	usb_free_urb(agg->urb);
2034 	put_page(agg->page);
2035 	kfree(agg);
2036 
2037 	atomic_dec(&tp->rx_count);
2038 }
2039 
2040 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
2041 {
2042 	struct net_device *netdev = tp->netdev;
2043 	int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
2044 	unsigned int order = get_order(tp->rx_buf_sz);
2045 	struct rx_agg *rx_agg;
2046 	unsigned long flags;
2047 
2048 	rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
2049 	if (!rx_agg)
2050 		return NULL;
2051 
2052 	rx_agg->page = alloc_pages(mflags | __GFP_COMP | __GFP_NOWARN, order);
2053 	if (!rx_agg->page)
2054 		goto free_rx;
2055 
2056 	rx_agg->buffer = page_address(rx_agg->page);
2057 
2058 	rx_agg->urb = usb_alloc_urb(0, mflags);
2059 	if (!rx_agg->urb)
2060 		goto free_buf;
2061 
2062 	rx_agg->context = tp;
2063 
2064 	INIT_LIST_HEAD(&rx_agg->list);
2065 	INIT_LIST_HEAD(&rx_agg->info_list);
2066 	spin_lock_irqsave(&tp->rx_lock, flags);
2067 	list_add_tail(&rx_agg->info_list, &tp->rx_info);
2068 	spin_unlock_irqrestore(&tp->rx_lock, flags);
2069 
2070 	atomic_inc(&tp->rx_count);
2071 
2072 	return rx_agg;
2073 
2074 free_buf:
2075 	__free_pages(rx_agg->page, order);
2076 free_rx:
2077 	kfree(rx_agg);
2078 	return NULL;
2079 }
2080 
2081 static void free_all_mem(struct r8152 *tp)
2082 {
2083 	struct rx_agg *agg, *agg_next;
2084 	unsigned long flags;
2085 	int i;
2086 
2087 	spin_lock_irqsave(&tp->rx_lock, flags);
2088 
2089 	list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
2090 		free_rx_agg(tp, agg);
2091 
2092 	spin_unlock_irqrestore(&tp->rx_lock, flags);
2093 
2094 	WARN_ON(atomic_read(&tp->rx_count));
2095 
2096 	for (i = 0; i < RTL8152_MAX_TX; i++) {
2097 		usb_free_urb(tp->tx_info[i].urb);
2098 		tp->tx_info[i].urb = NULL;
2099 
2100 		kfree(tp->tx_info[i].buffer);
2101 		tp->tx_info[i].buffer = NULL;
2102 		tp->tx_info[i].head = NULL;
2103 	}
2104 
2105 	usb_free_urb(tp->intr_urb);
2106 	tp->intr_urb = NULL;
2107 
2108 	kfree(tp->intr_buff);
2109 	tp->intr_buff = NULL;
2110 }
2111 
2112 static int alloc_all_mem(struct r8152 *tp)
2113 {
2114 	struct net_device *netdev = tp->netdev;
2115 	struct usb_interface *intf = tp->intf;
2116 	struct usb_host_interface *alt = intf->cur_altsetting;
2117 	struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
2118 	int node, i;
2119 
2120 	node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
2121 
2122 	spin_lock_init(&tp->rx_lock);
2123 	spin_lock_init(&tp->tx_lock);
2124 	INIT_LIST_HEAD(&tp->rx_info);
2125 	INIT_LIST_HEAD(&tp->tx_free);
2126 	INIT_LIST_HEAD(&tp->rx_done);
2127 	skb_queue_head_init(&tp->tx_queue);
2128 	skb_queue_head_init(&tp->rx_queue);
2129 	atomic_set(&tp->rx_count, 0);
2130 
2131 	for (i = 0; i < RTL8152_MAX_RX; i++) {
2132 		if (!alloc_rx_agg(tp, GFP_KERNEL))
2133 			goto err1;
2134 	}
2135 
2136 	for (i = 0; i < RTL8152_MAX_TX; i++) {
2137 		struct urb *urb;
2138 		u8 *buf;
2139 
2140 		buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
2141 		if (!buf)
2142 			goto err1;
2143 
2144 		if (buf != tx_agg_align(buf)) {
2145 			kfree(buf);
2146 			buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
2147 					   node);
2148 			if (!buf)
2149 				goto err1;
2150 		}
2151 
2152 		urb = usb_alloc_urb(0, GFP_KERNEL);
2153 		if (!urb) {
2154 			kfree(buf);
2155 			goto err1;
2156 		}
2157 
2158 		INIT_LIST_HEAD(&tp->tx_info[i].list);
2159 		tp->tx_info[i].context = tp;
2160 		tp->tx_info[i].urb = urb;
2161 		tp->tx_info[i].buffer = buf;
2162 		tp->tx_info[i].head = tx_agg_align(buf);
2163 
2164 		list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
2165 	}
2166 
2167 	tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
2168 	if (!tp->intr_urb)
2169 		goto err1;
2170 
2171 	tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
2172 	if (!tp->intr_buff)
2173 		goto err1;
2174 
2175 	tp->intr_interval = (int)ep_intr->desc.bInterval;
2176 	usb_fill_int_urb(tp->intr_urb, tp->udev, tp->pipe_intr,
2177 			 tp->intr_buff, INTBUFSIZE, intr_callback,
2178 			 tp, tp->intr_interval);
2179 
2180 	return 0;
2181 
2182 err1:
2183 	free_all_mem(tp);
2184 	return -ENOMEM;
2185 }
2186 
2187 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
2188 {
2189 	struct tx_agg *agg = NULL;
2190 	unsigned long flags;
2191 
2192 	if (list_empty(&tp->tx_free))
2193 		return NULL;
2194 
2195 	spin_lock_irqsave(&tp->tx_lock, flags);
2196 	if (!list_empty(&tp->tx_free)) {
2197 		struct list_head *cursor;
2198 
2199 		cursor = tp->tx_free.next;
2200 		list_del_init(cursor);
2201 		agg = list_entry(cursor, struct tx_agg, list);
2202 	}
2203 	spin_unlock_irqrestore(&tp->tx_lock, flags);
2204 
2205 	return agg;
2206 }
2207 
2208 /* r8152_csum_workaround()
2209  * The hw limits the value of the transport offset. When the offset is out of
2210  * range, calculate the checksum by sw.
2211  */
2212 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
2213 				  struct sk_buff_head *list)
2214 {
2215 	if (skb_shinfo(skb)->gso_size) {
2216 		netdev_features_t features = tp->netdev->features;
2217 		struct sk_buff *segs, *seg, *next;
2218 		struct sk_buff_head seg_list;
2219 
2220 		features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
2221 		segs = skb_gso_segment(skb, features);
2222 		if (IS_ERR(segs) || !segs)
2223 			goto drop;
2224 
2225 		__skb_queue_head_init(&seg_list);
2226 
2227 		skb_list_walk_safe(segs, seg, next) {
2228 			skb_mark_not_on_list(seg);
2229 			__skb_queue_tail(&seg_list, seg);
2230 		}
2231 
2232 		skb_queue_splice(&seg_list, list);
2233 		dev_kfree_skb(skb);
2234 	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2235 		if (skb_checksum_help(skb) < 0)
2236 			goto drop;
2237 
2238 		__skb_queue_head(list, skb);
2239 	} else {
2240 		struct net_device_stats *stats;
2241 
2242 drop:
2243 		stats = &tp->netdev->stats;
2244 		stats->tx_dropped++;
2245 		dev_kfree_skb(skb);
2246 	}
2247 }
2248 
2249 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
2250 {
2251 	if (skb_vlan_tag_present(skb)) {
2252 		u32 opts2;
2253 
2254 		opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
2255 		desc->opts2 |= cpu_to_le32(opts2);
2256 	}
2257 }
2258 
2259 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
2260 {
2261 	u32 opts2 = le32_to_cpu(desc->opts2);
2262 
2263 	if (opts2 & RX_VLAN_TAG)
2264 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2265 				       swab16(opts2 & 0xffff));
2266 }
2267 
2268 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
2269 			 struct sk_buff *skb, u32 len)
2270 {
2271 	u32 mss = skb_shinfo(skb)->gso_size;
2272 	u32 opts1, opts2 = 0;
2273 	int ret = TX_CSUM_SUCCESS;
2274 
2275 	WARN_ON_ONCE(len > TX_LEN_MAX);
2276 
2277 	opts1 = len | TX_FS | TX_LS;
2278 
2279 	if (mss) {
2280 		u32 transport_offset = (u32)skb_transport_offset(skb);
2281 
2282 		if (transport_offset > GTTCPHO_MAX) {
2283 			netif_warn(tp, tx_err, tp->netdev,
2284 				   "Invalid transport offset 0x%x for TSO\n",
2285 				   transport_offset);
2286 			ret = TX_CSUM_TSO;
2287 			goto unavailable;
2288 		}
2289 
2290 		switch (vlan_get_protocol(skb)) {
2291 		case htons(ETH_P_IP):
2292 			opts1 |= GTSENDV4;
2293 			break;
2294 
2295 		case htons(ETH_P_IPV6):
2296 			if (skb_cow_head(skb, 0)) {
2297 				ret = TX_CSUM_TSO;
2298 				goto unavailable;
2299 			}
2300 			tcp_v6_gso_csum_prep(skb);
2301 			opts1 |= GTSENDV6;
2302 			break;
2303 
2304 		default:
2305 			WARN_ON_ONCE(1);
2306 			break;
2307 		}
2308 
2309 		opts1 |= transport_offset << GTTCPHO_SHIFT;
2310 		opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2311 	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2312 		u32 transport_offset = (u32)skb_transport_offset(skb);
2313 		u8 ip_protocol;
2314 
2315 		if (transport_offset > TCPHO_MAX) {
2316 			netif_warn(tp, tx_err, tp->netdev,
2317 				   "Invalid transport offset 0x%x\n",
2318 				   transport_offset);
2319 			ret = TX_CSUM_NONE;
2320 			goto unavailable;
2321 		}
2322 
2323 		switch (vlan_get_protocol(skb)) {
2324 		case htons(ETH_P_IP):
2325 			opts2 |= IPV4_CS;
2326 			ip_protocol = ip_hdr(skb)->protocol;
2327 			break;
2328 
2329 		case htons(ETH_P_IPV6):
2330 			opts2 |= IPV6_CS;
2331 			ip_protocol = ipv6_hdr(skb)->nexthdr;
2332 			break;
2333 
2334 		default:
2335 			ip_protocol = IPPROTO_RAW;
2336 			break;
2337 		}
2338 
2339 		if (ip_protocol == IPPROTO_TCP)
2340 			opts2 |= TCP_CS;
2341 		else if (ip_protocol == IPPROTO_UDP)
2342 			opts2 |= UDP_CS;
2343 		else
2344 			WARN_ON_ONCE(1);
2345 
2346 		opts2 |= transport_offset << TCPHO_SHIFT;
2347 	}
2348 
2349 	desc->opts2 = cpu_to_le32(opts2);
2350 	desc->opts1 = cpu_to_le32(opts1);
2351 
2352 unavailable:
2353 	return ret;
2354 }
2355 
2356 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2357 {
2358 	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2359 	int remain, ret;
2360 	u8 *tx_data;
2361 
2362 	__skb_queue_head_init(&skb_head);
2363 	spin_lock(&tx_queue->lock);
2364 	skb_queue_splice_init(tx_queue, &skb_head);
2365 	spin_unlock(&tx_queue->lock);
2366 
2367 	tx_data = agg->head;
2368 	agg->skb_num = 0;
2369 	agg->skb_len = 0;
2370 	remain = agg_buf_sz;
2371 
2372 	while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2373 		struct tx_desc *tx_desc;
2374 		struct sk_buff *skb;
2375 		unsigned int len;
2376 
2377 		skb = __skb_dequeue(&skb_head);
2378 		if (!skb)
2379 			break;
2380 
2381 		len = skb->len + sizeof(*tx_desc);
2382 
2383 		if (len > remain) {
2384 			__skb_queue_head(&skb_head, skb);
2385 			break;
2386 		}
2387 
2388 		tx_data = tx_agg_align(tx_data);
2389 		tx_desc = (struct tx_desc *)tx_data;
2390 
2391 		if (r8152_tx_csum(tp, tx_desc, skb, skb->len)) {
2392 			r8152_csum_workaround(tp, skb, &skb_head);
2393 			continue;
2394 		}
2395 
2396 		rtl_tx_vlan_tag(tx_desc, skb);
2397 
2398 		tx_data += sizeof(*tx_desc);
2399 
2400 		len = skb->len;
2401 		if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2402 			struct net_device_stats *stats = &tp->netdev->stats;
2403 
2404 			stats->tx_dropped++;
2405 			dev_kfree_skb_any(skb);
2406 			tx_data -= sizeof(*tx_desc);
2407 			continue;
2408 		}
2409 
2410 		tx_data += len;
2411 		agg->skb_len += len;
2412 		agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2413 
2414 		dev_kfree_skb_any(skb);
2415 
2416 		remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2417 
2418 		if (tp->dell_tb_rx_agg_bug)
2419 			break;
2420 	}
2421 
2422 	if (!skb_queue_empty(&skb_head)) {
2423 		spin_lock(&tx_queue->lock);
2424 		skb_queue_splice(&skb_head, tx_queue);
2425 		spin_unlock(&tx_queue->lock);
2426 	}
2427 
2428 	netif_tx_lock(tp->netdev);
2429 
2430 	if (netif_queue_stopped(tp->netdev) &&
2431 	    skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2432 		netif_wake_queue(tp->netdev);
2433 
2434 	netif_tx_unlock(tp->netdev);
2435 
2436 	ret = usb_autopm_get_interface_async(tp->intf);
2437 	if (ret < 0)
2438 		goto out_tx_fill;
2439 
2440 	usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_out,
2441 			  agg->head, (int)(tx_data - (u8 *)agg->head),
2442 			  (usb_complete_t)write_bulk_callback, agg);
2443 
2444 	ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2445 	if (ret < 0)
2446 		usb_autopm_put_interface_async(tp->intf);
2447 
2448 out_tx_fill:
2449 	return ret;
2450 }
2451 
2452 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2453 {
2454 	u8 checksum = CHECKSUM_NONE;
2455 	u32 opts2, opts3;
2456 
2457 	if (!(tp->netdev->features & NETIF_F_RXCSUM))
2458 		goto return_result;
2459 
2460 	opts2 = le32_to_cpu(rx_desc->opts2);
2461 	opts3 = le32_to_cpu(rx_desc->opts3);
2462 
2463 	if (opts2 & RD_IPV4_CS) {
2464 		if (opts3 & IPF)
2465 			checksum = CHECKSUM_NONE;
2466 		else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2467 			checksum = CHECKSUM_UNNECESSARY;
2468 		else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2469 			checksum = CHECKSUM_UNNECESSARY;
2470 	} else if (opts2 & RD_IPV6_CS) {
2471 		if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2472 			checksum = CHECKSUM_UNNECESSARY;
2473 		else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2474 			checksum = CHECKSUM_UNNECESSARY;
2475 	}
2476 
2477 return_result:
2478 	return checksum;
2479 }
2480 
2481 static inline bool rx_count_exceed(struct r8152 *tp)
2482 {
2483 	return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2484 }
2485 
2486 static inline int agg_offset(struct rx_agg *agg, void *addr)
2487 {
2488 	return (int)(addr - agg->buffer);
2489 }
2490 
2491 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2492 {
2493 	struct rx_agg *agg, *agg_next, *agg_free = NULL;
2494 	unsigned long flags;
2495 
2496 	spin_lock_irqsave(&tp->rx_lock, flags);
2497 
2498 	list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2499 		if (page_count(agg->page) == 1) {
2500 			if (!agg_free) {
2501 				list_del_init(&agg->list);
2502 				agg_free = agg;
2503 				continue;
2504 			}
2505 			if (rx_count_exceed(tp)) {
2506 				list_del_init(&agg->list);
2507 				free_rx_agg(tp, agg);
2508 			}
2509 			break;
2510 		}
2511 	}
2512 
2513 	spin_unlock_irqrestore(&tp->rx_lock, flags);
2514 
2515 	if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2516 		agg_free = alloc_rx_agg(tp, mflags);
2517 
2518 	return agg_free;
2519 }
2520 
2521 static int rx_bottom(struct r8152 *tp, int budget)
2522 {
2523 	unsigned long flags;
2524 	struct list_head *cursor, *next, rx_queue;
2525 	int ret = 0, work_done = 0;
2526 	struct napi_struct *napi = &tp->napi;
2527 
2528 	if (!skb_queue_empty(&tp->rx_queue)) {
2529 		while (work_done < budget) {
2530 			struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2531 			struct net_device *netdev = tp->netdev;
2532 			struct net_device_stats *stats = &netdev->stats;
2533 			unsigned int pkt_len;
2534 
2535 			if (!skb)
2536 				break;
2537 
2538 			pkt_len = skb->len;
2539 			napi_gro_receive(napi, skb);
2540 			work_done++;
2541 			stats->rx_packets++;
2542 			stats->rx_bytes += pkt_len;
2543 		}
2544 	}
2545 
2546 	if (list_empty(&tp->rx_done) || work_done >= budget)
2547 		goto out1;
2548 
2549 	clear_bit(RX_EPROTO, &tp->flags);
2550 	INIT_LIST_HEAD(&rx_queue);
2551 	spin_lock_irqsave(&tp->rx_lock, flags);
2552 	list_splice_init(&tp->rx_done, &rx_queue);
2553 	spin_unlock_irqrestore(&tp->rx_lock, flags);
2554 
2555 	list_for_each_safe(cursor, next, &rx_queue) {
2556 		struct rx_desc *rx_desc;
2557 		struct rx_agg *agg, *agg_free;
2558 		int len_used = 0;
2559 		struct urb *urb;
2560 		u8 *rx_data;
2561 
2562 		/* A bulk transfer of USB may contain may packets, so the
2563 		 * total packets may more than the budget. Deal with all
2564 		 * packets in current bulk transfer, and stop to handle the
2565 		 * next bulk transfer until next schedule, if budget is
2566 		 * exhausted.
2567 		 */
2568 		if (work_done >= budget)
2569 			break;
2570 
2571 		list_del_init(cursor);
2572 
2573 		agg = list_entry(cursor, struct rx_agg, list);
2574 		urb = agg->urb;
2575 		if (urb->status != 0 || urb->actual_length < ETH_ZLEN)
2576 			goto submit;
2577 
2578 		agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2579 
2580 		rx_desc = agg->buffer;
2581 		rx_data = agg->buffer;
2582 		len_used += sizeof(struct rx_desc);
2583 
2584 		while (urb->actual_length > len_used) {
2585 			struct net_device *netdev = tp->netdev;
2586 			struct net_device_stats *stats = &netdev->stats;
2587 			unsigned int pkt_len, rx_frag_head_sz;
2588 			struct sk_buff *skb;
2589 
2590 			WARN_ON_ONCE(skb_queue_len(&tp->rx_queue) >= 1000);
2591 
2592 			pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2593 			if (pkt_len < ETH_ZLEN)
2594 				break;
2595 
2596 			len_used += pkt_len;
2597 			if (urb->actual_length < len_used)
2598 				break;
2599 
2600 			pkt_len -= ETH_FCS_LEN;
2601 			rx_data += sizeof(struct rx_desc);
2602 
2603 			if (!agg_free || tp->rx_copybreak > pkt_len)
2604 				rx_frag_head_sz = pkt_len;
2605 			else
2606 				rx_frag_head_sz = tp->rx_copybreak;
2607 
2608 			skb = napi_alloc_skb(napi, rx_frag_head_sz);
2609 			if (!skb) {
2610 				stats->rx_dropped++;
2611 				goto find_next_rx;
2612 			}
2613 
2614 			skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2615 			memcpy(skb->data, rx_data, rx_frag_head_sz);
2616 			skb_put(skb, rx_frag_head_sz);
2617 			pkt_len -= rx_frag_head_sz;
2618 			rx_data += rx_frag_head_sz;
2619 			if (pkt_len) {
2620 				skb_add_rx_frag(skb, 0, agg->page,
2621 						agg_offset(agg, rx_data),
2622 						pkt_len,
2623 						SKB_DATA_ALIGN(pkt_len));
2624 				get_page(agg->page);
2625 			}
2626 
2627 			skb->protocol = eth_type_trans(skb, netdev);
2628 			rtl_rx_vlan_tag(rx_desc, skb);
2629 			if (work_done < budget) {
2630 				work_done++;
2631 				stats->rx_packets++;
2632 				stats->rx_bytes += skb->len;
2633 				napi_gro_receive(napi, skb);
2634 			} else {
2635 				__skb_queue_tail(&tp->rx_queue, skb);
2636 			}
2637 
2638 find_next_rx:
2639 			rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2640 			rx_desc = (struct rx_desc *)rx_data;
2641 			len_used = agg_offset(agg, rx_data);
2642 			len_used += sizeof(struct rx_desc);
2643 		}
2644 
2645 		WARN_ON(!agg_free && page_count(agg->page) > 1);
2646 
2647 		if (agg_free) {
2648 			spin_lock_irqsave(&tp->rx_lock, flags);
2649 			if (page_count(agg->page) == 1) {
2650 				list_add(&agg_free->list, &tp->rx_used);
2651 			} else {
2652 				list_add_tail(&agg->list, &tp->rx_used);
2653 				agg = agg_free;
2654 				urb = agg->urb;
2655 			}
2656 			spin_unlock_irqrestore(&tp->rx_lock, flags);
2657 		}
2658 
2659 submit:
2660 		if (!ret) {
2661 			ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2662 		} else {
2663 			urb->actual_length = 0;
2664 			list_add_tail(&agg->list, next);
2665 		}
2666 	}
2667 
2668 	/* Splice the remained list back to rx_done for next schedule */
2669 	if (!list_empty(&rx_queue)) {
2670 		spin_lock_irqsave(&tp->rx_lock, flags);
2671 		list_splice(&rx_queue, &tp->rx_done);
2672 		spin_unlock_irqrestore(&tp->rx_lock, flags);
2673 	}
2674 
2675 out1:
2676 	return work_done;
2677 }
2678 
2679 static void tx_bottom(struct r8152 *tp)
2680 {
2681 	int res;
2682 
2683 	do {
2684 		struct net_device *netdev = tp->netdev;
2685 		struct tx_agg *agg;
2686 
2687 		if (skb_queue_empty(&tp->tx_queue))
2688 			break;
2689 
2690 		agg = r8152_get_tx_agg(tp);
2691 		if (!agg)
2692 			break;
2693 
2694 		res = r8152_tx_agg_fill(tp, agg);
2695 		if (!res)
2696 			continue;
2697 
2698 		if (res == -ENODEV) {
2699 			rtl_set_unplug(tp);
2700 			netif_device_detach(netdev);
2701 		} else {
2702 			struct net_device_stats *stats = &netdev->stats;
2703 			unsigned long flags;
2704 
2705 			netif_warn(tp, tx_err, netdev,
2706 				   "failed tx_urb %d\n", res);
2707 			stats->tx_dropped += agg->skb_num;
2708 
2709 			spin_lock_irqsave(&tp->tx_lock, flags);
2710 			list_add_tail(&agg->list, &tp->tx_free);
2711 			spin_unlock_irqrestore(&tp->tx_lock, flags);
2712 		}
2713 	} while (res == 0);
2714 }
2715 
2716 static void bottom_half(struct tasklet_struct *t)
2717 {
2718 	struct r8152 *tp = from_tasklet(tp, t, tx_tl);
2719 
2720 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
2721 		return;
2722 
2723 	if (!test_bit(WORK_ENABLE, &tp->flags))
2724 		return;
2725 
2726 	/* When link down, the driver would cancel all bulks. */
2727 	/* This avoid the re-submitting bulk */
2728 	if (!netif_carrier_ok(tp->netdev))
2729 		return;
2730 
2731 	clear_bit(SCHEDULE_TASKLET, &tp->flags);
2732 
2733 	tx_bottom(tp);
2734 }
2735 
2736 static int r8152_poll(struct napi_struct *napi, int budget)
2737 {
2738 	struct r8152 *tp = container_of(napi, struct r8152, napi);
2739 	int work_done;
2740 
2741 	if (!budget)
2742 		return 0;
2743 
2744 	work_done = rx_bottom(tp, budget);
2745 
2746 	if (work_done < budget) {
2747 		if (!napi_complete_done(napi, work_done))
2748 			goto out;
2749 		if (!list_empty(&tp->rx_done))
2750 			napi_schedule(napi);
2751 	}
2752 
2753 out:
2754 	return work_done;
2755 }
2756 
2757 static
2758 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2759 {
2760 	int ret;
2761 
2762 	/* The rx would be stopped, so skip submitting */
2763 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) ||
2764 	    !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2765 		return 0;
2766 
2767 	usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_in,
2768 			  agg->buffer, tp->rx_buf_sz,
2769 			  (usb_complete_t)read_bulk_callback, agg);
2770 
2771 	ret = usb_submit_urb(agg->urb, mem_flags);
2772 	if (ret == -ENODEV) {
2773 		rtl_set_unplug(tp);
2774 		netif_device_detach(tp->netdev);
2775 	} else if (ret) {
2776 		struct urb *urb = agg->urb;
2777 		unsigned long flags;
2778 
2779 		urb->actual_length = 0;
2780 		spin_lock_irqsave(&tp->rx_lock, flags);
2781 		list_add_tail(&agg->list, &tp->rx_done);
2782 		spin_unlock_irqrestore(&tp->rx_lock, flags);
2783 
2784 		netif_err(tp, rx_err, tp->netdev,
2785 			  "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2786 
2787 		napi_schedule(&tp->napi);
2788 	}
2789 
2790 	return ret;
2791 }
2792 
2793 static void rtl_drop_queued_tx(struct r8152 *tp)
2794 {
2795 	struct net_device_stats *stats = &tp->netdev->stats;
2796 	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2797 	struct sk_buff *skb;
2798 
2799 	if (skb_queue_empty(tx_queue))
2800 		return;
2801 
2802 	__skb_queue_head_init(&skb_head);
2803 	spin_lock_bh(&tx_queue->lock);
2804 	skb_queue_splice_init(tx_queue, &skb_head);
2805 	spin_unlock_bh(&tx_queue->lock);
2806 
2807 	while ((skb = __skb_dequeue(&skb_head))) {
2808 		dev_kfree_skb(skb);
2809 		stats->tx_dropped++;
2810 	}
2811 }
2812 
2813 static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2814 {
2815 	struct r8152 *tp = netdev_priv(netdev);
2816 
2817 	netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2818 
2819 	usb_queue_reset_device(tp->intf);
2820 }
2821 
2822 static void rtl8152_set_rx_mode(struct net_device *netdev)
2823 {
2824 	struct r8152 *tp = netdev_priv(netdev);
2825 
2826 	if (netif_carrier_ok(netdev)) {
2827 		set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2828 		schedule_delayed_work(&tp->schedule, 0);
2829 	}
2830 }
2831 
2832 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2833 {
2834 	struct r8152 *tp = netdev_priv(netdev);
2835 	u32 mc_filter[2];	/* Multicast hash filter */
2836 	__le32 tmp[2];
2837 	u32 ocp_data;
2838 
2839 	netif_stop_queue(netdev);
2840 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2841 	ocp_data &= ~RCR_ACPT_ALL;
2842 	ocp_data |= RCR_AB | RCR_APM;
2843 
2844 	if (netdev->flags & IFF_PROMISC) {
2845 		/* Unconditionally log net taps. */
2846 		netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2847 		ocp_data |= RCR_AM | RCR_AAP;
2848 		mc_filter[1] = 0xffffffff;
2849 		mc_filter[0] = 0xffffffff;
2850 	} else if ((netdev->flags & IFF_MULTICAST &&
2851 				netdev_mc_count(netdev) > multicast_filter_limit) ||
2852 			   (netdev->flags & IFF_ALLMULTI)) {
2853 		/* Too many to filter perfectly -- accept all multicasts. */
2854 		ocp_data |= RCR_AM;
2855 		mc_filter[1] = 0xffffffff;
2856 		mc_filter[0] = 0xffffffff;
2857 	} else {
2858 		mc_filter[1] = 0;
2859 		mc_filter[0] = 0;
2860 
2861 		if (netdev->flags & IFF_MULTICAST) {
2862 			struct netdev_hw_addr *ha;
2863 
2864 			netdev_for_each_mc_addr(ha, netdev) {
2865 				int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2866 
2867 				mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2868 				ocp_data |= RCR_AM;
2869 			}
2870 		}
2871 	}
2872 
2873 	tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2874 	tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2875 
2876 	pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2877 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2878 	netif_wake_queue(netdev);
2879 }
2880 
2881 static netdev_features_t
2882 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2883 		       netdev_features_t features)
2884 {
2885 	u32 mss = skb_shinfo(skb)->gso_size;
2886 	int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2887 
2888 	if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) &&
2889 	    skb_transport_offset(skb) > max_offset)
2890 		features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2891 	else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2892 		features &= ~NETIF_F_GSO_MASK;
2893 
2894 	return features;
2895 }
2896 
2897 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2898 				      struct net_device *netdev)
2899 {
2900 	struct r8152 *tp = netdev_priv(netdev);
2901 
2902 	skb_tx_timestamp(skb);
2903 
2904 	skb_queue_tail(&tp->tx_queue, skb);
2905 
2906 	if (!list_empty(&tp->tx_free)) {
2907 		if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2908 			set_bit(SCHEDULE_TASKLET, &tp->flags);
2909 			schedule_delayed_work(&tp->schedule, 0);
2910 		} else {
2911 			usb_mark_last_busy(tp->udev);
2912 			tasklet_schedule(&tp->tx_tl);
2913 		}
2914 	} else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2915 		netif_stop_queue(netdev);
2916 	}
2917 
2918 	return NETDEV_TX_OK;
2919 }
2920 
2921 static void r8152b_reset_packet_filter(struct r8152 *tp)
2922 {
2923 	u32 ocp_data;
2924 
2925 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2926 	ocp_data &= ~FMC_FCR_MCU_EN;
2927 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2928 	ocp_data |= FMC_FCR_MCU_EN;
2929 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2930 }
2931 
2932 static void rtl8152_nic_reset(struct r8152 *tp)
2933 {
2934 	u32 ocp_data;
2935 	int i;
2936 
2937 	switch (tp->version) {
2938 	case RTL_TEST_01:
2939 	case RTL_VER_10:
2940 	case RTL_VER_11:
2941 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2942 		ocp_data &= ~CR_TE;
2943 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2944 
2945 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2946 		ocp_data &= ~BMU_RESET_EP_IN;
2947 		ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2948 
2949 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2950 		ocp_data |= CDC_ECM_EN;
2951 		ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2952 
2953 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2954 		ocp_data &= ~CR_RE;
2955 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2956 
2957 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2958 		ocp_data |= BMU_RESET_EP_IN;
2959 		ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2960 
2961 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2962 		ocp_data &= ~CDC_ECM_EN;
2963 		ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2964 		break;
2965 
2966 	default:
2967 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2968 
2969 		for (i = 0; i < 1000; i++) {
2970 			if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
2971 				break;
2972 			if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2973 				break;
2974 			usleep_range(100, 400);
2975 		}
2976 		break;
2977 	}
2978 }
2979 
2980 static void set_tx_qlen(struct r8152 *tp)
2981 {
2982 	tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));
2983 }
2984 
2985 static inline u16 rtl8152_get_speed(struct r8152 *tp)
2986 {
2987 	return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2988 }
2989 
2990 static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
2991 {
2992 	u32 ocp_data;
2993 
2994 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2995 	if (enable)
2996 		ocp_data |= EEEP_CR_EEEP_TX;
2997 	else
2998 		ocp_data &= ~EEEP_CR_EEEP_TX;
2999 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
3000 }
3001 
3002 static void rtl_set_eee_plus(struct r8152 *tp)
3003 {
3004 	if (rtl8152_get_speed(tp) & _10bps)
3005 		rtl_eee_plus_en(tp, true);
3006 	else
3007 		rtl_eee_plus_en(tp, false);
3008 }
3009 
3010 static void rxdy_gated_en(struct r8152 *tp, bool enable)
3011 {
3012 	u32 ocp_data;
3013 
3014 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
3015 	if (enable)
3016 		ocp_data |= RXDY_GATED_EN;
3017 	else
3018 		ocp_data &= ~RXDY_GATED_EN;
3019 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
3020 }
3021 
3022 static int rtl_start_rx(struct r8152 *tp)
3023 {
3024 	struct rx_agg *agg, *agg_next;
3025 	struct list_head tmp_list;
3026 	unsigned long flags;
3027 	int ret = 0, i = 0;
3028 
3029 	INIT_LIST_HEAD(&tmp_list);
3030 
3031 	spin_lock_irqsave(&tp->rx_lock, flags);
3032 
3033 	INIT_LIST_HEAD(&tp->rx_done);
3034 	INIT_LIST_HEAD(&tp->rx_used);
3035 
3036 	list_splice_init(&tp->rx_info, &tmp_list);
3037 
3038 	spin_unlock_irqrestore(&tp->rx_lock, flags);
3039 
3040 	list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
3041 		INIT_LIST_HEAD(&agg->list);
3042 
3043 		/* Only RTL8152_MAX_RX rx_agg need to be submitted. */
3044 		if (++i > RTL8152_MAX_RX) {
3045 			spin_lock_irqsave(&tp->rx_lock, flags);
3046 			list_add_tail(&agg->list, &tp->rx_used);
3047 			spin_unlock_irqrestore(&tp->rx_lock, flags);
3048 		} else if (unlikely(ret < 0)) {
3049 			spin_lock_irqsave(&tp->rx_lock, flags);
3050 			list_add_tail(&agg->list, &tp->rx_done);
3051 			spin_unlock_irqrestore(&tp->rx_lock, flags);
3052 		} else {
3053 			ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
3054 		}
3055 	}
3056 
3057 	spin_lock_irqsave(&tp->rx_lock, flags);
3058 	WARN_ON(!list_empty(&tp->rx_info));
3059 	list_splice(&tmp_list, &tp->rx_info);
3060 	spin_unlock_irqrestore(&tp->rx_lock, flags);
3061 
3062 	return ret;
3063 }
3064 
3065 static int rtl_stop_rx(struct r8152 *tp)
3066 {
3067 	struct rx_agg *agg, *agg_next;
3068 	struct list_head tmp_list;
3069 	unsigned long flags;
3070 
3071 	INIT_LIST_HEAD(&tmp_list);
3072 
3073 	/* The usb_kill_urb() couldn't be used in atomic.
3074 	 * Therefore, move the list of rx_info to a tmp one.
3075 	 * Then, list_for_each_entry_safe could be used without
3076 	 * spin lock.
3077 	 */
3078 
3079 	spin_lock_irqsave(&tp->rx_lock, flags);
3080 	list_splice_init(&tp->rx_info, &tmp_list);
3081 	spin_unlock_irqrestore(&tp->rx_lock, flags);
3082 
3083 	list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
3084 		/* At least RTL8152_MAX_RX rx_agg have the page_count being
3085 		 * equal to 1, so the other ones could be freed safely.
3086 		 */
3087 		if (page_count(agg->page) > 1)
3088 			free_rx_agg(tp, agg);
3089 		else
3090 			usb_kill_urb(agg->urb);
3091 	}
3092 
3093 	/* Move back the list of temp to the rx_info */
3094 	spin_lock_irqsave(&tp->rx_lock, flags);
3095 	WARN_ON(!list_empty(&tp->rx_info));
3096 	list_splice(&tmp_list, &tp->rx_info);
3097 	spin_unlock_irqrestore(&tp->rx_lock, flags);
3098 
3099 	while (!skb_queue_empty(&tp->rx_queue))
3100 		dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
3101 
3102 	return 0;
3103 }
3104 
3105 static void rtl_set_ifg(struct r8152 *tp, u16 speed)
3106 {
3107 	u32 ocp_data;
3108 
3109 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3110 	ocp_data &= ~IFG_MASK;
3111 	if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {
3112 		ocp_data |= IFG_144NS;
3113 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
3114 
3115 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
3116 		ocp_data &= ~TX10MIDLE_EN;
3117 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
3118 	} else {
3119 		ocp_data |= IFG_96NS;
3120 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
3121 
3122 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
3123 		ocp_data |= TX10MIDLE_EN;
3124 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
3125 	}
3126 }
3127 
3128 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
3129 {
3130 	ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
3131 		       OWN_UPDATE | OWN_CLEAR);
3132 }
3133 
3134 static int rtl_enable(struct r8152 *tp)
3135 {
3136 	u32 ocp_data;
3137 
3138 	r8152b_reset_packet_filter(tp);
3139 
3140 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
3141 	ocp_data |= CR_RE | CR_TE;
3142 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
3143 
3144 	switch (tp->version) {
3145 	case RTL_VER_01:
3146 	case RTL_VER_02:
3147 	case RTL_VER_03:
3148 	case RTL_VER_04:
3149 	case RTL_VER_05:
3150 	case RTL_VER_06:
3151 	case RTL_VER_07:
3152 		break;
3153 	default:
3154 		r8153b_rx_agg_chg_indicate(tp);
3155 		break;
3156 	}
3157 
3158 	rxdy_gated_en(tp, false);
3159 
3160 	return 0;
3161 }
3162 
3163 static int rtl8152_enable(struct r8152 *tp)
3164 {
3165 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3166 		return -ENODEV;
3167 
3168 	set_tx_qlen(tp);
3169 	rtl_set_eee_plus(tp);
3170 
3171 	return rtl_enable(tp);
3172 }
3173 
3174 static void r8153_set_rx_early_timeout(struct r8152 *tp)
3175 {
3176 	u32 ocp_data = tp->coalesce / 8;
3177 
3178 	switch (tp->version) {
3179 	case RTL_VER_03:
3180 	case RTL_VER_04:
3181 	case RTL_VER_05:
3182 	case RTL_VER_06:
3183 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3184 			       ocp_data);
3185 		break;
3186 
3187 	case RTL_VER_08:
3188 	case RTL_VER_09:
3189 	case RTL_VER_14:
3190 		/* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
3191 		 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
3192 		 */
3193 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3194 			       128 / 8);
3195 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3196 			       ocp_data);
3197 		break;
3198 
3199 	case RTL_VER_10:
3200 	case RTL_VER_11:
3201 	case RTL_VER_12:
3202 	case RTL_VER_13:
3203 	case RTL_VER_15:
3204 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3205 			       640 / 8);
3206 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3207 			       ocp_data);
3208 		break;
3209 
3210 	default:
3211 		break;
3212 	}
3213 }
3214 
3215 static void r8153_set_rx_early_size(struct r8152 *tp)
3216 {
3217 	u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
3218 
3219 	switch (tp->version) {
3220 	case RTL_VER_03:
3221 	case RTL_VER_04:
3222 	case RTL_VER_05:
3223 	case RTL_VER_06:
3224 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3225 			       ocp_data / 4);
3226 		break;
3227 	case RTL_VER_08:
3228 	case RTL_VER_09:
3229 	case RTL_VER_14:
3230 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3231 			       ocp_data / 8);
3232 		break;
3233 	case RTL_TEST_01:
3234 	case RTL_VER_10:
3235 	case RTL_VER_11:
3236 	case RTL_VER_12:
3237 	case RTL_VER_13:
3238 	case RTL_VER_15:
3239 		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3240 			       ocp_data / 8);
3241 		break;
3242 	default:
3243 		WARN_ON_ONCE(1);
3244 		break;
3245 	}
3246 }
3247 
3248 static int rtl8153_enable(struct r8152 *tp)
3249 {
3250 	u32 ocp_data;
3251 
3252 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3253 		return -ENODEV;
3254 
3255 	set_tx_qlen(tp);
3256 	rtl_set_eee_plus(tp);
3257 	r8153_set_rx_early_timeout(tp);
3258 	r8153_set_rx_early_size(tp);
3259 
3260 	rtl_set_ifg(tp, rtl8152_get_speed(tp));
3261 
3262 	switch (tp->version) {
3263 	case RTL_VER_09:
3264 	case RTL_VER_14:
3265 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
3266 		ocp_data &= ~FC_PATCH_TASK;
3267 		ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3268 		usleep_range(1000, 2000);
3269 		ocp_data |= FC_PATCH_TASK;
3270 		ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3271 		break;
3272 	default:
3273 		break;
3274 	}
3275 
3276 	return rtl_enable(tp);
3277 }
3278 
3279 static void rtl_disable(struct r8152 *tp)
3280 {
3281 	u32 ocp_data;
3282 	int i;
3283 
3284 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
3285 		rtl_drop_queued_tx(tp);
3286 		return;
3287 	}
3288 
3289 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3290 	ocp_data &= ~RCR_ACPT_ALL;
3291 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3292 
3293 	rtl_drop_queued_tx(tp);
3294 
3295 	for (i = 0; i < RTL8152_MAX_TX; i++)
3296 		usb_kill_urb(tp->tx_info[i].urb);
3297 
3298 	rxdy_gated_en(tp, true);
3299 
3300 	for (i = 0; i < 1000; i++) {
3301 		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3302 			break;
3303 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3304 		if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
3305 			break;
3306 		usleep_range(1000, 2000);
3307 	}
3308 
3309 	for (i = 0; i < 1000; i++) {
3310 		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3311 			break;
3312 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
3313 			break;
3314 		usleep_range(1000, 2000);
3315 	}
3316 
3317 	rtl_stop_rx(tp);
3318 
3319 	rtl8152_nic_reset(tp);
3320 }
3321 
3322 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
3323 {
3324 	u32 ocp_data;
3325 
3326 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
3327 	if (enable)
3328 		ocp_data |= POWER_CUT;
3329 	else
3330 		ocp_data &= ~POWER_CUT;
3331 	ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
3332 
3333 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
3334 	ocp_data &= ~RESUME_INDICATE;
3335 	ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
3336 }
3337 
3338 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
3339 {
3340 	u32 ocp_data;
3341 
3342 	switch (tp->version) {
3343 	case RTL_VER_01:
3344 	case RTL_VER_02:
3345 	case RTL_VER_03:
3346 	case RTL_VER_04:
3347 	case RTL_VER_05:
3348 	case RTL_VER_06:
3349 	case RTL_VER_07:
3350 	case RTL_VER_08:
3351 	case RTL_VER_09:
3352 	case RTL_VER_14:
3353 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
3354 		if (enable)
3355 			ocp_data |= CPCR_RX_VLAN;
3356 		else
3357 			ocp_data &= ~CPCR_RX_VLAN;
3358 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
3359 		break;
3360 
3361 	case RTL_TEST_01:
3362 	case RTL_VER_10:
3363 	case RTL_VER_11:
3364 	case RTL_VER_12:
3365 	case RTL_VER_13:
3366 	case RTL_VER_15:
3367 	default:
3368 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
3369 		if (enable)
3370 			ocp_data |= OUTER_VLAN | INNER_VLAN;
3371 		else
3372 			ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
3373 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data);
3374 		break;
3375 	}
3376 }
3377 
3378 static int rtl8152_set_features(struct net_device *dev,
3379 				netdev_features_t features)
3380 {
3381 	netdev_features_t changed = features ^ dev->features;
3382 	struct r8152 *tp = netdev_priv(dev);
3383 	int ret;
3384 
3385 	ret = usb_autopm_get_interface(tp->intf);
3386 	if (ret < 0)
3387 		goto out;
3388 
3389 	mutex_lock(&tp->control);
3390 
3391 	if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
3392 		if (features & NETIF_F_HW_VLAN_CTAG_RX)
3393 			rtl_rx_vlan_en(tp, true);
3394 		else
3395 			rtl_rx_vlan_en(tp, false);
3396 	}
3397 
3398 	mutex_unlock(&tp->control);
3399 
3400 	usb_autopm_put_interface(tp->intf);
3401 
3402 out:
3403 	return ret;
3404 }
3405 
3406 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
3407 
3408 static u32 __rtl_get_wol(struct r8152 *tp)
3409 {
3410 	u32 ocp_data;
3411 	u32 wolopts = 0;
3412 
3413 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3414 	if (ocp_data & LINK_ON_WAKE_EN)
3415 		wolopts |= WAKE_PHY;
3416 
3417 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3418 	if (ocp_data & UWF_EN)
3419 		wolopts |= WAKE_UCAST;
3420 	if (ocp_data & BWF_EN)
3421 		wolopts |= WAKE_BCAST;
3422 	if (ocp_data & MWF_EN)
3423 		wolopts |= WAKE_MCAST;
3424 
3425 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3426 	if (ocp_data & MAGIC_EN)
3427 		wolopts |= WAKE_MAGIC;
3428 
3429 	return wolopts;
3430 }
3431 
3432 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3433 {
3434 	u32 ocp_data;
3435 
3436 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3437 
3438 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3439 	ocp_data &= ~LINK_ON_WAKE_EN;
3440 	if (wolopts & WAKE_PHY)
3441 		ocp_data |= LINK_ON_WAKE_EN;
3442 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3443 
3444 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3445 	ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3446 	if (wolopts & WAKE_UCAST)
3447 		ocp_data |= UWF_EN;
3448 	if (wolopts & WAKE_BCAST)
3449 		ocp_data |= BWF_EN;
3450 	if (wolopts & WAKE_MCAST)
3451 		ocp_data |= MWF_EN;
3452 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3453 
3454 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3455 
3456 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3457 	ocp_data &= ~MAGIC_EN;
3458 	if (wolopts & WAKE_MAGIC)
3459 		ocp_data |= MAGIC_EN;
3460 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3461 
3462 	if (wolopts & WAKE_ANY)
3463 		device_set_wakeup_enable(&tp->udev->dev, true);
3464 	else
3465 		device_set_wakeup_enable(&tp->udev->dev, false);
3466 }
3467 
3468 static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)
3469 {
3470 	u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3471 
3472 	/* MAC clock speed down */
3473 	if (enable)
3474 		ocp_data |= MAC_CLK_SPDWN_EN;
3475 	else
3476 		ocp_data &= ~MAC_CLK_SPDWN_EN;
3477 
3478 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3479 }
3480 
3481 static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)
3482 {
3483 	u32 ocp_data;
3484 
3485 	/* MAC clock speed down */
3486 	if (enable) {
3487 		/* aldps_spdwn_ratio, tp10_spdwn_ratio */
3488 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3489 			       0x0403);
3490 
3491 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3492 		ocp_data &= ~EEE_SPDWN_RATIO_MASK;
3493 		ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */
3494 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3495 	} else {
3496 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3497 		ocp_data &= ~MAC_CLK_SPDWN_EN;
3498 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3499 	}
3500 }
3501 
3502 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3503 {
3504 	u8 u1u2[8];
3505 
3506 	if (enable)
3507 		memset(u1u2, 0xff, sizeof(u1u2));
3508 	else
3509 		memset(u1u2, 0x00, sizeof(u1u2));
3510 
3511 	usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3512 }
3513 
3514 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3515 {
3516 	u32 ocp_data;
3517 
3518 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3519 	if (enable)
3520 		ocp_data |= LPM_U1U2_EN;
3521 	else
3522 		ocp_data &= ~LPM_U1U2_EN;
3523 
3524 	ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3525 }
3526 
3527 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3528 {
3529 	u32 ocp_data;
3530 
3531 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3532 	if (enable)
3533 		ocp_data |= U2P3_ENABLE;
3534 	else
3535 		ocp_data &= ~U2P3_ENABLE;
3536 	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3537 }
3538 
3539 static void r8153b_ups_flags(struct r8152 *tp)
3540 {
3541 	u32 ups_flags = 0;
3542 
3543 	if (tp->ups_info.green)
3544 		ups_flags |= UPS_FLAGS_EN_GREEN;
3545 
3546 	if (tp->ups_info.aldps)
3547 		ups_flags |= UPS_FLAGS_EN_ALDPS;
3548 
3549 	if (tp->ups_info.eee)
3550 		ups_flags |= UPS_FLAGS_EN_EEE;
3551 
3552 	if (tp->ups_info.flow_control)
3553 		ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3554 
3555 	if (tp->ups_info.eee_ckdiv)
3556 		ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3557 
3558 	if (tp->ups_info.eee_cmod_lv)
3559 		ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3560 
3561 	if (tp->ups_info.r_tune)
3562 		ups_flags |= UPS_FLAGS_R_TUNE;
3563 
3564 	if (tp->ups_info._10m_ckdiv)
3565 		ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3566 
3567 	if (tp->ups_info.eee_plloff_100)
3568 		ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3569 
3570 	if (tp->ups_info.eee_plloff_giga)
3571 		ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3572 
3573 	if (tp->ups_info._250m_ckdiv)
3574 		ups_flags |= UPS_FLAGS_250M_CKDIV;
3575 
3576 	if (tp->ups_info.ctap_short_off)
3577 		ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3578 
3579 	switch (tp->ups_info.speed_duplex) {
3580 	case NWAY_10M_HALF:
3581 		ups_flags |= ups_flags_speed(1);
3582 		break;
3583 	case NWAY_10M_FULL:
3584 		ups_flags |= ups_flags_speed(2);
3585 		break;
3586 	case NWAY_100M_HALF:
3587 		ups_flags |= ups_flags_speed(3);
3588 		break;
3589 	case NWAY_100M_FULL:
3590 		ups_flags |= ups_flags_speed(4);
3591 		break;
3592 	case NWAY_1000M_FULL:
3593 		ups_flags |= ups_flags_speed(5);
3594 		break;
3595 	case FORCE_10M_HALF:
3596 		ups_flags |= ups_flags_speed(6);
3597 		break;
3598 	case FORCE_10M_FULL:
3599 		ups_flags |= ups_flags_speed(7);
3600 		break;
3601 	case FORCE_100M_HALF:
3602 		ups_flags |= ups_flags_speed(8);
3603 		break;
3604 	case FORCE_100M_FULL:
3605 		ups_flags |= ups_flags_speed(9);
3606 		break;
3607 	default:
3608 		break;
3609 	}
3610 
3611 	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3612 }
3613 
3614 static void r8156_ups_flags(struct r8152 *tp)
3615 {
3616 	u32 ups_flags = 0;
3617 
3618 	if (tp->ups_info.green)
3619 		ups_flags |= UPS_FLAGS_EN_GREEN;
3620 
3621 	if (tp->ups_info.aldps)
3622 		ups_flags |= UPS_FLAGS_EN_ALDPS;
3623 
3624 	if (tp->ups_info.eee)
3625 		ups_flags |= UPS_FLAGS_EN_EEE;
3626 
3627 	if (tp->ups_info.flow_control)
3628 		ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3629 
3630 	if (tp->ups_info.eee_ckdiv)
3631 		ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3632 
3633 	if (tp->ups_info._10m_ckdiv)
3634 		ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3635 
3636 	if (tp->ups_info.eee_plloff_100)
3637 		ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3638 
3639 	if (tp->ups_info.eee_plloff_giga)
3640 		ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3641 
3642 	if (tp->ups_info._250m_ckdiv)
3643 		ups_flags |= UPS_FLAGS_250M_CKDIV;
3644 
3645 	switch (tp->ups_info.speed_duplex) {
3646 	case FORCE_10M_HALF:
3647 		ups_flags |= ups_flags_speed(0);
3648 		break;
3649 	case FORCE_10M_FULL:
3650 		ups_flags |= ups_flags_speed(1);
3651 		break;
3652 	case FORCE_100M_HALF:
3653 		ups_flags |= ups_flags_speed(2);
3654 		break;
3655 	case FORCE_100M_FULL:
3656 		ups_flags |= ups_flags_speed(3);
3657 		break;
3658 	case NWAY_10M_HALF:
3659 		ups_flags |= ups_flags_speed(4);
3660 		break;
3661 	case NWAY_10M_FULL:
3662 		ups_flags |= ups_flags_speed(5);
3663 		break;
3664 	case NWAY_100M_HALF:
3665 		ups_flags |= ups_flags_speed(6);
3666 		break;
3667 	case NWAY_100M_FULL:
3668 		ups_flags |= ups_flags_speed(7);
3669 		break;
3670 	case NWAY_1000M_FULL:
3671 		ups_flags |= ups_flags_speed(8);
3672 		break;
3673 	case NWAY_2500M_FULL:
3674 		ups_flags |= ups_flags_speed(9);
3675 		break;
3676 	default:
3677 		break;
3678 	}
3679 
3680 	switch (tp->ups_info.lite_mode) {
3681 	case 1:
3682 		ups_flags |= 0 << 5;
3683 		break;
3684 	case 2:
3685 		ups_flags |= 2 << 5;
3686 		break;
3687 	case 0:
3688 	default:
3689 		ups_flags |= 1 << 5;
3690 		break;
3691 	}
3692 
3693 	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3694 }
3695 
3696 static void rtl_green_en(struct r8152 *tp, bool enable)
3697 {
3698 	u16 data;
3699 
3700 	data = sram_read(tp, SRAM_GREEN_CFG);
3701 	if (enable)
3702 		data |= GREEN_ETH_EN;
3703 	else
3704 		data &= ~GREEN_ETH_EN;
3705 	sram_write(tp, SRAM_GREEN_CFG, data);
3706 
3707 	tp->ups_info.green = enable;
3708 }
3709 
3710 static void r8153b_green_en(struct r8152 *tp, bool enable)
3711 {
3712 	if (enable) {
3713 		sram_write(tp, 0x8045, 0);	/* 10M abiq&ldvbias */
3714 		sram_write(tp, 0x804d, 0x1222);	/* 100M short abiq&ldvbias */
3715 		sram_write(tp, 0x805d, 0x0022);	/* 1000M short abiq&ldvbias */
3716 	} else {
3717 		sram_write(tp, 0x8045, 0x2444);	/* 10M abiq&ldvbias */
3718 		sram_write(tp, 0x804d, 0x2444);	/* 100M short abiq&ldvbias */
3719 		sram_write(tp, 0x805d, 0x2444);	/* 1000M short abiq&ldvbias */
3720 	}
3721 
3722 	rtl_green_en(tp, true);
3723 }
3724 
3725 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3726 {
3727 	u16 data;
3728 	int i;
3729 
3730 	for (i = 0; i < 500; i++) {
3731 		data = ocp_reg_read(tp, OCP_PHY_STATUS);
3732 		data &= PHY_STAT_MASK;
3733 		if (desired) {
3734 			if (data == desired)
3735 				break;
3736 		} else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3737 			   data == PHY_STAT_EXT_INIT) {
3738 			break;
3739 		}
3740 
3741 		msleep(20);
3742 		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3743 			break;
3744 	}
3745 
3746 	return data;
3747 }
3748 
3749 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3750 {
3751 	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3752 
3753 	if (enable) {
3754 		r8153b_ups_flags(tp);
3755 
3756 		ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3757 		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3758 
3759 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3760 		ocp_data |= UPS_FORCE_PWR_DOWN;
3761 		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3762 	} else {
3763 		ocp_data &= ~(UPS_EN | USP_PREWAKE);
3764 		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3765 
3766 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3767 		ocp_data &= ~UPS_FORCE_PWR_DOWN;
3768 		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3769 
3770 		if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3771 			int i;
3772 
3773 			for (i = 0; i < 500; i++) {
3774 				if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3775 					return;
3776 				if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3777 				    AUTOLOAD_DONE)
3778 					break;
3779 				msleep(20);
3780 			}
3781 
3782 			tp->rtl_ops.hw_phy_cfg(tp);
3783 
3784 			rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3785 					  tp->duplex, tp->advertising);
3786 		}
3787 	}
3788 }
3789 
3790 static void r8153c_ups_en(struct r8152 *tp, bool enable)
3791 {
3792 	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3793 
3794 	if (enable) {
3795 		r8153b_ups_flags(tp);
3796 
3797 		ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3798 		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3799 
3800 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3801 		ocp_data |= UPS_FORCE_PWR_DOWN;
3802 		ocp_data &= ~BIT(7);
3803 		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3804 	} else {
3805 		ocp_data &= ~(UPS_EN | USP_PREWAKE);
3806 		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3807 
3808 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3809 		ocp_data &= ~UPS_FORCE_PWR_DOWN;
3810 		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3811 
3812 		if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3813 			int i;
3814 
3815 			for (i = 0; i < 500; i++) {
3816 				if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3817 					return;
3818 				if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3819 				    AUTOLOAD_DONE)
3820 					break;
3821 				msleep(20);
3822 			}
3823 
3824 			tp->rtl_ops.hw_phy_cfg(tp);
3825 
3826 			rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3827 					  tp->duplex, tp->advertising);
3828 		}
3829 
3830 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3831 
3832 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3833 		ocp_data |= BIT(8);
3834 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3835 
3836 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3837 	}
3838 }
3839 
3840 static void r8156_ups_en(struct r8152 *tp, bool enable)
3841 {
3842 	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3843 
3844 	if (enable) {
3845 		r8156_ups_flags(tp);
3846 
3847 		ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3848 		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3849 
3850 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3851 		ocp_data |= UPS_FORCE_PWR_DOWN;
3852 		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3853 
3854 		switch (tp->version) {
3855 		case RTL_VER_13:
3856 		case RTL_VER_15:
3857 			ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
3858 			ocp_data &= ~OOBS_POLLING;
3859 			ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);
3860 			break;
3861 		default:
3862 			break;
3863 		}
3864 	} else {
3865 		ocp_data &= ~(UPS_EN | USP_PREWAKE);
3866 		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3867 
3868 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3869 		ocp_data &= ~UPS_FORCE_PWR_DOWN;
3870 		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3871 
3872 		if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3873 			tp->rtl_ops.hw_phy_cfg(tp);
3874 
3875 			rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3876 					  tp->duplex, tp->advertising);
3877 		}
3878 	}
3879 }
3880 
3881 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3882 {
3883 	u32 ocp_data;
3884 
3885 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3886 	if (enable)
3887 		ocp_data |= PWR_EN | PHASE2_EN;
3888 	else
3889 		ocp_data &= ~(PWR_EN | PHASE2_EN);
3890 	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3891 
3892 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3893 	ocp_data &= ~PCUT_STATUS;
3894 	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3895 }
3896 
3897 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3898 {
3899 	u32 ocp_data;
3900 
3901 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3902 	if (enable)
3903 		ocp_data |= PWR_EN | PHASE2_EN;
3904 	else
3905 		ocp_data &= ~PWR_EN;
3906 	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3907 
3908 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3909 	ocp_data &= ~PCUT_STATUS;
3910 	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3911 }
3912 
3913 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3914 {
3915 	u32 ocp_data;
3916 
3917 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3918 	if (enable)
3919 		ocp_data |= UPCOMING_RUNTIME_D3;
3920 	else
3921 		ocp_data &= ~UPCOMING_RUNTIME_D3;
3922 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3923 
3924 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3925 	ocp_data &= ~LINK_CHG_EVENT;
3926 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3927 
3928 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3929 	ocp_data &= ~LINK_CHANGE_FLAG;
3930 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3931 }
3932 
3933 static bool rtl_can_wakeup(struct r8152 *tp)
3934 {
3935 	struct usb_device *udev = tp->udev;
3936 
3937 	return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3938 }
3939 
3940 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3941 {
3942 	if (enable) {
3943 		u32 ocp_data;
3944 
3945 		__rtl_set_wol(tp, WAKE_ANY);
3946 
3947 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3948 
3949 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3950 		ocp_data |= LINK_OFF_WAKE_EN;
3951 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3952 
3953 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3954 	} else {
3955 		u32 ocp_data;
3956 
3957 		__rtl_set_wol(tp, tp->saved_wolopts);
3958 
3959 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3960 
3961 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3962 		ocp_data &= ~LINK_OFF_WAKE_EN;
3963 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3964 
3965 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3966 	}
3967 }
3968 
3969 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3970 {
3971 	if (enable) {
3972 		r8153_u1u2en(tp, false);
3973 		r8153_u2p3en(tp, false);
3974 		rtl_runtime_suspend_enable(tp, true);
3975 	} else {
3976 		rtl_runtime_suspend_enable(tp, false);
3977 
3978 		switch (tp->version) {
3979 		case RTL_VER_03:
3980 		case RTL_VER_04:
3981 			break;
3982 		case RTL_VER_05:
3983 		case RTL_VER_06:
3984 		default:
3985 			r8153_u2p3en(tp, true);
3986 			break;
3987 		}
3988 
3989 		r8153_u1u2en(tp, true);
3990 	}
3991 }
3992 
3993 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3994 {
3995 	if (enable) {
3996 		r8153_queue_wake(tp, true);
3997 		r8153b_u1u2en(tp, false);
3998 		r8153_u2p3en(tp, false);
3999 		rtl_runtime_suspend_enable(tp, true);
4000 		r8153b_ups_en(tp, true);
4001 	} else {
4002 		r8153b_ups_en(tp, false);
4003 		r8153_queue_wake(tp, false);
4004 		rtl_runtime_suspend_enable(tp, false);
4005 		if (tp->udev->speed >= USB_SPEED_SUPER)
4006 			r8153b_u1u2en(tp, true);
4007 	}
4008 }
4009 
4010 static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)
4011 {
4012 	if (enable) {
4013 		r8153_queue_wake(tp, true);
4014 		r8153b_u1u2en(tp, false);
4015 		r8153_u2p3en(tp, false);
4016 		rtl_runtime_suspend_enable(tp, true);
4017 		r8153c_ups_en(tp, true);
4018 	} else {
4019 		r8153c_ups_en(tp, false);
4020 		r8153_queue_wake(tp, false);
4021 		rtl_runtime_suspend_enable(tp, false);
4022 		r8153b_u1u2en(tp, true);
4023 	}
4024 }
4025 
4026 static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)
4027 {
4028 	if (enable) {
4029 		r8153_queue_wake(tp, true);
4030 		r8153b_u1u2en(tp, false);
4031 		r8153_u2p3en(tp, false);
4032 		rtl_runtime_suspend_enable(tp, true);
4033 	} else {
4034 		r8153_queue_wake(tp, false);
4035 		rtl_runtime_suspend_enable(tp, false);
4036 		r8153_u2p3en(tp, true);
4037 		if (tp->udev->speed >= USB_SPEED_SUPER)
4038 			r8153b_u1u2en(tp, true);
4039 	}
4040 }
4041 
4042 static void r8153_teredo_off(struct r8152 *tp)
4043 {
4044 	u32 ocp_data;
4045 
4046 	switch (tp->version) {
4047 	case RTL_VER_01:
4048 	case RTL_VER_02:
4049 	case RTL_VER_03:
4050 	case RTL_VER_04:
4051 	case RTL_VER_05:
4052 	case RTL_VER_06:
4053 	case RTL_VER_07:
4054 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4055 		ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
4056 			      OOB_TEREDO_EN);
4057 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
4058 		break;
4059 
4060 	case RTL_VER_08:
4061 	case RTL_VER_09:
4062 	case RTL_TEST_01:
4063 	case RTL_VER_10:
4064 	case RTL_VER_11:
4065 	case RTL_VER_12:
4066 	case RTL_VER_13:
4067 	case RTL_VER_14:
4068 	case RTL_VER_15:
4069 	default:
4070 		/* The bit 0 ~ 7 are relative with teredo settings. They are
4071 		 * W1C (write 1 to clear), so set all 1 to disable it.
4072 		 */
4073 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
4074 		break;
4075 	}
4076 
4077 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
4078 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
4079 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
4080 }
4081 
4082 static void rtl_reset_bmu(struct r8152 *tp)
4083 {
4084 	u32 ocp_data;
4085 
4086 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
4087 	ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
4088 	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
4089 	ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
4090 	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
4091 }
4092 
4093 /* Clear the bp to stop the firmware before loading a new one */
4094 static void rtl_clear_bp(struct r8152 *tp, u16 type)
4095 {
4096 	u16 bp[16] = {0};
4097 	u16 bp_num;
4098 
4099 	switch (tp->version) {
4100 	case RTL_VER_08:
4101 	case RTL_VER_09:
4102 	case RTL_VER_10:
4103 	case RTL_VER_11:
4104 	case RTL_VER_12:
4105 	case RTL_VER_13:
4106 	case RTL_VER_15:
4107 		if (type == MCU_TYPE_USB) {
4108 			ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
4109 			bp_num = 16;
4110 			break;
4111 		}
4112 		fallthrough;
4113 	case RTL_VER_03:
4114 	case RTL_VER_04:
4115 	case RTL_VER_05:
4116 	case RTL_VER_06:
4117 		ocp_write_byte(tp, type, PLA_BP_EN, 0);
4118 		fallthrough;
4119 	case RTL_VER_01:
4120 	case RTL_VER_02:
4121 	case RTL_VER_07:
4122 		bp_num = 8;
4123 		break;
4124 	case RTL_VER_14:
4125 	default:
4126 		ocp_write_word(tp, type, USB_BP2_EN, 0);
4127 		bp_num = 16;
4128 		break;
4129 	}
4130 
4131 	generic_ocp_write(tp, PLA_BP_0, BYTE_EN_DWORD, bp_num << 1, bp, type);
4132 
4133 	/* wait 3 ms to make sure the firmware is stopped */
4134 	usleep_range(3000, 6000);
4135 	ocp_write_word(tp, type, PLA_BP_BA, 0);
4136 }
4137 
4138 static inline void rtl_reset_ocp_base(struct r8152 *tp)
4139 {
4140 	tp->ocp_base = -1;
4141 }
4142 
4143 static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
4144 {
4145 	u16 data, check;
4146 	int i;
4147 
4148 	data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
4149 	if (request) {
4150 		data |= PATCH_REQUEST;
4151 		check = 0;
4152 	} else {
4153 		data &= ~PATCH_REQUEST;
4154 		check = PATCH_READY;
4155 	}
4156 	ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
4157 
4158 	for (i = 0; wait && i < 5000; i++) {
4159 		u32 ocp_data;
4160 
4161 		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
4162 			return -ENODEV;
4163 
4164 		usleep_range(1000, 2000);
4165 		ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
4166 		if ((ocp_data & PATCH_READY) ^ check)
4167 			break;
4168 	}
4169 
4170 	if (request && wait &&
4171 	    !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
4172 		dev_err(&tp->intf->dev, "PHY patch request fail\n");
4173 		rtl_phy_patch_request(tp, false, false);
4174 		return -ETIME;
4175 	} else {
4176 		return 0;
4177 	}
4178 }
4179 
4180 static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)
4181 {
4182 	if (patch_key && key_addr) {
4183 		sram_write(tp, key_addr, patch_key);
4184 		sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
4185 	} else if (key_addr) {
4186 		u16 data;
4187 
4188 		sram_write(tp, 0x0000, 0x0000);
4189 
4190 		data = ocp_reg_read(tp, OCP_PHY_LOCK);
4191 		data &= ~PATCH_LOCK;
4192 		ocp_reg_write(tp, OCP_PHY_LOCK, data);
4193 
4194 		sram_write(tp, key_addr, 0x0000);
4195 	} else {
4196 		WARN_ON_ONCE(1);
4197 	}
4198 }
4199 
4200 static int
4201 rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)
4202 {
4203 	if (rtl_phy_patch_request(tp, true, wait))
4204 		return -ETIME;
4205 
4206 	rtl_patch_key_set(tp, key_addr, patch_key);
4207 
4208 	return 0;
4209 }
4210 
4211 static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)
4212 {
4213 	rtl_patch_key_set(tp, key_addr, 0);
4214 
4215 	rtl_phy_patch_request(tp, false, wait);
4216 
4217 	return 0;
4218 }
4219 
4220 static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy)
4221 {
4222 	u16 fw_offset;
4223 	u32 length;
4224 	bool rc = false;
4225 
4226 	switch (tp->version) {
4227 	case RTL_VER_01:
4228 	case RTL_VER_02:
4229 	case RTL_VER_03:
4230 	case RTL_VER_04:
4231 	case RTL_VER_05:
4232 	case RTL_VER_06:
4233 	case RTL_VER_07:
4234 	case RTL_VER_08:
4235 	case RTL_VER_09:
4236 	case RTL_VER_10:
4237 	case RTL_VER_11:
4238 	case RTL_VER_12:
4239 	case RTL_VER_14:
4240 		goto out;
4241 	case RTL_VER_13:
4242 	case RTL_VER_15:
4243 	default:
4244 		break;
4245 	}
4246 
4247 	fw_offset = __le16_to_cpu(phy->fw_offset);
4248 	length = __le32_to_cpu(phy->blk_hdr.length);
4249 	if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4250 		dev_err(&tp->intf->dev, "invalid fw_offset\n");
4251 		goto out;
4252 	}
4253 
4254 	length -= fw_offset;
4255 	if (length & 3) {
4256 		dev_err(&tp->intf->dev, "invalid block length\n");
4257 		goto out;
4258 	}
4259 
4260 	if (__le16_to_cpu(phy->fw_reg) != 0x9A00) {
4261 		dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4262 		goto out;
4263 	}
4264 
4265 	rc = true;
4266 out:
4267 	return rc;
4268 }
4269 
4270 static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver)
4271 {
4272 	bool rc = false;
4273 
4274 	switch (tp->version) {
4275 	case RTL_VER_10:
4276 	case RTL_VER_11:
4277 	case RTL_VER_12:
4278 	case RTL_VER_13:
4279 	case RTL_VER_15:
4280 		break;
4281 	default:
4282 		goto out;
4283 	}
4284 
4285 	if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) {
4286 		dev_err(&tp->intf->dev, "invalid block length\n");
4287 		goto out;
4288 	}
4289 
4290 	if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) {
4291 		dev_err(&tp->intf->dev, "invalid phy ver addr\n");
4292 		goto out;
4293 	}
4294 
4295 	rc = true;
4296 out:
4297 	return rc;
4298 }
4299 
4300 static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix)
4301 {
4302 	bool rc = false;
4303 
4304 	switch (tp->version) {
4305 	case RTL_VER_10:
4306 	case RTL_VER_11:
4307 	case RTL_VER_12:
4308 	case RTL_VER_13:
4309 	case RTL_VER_15:
4310 		break;
4311 	default:
4312 		goto out;
4313 	}
4314 
4315 	if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) {
4316 		dev_err(&tp->intf->dev, "invalid block length\n");
4317 		goto out;
4318 	}
4319 
4320 	if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD ||
4321 	    __le16_to_cpu(fix->setting.data) != BIT(7)) {
4322 		dev_err(&tp->intf->dev, "invalid phy fixup\n");
4323 		goto out;
4324 	}
4325 
4326 	rc = true;
4327 out:
4328 	return rc;
4329 }
4330 
4331 static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy)
4332 {
4333 	u16 fw_offset;
4334 	u32 length;
4335 	bool rc = false;
4336 
4337 	switch (tp->version) {
4338 	case RTL_VER_10:
4339 	case RTL_VER_11:
4340 	case RTL_VER_12:
4341 	case RTL_VER_13:
4342 	case RTL_VER_15:
4343 		break;
4344 	default:
4345 		goto out;
4346 	}
4347 
4348 	fw_offset = __le16_to_cpu(phy->fw_offset);
4349 	length = __le32_to_cpu(phy->blk_hdr.length);
4350 	if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4351 		dev_err(&tp->intf->dev, "invalid fw_offset\n");
4352 		goto out;
4353 	}
4354 
4355 	length -= fw_offset;
4356 	if (length & 1) {
4357 		dev_err(&tp->intf->dev, "invalid block length\n");
4358 		goto out;
4359 	}
4360 
4361 	if (phy->pre_num > 2) {
4362 		dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num);
4363 		goto out;
4364 	}
4365 
4366 	if (phy->bp_num > 8) {
4367 		dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num);
4368 		goto out;
4369 	}
4370 
4371 	rc = true;
4372 out:
4373 	return rc;
4374 }
4375 
4376 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
4377 {
4378 	u32 length;
4379 	u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
4380 	bool rc = false;
4381 
4382 	switch (tp->version) {
4383 	case RTL_VER_04:
4384 	case RTL_VER_05:
4385 	case RTL_VER_06:
4386 		fw_reg = 0xa014;
4387 		ba_reg = 0xa012;
4388 		patch_en_addr = 0xa01a;
4389 		mode_reg = 0xb820;
4390 		bp_start = 0xa000;
4391 		break;
4392 	default:
4393 		goto out;
4394 	}
4395 
4396 	fw_offset = __le16_to_cpu(phy->fw_offset);
4397 	if (fw_offset < sizeof(*phy)) {
4398 		dev_err(&tp->intf->dev, "fw_offset too small\n");
4399 		goto out;
4400 	}
4401 
4402 	length = __le32_to_cpu(phy->blk_hdr.length);
4403 	if (length < fw_offset) {
4404 		dev_err(&tp->intf->dev, "invalid fw_offset\n");
4405 		goto out;
4406 	}
4407 
4408 	length -= __le16_to_cpu(phy->fw_offset);
4409 	if (!length || (length & 1)) {
4410 		dev_err(&tp->intf->dev, "invalid block length\n");
4411 		goto out;
4412 	}
4413 
4414 	if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
4415 		dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4416 		goto out;
4417 	}
4418 
4419 	if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
4420 		dev_err(&tp->intf->dev, "invalid base address register\n");
4421 		goto out;
4422 	}
4423 
4424 	if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
4425 		dev_err(&tp->intf->dev,
4426 			"invalid patch mode enabled register\n");
4427 		goto out;
4428 	}
4429 
4430 	if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
4431 		dev_err(&tp->intf->dev,
4432 			"invalid register to switch the mode\n");
4433 		goto out;
4434 	}
4435 
4436 	if (__le16_to_cpu(phy->bp_start) != bp_start) {
4437 		dev_err(&tp->intf->dev,
4438 			"invalid start register of break point\n");
4439 		goto out;
4440 	}
4441 
4442 	if (__le16_to_cpu(phy->bp_num) > 4) {
4443 		dev_err(&tp->intf->dev, "invalid break point number\n");
4444 		goto out;
4445 	}
4446 
4447 	rc = true;
4448 out:
4449 	return rc;
4450 }
4451 
4452 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
4453 {
4454 	u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
4455 	bool rc = false;
4456 	u32 length, type;
4457 	int i, max_bp;
4458 
4459 	type = __le32_to_cpu(mac->blk_hdr.type);
4460 	if (type == RTL_FW_PLA) {
4461 		switch (tp->version) {
4462 		case RTL_VER_01:
4463 		case RTL_VER_02:
4464 		case RTL_VER_07:
4465 			fw_reg = 0xf800;
4466 			bp_ba_addr = PLA_BP_BA;
4467 			bp_en_addr = 0;
4468 			bp_start = PLA_BP_0;
4469 			max_bp = 8;
4470 			break;
4471 		case RTL_VER_03:
4472 		case RTL_VER_04:
4473 		case RTL_VER_05:
4474 		case RTL_VER_06:
4475 		case RTL_VER_08:
4476 		case RTL_VER_09:
4477 		case RTL_VER_11:
4478 		case RTL_VER_12:
4479 		case RTL_VER_13:
4480 		case RTL_VER_15:
4481 			fw_reg = 0xf800;
4482 			bp_ba_addr = PLA_BP_BA;
4483 			bp_en_addr = PLA_BP_EN;
4484 			bp_start = PLA_BP_0;
4485 			max_bp = 8;
4486 			break;
4487 		case RTL_VER_14:
4488 			fw_reg = 0xf800;
4489 			bp_ba_addr = PLA_BP_BA;
4490 			bp_en_addr = USB_BP2_EN;
4491 			bp_start = PLA_BP_0;
4492 			max_bp = 16;
4493 			break;
4494 		default:
4495 			goto out;
4496 		}
4497 	} else if (type == RTL_FW_USB) {
4498 		switch (tp->version) {
4499 		case RTL_VER_03:
4500 		case RTL_VER_04:
4501 		case RTL_VER_05:
4502 		case RTL_VER_06:
4503 			fw_reg = 0xf800;
4504 			bp_ba_addr = USB_BP_BA;
4505 			bp_en_addr = USB_BP_EN;
4506 			bp_start = USB_BP_0;
4507 			max_bp = 8;
4508 			break;
4509 		case RTL_VER_08:
4510 		case RTL_VER_09:
4511 		case RTL_VER_11:
4512 		case RTL_VER_12:
4513 		case RTL_VER_13:
4514 		case RTL_VER_14:
4515 		case RTL_VER_15:
4516 			fw_reg = 0xe600;
4517 			bp_ba_addr = USB_BP_BA;
4518 			bp_en_addr = USB_BP2_EN;
4519 			bp_start = USB_BP_0;
4520 			max_bp = 16;
4521 			break;
4522 		case RTL_VER_01:
4523 		case RTL_VER_02:
4524 		case RTL_VER_07:
4525 		default:
4526 			goto out;
4527 		}
4528 	} else {
4529 		goto out;
4530 	}
4531 
4532 	fw_offset = __le16_to_cpu(mac->fw_offset);
4533 	if (fw_offset < sizeof(*mac)) {
4534 		dev_err(&tp->intf->dev, "fw_offset too small\n");
4535 		goto out;
4536 	}
4537 
4538 	length = __le32_to_cpu(mac->blk_hdr.length);
4539 	if (length < fw_offset) {
4540 		dev_err(&tp->intf->dev, "invalid fw_offset\n");
4541 		goto out;
4542 	}
4543 
4544 	length -= fw_offset;
4545 	if (length < 4 || (length & 3)) {
4546 		dev_err(&tp->intf->dev, "invalid block length\n");
4547 		goto out;
4548 	}
4549 
4550 	if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
4551 		dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4552 		goto out;
4553 	}
4554 
4555 	if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
4556 		dev_err(&tp->intf->dev, "invalid base address register\n");
4557 		goto out;
4558 	}
4559 
4560 	if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
4561 		dev_err(&tp->intf->dev, "invalid enabled mask register\n");
4562 		goto out;
4563 	}
4564 
4565 	if (__le16_to_cpu(mac->bp_start) != bp_start) {
4566 		dev_err(&tp->intf->dev,
4567 			"invalid start register of break point\n");
4568 		goto out;
4569 	}
4570 
4571 	if (__le16_to_cpu(mac->bp_num) > max_bp) {
4572 		dev_err(&tp->intf->dev, "invalid break point number\n");
4573 		goto out;
4574 	}
4575 
4576 	for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
4577 		if (mac->bp[i]) {
4578 			dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
4579 			goto out;
4580 		}
4581 	}
4582 
4583 	rc = true;
4584 out:
4585 	return rc;
4586 }
4587 
4588 /* Verify the checksum for the firmware file. It is calculated from the version
4589  * field to the end of the file. Compare the result with the checksum field to
4590  * make sure the file is correct.
4591  */
4592 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
4593 				       struct fw_header *fw_hdr, size_t size)
4594 {
4595 	unsigned char checksum[sizeof(fw_hdr->checksum)];
4596 	struct crypto_shash *alg;
4597 	struct shash_desc *sdesc;
4598 	size_t len;
4599 	long rc;
4600 
4601 	alg = crypto_alloc_shash("sha256", 0, 0);
4602 	if (IS_ERR(alg)) {
4603 		rc = PTR_ERR(alg);
4604 		goto out;
4605 	}
4606 
4607 	if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
4608 		rc = -EFAULT;
4609 		dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
4610 			crypto_shash_digestsize(alg));
4611 		goto free_shash;
4612 	}
4613 
4614 	len = sizeof(*sdesc) + crypto_shash_descsize(alg);
4615 	sdesc = kmalloc(len, GFP_KERNEL);
4616 	if (!sdesc) {
4617 		rc = -ENOMEM;
4618 		goto free_shash;
4619 	}
4620 	sdesc->tfm = alg;
4621 
4622 	len = size - sizeof(fw_hdr->checksum);
4623 	rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
4624 	kfree(sdesc);
4625 	if (rc)
4626 		goto free_shash;
4627 
4628 	if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
4629 		dev_err(&tp->intf->dev, "checksum fail\n");
4630 		rc = -EFAULT;
4631 	}
4632 
4633 free_shash:
4634 	crypto_free_shash(alg);
4635 out:
4636 	return rc;
4637 }
4638 
4639 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
4640 {
4641 	const struct firmware *fw = rtl_fw->fw;
4642 	struct fw_header *fw_hdr = (struct fw_header *)fw->data;
4643 	unsigned long fw_flags = 0;
4644 	long ret = -EFAULT;
4645 	int i;
4646 
4647 	if (fw->size < sizeof(*fw_hdr)) {
4648 		dev_err(&tp->intf->dev, "file too small\n");
4649 		goto fail;
4650 	}
4651 
4652 	ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
4653 	if (ret)
4654 		goto fail;
4655 
4656 	ret = -EFAULT;
4657 
4658 	for (i = sizeof(*fw_hdr); i < fw->size;) {
4659 		struct fw_block *block = (struct fw_block *)&fw->data[i];
4660 		u32 type;
4661 
4662 		if ((i + sizeof(*block)) > fw->size)
4663 			goto fail;
4664 
4665 		type = __le32_to_cpu(block->type);
4666 		switch (type) {
4667 		case RTL_FW_END:
4668 			if (__le32_to_cpu(block->length) != sizeof(*block))
4669 				goto fail;
4670 			goto fw_end;
4671 		case RTL_FW_PLA:
4672 			if (test_bit(FW_FLAGS_PLA, &fw_flags)) {
4673 				dev_err(&tp->intf->dev,
4674 					"multiple PLA firmware encountered");
4675 				goto fail;
4676 			}
4677 
4678 			if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4679 				dev_err(&tp->intf->dev,
4680 					"check PLA firmware failed\n");
4681 				goto fail;
4682 			}
4683 			__set_bit(FW_FLAGS_PLA, &fw_flags);
4684 			break;
4685 		case RTL_FW_USB:
4686 			if (test_bit(FW_FLAGS_USB, &fw_flags)) {
4687 				dev_err(&tp->intf->dev,
4688 					"multiple USB firmware encountered");
4689 				goto fail;
4690 			}
4691 
4692 			if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4693 				dev_err(&tp->intf->dev,
4694 					"check USB firmware failed\n");
4695 				goto fail;
4696 			}
4697 			__set_bit(FW_FLAGS_USB, &fw_flags);
4698 			break;
4699 		case RTL_FW_PHY_START:
4700 			if (test_bit(FW_FLAGS_START, &fw_flags) ||
4701 			    test_bit(FW_FLAGS_NC, &fw_flags) ||
4702 			    test_bit(FW_FLAGS_NC1, &fw_flags) ||
4703 			    test_bit(FW_FLAGS_NC2, &fw_flags) ||
4704 			    test_bit(FW_FLAGS_UC2, &fw_flags) ||
4705 			    test_bit(FW_FLAGS_UC, &fw_flags) ||
4706 			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
4707 				dev_err(&tp->intf->dev,
4708 					"check PHY_START fail\n");
4709 				goto fail;
4710 			}
4711 
4712 			if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) {
4713 				dev_err(&tp->intf->dev,
4714 					"Invalid length for PHY_START\n");
4715 				goto fail;
4716 			}
4717 			__set_bit(FW_FLAGS_START, &fw_flags);
4718 			break;
4719 		case RTL_FW_PHY_STOP:
4720 			if (test_bit(FW_FLAGS_STOP, &fw_flags) ||
4721 			    !test_bit(FW_FLAGS_START, &fw_flags)) {
4722 				dev_err(&tp->intf->dev,
4723 					"Check PHY_STOP fail\n");
4724 				goto fail;
4725 			}
4726 
4727 			if (__le32_to_cpu(block->length) != sizeof(*block)) {
4728 				dev_err(&tp->intf->dev,
4729 					"Invalid length for PHY_STOP\n");
4730 				goto fail;
4731 			}
4732 			__set_bit(FW_FLAGS_STOP, &fw_flags);
4733 			break;
4734 		case RTL_FW_PHY_NC:
4735 			if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4736 			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
4737 				dev_err(&tp->intf->dev,
4738 					"check PHY_NC fail\n");
4739 				goto fail;
4740 			}
4741 
4742 			if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4743 				dev_err(&tp->intf->dev,
4744 					"multiple PHY NC encountered\n");
4745 				goto fail;
4746 			}
4747 
4748 			if (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) {
4749 				dev_err(&tp->intf->dev,
4750 					"check PHY NC firmware failed\n");
4751 				goto fail;
4752 			}
4753 			__set_bit(FW_FLAGS_NC, &fw_flags);
4754 			break;
4755 		case RTL_FW_PHY_UNION_NC:
4756 			if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4757 			    test_bit(FW_FLAGS_NC1, &fw_flags) ||
4758 			    test_bit(FW_FLAGS_NC2, &fw_flags) ||
4759 			    test_bit(FW_FLAGS_UC2, &fw_flags) ||
4760 			    test_bit(FW_FLAGS_UC, &fw_flags) ||
4761 			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
4762 				dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n");
4763 				goto fail;
4764 			}
4765 
4766 			if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4767 				dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n");
4768 				goto fail;
4769 			}
4770 
4771 			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4772 				dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n");
4773 				goto fail;
4774 			}
4775 			__set_bit(FW_FLAGS_NC, &fw_flags);
4776 			break;
4777 		case RTL_FW_PHY_UNION_NC1:
4778 			if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4779 			    test_bit(FW_FLAGS_NC2, &fw_flags) ||
4780 			    test_bit(FW_FLAGS_UC2, &fw_flags) ||
4781 			    test_bit(FW_FLAGS_UC, &fw_flags) ||
4782 			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
4783 				dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n");
4784 				goto fail;
4785 			}
4786 
4787 			if (test_bit(FW_FLAGS_NC1, &fw_flags)) {
4788 				dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n");
4789 				goto fail;
4790 			}
4791 
4792 			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4793 				dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n");
4794 				goto fail;
4795 			}
4796 			__set_bit(FW_FLAGS_NC1, &fw_flags);
4797 			break;
4798 		case RTL_FW_PHY_UNION_NC2:
4799 			if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4800 			    test_bit(FW_FLAGS_UC2, &fw_flags) ||
4801 			    test_bit(FW_FLAGS_UC, &fw_flags) ||
4802 			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
4803 				dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n");
4804 				goto fail;
4805 			}
4806 
4807 			if (test_bit(FW_FLAGS_NC2, &fw_flags)) {
4808 				dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n");
4809 				goto fail;
4810 			}
4811 
4812 			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4813 				dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n");
4814 				goto fail;
4815 			}
4816 			__set_bit(FW_FLAGS_NC2, &fw_flags);
4817 			break;
4818 		case RTL_FW_PHY_UNION_UC2:
4819 			if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4820 			    test_bit(FW_FLAGS_UC, &fw_flags) ||
4821 			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
4822 				dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n");
4823 				goto fail;
4824 			}
4825 
4826 			if (test_bit(FW_FLAGS_UC2, &fw_flags)) {
4827 				dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n");
4828 				goto fail;
4829 			}
4830 
4831 			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4832 				dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n");
4833 				goto fail;
4834 			}
4835 			__set_bit(FW_FLAGS_UC2, &fw_flags);
4836 			break;
4837 		case RTL_FW_PHY_UNION_UC:
4838 			if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4839 			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
4840 				dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n");
4841 				goto fail;
4842 			}
4843 
4844 			if (test_bit(FW_FLAGS_UC, &fw_flags)) {
4845 				dev_err(&tp->intf->dev, "multiple PHY UC encountered\n");
4846 				goto fail;
4847 			}
4848 
4849 			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4850 				dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n");
4851 				goto fail;
4852 			}
4853 			__set_bit(FW_FLAGS_UC, &fw_flags);
4854 			break;
4855 		case RTL_FW_PHY_UNION_MISC:
4856 			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4857 				dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n");
4858 				goto fail;
4859 			}
4860 			break;
4861 		case RTL_FW_PHY_FIXUP:
4862 			if (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) {
4863 				dev_err(&tp->intf->dev, "check PHY fixup failed\n");
4864 				goto fail;
4865 			}
4866 			break;
4867 		case RTL_FW_PHY_SPEED_UP:
4868 			if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) {
4869 				dev_err(&tp->intf->dev, "multiple PHY firmware encountered");
4870 				goto fail;
4871 			}
4872 
4873 			if (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) {
4874 				dev_err(&tp->intf->dev, "check PHY speed up failed\n");
4875 				goto fail;
4876 			}
4877 			__set_bit(FW_FLAGS_SPEED_UP, &fw_flags);
4878 			break;
4879 		case RTL_FW_PHY_VER:
4880 			if (test_bit(FW_FLAGS_START, &fw_flags) ||
4881 			    test_bit(FW_FLAGS_NC, &fw_flags) ||
4882 			    test_bit(FW_FLAGS_NC1, &fw_flags) ||
4883 			    test_bit(FW_FLAGS_NC2, &fw_flags) ||
4884 			    test_bit(FW_FLAGS_UC2, &fw_flags) ||
4885 			    test_bit(FW_FLAGS_UC, &fw_flags) ||
4886 			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
4887 				dev_err(&tp->intf->dev, "Invalid order to set PHY version\n");
4888 				goto fail;
4889 			}
4890 
4891 			if (test_bit(FW_FLAGS_VER, &fw_flags)) {
4892 				dev_err(&tp->intf->dev, "multiple PHY version encountered");
4893 				goto fail;
4894 			}
4895 
4896 			if (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) {
4897 				dev_err(&tp->intf->dev, "check PHY version failed\n");
4898 				goto fail;
4899 			}
4900 			__set_bit(FW_FLAGS_VER, &fw_flags);
4901 			break;
4902 		default:
4903 			dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
4904 				 type);
4905 			break;
4906 		}
4907 
4908 		/* next block */
4909 		i += ALIGN(__le32_to_cpu(block->length), 8);
4910 	}
4911 
4912 fw_end:
4913 	if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) {
4914 		dev_err(&tp->intf->dev, "without PHY_STOP\n");
4915 		goto fail;
4916 	}
4917 
4918 	return 0;
4919 fail:
4920 	return ret;
4921 }
4922 
4923 static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)
4924 {
4925 	u32 len;
4926 	u8 *data;
4927 
4928 	rtl_reset_ocp_base(tp);
4929 
4930 	if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) {
4931 		dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4932 		return;
4933 	}
4934 
4935 	len = __le32_to_cpu(phy->blk_hdr.length);
4936 	len -= __le16_to_cpu(phy->fw_offset);
4937 	data = (u8 *)phy + __le16_to_cpu(phy->fw_offset);
4938 
4939 	if (rtl_phy_patch_request(tp, true, wait))
4940 		return;
4941 
4942 	while (len) {
4943 		u32 ocp_data, size;
4944 		int i;
4945 
4946 		if (len < 2048)
4947 			size = len;
4948 		else
4949 			size = 2048;
4950 
4951 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);
4952 		ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;
4953 		ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data);
4954 
4955 		generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB);
4956 
4957 		data += size;
4958 		len -= size;
4959 
4960 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);
4961 		ocp_data |= POL_GPHY_PATCH;
4962 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data);
4963 
4964 		for (i = 0; i < 1000; i++) {
4965 			if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))
4966 				break;
4967 		}
4968 
4969 		if (i == 1000) {
4970 			dev_err(&tp->intf->dev, "ram code speedup mode timeout\n");
4971 			break;
4972 		}
4973 	}
4974 
4975 	rtl_reset_ocp_base(tp);
4976 
4977 	rtl_phy_patch_request(tp, false, wait);
4978 
4979 	if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version))
4980 		dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4981 	else
4982 		dev_err(&tp->intf->dev, "ram code speedup mode fail\n");
4983 }
4984 
4985 static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver)
4986 {
4987 	u16 ver_addr, ver;
4988 
4989 	ver_addr = __le16_to_cpu(phy_ver->ver.addr);
4990 	ver = __le16_to_cpu(phy_ver->ver.data);
4991 
4992 	rtl_reset_ocp_base(tp);
4993 
4994 	if (sram_read(tp, ver_addr) >= ver) {
4995 		dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4996 		return 0;
4997 	}
4998 
4999 	sram_write(tp, ver_addr, ver);
5000 
5001 	dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver);
5002 
5003 	return ver;
5004 }
5005 
5006 static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix)
5007 {
5008 	u16 addr, data;
5009 
5010 	rtl_reset_ocp_base(tp);
5011 
5012 	addr = __le16_to_cpu(fix->setting.addr);
5013 	data = ocp_reg_read(tp, addr);
5014 
5015 	switch (__le16_to_cpu(fix->bit_cmd)) {
5016 	case FW_FIXUP_AND:
5017 		data &= __le16_to_cpu(fix->setting.data);
5018 		break;
5019 	case FW_FIXUP_OR:
5020 		data |= __le16_to_cpu(fix->setting.data);
5021 		break;
5022 	case FW_FIXUP_NOT:
5023 		data &= ~__le16_to_cpu(fix->setting.data);
5024 		break;
5025 	case FW_FIXUP_XOR:
5026 		data ^= __le16_to_cpu(fix->setting.data);
5027 		break;
5028 	default:
5029 		return;
5030 	}
5031 
5032 	ocp_reg_write(tp, addr, data);
5033 
5034 	dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data);
5035 }
5036 
5037 static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy)
5038 {
5039 	__le16 *data;
5040 	u32 length;
5041 	int i, num;
5042 
5043 	rtl_reset_ocp_base(tp);
5044 
5045 	num = phy->pre_num;
5046 	for (i = 0; i < num; i++)
5047 		sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr),
5048 			   __le16_to_cpu(phy->pre_set[i].data));
5049 
5050 	length = __le32_to_cpu(phy->blk_hdr.length);
5051 	length -= __le16_to_cpu(phy->fw_offset);
5052 	num = length / 2;
5053 	data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
5054 
5055 	ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
5056 	for (i = 0; i < num; i++)
5057 		ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
5058 
5059 	num = phy->bp_num;
5060 	for (i = 0; i < num; i++)
5061 		sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data));
5062 
5063 	if (phy->bp_num && phy->bp_en.addr)
5064 		sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data));
5065 
5066 	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
5067 }
5068 
5069 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
5070 {
5071 	u16 mode_reg, bp_index;
5072 	u32 length, i, num;
5073 	__le16 *data;
5074 
5075 	rtl_reset_ocp_base(tp);
5076 
5077 	mode_reg = __le16_to_cpu(phy->mode_reg);
5078 	sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
5079 	sram_write(tp, __le16_to_cpu(phy->ba_reg),
5080 		   __le16_to_cpu(phy->ba_data));
5081 
5082 	length = __le32_to_cpu(phy->blk_hdr.length);
5083 	length -= __le16_to_cpu(phy->fw_offset);
5084 	num = length / 2;
5085 	data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
5086 
5087 	ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
5088 	for (i = 0; i < num; i++)
5089 		ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
5090 
5091 	sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
5092 		   __le16_to_cpu(phy->patch_en_value));
5093 
5094 	bp_index = __le16_to_cpu(phy->bp_start);
5095 	num = __le16_to_cpu(phy->bp_num);
5096 	for (i = 0; i < num; i++) {
5097 		sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
5098 		bp_index += 2;
5099 	}
5100 
5101 	sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
5102 
5103 	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
5104 }
5105 
5106 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
5107 {
5108 	u16 bp_en_addr, type, fw_ver_reg;
5109 	u32 length;
5110 	u8 *data;
5111 
5112 	switch (__le32_to_cpu(mac->blk_hdr.type)) {
5113 	case RTL_FW_PLA:
5114 		type = MCU_TYPE_PLA;
5115 		break;
5116 	case RTL_FW_USB:
5117 		type = MCU_TYPE_USB;
5118 		break;
5119 	default:
5120 		return;
5121 	}
5122 
5123 	fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
5124 	if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) {
5125 		dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB");
5126 		return;
5127 	}
5128 
5129 	rtl_clear_bp(tp, type);
5130 
5131 	/* Enable backup/restore of MACDBG. This is required after clearing PLA
5132 	 * break points and before applying the PLA firmware.
5133 	 */
5134 	if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
5135 	    !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
5136 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
5137 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
5138 	}
5139 
5140 	length = __le32_to_cpu(mac->blk_hdr.length);
5141 	length -= __le16_to_cpu(mac->fw_offset);
5142 
5143 	data = (u8 *)mac;
5144 	data += __le16_to_cpu(mac->fw_offset);
5145 
5146 	generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
5147 			  type);
5148 
5149 	ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
5150 		       __le16_to_cpu(mac->bp_ba_value));
5151 
5152 	generic_ocp_write(tp, __le16_to_cpu(mac->bp_start), BYTE_EN_DWORD,
5153 			  __le16_to_cpu(mac->bp_num) << 1, mac->bp, type);
5154 
5155 	bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
5156 	if (bp_en_addr)
5157 		ocp_write_word(tp, type, bp_en_addr,
5158 			       __le16_to_cpu(mac->bp_en_value));
5159 
5160 	if (fw_ver_reg)
5161 		ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
5162 			       mac->fw_ver_data);
5163 
5164 	dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
5165 }
5166 
5167 static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)
5168 {
5169 	struct rtl_fw *rtl_fw = &tp->rtl_fw;
5170 	const struct firmware *fw;
5171 	struct fw_header *fw_hdr;
5172 	struct fw_phy_patch_key *key;
5173 	u16 key_addr = 0;
5174 	int i, patch_phy = 1;
5175 
5176 	if (IS_ERR_OR_NULL(rtl_fw->fw))
5177 		return;
5178 
5179 	fw = rtl_fw->fw;
5180 	fw_hdr = (struct fw_header *)fw->data;
5181 
5182 	if (rtl_fw->pre_fw)
5183 		rtl_fw->pre_fw(tp);
5184 
5185 	for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
5186 		struct fw_block *block = (struct fw_block *)&fw->data[i];
5187 
5188 		switch (__le32_to_cpu(block->type)) {
5189 		case RTL_FW_END:
5190 			goto post_fw;
5191 		case RTL_FW_PLA:
5192 		case RTL_FW_USB:
5193 			rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
5194 			break;
5195 		case RTL_FW_PHY_START:
5196 			if (!patch_phy)
5197 				break;
5198 			key = (struct fw_phy_patch_key *)block;
5199 			key_addr = __le16_to_cpu(key->key_reg);
5200 			rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut);
5201 			break;
5202 		case RTL_FW_PHY_STOP:
5203 			if (!patch_phy)
5204 				break;
5205 			WARN_ON(!key_addr);
5206 			rtl_post_ram_code(tp, key_addr, !power_cut);
5207 			break;
5208 		case RTL_FW_PHY_NC:
5209 			rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
5210 			break;
5211 		case RTL_FW_PHY_VER:
5212 			patch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block);
5213 			break;
5214 		case RTL_FW_PHY_UNION_NC:
5215 		case RTL_FW_PHY_UNION_NC1:
5216 		case RTL_FW_PHY_UNION_NC2:
5217 		case RTL_FW_PHY_UNION_UC2:
5218 		case RTL_FW_PHY_UNION_UC:
5219 		case RTL_FW_PHY_UNION_MISC:
5220 			if (patch_phy)
5221 				rtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block);
5222 			break;
5223 		case RTL_FW_PHY_FIXUP:
5224 			if (patch_phy)
5225 				rtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block);
5226 			break;
5227 		case RTL_FW_PHY_SPEED_UP:
5228 			rtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut);
5229 			break;
5230 		default:
5231 			break;
5232 		}
5233 
5234 		i += ALIGN(__le32_to_cpu(block->length), 8);
5235 	}
5236 
5237 post_fw:
5238 	if (rtl_fw->post_fw)
5239 		rtl_fw->post_fw(tp);
5240 
5241 	rtl_reset_ocp_base(tp);
5242 	strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
5243 	dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
5244 }
5245 
5246 static void rtl8152_release_firmware(struct r8152 *tp)
5247 {
5248 	struct rtl_fw *rtl_fw = &tp->rtl_fw;
5249 
5250 	if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
5251 		release_firmware(rtl_fw->fw);
5252 		rtl_fw->fw = NULL;
5253 	}
5254 }
5255 
5256 static int rtl8152_request_firmware(struct r8152 *tp)
5257 {
5258 	struct rtl_fw *rtl_fw = &tp->rtl_fw;
5259 	long rc;
5260 
5261 	if (rtl_fw->fw || !rtl_fw->fw_name) {
5262 		dev_info(&tp->intf->dev, "skip request firmware\n");
5263 		rc = 0;
5264 		goto result;
5265 	}
5266 
5267 	rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
5268 	if (rc < 0)
5269 		goto result;
5270 
5271 	rc = rtl8152_check_firmware(tp, rtl_fw);
5272 	if (rc < 0)
5273 		release_firmware(rtl_fw->fw);
5274 
5275 result:
5276 	if (rc) {
5277 		rtl_fw->fw = ERR_PTR(rc);
5278 
5279 		dev_warn(&tp->intf->dev,
5280 			 "unable to load firmware patch %s (%ld)\n",
5281 			 rtl_fw->fw_name, rc);
5282 	}
5283 
5284 	return rc;
5285 }
5286 
5287 static void r8152_aldps_en(struct r8152 *tp, bool enable)
5288 {
5289 	if (enable) {
5290 		ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
5291 						    LINKENA | DIS_SDSAVE);
5292 	} else {
5293 		ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
5294 						    DIS_SDSAVE);
5295 		msleep(20);
5296 	}
5297 }
5298 
5299 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
5300 {
5301 	ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
5302 	ocp_reg_write(tp, OCP_EEE_DATA, reg);
5303 	ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
5304 }
5305 
5306 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
5307 {
5308 	u16 data;
5309 
5310 	r8152_mmd_indirect(tp, dev, reg);
5311 	data = ocp_reg_read(tp, OCP_EEE_DATA);
5312 	ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5313 
5314 	return data;
5315 }
5316 
5317 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
5318 {
5319 	r8152_mmd_indirect(tp, dev, reg);
5320 	ocp_reg_write(tp, OCP_EEE_DATA, data);
5321 	ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5322 }
5323 
5324 static void r8152_eee_en(struct r8152 *tp, bool enable)
5325 {
5326 	u16 config1, config2, config3;
5327 	u32 ocp_data;
5328 
5329 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5330 	config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
5331 	config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
5332 	config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
5333 
5334 	if (enable) {
5335 		ocp_data |= EEE_RX_EN | EEE_TX_EN;
5336 		config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
5337 		config1 |= sd_rise_time(1);
5338 		config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
5339 		config3 |= fast_snr(42);
5340 	} else {
5341 		ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5342 		config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
5343 			     RX_QUIET_EN);
5344 		config1 |= sd_rise_time(7);
5345 		config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
5346 		config3 |= fast_snr(511);
5347 	}
5348 
5349 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5350 	ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
5351 	ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
5352 	ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
5353 }
5354 
5355 static void r8153_eee_en(struct r8152 *tp, bool enable)
5356 {
5357 	u32 ocp_data;
5358 	u16 config;
5359 
5360 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5361 	config = ocp_reg_read(tp, OCP_EEE_CFG);
5362 
5363 	if (enable) {
5364 		ocp_data |= EEE_RX_EN | EEE_TX_EN;
5365 		config |= EEE10_EN;
5366 	} else {
5367 		ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5368 		config &= ~EEE10_EN;
5369 	}
5370 
5371 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5372 	ocp_reg_write(tp, OCP_EEE_CFG, config);
5373 
5374 	tp->ups_info.eee = enable;
5375 }
5376 
5377 static void r8156_eee_en(struct r8152 *tp, bool enable)
5378 {
5379 	u16 config;
5380 
5381 	r8153_eee_en(tp, enable);
5382 
5383 	config = ocp_reg_read(tp, OCP_EEE_ADV2);
5384 
5385 	if (enable)
5386 		config |= MDIO_EEE_2_5GT;
5387 	else
5388 		config &= ~MDIO_EEE_2_5GT;
5389 
5390 	ocp_reg_write(tp, OCP_EEE_ADV2, config);
5391 }
5392 
5393 static void rtl_eee_enable(struct r8152 *tp, bool enable)
5394 {
5395 	switch (tp->version) {
5396 	case RTL_VER_01:
5397 	case RTL_VER_02:
5398 	case RTL_VER_07:
5399 		if (enable) {
5400 			r8152_eee_en(tp, true);
5401 			r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
5402 					tp->eee_adv);
5403 		} else {
5404 			r8152_eee_en(tp, false);
5405 			r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
5406 		}
5407 		break;
5408 	case RTL_VER_03:
5409 	case RTL_VER_04:
5410 	case RTL_VER_05:
5411 	case RTL_VER_06:
5412 	case RTL_VER_08:
5413 	case RTL_VER_09:
5414 	case RTL_VER_14:
5415 		if (enable) {
5416 			r8153_eee_en(tp, true);
5417 			ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5418 		} else {
5419 			r8153_eee_en(tp, false);
5420 			ocp_reg_write(tp, OCP_EEE_ADV, 0);
5421 		}
5422 		break;
5423 	case RTL_VER_10:
5424 	case RTL_VER_11:
5425 	case RTL_VER_12:
5426 	case RTL_VER_13:
5427 	case RTL_VER_15:
5428 		if (enable) {
5429 			r8156_eee_en(tp, true);
5430 			ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5431 		} else {
5432 			r8156_eee_en(tp, false);
5433 			ocp_reg_write(tp, OCP_EEE_ADV, 0);
5434 		}
5435 		break;
5436 	default:
5437 		break;
5438 	}
5439 }
5440 
5441 static void r8152b_enable_fc(struct r8152 *tp)
5442 {
5443 	u16 anar;
5444 
5445 	anar = r8152_mdio_read(tp, MII_ADVERTISE);
5446 	anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
5447 	r8152_mdio_write(tp, MII_ADVERTISE, anar);
5448 
5449 	tp->ups_info.flow_control = true;
5450 }
5451 
5452 static void rtl8152_disable(struct r8152 *tp)
5453 {
5454 	r8152_aldps_en(tp, false);
5455 	rtl_disable(tp);
5456 	r8152_aldps_en(tp, true);
5457 }
5458 
5459 static void r8152b_hw_phy_cfg(struct r8152 *tp)
5460 {
5461 	rtl8152_apply_firmware(tp, false);
5462 	rtl_eee_enable(tp, tp->eee_en);
5463 	r8152_aldps_en(tp, true);
5464 	r8152b_enable_fc(tp);
5465 
5466 	set_bit(PHY_RESET, &tp->flags);
5467 }
5468 
5469 static void wait_oob_link_list_ready(struct r8152 *tp)
5470 {
5471 	u32 ocp_data;
5472 	int i;
5473 
5474 	for (i = 0; i < 1000; i++) {
5475 		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
5476 			break;
5477 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5478 		if (ocp_data & LINK_LIST_READY)
5479 			break;
5480 		usleep_range(1000, 2000);
5481 	}
5482 }
5483 
5484 static void r8156b_wait_loading_flash(struct r8152 *tp)
5485 {
5486 	if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&
5487 	    !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {
5488 		int i;
5489 
5490 		for (i = 0; i < 100; i++) {
5491 			if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
5492 				break;
5493 			if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)
5494 				break;
5495 			usleep_range(1000, 2000);
5496 		}
5497 	}
5498 }
5499 
5500 static void r8152b_exit_oob(struct r8152 *tp)
5501 {
5502 	u32 ocp_data;
5503 
5504 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5505 	ocp_data &= ~RCR_ACPT_ALL;
5506 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5507 
5508 	rxdy_gated_en(tp, true);
5509 	r8153_teredo_off(tp);
5510 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
5511 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
5512 
5513 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5514 	ocp_data &= ~NOW_IS_OOB;
5515 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5516 
5517 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5518 	ocp_data &= ~MCU_BORW_EN;
5519 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5520 
5521 	wait_oob_link_list_ready(tp);
5522 
5523 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5524 	ocp_data |= RE_INIT_LL;
5525 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5526 
5527 	wait_oob_link_list_ready(tp);
5528 
5529 	rtl8152_nic_reset(tp);
5530 
5531 	/* rx share fifo credit full threshold */
5532 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5533 
5534 	if (tp->udev->speed == USB_SPEED_FULL ||
5535 	    tp->udev->speed == USB_SPEED_LOW) {
5536 		/* rx share fifo credit near full threshold */
5537 		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5538 				RXFIFO_THR2_FULL);
5539 		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5540 				RXFIFO_THR3_FULL);
5541 	} else {
5542 		/* rx share fifo credit near full threshold */
5543 		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5544 				RXFIFO_THR2_HIGH);
5545 		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5546 				RXFIFO_THR3_HIGH);
5547 	}
5548 
5549 	/* TX share fifo free credit full threshold */
5550 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5551 
5552 	ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
5553 	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
5554 	ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
5555 			TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
5556 
5557 	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5558 
5559 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5560 
5561 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5562 	ocp_data |= TCR0_AUTO_FIFO;
5563 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5564 }
5565 
5566 static void r8152b_enter_oob(struct r8152 *tp)
5567 {
5568 	u32 ocp_data;
5569 
5570 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5571 	ocp_data &= ~NOW_IS_OOB;
5572 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5573 
5574 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
5575 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
5576 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
5577 
5578 	rtl_disable(tp);
5579 
5580 	wait_oob_link_list_ready(tp);
5581 
5582 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5583 	ocp_data |= RE_INIT_LL;
5584 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5585 
5586 	wait_oob_link_list_ready(tp);
5587 
5588 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5589 
5590 	rtl_rx_vlan_en(tp, true);
5591 
5592 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5593 	ocp_data |= ALDPS_PROXY_MODE;
5594 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
5595 
5596 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5597 	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5598 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5599 
5600 	rxdy_gated_en(tp, false);
5601 
5602 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5603 	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5604 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5605 }
5606 
5607 static int r8153_pre_firmware_1(struct r8152 *tp)
5608 {
5609 	int i;
5610 
5611 	/* Wait till the WTD timer is ready. It would take at most 104 ms. */
5612 	for (i = 0; i < 104; i++) {
5613 		u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
5614 
5615 		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
5616 			return -ENODEV;
5617 		if (!(ocp_data & WTD1_EN))
5618 			break;
5619 		usleep_range(1000, 2000);
5620 	}
5621 
5622 	return 0;
5623 }
5624 
5625 static int r8153_post_firmware_1(struct r8152 *tp)
5626 {
5627 	/* set USB_BP_4 to support USB_SPEED_SUPER only */
5628 	if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
5629 		ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
5630 
5631 	/* reset UPHY timer to 36 ms */
5632 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5633 
5634 	return 0;
5635 }
5636 
5637 static int r8153_pre_firmware_2(struct r8152 *tp)
5638 {
5639 	u32 ocp_data;
5640 
5641 	r8153_pre_firmware_1(tp);
5642 
5643 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5644 	ocp_data &= ~FW_FIX_SUSPEND;
5645 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5646 
5647 	return 0;
5648 }
5649 
5650 static int r8153_post_firmware_2(struct r8152 *tp)
5651 {
5652 	u32 ocp_data;
5653 
5654 	/* enable bp0 if support USB_SPEED_SUPER only */
5655 	if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
5656 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5657 		ocp_data |= BIT(0);
5658 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5659 	}
5660 
5661 	/* reset UPHY timer to 36 ms */
5662 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5663 
5664 	/* enable U3P3 check, set the counter to 4 */
5665 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
5666 
5667 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5668 	ocp_data |= FW_FIX_SUSPEND;
5669 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5670 
5671 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5672 	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5673 	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5674 
5675 	return 0;
5676 }
5677 
5678 static int r8153_post_firmware_3(struct r8152 *tp)
5679 {
5680 	u32 ocp_data;
5681 
5682 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5683 	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5684 	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5685 
5686 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5687 	ocp_data |= FW_IP_RESET_EN;
5688 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5689 
5690 	return 0;
5691 }
5692 
5693 static int r8153b_pre_firmware_1(struct r8152 *tp)
5694 {
5695 	/* enable fc timer and set timer to 1 second. */
5696 	ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
5697 		       CTRL_TIMER_EN | (1000 / 8));
5698 
5699 	return 0;
5700 }
5701 
5702 static int r8153b_post_firmware_1(struct r8152 *tp)
5703 {
5704 	u32 ocp_data;
5705 
5706 	/* enable bp0 for RTL8153-BND */
5707 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
5708 	if (ocp_data & BND_MASK) {
5709 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5710 		ocp_data |= BIT(0);
5711 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5712 	}
5713 
5714 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5715 	ocp_data |= FLOW_CTRL_PATCH_OPT;
5716 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5717 
5718 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5719 	ocp_data |= FC_PATCH_TASK;
5720 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5721 
5722 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5723 	ocp_data |= FW_IP_RESET_EN;
5724 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5725 
5726 	return 0;
5727 }
5728 
5729 static int r8153c_post_firmware_1(struct r8152 *tp)
5730 {
5731 	u32 ocp_data;
5732 
5733 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5734 	ocp_data |= FLOW_CTRL_PATCH_2;
5735 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5736 
5737 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5738 	ocp_data |= FC_PATCH_TASK;
5739 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5740 
5741 	return 0;
5742 }
5743 
5744 static int r8156a_post_firmware_1(struct r8152 *tp)
5745 {
5746 	u32 ocp_data;
5747 
5748 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5749 	ocp_data |= FW_IP_RESET_EN;
5750 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5751 
5752 	/* Modify U3PHY parameter for compatibility issue */
5753 	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e);
5754 	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9);
5755 
5756 	return 0;
5757 }
5758 
5759 static void r8153_aldps_en(struct r8152 *tp, bool enable)
5760 {
5761 	u16 data;
5762 
5763 	data = ocp_reg_read(tp, OCP_POWER_CFG);
5764 	if (enable) {
5765 		data |= EN_ALDPS;
5766 		ocp_reg_write(tp, OCP_POWER_CFG, data);
5767 	} else {
5768 		int i;
5769 
5770 		data &= ~EN_ALDPS;
5771 		ocp_reg_write(tp, OCP_POWER_CFG, data);
5772 		for (i = 0; i < 20; i++) {
5773 			if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
5774 				return;
5775 			usleep_range(1000, 2000);
5776 			if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
5777 				break;
5778 		}
5779 	}
5780 
5781 	tp->ups_info.aldps = enable;
5782 }
5783 
5784 static void r8153_hw_phy_cfg(struct r8152 *tp)
5785 {
5786 	u32 ocp_data;
5787 	u16 data;
5788 
5789 	/* disable ALDPS before updating the PHY parameters */
5790 	r8153_aldps_en(tp, false);
5791 
5792 	/* disable EEE before updating the PHY parameters */
5793 	rtl_eee_enable(tp, false);
5794 
5795 	rtl8152_apply_firmware(tp, false);
5796 
5797 	if (tp->version == RTL_VER_03) {
5798 		data = ocp_reg_read(tp, OCP_EEE_CFG);
5799 		data &= ~CTAP_SHORT_EN;
5800 		ocp_reg_write(tp, OCP_EEE_CFG, data);
5801 	}
5802 
5803 	data = ocp_reg_read(tp, OCP_POWER_CFG);
5804 	data |= EEE_CLKDIV_EN;
5805 	ocp_reg_write(tp, OCP_POWER_CFG, data);
5806 
5807 	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5808 	data |= EN_10M_BGOFF;
5809 	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5810 	data = ocp_reg_read(tp, OCP_POWER_CFG);
5811 	data |= EN_10M_PLLOFF;
5812 	ocp_reg_write(tp, OCP_POWER_CFG, data);
5813 	sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
5814 
5815 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5816 	ocp_data |= PFM_PWM_SWITCH;
5817 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5818 
5819 	/* Enable LPF corner auto tune */
5820 	sram_write(tp, SRAM_LPF_CFG, 0xf70f);
5821 
5822 	/* Adjust 10M Amplitude */
5823 	sram_write(tp, SRAM_10M_AMP1, 0x00af);
5824 	sram_write(tp, SRAM_10M_AMP2, 0x0208);
5825 
5826 	if (tp->eee_en)
5827 		rtl_eee_enable(tp, true);
5828 
5829 	r8153_aldps_en(tp, true);
5830 	r8152b_enable_fc(tp);
5831 
5832 	switch (tp->version) {
5833 	case RTL_VER_03:
5834 	case RTL_VER_04:
5835 		break;
5836 	case RTL_VER_05:
5837 	case RTL_VER_06:
5838 	default:
5839 		r8153_u2p3en(tp, true);
5840 		break;
5841 	}
5842 
5843 	set_bit(PHY_RESET, &tp->flags);
5844 }
5845 
5846 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
5847 {
5848 	u32 ocp_data;
5849 
5850 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
5851 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
5852 	ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;	/* data of bit16 */
5853 	ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
5854 
5855 	return ocp_data;
5856 }
5857 
5858 static void r8153b_hw_phy_cfg(struct r8152 *tp)
5859 {
5860 	u32 ocp_data;
5861 	u16 data;
5862 
5863 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
5864 	if (ocp_data & PCUT_STATUS) {
5865 		ocp_data &= ~PCUT_STATUS;
5866 		ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
5867 	}
5868 
5869 	/* disable ALDPS before updating the PHY parameters */
5870 	r8153_aldps_en(tp, false);
5871 
5872 	/* disable EEE before updating the PHY parameters */
5873 	rtl_eee_enable(tp, false);
5874 
5875 	/* U1/U2/L1 idle timer. 500 us */
5876 	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5877 
5878 	data = r8153_phy_status(tp, 0);
5879 
5880 	switch (data) {
5881 	case PHY_STAT_PWRDN:
5882 	case PHY_STAT_EXT_INIT:
5883 		rtl8152_apply_firmware(tp, true);
5884 
5885 		data = r8152_mdio_read(tp, MII_BMCR);
5886 		data &= ~BMCR_PDOWN;
5887 		r8152_mdio_write(tp, MII_BMCR, data);
5888 		break;
5889 	case PHY_STAT_LAN_ON:
5890 	default:
5891 		rtl8152_apply_firmware(tp, false);
5892 		break;
5893 	}
5894 
5895 	r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
5896 
5897 	data = sram_read(tp, SRAM_GREEN_CFG);
5898 	data |= R_TUNE_EN;
5899 	sram_write(tp, SRAM_GREEN_CFG, data);
5900 	data = ocp_reg_read(tp, OCP_NCTL_CFG);
5901 	data |= PGA_RETURN_EN;
5902 	ocp_reg_write(tp, OCP_NCTL_CFG, data);
5903 
5904 	/* ADC Bias Calibration:
5905 	 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
5906 	 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
5907 	 * ADC ioffset.
5908 	 */
5909 	ocp_data = r8152_efuse_read(tp, 0x7d);
5910 	data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
5911 	if (data != 0xffff)
5912 		ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
5913 
5914 	/* ups mode tx-link-pulse timing adjustment:
5915 	 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
5916 	 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
5917 	 */
5918 	ocp_data = ocp_reg_read(tp, 0xc426);
5919 	ocp_data &= 0x3fff;
5920 	if (ocp_data) {
5921 		u32 swr_cnt_1ms_ini;
5922 
5923 		swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
5924 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
5925 		ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
5926 		ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
5927 	}
5928 
5929 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5930 	ocp_data |= PFM_PWM_SWITCH;
5931 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5932 
5933 	/* Advnace EEE */
5934 	if (!rtl_phy_patch_request(tp, true, true)) {
5935 		data = ocp_reg_read(tp, OCP_POWER_CFG);
5936 		data |= EEE_CLKDIV_EN;
5937 		ocp_reg_write(tp, OCP_POWER_CFG, data);
5938 		tp->ups_info.eee_ckdiv = true;
5939 
5940 		data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5941 		data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
5942 		ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5943 		tp->ups_info.eee_cmod_lv = true;
5944 		tp->ups_info._10m_ckdiv = true;
5945 		tp->ups_info.eee_plloff_giga = true;
5946 
5947 		ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
5948 		ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
5949 		tp->ups_info._250m_ckdiv = true;
5950 
5951 		rtl_phy_patch_request(tp, false, true);
5952 	}
5953 
5954 	if (tp->eee_en)
5955 		rtl_eee_enable(tp, true);
5956 
5957 	r8153_aldps_en(tp, true);
5958 	r8152b_enable_fc(tp);
5959 
5960 	set_bit(PHY_RESET, &tp->flags);
5961 }
5962 
5963 static void r8153c_hw_phy_cfg(struct r8152 *tp)
5964 {
5965 	r8153b_hw_phy_cfg(tp);
5966 
5967 	tp->ups_info.r_tune = true;
5968 }
5969 
5970 static void rtl8153_change_mtu(struct r8152 *tp)
5971 {
5972 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
5973 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
5974 }
5975 
5976 static void r8153_first_init(struct r8152 *tp)
5977 {
5978 	u32 ocp_data;
5979 
5980 	rxdy_gated_en(tp, true);
5981 	r8153_teredo_off(tp);
5982 
5983 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5984 	ocp_data &= ~RCR_ACPT_ALL;
5985 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5986 
5987 	rtl8152_nic_reset(tp);
5988 	rtl_reset_bmu(tp);
5989 
5990 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5991 	ocp_data &= ~NOW_IS_OOB;
5992 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5993 
5994 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5995 	ocp_data &= ~MCU_BORW_EN;
5996 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5997 
5998 	wait_oob_link_list_ready(tp);
5999 
6000 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6001 	ocp_data |= RE_INIT_LL;
6002 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6003 
6004 	wait_oob_link_list_ready(tp);
6005 
6006 	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6007 
6008 	rtl8153_change_mtu(tp);
6009 
6010 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
6011 	ocp_data |= TCR0_AUTO_FIFO;
6012 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
6013 
6014 	rtl8152_nic_reset(tp);
6015 
6016 	/* rx share fifo credit full threshold */
6017 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
6018 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
6019 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
6020 	/* TX share fifo free credit full threshold */
6021 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
6022 }
6023 
6024 static void r8153_enter_oob(struct r8152 *tp)
6025 {
6026 	u32 ocp_data;
6027 
6028 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6029 	ocp_data &= ~NOW_IS_OOB;
6030 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6031 
6032 	/* RX FIFO settings for OOB */
6033 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
6034 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
6035 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
6036 
6037 	rtl_disable(tp);
6038 	rtl_reset_bmu(tp);
6039 
6040 	wait_oob_link_list_ready(tp);
6041 
6042 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6043 	ocp_data |= RE_INIT_LL;
6044 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6045 
6046 	wait_oob_link_list_ready(tp);
6047 
6048 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522);
6049 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
6050 
6051 	switch (tp->version) {
6052 	case RTL_VER_03:
6053 	case RTL_VER_04:
6054 	case RTL_VER_05:
6055 	case RTL_VER_06:
6056 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
6057 		ocp_data &= ~TEREDO_WAKE_MASK;
6058 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
6059 		break;
6060 
6061 	case RTL_VER_08:
6062 	case RTL_VER_09:
6063 	case RTL_VER_14:
6064 		/* Clear teredo wake event. bit[15:8] is the teredo wakeup
6065 		 * type. Set it to zero. bits[7:0] are the W1C bits about
6066 		 * the events. Set them to all 1 to clear them.
6067 		 */
6068 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
6069 		break;
6070 
6071 	default:
6072 		break;
6073 	}
6074 
6075 	rtl_rx_vlan_en(tp, true);
6076 
6077 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
6078 	ocp_data |= ALDPS_PROXY_MODE;
6079 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
6080 
6081 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6082 	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
6083 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6084 
6085 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6086 	ocp_data |= MCU_BORW_EN;
6087 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6088 
6089 	rxdy_gated_en(tp, false);
6090 
6091 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6092 	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6093 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6094 }
6095 
6096 static void rtl8153_disable(struct r8152 *tp)
6097 {
6098 	r8153_aldps_en(tp, false);
6099 	rtl_disable(tp);
6100 	rtl_reset_bmu(tp);
6101 	r8153_aldps_en(tp, true);
6102 }
6103 
6104 static u32 fc_pause_on_auto(struct r8152 *tp)
6105 {
6106 	return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);
6107 }
6108 
6109 static u32 fc_pause_off_auto(struct r8152 *tp)
6110 {
6111 	return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);
6112 }
6113 
6114 static void r8156_fc_parameter(struct r8152 *tp)
6115 {
6116 	u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);
6117 	u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);
6118 
6119 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16);
6120 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16);
6121 }
6122 
6123 static int rtl8156_enable(struct r8152 *tp)
6124 {
6125 	u32 ocp_data;
6126 	u16 speed;
6127 
6128 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6129 		return -ENODEV;
6130 
6131 	r8156_fc_parameter(tp);
6132 	set_tx_qlen(tp);
6133 	rtl_set_eee_plus(tp);
6134 	r8153_set_rx_early_timeout(tp);
6135 	r8153_set_rx_early_size(tp);
6136 
6137 	speed = rtl8152_get_speed(tp);
6138 	rtl_set_ifg(tp, speed);
6139 
6140 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6141 	if (speed & _2500bps)
6142 		ocp_data &= ~IDLE_SPDWN_EN;
6143 	else
6144 		ocp_data |= IDLE_SPDWN_EN;
6145 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
6146 
6147 	if (speed & _1000bps)
6148 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11);
6149 	else if (speed & _500bps)
6150 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d);
6151 
6152 	if (tp->udev->speed == USB_SPEED_HIGH) {
6153 		/* USB 0xb45e[3:0] l1_nyet_hird */
6154 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6155 		ocp_data &= ~0xf;
6156 		if (is_flow_control(speed))
6157 			ocp_data |= 0xf;
6158 		else
6159 			ocp_data |= 0x1;
6160 		ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
6161 	}
6162 
6163 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6164 	ocp_data &= ~FC_PATCH_TASK;
6165 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6166 	usleep_range(1000, 2000);
6167 	ocp_data |= FC_PATCH_TASK;
6168 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6169 
6170 	return rtl_enable(tp);
6171 }
6172 
6173 static void rtl8156_disable(struct r8152 *tp)
6174 {
6175 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 0);
6176 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 0);
6177 
6178 	rtl8153_disable(tp);
6179 }
6180 
6181 static int rtl8156b_enable(struct r8152 *tp)
6182 {
6183 	u32 ocp_data;
6184 	u16 speed;
6185 
6186 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6187 		return -ENODEV;
6188 
6189 	set_tx_qlen(tp);
6190 	rtl_set_eee_plus(tp);
6191 
6192 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);
6193 	ocp_data &= ~RX_AGGR_NUM_MASK;
6194 	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data);
6195 
6196 	r8153_set_rx_early_timeout(tp);
6197 	r8153_set_rx_early_size(tp);
6198 
6199 	speed = rtl8152_get_speed(tp);
6200 	rtl_set_ifg(tp, speed);
6201 
6202 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6203 	if (speed & _2500bps)
6204 		ocp_data &= ~IDLE_SPDWN_EN;
6205 	else
6206 		ocp_data |= IDLE_SPDWN_EN;
6207 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
6208 
6209 	if (tp->udev->speed == USB_SPEED_HIGH) {
6210 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6211 		ocp_data &= ~0xf;
6212 		if (is_flow_control(speed))
6213 			ocp_data |= 0xf;
6214 		else
6215 			ocp_data |= 0x1;
6216 		ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
6217 	}
6218 
6219 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6220 	ocp_data &= ~FC_PATCH_TASK;
6221 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6222 	usleep_range(1000, 2000);
6223 	ocp_data |= FC_PATCH_TASK;
6224 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6225 
6226 	return rtl_enable(tp);
6227 }
6228 
6229 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
6230 			     u32 advertising)
6231 {
6232 	u16 bmcr;
6233 	int ret = 0;
6234 
6235 	if (autoneg == AUTONEG_DISABLE) {
6236 		if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
6237 			return -EINVAL;
6238 
6239 		switch (speed) {
6240 		case SPEED_10:
6241 			bmcr = BMCR_SPEED10;
6242 			if (duplex == DUPLEX_FULL) {
6243 				bmcr |= BMCR_FULLDPLX;
6244 				tp->ups_info.speed_duplex = FORCE_10M_FULL;
6245 			} else {
6246 				tp->ups_info.speed_duplex = FORCE_10M_HALF;
6247 			}
6248 			break;
6249 		case SPEED_100:
6250 			bmcr = BMCR_SPEED100;
6251 			if (duplex == DUPLEX_FULL) {
6252 				bmcr |= BMCR_FULLDPLX;
6253 				tp->ups_info.speed_duplex = FORCE_100M_FULL;
6254 			} else {
6255 				tp->ups_info.speed_duplex = FORCE_100M_HALF;
6256 			}
6257 			break;
6258 		case SPEED_1000:
6259 			if (tp->mii.supports_gmii) {
6260 				bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
6261 				tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6262 				break;
6263 			}
6264 			fallthrough;
6265 		default:
6266 			ret = -EINVAL;
6267 			goto out;
6268 		}
6269 
6270 		if (duplex == DUPLEX_FULL)
6271 			tp->mii.full_duplex = 1;
6272 		else
6273 			tp->mii.full_duplex = 0;
6274 
6275 		tp->mii.force_media = 1;
6276 	} else {
6277 		u16 orig, new1;
6278 		u32 support;
6279 
6280 		support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6281 			  RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6282 
6283 		if (tp->mii.supports_gmii) {
6284 			support |= RTL_ADVERTISED_1000_FULL;
6285 
6286 			if (tp->support_2500full)
6287 				support |= RTL_ADVERTISED_2500_FULL;
6288 		}
6289 
6290 		if (!(advertising & support))
6291 			return -EINVAL;
6292 
6293 		orig = r8152_mdio_read(tp, MII_ADVERTISE);
6294 		new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
6295 				ADVERTISE_100HALF | ADVERTISE_100FULL);
6296 		if (advertising & RTL_ADVERTISED_10_HALF) {
6297 			new1 |= ADVERTISE_10HALF;
6298 			tp->ups_info.speed_duplex = NWAY_10M_HALF;
6299 		}
6300 		if (advertising & RTL_ADVERTISED_10_FULL) {
6301 			new1 |= ADVERTISE_10FULL;
6302 			tp->ups_info.speed_duplex = NWAY_10M_FULL;
6303 		}
6304 
6305 		if (advertising & RTL_ADVERTISED_100_HALF) {
6306 			new1 |= ADVERTISE_100HALF;
6307 			tp->ups_info.speed_duplex = NWAY_100M_HALF;
6308 		}
6309 		if (advertising & RTL_ADVERTISED_100_FULL) {
6310 			new1 |= ADVERTISE_100FULL;
6311 			tp->ups_info.speed_duplex = NWAY_100M_FULL;
6312 		}
6313 
6314 		if (orig != new1) {
6315 			r8152_mdio_write(tp, MII_ADVERTISE, new1);
6316 			tp->mii.advertising = new1;
6317 		}
6318 
6319 		if (tp->mii.supports_gmii) {
6320 			orig = r8152_mdio_read(tp, MII_CTRL1000);
6321 			new1 = orig & ~(ADVERTISE_1000FULL |
6322 					ADVERTISE_1000HALF);
6323 
6324 			if (advertising & RTL_ADVERTISED_1000_FULL) {
6325 				new1 |= ADVERTISE_1000FULL;
6326 				tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6327 			}
6328 
6329 			if (orig != new1)
6330 				r8152_mdio_write(tp, MII_CTRL1000, new1);
6331 		}
6332 
6333 		if (tp->support_2500full) {
6334 			orig = ocp_reg_read(tp, OCP_10GBT_CTRL);
6335 			new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;
6336 
6337 			if (advertising & RTL_ADVERTISED_2500_FULL) {
6338 				new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;
6339 				tp->ups_info.speed_duplex = NWAY_2500M_FULL;
6340 			}
6341 
6342 			if (orig != new1)
6343 				ocp_reg_write(tp, OCP_10GBT_CTRL, new1);
6344 		}
6345 
6346 		bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
6347 
6348 		tp->mii.force_media = 0;
6349 	}
6350 
6351 	if (test_and_clear_bit(PHY_RESET, &tp->flags))
6352 		bmcr |= BMCR_RESET;
6353 
6354 	r8152_mdio_write(tp, MII_BMCR, bmcr);
6355 
6356 	if (bmcr & BMCR_RESET) {
6357 		int i;
6358 
6359 		for (i = 0; i < 50; i++) {
6360 			msleep(20);
6361 			if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
6362 				break;
6363 		}
6364 	}
6365 
6366 out:
6367 	return ret;
6368 }
6369 
6370 static void rtl8152_up(struct r8152 *tp)
6371 {
6372 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6373 		return;
6374 
6375 	r8152_aldps_en(tp, false);
6376 	r8152b_exit_oob(tp);
6377 	r8152_aldps_en(tp, true);
6378 }
6379 
6380 static void rtl8152_down(struct r8152 *tp)
6381 {
6382 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6383 		rtl_drop_queued_tx(tp);
6384 		return;
6385 	}
6386 
6387 	r8152_power_cut_en(tp, false);
6388 	r8152_aldps_en(tp, false);
6389 	r8152b_enter_oob(tp);
6390 	r8152_aldps_en(tp, true);
6391 }
6392 
6393 static void rtl8153_up(struct r8152 *tp)
6394 {
6395 	u32 ocp_data;
6396 
6397 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6398 		return;
6399 
6400 	r8153_u1u2en(tp, false);
6401 	r8153_u2p3en(tp, false);
6402 	r8153_aldps_en(tp, false);
6403 	r8153_first_init(tp);
6404 
6405 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6406 	ocp_data |= LANWAKE_CLR_EN;
6407 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6408 
6409 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6410 	ocp_data &= ~LANWAKE_PIN;
6411 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
6412 
6413 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
6414 	ocp_data &= ~DELAY_PHY_PWR_CHG;
6415 	ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
6416 
6417 	r8153_aldps_en(tp, true);
6418 
6419 	switch (tp->version) {
6420 	case RTL_VER_03:
6421 	case RTL_VER_04:
6422 		break;
6423 	case RTL_VER_05:
6424 	case RTL_VER_06:
6425 	default:
6426 		r8153_u2p3en(tp, true);
6427 		break;
6428 	}
6429 
6430 	r8153_u1u2en(tp, true);
6431 }
6432 
6433 static void rtl8153_down(struct r8152 *tp)
6434 {
6435 	u32 ocp_data;
6436 
6437 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6438 		rtl_drop_queued_tx(tp);
6439 		return;
6440 	}
6441 
6442 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6443 	ocp_data &= ~LANWAKE_CLR_EN;
6444 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6445 
6446 	r8153_u1u2en(tp, false);
6447 	r8153_u2p3en(tp, false);
6448 	r8153_power_cut_en(tp, false);
6449 	r8153_aldps_en(tp, false);
6450 	r8153_enter_oob(tp);
6451 	r8153_aldps_en(tp, true);
6452 }
6453 
6454 static void rtl8153b_up(struct r8152 *tp)
6455 {
6456 	u32 ocp_data;
6457 
6458 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6459 		return;
6460 
6461 	r8153b_u1u2en(tp, false);
6462 	r8153_u2p3en(tp, false);
6463 	r8153_aldps_en(tp, false);
6464 
6465 	r8153_first_init(tp);
6466 	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6467 
6468 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6469 	ocp_data &= ~PLA_MCU_SPDWN_EN;
6470 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6471 
6472 	r8153_aldps_en(tp, true);
6473 
6474 	if (tp->udev->speed >= USB_SPEED_SUPER)
6475 		r8153b_u1u2en(tp, true);
6476 }
6477 
6478 static void rtl8153b_down(struct r8152 *tp)
6479 {
6480 	u32 ocp_data;
6481 
6482 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6483 		rtl_drop_queued_tx(tp);
6484 		return;
6485 	}
6486 
6487 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6488 	ocp_data |= PLA_MCU_SPDWN_EN;
6489 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6490 
6491 	r8153b_u1u2en(tp, false);
6492 	r8153_u2p3en(tp, false);
6493 	r8153b_power_cut_en(tp, false);
6494 	r8153_aldps_en(tp, false);
6495 	r8153_enter_oob(tp);
6496 	r8153_aldps_en(tp, true);
6497 }
6498 
6499 static void rtl8153c_change_mtu(struct r8152 *tp)
6500 {
6501 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
6502 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64);
6503 
6504 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6505 
6506 	/* Adjust the tx fifo free credit full threshold, otherwise
6507 	 * the fifo would be too small to send a jumbo frame packet.
6508 	 */
6509 	if (tp->netdev->mtu < 8000)
6510 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8);
6511 	else
6512 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8);
6513 }
6514 
6515 static void rtl8153c_up(struct r8152 *tp)
6516 {
6517 	u32 ocp_data;
6518 
6519 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6520 		return;
6521 
6522 	r8153b_u1u2en(tp, false);
6523 	r8153_u2p3en(tp, false);
6524 	r8153_aldps_en(tp, false);
6525 
6526 	rxdy_gated_en(tp, true);
6527 	r8153_teredo_off(tp);
6528 
6529 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6530 	ocp_data &= ~RCR_ACPT_ALL;
6531 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6532 
6533 	rtl8152_nic_reset(tp);
6534 	rtl_reset_bmu(tp);
6535 
6536 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6537 	ocp_data &= ~NOW_IS_OOB;
6538 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6539 
6540 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6541 	ocp_data &= ~MCU_BORW_EN;
6542 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6543 
6544 	wait_oob_link_list_ready(tp);
6545 
6546 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6547 	ocp_data |= RE_INIT_LL;
6548 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6549 
6550 	wait_oob_link_list_ready(tp);
6551 
6552 	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6553 
6554 	rtl8153c_change_mtu(tp);
6555 
6556 	rtl8152_nic_reset(tp);
6557 
6558 	/* rx share fifo credit full threshold */
6559 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02);
6560 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08);
6561 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
6562 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
6563 
6564 	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6565 
6566 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
6567 
6568 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
6569 	ocp_data |= BIT(8);
6570 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
6571 
6572 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
6573 
6574 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6575 	ocp_data &= ~PLA_MCU_SPDWN_EN;
6576 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6577 
6578 	r8153_aldps_en(tp, true);
6579 	r8153b_u1u2en(tp, true);
6580 }
6581 
6582 static void rtl8156_change_mtu(struct r8152 *tp)
6583 {
6584 	u32 rx_max_size = mtu_to_size(tp->netdev->mtu);
6585 
6586 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size);
6587 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
6588 	r8156_fc_parameter(tp);
6589 
6590 	/* TX share fifo free credit full threshold */
6591 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6592 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,
6593 		       ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);
6594 }
6595 
6596 static void rtl8156_up(struct r8152 *tp)
6597 {
6598 	u32 ocp_data;
6599 
6600 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6601 		return;
6602 
6603 	r8153b_u1u2en(tp, false);
6604 	r8153_u2p3en(tp, false);
6605 	r8153_aldps_en(tp, false);
6606 
6607 	rxdy_gated_en(tp, true);
6608 	r8153_teredo_off(tp);
6609 
6610 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6611 	ocp_data &= ~RCR_ACPT_ALL;
6612 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6613 
6614 	rtl8152_nic_reset(tp);
6615 	rtl_reset_bmu(tp);
6616 
6617 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6618 	ocp_data &= ~NOW_IS_OOB;
6619 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6620 
6621 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6622 	ocp_data &= ~MCU_BORW_EN;
6623 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6624 
6625 	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6626 
6627 	rtl8156_change_mtu(tp);
6628 
6629 	switch (tp->version) {
6630 	case RTL_TEST_01:
6631 	case RTL_VER_10:
6632 	case RTL_VER_11:
6633 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
6634 		ocp_data |= ACT_ODMA;
6635 		ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
6636 		break;
6637 	default:
6638 		break;
6639 	}
6640 
6641 	/* share FIFO settings */
6642 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);
6643 	ocp_data &= ~RXFIFO_FULL_MASK;
6644 	ocp_data |= 0x08;
6645 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data);
6646 
6647 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6648 	ocp_data &= ~PLA_MCU_SPDWN_EN;
6649 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6650 
6651 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);
6652 	ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);
6653 	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data);
6654 
6655 	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400);
6656 
6657 	if (tp->saved_wolopts != __rtl_get_wol(tp)) {
6658 		netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n");
6659 		__rtl_set_wol(tp, tp->saved_wolopts);
6660 	}
6661 
6662 	r8153_aldps_en(tp, true);
6663 	r8153_u2p3en(tp, true);
6664 
6665 	if (tp->udev->speed >= USB_SPEED_SUPER)
6666 		r8153b_u1u2en(tp, true);
6667 }
6668 
6669 static void rtl8156_down(struct r8152 *tp)
6670 {
6671 	u32 ocp_data;
6672 
6673 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6674 		rtl_drop_queued_tx(tp);
6675 		return;
6676 	}
6677 
6678 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6679 	ocp_data |= PLA_MCU_SPDWN_EN;
6680 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6681 
6682 	r8153b_u1u2en(tp, false);
6683 	r8153_u2p3en(tp, false);
6684 	r8153b_power_cut_en(tp, false);
6685 	r8153_aldps_en(tp, false);
6686 
6687 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6688 	ocp_data &= ~NOW_IS_OOB;
6689 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6690 
6691 	/* RX FIFO settings for OOB */
6692 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 64 / 16);
6693 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 1024 / 16);
6694 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 4096 / 16);
6695 
6696 	rtl_disable(tp);
6697 	rtl_reset_bmu(tp);
6698 
6699 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522);
6700 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
6701 
6702 	/* Clear teredo wake event. bit[15:8] is the teredo wakeup
6703 	 * type. Set it to zero. bits[7:0] are the W1C bits about
6704 	 * the events. Set them to all 1 to clear them.
6705 	 */
6706 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
6707 
6708 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6709 	ocp_data |= NOW_IS_OOB;
6710 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6711 
6712 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6713 	ocp_data |= MCU_BORW_EN;
6714 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6715 
6716 	rtl_rx_vlan_en(tp, true);
6717 	rxdy_gated_en(tp, false);
6718 
6719 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6720 	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6721 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6722 
6723 	r8153_aldps_en(tp, true);
6724 }
6725 
6726 static bool rtl8152_in_nway(struct r8152 *tp)
6727 {
6728 	u16 nway_state;
6729 
6730 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
6731 	tp->ocp_base = 0x2000;
6732 	ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);		/* phy state */
6733 	nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
6734 
6735 	/* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
6736 	if (nway_state & 0xc000)
6737 		return false;
6738 	else
6739 		return true;
6740 }
6741 
6742 static bool rtl8153_in_nway(struct r8152 *tp)
6743 {
6744 	u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
6745 
6746 	if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
6747 		return false;
6748 	else
6749 		return true;
6750 }
6751 
6752 static void r8156_mdio_force_mode(struct r8152 *tp)
6753 {
6754 	u16 data;
6755 
6756 	/* Select force mode through 0xa5b4 bit 15
6757 	 * 0: MDIO force mode
6758 	 * 1: MMD force mode
6759 	 */
6760 	data = ocp_reg_read(tp, 0xa5b4);
6761 	if (data & BIT(15)) {
6762 		data &= ~BIT(15);
6763 		ocp_reg_write(tp, 0xa5b4, data);
6764 	}
6765 }
6766 
6767 static void set_carrier(struct r8152 *tp)
6768 {
6769 	struct net_device *netdev = tp->netdev;
6770 	struct napi_struct *napi = &tp->napi;
6771 	u16 speed;
6772 
6773 	speed = rtl8152_get_speed(tp);
6774 
6775 	if (speed & LINK_STATUS) {
6776 		if (!netif_carrier_ok(netdev)) {
6777 			tp->rtl_ops.enable(tp);
6778 			netif_stop_queue(netdev);
6779 			napi_disable(napi);
6780 			netif_carrier_on(netdev);
6781 			rtl_start_rx(tp);
6782 			clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6783 			_rtl8152_set_rx_mode(netdev);
6784 			napi_enable(napi);
6785 			netif_wake_queue(netdev);
6786 			netif_info(tp, link, netdev, "carrier on\n");
6787 		} else if (netif_queue_stopped(netdev) &&
6788 			   skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
6789 			netif_wake_queue(netdev);
6790 		}
6791 	} else {
6792 		if (netif_carrier_ok(netdev)) {
6793 			netif_carrier_off(netdev);
6794 			tasklet_disable(&tp->tx_tl);
6795 			napi_disable(napi);
6796 			tp->rtl_ops.disable(tp);
6797 			napi_enable(napi);
6798 			tasklet_enable(&tp->tx_tl);
6799 			netif_info(tp, link, netdev, "carrier off\n");
6800 		}
6801 	}
6802 }
6803 
6804 static void rtl_work_func_t(struct work_struct *work)
6805 {
6806 	struct r8152 *tp = container_of(work, struct r8152, schedule.work);
6807 
6808 	/* If the device is unplugged or !netif_running(), the workqueue
6809 	 * doesn't need to wake the device, and could return directly.
6810 	 */
6811 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) || !netif_running(tp->netdev))
6812 		return;
6813 
6814 	if (usb_autopm_get_interface(tp->intf) < 0)
6815 		return;
6816 
6817 	if (!test_bit(WORK_ENABLE, &tp->flags))
6818 		goto out1;
6819 
6820 	if (!mutex_trylock(&tp->control)) {
6821 		schedule_delayed_work(&tp->schedule, 0);
6822 		goto out1;
6823 	}
6824 
6825 	if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
6826 		set_carrier(tp);
6827 
6828 	if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
6829 		_rtl8152_set_rx_mode(tp->netdev);
6830 
6831 	/* don't schedule tasket before linking */
6832 	if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
6833 	    netif_carrier_ok(tp->netdev))
6834 		tasklet_schedule(&tp->tx_tl);
6835 
6836 	if (test_and_clear_bit(RX_EPROTO, &tp->flags) &&
6837 	    !list_empty(&tp->rx_done))
6838 		napi_schedule(&tp->napi);
6839 
6840 	mutex_unlock(&tp->control);
6841 
6842 out1:
6843 	usb_autopm_put_interface(tp->intf);
6844 }
6845 
6846 static void rtl_hw_phy_work_func_t(struct work_struct *work)
6847 {
6848 	struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
6849 
6850 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6851 		return;
6852 
6853 	if (usb_autopm_get_interface(tp->intf) < 0)
6854 		return;
6855 
6856 	mutex_lock(&tp->control);
6857 
6858 	if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
6859 		tp->rtl_fw.retry = false;
6860 		tp->rtl_fw.fw = NULL;
6861 
6862 		/* Delay execution in case request_firmware() is not ready yet.
6863 		 */
6864 		queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
6865 		goto ignore_once;
6866 	}
6867 
6868 	tp->rtl_ops.hw_phy_cfg(tp);
6869 
6870 	rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
6871 			  tp->advertising);
6872 
6873 ignore_once:
6874 	mutex_unlock(&tp->control);
6875 
6876 	usb_autopm_put_interface(tp->intf);
6877 }
6878 
6879 #ifdef CONFIG_PM_SLEEP
6880 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
6881 			void *data)
6882 {
6883 	struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
6884 
6885 	switch (action) {
6886 	case PM_HIBERNATION_PREPARE:
6887 	case PM_SUSPEND_PREPARE:
6888 		usb_autopm_get_interface(tp->intf);
6889 		break;
6890 
6891 	case PM_POST_HIBERNATION:
6892 	case PM_POST_SUSPEND:
6893 		usb_autopm_put_interface(tp->intf);
6894 		break;
6895 
6896 	case PM_POST_RESTORE:
6897 	case PM_RESTORE_PREPARE:
6898 	default:
6899 		break;
6900 	}
6901 
6902 	return NOTIFY_DONE;
6903 }
6904 #endif
6905 
6906 static int rtl8152_open(struct net_device *netdev)
6907 {
6908 	struct r8152 *tp = netdev_priv(netdev);
6909 	int res = 0;
6910 
6911 	if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
6912 		cancel_delayed_work_sync(&tp->hw_phy_work);
6913 		rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
6914 	}
6915 
6916 	res = alloc_all_mem(tp);
6917 	if (res)
6918 		goto out;
6919 
6920 	res = usb_autopm_get_interface(tp->intf);
6921 	if (res < 0)
6922 		goto out_free;
6923 
6924 	mutex_lock(&tp->control);
6925 
6926 	tp->rtl_ops.up(tp);
6927 
6928 	netif_carrier_off(netdev);
6929 	netif_start_queue(netdev);
6930 	set_bit(WORK_ENABLE, &tp->flags);
6931 
6932 	res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
6933 	if (res) {
6934 		if (res == -ENODEV)
6935 			netif_device_detach(tp->netdev);
6936 		netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
6937 			   res);
6938 		goto out_unlock;
6939 	}
6940 	napi_enable(&tp->napi);
6941 	tasklet_enable(&tp->tx_tl);
6942 
6943 	mutex_unlock(&tp->control);
6944 
6945 	usb_autopm_put_interface(tp->intf);
6946 #ifdef CONFIG_PM_SLEEP
6947 	tp->pm_notifier.notifier_call = rtl_notifier;
6948 	register_pm_notifier(&tp->pm_notifier);
6949 #endif
6950 	return 0;
6951 
6952 out_unlock:
6953 	mutex_unlock(&tp->control);
6954 	usb_autopm_put_interface(tp->intf);
6955 out_free:
6956 	free_all_mem(tp);
6957 out:
6958 	return res;
6959 }
6960 
6961 static int rtl8152_close(struct net_device *netdev)
6962 {
6963 	struct r8152 *tp = netdev_priv(netdev);
6964 	int res = 0;
6965 
6966 #ifdef CONFIG_PM_SLEEP
6967 	unregister_pm_notifier(&tp->pm_notifier);
6968 #endif
6969 	tasklet_disable(&tp->tx_tl);
6970 	clear_bit(WORK_ENABLE, &tp->flags);
6971 	usb_kill_urb(tp->intr_urb);
6972 	cancel_delayed_work_sync(&tp->schedule);
6973 	napi_disable(&tp->napi);
6974 	netif_stop_queue(netdev);
6975 
6976 	res = usb_autopm_get_interface(tp->intf);
6977 	if (res < 0 || test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6978 		rtl_drop_queued_tx(tp);
6979 		rtl_stop_rx(tp);
6980 	} else {
6981 		mutex_lock(&tp->control);
6982 
6983 		tp->rtl_ops.down(tp);
6984 
6985 		mutex_unlock(&tp->control);
6986 	}
6987 
6988 	if (!res)
6989 		usb_autopm_put_interface(tp->intf);
6990 
6991 	free_all_mem(tp);
6992 
6993 	return res;
6994 }
6995 
6996 static void rtl_tally_reset(struct r8152 *tp)
6997 {
6998 	u32 ocp_data;
6999 
7000 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
7001 	ocp_data |= TALLY_RESET;
7002 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
7003 }
7004 
7005 static void r8152b_init(struct r8152 *tp)
7006 {
7007 	u32 ocp_data;
7008 	u16 data;
7009 
7010 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7011 		return;
7012 
7013 	data = r8152_mdio_read(tp, MII_BMCR);
7014 	if (data & BMCR_PDOWN) {
7015 		data &= ~BMCR_PDOWN;
7016 		r8152_mdio_write(tp, MII_BMCR, data);
7017 	}
7018 
7019 	r8152_aldps_en(tp, false);
7020 
7021 	if (tp->version == RTL_VER_01) {
7022 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
7023 		ocp_data &= ~LED_MODE_MASK;
7024 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
7025 	}
7026 
7027 	r8152_power_cut_en(tp, false);
7028 
7029 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7030 	ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
7031 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7032 	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
7033 	ocp_data &= ~MCU_CLK_RATIO_MASK;
7034 	ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
7035 	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
7036 	ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
7037 		   SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
7038 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
7039 
7040 	rtl_tally_reset(tp);
7041 
7042 	/* enable rx aggregation */
7043 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7044 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7045 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7046 }
7047 
7048 static void r8153_init(struct r8152 *tp)
7049 {
7050 	u32 ocp_data;
7051 	u16 data;
7052 	int i;
7053 
7054 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7055 		return;
7056 
7057 	r8153_u1u2en(tp, false);
7058 
7059 	for (i = 0; i < 500; i++) {
7060 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7061 		    AUTOLOAD_DONE)
7062 			break;
7063 
7064 		msleep(20);
7065 		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7066 			break;
7067 	}
7068 
7069 	data = r8153_phy_status(tp, 0);
7070 
7071 	if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
7072 	    tp->version == RTL_VER_05)
7073 		ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
7074 
7075 	data = r8152_mdio_read(tp, MII_BMCR);
7076 	if (data & BMCR_PDOWN) {
7077 		data &= ~BMCR_PDOWN;
7078 		r8152_mdio_write(tp, MII_BMCR, data);
7079 	}
7080 
7081 	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7082 
7083 	r8153_u2p3en(tp, false);
7084 
7085 	if (tp->version == RTL_VER_04) {
7086 		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
7087 		ocp_data &= ~pwd_dn_scale_mask;
7088 		ocp_data |= pwd_dn_scale(96);
7089 		ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
7090 
7091 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
7092 		ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
7093 		ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
7094 	} else if (tp->version == RTL_VER_05) {
7095 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
7096 		ocp_data &= ~ECM_ALDPS;
7097 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
7098 
7099 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
7100 		if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
7101 			ocp_data &= ~DYNAMIC_BURST;
7102 		else
7103 			ocp_data |= DYNAMIC_BURST;
7104 		ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
7105 	} else if (tp->version == RTL_VER_06) {
7106 		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
7107 		if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
7108 			ocp_data &= ~DYNAMIC_BURST;
7109 		else
7110 			ocp_data |= DYNAMIC_BURST;
7111 		ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
7112 
7113 		r8153_queue_wake(tp, false);
7114 
7115 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7116 		if (rtl8152_get_speed(tp) & LINK_STATUS)
7117 			ocp_data |= CUR_LINK_OK;
7118 		else
7119 			ocp_data &= ~CUR_LINK_OK;
7120 		ocp_data |= POLL_LINK_CHG;
7121 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7122 	}
7123 
7124 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
7125 	ocp_data |= EP4_FULL_FC;
7126 	ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
7127 
7128 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
7129 	ocp_data &= ~TIMER11_EN;
7130 	ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
7131 
7132 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
7133 	ocp_data &= ~LED_MODE_MASK;
7134 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
7135 
7136 	ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
7137 	if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
7138 		ocp_data |= LPM_TIMER_500MS;
7139 	else
7140 		ocp_data |= LPM_TIMER_500US;
7141 	ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
7142 
7143 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
7144 	ocp_data &= ~SEN_VAL_MASK;
7145 	ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
7146 	ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
7147 
7148 	ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
7149 
7150 	r8153_power_cut_en(tp, false);
7151 	rtl_runtime_suspend_enable(tp, false);
7152 	r8153_mac_clk_speed_down(tp, false);
7153 	r8153_u1u2en(tp, true);
7154 	usb_enable_lpm(tp->udev);
7155 
7156 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
7157 	ocp_data |= LANWAKE_CLR_EN;
7158 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
7159 
7160 	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
7161 	ocp_data &= ~LANWAKE_PIN;
7162 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
7163 
7164 	/* rx aggregation */
7165 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7166 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7167 	if (tp->dell_tb_rx_agg_bug)
7168 		ocp_data |= RX_AGG_DISABLE;
7169 
7170 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7171 
7172 	rtl_tally_reset(tp);
7173 
7174 	switch (tp->udev->speed) {
7175 	case USB_SPEED_SUPER:
7176 	case USB_SPEED_SUPER_PLUS:
7177 		tp->coalesce = COALESCE_SUPER;
7178 		break;
7179 	case USB_SPEED_HIGH:
7180 		tp->coalesce = COALESCE_HIGH;
7181 		break;
7182 	default:
7183 		tp->coalesce = COALESCE_SLOW;
7184 		break;
7185 	}
7186 }
7187 
7188 static void r8153b_init(struct r8152 *tp)
7189 {
7190 	u32 ocp_data;
7191 	u16 data;
7192 	int i;
7193 
7194 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7195 		return;
7196 
7197 	r8153b_u1u2en(tp, false);
7198 
7199 	for (i = 0; i < 500; i++) {
7200 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7201 		    AUTOLOAD_DONE)
7202 			break;
7203 
7204 		msleep(20);
7205 		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7206 			break;
7207 	}
7208 
7209 	data = r8153_phy_status(tp, 0);
7210 
7211 	data = r8152_mdio_read(tp, MII_BMCR);
7212 	if (data & BMCR_PDOWN) {
7213 		data &= ~BMCR_PDOWN;
7214 		r8152_mdio_write(tp, MII_BMCR, data);
7215 	}
7216 
7217 	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7218 
7219 	r8153_u2p3en(tp, false);
7220 
7221 	/* MSC timer = 0xfff * 8ms = 32760 ms */
7222 	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7223 
7224 	r8153b_power_cut_en(tp, false);
7225 	r8153b_ups_en(tp, false);
7226 	r8153_queue_wake(tp, false);
7227 	rtl_runtime_suspend_enable(tp, false);
7228 
7229 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7230 	if (rtl8152_get_speed(tp) & LINK_STATUS)
7231 		ocp_data |= CUR_LINK_OK;
7232 	else
7233 		ocp_data &= ~CUR_LINK_OK;
7234 	ocp_data |= POLL_LINK_CHG;
7235 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7236 
7237 	if (tp->udev->speed >= USB_SPEED_SUPER)
7238 		r8153b_u1u2en(tp, true);
7239 
7240 	usb_enable_lpm(tp->udev);
7241 
7242 	/* MAC clock speed down */
7243 	r8153_mac_clk_speed_down(tp, true);
7244 
7245 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7246 	ocp_data &= ~PLA_MCU_SPDWN_EN;
7247 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
7248 
7249 	if (tp->version == RTL_VER_09) {
7250 		/* Disable Test IO for 32QFN */
7251 		if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
7252 			ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7253 			ocp_data |= TEST_IO_OFF;
7254 			ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7255 		}
7256 	}
7257 
7258 	set_bit(GREEN_ETHERNET, &tp->flags);
7259 
7260 	/* rx aggregation */
7261 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7262 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7263 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7264 
7265 	rtl_tally_reset(tp);
7266 
7267 	tp->coalesce = 15000;	/* 15 us */
7268 }
7269 
7270 static void r8153c_init(struct r8152 *tp)
7271 {
7272 	u32 ocp_data;
7273 	u16 data;
7274 	int i;
7275 
7276 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7277 		return;
7278 
7279 	r8153b_u1u2en(tp, false);
7280 
7281 	/* Disable spi_en */
7282 	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
7283 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
7284 	ocp_data &= ~BIT(3);
7285 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
7286 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0);
7287 	ocp_data |= BIT(1);
7288 	ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data);
7289 
7290 	for (i = 0; i < 500; i++) {
7291 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7292 		    AUTOLOAD_DONE)
7293 			break;
7294 
7295 		msleep(20);
7296 		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7297 			return;
7298 	}
7299 
7300 	data = r8153_phy_status(tp, 0);
7301 
7302 	data = r8152_mdio_read(tp, MII_BMCR);
7303 	if (data & BMCR_PDOWN) {
7304 		data &= ~BMCR_PDOWN;
7305 		r8152_mdio_write(tp, MII_BMCR, data);
7306 	}
7307 
7308 	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7309 
7310 	r8153_u2p3en(tp, false);
7311 
7312 	/* MSC timer = 0xfff * 8ms = 32760 ms */
7313 	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7314 
7315 	r8153b_power_cut_en(tp, false);
7316 	r8153c_ups_en(tp, false);
7317 	r8153_queue_wake(tp, false);
7318 	rtl_runtime_suspend_enable(tp, false);
7319 
7320 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7321 	if (rtl8152_get_speed(tp) & LINK_STATUS)
7322 		ocp_data |= CUR_LINK_OK;
7323 	else
7324 		ocp_data &= ~CUR_LINK_OK;
7325 
7326 	ocp_data |= POLL_LINK_CHG;
7327 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7328 
7329 	r8153b_u1u2en(tp, true);
7330 
7331 	usb_enable_lpm(tp->udev);
7332 
7333 	/* MAC clock speed down */
7334 	r8153_mac_clk_speed_down(tp, true);
7335 
7336 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
7337 	ocp_data &= ~BIT(7);
7338 	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
7339 
7340 	set_bit(GREEN_ETHERNET, &tp->flags);
7341 
7342 	/* rx aggregation */
7343 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7344 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7345 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7346 
7347 	rtl_tally_reset(tp);
7348 
7349 	tp->coalesce = 15000;	/* 15 us */
7350 }
7351 
7352 static void r8156_hw_phy_cfg(struct r8152 *tp)
7353 {
7354 	u32 ocp_data;
7355 	u16 data;
7356 
7357 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7358 	if (ocp_data & PCUT_STATUS) {
7359 		ocp_data &= ~PCUT_STATUS;
7360 		ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7361 	}
7362 
7363 	data = r8153_phy_status(tp, 0);
7364 	switch (data) {
7365 	case PHY_STAT_EXT_INIT:
7366 		rtl8152_apply_firmware(tp, true);
7367 
7368 		data = ocp_reg_read(tp, 0xa468);
7369 		data &= ~(BIT(3) | BIT(1));
7370 		ocp_reg_write(tp, 0xa468, data);
7371 		break;
7372 	case PHY_STAT_LAN_ON:
7373 	case PHY_STAT_PWRDN:
7374 	default:
7375 		rtl8152_apply_firmware(tp, false);
7376 		break;
7377 	}
7378 
7379 	/* disable ALDPS before updating the PHY parameters */
7380 	r8153_aldps_en(tp, false);
7381 
7382 	/* disable EEE before updating the PHY parameters */
7383 	rtl_eee_enable(tp, false);
7384 
7385 	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7386 	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7387 
7388 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7389 	ocp_data |= PFM_PWM_SWITCH;
7390 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7391 
7392 	switch (tp->version) {
7393 	case RTL_VER_10:
7394 		data = ocp_reg_read(tp, 0xad40);
7395 		data &= ~0x3ff;
7396 		data |= BIT(7) | BIT(2);
7397 		ocp_reg_write(tp, 0xad40, data);
7398 
7399 		data = ocp_reg_read(tp, 0xad4e);
7400 		data |= BIT(4);
7401 		ocp_reg_write(tp, 0xad4e, data);
7402 		data = ocp_reg_read(tp, 0xad16);
7403 		data &= ~0x3ff;
7404 		data |= 0x6;
7405 		ocp_reg_write(tp, 0xad16, data);
7406 		data = ocp_reg_read(tp, 0xad32);
7407 		data &= ~0x3f;
7408 		data |= 6;
7409 		ocp_reg_write(tp, 0xad32, data);
7410 		data = ocp_reg_read(tp, 0xac08);
7411 		data &= ~(BIT(12) | BIT(8));
7412 		ocp_reg_write(tp, 0xac08, data);
7413 		data = ocp_reg_read(tp, 0xac8a);
7414 		data |= BIT(12) | BIT(13) | BIT(14);
7415 		data &= ~BIT(15);
7416 		ocp_reg_write(tp, 0xac8a, data);
7417 		data = ocp_reg_read(tp, 0xad18);
7418 		data |= BIT(10);
7419 		ocp_reg_write(tp, 0xad18, data);
7420 		data = ocp_reg_read(tp, 0xad1a);
7421 		data |= 0x3ff;
7422 		ocp_reg_write(tp, 0xad1a, data);
7423 		data = ocp_reg_read(tp, 0xad1c);
7424 		data |= 0x3ff;
7425 		ocp_reg_write(tp, 0xad1c, data);
7426 
7427 		data = sram_read(tp, 0x80ea);
7428 		data &= ~0xff00;
7429 		data |= 0xc400;
7430 		sram_write(tp, 0x80ea, data);
7431 		data = sram_read(tp, 0x80eb);
7432 		data &= ~0x0700;
7433 		data |= 0x0300;
7434 		sram_write(tp, 0x80eb, data);
7435 		data = sram_read(tp, 0x80f8);
7436 		data &= ~0xff00;
7437 		data |= 0x1c00;
7438 		sram_write(tp, 0x80f8, data);
7439 		data = sram_read(tp, 0x80f1);
7440 		data &= ~0xff00;
7441 		data |= 0x3000;
7442 		sram_write(tp, 0x80f1, data);
7443 
7444 		data = sram_read(tp, 0x80fe);
7445 		data &= ~0xff00;
7446 		data |= 0xa500;
7447 		sram_write(tp, 0x80fe, data);
7448 		data = sram_read(tp, 0x8102);
7449 		data &= ~0xff00;
7450 		data |= 0x5000;
7451 		sram_write(tp, 0x8102, data);
7452 		data = sram_read(tp, 0x8015);
7453 		data &= ~0xff00;
7454 		data |= 0x3300;
7455 		sram_write(tp, 0x8015, data);
7456 		data = sram_read(tp, 0x8100);
7457 		data &= ~0xff00;
7458 		data |= 0x7000;
7459 		sram_write(tp, 0x8100, data);
7460 		data = sram_read(tp, 0x8014);
7461 		data &= ~0xff00;
7462 		data |= 0xf000;
7463 		sram_write(tp, 0x8014, data);
7464 		data = sram_read(tp, 0x8016);
7465 		data &= ~0xff00;
7466 		data |= 0x6500;
7467 		sram_write(tp, 0x8016, data);
7468 		data = sram_read(tp, 0x80dc);
7469 		data &= ~0xff00;
7470 		data |= 0xed00;
7471 		sram_write(tp, 0x80dc, data);
7472 		data = sram_read(tp, 0x80df);
7473 		data |= BIT(8);
7474 		sram_write(tp, 0x80df, data);
7475 		data = sram_read(tp, 0x80e1);
7476 		data &= ~BIT(8);
7477 		sram_write(tp, 0x80e1, data);
7478 
7479 		data = ocp_reg_read(tp, 0xbf06);
7480 		data &= ~0x003f;
7481 		data |= 0x0038;
7482 		ocp_reg_write(tp, 0xbf06, data);
7483 
7484 		sram_write(tp, 0x819f, 0xddb6);
7485 
7486 		ocp_reg_write(tp, 0xbc34, 0x5555);
7487 		data = ocp_reg_read(tp, 0xbf0a);
7488 		data &= ~0x0e00;
7489 		data |= 0x0a00;
7490 		ocp_reg_write(tp, 0xbf0a, data);
7491 
7492 		data = ocp_reg_read(tp, 0xbd2c);
7493 		data &= ~BIT(13);
7494 		ocp_reg_write(tp, 0xbd2c, data);
7495 		break;
7496 	case RTL_VER_11:
7497 		data = ocp_reg_read(tp, 0xad16);
7498 		data |= 0x3ff;
7499 		ocp_reg_write(tp, 0xad16, data);
7500 		data = ocp_reg_read(tp, 0xad32);
7501 		data &= ~0x3f;
7502 		data |= 6;
7503 		ocp_reg_write(tp, 0xad32, data);
7504 		data = ocp_reg_read(tp, 0xac08);
7505 		data &= ~(BIT(12) | BIT(8));
7506 		ocp_reg_write(tp, 0xac08, data);
7507 		data = ocp_reg_read(tp, 0xacc0);
7508 		data &= ~0x3;
7509 		data |= BIT(1);
7510 		ocp_reg_write(tp, 0xacc0, data);
7511 		data = ocp_reg_read(tp, 0xad40);
7512 		data &= ~0xe7;
7513 		data |= BIT(6) | BIT(2);
7514 		ocp_reg_write(tp, 0xad40, data);
7515 		data = ocp_reg_read(tp, 0xac14);
7516 		data &= ~BIT(7);
7517 		ocp_reg_write(tp, 0xac14, data);
7518 		data = ocp_reg_read(tp, 0xac80);
7519 		data &= ~(BIT(8) | BIT(9));
7520 		ocp_reg_write(tp, 0xac80, data);
7521 		data = ocp_reg_read(tp, 0xac5e);
7522 		data &= ~0x7;
7523 		data |= BIT(1);
7524 		ocp_reg_write(tp, 0xac5e, data);
7525 		ocp_reg_write(tp, 0xad4c, 0x00a8);
7526 		ocp_reg_write(tp, 0xac5c, 0x01ff);
7527 		data = ocp_reg_read(tp, 0xac8a);
7528 		data &= ~0xf0;
7529 		data |= BIT(4) | BIT(5);
7530 		ocp_reg_write(tp, 0xac8a, data);
7531 		ocp_reg_write(tp, 0xb87c, 0x8157);
7532 		data = ocp_reg_read(tp, 0xb87e);
7533 		data &= ~0xff00;
7534 		data |= 0x0500;
7535 		ocp_reg_write(tp, 0xb87e, data);
7536 		ocp_reg_write(tp, 0xb87c, 0x8159);
7537 		data = ocp_reg_read(tp, 0xb87e);
7538 		data &= ~0xff00;
7539 		data |= 0x0700;
7540 		ocp_reg_write(tp, 0xb87e, data);
7541 
7542 		/* AAGC */
7543 		ocp_reg_write(tp, 0xb87c, 0x80a2);
7544 		ocp_reg_write(tp, 0xb87e, 0x0153);
7545 		ocp_reg_write(tp, 0xb87c, 0x809c);
7546 		ocp_reg_write(tp, 0xb87e, 0x0153);
7547 
7548 		/* EEE parameter */
7549 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);
7550 
7551 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7552 		ocp_data |= EN_XG_LIP | EN_G_LIP;
7553 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7554 
7555 		sram_write(tp, 0x8257, 0x020f); /*  XG PLL */
7556 		sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */
7557 
7558 		if (rtl_phy_patch_request(tp, true, true))
7559 			return;
7560 
7561 		/* Advance EEE */
7562 		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7563 		ocp_data |= EEE_SPDWN_EN;
7564 		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
7565 
7566 		data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7567 		data &= ~(EN_EEE_100 | EN_EEE_1000);
7568 		data |= EN_10M_CLKDIV;
7569 		ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7570 		tp->ups_info._10m_ckdiv = true;
7571 		tp->ups_info.eee_plloff_100 = false;
7572 		tp->ups_info.eee_plloff_giga = false;
7573 
7574 		data = ocp_reg_read(tp, OCP_POWER_CFG);
7575 		data &= ~EEE_CLKDIV_EN;
7576 		ocp_reg_write(tp, OCP_POWER_CFG, data);
7577 		tp->ups_info.eee_ckdiv = false;
7578 
7579 		ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
7580 		ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));
7581 		tp->ups_info._250m_ckdiv = false;
7582 
7583 		rtl_phy_patch_request(tp, false, true);
7584 
7585 		/* enable ADC Ibias Cal */
7586 		data = ocp_reg_read(tp, 0xd068);
7587 		data |= BIT(13);
7588 		ocp_reg_write(tp, 0xd068, data);
7589 
7590 		/* enable Thermal Sensor */
7591 		data = sram_read(tp, 0x81a2);
7592 		data &= ~BIT(8);
7593 		sram_write(tp, 0x81a2, data);
7594 		data = ocp_reg_read(tp, 0xb54c);
7595 		data &= ~0xff00;
7596 		data |= 0xdb00;
7597 		ocp_reg_write(tp, 0xb54c, data);
7598 
7599 		/* Nway 2.5G Lite */
7600 		data = ocp_reg_read(tp, 0xa454);
7601 		data &= ~BIT(0);
7602 		ocp_reg_write(tp, 0xa454, data);
7603 
7604 		/* CS DSP solution */
7605 		data = ocp_reg_read(tp, OCP_10GBT_CTRL);
7606 		data |= RTL_ADV2_5G_F_R;
7607 		ocp_reg_write(tp, OCP_10GBT_CTRL, data);
7608 		data = ocp_reg_read(tp, 0xad4e);
7609 		data &= ~BIT(4);
7610 		ocp_reg_write(tp, 0xad4e, data);
7611 		data = ocp_reg_read(tp, 0xa86a);
7612 		data &= ~BIT(0);
7613 		ocp_reg_write(tp, 0xa86a, data);
7614 
7615 		/* MDI SWAP */
7616 		if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&
7617 		    (ocp_reg_read(tp, 0xd068) & BIT(1))) {
7618 			u16 swap_a, swap_b;
7619 
7620 			data = ocp_reg_read(tp, 0xd068);
7621 			data &= ~0x1f;
7622 			data |= 0x1; /* p0 */
7623 			ocp_reg_write(tp, 0xd068, data);
7624 			swap_a = ocp_reg_read(tp, 0xd06a);
7625 			data &= ~0x18;
7626 			data |= 0x18; /* p3 */
7627 			ocp_reg_write(tp, 0xd068, data);
7628 			swap_b = ocp_reg_read(tp, 0xd06a);
7629 			data &= ~0x18; /* p0 */
7630 			ocp_reg_write(tp, 0xd068, data);
7631 			ocp_reg_write(tp, 0xd06a,
7632 				      (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7633 			data |= 0x18; /* p3 */
7634 			ocp_reg_write(tp, 0xd068, data);
7635 			ocp_reg_write(tp, 0xd06a,
7636 				      (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7637 			data &= ~0x18;
7638 			data |= 0x08; /* p1 */
7639 			ocp_reg_write(tp, 0xd068, data);
7640 			swap_a = ocp_reg_read(tp, 0xd06a);
7641 			data &= ~0x18;
7642 			data |= 0x10; /* p2 */
7643 			ocp_reg_write(tp, 0xd068, data);
7644 			swap_b = ocp_reg_read(tp, 0xd06a);
7645 			data &= ~0x18;
7646 			data |= 0x08; /* p1 */
7647 			ocp_reg_write(tp, 0xd068, data);
7648 			ocp_reg_write(tp, 0xd06a,
7649 				      (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7650 			data &= ~0x18;
7651 			data |= 0x10; /* p2 */
7652 			ocp_reg_write(tp, 0xd068, data);
7653 			ocp_reg_write(tp, 0xd06a,
7654 				      (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7655 			swap_a = ocp_reg_read(tp, 0xbd5a);
7656 			swap_b = ocp_reg_read(tp, 0xbd5c);
7657 			ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) |
7658 				      ((swap_b & 0x1f) << 8) |
7659 				      ((swap_b >> 8) & 0x1f));
7660 			ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) |
7661 				      ((swap_a & 0x1f) << 8) |
7662 				      ((swap_a >> 8) & 0x1f));
7663 			swap_a = ocp_reg_read(tp, 0xbc18);
7664 			swap_b = ocp_reg_read(tp, 0xbc1a);
7665 			ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) |
7666 				      ((swap_b & 0x1f) << 8) |
7667 				      ((swap_b >> 8) & 0x1f));
7668 			ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) |
7669 				      ((swap_a & 0x1f) << 8) |
7670 				      ((swap_a >> 8) & 0x1f));
7671 		}
7672 
7673 		/* Notify the MAC when the speed is changed to force mode. */
7674 		data = ocp_reg_read(tp, OCP_INTR_EN);
7675 		data |= INTR_SPEED_FORCE;
7676 		ocp_reg_write(tp, OCP_INTR_EN, data);
7677 		break;
7678 	default:
7679 		break;
7680 	}
7681 
7682 	rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7683 
7684 	data = ocp_reg_read(tp, 0xa428);
7685 	data &= ~BIT(9);
7686 	ocp_reg_write(tp, 0xa428, data);
7687 	data = ocp_reg_read(tp, 0xa5ea);
7688 	data &= ~BIT(0);
7689 	ocp_reg_write(tp, 0xa5ea, data);
7690 	tp->ups_info.lite_mode = 0;
7691 
7692 	if (tp->eee_en)
7693 		rtl_eee_enable(tp, true);
7694 
7695 	r8153_aldps_en(tp, true);
7696 	r8152b_enable_fc(tp);
7697 	r8153_u2p3en(tp, true);
7698 
7699 	set_bit(PHY_RESET, &tp->flags);
7700 }
7701 
7702 static void r8156b_hw_phy_cfg(struct r8152 *tp)
7703 {
7704 	u32 ocp_data;
7705 	u16 data;
7706 
7707 	switch (tp->version) {
7708 	case RTL_VER_12:
7709 		ocp_reg_write(tp, 0xbf86, 0x9000);
7710 		data = ocp_reg_read(tp, 0xc402);
7711 		data |= BIT(10);
7712 		ocp_reg_write(tp, 0xc402, data);
7713 		data &= ~BIT(10);
7714 		ocp_reg_write(tp, 0xc402, data);
7715 		ocp_reg_write(tp, 0xbd86, 0x1010);
7716 		ocp_reg_write(tp, 0xbd88, 0x1010);
7717 		data = ocp_reg_read(tp, 0xbd4e);
7718 		data &= ~(BIT(10) | BIT(11));
7719 		data |= BIT(11);
7720 		ocp_reg_write(tp, 0xbd4e, data);
7721 		data = ocp_reg_read(tp, 0xbf46);
7722 		data &= ~0xf00;
7723 		data |= 0x700;
7724 		ocp_reg_write(tp, 0xbf46, data);
7725 		break;
7726 	case RTL_VER_13:
7727 	case RTL_VER_15:
7728 		r8156b_wait_loading_flash(tp);
7729 		break;
7730 	default:
7731 		break;
7732 	}
7733 
7734 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7735 	if (ocp_data & PCUT_STATUS) {
7736 		ocp_data &= ~PCUT_STATUS;
7737 		ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7738 	}
7739 
7740 	data = r8153_phy_status(tp, 0);
7741 	switch (data) {
7742 	case PHY_STAT_EXT_INIT:
7743 		rtl8152_apply_firmware(tp, true);
7744 
7745 		data = ocp_reg_read(tp, 0xa466);
7746 		data &= ~BIT(0);
7747 		ocp_reg_write(tp, 0xa466, data);
7748 
7749 		data = ocp_reg_read(tp, 0xa468);
7750 		data &= ~(BIT(3) | BIT(1));
7751 		ocp_reg_write(tp, 0xa468, data);
7752 		break;
7753 	case PHY_STAT_LAN_ON:
7754 	case PHY_STAT_PWRDN:
7755 	default:
7756 		rtl8152_apply_firmware(tp, false);
7757 		break;
7758 	}
7759 
7760 	data = r8152_mdio_read(tp, MII_BMCR);
7761 	if (data & BMCR_PDOWN) {
7762 		data &= ~BMCR_PDOWN;
7763 		r8152_mdio_write(tp, MII_BMCR, data);
7764 	}
7765 
7766 	/* disable ALDPS before updating the PHY parameters */
7767 	r8153_aldps_en(tp, false);
7768 
7769 	/* disable EEE before updating the PHY parameters */
7770 	rtl_eee_enable(tp, false);
7771 
7772 	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7773 	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7774 
7775 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7776 	ocp_data |= PFM_PWM_SWITCH;
7777 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7778 
7779 	switch (tp->version) {
7780 	case RTL_VER_12:
7781 		data = ocp_reg_read(tp, 0xbc08);
7782 		data |= BIT(3) | BIT(2);
7783 		ocp_reg_write(tp, 0xbc08, data);
7784 
7785 		data = sram_read(tp, 0x8fff);
7786 		data &= ~0xff00;
7787 		data |= 0x0400;
7788 		sram_write(tp, 0x8fff, data);
7789 
7790 		data = ocp_reg_read(tp, 0xacda);
7791 		data |= 0xff00;
7792 		ocp_reg_write(tp, 0xacda, data);
7793 		data = ocp_reg_read(tp, 0xacde);
7794 		data |= 0xf000;
7795 		ocp_reg_write(tp, 0xacde, data);
7796 		ocp_reg_write(tp, 0xac8c, 0x0ffc);
7797 		ocp_reg_write(tp, 0xac46, 0xb7b4);
7798 		ocp_reg_write(tp, 0xac50, 0x0fbc);
7799 		ocp_reg_write(tp, 0xac3c, 0x9240);
7800 		ocp_reg_write(tp, 0xac4e, 0x0db4);
7801 		ocp_reg_write(tp, 0xacc6, 0x0707);
7802 		ocp_reg_write(tp, 0xacc8, 0xa0d3);
7803 		ocp_reg_write(tp, 0xad08, 0x0007);
7804 
7805 		ocp_reg_write(tp, 0xb87c, 0x8560);
7806 		ocp_reg_write(tp, 0xb87e, 0x19cc);
7807 		ocp_reg_write(tp, 0xb87c, 0x8562);
7808 		ocp_reg_write(tp, 0xb87e, 0x19cc);
7809 		ocp_reg_write(tp, 0xb87c, 0x8564);
7810 		ocp_reg_write(tp, 0xb87e, 0x19cc);
7811 		ocp_reg_write(tp, 0xb87c, 0x8566);
7812 		ocp_reg_write(tp, 0xb87e, 0x147d);
7813 		ocp_reg_write(tp, 0xb87c, 0x8568);
7814 		ocp_reg_write(tp, 0xb87e, 0x147d);
7815 		ocp_reg_write(tp, 0xb87c, 0x856a);
7816 		ocp_reg_write(tp, 0xb87e, 0x147d);
7817 		ocp_reg_write(tp, 0xb87c, 0x8ffe);
7818 		ocp_reg_write(tp, 0xb87e, 0x0907);
7819 		ocp_reg_write(tp, 0xb87c, 0x80d6);
7820 		ocp_reg_write(tp, 0xb87e, 0x2801);
7821 		ocp_reg_write(tp, 0xb87c, 0x80f2);
7822 		ocp_reg_write(tp, 0xb87e, 0x2801);
7823 		ocp_reg_write(tp, 0xb87c, 0x80f4);
7824 		ocp_reg_write(tp, 0xb87e, 0x6077);
7825 		ocp_reg_write(tp, 0xb506, 0x01e7);
7826 
7827 		ocp_reg_write(tp, 0xb87c, 0x8013);
7828 		ocp_reg_write(tp, 0xb87e, 0x0700);
7829 		ocp_reg_write(tp, 0xb87c, 0x8fb9);
7830 		ocp_reg_write(tp, 0xb87e, 0x2801);
7831 		ocp_reg_write(tp, 0xb87c, 0x8fba);
7832 		ocp_reg_write(tp, 0xb87e, 0x0100);
7833 		ocp_reg_write(tp, 0xb87c, 0x8fbc);
7834 		ocp_reg_write(tp, 0xb87e, 0x1900);
7835 		ocp_reg_write(tp, 0xb87c, 0x8fbe);
7836 		ocp_reg_write(tp, 0xb87e, 0xe100);
7837 		ocp_reg_write(tp, 0xb87c, 0x8fc0);
7838 		ocp_reg_write(tp, 0xb87e, 0x0800);
7839 		ocp_reg_write(tp, 0xb87c, 0x8fc2);
7840 		ocp_reg_write(tp, 0xb87e, 0xe500);
7841 		ocp_reg_write(tp, 0xb87c, 0x8fc4);
7842 		ocp_reg_write(tp, 0xb87e, 0x0f00);
7843 		ocp_reg_write(tp, 0xb87c, 0x8fc6);
7844 		ocp_reg_write(tp, 0xb87e, 0xf100);
7845 		ocp_reg_write(tp, 0xb87c, 0x8fc8);
7846 		ocp_reg_write(tp, 0xb87e, 0x0400);
7847 		ocp_reg_write(tp, 0xb87c, 0x8fca);
7848 		ocp_reg_write(tp, 0xb87e, 0xf300);
7849 		ocp_reg_write(tp, 0xb87c, 0x8fcc);
7850 		ocp_reg_write(tp, 0xb87e, 0xfd00);
7851 		ocp_reg_write(tp, 0xb87c, 0x8fce);
7852 		ocp_reg_write(tp, 0xb87e, 0xff00);
7853 		ocp_reg_write(tp, 0xb87c, 0x8fd0);
7854 		ocp_reg_write(tp, 0xb87e, 0xfb00);
7855 		ocp_reg_write(tp, 0xb87c, 0x8fd2);
7856 		ocp_reg_write(tp, 0xb87e, 0x0100);
7857 		ocp_reg_write(tp, 0xb87c, 0x8fd4);
7858 		ocp_reg_write(tp, 0xb87e, 0xf400);
7859 		ocp_reg_write(tp, 0xb87c, 0x8fd6);
7860 		ocp_reg_write(tp, 0xb87e, 0xff00);
7861 		ocp_reg_write(tp, 0xb87c, 0x8fd8);
7862 		ocp_reg_write(tp, 0xb87e, 0xf600);
7863 
7864 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7865 		ocp_data |= EN_XG_LIP | EN_G_LIP;
7866 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7867 		ocp_reg_write(tp, 0xb87c, 0x813d);
7868 		ocp_reg_write(tp, 0xb87e, 0x390e);
7869 		ocp_reg_write(tp, 0xb87c, 0x814f);
7870 		ocp_reg_write(tp, 0xb87e, 0x790e);
7871 		ocp_reg_write(tp, 0xb87c, 0x80b0);
7872 		ocp_reg_write(tp, 0xb87e, 0x0f31);
7873 		data = ocp_reg_read(tp, 0xbf4c);
7874 		data |= BIT(1);
7875 		ocp_reg_write(tp, 0xbf4c, data);
7876 		data = ocp_reg_read(tp, 0xbcca);
7877 		data |= BIT(9) | BIT(8);
7878 		ocp_reg_write(tp, 0xbcca, data);
7879 		ocp_reg_write(tp, 0xb87c, 0x8141);
7880 		ocp_reg_write(tp, 0xb87e, 0x320e);
7881 		ocp_reg_write(tp, 0xb87c, 0x8153);
7882 		ocp_reg_write(tp, 0xb87e, 0x720e);
7883 		ocp_reg_write(tp, 0xb87c, 0x8529);
7884 		ocp_reg_write(tp, 0xb87e, 0x050e);
7885 		data = ocp_reg_read(tp, OCP_EEE_CFG);
7886 		data &= ~CTAP_SHORT_EN;
7887 		ocp_reg_write(tp, OCP_EEE_CFG, data);
7888 
7889 		sram_write(tp, 0x816c, 0xc4a0);
7890 		sram_write(tp, 0x8170, 0xc4a0);
7891 		sram_write(tp, 0x8174, 0x04a0);
7892 		sram_write(tp, 0x8178, 0x04a0);
7893 		sram_write(tp, 0x817c, 0x0719);
7894 		sram_write(tp, 0x8ff4, 0x0400);
7895 		sram_write(tp, 0x8ff1, 0x0404);
7896 
7897 		ocp_reg_write(tp, 0xbf4a, 0x001b);
7898 		ocp_reg_write(tp, 0xb87c, 0x8033);
7899 		ocp_reg_write(tp, 0xb87e, 0x7c13);
7900 		ocp_reg_write(tp, 0xb87c, 0x8037);
7901 		ocp_reg_write(tp, 0xb87e, 0x7c13);
7902 		ocp_reg_write(tp, 0xb87c, 0x803b);
7903 		ocp_reg_write(tp, 0xb87e, 0xfc32);
7904 		ocp_reg_write(tp, 0xb87c, 0x803f);
7905 		ocp_reg_write(tp, 0xb87e, 0x7c13);
7906 		ocp_reg_write(tp, 0xb87c, 0x8043);
7907 		ocp_reg_write(tp, 0xb87e, 0x7c13);
7908 		ocp_reg_write(tp, 0xb87c, 0x8047);
7909 		ocp_reg_write(tp, 0xb87e, 0x7c13);
7910 
7911 		ocp_reg_write(tp, 0xb87c, 0x8145);
7912 		ocp_reg_write(tp, 0xb87e, 0x370e);
7913 		ocp_reg_write(tp, 0xb87c, 0x8157);
7914 		ocp_reg_write(tp, 0xb87e, 0x770e);
7915 		ocp_reg_write(tp, 0xb87c, 0x8169);
7916 		ocp_reg_write(tp, 0xb87e, 0x0d0a);
7917 		ocp_reg_write(tp, 0xb87c, 0x817b);
7918 		ocp_reg_write(tp, 0xb87e, 0x1d0a);
7919 
7920 		data = sram_read(tp, 0x8217);
7921 		data &= ~0xff00;
7922 		data |= 0x5000;
7923 		sram_write(tp, 0x8217, data);
7924 		data = sram_read(tp, 0x821a);
7925 		data &= ~0xff00;
7926 		data |= 0x5000;
7927 		sram_write(tp, 0x821a, data);
7928 		sram_write(tp, 0x80da, 0x0403);
7929 		data = sram_read(tp, 0x80dc);
7930 		data &= ~0xff00;
7931 		data |= 0x1000;
7932 		sram_write(tp, 0x80dc, data);
7933 		sram_write(tp, 0x80b3, 0x0384);
7934 		sram_write(tp, 0x80b7, 0x2007);
7935 		data = sram_read(tp, 0x80ba);
7936 		data &= ~0xff00;
7937 		data |= 0x6c00;
7938 		sram_write(tp, 0x80ba, data);
7939 		sram_write(tp, 0x80b5, 0xf009);
7940 		data = sram_read(tp, 0x80bd);
7941 		data &= ~0xff00;
7942 		data |= 0x9f00;
7943 		sram_write(tp, 0x80bd, data);
7944 		sram_write(tp, 0x80c7, 0xf083);
7945 		sram_write(tp, 0x80dd, 0x03f0);
7946 		data = sram_read(tp, 0x80df);
7947 		data &= ~0xff00;
7948 		data |= 0x1000;
7949 		sram_write(tp, 0x80df, data);
7950 		sram_write(tp, 0x80cb, 0x2007);
7951 		data = sram_read(tp, 0x80ce);
7952 		data &= ~0xff00;
7953 		data |= 0x6c00;
7954 		sram_write(tp, 0x80ce, data);
7955 		sram_write(tp, 0x80c9, 0x8009);
7956 		data = sram_read(tp, 0x80d1);
7957 		data &= ~0xff00;
7958 		data |= 0x8000;
7959 		sram_write(tp, 0x80d1, data);
7960 		sram_write(tp, 0x80a3, 0x200a);
7961 		sram_write(tp, 0x80a5, 0xf0ad);
7962 		sram_write(tp, 0x809f, 0x6073);
7963 		sram_write(tp, 0x80a1, 0x000b);
7964 		data = sram_read(tp, 0x80a9);
7965 		data &= ~0xff00;
7966 		data |= 0xc000;
7967 		sram_write(tp, 0x80a9, data);
7968 
7969 		if (rtl_phy_patch_request(tp, true, true))
7970 			return;
7971 
7972 		data = ocp_reg_read(tp, 0xb896);
7973 		data &= ~BIT(0);
7974 		ocp_reg_write(tp, 0xb896, data);
7975 		data = ocp_reg_read(tp, 0xb892);
7976 		data &= ~0xff00;
7977 		ocp_reg_write(tp, 0xb892, data);
7978 		ocp_reg_write(tp, 0xb88e, 0xc23e);
7979 		ocp_reg_write(tp, 0xb890, 0x0000);
7980 		ocp_reg_write(tp, 0xb88e, 0xc240);
7981 		ocp_reg_write(tp, 0xb890, 0x0103);
7982 		ocp_reg_write(tp, 0xb88e, 0xc242);
7983 		ocp_reg_write(tp, 0xb890, 0x0507);
7984 		ocp_reg_write(tp, 0xb88e, 0xc244);
7985 		ocp_reg_write(tp, 0xb890, 0x090b);
7986 		ocp_reg_write(tp, 0xb88e, 0xc246);
7987 		ocp_reg_write(tp, 0xb890, 0x0c0e);
7988 		ocp_reg_write(tp, 0xb88e, 0xc248);
7989 		ocp_reg_write(tp, 0xb890, 0x1012);
7990 		ocp_reg_write(tp, 0xb88e, 0xc24a);
7991 		ocp_reg_write(tp, 0xb890, 0x1416);
7992 		data = ocp_reg_read(tp, 0xb896);
7993 		data |= BIT(0);
7994 		ocp_reg_write(tp, 0xb896, data);
7995 
7996 		rtl_phy_patch_request(tp, false, true);
7997 
7998 		data = ocp_reg_read(tp, 0xa86a);
7999 		data |= BIT(0);
8000 		ocp_reg_write(tp, 0xa86a, data);
8001 		data = ocp_reg_read(tp, 0xa6f0);
8002 		data |= BIT(0);
8003 		ocp_reg_write(tp, 0xa6f0, data);
8004 
8005 		ocp_reg_write(tp, 0xbfa0, 0xd70d);
8006 		ocp_reg_write(tp, 0xbfa2, 0x4100);
8007 		ocp_reg_write(tp, 0xbfa4, 0xe868);
8008 		ocp_reg_write(tp, 0xbfa6, 0xdc59);
8009 		ocp_reg_write(tp, 0xb54c, 0x3c18);
8010 		data = ocp_reg_read(tp, 0xbfa4);
8011 		data &= ~BIT(5);
8012 		ocp_reg_write(tp, 0xbfa4, data);
8013 		data = sram_read(tp, 0x817d);
8014 		data |= BIT(12);
8015 		sram_write(tp, 0x817d, data);
8016 		break;
8017 	case RTL_VER_13:
8018 		/* 2.5G INRX */
8019 		data = ocp_reg_read(tp, 0xac46);
8020 		data &= ~0x00f0;
8021 		data |= 0x0090;
8022 		ocp_reg_write(tp, 0xac46, data);
8023 		data = ocp_reg_read(tp, 0xad30);
8024 		data &= ~0x0003;
8025 		data |= 0x0001;
8026 		ocp_reg_write(tp, 0xad30, data);
8027 		fallthrough;
8028 	case RTL_VER_15:
8029 		/* EEE parameter */
8030 		ocp_reg_write(tp, 0xb87c, 0x80f5);
8031 		ocp_reg_write(tp, 0xb87e, 0x760e);
8032 		ocp_reg_write(tp, 0xb87c, 0x8107);
8033 		ocp_reg_write(tp, 0xb87e, 0x360e);
8034 		ocp_reg_write(tp, 0xb87c, 0x8551);
8035 		data = ocp_reg_read(tp, 0xb87e);
8036 		data &= ~0xff00;
8037 		data |= 0x0800;
8038 		ocp_reg_write(tp, 0xb87e, data);
8039 
8040 		/* ADC_PGA parameter */
8041 		data = ocp_reg_read(tp, 0xbf00);
8042 		data &= ~0xe000;
8043 		data |= 0xa000;
8044 		ocp_reg_write(tp, 0xbf00, data);
8045 		data = ocp_reg_read(tp, 0xbf46);
8046 		data &= ~0x0f00;
8047 		data |= 0x0300;
8048 		ocp_reg_write(tp, 0xbf46, data);
8049 
8050 		/* Green Table-PGA, 1G full viterbi */
8051 		sram_write(tp, 0x8044, 0x2417);
8052 		sram_write(tp, 0x804a, 0x2417);
8053 		sram_write(tp, 0x8050, 0x2417);
8054 		sram_write(tp, 0x8056, 0x2417);
8055 		sram_write(tp, 0x805c, 0x2417);
8056 		sram_write(tp, 0x8062, 0x2417);
8057 		sram_write(tp, 0x8068, 0x2417);
8058 		sram_write(tp, 0x806e, 0x2417);
8059 		sram_write(tp, 0x8074, 0x2417);
8060 		sram_write(tp, 0x807a, 0x2417);
8061 
8062 		/* XG PLL */
8063 		data = ocp_reg_read(tp, 0xbf84);
8064 		data &= ~0xe000;
8065 		data |= 0xa000;
8066 		ocp_reg_write(tp, 0xbf84, data);
8067 		break;
8068 	default:
8069 		break;
8070 	}
8071 
8072 	/* Notify the MAC when the speed is changed to force mode. */
8073 	data = ocp_reg_read(tp, OCP_INTR_EN);
8074 	data |= INTR_SPEED_FORCE;
8075 	ocp_reg_write(tp, OCP_INTR_EN, data);
8076 
8077 	if (rtl_phy_patch_request(tp, true, true))
8078 		return;
8079 
8080 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
8081 	ocp_data |= EEE_SPDWN_EN;
8082 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
8083 
8084 	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
8085 	data &= ~(EN_EEE_100 | EN_EEE_1000);
8086 	data |= EN_10M_CLKDIV;
8087 	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
8088 	tp->ups_info._10m_ckdiv = true;
8089 	tp->ups_info.eee_plloff_100 = false;
8090 	tp->ups_info.eee_plloff_giga = false;
8091 
8092 	data = ocp_reg_read(tp, OCP_POWER_CFG);
8093 	data &= ~EEE_CLKDIV_EN;
8094 	ocp_reg_write(tp, OCP_POWER_CFG, data);
8095 	tp->ups_info.eee_ckdiv = false;
8096 
8097 	rtl_phy_patch_request(tp, false, true);
8098 
8099 	rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
8100 
8101 	data = ocp_reg_read(tp, 0xa428);
8102 	data &= ~BIT(9);
8103 	ocp_reg_write(tp, 0xa428, data);
8104 	data = ocp_reg_read(tp, 0xa5ea);
8105 	data &= ~BIT(0);
8106 	ocp_reg_write(tp, 0xa5ea, data);
8107 	tp->ups_info.lite_mode = 0;
8108 
8109 	if (tp->eee_en)
8110 		rtl_eee_enable(tp, true);
8111 
8112 	r8153_aldps_en(tp, true);
8113 	r8152b_enable_fc(tp);
8114 	r8153_u2p3en(tp, true);
8115 
8116 	set_bit(PHY_RESET, &tp->flags);
8117 }
8118 
8119 static void r8156_init(struct r8152 *tp)
8120 {
8121 	u32 ocp_data;
8122 	u16 data;
8123 	int i;
8124 
8125 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8126 		return;
8127 
8128 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8129 	ocp_data &= ~EN_ALL_SPEED;
8130 	ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
8131 
8132 	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
8133 
8134 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8135 	ocp_data |= BYPASS_MAC_RESET;
8136 	ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
8137 
8138 	r8153b_u1u2en(tp, false);
8139 
8140 	for (i = 0; i < 500; i++) {
8141 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8142 		    AUTOLOAD_DONE)
8143 			break;
8144 
8145 		msleep(20);
8146 		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8147 			return;
8148 	}
8149 
8150 	data = r8153_phy_status(tp, 0);
8151 	if (data == PHY_STAT_EXT_INIT) {
8152 		data = ocp_reg_read(tp, 0xa468);
8153 		data &= ~(BIT(3) | BIT(1));
8154 		ocp_reg_write(tp, 0xa468, data);
8155 	}
8156 
8157 	data = r8152_mdio_read(tp, MII_BMCR);
8158 	if (data & BMCR_PDOWN) {
8159 		data &= ~BMCR_PDOWN;
8160 		r8152_mdio_write(tp, MII_BMCR, data);
8161 	}
8162 
8163 	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8164 	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
8165 
8166 	r8153_u2p3en(tp, false);
8167 
8168 	/* MSC timer = 0xfff * 8ms = 32760 ms */
8169 	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
8170 
8171 	/* U1/U2/L1 idle timer. 500 us */
8172 	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
8173 
8174 	r8153b_power_cut_en(tp, false);
8175 	r8156_ups_en(tp, false);
8176 	r8153_queue_wake(tp, false);
8177 	rtl_runtime_suspend_enable(tp, false);
8178 
8179 	if (tp->udev->speed >= USB_SPEED_SUPER)
8180 		r8153b_u1u2en(tp, true);
8181 
8182 	usb_enable_lpm(tp->udev);
8183 
8184 	r8156_mac_clk_spd(tp, true);
8185 
8186 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8187 	ocp_data &= ~PLA_MCU_SPDWN_EN;
8188 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
8189 
8190 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8191 	if (rtl8152_get_speed(tp) & LINK_STATUS)
8192 		ocp_data |= CUR_LINK_OK;
8193 	else
8194 		ocp_data &= ~CUR_LINK_OK;
8195 	ocp_data |= POLL_LINK_CHG;
8196 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8197 
8198 	set_bit(GREEN_ETHERNET, &tp->flags);
8199 
8200 	/* rx aggregation */
8201 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8202 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8203 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8204 
8205 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
8206 	ocp_data |= ACT_ODMA;
8207 	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
8208 
8209 	r8156_mdio_force_mode(tp);
8210 	rtl_tally_reset(tp);
8211 
8212 	tp->coalesce = 15000;	/* 15 us */
8213 }
8214 
8215 static void r8156b_init(struct r8152 *tp)
8216 {
8217 	u32 ocp_data;
8218 	u16 data;
8219 	int i;
8220 
8221 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8222 		return;
8223 
8224 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8225 	ocp_data &= ~EN_ALL_SPEED;
8226 	ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
8227 
8228 	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
8229 
8230 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8231 	ocp_data |= BYPASS_MAC_RESET;
8232 	ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
8233 
8234 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
8235 	ocp_data |= RX_DETECT8;
8236 	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
8237 
8238 	r8153b_u1u2en(tp, false);
8239 
8240 	switch (tp->version) {
8241 	case RTL_VER_13:
8242 	case RTL_VER_15:
8243 		r8156b_wait_loading_flash(tp);
8244 		break;
8245 	default:
8246 		break;
8247 	}
8248 
8249 	for (i = 0; i < 500; i++) {
8250 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8251 		    AUTOLOAD_DONE)
8252 			break;
8253 
8254 		msleep(20);
8255 		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8256 			return;
8257 	}
8258 
8259 	data = r8153_phy_status(tp, 0);
8260 	if (data == PHY_STAT_EXT_INIT) {
8261 		data = ocp_reg_read(tp, 0xa468);
8262 		data &= ~(BIT(3) | BIT(1));
8263 		ocp_reg_write(tp, 0xa468, data);
8264 
8265 		data = ocp_reg_read(tp, 0xa466);
8266 		data &= ~BIT(0);
8267 		ocp_reg_write(tp, 0xa466, data);
8268 	}
8269 
8270 	data = r8152_mdio_read(tp, MII_BMCR);
8271 	if (data & BMCR_PDOWN) {
8272 		data &= ~BMCR_PDOWN;
8273 		r8152_mdio_write(tp, MII_BMCR, data);
8274 	}
8275 
8276 	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8277 
8278 	r8153_u2p3en(tp, false);
8279 
8280 	/* MSC timer = 0xfff * 8ms = 32760 ms */
8281 	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
8282 
8283 	/* U1/U2/L1 idle timer. 500 us */
8284 	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
8285 
8286 	r8153b_power_cut_en(tp, false);
8287 	r8156_ups_en(tp, false);
8288 	r8153_queue_wake(tp, false);
8289 	rtl_runtime_suspend_enable(tp, false);
8290 
8291 	if (tp->udev->speed >= USB_SPEED_SUPER)
8292 		r8153b_u1u2en(tp, true);
8293 
8294 	usb_enable_lpm(tp->udev);
8295 
8296 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);
8297 	ocp_data &= ~SLOT_EN;
8298 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8299 
8300 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
8301 	ocp_data |= FLOW_CTRL_EN;
8302 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
8303 
8304 	/* enable fc timer and set timer to 600 ms. */
8305 	ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
8306 		       CTRL_TIMER_EN | (600 / 8));
8307 
8308 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
8309 	if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))
8310 		ocp_data |= FLOW_CTRL_PATCH_2;
8311 	ocp_data &= ~AUTO_SPEEDUP;
8312 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
8313 
8314 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
8315 	ocp_data |= FC_PATCH_TASK;
8316 	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
8317 
8318 	r8156_mac_clk_spd(tp, true);
8319 
8320 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8321 	ocp_data &= ~PLA_MCU_SPDWN_EN;
8322 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
8323 
8324 	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8325 	if (rtl8152_get_speed(tp) & LINK_STATUS)
8326 		ocp_data |= CUR_LINK_OK;
8327 	else
8328 		ocp_data &= ~CUR_LINK_OK;
8329 	ocp_data |= POLL_LINK_CHG;
8330 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8331 
8332 	set_bit(GREEN_ETHERNET, &tp->flags);
8333 
8334 	/* rx aggregation */
8335 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8336 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8337 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8338 
8339 	r8156_mdio_force_mode(tp);
8340 	rtl_tally_reset(tp);
8341 
8342 	tp->coalesce = 15000;	/* 15 us */
8343 }
8344 
8345 static bool rtl_check_vendor_ok(struct usb_interface *intf)
8346 {
8347 	struct usb_host_interface *alt = intf->cur_altsetting;
8348 	struct usb_endpoint_descriptor *in, *out, *intr;
8349 
8350 	if (usb_find_common_endpoints(alt, &in, &out, &intr, NULL) < 0) {
8351 		dev_err(&intf->dev, "Expected endpoints are not found\n");
8352 		return false;
8353 	}
8354 
8355 	/* Check Rx endpoint address */
8356 	if (usb_endpoint_num(in) != 1) {
8357 		dev_err(&intf->dev, "Invalid Rx endpoint address\n");
8358 		return false;
8359 	}
8360 
8361 	/* Check Tx endpoint address */
8362 	if (usb_endpoint_num(out) != 2) {
8363 		dev_err(&intf->dev, "Invalid Tx endpoint address\n");
8364 		return false;
8365 	}
8366 
8367 	/* Check interrupt endpoint address */
8368 	if (usb_endpoint_num(intr) != 3) {
8369 		dev_err(&intf->dev, "Invalid interrupt endpoint address\n");
8370 		return false;
8371 	}
8372 
8373 	return true;
8374 }
8375 
8376 static int rtl8152_pre_reset(struct usb_interface *intf)
8377 {
8378 	struct r8152 *tp = usb_get_intfdata(intf);
8379 	struct net_device *netdev;
8380 
8381 	rtnl_lock();
8382 
8383 	if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags))
8384 		return 0;
8385 
8386 	netdev = tp->netdev;
8387 	if (!netif_running(netdev))
8388 		return 0;
8389 
8390 	netif_stop_queue(netdev);
8391 	tasklet_disable(&tp->tx_tl);
8392 	clear_bit(WORK_ENABLE, &tp->flags);
8393 	usb_kill_urb(tp->intr_urb);
8394 	cancel_delayed_work_sync(&tp->schedule);
8395 	napi_disable(&tp->napi);
8396 	if (netif_carrier_ok(netdev)) {
8397 		mutex_lock(&tp->control);
8398 		set_bit(IN_PRE_RESET, &tp->flags);
8399 		tp->rtl_ops.disable(tp);
8400 		clear_bit(IN_PRE_RESET, &tp->flags);
8401 		mutex_unlock(&tp->control);
8402 	}
8403 
8404 	return 0;
8405 }
8406 
8407 static int rtl8152_post_reset(struct usb_interface *intf)
8408 {
8409 	struct r8152 *tp = usb_get_intfdata(intf);
8410 	struct net_device *netdev;
8411 	struct sockaddr sa;
8412 
8413 	if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags))
8414 		goto exit;
8415 
8416 	rtl_set_accessible(tp);
8417 
8418 	/* reset the MAC address in case of policy change */
8419 	if (determine_ethernet_addr(tp, &sa) >= 0)
8420 		dev_set_mac_address (tp->netdev, &sa, NULL);
8421 
8422 	netdev = tp->netdev;
8423 	if (!netif_running(netdev))
8424 		goto exit;
8425 
8426 	set_bit(WORK_ENABLE, &tp->flags);
8427 	if (netif_carrier_ok(netdev)) {
8428 		mutex_lock(&tp->control);
8429 		tp->rtl_ops.enable(tp);
8430 		rtl_start_rx(tp);
8431 		_rtl8152_set_rx_mode(netdev);
8432 		mutex_unlock(&tp->control);
8433 	}
8434 
8435 	napi_enable(&tp->napi);
8436 	tasklet_enable(&tp->tx_tl);
8437 	netif_wake_queue(netdev);
8438 	usb_submit_urb(tp->intr_urb, GFP_KERNEL);
8439 
8440 	if (!list_empty(&tp->rx_done))
8441 		napi_schedule(&tp->napi);
8442 
8443 exit:
8444 	rtnl_unlock();
8445 	return 0;
8446 }
8447 
8448 static bool delay_autosuspend(struct r8152 *tp)
8449 {
8450 	bool sw_linking = !!netif_carrier_ok(tp->netdev);
8451 	bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
8452 
8453 	/* This means a linking change occurs and the driver doesn't detect it,
8454 	 * yet. If the driver has disabled tx/rx and hw is linking on, the
8455 	 * device wouldn't wake up by receiving any packet.
8456 	 */
8457 	if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
8458 		return true;
8459 
8460 	/* If the linking down is occurred by nway, the device may miss the
8461 	 * linking change event. And it wouldn't wake when linking on.
8462 	 */
8463 	if (!sw_linking && tp->rtl_ops.in_nway(tp))
8464 		return true;
8465 	else if (!skb_queue_empty(&tp->tx_queue))
8466 		return true;
8467 	else
8468 		return false;
8469 }
8470 
8471 static int rtl8152_runtime_resume(struct r8152 *tp)
8472 {
8473 	struct net_device *netdev = tp->netdev;
8474 
8475 	if (netif_running(netdev) && netdev->flags & IFF_UP) {
8476 		struct napi_struct *napi = &tp->napi;
8477 
8478 		tp->rtl_ops.autosuspend_en(tp, false);
8479 		napi_disable(napi);
8480 		set_bit(WORK_ENABLE, &tp->flags);
8481 
8482 		if (netif_carrier_ok(netdev)) {
8483 			if (rtl8152_get_speed(tp) & LINK_STATUS) {
8484 				rtl_start_rx(tp);
8485 			} else {
8486 				netif_carrier_off(netdev);
8487 				tp->rtl_ops.disable(tp);
8488 				netif_info(tp, link, netdev, "linking down\n");
8489 			}
8490 		}
8491 
8492 		napi_enable(napi);
8493 		clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8494 		smp_mb__after_atomic();
8495 
8496 		if (!list_empty(&tp->rx_done))
8497 			napi_schedule(&tp->napi);
8498 
8499 		usb_submit_urb(tp->intr_urb, GFP_NOIO);
8500 	} else {
8501 		if (netdev->flags & IFF_UP)
8502 			tp->rtl_ops.autosuspend_en(tp, false);
8503 
8504 		clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8505 	}
8506 
8507 	return 0;
8508 }
8509 
8510 static int rtl8152_system_resume(struct r8152 *tp)
8511 {
8512 	struct net_device *netdev = tp->netdev;
8513 
8514 	netif_device_attach(netdev);
8515 
8516 	if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
8517 		tp->rtl_ops.up(tp);
8518 		netif_carrier_off(netdev);
8519 		set_bit(WORK_ENABLE, &tp->flags);
8520 		usb_submit_urb(tp->intr_urb, GFP_NOIO);
8521 	}
8522 
8523 	return 0;
8524 }
8525 
8526 static int rtl8152_runtime_suspend(struct r8152 *tp)
8527 {
8528 	struct net_device *netdev = tp->netdev;
8529 	int ret = 0;
8530 
8531 	if (!tp->rtl_ops.autosuspend_en)
8532 		return -EBUSY;
8533 
8534 	set_bit(SELECTIVE_SUSPEND, &tp->flags);
8535 	smp_mb__after_atomic();
8536 
8537 	if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8538 		u32 rcr = 0;
8539 
8540 		if (netif_carrier_ok(netdev)) {
8541 			u32 ocp_data;
8542 
8543 			rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
8544 			ocp_data = rcr & ~RCR_ACPT_ALL;
8545 			ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8546 			rxdy_gated_en(tp, true);
8547 			ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
8548 						 PLA_OOB_CTRL);
8549 			if (!(ocp_data & RXFIFO_EMPTY)) {
8550 				rxdy_gated_en(tp, false);
8551 				ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8552 				clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8553 				smp_mb__after_atomic();
8554 				ret = -EBUSY;
8555 				goto out1;
8556 			}
8557 		}
8558 
8559 		clear_bit(WORK_ENABLE, &tp->flags);
8560 		usb_kill_urb(tp->intr_urb);
8561 
8562 		tp->rtl_ops.autosuspend_en(tp, true);
8563 
8564 		if (netif_carrier_ok(netdev)) {
8565 			struct napi_struct *napi = &tp->napi;
8566 
8567 			napi_disable(napi);
8568 			rtl_stop_rx(tp);
8569 			rxdy_gated_en(tp, false);
8570 			ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8571 			napi_enable(napi);
8572 		}
8573 
8574 		if (delay_autosuspend(tp)) {
8575 			rtl8152_runtime_resume(tp);
8576 			ret = -EBUSY;
8577 		}
8578 	}
8579 
8580 out1:
8581 	return ret;
8582 }
8583 
8584 static int rtl8152_system_suspend(struct r8152 *tp)
8585 {
8586 	struct net_device *netdev = tp->netdev;
8587 
8588 	netif_device_detach(netdev);
8589 
8590 	if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8591 		struct napi_struct *napi = &tp->napi;
8592 
8593 		clear_bit(WORK_ENABLE, &tp->flags);
8594 		usb_kill_urb(tp->intr_urb);
8595 		tasklet_disable(&tp->tx_tl);
8596 		napi_disable(napi);
8597 		cancel_delayed_work_sync(&tp->schedule);
8598 		tp->rtl_ops.down(tp);
8599 		napi_enable(napi);
8600 		tasklet_enable(&tp->tx_tl);
8601 	}
8602 
8603 	return 0;
8604 }
8605 
8606 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
8607 {
8608 	struct r8152 *tp = usb_get_intfdata(intf);
8609 	int ret;
8610 
8611 	mutex_lock(&tp->control);
8612 
8613 	if (PMSG_IS_AUTO(message))
8614 		ret = rtl8152_runtime_suspend(tp);
8615 	else
8616 		ret = rtl8152_system_suspend(tp);
8617 
8618 	mutex_unlock(&tp->control);
8619 
8620 	return ret;
8621 }
8622 
8623 static int rtl8152_resume(struct usb_interface *intf)
8624 {
8625 	struct r8152 *tp = usb_get_intfdata(intf);
8626 	int ret;
8627 
8628 	mutex_lock(&tp->control);
8629 
8630 	rtl_reset_ocp_base(tp);
8631 
8632 	if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
8633 		ret = rtl8152_runtime_resume(tp);
8634 	else
8635 		ret = rtl8152_system_resume(tp);
8636 
8637 	mutex_unlock(&tp->control);
8638 
8639 	return ret;
8640 }
8641 
8642 static int rtl8152_reset_resume(struct usb_interface *intf)
8643 {
8644 	struct r8152 *tp = usb_get_intfdata(intf);
8645 
8646 	clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8647 	rtl_reset_ocp_base(tp);
8648 	tp->rtl_ops.init(tp);
8649 	queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
8650 	set_ethernet_addr(tp, true);
8651 	return rtl8152_resume(intf);
8652 }
8653 
8654 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8655 {
8656 	struct r8152 *tp = netdev_priv(dev);
8657 
8658 	if (usb_autopm_get_interface(tp->intf) < 0)
8659 		return;
8660 
8661 	if (!rtl_can_wakeup(tp)) {
8662 		wol->supported = 0;
8663 		wol->wolopts = 0;
8664 	} else {
8665 		mutex_lock(&tp->control);
8666 		wol->supported = WAKE_ANY;
8667 		wol->wolopts = __rtl_get_wol(tp);
8668 		mutex_unlock(&tp->control);
8669 	}
8670 
8671 	usb_autopm_put_interface(tp->intf);
8672 }
8673 
8674 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8675 {
8676 	struct r8152 *tp = netdev_priv(dev);
8677 	int ret;
8678 
8679 	if (!rtl_can_wakeup(tp))
8680 		return -EOPNOTSUPP;
8681 
8682 	if (wol->wolopts & ~WAKE_ANY)
8683 		return -EINVAL;
8684 
8685 	ret = usb_autopm_get_interface(tp->intf);
8686 	if (ret < 0)
8687 		goto out_set_wol;
8688 
8689 	mutex_lock(&tp->control);
8690 
8691 	__rtl_set_wol(tp, wol->wolopts);
8692 	tp->saved_wolopts = wol->wolopts & WAKE_ANY;
8693 
8694 	mutex_unlock(&tp->control);
8695 
8696 	usb_autopm_put_interface(tp->intf);
8697 
8698 out_set_wol:
8699 	return ret;
8700 }
8701 
8702 static u32 rtl8152_get_msglevel(struct net_device *dev)
8703 {
8704 	struct r8152 *tp = netdev_priv(dev);
8705 
8706 	return tp->msg_enable;
8707 }
8708 
8709 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
8710 {
8711 	struct r8152 *tp = netdev_priv(dev);
8712 
8713 	tp->msg_enable = value;
8714 }
8715 
8716 static void rtl8152_get_drvinfo(struct net_device *netdev,
8717 				struct ethtool_drvinfo *info)
8718 {
8719 	struct r8152 *tp = netdev_priv(netdev);
8720 
8721 	strscpy(info->driver, MODULENAME, sizeof(info->driver));
8722 	strscpy(info->version, DRIVER_VERSION, sizeof(info->version));
8723 	usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
8724 	if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
8725 		strscpy(info->fw_version, tp->rtl_fw.version,
8726 			sizeof(info->fw_version));
8727 }
8728 
8729 static
8730 int rtl8152_get_link_ksettings(struct net_device *netdev,
8731 			       struct ethtool_link_ksettings *cmd)
8732 {
8733 	struct r8152 *tp = netdev_priv(netdev);
8734 	int ret;
8735 
8736 	if (!tp->mii.mdio_read)
8737 		return -EOPNOTSUPP;
8738 
8739 	ret = usb_autopm_get_interface(tp->intf);
8740 	if (ret < 0)
8741 		goto out;
8742 
8743 	mutex_lock(&tp->control);
8744 
8745 	mii_ethtool_get_link_ksettings(&tp->mii, cmd);
8746 
8747 	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8748 			 cmd->link_modes.supported, tp->support_2500full);
8749 
8750 	if (tp->support_2500full) {
8751 		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8752 				 cmd->link_modes.advertising,
8753 				 ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);
8754 
8755 		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8756 				 cmd->link_modes.lp_advertising,
8757 				 ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);
8758 
8759 		if (is_speed_2500(rtl8152_get_speed(tp)))
8760 			cmd->base.speed = SPEED_2500;
8761 	}
8762 
8763 	mutex_unlock(&tp->control);
8764 
8765 	usb_autopm_put_interface(tp->intf);
8766 
8767 out:
8768 	return ret;
8769 }
8770 
8771 static int rtl8152_set_link_ksettings(struct net_device *dev,
8772 				      const struct ethtool_link_ksettings *cmd)
8773 {
8774 	struct r8152 *tp = netdev_priv(dev);
8775 	u32 advertising = 0;
8776 	int ret;
8777 
8778 	ret = usb_autopm_get_interface(tp->intf);
8779 	if (ret < 0)
8780 		goto out;
8781 
8782 	if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
8783 		     cmd->link_modes.advertising))
8784 		advertising |= RTL_ADVERTISED_10_HALF;
8785 
8786 	if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
8787 		     cmd->link_modes.advertising))
8788 		advertising |= RTL_ADVERTISED_10_FULL;
8789 
8790 	if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
8791 		     cmd->link_modes.advertising))
8792 		advertising |= RTL_ADVERTISED_100_HALF;
8793 
8794 	if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
8795 		     cmd->link_modes.advertising))
8796 		advertising |= RTL_ADVERTISED_100_FULL;
8797 
8798 	if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
8799 		     cmd->link_modes.advertising))
8800 		advertising |= RTL_ADVERTISED_1000_HALF;
8801 
8802 	if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
8803 		     cmd->link_modes.advertising))
8804 		advertising |= RTL_ADVERTISED_1000_FULL;
8805 
8806 	if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8807 		     cmd->link_modes.advertising))
8808 		advertising |= RTL_ADVERTISED_2500_FULL;
8809 
8810 	mutex_lock(&tp->control);
8811 
8812 	ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
8813 				cmd->base.duplex, advertising);
8814 	if (!ret) {
8815 		tp->autoneg = cmd->base.autoneg;
8816 		tp->speed = cmd->base.speed;
8817 		tp->duplex = cmd->base.duplex;
8818 		tp->advertising = advertising;
8819 	}
8820 
8821 	mutex_unlock(&tp->control);
8822 
8823 	usb_autopm_put_interface(tp->intf);
8824 
8825 out:
8826 	return ret;
8827 }
8828 
8829 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
8830 	"tx_packets",
8831 	"rx_packets",
8832 	"tx_errors",
8833 	"rx_errors",
8834 	"rx_missed",
8835 	"align_errors",
8836 	"tx_single_collisions",
8837 	"tx_multi_collisions",
8838 	"rx_unicast",
8839 	"rx_broadcast",
8840 	"rx_multicast",
8841 	"tx_aborted",
8842 	"tx_underrun",
8843 };
8844 
8845 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
8846 {
8847 	switch (sset) {
8848 	case ETH_SS_STATS:
8849 		return ARRAY_SIZE(rtl8152_gstrings);
8850 	default:
8851 		return -EOPNOTSUPP;
8852 	}
8853 }
8854 
8855 static void rtl8152_get_ethtool_stats(struct net_device *dev,
8856 				      struct ethtool_stats *stats, u64 *data)
8857 {
8858 	struct r8152 *tp = netdev_priv(dev);
8859 	struct tally_counter tally;
8860 
8861 	if (usb_autopm_get_interface(tp->intf) < 0)
8862 		return;
8863 
8864 	generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
8865 
8866 	usb_autopm_put_interface(tp->intf);
8867 
8868 	data[0] = le64_to_cpu(tally.tx_packets);
8869 	data[1] = le64_to_cpu(tally.rx_packets);
8870 	data[2] = le64_to_cpu(tally.tx_errors);
8871 	data[3] = le32_to_cpu(tally.rx_errors);
8872 	data[4] = le16_to_cpu(tally.rx_missed);
8873 	data[5] = le16_to_cpu(tally.align_errors);
8874 	data[6] = le32_to_cpu(tally.tx_one_collision);
8875 	data[7] = le32_to_cpu(tally.tx_multi_collision);
8876 	data[8] = le64_to_cpu(tally.rx_unicast);
8877 	data[9] = le64_to_cpu(tally.rx_broadcast);
8878 	data[10] = le32_to_cpu(tally.rx_multicast);
8879 	data[11] = le16_to_cpu(tally.tx_aborted);
8880 	data[12] = le16_to_cpu(tally.tx_underrun);
8881 }
8882 
8883 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
8884 {
8885 	switch (stringset) {
8886 	case ETH_SS_STATS:
8887 		memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
8888 		break;
8889 	}
8890 }
8891 
8892 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8893 {
8894 	u32 lp, adv, supported = 0;
8895 	u16 val;
8896 
8897 	val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
8898 	supported = mmd_eee_cap_to_ethtool_sup_t(val);
8899 
8900 	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
8901 	adv = mmd_eee_adv_to_ethtool_adv_t(val);
8902 
8903 	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
8904 	lp = mmd_eee_adv_to_ethtool_adv_t(val);
8905 
8906 	eee->eee_enabled = tp->eee_en;
8907 	eee->eee_active = !!(supported & adv & lp);
8908 	eee->supported = supported;
8909 	eee->advertised = tp->eee_adv;
8910 	eee->lp_advertised = lp;
8911 
8912 	return 0;
8913 }
8914 
8915 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
8916 {
8917 	u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
8918 
8919 	tp->eee_en = eee->eee_enabled;
8920 	tp->eee_adv = val;
8921 
8922 	rtl_eee_enable(tp, tp->eee_en);
8923 
8924 	return 0;
8925 }
8926 
8927 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8928 {
8929 	u32 lp, adv, supported = 0;
8930 	u16 val;
8931 
8932 	val = ocp_reg_read(tp, OCP_EEE_ABLE);
8933 	supported = mmd_eee_cap_to_ethtool_sup_t(val);
8934 
8935 	val = ocp_reg_read(tp, OCP_EEE_ADV);
8936 	adv = mmd_eee_adv_to_ethtool_adv_t(val);
8937 
8938 	val = ocp_reg_read(tp, OCP_EEE_LPABLE);
8939 	lp = mmd_eee_adv_to_ethtool_adv_t(val);
8940 
8941 	eee->eee_enabled = tp->eee_en;
8942 	eee->eee_active = !!(supported & adv & lp);
8943 	eee->supported = supported;
8944 	eee->advertised = tp->eee_adv;
8945 	eee->lp_advertised = lp;
8946 
8947 	return 0;
8948 }
8949 
8950 static int
8951 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
8952 {
8953 	struct r8152 *tp = netdev_priv(net);
8954 	int ret;
8955 
8956 	if (!tp->rtl_ops.eee_get) {
8957 		ret = -EOPNOTSUPP;
8958 		goto out;
8959 	}
8960 
8961 	ret = usb_autopm_get_interface(tp->intf);
8962 	if (ret < 0)
8963 		goto out;
8964 
8965 	mutex_lock(&tp->control);
8966 
8967 	ret = tp->rtl_ops.eee_get(tp, edata);
8968 
8969 	mutex_unlock(&tp->control);
8970 
8971 	usb_autopm_put_interface(tp->intf);
8972 
8973 out:
8974 	return ret;
8975 }
8976 
8977 static int
8978 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
8979 {
8980 	struct r8152 *tp = netdev_priv(net);
8981 	int ret;
8982 
8983 	if (!tp->rtl_ops.eee_set) {
8984 		ret = -EOPNOTSUPP;
8985 		goto out;
8986 	}
8987 
8988 	ret = usb_autopm_get_interface(tp->intf);
8989 	if (ret < 0)
8990 		goto out;
8991 
8992 	mutex_lock(&tp->control);
8993 
8994 	ret = tp->rtl_ops.eee_set(tp, edata);
8995 	if (!ret)
8996 		ret = mii_nway_restart(&tp->mii);
8997 
8998 	mutex_unlock(&tp->control);
8999 
9000 	usb_autopm_put_interface(tp->intf);
9001 
9002 out:
9003 	return ret;
9004 }
9005 
9006 static int rtl8152_nway_reset(struct net_device *dev)
9007 {
9008 	struct r8152 *tp = netdev_priv(dev);
9009 	int ret;
9010 
9011 	ret = usb_autopm_get_interface(tp->intf);
9012 	if (ret < 0)
9013 		goto out;
9014 
9015 	mutex_lock(&tp->control);
9016 
9017 	ret = mii_nway_restart(&tp->mii);
9018 
9019 	mutex_unlock(&tp->control);
9020 
9021 	usb_autopm_put_interface(tp->intf);
9022 
9023 out:
9024 	return ret;
9025 }
9026 
9027 static int rtl8152_get_coalesce(struct net_device *netdev,
9028 				struct ethtool_coalesce *coalesce,
9029 				struct kernel_ethtool_coalesce *kernel_coal,
9030 				struct netlink_ext_ack *extack)
9031 {
9032 	struct r8152 *tp = netdev_priv(netdev);
9033 
9034 	switch (tp->version) {
9035 	case RTL_VER_01:
9036 	case RTL_VER_02:
9037 	case RTL_VER_07:
9038 		return -EOPNOTSUPP;
9039 	default:
9040 		break;
9041 	}
9042 
9043 	coalesce->rx_coalesce_usecs = tp->coalesce;
9044 
9045 	return 0;
9046 }
9047 
9048 static int rtl8152_set_coalesce(struct net_device *netdev,
9049 				struct ethtool_coalesce *coalesce,
9050 				struct kernel_ethtool_coalesce *kernel_coal,
9051 				struct netlink_ext_ack *extack)
9052 {
9053 	struct r8152 *tp = netdev_priv(netdev);
9054 	int ret;
9055 
9056 	switch (tp->version) {
9057 	case RTL_VER_01:
9058 	case RTL_VER_02:
9059 	case RTL_VER_07:
9060 		return -EOPNOTSUPP;
9061 	default:
9062 		break;
9063 	}
9064 
9065 	if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
9066 		return -EINVAL;
9067 
9068 	ret = usb_autopm_get_interface(tp->intf);
9069 	if (ret < 0)
9070 		return ret;
9071 
9072 	mutex_lock(&tp->control);
9073 
9074 	if (tp->coalesce != coalesce->rx_coalesce_usecs) {
9075 		tp->coalesce = coalesce->rx_coalesce_usecs;
9076 
9077 		if (netif_running(netdev) && netif_carrier_ok(netdev)) {
9078 			netif_stop_queue(netdev);
9079 			napi_disable(&tp->napi);
9080 			tp->rtl_ops.disable(tp);
9081 			tp->rtl_ops.enable(tp);
9082 			rtl_start_rx(tp);
9083 			clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
9084 			_rtl8152_set_rx_mode(netdev);
9085 			napi_enable(&tp->napi);
9086 			netif_wake_queue(netdev);
9087 		}
9088 	}
9089 
9090 	mutex_unlock(&tp->control);
9091 
9092 	usb_autopm_put_interface(tp->intf);
9093 
9094 	return ret;
9095 }
9096 
9097 static int rtl8152_get_tunable(struct net_device *netdev,
9098 			       const struct ethtool_tunable *tunable, void *d)
9099 {
9100 	struct r8152 *tp = netdev_priv(netdev);
9101 
9102 	switch (tunable->id) {
9103 	case ETHTOOL_RX_COPYBREAK:
9104 		*(u32 *)d = tp->rx_copybreak;
9105 		break;
9106 	default:
9107 		return -EOPNOTSUPP;
9108 	}
9109 
9110 	return 0;
9111 }
9112 
9113 static int rtl8152_set_tunable(struct net_device *netdev,
9114 			       const struct ethtool_tunable *tunable,
9115 			       const void *d)
9116 {
9117 	struct r8152 *tp = netdev_priv(netdev);
9118 	u32 val;
9119 
9120 	switch (tunable->id) {
9121 	case ETHTOOL_RX_COPYBREAK:
9122 		val = *(u32 *)d;
9123 		if (val < ETH_ZLEN) {
9124 			netif_err(tp, rx_err, netdev,
9125 				  "Invalid rx copy break value\n");
9126 			return -EINVAL;
9127 		}
9128 
9129 		if (tp->rx_copybreak != val) {
9130 			if (netdev->flags & IFF_UP) {
9131 				mutex_lock(&tp->control);
9132 				napi_disable(&tp->napi);
9133 				tp->rx_copybreak = val;
9134 				napi_enable(&tp->napi);
9135 				mutex_unlock(&tp->control);
9136 			} else {
9137 				tp->rx_copybreak = val;
9138 			}
9139 		}
9140 		break;
9141 	default:
9142 		return -EOPNOTSUPP;
9143 	}
9144 
9145 	return 0;
9146 }
9147 
9148 static void rtl8152_get_ringparam(struct net_device *netdev,
9149 				  struct ethtool_ringparam *ring,
9150 				  struct kernel_ethtool_ringparam *kernel_ring,
9151 				  struct netlink_ext_ack *extack)
9152 {
9153 	struct r8152 *tp = netdev_priv(netdev);
9154 
9155 	ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
9156 	ring->rx_pending = tp->rx_pending;
9157 }
9158 
9159 static int rtl8152_set_ringparam(struct net_device *netdev,
9160 				 struct ethtool_ringparam *ring,
9161 				 struct kernel_ethtool_ringparam *kernel_ring,
9162 				 struct netlink_ext_ack *extack)
9163 {
9164 	struct r8152 *tp = netdev_priv(netdev);
9165 
9166 	if (ring->rx_pending < (RTL8152_MAX_RX * 2))
9167 		return -EINVAL;
9168 
9169 	if (tp->rx_pending != ring->rx_pending) {
9170 		if (netdev->flags & IFF_UP) {
9171 			mutex_lock(&tp->control);
9172 			napi_disable(&tp->napi);
9173 			tp->rx_pending = ring->rx_pending;
9174 			napi_enable(&tp->napi);
9175 			mutex_unlock(&tp->control);
9176 		} else {
9177 			tp->rx_pending = ring->rx_pending;
9178 		}
9179 	}
9180 
9181 	return 0;
9182 }
9183 
9184 static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9185 {
9186 	struct r8152 *tp = netdev_priv(netdev);
9187 	u16 bmcr, lcladv, rmtadv;
9188 	u8 cap;
9189 
9190 	if (usb_autopm_get_interface(tp->intf) < 0)
9191 		return;
9192 
9193 	mutex_lock(&tp->control);
9194 
9195 	bmcr = r8152_mdio_read(tp, MII_BMCR);
9196 	lcladv = r8152_mdio_read(tp, MII_ADVERTISE);
9197 	rmtadv = r8152_mdio_read(tp, MII_LPA);
9198 
9199 	mutex_unlock(&tp->control);
9200 
9201 	usb_autopm_put_interface(tp->intf);
9202 
9203 	if (!(bmcr & BMCR_ANENABLE)) {
9204 		pause->autoneg = 0;
9205 		pause->rx_pause = 0;
9206 		pause->tx_pause = 0;
9207 		return;
9208 	}
9209 
9210 	pause->autoneg = 1;
9211 
9212 	cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
9213 
9214 	if (cap & FLOW_CTRL_RX)
9215 		pause->rx_pause = 1;
9216 
9217 	if (cap & FLOW_CTRL_TX)
9218 		pause->tx_pause = 1;
9219 }
9220 
9221 static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9222 {
9223 	struct r8152 *tp = netdev_priv(netdev);
9224 	u16 old, new1;
9225 	u8 cap = 0;
9226 	int ret;
9227 
9228 	ret = usb_autopm_get_interface(tp->intf);
9229 	if (ret < 0)
9230 		return ret;
9231 
9232 	mutex_lock(&tp->control);
9233 
9234 	if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) {
9235 		ret = -EINVAL;
9236 		goto out;
9237 	}
9238 
9239 	if (pause->rx_pause)
9240 		cap |= FLOW_CTRL_RX;
9241 
9242 	if (pause->tx_pause)
9243 		cap |= FLOW_CTRL_TX;
9244 
9245 	old = r8152_mdio_read(tp, MII_ADVERTISE);
9246 	new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap);
9247 	if (old != new1)
9248 		r8152_mdio_write(tp, MII_ADVERTISE, new1);
9249 
9250 out:
9251 	mutex_unlock(&tp->control);
9252 	usb_autopm_put_interface(tp->intf);
9253 
9254 	return ret;
9255 }
9256 
9257 static const struct ethtool_ops ops = {
9258 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS,
9259 	.get_drvinfo = rtl8152_get_drvinfo,
9260 	.get_link = ethtool_op_get_link,
9261 	.nway_reset = rtl8152_nway_reset,
9262 	.get_msglevel = rtl8152_get_msglevel,
9263 	.set_msglevel = rtl8152_set_msglevel,
9264 	.get_wol = rtl8152_get_wol,
9265 	.set_wol = rtl8152_set_wol,
9266 	.get_strings = rtl8152_get_strings,
9267 	.get_sset_count = rtl8152_get_sset_count,
9268 	.get_ethtool_stats = rtl8152_get_ethtool_stats,
9269 	.get_coalesce = rtl8152_get_coalesce,
9270 	.set_coalesce = rtl8152_set_coalesce,
9271 	.get_eee = rtl_ethtool_get_eee,
9272 	.set_eee = rtl_ethtool_set_eee,
9273 	.get_link_ksettings = rtl8152_get_link_ksettings,
9274 	.set_link_ksettings = rtl8152_set_link_ksettings,
9275 	.get_tunable = rtl8152_get_tunable,
9276 	.set_tunable = rtl8152_set_tunable,
9277 	.get_ringparam = rtl8152_get_ringparam,
9278 	.set_ringparam = rtl8152_set_ringparam,
9279 	.get_pauseparam = rtl8152_get_pauseparam,
9280 	.set_pauseparam = rtl8152_set_pauseparam,
9281 };
9282 
9283 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
9284 {
9285 	struct r8152 *tp = netdev_priv(netdev);
9286 	struct mii_ioctl_data *data = if_mii(rq);
9287 	int res;
9288 
9289 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9290 		return -ENODEV;
9291 
9292 	res = usb_autopm_get_interface(tp->intf);
9293 	if (res < 0)
9294 		goto out;
9295 
9296 	switch (cmd) {
9297 	case SIOCGMIIPHY:
9298 		data->phy_id = R8152_PHY_ID; /* Internal PHY */
9299 		break;
9300 
9301 	case SIOCGMIIREG:
9302 		mutex_lock(&tp->control);
9303 		data->val_out = r8152_mdio_read(tp, data->reg_num);
9304 		mutex_unlock(&tp->control);
9305 		break;
9306 
9307 	case SIOCSMIIREG:
9308 		if (!capable(CAP_NET_ADMIN)) {
9309 			res = -EPERM;
9310 			break;
9311 		}
9312 		mutex_lock(&tp->control);
9313 		r8152_mdio_write(tp, data->reg_num, data->val_in);
9314 		mutex_unlock(&tp->control);
9315 		break;
9316 
9317 	default:
9318 		res = -EOPNOTSUPP;
9319 	}
9320 
9321 	usb_autopm_put_interface(tp->intf);
9322 
9323 out:
9324 	return res;
9325 }
9326 
9327 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
9328 {
9329 	struct r8152 *tp = netdev_priv(dev);
9330 	int ret;
9331 
9332 	switch (tp->version) {
9333 	case RTL_VER_01:
9334 	case RTL_VER_02:
9335 	case RTL_VER_07:
9336 		dev->mtu = new_mtu;
9337 		return 0;
9338 	default:
9339 		break;
9340 	}
9341 
9342 	ret = usb_autopm_get_interface(tp->intf);
9343 	if (ret < 0)
9344 		return ret;
9345 
9346 	mutex_lock(&tp->control);
9347 
9348 	dev->mtu = new_mtu;
9349 
9350 	if (netif_running(dev)) {
9351 		if (tp->rtl_ops.change_mtu)
9352 			tp->rtl_ops.change_mtu(tp);
9353 
9354 		if (netif_carrier_ok(dev)) {
9355 			netif_stop_queue(dev);
9356 			napi_disable(&tp->napi);
9357 			tasklet_disable(&tp->tx_tl);
9358 			tp->rtl_ops.disable(tp);
9359 			tp->rtl_ops.enable(tp);
9360 			rtl_start_rx(tp);
9361 			tasklet_enable(&tp->tx_tl);
9362 			napi_enable(&tp->napi);
9363 			rtl8152_set_rx_mode(dev);
9364 			netif_wake_queue(dev);
9365 		}
9366 	}
9367 
9368 	mutex_unlock(&tp->control);
9369 
9370 	usb_autopm_put_interface(tp->intf);
9371 
9372 	return ret;
9373 }
9374 
9375 static const struct net_device_ops rtl8152_netdev_ops = {
9376 	.ndo_open		= rtl8152_open,
9377 	.ndo_stop		= rtl8152_close,
9378 	.ndo_eth_ioctl		= rtl8152_ioctl,
9379 	.ndo_start_xmit		= rtl8152_start_xmit,
9380 	.ndo_tx_timeout		= rtl8152_tx_timeout,
9381 	.ndo_set_features	= rtl8152_set_features,
9382 	.ndo_set_rx_mode	= rtl8152_set_rx_mode,
9383 	.ndo_set_mac_address	= rtl8152_set_mac_address,
9384 	.ndo_change_mtu		= rtl8152_change_mtu,
9385 	.ndo_validate_addr	= eth_validate_addr,
9386 	.ndo_features_check	= rtl8152_features_check,
9387 };
9388 
9389 static void rtl8152_unload(struct r8152 *tp)
9390 {
9391 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9392 		return;
9393 
9394 	if (tp->version != RTL_VER_01)
9395 		r8152_power_cut_en(tp, true);
9396 }
9397 
9398 static void rtl8153_unload(struct r8152 *tp)
9399 {
9400 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9401 		return;
9402 
9403 	r8153_power_cut_en(tp, false);
9404 }
9405 
9406 static void rtl8153b_unload(struct r8152 *tp)
9407 {
9408 	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9409 		return;
9410 
9411 	r8153b_power_cut_en(tp, false);
9412 }
9413 
9414 static int rtl_ops_init(struct r8152 *tp)
9415 {
9416 	struct rtl_ops *ops = &tp->rtl_ops;
9417 	int ret = 0;
9418 
9419 	switch (tp->version) {
9420 	case RTL_VER_01:
9421 	case RTL_VER_02:
9422 	case RTL_VER_07:
9423 		ops->init		= r8152b_init;
9424 		ops->enable		= rtl8152_enable;
9425 		ops->disable		= rtl8152_disable;
9426 		ops->up			= rtl8152_up;
9427 		ops->down		= rtl8152_down;
9428 		ops->unload		= rtl8152_unload;
9429 		ops->eee_get		= r8152_get_eee;
9430 		ops->eee_set		= r8152_set_eee;
9431 		ops->in_nway		= rtl8152_in_nway;
9432 		ops->hw_phy_cfg		= r8152b_hw_phy_cfg;
9433 		ops->autosuspend_en	= rtl_runtime_suspend_enable;
9434 		tp->rx_buf_sz		= 16 * 1024;
9435 		tp->eee_en		= true;
9436 		tp->eee_adv		= MDIO_EEE_100TX;
9437 		break;
9438 
9439 	case RTL_VER_03:
9440 	case RTL_VER_04:
9441 	case RTL_VER_05:
9442 	case RTL_VER_06:
9443 		ops->init		= r8153_init;
9444 		ops->enable		= rtl8153_enable;
9445 		ops->disable		= rtl8153_disable;
9446 		ops->up			= rtl8153_up;
9447 		ops->down		= rtl8153_down;
9448 		ops->unload		= rtl8153_unload;
9449 		ops->eee_get		= r8153_get_eee;
9450 		ops->eee_set		= r8152_set_eee;
9451 		ops->in_nway		= rtl8153_in_nway;
9452 		ops->hw_phy_cfg		= r8153_hw_phy_cfg;
9453 		ops->autosuspend_en	= rtl8153_runtime_enable;
9454 		ops->change_mtu		= rtl8153_change_mtu;
9455 		if (tp->udev->speed < USB_SPEED_SUPER)
9456 			tp->rx_buf_sz	= 16 * 1024;
9457 		else
9458 			tp->rx_buf_sz	= 32 * 1024;
9459 		tp->eee_en		= true;
9460 		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
9461 		break;
9462 
9463 	case RTL_VER_08:
9464 	case RTL_VER_09:
9465 		ops->init		= r8153b_init;
9466 		ops->enable		= rtl8153_enable;
9467 		ops->disable		= rtl8153_disable;
9468 		ops->up			= rtl8153b_up;
9469 		ops->down		= rtl8153b_down;
9470 		ops->unload		= rtl8153b_unload;
9471 		ops->eee_get		= r8153_get_eee;
9472 		ops->eee_set		= r8152_set_eee;
9473 		ops->in_nway		= rtl8153_in_nway;
9474 		ops->hw_phy_cfg		= r8153b_hw_phy_cfg;
9475 		ops->autosuspend_en	= rtl8153b_runtime_enable;
9476 		ops->change_mtu		= rtl8153_change_mtu;
9477 		tp->rx_buf_sz		= 32 * 1024;
9478 		tp->eee_en		= true;
9479 		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
9480 		break;
9481 
9482 	case RTL_VER_11:
9483 		tp->eee_en		= true;
9484 		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
9485 		fallthrough;
9486 	case RTL_VER_10:
9487 		ops->init		= r8156_init;
9488 		ops->enable		= rtl8156_enable;
9489 		ops->disable		= rtl8156_disable;
9490 		ops->up			= rtl8156_up;
9491 		ops->down		= rtl8156_down;
9492 		ops->unload		= rtl8153_unload;
9493 		ops->eee_get		= r8153_get_eee;
9494 		ops->eee_set		= r8152_set_eee;
9495 		ops->in_nway		= rtl8153_in_nway;
9496 		ops->hw_phy_cfg		= r8156_hw_phy_cfg;
9497 		ops->autosuspend_en	= rtl8156_runtime_enable;
9498 		ops->change_mtu		= rtl8156_change_mtu;
9499 		tp->rx_buf_sz		= 48 * 1024;
9500 		tp->support_2500full	= 1;
9501 		break;
9502 
9503 	case RTL_VER_12:
9504 	case RTL_VER_13:
9505 		tp->support_2500full	= 1;
9506 		fallthrough;
9507 	case RTL_VER_15:
9508 		tp->eee_en		= true;
9509 		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
9510 		ops->init		= r8156b_init;
9511 		ops->enable		= rtl8156b_enable;
9512 		ops->disable		= rtl8153_disable;
9513 		ops->up			= rtl8156_up;
9514 		ops->down		= rtl8156_down;
9515 		ops->unload		= rtl8153_unload;
9516 		ops->eee_get		= r8153_get_eee;
9517 		ops->eee_set		= r8152_set_eee;
9518 		ops->in_nway		= rtl8153_in_nway;
9519 		ops->hw_phy_cfg		= r8156b_hw_phy_cfg;
9520 		ops->autosuspend_en	= rtl8156_runtime_enable;
9521 		ops->change_mtu		= rtl8156_change_mtu;
9522 		tp->rx_buf_sz		= 48 * 1024;
9523 		break;
9524 
9525 	case RTL_VER_14:
9526 		ops->init		= r8153c_init;
9527 		ops->enable		= rtl8153_enable;
9528 		ops->disable		= rtl8153_disable;
9529 		ops->up			= rtl8153c_up;
9530 		ops->down		= rtl8153b_down;
9531 		ops->unload		= rtl8153_unload;
9532 		ops->eee_get		= r8153_get_eee;
9533 		ops->eee_set		= r8152_set_eee;
9534 		ops->in_nway		= rtl8153_in_nway;
9535 		ops->hw_phy_cfg		= r8153c_hw_phy_cfg;
9536 		ops->autosuspend_en	= rtl8153c_runtime_enable;
9537 		ops->change_mtu		= rtl8153c_change_mtu;
9538 		tp->rx_buf_sz		= 32 * 1024;
9539 		tp->eee_en		= true;
9540 		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
9541 		break;
9542 
9543 	default:
9544 		ret = -ENODEV;
9545 		dev_err(&tp->intf->dev, "Unknown Device\n");
9546 		break;
9547 	}
9548 
9549 	return ret;
9550 }
9551 
9552 #define FIRMWARE_8153A_2	"rtl_nic/rtl8153a-2.fw"
9553 #define FIRMWARE_8153A_3	"rtl_nic/rtl8153a-3.fw"
9554 #define FIRMWARE_8153A_4	"rtl_nic/rtl8153a-4.fw"
9555 #define FIRMWARE_8153B_2	"rtl_nic/rtl8153b-2.fw"
9556 #define FIRMWARE_8153C_1	"rtl_nic/rtl8153c-1.fw"
9557 #define FIRMWARE_8156A_2	"rtl_nic/rtl8156a-2.fw"
9558 #define FIRMWARE_8156B_2	"rtl_nic/rtl8156b-2.fw"
9559 
9560 MODULE_FIRMWARE(FIRMWARE_8153A_2);
9561 MODULE_FIRMWARE(FIRMWARE_8153A_3);
9562 MODULE_FIRMWARE(FIRMWARE_8153A_4);
9563 MODULE_FIRMWARE(FIRMWARE_8153B_2);
9564 MODULE_FIRMWARE(FIRMWARE_8153C_1);
9565 MODULE_FIRMWARE(FIRMWARE_8156A_2);
9566 MODULE_FIRMWARE(FIRMWARE_8156B_2);
9567 
9568 static int rtl_fw_init(struct r8152 *tp)
9569 {
9570 	struct rtl_fw *rtl_fw = &tp->rtl_fw;
9571 
9572 	switch (tp->version) {
9573 	case RTL_VER_04:
9574 		rtl_fw->fw_name		= FIRMWARE_8153A_2;
9575 		rtl_fw->pre_fw		= r8153_pre_firmware_1;
9576 		rtl_fw->post_fw		= r8153_post_firmware_1;
9577 		break;
9578 	case RTL_VER_05:
9579 		rtl_fw->fw_name		= FIRMWARE_8153A_3;
9580 		rtl_fw->pre_fw		= r8153_pre_firmware_2;
9581 		rtl_fw->post_fw		= r8153_post_firmware_2;
9582 		break;
9583 	case RTL_VER_06:
9584 		rtl_fw->fw_name		= FIRMWARE_8153A_4;
9585 		rtl_fw->post_fw		= r8153_post_firmware_3;
9586 		break;
9587 	case RTL_VER_09:
9588 		rtl_fw->fw_name		= FIRMWARE_8153B_2;
9589 		rtl_fw->pre_fw		= r8153b_pre_firmware_1;
9590 		rtl_fw->post_fw		= r8153b_post_firmware_1;
9591 		break;
9592 	case RTL_VER_11:
9593 		rtl_fw->fw_name		= FIRMWARE_8156A_2;
9594 		rtl_fw->post_fw		= r8156a_post_firmware_1;
9595 		break;
9596 	case RTL_VER_13:
9597 	case RTL_VER_15:
9598 		rtl_fw->fw_name		= FIRMWARE_8156B_2;
9599 		break;
9600 	case RTL_VER_14:
9601 		rtl_fw->fw_name		= FIRMWARE_8153C_1;
9602 		rtl_fw->pre_fw		= r8153b_pre_firmware_1;
9603 		rtl_fw->post_fw		= r8153c_post_firmware_1;
9604 		break;
9605 	default:
9606 		break;
9607 	}
9608 
9609 	return 0;
9610 }
9611 
9612 static u8 __rtl_get_hw_ver(struct usb_device *udev)
9613 {
9614 	u32 ocp_data = 0;
9615 	__le32 *tmp;
9616 	u8 version;
9617 	int ret;
9618 	int i;
9619 
9620 	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
9621 	if (!tmp)
9622 		return 0;
9623 
9624 	/* Retry up to 3 times in case there is a transitory error. We do this
9625 	 * since retrying a read of the version is always safe and this
9626 	 * function doesn't take advantage of r8152_control_msg().
9627 	 */
9628 	for (i = 0; i < 3; i++) {
9629 		ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
9630 				      RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
9631 				      PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp),
9632 				      USB_CTRL_GET_TIMEOUT);
9633 		if (ret > 0) {
9634 			ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
9635 			break;
9636 		}
9637 	}
9638 
9639 	if (i != 0 && ret > 0)
9640 		dev_warn(&udev->dev, "Needed %d retries to read version\n", i);
9641 
9642 	kfree(tmp);
9643 
9644 	switch (ocp_data) {
9645 	case 0x4c00:
9646 		version = RTL_VER_01;
9647 		break;
9648 	case 0x4c10:
9649 		version = RTL_VER_02;
9650 		break;
9651 	case 0x5c00:
9652 		version = RTL_VER_03;
9653 		break;
9654 	case 0x5c10:
9655 		version = RTL_VER_04;
9656 		break;
9657 	case 0x5c20:
9658 		version = RTL_VER_05;
9659 		break;
9660 	case 0x5c30:
9661 		version = RTL_VER_06;
9662 		break;
9663 	case 0x4800:
9664 		version = RTL_VER_07;
9665 		break;
9666 	case 0x6000:
9667 		version = RTL_VER_08;
9668 		break;
9669 	case 0x6010:
9670 		version = RTL_VER_09;
9671 		break;
9672 	case 0x7010:
9673 		version = RTL_TEST_01;
9674 		break;
9675 	case 0x7020:
9676 		version = RTL_VER_10;
9677 		break;
9678 	case 0x7030:
9679 		version = RTL_VER_11;
9680 		break;
9681 	case 0x7400:
9682 		version = RTL_VER_12;
9683 		break;
9684 	case 0x7410:
9685 		version = RTL_VER_13;
9686 		break;
9687 	case 0x6400:
9688 		version = RTL_VER_14;
9689 		break;
9690 	case 0x7420:
9691 		version = RTL_VER_15;
9692 		break;
9693 	default:
9694 		version = RTL_VER_UNKNOWN;
9695 		dev_info(&udev->dev, "Unknown version 0x%04x\n", ocp_data);
9696 		break;
9697 	}
9698 
9699 	return version;
9700 }
9701 
9702 u8 rtl8152_get_version(struct usb_interface *intf)
9703 {
9704 	u8 version;
9705 
9706 	version = __rtl_get_hw_ver(interface_to_usbdev(intf));
9707 
9708 	dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
9709 
9710 	return version;
9711 }
9712 EXPORT_SYMBOL_GPL(rtl8152_get_version);
9713 
9714 static bool rtl8152_supports_lenovo_macpassthru(struct usb_device *udev)
9715 {
9716 	int parent_vendor_id = le16_to_cpu(udev->parent->descriptor.idVendor);
9717 	int product_id = le16_to_cpu(udev->descriptor.idProduct);
9718 	int vendor_id = le16_to_cpu(udev->descriptor.idVendor);
9719 
9720 	if (vendor_id == VENDOR_ID_LENOVO) {
9721 		switch (product_id) {
9722 		case DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB:
9723 		case DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK:
9724 		case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
9725 		case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
9726 		case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3:
9727 		case DEVICE_ID_THINKPAD_USB_C_DONGLE:
9728 			return 1;
9729 		}
9730 	} else if (vendor_id == VENDOR_ID_REALTEK && parent_vendor_id == VENDOR_ID_LENOVO) {
9731 		switch (product_id) {
9732 		case 0x8153:
9733 			return 1;
9734 		}
9735 	}
9736 	return 0;
9737 }
9738 
9739 static int rtl8152_probe_once(struct usb_interface *intf,
9740 			      const struct usb_device_id *id, u8 version)
9741 {
9742 	struct usb_device *udev = interface_to_usbdev(intf);
9743 	struct r8152 *tp;
9744 	struct net_device *netdev;
9745 	int ret;
9746 
9747 	usb_reset_device(udev);
9748 	netdev = alloc_etherdev(sizeof(struct r8152));
9749 	if (!netdev) {
9750 		dev_err(&intf->dev, "Out of memory\n");
9751 		return -ENOMEM;
9752 	}
9753 
9754 	SET_NETDEV_DEV(netdev, &intf->dev);
9755 	tp = netdev_priv(netdev);
9756 	tp->msg_enable = 0x7FFF;
9757 
9758 	tp->udev = udev;
9759 	tp->netdev = netdev;
9760 	tp->intf = intf;
9761 	tp->version = version;
9762 
9763 	tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0);
9764 	tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0);
9765 	tp->pipe_in = usb_rcvbulkpipe(udev, 1);
9766 	tp->pipe_out = usb_sndbulkpipe(udev, 2);
9767 	tp->pipe_intr = usb_rcvintpipe(udev, 3);
9768 
9769 	switch (version) {
9770 	case RTL_VER_01:
9771 	case RTL_VER_02:
9772 	case RTL_VER_07:
9773 		tp->mii.supports_gmii = 0;
9774 		break;
9775 	default:
9776 		tp->mii.supports_gmii = 1;
9777 		break;
9778 	}
9779 
9780 	ret = rtl_ops_init(tp);
9781 	if (ret)
9782 		goto out;
9783 
9784 	rtl_fw_init(tp);
9785 
9786 	mutex_init(&tp->control);
9787 	INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
9788 	INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
9789 	tasklet_setup(&tp->tx_tl, bottom_half);
9790 	tasklet_disable(&tp->tx_tl);
9791 
9792 	netdev->netdev_ops = &rtl8152_netdev_ops;
9793 	netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
9794 
9795 	netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9796 			    NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
9797 			    NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
9798 			    NETIF_F_HW_VLAN_CTAG_TX;
9799 	netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9800 			      NETIF_F_TSO | NETIF_F_FRAGLIST |
9801 			      NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
9802 			      NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
9803 	netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
9804 				NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
9805 				NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
9806 
9807 	if (tp->version == RTL_VER_01) {
9808 		netdev->features &= ~NETIF_F_RXCSUM;
9809 		netdev->hw_features &= ~NETIF_F_RXCSUM;
9810 	}
9811 
9812 	tp->lenovo_macpassthru = rtl8152_supports_lenovo_macpassthru(udev);
9813 
9814 	if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
9815 	    (!strcmp(udev->serial, "000001000000") ||
9816 	     !strcmp(udev->serial, "000002000000"))) {
9817 		dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
9818 		tp->dell_tb_rx_agg_bug = 1;
9819 	}
9820 
9821 	netdev->ethtool_ops = &ops;
9822 	netif_set_tso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
9823 
9824 	/* MTU range: 68 - 1500 or 9194 */
9825 	netdev->min_mtu = ETH_MIN_MTU;
9826 	switch (tp->version) {
9827 	case RTL_VER_03:
9828 	case RTL_VER_04:
9829 	case RTL_VER_05:
9830 	case RTL_VER_06:
9831 	case RTL_VER_08:
9832 	case RTL_VER_09:
9833 	case RTL_VER_14:
9834 		netdev->max_mtu = size_to_mtu(9 * 1024);
9835 		break;
9836 	case RTL_VER_10:
9837 	case RTL_VER_11:
9838 		netdev->max_mtu = size_to_mtu(15 * 1024);
9839 		break;
9840 	case RTL_VER_12:
9841 	case RTL_VER_13:
9842 	case RTL_VER_15:
9843 		netdev->max_mtu = size_to_mtu(16 * 1024);
9844 		break;
9845 	case RTL_VER_01:
9846 	case RTL_VER_02:
9847 	case RTL_VER_07:
9848 	default:
9849 		netdev->max_mtu = ETH_DATA_LEN;
9850 		break;
9851 	}
9852 
9853 	tp->mii.dev = netdev;
9854 	tp->mii.mdio_read = read_mii_word;
9855 	tp->mii.mdio_write = write_mii_word;
9856 	tp->mii.phy_id_mask = 0x3f;
9857 	tp->mii.reg_num_mask = 0x1f;
9858 	tp->mii.phy_id = R8152_PHY_ID;
9859 
9860 	tp->autoneg = AUTONEG_ENABLE;
9861 	tp->speed = SPEED_100;
9862 	tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
9863 			  RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
9864 	if (tp->mii.supports_gmii) {
9865 		if (tp->support_2500full &&
9866 		    tp->udev->speed >= USB_SPEED_SUPER) {
9867 			tp->speed = SPEED_2500;
9868 			tp->advertising |= RTL_ADVERTISED_2500_FULL;
9869 		} else {
9870 			tp->speed = SPEED_1000;
9871 		}
9872 		tp->advertising |= RTL_ADVERTISED_1000_FULL;
9873 	}
9874 	tp->duplex = DUPLEX_FULL;
9875 
9876 	tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
9877 	tp->rx_pending = 10 * RTL8152_MAX_RX;
9878 
9879 	intf->needs_remote_wakeup = 1;
9880 
9881 	if (!rtl_can_wakeup(tp))
9882 		__rtl_set_wol(tp, 0);
9883 	else
9884 		tp->saved_wolopts = __rtl_get_wol(tp);
9885 
9886 	tp->rtl_ops.init(tp);
9887 #if IS_BUILTIN(CONFIG_USB_RTL8152)
9888 	/* Retry in case request_firmware() is not ready yet. */
9889 	tp->rtl_fw.retry = true;
9890 #endif
9891 	queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
9892 	set_ethernet_addr(tp, false);
9893 
9894 	usb_set_intfdata(intf, tp);
9895 
9896 	netif_napi_add(netdev, &tp->napi, r8152_poll);
9897 
9898 	ret = register_netdev(netdev);
9899 	if (ret != 0) {
9900 		dev_err(&intf->dev, "couldn't register the device\n");
9901 		goto out1;
9902 	}
9903 
9904 	if (tp->saved_wolopts)
9905 		device_set_wakeup_enable(&udev->dev, true);
9906 	else
9907 		device_set_wakeup_enable(&udev->dev, false);
9908 
9909 	/* If we saw a control transfer error while probing then we may
9910 	 * want to try probe() again. Consider this an error.
9911 	 */
9912 	if (test_bit(PROBE_SHOULD_RETRY, &tp->flags))
9913 		goto out2;
9914 
9915 	set_bit(PROBED_WITH_NO_ERRORS, &tp->flags);
9916 	netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
9917 
9918 	return 0;
9919 
9920 out2:
9921 	unregister_netdev(netdev);
9922 
9923 out1:
9924 	tasklet_kill(&tp->tx_tl);
9925 	cancel_delayed_work_sync(&tp->hw_phy_work);
9926 	if (tp->rtl_ops.unload)
9927 		tp->rtl_ops.unload(tp);
9928 	rtl8152_release_firmware(tp);
9929 	usb_set_intfdata(intf, NULL);
9930 out:
9931 	if (test_bit(PROBE_SHOULD_RETRY, &tp->flags))
9932 		ret = -EAGAIN;
9933 
9934 	free_netdev(netdev);
9935 	return ret;
9936 }
9937 
9938 #define RTL8152_PROBE_TRIES	3
9939 
9940 static int rtl8152_probe(struct usb_interface *intf,
9941 			 const struct usb_device_id *id)
9942 {
9943 	u8 version;
9944 	int ret;
9945 	int i;
9946 
9947 	if (intf->cur_altsetting->desc.bInterfaceClass != USB_CLASS_VENDOR_SPEC)
9948 		return -ENODEV;
9949 
9950 	if (!rtl_check_vendor_ok(intf))
9951 		return -ENODEV;
9952 
9953 	version = rtl8152_get_version(intf);
9954 	if (version == RTL_VER_UNKNOWN)
9955 		return -ENODEV;
9956 
9957 	for (i = 0; i < RTL8152_PROBE_TRIES; i++) {
9958 		ret = rtl8152_probe_once(intf, id, version);
9959 		if (ret != -EAGAIN)
9960 			break;
9961 	}
9962 	if (ret == -EAGAIN) {
9963 		dev_err(&intf->dev,
9964 			"r8152 failed probe after %d tries; giving up\n", i);
9965 		return -ENODEV;
9966 	}
9967 
9968 	return ret;
9969 }
9970 
9971 static void rtl8152_disconnect(struct usb_interface *intf)
9972 {
9973 	struct r8152 *tp = usb_get_intfdata(intf);
9974 
9975 	usb_set_intfdata(intf, NULL);
9976 	if (tp) {
9977 		rtl_set_unplug(tp);
9978 
9979 		unregister_netdev(tp->netdev);
9980 		tasklet_kill(&tp->tx_tl);
9981 		cancel_delayed_work_sync(&tp->hw_phy_work);
9982 		if (tp->rtl_ops.unload)
9983 			tp->rtl_ops.unload(tp);
9984 		rtl8152_release_firmware(tp);
9985 		free_netdev(tp->netdev);
9986 	}
9987 }
9988 
9989 /* table of devices that work with this driver */
9990 static const struct usb_device_id rtl8152_table[] = {
9991 	/* Realtek */
9992 	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8050) },
9993 	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8053) },
9994 	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8152) },
9995 	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8153) },
9996 	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8155) },
9997 	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8156) },
9998 
9999 	/* Microsoft */
10000 	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab) },
10001 	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6) },
10002 	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927) },
10003 	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0c5e) },
10004 	{ USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101) },
10005 	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x304f) },
10006 	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x3054) },
10007 	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x3062) },
10008 	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x3069) },
10009 	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x3082) },
10010 	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x7205) },
10011 	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x720c) },
10012 	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x7214) },
10013 	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x721e) },
10014 	{ USB_DEVICE(VENDOR_ID_LENOVO,  0xa387) },
10015 	{ USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) },
10016 	{ USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff) },
10017 	{ USB_DEVICE(VENDOR_ID_TPLINK,  0x0601) },
10018 	{ USB_DEVICE(VENDOR_ID_DLINK,   0xb301) },
10019 	{ USB_DEVICE(VENDOR_ID_ASUS,    0x1976) },
10020 	{}
10021 };
10022 
10023 MODULE_DEVICE_TABLE(usb, rtl8152_table);
10024 
10025 static struct usb_driver rtl8152_driver = {
10026 	.name =		MODULENAME,
10027 	.id_table =	rtl8152_table,
10028 	.probe =	rtl8152_probe,
10029 	.disconnect =	rtl8152_disconnect,
10030 	.suspend =	rtl8152_suspend,
10031 	.resume =	rtl8152_resume,
10032 	.reset_resume =	rtl8152_reset_resume,
10033 	.pre_reset =	rtl8152_pre_reset,
10034 	.post_reset =	rtl8152_post_reset,
10035 	.supports_autosuspend = 1,
10036 	.disable_hub_initiated_lpm = 1,
10037 };
10038 
10039 static int rtl8152_cfgselector_probe(struct usb_device *udev)
10040 {
10041 	struct usb_host_config *c;
10042 	int i, num_configs;
10043 
10044 	/* Switch the device to vendor mode, if and only if the vendor mode
10045 	 * driver supports it.
10046 	 */
10047 	if (__rtl_get_hw_ver(udev) == RTL_VER_UNKNOWN)
10048 		return 0;
10049 
10050 	/* The vendor mode is not always config #1, so to find it out. */
10051 	c = udev->config;
10052 	num_configs = udev->descriptor.bNumConfigurations;
10053 	for (i = 0; i < num_configs; (i++, c++)) {
10054 		struct usb_interface_descriptor	*desc = NULL;
10055 
10056 		if (!c->desc.bNumInterfaces)
10057 			continue;
10058 		desc = &c->intf_cache[0]->altsetting->desc;
10059 		if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC)
10060 			break;
10061 	}
10062 
10063 	if (i == num_configs)
10064 		return -ENODEV;
10065 
10066 	if (usb_set_configuration(udev, c->desc.bConfigurationValue)) {
10067 		dev_err(&udev->dev, "Failed to set configuration %d\n",
10068 			c->desc.bConfigurationValue);
10069 		return -ENODEV;
10070 	}
10071 
10072 	return 0;
10073 }
10074 
10075 static struct usb_device_driver rtl8152_cfgselector_driver = {
10076 	.name =		MODULENAME "-cfgselector",
10077 	.probe =	rtl8152_cfgselector_probe,
10078 	.id_table =	rtl8152_table,
10079 	.generic_subclass = 1,
10080 	.supports_autosuspend = 1,
10081 };
10082 
10083 static int __init rtl8152_driver_init(void)
10084 {
10085 	int ret;
10086 
10087 	ret = usb_register_device_driver(&rtl8152_cfgselector_driver, THIS_MODULE);
10088 	if (ret)
10089 		return ret;
10090 	return usb_register(&rtl8152_driver);
10091 }
10092 
10093 static void __exit rtl8152_driver_exit(void)
10094 {
10095 	usb_deregister(&rtl8152_driver);
10096 	usb_deregister_device_driver(&rtl8152_cfgselector_driver);
10097 }
10098 
10099 module_init(rtl8152_driver_init);
10100 module_exit(rtl8152_driver_exit);
10101 
10102 MODULE_AUTHOR(DRIVER_AUTHOR);
10103 MODULE_DESCRIPTION(DRIVER_DESC);
10104 MODULE_LICENSE("GPL");
10105 MODULE_VERSION(DRIVER_VERSION);
10106