1 /* 2 * Copyright (C) 2015 Microchip Technology 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 #ifndef _LAN78XX_H 18 #define _LAN78XX_H 19 20 /* USB Vendor Requests */ 21 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 22 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 23 #define USB_VENDOR_REQUEST_GET_STATS 0xA2 24 25 /* Interrupt Endpoint status word bitfields */ 26 #define INT_ENP_EEE_START_TX_LPI_INT BIT(26) 27 #define INT_ENP_EEE_STOP_TX_LPI_INT BIT(25) 28 #define INT_ENP_EEE_RX_LPI_INT BIT(24) 29 #define INT_ENP_RDFO_INT BIT(22) 30 #define INT_ENP_TXE_INT BIT(21) 31 #define INT_ENP_TX_DIS_INT BIT(19) 32 #define INT_ENP_RX_DIS_INT BIT(18) 33 #define INT_ENP_PHY_INT BIT(17) 34 #define INT_ENP_DP_INT BIT(16) 35 #define INT_ENP_MAC_ERR_INT BIT(15) 36 #define INT_ENP_TDFU_INT BIT(14) 37 #define INT_ENP_TDFO_INT BIT(13) 38 #define INT_ENP_UTX_FP_INT BIT(12) 39 40 #define TX_PKT_ALIGNMENT 4 41 #define RX_PKT_ALIGNMENT 4 42 43 /* Tx Command A */ 44 #define TX_CMD_A_IGE_ (0x20000000) 45 #define TX_CMD_A_ICE_ (0x10000000) 46 #define TX_CMD_A_LSO_ (0x08000000) 47 #define TX_CMD_A_IPE_ (0x04000000) 48 #define TX_CMD_A_TPE_ (0x02000000) 49 #define TX_CMD_A_IVTG_ (0x01000000) 50 #define TX_CMD_A_RVTG_ (0x00800000) 51 #define TX_CMD_A_FCS_ (0x00400000) 52 #define TX_CMD_A_LEN_MASK_ (0x000FFFFF) 53 54 /* Tx Command B */ 55 #define TX_CMD_B_MSS_SHIFT_ (16) 56 #define TX_CMD_B_MSS_MASK_ (0x3FFF0000) 57 #define TX_CMD_B_MSS_MIN_ ((unsigned short)8) 58 #define TX_CMD_B_VTAG_MASK_ (0x0000FFFF) 59 #define TX_CMD_B_VTAG_PRI_MASK_ (0x0000E000) 60 #define TX_CMD_B_VTAG_CFI_MASK_ (0x00001000) 61 #define TX_CMD_B_VTAG_VID_MASK_ (0x00000FFF) 62 63 /* Rx Command A */ 64 #define RX_CMD_A_ICE_ (0x80000000) 65 #define RX_CMD_A_TCE_ (0x40000000) 66 #define RX_CMD_A_CSE_MASK_ (0xC0000000) 67 #define RX_CMD_A_IPV_ (0x20000000) 68 #define RX_CMD_A_PID_MASK_ (0x18000000) 69 #define RX_CMD_A_PID_NONE_IP_ (0x00000000) 70 #define RX_CMD_A_PID_TCP_IP_ (0x08000000) 71 #define RX_CMD_A_PID_UDP_IP_ (0x10000000) 72 #define RX_CMD_A_PID_IP_ (0x18000000) 73 #define RX_CMD_A_PFF_ (0x04000000) 74 #define RX_CMD_A_BAM_ (0x02000000) 75 #define RX_CMD_A_MAM_ (0x01000000) 76 #define RX_CMD_A_FVTG_ (0x00800000) 77 #define RX_CMD_A_RED_ (0x00400000) 78 #define RX_CMD_A_RX_ERRS_MASK_ (0xC03F0000) 79 #define RX_CMD_A_RWT_ (0x00200000) 80 #define RX_CMD_A_RUNT_ (0x00100000) 81 #define RX_CMD_A_LONG_ (0x00080000) 82 #define RX_CMD_A_RXE_ (0x00040000) 83 #define RX_CMD_A_DRB_ (0x00020000) 84 #define RX_CMD_A_FCS_ (0x00010000) 85 #define RX_CMD_A_UAM_ (0x00008000) 86 #define RX_CMD_A_ICSM_ (0x00004000) 87 #define RX_CMD_A_LEN_MASK_ (0x00003FFF) 88 89 /* Rx Command B */ 90 #define RX_CMD_B_CSUM_SHIFT_ (16) 91 #define RX_CMD_B_CSUM_MASK_ (0xFFFF0000) 92 #define RX_CMD_B_VTAG_MASK_ (0x0000FFFF) 93 #define RX_CMD_B_VTAG_PRI_MASK_ (0x0000E000) 94 #define RX_CMD_B_VTAG_CFI_MASK_ (0x00001000) 95 #define RX_CMD_B_VTAG_VID_MASK_ (0x00000FFF) 96 97 /* Rx Command C */ 98 #define RX_CMD_C_WAKE_SHIFT_ (15) 99 #define RX_CMD_C_WAKE_ (0x8000) 100 #define RX_CMD_C_REF_FAIL_SHIFT_ (14) 101 #define RX_CMD_C_REF_FAIL_ (0x4000) 102 103 /* SCSRs */ 104 #define NUMBER_OF_REGS (193) 105 106 #define ID_REV (0x00) 107 #define ID_REV_CHIP_ID_MASK_ (0xFFFF0000) 108 #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) 109 #define ID_REV_CHIP_ID_7800_ (0x7800) 110 #define ID_REV_CHIP_ID_7850_ (0x7850) 111 #define ID_REV_CHIP_ID_7801_ (0x7801) 112 113 #define FPGA_REV (0x04) 114 #define FPGA_REV_MINOR_MASK_ (0x0000FF00) 115 #define FPGA_REV_MAJOR_MASK_ (0x000000FF) 116 117 #define INT_STS (0x0C) 118 #define INT_STS_CLEAR_ALL_ (0xFFFFFFFF) 119 #define INT_STS_EEE_TX_LPI_STRT_ (0x04000000) 120 #define INT_STS_EEE_TX_LPI_STOP_ (0x02000000) 121 #define INT_STS_EEE_RX_LPI_ (0x01000000) 122 #define INT_STS_RDFO_ (0x00400000) 123 #define INT_STS_TXE_ (0x00200000) 124 #define INT_STS_TX_DIS_ (0x00080000) 125 #define INT_STS_RX_DIS_ (0x00040000) 126 #define INT_STS_PHY_INT_ (0x00020000) 127 #define INT_STS_DP_INT_ (0x00010000) 128 #define INT_STS_MAC_ERR_ (0x00008000) 129 #define INT_STS_TDFU_ (0x00004000) 130 #define INT_STS_TDFO_ (0x00002000) 131 #define INT_STS_UFX_FP_ (0x00001000) 132 #define INT_STS_GPIO_MASK_ (0x00000FFF) 133 #define INT_STS_GPIO11_ (0x00000800) 134 #define INT_STS_GPIO10_ (0x00000400) 135 #define INT_STS_GPIO9_ (0x00000200) 136 #define INT_STS_GPIO8_ (0x00000100) 137 #define INT_STS_GPIO7_ (0x00000080) 138 #define INT_STS_GPIO6_ (0x00000040) 139 #define INT_STS_GPIO5_ (0x00000020) 140 #define INT_STS_GPIO4_ (0x00000010) 141 #define INT_STS_GPIO3_ (0x00000008) 142 #define INT_STS_GPIO2_ (0x00000004) 143 #define INT_STS_GPIO1_ (0x00000002) 144 #define INT_STS_GPIO0_ (0x00000001) 145 146 #define HW_CFG (0x010) 147 #define HW_CFG_CLK125_EN_ (0x02000000) 148 #define HW_CFG_REFCLK25_EN_ (0x01000000) 149 #define HW_CFG_LED3_EN_ (0x00800000) 150 #define HW_CFG_LED2_EN_ (0x00400000) 151 #define HW_CFG_LED1_EN_ (0x00200000) 152 #define HW_CFG_LED0_EN_ (0x00100000) 153 #define HW_CFG_EEE_PHY_LUSU_ (0x00020000) 154 #define HW_CFG_EEE_TSU_ (0x00010000) 155 #define HW_CFG_NETDET_STS_ (0x00008000) 156 #define HW_CFG_NETDET_EN_ (0x00004000) 157 #define HW_CFG_EEM_ (0x00002000) 158 #define HW_CFG_RST_PROTECT_ (0x00001000) 159 #define HW_CFG_CONNECT_BUF_ (0x00000400) 160 #define HW_CFG_CONNECT_EN_ (0x00000200) 161 #define HW_CFG_CONNECT_POL_ (0x00000100) 162 #define HW_CFG_SUSPEND_N_SEL_MASK_ (0x000000C0) 163 #define HW_CFG_SUSPEND_N_SEL_2 (0x00000000) 164 #define HW_CFG_SUSPEND_N_SEL_12N (0x00000040) 165 #define HW_CFG_SUSPEND_N_SEL_012N (0x00000080) 166 #define HW_CFG_SUSPEND_N_SEL_0123N (0x000000C0) 167 #define HW_CFG_SUSPEND_N_POL_ (0x00000020) 168 #define HW_CFG_MEF_ (0x00000010) 169 #define HW_CFG_ETC_ (0x00000008) 170 #define HW_CFG_LRST_ (0x00000002) 171 #define HW_CFG_SRST_ (0x00000001) 172 173 #define PMT_CTL (0x014) 174 #define PMT_CTL_EEE_WAKEUP_EN_ (0x00002000) 175 #define PMT_CTL_EEE_WUPS_ (0x00001000) 176 #define PMT_CTL_MAC_SRST_ (0x00000800) 177 #define PMT_CTL_PHY_PWRUP_ (0x00000400) 178 #define PMT_CTL_RES_CLR_WKP_MASK_ (0x00000300) 179 #define PMT_CTL_RES_CLR_WKP_STS_ (0x00000200) 180 #define PMT_CTL_RES_CLR_WKP_EN_ (0x00000100) 181 #define PMT_CTL_READY_ (0x00000080) 182 #define PMT_CTL_SUS_MODE_MASK_ (0x00000060) 183 #define PMT_CTL_SUS_MODE_0_ (0x00000000) 184 #define PMT_CTL_SUS_MODE_1_ (0x00000020) 185 #define PMT_CTL_SUS_MODE_2_ (0x00000040) 186 #define PMT_CTL_SUS_MODE_3_ (0x00000060) 187 #define PMT_CTL_PHY_RST_ (0x00000010) 188 #define PMT_CTL_WOL_EN_ (0x00000008) 189 #define PMT_CTL_PHY_WAKE_EN_ (0x00000004) 190 #define PMT_CTL_WUPS_MASK_ (0x00000003) 191 #define PMT_CTL_WUPS_MLT_ (0x00000003) 192 #define PMT_CTL_WUPS_MAC_ (0x00000002) 193 #define PMT_CTL_WUPS_PHY_ (0x00000001) 194 195 #define GPIO_CFG0 (0x018) 196 #define GPIO_CFG0_GPIOEN_MASK_ (0x0000F000) 197 #define GPIO_CFG0_GPIOEN3_ (0x00008000) 198 #define GPIO_CFG0_GPIOEN2_ (0x00004000) 199 #define GPIO_CFG0_GPIOEN1_ (0x00002000) 200 #define GPIO_CFG0_GPIOEN0_ (0x00001000) 201 #define GPIO_CFG0_GPIOBUF_MASK_ (0x00000F00) 202 #define GPIO_CFG0_GPIOBUF3_ (0x00000800) 203 #define GPIO_CFG0_GPIOBUF2_ (0x00000400) 204 #define GPIO_CFG0_GPIOBUF1_ (0x00000200) 205 #define GPIO_CFG0_GPIOBUF0_ (0x00000100) 206 #define GPIO_CFG0_GPIODIR_MASK_ (0x000000F0) 207 #define GPIO_CFG0_GPIODIR3_ (0x00000080) 208 #define GPIO_CFG0_GPIODIR2_ (0x00000040) 209 #define GPIO_CFG0_GPIODIR1_ (0x00000020) 210 #define GPIO_CFG0_GPIODIR0_ (0x00000010) 211 #define GPIO_CFG0_GPIOD_MASK_ (0x0000000F) 212 #define GPIO_CFG0_GPIOD3_ (0x00000008) 213 #define GPIO_CFG0_GPIOD2_ (0x00000004) 214 #define GPIO_CFG0_GPIOD1_ (0x00000002) 215 #define GPIO_CFG0_GPIOD0_ (0x00000001) 216 217 #define GPIO_CFG1 (0x01C) 218 #define GPIO_CFG1_GPIOEN_MASK_ (0xFF000000) 219 #define GPIO_CFG1_GPIOEN11_ (0x80000000) 220 #define GPIO_CFG1_GPIOEN10_ (0x40000000) 221 #define GPIO_CFG1_GPIOEN9_ (0x20000000) 222 #define GPIO_CFG1_GPIOEN8_ (0x10000000) 223 #define GPIO_CFG1_GPIOEN7_ (0x08000000) 224 #define GPIO_CFG1_GPIOEN6_ (0x04000000) 225 #define GPIO_CFG1_GPIOEN5_ (0x02000000) 226 #define GPIO_CFG1_GPIOEN4_ (0x01000000) 227 #define GPIO_CFG1_GPIOBUF_MASK_ (0x00FF0000) 228 #define GPIO_CFG1_GPIOBUF11_ (0x00800000) 229 #define GPIO_CFG1_GPIOBUF10_ (0x00400000) 230 #define GPIO_CFG1_GPIOBUF9_ (0x00200000) 231 #define GPIO_CFG1_GPIOBUF8_ (0x00100000) 232 #define GPIO_CFG1_GPIOBUF7_ (0x00080000) 233 #define GPIO_CFG1_GPIOBUF6_ (0x00040000) 234 #define GPIO_CFG1_GPIOBUF5_ (0x00020000) 235 #define GPIO_CFG1_GPIOBUF4_ (0x00010000) 236 #define GPIO_CFG1_GPIODIR_MASK_ (0x0000FF00) 237 #define GPIO_CFG1_GPIODIR11_ (0x00008000) 238 #define GPIO_CFG1_GPIODIR10_ (0x00004000) 239 #define GPIO_CFG1_GPIODIR9_ (0x00002000) 240 #define GPIO_CFG1_GPIODIR8_ (0x00001000) 241 #define GPIO_CFG1_GPIODIR7_ (0x00000800) 242 #define GPIO_CFG1_GPIODIR6_ (0x00000400) 243 #define GPIO_CFG1_GPIODIR5_ (0x00000200) 244 #define GPIO_CFG1_GPIODIR4_ (0x00000100) 245 #define GPIO_CFG1_GPIOD_MASK_ (0x000000FF) 246 #define GPIO_CFG1_GPIOD11_ (0x00000080) 247 #define GPIO_CFG1_GPIOD10_ (0x00000040) 248 #define GPIO_CFG1_GPIOD9_ (0x00000020) 249 #define GPIO_CFG1_GPIOD8_ (0x00000010) 250 #define GPIO_CFG1_GPIOD7_ (0x00000008) 251 #define GPIO_CFG1_GPIOD6_ (0x00000004) 252 #define GPIO_CFG1_GPIOD6_ (0x00000004) 253 #define GPIO_CFG1_GPIOD5_ (0x00000002) 254 #define GPIO_CFG1_GPIOD4_ (0x00000001) 255 256 #define GPIO_WAKE (0x020) 257 #define GPIO_WAKE_GPIOPOL_MASK_ (0x0FFF0000) 258 #define GPIO_WAKE_GPIOPOL11_ (0x08000000) 259 #define GPIO_WAKE_GPIOPOL10_ (0x04000000) 260 #define GPIO_WAKE_GPIOPOL9_ (0x02000000) 261 #define GPIO_WAKE_GPIOPOL8_ (0x01000000) 262 #define GPIO_WAKE_GPIOPOL7_ (0x00800000) 263 #define GPIO_WAKE_GPIOPOL6_ (0x00400000) 264 #define GPIO_WAKE_GPIOPOL5_ (0x00200000) 265 #define GPIO_WAKE_GPIOPOL4_ (0x00100000) 266 #define GPIO_WAKE_GPIOPOL3_ (0x00080000) 267 #define GPIO_WAKE_GPIOPOL2_ (0x00040000) 268 #define GPIO_WAKE_GPIOPOL1_ (0x00020000) 269 #define GPIO_WAKE_GPIOPOL0_ (0x00010000) 270 #define GPIO_WAKE_GPIOWK_MASK_ (0x00000FFF) 271 #define GPIO_WAKE_GPIOWK11_ (0x00000800) 272 #define GPIO_WAKE_GPIOWK10_ (0x00000400) 273 #define GPIO_WAKE_GPIOWK9_ (0x00000200) 274 #define GPIO_WAKE_GPIOWK8_ (0x00000100) 275 #define GPIO_WAKE_GPIOWK7_ (0x00000080) 276 #define GPIO_WAKE_GPIOWK6_ (0x00000040) 277 #define GPIO_WAKE_GPIOWK5_ (0x00000020) 278 #define GPIO_WAKE_GPIOWK4_ (0x00000010) 279 #define GPIO_WAKE_GPIOWK3_ (0x00000008) 280 #define GPIO_WAKE_GPIOWK2_ (0x00000004) 281 #define GPIO_WAKE_GPIOWK1_ (0x00000002) 282 #define GPIO_WAKE_GPIOWK0_ (0x00000001) 283 284 #define DP_SEL (0x024) 285 #define DP_SEL_DPRDY_ (0x80000000) 286 #define DP_SEL_RSEL_MASK_ (0x0000000F) 287 #define DP_SEL_RSEL_USB_PHY_CSRS_ (0x0000000F) 288 #define DP_SEL_RSEL_OTP_64BIT_ (0x00000009) 289 #define DP_SEL_RSEL_OTP_8BIT_ (0x00000008) 290 #define DP_SEL_RSEL_UTX_BUF_RAM_ (0x00000007) 291 #define DP_SEL_RSEL_DESC_RAM_ (0x00000005) 292 #define DP_SEL_RSEL_TXFIFO_ (0x00000004) 293 #define DP_SEL_RSEL_RXFIFO_ (0x00000003) 294 #define DP_SEL_RSEL_LSO_ (0x00000002) 295 #define DP_SEL_RSEL_VLAN_DA_ (0x00000001) 296 #define DP_SEL_RSEL_URXBUF_ (0x00000000) 297 #define DP_SEL_VHF_HASH_LEN (16) 298 #define DP_SEL_VHF_VLAN_LEN (128) 299 300 #define DP_CMD (0x028) 301 #define DP_CMD_WRITE_ (0x00000001) 302 #define DP_CMD_READ_ (0x00000000) 303 304 #define DP_ADDR (0x02C) 305 #define DP_ADDR_MASK_ (0x00003FFF) 306 307 #define DP_DATA (0x030) 308 309 #define E2P_CMD (0x040) 310 #define E2P_CMD_EPC_BUSY_ (0x80000000) 311 #define E2P_CMD_EPC_CMD_MASK_ (0x70000000) 312 #define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000) 313 #define E2P_CMD_EPC_CMD_ERAL_ (0x60000000) 314 #define E2P_CMD_EPC_CMD_ERASE_ (0x50000000) 315 #define E2P_CMD_EPC_CMD_WRAL_ (0x40000000) 316 #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) 317 #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) 318 #define E2P_CMD_EPC_CMD_EWDS_ (0x10000000) 319 #define E2P_CMD_EPC_CMD_READ_ (0x00000000) 320 #define E2P_CMD_EPC_TIMEOUT_ (0x00000400) 321 #define E2P_CMD_EPC_DL_ (0x00000200) 322 #define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF) 323 324 #define E2P_DATA (0x044) 325 #define E2P_DATA_EEPROM_DATA_MASK_ (0x000000FF) 326 327 #define BOS_ATTR (0x050) 328 #define BOS_ATTR_BLOCK_SIZE_MASK_ (0x000000FF) 329 330 #define SS_ATTR (0x054) 331 #define SS_ATTR_POLL_INT_MASK_ (0x00FF0000) 332 #define SS_ATTR_DEV_DESC_SIZE_MASK_ (0x0000FF00) 333 #define SS_ATTR_CFG_BLK_SIZE_MASK_ (0x000000FF) 334 335 #define HS_ATTR (0x058) 336 #define HS_ATTR_POLL_INT_MASK_ (0x00FF0000) 337 #define HS_ATTR_DEV_DESC_SIZE_MASK_ (0x0000FF00) 338 #define HS_ATTR_CFG_BLK_SIZE_MASK_ (0x000000FF) 339 340 #define FS_ATTR (0x05C) 341 #define FS_ATTR_POLL_INT_MASK_ (0x00FF0000) 342 #define FS_ATTR_DEV_DESC_SIZE_MASK_ (0x0000FF00) 343 #define FS_ATTR_CFG_BLK_SIZE_MASK_ (0x000000FF) 344 345 #define STR_ATTR0 (0x060) 346 #define STR_ATTR0_CFGSTR_DESC_SIZE_MASK_ (0xFF000000) 347 #define STR_ATTR0_SERSTR_DESC_SIZE_MASK_ (0x00FF0000) 348 #define STR_ATTR0_PRODSTR_DESC_SIZE_MASK_ (0x0000FF00) 349 #define STR_ATTR0_MANUF_DESC_SIZE_MASK_ (0x000000FF) 350 351 #define STR_ATTR1 (0x064) 352 #define STR_ATTR1_INTSTR_DESC_SIZE_MASK_ (0x000000FF) 353 354 #define STR_FLAG_ATTR (0x068) 355 #define STR_FLAG_ATTR_PME_FLAGS_MASK_ (0x000000FF) 356 357 #define USB_CFG0 (0x080) 358 #define USB_CFG_LPM_RESPONSE_ (0x80000000) 359 #define USB_CFG_LPM_CAPABILITY_ (0x40000000) 360 #define USB_CFG_LPM_ENBL_SLPM_ (0x20000000) 361 #define USB_CFG_HIRD_THR_MASK_ (0x1F000000) 362 #define USB_CFG_HIRD_THR_960_ (0x1C000000) 363 #define USB_CFG_HIRD_THR_885_ (0x1B000000) 364 #define USB_CFG_HIRD_THR_810_ (0x1A000000) 365 #define USB_CFG_HIRD_THR_735_ (0x19000000) 366 #define USB_CFG_HIRD_THR_660_ (0x18000000) 367 #define USB_CFG_HIRD_THR_585_ (0x17000000) 368 #define USB_CFG_HIRD_THR_510_ (0x16000000) 369 #define USB_CFG_HIRD_THR_435_ (0x15000000) 370 #define USB_CFG_HIRD_THR_360_ (0x14000000) 371 #define USB_CFG_HIRD_THR_285_ (0x13000000) 372 #define USB_CFG_HIRD_THR_210_ (0x12000000) 373 #define USB_CFG_HIRD_THR_135_ (0x11000000) 374 #define USB_CFG_HIRD_THR_60_ (0x10000000) 375 #define USB_CFG_MAX_BURST_BI_MASK_ (0x00F00000) 376 #define USB_CFG_MAX_BURST_BO_MASK_ (0x000F0000) 377 #define USB_CFG_MAX_DEV_SPEED_MASK_ (0x0000E000) 378 #define USB_CFG_MAX_DEV_SPEED_SS_ (0x00008000) 379 #define USB_CFG_MAX_DEV_SPEED_HS_ (0x00000000) 380 #define USB_CFG_MAX_DEV_SPEED_FS_ (0x00002000) 381 #define USB_CFG_PHY_BOOST_MASK_ (0x00000180) 382 #define USB_CFG_PHY_BOOST_PLUS_12_ (0x00000180) 383 #define USB_CFG_PHY_BOOST_PLUS_8_ (0x00000100) 384 #define USB_CFG_PHY_BOOST_PLUS_4_ (0x00000080) 385 #define USB_CFG_PHY_BOOST_NORMAL_ (0x00000000) 386 #define USB_CFG_BIR_ (0x00000040) 387 #define USB_CFG_BCE_ (0x00000020) 388 #define USB_CFG_PORT_SWAP_ (0x00000010) 389 #define USB_CFG_LPM_EN_ (0x00000008) 390 #define USB_CFG_RMT_WKP_ (0x00000004) 391 #define USB_CFG_PWR_SEL_ (0x00000002) 392 #define USB_CFG_STALL_BO_DIS_ (0x00000001) 393 394 #define USB_CFG1 (0x084) 395 #define USB_CFG1_U1_TIMEOUT_MASK_ (0xFF000000) 396 #define USB_CFG1_U2_TIMEOUT_MASK_ (0x00FF0000) 397 #define USB_CFG1_HS_TOUT_CAL_MASK_ (0x0000E000) 398 #define USB_CFG1_DEV_U2_INIT_EN_ (0x00001000) 399 #define USB_CFG1_DEV_U2_EN_ (0x00000800) 400 #define USB_CFG1_DEV_U1_INIT_EN_ (0x00000400) 401 #define USB_CFG1_DEV_U1_EN_ (0x00000200) 402 #define USB_CFG1_LTM_ENABLE_ (0x00000100) 403 #define USB_CFG1_FS_TOUT_CAL_MASK_ (0x00000070) 404 #define USB_CFG1_SCALE_DOWN_MASK_ (0x00000003) 405 #define USB_CFG1_SCALE_DOWN_MODE3_ (0x00000003) 406 #define USB_CFG1_SCALE_DOWN_MODE2_ (0x00000002) 407 #define USB_CFG1_SCALE_DOWN_MODE1_ (0x00000001) 408 #define USB_CFG1_SCALE_DOWN_MODE0_ (0x00000000) 409 410 #define USB_CFG2 (0x088) 411 #define USB_CFG2_SS_DETACH_TIME_MASK_ (0xFFFF0000) 412 #define USB_CFG2_HS_DETACH_TIME_MASK_ (0x0000FFFF) 413 414 #define BURST_CAP (0x090) 415 #define BURST_CAP_SIZE_MASK_ (0x000000FF) 416 417 #define BULK_IN_DLY (0x094) 418 #define BULK_IN_DLY_MASK_ (0x0000FFFF) 419 420 #define INT_EP_CTL (0x098) 421 #define INT_EP_INTEP_ON_ (0x80000000) 422 #define INT_STS_EEE_TX_LPI_STRT_EN_ (0x04000000) 423 #define INT_STS_EEE_TX_LPI_STOP_EN_ (0x02000000) 424 #define INT_STS_EEE_RX_LPI_EN_ (0x01000000) 425 #define INT_EP_RDFO_EN_ (0x00400000) 426 #define INT_EP_TXE_EN_ (0x00200000) 427 #define INT_EP_TX_DIS_EN_ (0x00080000) 428 #define INT_EP_RX_DIS_EN_ (0x00040000) 429 #define INT_EP_PHY_INT_EN_ (0x00020000) 430 #define INT_EP_DP_INT_EN_ (0x00010000) 431 #define INT_EP_MAC_ERR_EN_ (0x00008000) 432 #define INT_EP_TDFU_EN_ (0x00004000) 433 #define INT_EP_TDFO_EN_ (0x00002000) 434 #define INT_EP_UTX_FP_EN_ (0x00001000) 435 #define INT_EP_GPIO_EN_MASK_ (0x00000FFF) 436 437 #define PIPE_CTL (0x09C) 438 #define PIPE_CTL_TXSWING_ (0x00000040) 439 #define PIPE_CTL_TXMARGIN_MASK_ (0x00000038) 440 #define PIPE_CTL_TXDEEMPHASIS_MASK_ (0x00000006) 441 #define PIPE_CTL_ELASTICITYBUFFERMODE_ (0x00000001) 442 443 #define U1_LATENCY (0xA0) 444 #define U2_LATENCY (0xA4) 445 446 #define USB_STATUS (0x0A8) 447 #define USB_STATUS_REMOTE_WK_ (0x00100000) 448 #define USB_STATUS_FUNC_REMOTE_WK_ (0x00080000) 449 #define USB_STATUS_LTM_ENABLE_ (0x00040000) 450 #define USB_STATUS_U2_ENABLE_ (0x00020000) 451 #define USB_STATUS_U1_ENABLE_ (0x00010000) 452 #define USB_STATUS_SET_SEL_ (0x00000020) 453 #define USB_STATUS_REMOTE_WK_STS_ (0x00000010) 454 #define USB_STATUS_FUNC_REMOTE_WK_STS_ (0x00000008) 455 #define USB_STATUS_LTM_ENABLE_STS_ (0x00000004) 456 #define USB_STATUS_U2_ENABLE_STS_ (0x00000002) 457 #define USB_STATUS_U1_ENABLE_STS_ (0x00000001) 458 459 #define USB_CFG3 (0x0AC) 460 #define USB_CFG3_EN_U2_LTM_ (0x40000000) 461 #define USB_CFG3_BULK_OUT_NUMP_OVR_ (0x20000000) 462 #define USB_CFG3_DIS_FAST_U1_EXIT_ (0x10000000) 463 #define USB_CFG3_LPM_NYET_THR_ (0x0F000000) 464 #define USB_CFG3_RX_DET_2_POL_LFPS_ (0x00800000) 465 #define USB_CFG3_LFPS_FILT_ (0x00400000) 466 #define USB_CFG3_SKIP_RX_DET_ (0x00200000) 467 #define USB_CFG3_DELAY_P1P2P3_ (0x001C0000) 468 #define USB_CFG3_DELAY_PHY_PWR_CHG_ (0x00020000) 469 #define USB_CFG3_U1U2_EXIT_FR_ (0x00010000) 470 #define USB_CFG3_REQ_P1P2P3 (0x00008000) 471 #define USB_CFG3_HST_PRT_CMPL_ (0x00004000) 472 #define USB_CFG3_DIS_SCRAMB_ (0x00002000) 473 #define USB_CFG3_PWR_DN_SCALE_ (0x00001FFF) 474 475 #define RFE_CTL (0x0B0) 476 #define RFE_CTL_IGMP_COE_ (0x00004000) 477 #define RFE_CTL_ICMP_COE_ (0x00002000) 478 #define RFE_CTL_TCPUDP_COE_ (0x00001000) 479 #define RFE_CTL_IP_COE_ (0x00000800) 480 #define RFE_CTL_BCAST_EN_ (0x00000400) 481 #define RFE_CTL_MCAST_EN_ (0x00000200) 482 #define RFE_CTL_UCAST_EN_ (0x00000100) 483 #define RFE_CTL_VLAN_STRIP_ (0x00000080) 484 #define RFE_CTL_DISCARD_UNTAGGED_ (0x00000040) 485 #define RFE_CTL_VLAN_FILTER_ (0x00000020) 486 #define RFE_CTL_SA_FILTER_ (0x00000010) 487 #define RFE_CTL_MCAST_HASH_ (0x00000008) 488 #define RFE_CTL_DA_HASH_ (0x00000004) 489 #define RFE_CTL_DA_PERFECT_ (0x00000002) 490 #define RFE_CTL_RST_ (0x00000001) 491 492 #define VLAN_TYPE (0x0B4) 493 #define VLAN_TYPE_MASK_ (0x0000FFFF) 494 495 #define FCT_RX_CTL (0x0C0) 496 #define FCT_RX_CTL_EN_ (0x80000000) 497 #define FCT_RX_CTL_RST_ (0x40000000) 498 #define FCT_RX_CTL_SBF_ (0x02000000) 499 #define FCT_RX_CTL_OVFL_ (0x01000000) 500 #define FCT_RX_CTL_DROP_ (0x00800000) 501 #define FCT_RX_CTL_NOT_EMPTY_ (0x00400000) 502 #define FCT_RX_CTL_EMPTY_ (0x00200000) 503 #define FCT_RX_CTL_DIS_ (0x00100000) 504 #define FCT_RX_CTL_USED_MASK_ (0x0000FFFF) 505 506 #define FCT_TX_CTL (0x0C4) 507 #define FCT_TX_CTL_EN_ (0x80000000) 508 #define FCT_TX_CTL_RST_ (0x40000000) 509 #define FCT_TX_CTL_NOT_EMPTY_ (0x00400000) 510 #define FCT_TX_CTL_EMPTY_ (0x00200000) 511 #define FCT_TX_CTL_DIS_ (0x00100000) 512 #define FCT_TX_CTL_USED_MASK_ (0x0000FFFF) 513 514 #define FCT_RX_FIFO_END (0x0C8) 515 #define FCT_RX_FIFO_END_MASK_ (0x0000007F) 516 517 #define FCT_TX_FIFO_END (0x0CC) 518 #define FCT_TX_FIFO_END_MASK_ (0x0000003F) 519 520 #define FCT_FLOW (0x0D0) 521 #define FCT_FLOW_OFF_MASK_ (0x00007F00) 522 #define FCT_FLOW_ON_MASK_ (0x0000007F) 523 524 #define RX_DP_STOR (0x0D4) 525 #define RX_DP_STORE_TOT_RXUSED_MASK_ (0xFFFF0000) 526 #define RX_DP_STORE_UTX_RXUSED_MASK_ (0x0000FFFF) 527 528 #define TX_DP_STOR (0x0D8) 529 #define TX_DP_STORE_TOT_TXUSED_MASK_ (0xFFFF0000) 530 #define TX_DP_STORE_URX_TXUSED_MASK_ (0x0000FFFF) 531 532 #define LTM_BELT_IDLE0 (0x0E0) 533 #define LTM_BELT_IDLE0_IDLE1000_ (0x0FFF0000) 534 #define LTM_BELT_IDLE0_IDLE100_ (0x00000FFF) 535 536 #define LTM_BELT_IDLE1 (0x0E4) 537 #define LTM_BELT_IDLE1_IDLE10_ (0x00000FFF) 538 539 #define LTM_BELT_ACT0 (0x0E8) 540 #define LTM_BELT_ACT0_ACT1000_ (0x0FFF0000) 541 #define LTM_BELT_ACT0_ACT100_ (0x00000FFF) 542 543 #define LTM_BELT_ACT1 (0x0EC) 544 #define LTM_BELT_ACT1_ACT10_ (0x00000FFF) 545 546 #define LTM_INACTIVE0 (0x0F0) 547 #define LTM_INACTIVE0_TIMER1000_ (0xFFFF0000) 548 #define LTM_INACTIVE0_TIMER100_ (0x0000FFFF) 549 550 #define LTM_INACTIVE1 (0x0F4) 551 #define LTM_INACTIVE1_TIMER10_ (0x0000FFFF) 552 553 #define MAC_CR (0x100) 554 #define MAC_CR_GMII_EN_ (0x00080000) 555 #define MAC_CR_EEE_TX_CLK_STOP_EN_ (0x00040000) 556 #define MAC_CR_EEE_EN_ (0x00020000) 557 #define MAC_CR_EEE_TLAR_EN_ (0x00010000) 558 #define MAC_CR_ADP_ (0x00002000) 559 #define MAC_CR_AUTO_DUPLEX_ (0x00001000) 560 #define MAC_CR_AUTO_SPEED_ (0x00000800) 561 #define MAC_CR_LOOPBACK_ (0x00000400) 562 #define MAC_CR_BOLMT_MASK_ (0x000000C0) 563 #define MAC_CR_FULL_DUPLEX_ (0x00000008) 564 #define MAC_CR_SPEED_MASK_ (0x00000006) 565 #define MAC_CR_SPEED_1000_ (0x00000004) 566 #define MAC_CR_SPEED_100_ (0x00000002) 567 #define MAC_CR_SPEED_10_ (0x00000000) 568 #define MAC_CR_RST_ (0x00000001) 569 570 #define MAC_RX (0x104) 571 #define MAC_RX_MAX_SIZE_SHIFT_ (16) 572 #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000) 573 #define MAC_RX_FCS_STRIP_ (0x00000010) 574 #define MAC_RX_VLAN_FSE_ (0x00000004) 575 #define MAC_RX_RXD_ (0x00000002) 576 #define MAC_RX_RXEN_ (0x00000001) 577 578 #define MAC_TX (0x108) 579 #define MAC_TX_BAD_FCS_ (0x00000004) 580 #define MAC_TX_TXD_ (0x00000002) 581 #define MAC_TX_TXEN_ (0x00000001) 582 583 #define FLOW (0x10C) 584 #define FLOW_CR_FORCE_FC_ (0x80000000) 585 #define FLOW_CR_TX_FCEN_ (0x40000000) 586 #define FLOW_CR_RX_FCEN_ (0x20000000) 587 #define FLOW_CR_FPF_ (0x10000000) 588 #define FLOW_CR_FCPT_MASK_ (0x0000FFFF) 589 590 #define RAND_SEED (0x110) 591 #define RAND_SEED_MASK_ (0x0000FFFF) 592 593 #define ERR_STS (0x114) 594 #define ERR_STS_FERR_ (0x00000100) 595 #define ERR_STS_LERR_ (0x00000080) 596 #define ERR_STS_RFERR_ (0x00000040) 597 #define ERR_STS_ECERR_ (0x00000010) 598 #define ERR_STS_ALERR_ (0x00000008) 599 #define ERR_STS_URERR_ (0x00000004) 600 601 #define RX_ADDRH (0x118) 602 #define RX_ADDRH_MASK_ (0x0000FFFF) 603 604 #define RX_ADDRL (0x11C) 605 #define RX_ADDRL_MASK_ (0xFFFFFFFF) 606 607 #define MII_ACC (0x120) 608 #define MII_ACC_PHY_ADDR_SHIFT_ (11) 609 #define MII_ACC_PHY_ADDR_MASK_ (0x0000F800) 610 #define MII_ACC_MIIRINDA_SHIFT_ (6) 611 #define MII_ACC_MIIRINDA_MASK_ (0x000007C0) 612 #define MII_ACC_MII_READ_ (0x00000000) 613 #define MII_ACC_MII_WRITE_ (0x00000002) 614 #define MII_ACC_MII_BUSY_ (0x00000001) 615 616 #define MII_DATA (0x124) 617 #define MII_DATA_MASK_ (0x0000FFFF) 618 619 #define MAC_RGMII_ID (0x128) 620 #define MAC_RGMII_ID_TXC_DELAY_EN_ (0x00000002) 621 #define MAC_RGMII_ID_RXC_DELAY_EN_ (0x00000001) 622 623 #define EEE_TX_LPI_REQ_DLY (0x130) 624 #define EEE_TX_LPI_REQ_DLY_CNT_MASK_ (0xFFFFFFFF) 625 626 #define EEE_TW_TX_SYS (0x134) 627 #define EEE_TW_TX_SYS_CNT1G_MASK_ (0xFFFF0000) 628 #define EEE_TW_TX_SYS_CNT100M_MASK_ (0x0000FFFF) 629 630 #define EEE_TX_LPI_REM_DLY (0x138) 631 #define EEE_TX_LPI_REM_DLY_CNT_ (0x00FFFFFF) 632 633 #define WUCSR (0x140) 634 #define WUCSR_TESTMODE_ (0x80000000) 635 #define WUCSR_RFE_WAKE_EN_ (0x00004000) 636 #define WUCSR_EEE_TX_WAKE_ (0x00002000) 637 #define WUCSR_EEE_TX_WAKE_EN_ (0x00001000) 638 #define WUCSR_EEE_RX_WAKE_ (0x00000800) 639 #define WUCSR_EEE_RX_WAKE_EN_ (0x00000400) 640 #define WUCSR_RFE_WAKE_FR_ (0x00000200) 641 #define WUCSR_STORE_WAKE_ (0x00000100) 642 #define WUCSR_PFDA_FR_ (0x00000080) 643 #define WUCSR_WUFR_ (0x00000040) 644 #define WUCSR_MPR_ (0x00000020) 645 #define WUCSR_BCST_FR_ (0x00000010) 646 #define WUCSR_PFDA_EN_ (0x00000008) 647 #define WUCSR_WAKE_EN_ (0x00000004) 648 #define WUCSR_MPEN_ (0x00000002) 649 #define WUCSR_BCST_EN_ (0x00000001) 650 651 #define WK_SRC (0x144) 652 #define WK_SRC_GPIOX_INT_WK_SHIFT_ (20) 653 #define WK_SRC_GPIOX_INT_WK_MASK_ (0xFFF00000) 654 #define WK_SRC_IPV6_TCPSYN_RCD_WK_ (0x00010000) 655 #define WK_SRC_IPV4_TCPSYN_RCD_WK_ (0x00008000) 656 #define WK_SRC_EEE_TX_WK_ (0x00004000) 657 #define WK_SRC_EEE_RX_WK_ (0x00002000) 658 #define WK_SRC_GOOD_FR_WK_ (0x00001000) 659 #define WK_SRC_PFDA_FR_WK_ (0x00000800) 660 #define WK_SRC_MP_FR_WK_ (0x00000400) 661 #define WK_SRC_BCAST_FR_WK_ (0x00000200) 662 #define WK_SRC_WU_FR_WK_ (0x00000100) 663 #define WK_SRC_WUFF_MATCH_MASK_ (0x0000001F) 664 665 #define WUF_CFG0 (0x150) 666 #define NUM_OF_WUF_CFG (32) 667 #define WUF_CFG_BEGIN (WUF_CFG0) 668 #define WUF_CFG(index) (WUF_CFG_BEGIN + (4 * (index))) 669 #define WUF_CFGX_EN_ (0x80000000) 670 #define WUF_CFGX_TYPE_MASK_ (0x03000000) 671 #define WUF_CFGX_TYPE_MCAST_ (0x02000000) 672 #define WUF_CFGX_TYPE_ALL_ (0x01000000) 673 #define WUF_CFGX_TYPE_UCAST_ (0x00000000) 674 #define WUF_CFGX_OFFSET_SHIFT_ (16) 675 #define WUF_CFGX_OFFSET_MASK_ (0x00FF0000) 676 #define WUF_CFGX_CRC16_MASK_ (0x0000FFFF) 677 678 #define WUF_MASK0_0 (0x200) 679 #define WUF_MASK0_1 (0x204) 680 #define WUF_MASK0_2 (0x208) 681 #define WUF_MASK0_3 (0x20C) 682 #define NUM_OF_WUF_MASK (32) 683 #define WUF_MASK0_BEGIN (WUF_MASK0_0) 684 #define WUF_MASK1_BEGIN (WUF_MASK0_1) 685 #define WUF_MASK2_BEGIN (WUF_MASK0_2) 686 #define WUF_MASK3_BEGIN (WUF_MASK0_3) 687 #define WUF_MASK0(index) (WUF_MASK0_BEGIN + (0x10 * (index))) 688 #define WUF_MASK1(index) (WUF_MASK1_BEGIN + (0x10 * (index))) 689 #define WUF_MASK2(index) (WUF_MASK2_BEGIN + (0x10 * (index))) 690 #define WUF_MASK3(index) (WUF_MASK3_BEGIN + (0x10 * (index))) 691 692 #define MAF_BASE (0x400) 693 #define MAF_HIX (0x00) 694 #define MAF_LOX (0x04) 695 #define NUM_OF_MAF (33) 696 #define MAF_HI_BEGIN (MAF_BASE + MAF_HIX) 697 #define MAF_LO_BEGIN (MAF_BASE + MAF_LOX) 698 #define MAF_HI(index) (MAF_BASE + (8 * (index)) + (MAF_HIX)) 699 #define MAF_LO(index) (MAF_BASE + (8 * (index)) + (MAF_LOX)) 700 #define MAF_HI_VALID_ (0x80000000) 701 #define MAF_HI_TYPE_MASK_ (0x40000000) 702 #define MAF_HI_TYPE_SRC_ (0x40000000) 703 #define MAF_HI_TYPE_DST_ (0x00000000) 704 #define MAF_HI_ADDR_MASK (0x0000FFFF) 705 #define MAF_LO_ADDR_MASK (0xFFFFFFFF) 706 707 #define WUCSR2 (0x600) 708 #define WUCSR2_CSUM_DISABLE_ (0x80000000) 709 #define WUCSR2_NA_SA_SEL_ (0x00000100) 710 #define WUCSR2_NS_RCD_ (0x00000080) 711 #define WUCSR2_ARP_RCD_ (0x00000040) 712 #define WUCSR2_IPV6_TCPSYN_RCD_ (0x00000020) 713 #define WUCSR2_IPV4_TCPSYN_RCD_ (0x00000010) 714 #define WUCSR2_NS_OFFLOAD_EN_ (0x00000008) 715 #define WUCSR2_ARP_OFFLOAD_EN_ (0x00000004) 716 #define WUCSR2_IPV6_TCPSYN_WAKE_EN_ (0x00000002) 717 #define WUCSR2_IPV4_TCPSYN_WAKE_EN_ (0x00000001) 718 719 #define NS1_IPV6_ADDR_DEST0 (0x610) 720 #define NS1_IPV6_ADDR_DEST1 (0x614) 721 #define NS1_IPV6_ADDR_DEST2 (0x618) 722 #define NS1_IPV6_ADDR_DEST3 (0x61C) 723 724 #define NS1_IPV6_ADDR_SRC0 (0x620) 725 #define NS1_IPV6_ADDR_SRC1 (0x624) 726 #define NS1_IPV6_ADDR_SRC2 (0x628) 727 #define NS1_IPV6_ADDR_SRC3 (0x62C) 728 729 #define NS1_ICMPV6_ADDR0_0 (0x630) 730 #define NS1_ICMPV6_ADDR0_1 (0x634) 731 #define NS1_ICMPV6_ADDR0_2 (0x638) 732 #define NS1_ICMPV6_ADDR0_3 (0x63C) 733 734 #define NS1_ICMPV6_ADDR1_0 (0x640) 735 #define NS1_ICMPV6_ADDR1_1 (0x644) 736 #define NS1_ICMPV6_ADDR1_2 (0x648) 737 #define NS1_ICMPV6_ADDR1_3 (0x64C) 738 739 #define NS2_IPV6_ADDR_DEST0 (0x650) 740 #define NS2_IPV6_ADDR_DEST1 (0x654) 741 #define NS2_IPV6_ADDR_DEST2 (0x658) 742 #define NS2_IPV6_ADDR_DEST3 (0x65C) 743 744 #define NS2_IPV6_ADDR_SRC0 (0x660) 745 #define NS2_IPV6_ADDR_SRC1 (0x664) 746 #define NS2_IPV6_ADDR_SRC2 (0x668) 747 #define NS2_IPV6_ADDR_SRC3 (0x66C) 748 749 #define NS2_ICMPV6_ADDR0_0 (0x670) 750 #define NS2_ICMPV6_ADDR0_1 (0x674) 751 #define NS2_ICMPV6_ADDR0_2 (0x678) 752 #define NS2_ICMPV6_ADDR0_3 (0x67C) 753 754 #define NS2_ICMPV6_ADDR1_0 (0x680) 755 #define NS2_ICMPV6_ADDR1_1 (0x684) 756 #define NS2_ICMPV6_ADDR1_2 (0x688) 757 #define NS2_ICMPV6_ADDR1_3 (0x68C) 758 759 #define SYN_IPV4_ADDR_SRC (0x690) 760 #define SYN_IPV4_ADDR_DEST (0x694) 761 #define SYN_IPV4_TCP_PORTS (0x698) 762 #define SYN_IPV4_TCP_PORTS_IPV4_DEST_PORT_SHIFT_ (16) 763 #define SYN_IPV4_TCP_PORTS_IPV4_DEST_PORT_MASK_ (0xFFFF0000) 764 #define SYN_IPV4_TCP_PORTS_IPV4_SRC_PORT_MASK_ (0x0000FFFF) 765 766 #define SYN_IPV6_ADDR_SRC0 (0x69C) 767 #define SYN_IPV6_ADDR_SRC1 (0x6A0) 768 #define SYN_IPV6_ADDR_SRC2 (0x6A4) 769 #define SYN_IPV6_ADDR_SRC3 (0x6A8) 770 771 #define SYN_IPV6_ADDR_DEST0 (0x6AC) 772 #define SYN_IPV6_ADDR_DEST1 (0x6B0) 773 #define SYN_IPV6_ADDR_DEST2 (0x6B4) 774 #define SYN_IPV6_ADDR_DEST3 (0x6B8) 775 776 #define SYN_IPV6_TCP_PORTS (0x6BC) 777 #define SYN_IPV6_TCP_PORTS_IPV6_DEST_PORT_SHIFT_ (16) 778 #define SYN_IPV6_TCP_PORTS_IPV6_DEST_PORT_MASK_ (0xFFFF0000) 779 #define SYN_IPV6_TCP_PORTS_IPV6_SRC_PORT_MASK_ (0x0000FFFF) 780 781 #define ARP_SPA (0x6C0) 782 #define ARP_TPA (0x6C4) 783 784 #define PHY_DEV_ID (0x700) 785 #define PHY_DEV_ID_REV_SHIFT_ (28) 786 #define PHY_DEV_ID_REV_SHIFT_ (28) 787 #define PHY_DEV_ID_REV_MASK_ (0xF0000000) 788 #define PHY_DEV_ID_MODEL_SHIFT_ (22) 789 #define PHY_DEV_ID_MODEL_MASK_ (0x0FC00000) 790 #define PHY_DEV_ID_OUI_MASK_ (0x003FFFFF) 791 792 #define RGMII_TX_BYP_DLL (0x708) 793 #define RGMII_TX_BYP_DLL_TX_TUNE_ADJ_MASK_ (0x000FC00) 794 #define RGMII_TX_BYP_DLL_TX_TUNE_SEL_MASK_ (0x00003F0) 795 #define RGMII_TX_BYP_DLL_TX_DLL_RESET_ (0x0000002) 796 #define RGMII_TX_BYP_DLL_TX_DLL_BYPASS_ (0x0000001) 797 798 #define RGMII_RX_BYP_DLL (0x70C) 799 #define RGMII_RX_BYP_DLL_RX_TUNE_ADJ_MASK_ (0x000FC00) 800 #define RGMII_RX_BYP_DLL_RX_TUNE_SEL_MASK_ (0x00003F0) 801 #define RGMII_RX_BYP_DLL_RX_DLL_RESET_ (0x0000002) 802 #define RGMII_RX_BYP_DLL_RX_DLL_BYPASS_ (0x0000001) 803 804 #define OTP_BASE_ADDR (0x00001000) 805 #define OTP_ADDR_RANGE_ (0x1FF) 806 807 #define OTP_PWR_DN (OTP_BASE_ADDR + 4 * 0x00) 808 #define OTP_PWR_DN_PWRDN_N_ (0x01) 809 810 #define OTP_ADDR1 (OTP_BASE_ADDR + 4 * 0x01) 811 #define OTP_ADDR1_15_11 (0x1F) 812 813 #define OTP_ADDR2 (OTP_BASE_ADDR + 4 * 0x02) 814 #define OTP_ADDR2_10_3 (0xFF) 815 816 #define OTP_ADDR3 (OTP_BASE_ADDR + 4 * 0x03) 817 #define OTP_ADDR3_2_0 (0x03) 818 819 #define OTP_PRGM_DATA (OTP_BASE_ADDR + 4 * 0x04) 820 821 #define OTP_PRGM_MODE (OTP_BASE_ADDR + 4 * 0x05) 822 #define OTP_PRGM_MODE_BYTE_ (0x01) 823 824 #define OTP_RD_DATA (OTP_BASE_ADDR + 4 * 0x06) 825 826 #define OTP_FUNC_CMD (OTP_BASE_ADDR + 4 * 0x08) 827 #define OTP_FUNC_CMD_RESET_ (0x04) 828 #define OTP_FUNC_CMD_PROGRAM_ (0x02) 829 #define OTP_FUNC_CMD_READ_ (0x01) 830 831 #define OTP_TST_CMD (OTP_BASE_ADDR + 4 * 0x09) 832 #define OTP_TST_CMD_TEST_DEC_SEL_ (0x10) 833 #define OTP_TST_CMD_PRGVRFY_ (0x08) 834 #define OTP_TST_CMD_WRTEST_ (0x04) 835 #define OTP_TST_CMD_TESTDEC_ (0x02) 836 #define OTP_TST_CMD_BLANKCHECK_ (0x01) 837 838 #define OTP_CMD_GO (OTP_BASE_ADDR + 4 * 0x0A) 839 #define OTP_CMD_GO_GO_ (0x01) 840 841 #define OTP_PASS_FAIL (OTP_BASE_ADDR + 4 * 0x0B) 842 #define OTP_PASS_FAIL_PASS_ (0x02) 843 #define OTP_PASS_FAIL_FAIL_ (0x01) 844 845 #define OTP_STATUS (OTP_BASE_ADDR + 4 * 0x0C) 846 #define OTP_STATUS_OTP_LOCK_ (0x10) 847 #define OTP_STATUS_WEB_ (0x08) 848 #define OTP_STATUS_PGMEN (0x04) 849 #define OTP_STATUS_CPUMPEN_ (0x02) 850 #define OTP_STATUS_BUSY_ (0x01) 851 852 #define OTP_MAX_PRG (OTP_BASE_ADDR + 4 * 0x0D) 853 #define OTP_MAX_PRG_MAX_PROG (0x1F) 854 855 #define OTP_INTR_STATUS (OTP_BASE_ADDR + 4 * 0x10) 856 #define OTP_INTR_STATUS_READY_ (0x01) 857 858 #define OTP_INTR_MASK (OTP_BASE_ADDR + 4 * 0x11) 859 #define OTP_INTR_MASK_READY_ (0x01) 860 861 #define OTP_RSTB_PW1 (OTP_BASE_ADDR + 4 * 0x14) 862 #define OTP_RSTB_PW2 (OTP_BASE_ADDR + 4 * 0x15) 863 #define OTP_PGM_PW1 (OTP_BASE_ADDR + 4 * 0x18) 864 #define OTP_PGM_PW2 (OTP_BASE_ADDR + 4 * 0x19) 865 #define OTP_READ_PW1 (OTP_BASE_ADDR + 4 * 0x1C) 866 #define OTP_READ_PW2 (OTP_BASE_ADDR + 4 * 0x1D) 867 #define OTP_TCRST (OTP_BASE_ADDR + 4 * 0x20) 868 #define OTP_RSRD (OTP_BASE_ADDR + 4 * 0x21) 869 #define OTP_TREADEN_VAL (OTP_BASE_ADDR + 4 * 0x22) 870 #define OTP_TDLES_VAL (OTP_BASE_ADDR + 4 * 0x23) 871 #define OTP_TWWL_VAL (OTP_BASE_ADDR + 4 * 0x24) 872 #define OTP_TDLEH_VAL (OTP_BASE_ADDR + 4 * 0x25) 873 #define OTP_TWPED_VAL (OTP_BASE_ADDR + 4 * 0x26) 874 #define OTP_TPES_VAL (OTP_BASE_ADDR + 4 * 0x27) 875 #define OTP_TCPS_VAL (OTP_BASE_ADDR + 4 * 0x28) 876 #define OTP_TCPH_VAL (OTP_BASE_ADDR + 4 * 0x29) 877 #define OTP_TPGMVFY_VAL (OTP_BASE_ADDR + 4 * 0x2A) 878 #define OTP_TPEH_VAL (OTP_BASE_ADDR + 4 * 0x2B) 879 #define OTP_TPGRST_VAL (OTP_BASE_ADDR + 4 * 0x2C) 880 #define OTP_TCLES_VAL (OTP_BASE_ADDR + 4 * 0x2D) 881 #define OTP_TCLEH_VAL (OTP_BASE_ADDR + 4 * 0x2E) 882 #define OTP_TRDES_VAL (OTP_BASE_ADDR + 4 * 0x2F) 883 #define OTP_TBCACC_VAL (OTP_BASE_ADDR + 4 * 0x30) 884 #define OTP_TAAC_VAL (OTP_BASE_ADDR + 4 * 0x31) 885 #define OTP_TACCT_VAL (OTP_BASE_ADDR + 4 * 0x32) 886 #define OTP_TRDEP_VAL (OTP_BASE_ADDR + 4 * 0x38) 887 #define OTP_TPGSV_VAL (OTP_BASE_ADDR + 4 * 0x39) 888 #define OTP_TPVSR_VAL (OTP_BASE_ADDR + 4 * 0x3A) 889 #define OTP_TPVHR_VAL (OTP_BASE_ADDR + 4 * 0x3B) 890 #define OTP_TPVSA_VAL (OTP_BASE_ADDR + 4 * 0x3C) 891 #endif /* _LAN78XX_H */ 892