1 /* 2 * ASIX AX88179/178A USB 3.0/2.0 to Gigabit Ethernet Devices 3 * 4 * Copyright (C) 2011-2013 ASIX 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21 #include <linux/module.h> 22 #include <linux/etherdevice.h> 23 #include <linux/mii.h> 24 #include <linux/usb.h> 25 #include <linux/crc32.h> 26 #include <linux/usb/usbnet.h> 27 28 #define AX88179_PHY_ID 0x03 29 #define AX_EEPROM_LEN 0x100 30 #define AX88179_EEPROM_MAGIC 0x17900b95 31 #define AX_MCAST_FLTSIZE 8 32 #define AX_MAX_MCAST 64 33 #define AX_INT_PPLS_LINK ((u32)BIT(16)) 34 #define AX_RXHDR_L4_TYPE_MASK 0x1c 35 #define AX_RXHDR_L4_TYPE_UDP 4 36 #define AX_RXHDR_L4_TYPE_TCP 16 37 #define AX_RXHDR_L3CSUM_ERR 2 38 #define AX_RXHDR_L4CSUM_ERR 1 39 #define AX_RXHDR_CRC_ERR ((u32)BIT(29)) 40 #define AX_RXHDR_DROP_ERR ((u32)BIT(31)) 41 #define AX_ACCESS_MAC 0x01 42 #define AX_ACCESS_PHY 0x02 43 #define AX_ACCESS_EEPROM 0x04 44 #define AX_ACCESS_EFUS 0x05 45 #define AX_PAUSE_WATERLVL_HIGH 0x54 46 #define AX_PAUSE_WATERLVL_LOW 0x55 47 48 #define PHYSICAL_LINK_STATUS 0x02 49 #define AX_USB_SS 0x04 50 #define AX_USB_HS 0x02 51 52 #define GENERAL_STATUS 0x03 53 /* Check AX88179 version. UA1:Bit2 = 0, UA2:Bit2 = 1 */ 54 #define AX_SECLD 0x04 55 56 #define AX_SROM_ADDR 0x07 57 #define AX_SROM_CMD 0x0a 58 #define EEP_RD 0x04 59 #define EEP_BUSY 0x10 60 61 #define AX_SROM_DATA_LOW 0x08 62 #define AX_SROM_DATA_HIGH 0x09 63 64 #define AX_RX_CTL 0x0b 65 #define AX_RX_CTL_DROPCRCERR 0x0100 66 #define AX_RX_CTL_IPE 0x0200 67 #define AX_RX_CTL_START 0x0080 68 #define AX_RX_CTL_AP 0x0020 69 #define AX_RX_CTL_AM 0x0010 70 #define AX_RX_CTL_AB 0x0008 71 #define AX_RX_CTL_AMALL 0x0002 72 #define AX_RX_CTL_PRO 0x0001 73 #define AX_RX_CTL_STOP 0x0000 74 75 #define AX_NODE_ID 0x10 76 #define AX_MULFLTARY 0x16 77 78 #define AX_MEDIUM_STATUS_MODE 0x22 79 #define AX_MEDIUM_GIGAMODE 0x01 80 #define AX_MEDIUM_FULL_DUPLEX 0x02 81 #define AX_MEDIUM_ALWAYS_ONE 0x04 82 #define AX_MEDIUM_EN_125MHZ 0x08 83 #define AX_MEDIUM_RXFLOW_CTRLEN 0x10 84 #define AX_MEDIUM_TXFLOW_CTRLEN 0x20 85 #define AX_MEDIUM_RECEIVE_EN 0x100 86 #define AX_MEDIUM_PS 0x200 87 #define AX_MEDIUM_JUMBO_EN 0x8040 88 89 #define AX_MONITOR_MOD 0x24 90 #define AX_MONITOR_MODE_RWLC 0x02 91 #define AX_MONITOR_MODE_RWMP 0x04 92 #define AX_MONITOR_MODE_PMEPOL 0x20 93 #define AX_MONITOR_MODE_PMETYPE 0x40 94 95 #define AX_GPIO_CTRL 0x25 96 #define AX_GPIO_CTRL_GPIO3EN 0x80 97 #define AX_GPIO_CTRL_GPIO2EN 0x40 98 #define AX_GPIO_CTRL_GPIO1EN 0x20 99 100 #define AX_PHYPWR_RSTCTL 0x26 101 #define AX_PHYPWR_RSTCTL_BZ 0x0010 102 #define AX_PHYPWR_RSTCTL_IPRL 0x0020 103 #define AX_PHYPWR_RSTCTL_AT 0x1000 104 105 #define AX_RX_BULKIN_QCTRL 0x2e 106 #define AX_CLK_SELECT 0x33 107 #define AX_CLK_SELECT_BCS 0x01 108 #define AX_CLK_SELECT_ACS 0x02 109 #define AX_CLK_SELECT_ULR 0x08 110 111 #define AX_RXCOE_CTL 0x34 112 #define AX_RXCOE_IP 0x01 113 #define AX_RXCOE_TCP 0x02 114 #define AX_RXCOE_UDP 0x04 115 #define AX_RXCOE_TCPV6 0x20 116 #define AX_RXCOE_UDPV6 0x40 117 118 #define AX_TXCOE_CTL 0x35 119 #define AX_TXCOE_IP 0x01 120 #define AX_TXCOE_TCP 0x02 121 #define AX_TXCOE_UDP 0x04 122 #define AX_TXCOE_TCPV6 0x20 123 #define AX_TXCOE_UDPV6 0x40 124 125 #define AX_LEDCTRL 0x73 126 127 #define GMII_PHY_PHYSR 0x11 128 #define GMII_PHY_PHYSR_SMASK 0xc000 129 #define GMII_PHY_PHYSR_GIGA 0x8000 130 #define GMII_PHY_PHYSR_100 0x4000 131 #define GMII_PHY_PHYSR_FULL 0x2000 132 #define GMII_PHY_PHYSR_LINK 0x400 133 134 #define GMII_LED_ACT 0x1a 135 #define GMII_LED_ACTIVE_MASK 0xff8f 136 #define GMII_LED0_ACTIVE BIT(4) 137 #define GMII_LED1_ACTIVE BIT(5) 138 #define GMII_LED2_ACTIVE BIT(6) 139 140 #define GMII_LED_LINK 0x1c 141 #define GMII_LED_LINK_MASK 0xf888 142 #define GMII_LED0_LINK_10 BIT(0) 143 #define GMII_LED0_LINK_100 BIT(1) 144 #define GMII_LED0_LINK_1000 BIT(2) 145 #define GMII_LED1_LINK_10 BIT(4) 146 #define GMII_LED1_LINK_100 BIT(5) 147 #define GMII_LED1_LINK_1000 BIT(6) 148 #define GMII_LED2_LINK_10 BIT(8) 149 #define GMII_LED2_LINK_100 BIT(9) 150 #define GMII_LED2_LINK_1000 BIT(10) 151 #define LED0_ACTIVE BIT(0) 152 #define LED0_LINK_10 BIT(1) 153 #define LED0_LINK_100 BIT(2) 154 #define LED0_LINK_1000 BIT(3) 155 #define LED0_FD BIT(4) 156 #define LED0_USB3_MASK 0x001f 157 #define LED1_ACTIVE BIT(5) 158 #define LED1_LINK_10 BIT(6) 159 #define LED1_LINK_100 BIT(7) 160 #define LED1_LINK_1000 BIT(8) 161 #define LED1_FD BIT(9) 162 #define LED1_USB3_MASK 0x03e0 163 #define LED2_ACTIVE BIT(10) 164 #define LED2_LINK_1000 BIT(13) 165 #define LED2_LINK_100 BIT(12) 166 #define LED2_LINK_10 BIT(11) 167 #define LED2_FD BIT(14) 168 #define LED_VALID BIT(15) 169 #define LED2_USB3_MASK 0x7c00 170 171 #define GMII_PHYPAGE 0x1e 172 #define GMII_PHY_PAGE_SELECT 0x1f 173 #define GMII_PHY_PGSEL_EXT 0x0007 174 #define GMII_PHY_PGSEL_PAGE0 0x0000 175 176 struct ax88179_data { 177 u16 rxctl; 178 u16 reserved; 179 }; 180 181 struct ax88179_int_data { 182 __le32 intdata1; 183 __le32 intdata2; 184 }; 185 186 static const struct { 187 unsigned char ctrl, timer_l, timer_h, size, ifg; 188 } AX88179_BULKIN_SIZE[] = { 189 {7, 0x4f, 0, 0x12, 0xff}, 190 {7, 0x20, 3, 0x16, 0xff}, 191 {7, 0xae, 7, 0x18, 0xff}, 192 {7, 0xcc, 0x4c, 0x18, 8}, 193 }; 194 195 static int __ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 196 u16 size, void *data, int in_pm) 197 { 198 int ret; 199 int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16); 200 201 BUG_ON(!dev); 202 203 if (!in_pm) 204 fn = usbnet_read_cmd; 205 else 206 fn = usbnet_read_cmd_nopm; 207 208 ret = fn(dev, cmd, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 209 value, index, data, size); 210 211 if (unlikely(ret < 0)) 212 netdev_warn(dev->net, "Failed to read reg index 0x%04x: %d\n", 213 index, ret); 214 215 return ret; 216 } 217 218 static int __ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 219 u16 size, void *data, int in_pm) 220 { 221 int ret; 222 int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16); 223 224 BUG_ON(!dev); 225 226 if (!in_pm) 227 fn = usbnet_write_cmd; 228 else 229 fn = usbnet_write_cmd_nopm; 230 231 ret = fn(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 232 value, index, data, size); 233 234 if (unlikely(ret < 0)) 235 netdev_warn(dev->net, "Failed to write reg index 0x%04x: %d\n", 236 index, ret); 237 238 return ret; 239 } 240 241 static void ax88179_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, 242 u16 index, u16 size, void *data) 243 { 244 u16 buf; 245 246 if (2 == size) { 247 buf = *((u16 *)data); 248 cpu_to_le16s(&buf); 249 usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | 250 USB_RECIP_DEVICE, value, index, &buf, 251 size); 252 } else { 253 usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | 254 USB_RECIP_DEVICE, value, index, data, 255 size); 256 } 257 } 258 259 static int ax88179_read_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value, 260 u16 index, u16 size, void *data) 261 { 262 int ret; 263 264 if (2 == size) { 265 u16 buf; 266 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1); 267 le16_to_cpus(&buf); 268 *((u16 *)data) = buf; 269 } else if (4 == size) { 270 u32 buf; 271 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1); 272 le32_to_cpus(&buf); 273 *((u32 *)data) = buf; 274 } else { 275 ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 1); 276 } 277 278 return ret; 279 } 280 281 static int ax88179_write_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value, 282 u16 index, u16 size, void *data) 283 { 284 int ret; 285 286 if (2 == size) { 287 u16 buf; 288 buf = *((u16 *)data); 289 cpu_to_le16s(&buf); 290 ret = __ax88179_write_cmd(dev, cmd, value, index, 291 size, &buf, 1); 292 } else { 293 ret = __ax88179_write_cmd(dev, cmd, value, index, 294 size, data, 1); 295 } 296 297 return ret; 298 } 299 300 static int ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 301 u16 size, void *data) 302 { 303 int ret; 304 305 if (2 == size) { 306 u16 buf; 307 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0); 308 le16_to_cpus(&buf); 309 *((u16 *)data) = buf; 310 } else if (4 == size) { 311 u32 buf; 312 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0); 313 le32_to_cpus(&buf); 314 *((u32 *)data) = buf; 315 } else { 316 ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 0); 317 } 318 319 return ret; 320 } 321 322 static int ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 323 u16 size, void *data) 324 { 325 int ret; 326 327 if (2 == size) { 328 u16 buf; 329 buf = *((u16 *)data); 330 cpu_to_le16s(&buf); 331 ret = __ax88179_write_cmd(dev, cmd, value, index, 332 size, &buf, 0); 333 } else { 334 ret = __ax88179_write_cmd(dev, cmd, value, index, 335 size, data, 0); 336 } 337 338 return ret; 339 } 340 341 static void ax88179_status(struct usbnet *dev, struct urb *urb) 342 { 343 struct ax88179_int_data *event; 344 u32 link; 345 346 if (urb->actual_length < 8) 347 return; 348 349 event = urb->transfer_buffer; 350 le32_to_cpus((void *)&event->intdata1); 351 352 link = (((__force u32)event->intdata1) & AX_INT_PPLS_LINK) >> 16; 353 354 if (netif_carrier_ok(dev->net) != link) { 355 usbnet_link_change(dev, link, 1); 356 netdev_info(dev->net, "ax88179 - Link status is: %d\n", link); 357 } 358 } 359 360 static int ax88179_mdio_read(struct net_device *netdev, int phy_id, int loc) 361 { 362 struct usbnet *dev = netdev_priv(netdev); 363 u16 res; 364 365 ax88179_read_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res); 366 return res; 367 } 368 369 static void ax88179_mdio_write(struct net_device *netdev, int phy_id, int loc, 370 int val) 371 { 372 struct usbnet *dev = netdev_priv(netdev); 373 u16 res = (u16) val; 374 375 ax88179_write_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res); 376 } 377 378 static int ax88179_suspend(struct usb_interface *intf, pm_message_t message) 379 { 380 struct usbnet *dev = usb_get_intfdata(intf); 381 u16 tmp16; 382 u8 tmp8; 383 384 usbnet_suspend(intf, message); 385 386 /* Disable RX path */ 387 ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 388 2, 2, &tmp16); 389 tmp16 &= ~AX_MEDIUM_RECEIVE_EN; 390 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 391 2, 2, &tmp16); 392 393 /* Force bulk-in zero length */ 394 ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 395 2, 2, &tmp16); 396 397 tmp16 |= AX_PHYPWR_RSTCTL_BZ | AX_PHYPWR_RSTCTL_IPRL; 398 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 399 2, 2, &tmp16); 400 401 /* change clock */ 402 tmp8 = 0; 403 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 404 405 /* Configure RX control register => stop operation */ 406 tmp16 = AX_RX_CTL_STOP; 407 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16); 408 409 return 0; 410 } 411 412 /* This function is used to enable the autodetach function. */ 413 /* This function is determined by offset 0x43 of EEPROM */ 414 static int ax88179_auto_detach(struct usbnet *dev, int in_pm) 415 { 416 u16 tmp16; 417 u8 tmp8; 418 int (*fnr)(struct usbnet *, u8, u16, u16, u16, void *); 419 int (*fnw)(struct usbnet *, u8, u16, u16, u16, void *); 420 421 if (!in_pm) { 422 fnr = ax88179_read_cmd; 423 fnw = ax88179_write_cmd; 424 } else { 425 fnr = ax88179_read_cmd_nopm; 426 fnw = ax88179_write_cmd_nopm; 427 } 428 429 if (fnr(dev, AX_ACCESS_EEPROM, 0x43, 1, 2, &tmp16) < 0) 430 return 0; 431 432 if ((tmp16 == 0xFFFF) || (!(tmp16 & 0x0100))) 433 return 0; 434 435 /* Enable Auto Detach bit */ 436 tmp8 = 0; 437 fnr(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 438 tmp8 |= AX_CLK_SELECT_ULR; 439 fnw(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 440 441 fnr(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16); 442 tmp16 |= AX_PHYPWR_RSTCTL_AT; 443 fnw(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16); 444 445 return 0; 446 } 447 448 static int ax88179_resume(struct usb_interface *intf) 449 { 450 struct usbnet *dev = usb_get_intfdata(intf); 451 u16 tmp16; 452 u8 tmp8; 453 454 usbnet_link_change(dev, 0, 0); 455 456 /* Power up ethernet PHY */ 457 tmp16 = 0; 458 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 459 2, 2, &tmp16); 460 udelay(1000); 461 462 tmp16 = AX_PHYPWR_RSTCTL_IPRL; 463 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 464 2, 2, &tmp16); 465 msleep(200); 466 467 /* Ethernet PHY Auto Detach*/ 468 ax88179_auto_detach(dev, 1); 469 470 /* Enable clock */ 471 ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 472 tmp8 |= AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 473 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 474 msleep(100); 475 476 /* Configure RX control register => start operation */ 477 tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 478 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 479 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16); 480 481 return usbnet_resume(intf); 482 } 483 484 static void 485 ax88179_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) 486 { 487 struct usbnet *dev = netdev_priv(net); 488 u8 opt; 489 490 if (ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 491 1, 1, &opt) < 0) { 492 wolinfo->supported = 0; 493 wolinfo->wolopts = 0; 494 return; 495 } 496 497 wolinfo->supported = WAKE_PHY | WAKE_MAGIC; 498 wolinfo->wolopts = 0; 499 if (opt & AX_MONITOR_MODE_RWLC) 500 wolinfo->wolopts |= WAKE_PHY; 501 if (opt & AX_MONITOR_MODE_RWMP) 502 wolinfo->wolopts |= WAKE_MAGIC; 503 } 504 505 static int 506 ax88179_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) 507 { 508 struct usbnet *dev = netdev_priv(net); 509 u8 opt = 0; 510 511 if (wolinfo->wolopts & WAKE_PHY) 512 opt |= AX_MONITOR_MODE_RWLC; 513 if (wolinfo->wolopts & WAKE_MAGIC) 514 opt |= AX_MONITOR_MODE_RWMP; 515 516 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 517 1, 1, &opt) < 0) 518 return -EINVAL; 519 520 return 0; 521 } 522 523 static int ax88179_get_eeprom_len(struct net_device *net) 524 { 525 return AX_EEPROM_LEN; 526 } 527 528 static int 529 ax88179_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom, 530 u8 *data) 531 { 532 struct usbnet *dev = netdev_priv(net); 533 u16 *eeprom_buff; 534 int first_word, last_word; 535 int i, ret; 536 537 if (eeprom->len == 0) 538 return -EINVAL; 539 540 eeprom->magic = AX88179_EEPROM_MAGIC; 541 542 first_word = eeprom->offset >> 1; 543 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 544 eeprom_buff = kmalloc(sizeof(u16) * (last_word - first_word + 1), 545 GFP_KERNEL); 546 if (!eeprom_buff) 547 return -ENOMEM; 548 549 /* ax88179/178A returns 2 bytes from eeprom on read */ 550 for (i = first_word; i <= last_word; i++) { 551 ret = __ax88179_read_cmd(dev, AX_ACCESS_EEPROM, i, 1, 2, 552 &eeprom_buff[i - first_word], 553 0); 554 if (ret < 0) { 555 kfree(eeprom_buff); 556 return -EIO; 557 } 558 } 559 560 memcpy(data, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); 561 kfree(eeprom_buff); 562 return 0; 563 } 564 565 static int ax88179_get_settings(struct net_device *net, struct ethtool_cmd *cmd) 566 { 567 struct usbnet *dev = netdev_priv(net); 568 return mii_ethtool_gset(&dev->mii, cmd); 569 } 570 571 static int ax88179_set_settings(struct net_device *net, struct ethtool_cmd *cmd) 572 { 573 struct usbnet *dev = netdev_priv(net); 574 return mii_ethtool_sset(&dev->mii, cmd); 575 } 576 577 578 static int ax88179_ioctl(struct net_device *net, struct ifreq *rq, int cmd) 579 { 580 struct usbnet *dev = netdev_priv(net); 581 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); 582 } 583 584 static const struct ethtool_ops ax88179_ethtool_ops = { 585 .get_link = ethtool_op_get_link, 586 .get_msglevel = usbnet_get_msglevel, 587 .set_msglevel = usbnet_set_msglevel, 588 .get_wol = ax88179_get_wol, 589 .set_wol = ax88179_set_wol, 590 .get_eeprom_len = ax88179_get_eeprom_len, 591 .get_eeprom = ax88179_get_eeprom, 592 .get_settings = ax88179_get_settings, 593 .set_settings = ax88179_set_settings, 594 .nway_reset = usbnet_nway_reset, 595 }; 596 597 static void ax88179_set_multicast(struct net_device *net) 598 { 599 struct usbnet *dev = netdev_priv(net); 600 struct ax88179_data *data = (struct ax88179_data *)dev->data; 601 u8 *m_filter = ((u8 *)dev->data) + 12; 602 603 data->rxctl = (AX_RX_CTL_START | AX_RX_CTL_AB | AX_RX_CTL_IPE); 604 605 if (net->flags & IFF_PROMISC) { 606 data->rxctl |= AX_RX_CTL_PRO; 607 } else if (net->flags & IFF_ALLMULTI || 608 netdev_mc_count(net) > AX_MAX_MCAST) { 609 data->rxctl |= AX_RX_CTL_AMALL; 610 } else if (netdev_mc_empty(net)) { 611 /* just broadcast and directed */ 612 } else { 613 /* We use the 20 byte dev->data for our 8 byte filter buffer 614 * to avoid allocating memory that is tricky to free later 615 */ 616 u32 crc_bits; 617 struct netdev_hw_addr *ha; 618 619 memset(m_filter, 0, AX_MCAST_FLTSIZE); 620 621 netdev_for_each_mc_addr(ha, net) { 622 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; 623 *(m_filter + (crc_bits >> 3)) |= (1 << (crc_bits & 7)); 624 } 625 626 ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_MULFLTARY, 627 AX_MCAST_FLTSIZE, AX_MCAST_FLTSIZE, 628 m_filter); 629 630 data->rxctl |= AX_RX_CTL_AM; 631 } 632 633 ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_RX_CTL, 634 2, 2, &data->rxctl); 635 } 636 637 static int 638 ax88179_set_features(struct net_device *net, netdev_features_t features) 639 { 640 u8 tmp; 641 struct usbnet *dev = netdev_priv(net); 642 netdev_features_t changed = net->features ^ features; 643 644 if (changed & NETIF_F_IP_CSUM) { 645 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 646 tmp ^= AX_TXCOE_TCP | AX_TXCOE_UDP; 647 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 648 } 649 650 if (changed & NETIF_F_IPV6_CSUM) { 651 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 652 tmp ^= AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 653 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 654 } 655 656 if (changed & NETIF_F_RXCSUM) { 657 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp); 658 tmp ^= AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 659 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 660 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp); 661 } 662 663 return 0; 664 } 665 666 static int ax88179_change_mtu(struct net_device *net, int new_mtu) 667 { 668 struct usbnet *dev = netdev_priv(net); 669 u16 tmp16; 670 671 if (new_mtu <= 0 || new_mtu > 4088) 672 return -EINVAL; 673 674 net->mtu = new_mtu; 675 dev->hard_mtu = net->mtu + net->hard_header_len; 676 677 if (net->mtu > 1500) { 678 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 679 2, 2, &tmp16); 680 tmp16 |= AX_MEDIUM_JUMBO_EN; 681 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 682 2, 2, &tmp16); 683 } else { 684 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 685 2, 2, &tmp16); 686 tmp16 &= ~AX_MEDIUM_JUMBO_EN; 687 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 688 2, 2, &tmp16); 689 } 690 691 /* max qlen depend on hard_mtu and rx_urb_size */ 692 usbnet_update_max_qlen(dev); 693 694 return 0; 695 } 696 697 static int ax88179_set_mac_addr(struct net_device *net, void *p) 698 { 699 struct usbnet *dev = netdev_priv(net); 700 struct sockaddr *addr = p; 701 702 if (netif_running(net)) 703 return -EBUSY; 704 if (!is_valid_ether_addr(addr->sa_data)) 705 return -EADDRNOTAVAIL; 706 707 memcpy(net->dev_addr, addr->sa_data, ETH_ALEN); 708 709 /* Set the MAC address */ 710 return ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, 711 ETH_ALEN, net->dev_addr); 712 } 713 714 static const struct net_device_ops ax88179_netdev_ops = { 715 .ndo_open = usbnet_open, 716 .ndo_stop = usbnet_stop, 717 .ndo_start_xmit = usbnet_start_xmit, 718 .ndo_tx_timeout = usbnet_tx_timeout, 719 .ndo_change_mtu = ax88179_change_mtu, 720 .ndo_set_mac_address = ax88179_set_mac_addr, 721 .ndo_validate_addr = eth_validate_addr, 722 .ndo_do_ioctl = ax88179_ioctl, 723 .ndo_set_rx_mode = ax88179_set_multicast, 724 .ndo_set_features = ax88179_set_features, 725 }; 726 727 static int ax88179_check_eeprom(struct usbnet *dev) 728 { 729 u8 i, buf, eeprom[20]; 730 u16 csum, delay = HZ / 10; 731 unsigned long jtimeout; 732 733 /* Read EEPROM content */ 734 for (i = 0; i < 6; i++) { 735 buf = i; 736 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR, 737 1, 1, &buf) < 0) 738 return -EINVAL; 739 740 buf = EEP_RD; 741 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 742 1, 1, &buf) < 0) 743 return -EINVAL; 744 745 jtimeout = jiffies + delay; 746 do { 747 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 748 1, 1, &buf); 749 750 if (time_after(jiffies, jtimeout)) 751 return -EINVAL; 752 753 } while (buf & EEP_BUSY); 754 755 __ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW, 756 2, 2, &eeprom[i * 2], 0); 757 758 if ((i == 0) && (eeprom[0] == 0xFF)) 759 return -EINVAL; 760 } 761 762 csum = eeprom[6] + eeprom[7] + eeprom[8] + eeprom[9]; 763 csum = (csum >> 8) + (csum & 0xff); 764 if ((csum + eeprom[10]) != 0xff) 765 return -EINVAL; 766 767 return 0; 768 } 769 770 static int ax88179_check_efuse(struct usbnet *dev, u16 *ledmode) 771 { 772 u8 i; 773 u8 efuse[64]; 774 u16 csum = 0; 775 776 if (ax88179_read_cmd(dev, AX_ACCESS_EFUS, 0, 64, 64, efuse) < 0) 777 return -EINVAL; 778 779 if (*efuse == 0xFF) 780 return -EINVAL; 781 782 for (i = 0; i < 64; i++) 783 csum = csum + efuse[i]; 784 785 while (csum > 255) 786 csum = (csum & 0x00FF) + ((csum >> 8) & 0x00FF); 787 788 if (csum != 0xFF) 789 return -EINVAL; 790 791 *ledmode = (efuse[51] << 8) | efuse[52]; 792 793 return 0; 794 } 795 796 static int ax88179_convert_old_led(struct usbnet *dev, u16 *ledvalue) 797 { 798 u16 led; 799 800 /* Loaded the old eFuse LED Mode */ 801 if (ax88179_read_cmd(dev, AX_ACCESS_EEPROM, 0x3C, 1, 2, &led) < 0) 802 return -EINVAL; 803 804 led >>= 8; 805 switch (led) { 806 case 0xFF: 807 led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 | 808 LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 | 809 LED2_LINK_100 | LED2_LINK_1000 | LED_VALID; 810 break; 811 case 0xFE: 812 led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 | LED_VALID; 813 break; 814 case 0xFD: 815 led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 | 816 LED2_LINK_10 | LED_VALID; 817 break; 818 case 0xFC: 819 led = LED0_ACTIVE | LED1_ACTIVE | LED1_LINK_1000 | LED2_ACTIVE | 820 LED2_LINK_100 | LED2_LINK_10 | LED_VALID; 821 break; 822 default: 823 led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 | 824 LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 | 825 LED2_LINK_100 | LED2_LINK_1000 | LED_VALID; 826 break; 827 } 828 829 *ledvalue = led; 830 831 return 0; 832 } 833 834 static int ax88179_led_setting(struct usbnet *dev) 835 { 836 u8 ledfd, value = 0; 837 u16 tmp, ledact, ledlink, ledvalue = 0, delay = HZ / 10; 838 unsigned long jtimeout; 839 840 /* Check AX88179 version. UA1 or UA2*/ 841 ax88179_read_cmd(dev, AX_ACCESS_MAC, GENERAL_STATUS, 1, 1, &value); 842 843 if (!(value & AX_SECLD)) { /* UA1 */ 844 value = AX_GPIO_CTRL_GPIO3EN | AX_GPIO_CTRL_GPIO2EN | 845 AX_GPIO_CTRL_GPIO1EN; 846 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_GPIO_CTRL, 847 1, 1, &value) < 0) 848 return -EINVAL; 849 } 850 851 /* Check EEPROM */ 852 if (!ax88179_check_eeprom(dev)) { 853 value = 0x42; 854 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR, 855 1, 1, &value) < 0) 856 return -EINVAL; 857 858 value = EEP_RD; 859 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 860 1, 1, &value) < 0) 861 return -EINVAL; 862 863 jtimeout = jiffies + delay; 864 do { 865 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 866 1, 1, &value); 867 868 if (time_after(jiffies, jtimeout)) 869 return -EINVAL; 870 871 } while (value & EEP_BUSY); 872 873 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_HIGH, 874 1, 1, &value); 875 ledvalue = (value << 8); 876 877 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW, 878 1, 1, &value); 879 ledvalue |= value; 880 881 /* load internal ROM for defaule setting */ 882 if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0)) 883 ax88179_convert_old_led(dev, &ledvalue); 884 885 } else if (!ax88179_check_efuse(dev, &ledvalue)) { 886 if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0)) 887 ax88179_convert_old_led(dev, &ledvalue); 888 } else { 889 ax88179_convert_old_led(dev, &ledvalue); 890 } 891 892 tmp = GMII_PHY_PGSEL_EXT; 893 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 894 GMII_PHY_PAGE_SELECT, 2, &tmp); 895 896 tmp = 0x2c; 897 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 898 GMII_PHYPAGE, 2, &tmp); 899 900 ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 901 GMII_LED_ACT, 2, &ledact); 902 903 ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 904 GMII_LED_LINK, 2, &ledlink); 905 906 ledact &= GMII_LED_ACTIVE_MASK; 907 ledlink &= GMII_LED_LINK_MASK; 908 909 if (ledvalue & LED0_ACTIVE) 910 ledact |= GMII_LED0_ACTIVE; 911 912 if (ledvalue & LED1_ACTIVE) 913 ledact |= GMII_LED1_ACTIVE; 914 915 if (ledvalue & LED2_ACTIVE) 916 ledact |= GMII_LED2_ACTIVE; 917 918 if (ledvalue & LED0_LINK_10) 919 ledlink |= GMII_LED0_LINK_10; 920 921 if (ledvalue & LED1_LINK_10) 922 ledlink |= GMII_LED1_LINK_10; 923 924 if (ledvalue & LED2_LINK_10) 925 ledlink |= GMII_LED2_LINK_10; 926 927 if (ledvalue & LED0_LINK_100) 928 ledlink |= GMII_LED0_LINK_100; 929 930 if (ledvalue & LED1_LINK_100) 931 ledlink |= GMII_LED1_LINK_100; 932 933 if (ledvalue & LED2_LINK_100) 934 ledlink |= GMII_LED2_LINK_100; 935 936 if (ledvalue & LED0_LINK_1000) 937 ledlink |= GMII_LED0_LINK_1000; 938 939 if (ledvalue & LED1_LINK_1000) 940 ledlink |= GMII_LED1_LINK_1000; 941 942 if (ledvalue & LED2_LINK_1000) 943 ledlink |= GMII_LED2_LINK_1000; 944 945 tmp = ledact; 946 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 947 GMII_LED_ACT, 2, &tmp); 948 949 tmp = ledlink; 950 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 951 GMII_LED_LINK, 2, &tmp); 952 953 tmp = GMII_PHY_PGSEL_PAGE0; 954 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 955 GMII_PHY_PAGE_SELECT, 2, &tmp); 956 957 /* LED full duplex setting */ 958 ledfd = 0; 959 if (ledvalue & LED0_FD) 960 ledfd |= 0x01; 961 else if ((ledvalue & LED0_USB3_MASK) == 0) 962 ledfd |= 0x02; 963 964 if (ledvalue & LED1_FD) 965 ledfd |= 0x04; 966 else if ((ledvalue & LED1_USB3_MASK) == 0) 967 ledfd |= 0x08; 968 969 if (ledvalue & LED2_FD) 970 ledfd |= 0x10; 971 else if ((ledvalue & LED2_USB3_MASK) == 0) 972 ledfd |= 0x20; 973 974 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_LEDCTRL, 1, 1, &ledfd); 975 976 return 0; 977 } 978 979 static int ax88179_bind(struct usbnet *dev, struct usb_interface *intf) 980 { 981 u8 buf[5]; 982 u16 *tmp16; 983 u8 *tmp; 984 struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data; 985 986 usbnet_get_endpoints(dev, intf); 987 988 tmp16 = (u16 *)buf; 989 tmp = (u8 *)buf; 990 991 memset(ax179_data, 0, sizeof(*ax179_data)); 992 993 /* Power up ethernet PHY */ 994 *tmp16 = 0; 995 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 996 *tmp16 = AX_PHYPWR_RSTCTL_IPRL; 997 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 998 msleep(200); 999 1000 *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 1001 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); 1002 msleep(100); 1003 1004 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, 1005 ETH_ALEN, dev->net->dev_addr); 1006 memcpy(dev->net->perm_addr, dev->net->dev_addr, ETH_ALEN); 1007 1008 /* RX bulk configuration */ 1009 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 1010 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 1011 1012 dev->rx_urb_size = 1024 * 20; 1013 1014 *tmp = 0x34; 1015 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); 1016 1017 *tmp = 0x52; 1018 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1019 1, 1, tmp); 1020 1021 dev->net->netdev_ops = &ax88179_netdev_ops; 1022 dev->net->ethtool_ops = &ax88179_ethtool_ops; 1023 dev->net->needed_headroom = 8; 1024 1025 /* Initialize MII structure */ 1026 dev->mii.dev = dev->net; 1027 dev->mii.mdio_read = ax88179_mdio_read; 1028 dev->mii.mdio_write = ax88179_mdio_write; 1029 dev->mii.phy_id_mask = 0xff; 1030 dev->mii.reg_num_mask = 0xff; 1031 dev->mii.phy_id = 0x03; 1032 dev->mii.supports_gmii = 1; 1033 1034 if (usb_device_no_sg_constraint(dev->udev)) 1035 dev->can_dma_sg = 1; 1036 1037 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1038 NETIF_F_RXCSUM; 1039 1040 dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1041 NETIF_F_RXCSUM; 1042 1043 if (dev->can_dma_sg) { 1044 dev->net->features |= NETIF_F_SG | NETIF_F_TSO; 1045 dev->net->hw_features |= NETIF_F_SG | NETIF_F_TSO; 1046 } 1047 1048 /* Enable checksum offload */ 1049 *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 1050 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 1051 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); 1052 1053 *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | 1054 AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 1055 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); 1056 1057 /* Configure RX control register => start operation */ 1058 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 1059 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 1060 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); 1061 1062 *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | 1063 AX_MONITOR_MODE_RWMP; 1064 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); 1065 1066 /* Configure default medium type => giga */ 1067 *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 1068 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_ALWAYS_ONE | 1069 AX_MEDIUM_FULL_DUPLEX | AX_MEDIUM_GIGAMODE; 1070 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1071 2, 2, tmp16); 1072 1073 ax88179_led_setting(dev); 1074 1075 /* Restart autoneg */ 1076 mii_nway_restart(&dev->mii); 1077 1078 usbnet_link_change(dev, 0, 0); 1079 1080 return 0; 1081 } 1082 1083 static void ax88179_unbind(struct usbnet *dev, struct usb_interface *intf) 1084 { 1085 u16 tmp16; 1086 1087 /* Configure RX control register => stop operation */ 1088 tmp16 = AX_RX_CTL_STOP; 1089 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16); 1090 1091 tmp16 = 0; 1092 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp16); 1093 1094 /* Power down ethernet PHY */ 1095 tmp16 = 0; 1096 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16); 1097 } 1098 1099 static void 1100 ax88179_rx_checksum(struct sk_buff *skb, u32 *pkt_hdr) 1101 { 1102 skb->ip_summed = CHECKSUM_NONE; 1103 1104 /* checksum error bit is set */ 1105 if ((*pkt_hdr & AX_RXHDR_L3CSUM_ERR) || 1106 (*pkt_hdr & AX_RXHDR_L4CSUM_ERR)) 1107 return; 1108 1109 /* It must be a TCP or UDP packet with a valid checksum */ 1110 if (((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_TCP) || 1111 ((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_UDP)) 1112 skb->ip_summed = CHECKSUM_UNNECESSARY; 1113 } 1114 1115 static int ax88179_rx_fixup(struct usbnet *dev, struct sk_buff *skb) 1116 { 1117 struct sk_buff *ax_skb; 1118 int pkt_cnt; 1119 u32 rx_hdr; 1120 u16 hdr_off; 1121 u32 *pkt_hdr; 1122 1123 skb_trim(skb, skb->len - 4); 1124 memcpy(&rx_hdr, skb_tail_pointer(skb), 4); 1125 le32_to_cpus(&rx_hdr); 1126 1127 pkt_cnt = (u16)rx_hdr; 1128 hdr_off = (u16)(rx_hdr >> 16); 1129 pkt_hdr = (u32 *)(skb->data + hdr_off); 1130 1131 while (pkt_cnt--) { 1132 u16 pkt_len; 1133 1134 le32_to_cpus(pkt_hdr); 1135 pkt_len = (*pkt_hdr >> 16) & 0x1fff; 1136 1137 /* Check CRC or runt packet */ 1138 if ((*pkt_hdr & AX_RXHDR_CRC_ERR) || 1139 (*pkt_hdr & AX_RXHDR_DROP_ERR)) { 1140 skb_pull(skb, (pkt_len + 7) & 0xFFF8); 1141 pkt_hdr++; 1142 continue; 1143 } 1144 1145 if (pkt_cnt == 0) { 1146 /* Skip IP alignment psudo header */ 1147 skb_pull(skb, 2); 1148 skb->len = pkt_len; 1149 skb_set_tail_pointer(skb, pkt_len); 1150 skb->truesize = pkt_len + sizeof(struct sk_buff); 1151 ax88179_rx_checksum(skb, pkt_hdr); 1152 return 1; 1153 } 1154 1155 ax_skb = skb_clone(skb, GFP_ATOMIC); 1156 if (ax_skb) { 1157 ax_skb->len = pkt_len; 1158 ax_skb->data = skb->data + 2; 1159 skb_set_tail_pointer(ax_skb, pkt_len); 1160 ax_skb->truesize = pkt_len + sizeof(struct sk_buff); 1161 ax88179_rx_checksum(ax_skb, pkt_hdr); 1162 usbnet_skb_return(dev, ax_skb); 1163 } else { 1164 return 0; 1165 } 1166 1167 skb_pull(skb, (pkt_len + 7) & 0xFFF8); 1168 pkt_hdr++; 1169 } 1170 return 1; 1171 } 1172 1173 static struct sk_buff * 1174 ax88179_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags) 1175 { 1176 u32 tx_hdr1, tx_hdr2; 1177 int frame_size = dev->maxpacket; 1178 int mss = skb_shinfo(skb)->gso_size; 1179 int headroom; 1180 1181 tx_hdr1 = skb->len; 1182 tx_hdr2 = mss; 1183 if (((skb->len + 8) % frame_size) == 0) 1184 tx_hdr2 |= 0x80008000; /* Enable padding */ 1185 1186 headroom = skb_headroom(skb) - 8; 1187 1188 if ((skb_header_cloned(skb) || headroom < 0) && 1189 pskb_expand_head(skb, headroom < 0 ? 8 : 0, 0, GFP_ATOMIC)) { 1190 dev_kfree_skb_any(skb); 1191 return NULL; 1192 } 1193 1194 skb_push(skb, 4); 1195 cpu_to_le32s(&tx_hdr2); 1196 skb_copy_to_linear_data(skb, &tx_hdr2, 4); 1197 1198 skb_push(skb, 4); 1199 cpu_to_le32s(&tx_hdr1); 1200 skb_copy_to_linear_data(skb, &tx_hdr1, 4); 1201 1202 return skb; 1203 } 1204 1205 static int ax88179_link_reset(struct usbnet *dev) 1206 { 1207 struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data; 1208 u8 tmp[5], link_sts; 1209 u16 mode, tmp16, delay = HZ / 10; 1210 u32 tmp32 = 0x40000000; 1211 unsigned long jtimeout; 1212 1213 jtimeout = jiffies + delay; 1214 while (tmp32 & 0x40000000) { 1215 mode = 0; 1216 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &mode); 1217 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, 1218 &ax179_data->rxctl); 1219 1220 /*link up, check the usb device control TX FIFO full or empty*/ 1221 ax88179_read_cmd(dev, 0x81, 0x8c, 0, 4, &tmp32); 1222 1223 if (time_after(jiffies, jtimeout)) 1224 return 0; 1225 } 1226 1227 mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 1228 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_ALWAYS_ONE; 1229 1230 ax88179_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS, 1231 1, 1, &link_sts); 1232 1233 ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1234 GMII_PHY_PHYSR, 2, &tmp16); 1235 1236 if (!(tmp16 & GMII_PHY_PHYSR_LINK)) { 1237 return 0; 1238 } else if (GMII_PHY_PHYSR_GIGA == (tmp16 & GMII_PHY_PHYSR_SMASK)) { 1239 mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ; 1240 if (dev->net->mtu > 1500) 1241 mode |= AX_MEDIUM_JUMBO_EN; 1242 1243 if (link_sts & AX_USB_SS) 1244 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 1245 else if (link_sts & AX_USB_HS) 1246 memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5); 1247 else 1248 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 1249 } else if (GMII_PHY_PHYSR_100 == (tmp16 & GMII_PHY_PHYSR_SMASK)) { 1250 mode |= AX_MEDIUM_PS; 1251 1252 if (link_sts & (AX_USB_SS | AX_USB_HS)) 1253 memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5); 1254 else 1255 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 1256 } else { 1257 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 1258 } 1259 1260 /* RX bulk configuration */ 1261 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 1262 1263 dev->rx_urb_size = (1024 * (tmp[3] + 2)); 1264 1265 if (tmp16 & GMII_PHY_PHYSR_FULL) 1266 mode |= AX_MEDIUM_FULL_DUPLEX; 1267 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1268 2, 2, &mode); 1269 1270 netif_carrier_on(dev->net); 1271 1272 return 0; 1273 } 1274 1275 static int ax88179_reset(struct usbnet *dev) 1276 { 1277 u8 buf[5]; 1278 u16 *tmp16; 1279 u8 *tmp; 1280 1281 tmp16 = (u16 *)buf; 1282 tmp = (u8 *)buf; 1283 1284 /* Power up ethernet PHY */ 1285 *tmp16 = 0; 1286 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 1287 1288 *tmp16 = AX_PHYPWR_RSTCTL_IPRL; 1289 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 1290 msleep(200); 1291 1292 *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 1293 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); 1294 msleep(100); 1295 1296 /* Ethernet PHY Auto Detach*/ 1297 ax88179_auto_detach(dev, 0); 1298 1299 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, ETH_ALEN, 1300 dev->net->dev_addr); 1301 memcpy(dev->net->perm_addr, dev->net->dev_addr, ETH_ALEN); 1302 1303 /* RX bulk configuration */ 1304 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 1305 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 1306 1307 dev->rx_urb_size = 1024 * 20; 1308 1309 *tmp = 0x34; 1310 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); 1311 1312 *tmp = 0x52; 1313 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1314 1, 1, tmp); 1315 1316 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1317 NETIF_F_RXCSUM; 1318 1319 dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1320 NETIF_F_RXCSUM; 1321 1322 /* Enable checksum offload */ 1323 *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 1324 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 1325 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); 1326 1327 *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | 1328 AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 1329 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); 1330 1331 /* Configure RX control register => start operation */ 1332 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 1333 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 1334 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); 1335 1336 *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | 1337 AX_MONITOR_MODE_RWMP; 1338 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); 1339 1340 /* Configure default medium type => giga */ 1341 *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 1342 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_ALWAYS_ONE | 1343 AX_MEDIUM_FULL_DUPLEX | AX_MEDIUM_GIGAMODE; 1344 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1345 2, 2, tmp16); 1346 1347 ax88179_led_setting(dev); 1348 1349 /* Restart autoneg */ 1350 mii_nway_restart(&dev->mii); 1351 1352 usbnet_link_change(dev, 0, 0); 1353 1354 return 0; 1355 } 1356 1357 static int ax88179_stop(struct usbnet *dev) 1358 { 1359 u16 tmp16; 1360 1361 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1362 2, 2, &tmp16); 1363 tmp16 &= ~AX_MEDIUM_RECEIVE_EN; 1364 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1365 2, 2, &tmp16); 1366 1367 return 0; 1368 } 1369 1370 static const struct driver_info ax88179_info = { 1371 .description = "ASIX AX88179 USB 3.0 Gigabit Ethernet", 1372 .bind = ax88179_bind, 1373 .unbind = ax88179_unbind, 1374 .status = ax88179_status, 1375 .link_reset = ax88179_link_reset, 1376 .reset = ax88179_reset, 1377 .stop = ax88179_stop, 1378 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1379 .rx_fixup = ax88179_rx_fixup, 1380 .tx_fixup = ax88179_tx_fixup, 1381 }; 1382 1383 static const struct driver_info ax88178a_info = { 1384 .description = "ASIX AX88178A USB 2.0 Gigabit Ethernet", 1385 .bind = ax88179_bind, 1386 .unbind = ax88179_unbind, 1387 .status = ax88179_status, 1388 .link_reset = ax88179_link_reset, 1389 .reset = ax88179_reset, 1390 .stop = ax88179_stop, 1391 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1392 .rx_fixup = ax88179_rx_fixup, 1393 .tx_fixup = ax88179_tx_fixup, 1394 }; 1395 1396 static const struct driver_info sitecom_info = { 1397 .description = "Sitecom USB 3.0 to Gigabit Adapter", 1398 .bind = ax88179_bind, 1399 .unbind = ax88179_unbind, 1400 .status = ax88179_status, 1401 .link_reset = ax88179_link_reset, 1402 .reset = ax88179_reset, 1403 .stop = ax88179_stop, 1404 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1405 .rx_fixup = ax88179_rx_fixup, 1406 .tx_fixup = ax88179_tx_fixup, 1407 }; 1408 1409 static const struct driver_info samsung_info = { 1410 .description = "Samsung USB Ethernet Adapter", 1411 .bind = ax88179_bind, 1412 .unbind = ax88179_unbind, 1413 .status = ax88179_status, 1414 .link_reset = ax88179_link_reset, 1415 .reset = ax88179_reset, 1416 .stop = ax88179_stop, 1417 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1418 .rx_fixup = ax88179_rx_fixup, 1419 .tx_fixup = ax88179_tx_fixup, 1420 }; 1421 1422 static const struct usb_device_id products[] = { 1423 { 1424 /* ASIX AX88179 10/100/1000 */ 1425 USB_DEVICE(0x0b95, 0x1790), 1426 .driver_info = (unsigned long)&ax88179_info, 1427 }, { 1428 /* ASIX AX88178A 10/100/1000 */ 1429 USB_DEVICE(0x0b95, 0x178a), 1430 .driver_info = (unsigned long)&ax88178a_info, 1431 }, { 1432 /* Sitecom USB 3.0 to Gigabit Adapter */ 1433 USB_DEVICE(0x0df6, 0x0072), 1434 .driver_info = (unsigned long)&sitecom_info, 1435 }, { 1436 /* Samsung USB Ethernet Adapter */ 1437 USB_DEVICE(0x04e8, 0xa100), 1438 .driver_info = (unsigned long)&samsung_info, 1439 }, 1440 { }, 1441 }; 1442 MODULE_DEVICE_TABLE(usb, products); 1443 1444 static struct usb_driver ax88179_178a_driver = { 1445 .name = "ax88179_178a", 1446 .id_table = products, 1447 .probe = usbnet_probe, 1448 .suspend = ax88179_suspend, 1449 .resume = ax88179_resume, 1450 .reset_resume = ax88179_resume, 1451 .disconnect = usbnet_disconnect, 1452 .supports_autosuspend = 1, 1453 .disable_hub_initiated_lpm = 1, 1454 }; 1455 1456 module_usb_driver(ax88179_178a_driver); 1457 1458 MODULE_DESCRIPTION("ASIX AX88179/178A based USB 3.0/2.0 Gigabit Ethernet Devices"); 1459 MODULE_LICENSE("GPL"); 1460