1 /* 2 * ASIX AX88179/178A USB 3.0/2.0 to Gigabit Ethernet Devices 3 * 4 * Copyright (C) 2011-2013 ASIX 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/module.h> 21 #include <linux/etherdevice.h> 22 #include <linux/mii.h> 23 #include <linux/usb.h> 24 #include <linux/crc32.h> 25 #include <linux/usb/usbnet.h> 26 #include <uapi/linux/mdio.h> 27 #include <linux/mdio.h> 28 29 #define AX88179_PHY_ID 0x03 30 #define AX_EEPROM_LEN 0x100 31 #define AX88179_EEPROM_MAGIC 0x17900b95 32 #define AX_MCAST_FLTSIZE 8 33 #define AX_MAX_MCAST 64 34 #define AX_INT_PPLS_LINK ((u32)BIT(16)) 35 #define AX_RXHDR_L4_TYPE_MASK 0x1c 36 #define AX_RXHDR_L4_TYPE_UDP 4 37 #define AX_RXHDR_L4_TYPE_TCP 16 38 #define AX_RXHDR_L3CSUM_ERR 2 39 #define AX_RXHDR_L4CSUM_ERR 1 40 #define AX_RXHDR_CRC_ERR ((u32)BIT(29)) 41 #define AX_RXHDR_DROP_ERR ((u32)BIT(31)) 42 #define AX_ACCESS_MAC 0x01 43 #define AX_ACCESS_PHY 0x02 44 #define AX_ACCESS_EEPROM 0x04 45 #define AX_ACCESS_EFUS 0x05 46 #define AX_PAUSE_WATERLVL_HIGH 0x54 47 #define AX_PAUSE_WATERLVL_LOW 0x55 48 49 #define PHYSICAL_LINK_STATUS 0x02 50 #define AX_USB_SS 0x04 51 #define AX_USB_HS 0x02 52 53 #define GENERAL_STATUS 0x03 54 /* Check AX88179 version. UA1:Bit2 = 0, UA2:Bit2 = 1 */ 55 #define AX_SECLD 0x04 56 57 #define AX_SROM_ADDR 0x07 58 #define AX_SROM_CMD 0x0a 59 #define EEP_RD 0x04 60 #define EEP_BUSY 0x10 61 62 #define AX_SROM_DATA_LOW 0x08 63 #define AX_SROM_DATA_HIGH 0x09 64 65 #define AX_RX_CTL 0x0b 66 #define AX_RX_CTL_DROPCRCERR 0x0100 67 #define AX_RX_CTL_IPE 0x0200 68 #define AX_RX_CTL_START 0x0080 69 #define AX_RX_CTL_AP 0x0020 70 #define AX_RX_CTL_AM 0x0010 71 #define AX_RX_CTL_AB 0x0008 72 #define AX_RX_CTL_AMALL 0x0002 73 #define AX_RX_CTL_PRO 0x0001 74 #define AX_RX_CTL_STOP 0x0000 75 76 #define AX_NODE_ID 0x10 77 #define AX_MULFLTARY 0x16 78 79 #define AX_MEDIUM_STATUS_MODE 0x22 80 #define AX_MEDIUM_GIGAMODE 0x01 81 #define AX_MEDIUM_FULL_DUPLEX 0x02 82 #define AX_MEDIUM_EN_125MHZ 0x08 83 #define AX_MEDIUM_RXFLOW_CTRLEN 0x10 84 #define AX_MEDIUM_TXFLOW_CTRLEN 0x20 85 #define AX_MEDIUM_RECEIVE_EN 0x100 86 #define AX_MEDIUM_PS 0x200 87 #define AX_MEDIUM_JUMBO_EN 0x8040 88 89 #define AX_MONITOR_MOD 0x24 90 #define AX_MONITOR_MODE_RWLC 0x02 91 #define AX_MONITOR_MODE_RWMP 0x04 92 #define AX_MONITOR_MODE_PMEPOL 0x20 93 #define AX_MONITOR_MODE_PMETYPE 0x40 94 95 #define AX_GPIO_CTRL 0x25 96 #define AX_GPIO_CTRL_GPIO3EN 0x80 97 #define AX_GPIO_CTRL_GPIO2EN 0x40 98 #define AX_GPIO_CTRL_GPIO1EN 0x20 99 100 #define AX_PHYPWR_RSTCTL 0x26 101 #define AX_PHYPWR_RSTCTL_BZ 0x0010 102 #define AX_PHYPWR_RSTCTL_IPRL 0x0020 103 #define AX_PHYPWR_RSTCTL_AT 0x1000 104 105 #define AX_RX_BULKIN_QCTRL 0x2e 106 #define AX_CLK_SELECT 0x33 107 #define AX_CLK_SELECT_BCS 0x01 108 #define AX_CLK_SELECT_ACS 0x02 109 #define AX_CLK_SELECT_ULR 0x08 110 111 #define AX_RXCOE_CTL 0x34 112 #define AX_RXCOE_IP 0x01 113 #define AX_RXCOE_TCP 0x02 114 #define AX_RXCOE_UDP 0x04 115 #define AX_RXCOE_TCPV6 0x20 116 #define AX_RXCOE_UDPV6 0x40 117 118 #define AX_TXCOE_CTL 0x35 119 #define AX_TXCOE_IP 0x01 120 #define AX_TXCOE_TCP 0x02 121 #define AX_TXCOE_UDP 0x04 122 #define AX_TXCOE_TCPV6 0x20 123 #define AX_TXCOE_UDPV6 0x40 124 125 #define AX_LEDCTRL 0x73 126 127 #define GMII_PHY_PHYSR 0x11 128 #define GMII_PHY_PHYSR_SMASK 0xc000 129 #define GMII_PHY_PHYSR_GIGA 0x8000 130 #define GMII_PHY_PHYSR_100 0x4000 131 #define GMII_PHY_PHYSR_FULL 0x2000 132 #define GMII_PHY_PHYSR_LINK 0x400 133 134 #define GMII_LED_ACT 0x1a 135 #define GMII_LED_ACTIVE_MASK 0xff8f 136 #define GMII_LED0_ACTIVE BIT(4) 137 #define GMII_LED1_ACTIVE BIT(5) 138 #define GMII_LED2_ACTIVE BIT(6) 139 140 #define GMII_LED_LINK 0x1c 141 #define GMII_LED_LINK_MASK 0xf888 142 #define GMII_LED0_LINK_10 BIT(0) 143 #define GMII_LED0_LINK_100 BIT(1) 144 #define GMII_LED0_LINK_1000 BIT(2) 145 #define GMII_LED1_LINK_10 BIT(4) 146 #define GMII_LED1_LINK_100 BIT(5) 147 #define GMII_LED1_LINK_1000 BIT(6) 148 #define GMII_LED2_LINK_10 BIT(8) 149 #define GMII_LED2_LINK_100 BIT(9) 150 #define GMII_LED2_LINK_1000 BIT(10) 151 #define LED0_ACTIVE BIT(0) 152 #define LED0_LINK_10 BIT(1) 153 #define LED0_LINK_100 BIT(2) 154 #define LED0_LINK_1000 BIT(3) 155 #define LED0_FD BIT(4) 156 #define LED0_USB3_MASK 0x001f 157 #define LED1_ACTIVE BIT(5) 158 #define LED1_LINK_10 BIT(6) 159 #define LED1_LINK_100 BIT(7) 160 #define LED1_LINK_1000 BIT(8) 161 #define LED1_FD BIT(9) 162 #define LED1_USB3_MASK 0x03e0 163 #define LED2_ACTIVE BIT(10) 164 #define LED2_LINK_1000 BIT(13) 165 #define LED2_LINK_100 BIT(12) 166 #define LED2_LINK_10 BIT(11) 167 #define LED2_FD BIT(14) 168 #define LED_VALID BIT(15) 169 #define LED2_USB3_MASK 0x7c00 170 171 #define GMII_PHYPAGE 0x1e 172 #define GMII_PHY_PAGE_SELECT 0x1f 173 #define GMII_PHY_PGSEL_EXT 0x0007 174 #define GMII_PHY_PGSEL_PAGE0 0x0000 175 #define GMII_PHY_PGSEL_PAGE3 0x0003 176 #define GMII_PHY_PGSEL_PAGE5 0x0005 177 178 struct ax88179_data { 179 u8 eee_enabled; 180 u8 eee_active; 181 u16 rxctl; 182 u16 reserved; 183 }; 184 185 struct ax88179_int_data { 186 __le32 intdata1; 187 __le32 intdata2; 188 }; 189 190 static const struct { 191 unsigned char ctrl, timer_l, timer_h, size, ifg; 192 } AX88179_BULKIN_SIZE[] = { 193 {7, 0x4f, 0, 0x12, 0xff}, 194 {7, 0x20, 3, 0x16, 0xff}, 195 {7, 0xae, 7, 0x18, 0xff}, 196 {7, 0xcc, 0x4c, 0x18, 8}, 197 }; 198 199 static int __ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 200 u16 size, void *data, int in_pm) 201 { 202 int ret; 203 int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16); 204 205 BUG_ON(!dev); 206 207 if (!in_pm) 208 fn = usbnet_read_cmd; 209 else 210 fn = usbnet_read_cmd_nopm; 211 212 ret = fn(dev, cmd, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 213 value, index, data, size); 214 215 if (unlikely(ret < 0)) 216 netdev_warn(dev->net, "Failed to read reg index 0x%04x: %d\n", 217 index, ret); 218 219 return ret; 220 } 221 222 static int __ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 223 u16 size, void *data, int in_pm) 224 { 225 int ret; 226 int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16); 227 228 BUG_ON(!dev); 229 230 if (!in_pm) 231 fn = usbnet_write_cmd; 232 else 233 fn = usbnet_write_cmd_nopm; 234 235 ret = fn(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 236 value, index, data, size); 237 238 if (unlikely(ret < 0)) 239 netdev_warn(dev->net, "Failed to write reg index 0x%04x: %d\n", 240 index, ret); 241 242 return ret; 243 } 244 245 static void ax88179_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, 246 u16 index, u16 size, void *data) 247 { 248 u16 buf; 249 250 if (2 == size) { 251 buf = *((u16 *)data); 252 cpu_to_le16s(&buf); 253 usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | 254 USB_RECIP_DEVICE, value, index, &buf, 255 size); 256 } else { 257 usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | 258 USB_RECIP_DEVICE, value, index, data, 259 size); 260 } 261 } 262 263 static int ax88179_read_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value, 264 u16 index, u16 size, void *data) 265 { 266 int ret; 267 268 if (2 == size) { 269 u16 buf; 270 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1); 271 le16_to_cpus(&buf); 272 *((u16 *)data) = buf; 273 } else if (4 == size) { 274 u32 buf; 275 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1); 276 le32_to_cpus(&buf); 277 *((u32 *)data) = buf; 278 } else { 279 ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 1); 280 } 281 282 return ret; 283 } 284 285 static int ax88179_write_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value, 286 u16 index, u16 size, void *data) 287 { 288 int ret; 289 290 if (2 == size) { 291 u16 buf; 292 buf = *((u16 *)data); 293 cpu_to_le16s(&buf); 294 ret = __ax88179_write_cmd(dev, cmd, value, index, 295 size, &buf, 1); 296 } else { 297 ret = __ax88179_write_cmd(dev, cmd, value, index, 298 size, data, 1); 299 } 300 301 return ret; 302 } 303 304 static int ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 305 u16 size, void *data) 306 { 307 int ret; 308 309 if (2 == size) { 310 u16 buf; 311 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0); 312 le16_to_cpus(&buf); 313 *((u16 *)data) = buf; 314 } else if (4 == size) { 315 u32 buf; 316 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0); 317 le32_to_cpus(&buf); 318 *((u32 *)data) = buf; 319 } else { 320 ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 0); 321 } 322 323 return ret; 324 } 325 326 static int ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 327 u16 size, void *data) 328 { 329 int ret; 330 331 if (2 == size) { 332 u16 buf; 333 buf = *((u16 *)data); 334 cpu_to_le16s(&buf); 335 ret = __ax88179_write_cmd(dev, cmd, value, index, 336 size, &buf, 0); 337 } else { 338 ret = __ax88179_write_cmd(dev, cmd, value, index, 339 size, data, 0); 340 } 341 342 return ret; 343 } 344 345 static void ax88179_status(struct usbnet *dev, struct urb *urb) 346 { 347 struct ax88179_int_data *event; 348 u32 link; 349 350 if (urb->actual_length < 8) 351 return; 352 353 event = urb->transfer_buffer; 354 le32_to_cpus((void *)&event->intdata1); 355 356 link = (((__force u32)event->intdata1) & AX_INT_PPLS_LINK) >> 16; 357 358 if (netif_carrier_ok(dev->net) != link) { 359 usbnet_link_change(dev, link, 1); 360 netdev_info(dev->net, "ax88179 - Link status is: %d\n", link); 361 } 362 } 363 364 static int ax88179_mdio_read(struct net_device *netdev, int phy_id, int loc) 365 { 366 struct usbnet *dev = netdev_priv(netdev); 367 u16 res; 368 369 ax88179_read_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res); 370 return res; 371 } 372 373 static void ax88179_mdio_write(struct net_device *netdev, int phy_id, int loc, 374 int val) 375 { 376 struct usbnet *dev = netdev_priv(netdev); 377 u16 res = (u16) val; 378 379 ax88179_write_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res); 380 } 381 382 static inline int ax88179_phy_mmd_indirect(struct usbnet *dev, u16 prtad, 383 u16 devad) 384 { 385 u16 tmp16; 386 int ret; 387 388 tmp16 = devad; 389 ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 390 MII_MMD_CTRL, 2, &tmp16); 391 392 tmp16 = prtad; 393 ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 394 MII_MMD_DATA, 2, &tmp16); 395 396 tmp16 = devad | MII_MMD_CTRL_NOINCR; 397 ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 398 MII_MMD_CTRL, 2, &tmp16); 399 400 return ret; 401 } 402 403 static int 404 ax88179_phy_read_mmd_indirect(struct usbnet *dev, u16 prtad, u16 devad) 405 { 406 int ret; 407 u16 tmp16; 408 409 ax88179_phy_mmd_indirect(dev, prtad, devad); 410 411 ret = ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 412 MII_MMD_DATA, 2, &tmp16); 413 if (ret < 0) 414 return ret; 415 416 return tmp16; 417 } 418 419 static int 420 ax88179_phy_write_mmd_indirect(struct usbnet *dev, u16 prtad, u16 devad, 421 u16 data) 422 { 423 int ret; 424 425 ax88179_phy_mmd_indirect(dev, prtad, devad); 426 427 ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 428 MII_MMD_DATA, 2, &data); 429 430 if (ret < 0) 431 return ret; 432 433 return 0; 434 } 435 436 static int ax88179_suspend(struct usb_interface *intf, pm_message_t message) 437 { 438 struct usbnet *dev = usb_get_intfdata(intf); 439 u16 tmp16; 440 u8 tmp8; 441 442 usbnet_suspend(intf, message); 443 444 /* Disable RX path */ 445 ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 446 2, 2, &tmp16); 447 tmp16 &= ~AX_MEDIUM_RECEIVE_EN; 448 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 449 2, 2, &tmp16); 450 451 /* Force bulk-in zero length */ 452 ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 453 2, 2, &tmp16); 454 455 tmp16 |= AX_PHYPWR_RSTCTL_BZ | AX_PHYPWR_RSTCTL_IPRL; 456 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 457 2, 2, &tmp16); 458 459 /* change clock */ 460 tmp8 = 0; 461 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 462 463 /* Configure RX control register => stop operation */ 464 tmp16 = AX_RX_CTL_STOP; 465 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16); 466 467 return 0; 468 } 469 470 /* This function is used to enable the autodetach function. */ 471 /* This function is determined by offset 0x43 of EEPROM */ 472 static int ax88179_auto_detach(struct usbnet *dev, int in_pm) 473 { 474 u16 tmp16; 475 u8 tmp8; 476 int (*fnr)(struct usbnet *, u8, u16, u16, u16, void *); 477 int (*fnw)(struct usbnet *, u8, u16, u16, u16, void *); 478 479 if (!in_pm) { 480 fnr = ax88179_read_cmd; 481 fnw = ax88179_write_cmd; 482 } else { 483 fnr = ax88179_read_cmd_nopm; 484 fnw = ax88179_write_cmd_nopm; 485 } 486 487 if (fnr(dev, AX_ACCESS_EEPROM, 0x43, 1, 2, &tmp16) < 0) 488 return 0; 489 490 if ((tmp16 == 0xFFFF) || (!(tmp16 & 0x0100))) 491 return 0; 492 493 /* Enable Auto Detach bit */ 494 tmp8 = 0; 495 fnr(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 496 tmp8 |= AX_CLK_SELECT_ULR; 497 fnw(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 498 499 fnr(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16); 500 tmp16 |= AX_PHYPWR_RSTCTL_AT; 501 fnw(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16); 502 503 return 0; 504 } 505 506 static int ax88179_resume(struct usb_interface *intf) 507 { 508 struct usbnet *dev = usb_get_intfdata(intf); 509 u16 tmp16; 510 u8 tmp8; 511 512 usbnet_link_change(dev, 0, 0); 513 514 /* Power up ethernet PHY */ 515 tmp16 = 0; 516 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 517 2, 2, &tmp16); 518 udelay(1000); 519 520 tmp16 = AX_PHYPWR_RSTCTL_IPRL; 521 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 522 2, 2, &tmp16); 523 msleep(200); 524 525 /* Ethernet PHY Auto Detach*/ 526 ax88179_auto_detach(dev, 1); 527 528 /* Enable clock */ 529 ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 530 tmp8 |= AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 531 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 532 msleep(100); 533 534 /* Configure RX control register => start operation */ 535 tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 536 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 537 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16); 538 539 return usbnet_resume(intf); 540 } 541 542 static void 543 ax88179_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) 544 { 545 struct usbnet *dev = netdev_priv(net); 546 u8 opt; 547 548 if (ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 549 1, 1, &opt) < 0) { 550 wolinfo->supported = 0; 551 wolinfo->wolopts = 0; 552 return; 553 } 554 555 wolinfo->supported = WAKE_PHY | WAKE_MAGIC; 556 wolinfo->wolopts = 0; 557 if (opt & AX_MONITOR_MODE_RWLC) 558 wolinfo->wolopts |= WAKE_PHY; 559 if (opt & AX_MONITOR_MODE_RWMP) 560 wolinfo->wolopts |= WAKE_MAGIC; 561 } 562 563 static int 564 ax88179_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) 565 { 566 struct usbnet *dev = netdev_priv(net); 567 u8 opt = 0; 568 569 if (wolinfo->wolopts & ~(WAKE_PHY | WAKE_MAGIC)) 570 return -EINVAL; 571 572 if (wolinfo->wolopts & WAKE_PHY) 573 opt |= AX_MONITOR_MODE_RWLC; 574 if (wolinfo->wolopts & WAKE_MAGIC) 575 opt |= AX_MONITOR_MODE_RWMP; 576 577 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 578 1, 1, &opt) < 0) 579 return -EINVAL; 580 581 return 0; 582 } 583 584 static int ax88179_get_eeprom_len(struct net_device *net) 585 { 586 return AX_EEPROM_LEN; 587 } 588 589 static int 590 ax88179_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom, 591 u8 *data) 592 { 593 struct usbnet *dev = netdev_priv(net); 594 u16 *eeprom_buff; 595 int first_word, last_word; 596 int i, ret; 597 598 if (eeprom->len == 0) 599 return -EINVAL; 600 601 eeprom->magic = AX88179_EEPROM_MAGIC; 602 603 first_word = eeprom->offset >> 1; 604 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 605 eeprom_buff = kmalloc_array(last_word - first_word + 1, sizeof(u16), 606 GFP_KERNEL); 607 if (!eeprom_buff) 608 return -ENOMEM; 609 610 /* ax88179/178A returns 2 bytes from eeprom on read */ 611 for (i = first_word; i <= last_word; i++) { 612 ret = __ax88179_read_cmd(dev, AX_ACCESS_EEPROM, i, 1, 2, 613 &eeprom_buff[i - first_word], 614 0); 615 if (ret < 0) { 616 kfree(eeprom_buff); 617 return -EIO; 618 } 619 } 620 621 memcpy(data, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); 622 kfree(eeprom_buff); 623 return 0; 624 } 625 626 static int ax88179_get_link_ksettings(struct net_device *net, 627 struct ethtool_link_ksettings *cmd) 628 { 629 struct usbnet *dev = netdev_priv(net); 630 631 mii_ethtool_get_link_ksettings(&dev->mii, cmd); 632 633 return 0; 634 } 635 636 static int ax88179_set_link_ksettings(struct net_device *net, 637 const struct ethtool_link_ksettings *cmd) 638 { 639 struct usbnet *dev = netdev_priv(net); 640 return mii_ethtool_set_link_ksettings(&dev->mii, cmd); 641 } 642 643 static int 644 ax88179_ethtool_get_eee(struct usbnet *dev, struct ethtool_eee *data) 645 { 646 int val; 647 648 /* Get Supported EEE */ 649 val = ax88179_phy_read_mmd_indirect(dev, MDIO_PCS_EEE_ABLE, 650 MDIO_MMD_PCS); 651 if (val < 0) 652 return val; 653 data->supported = mmd_eee_cap_to_ethtool_sup_t(val); 654 655 /* Get advertisement EEE */ 656 val = ax88179_phy_read_mmd_indirect(dev, MDIO_AN_EEE_ADV, 657 MDIO_MMD_AN); 658 if (val < 0) 659 return val; 660 data->advertised = mmd_eee_adv_to_ethtool_adv_t(val); 661 662 /* Get LP advertisement EEE */ 663 val = ax88179_phy_read_mmd_indirect(dev, MDIO_AN_EEE_LPABLE, 664 MDIO_MMD_AN); 665 if (val < 0) 666 return val; 667 data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val); 668 669 return 0; 670 } 671 672 static int 673 ax88179_ethtool_set_eee(struct usbnet *dev, struct ethtool_eee *data) 674 { 675 u16 tmp16 = ethtool_adv_to_mmd_eee_adv_t(data->advertised); 676 677 return ax88179_phy_write_mmd_indirect(dev, MDIO_AN_EEE_ADV, 678 MDIO_MMD_AN, tmp16); 679 } 680 681 static int ax88179_chk_eee(struct usbnet *dev) 682 { 683 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 684 struct ax88179_data *priv = (struct ax88179_data *)dev->data; 685 686 mii_ethtool_gset(&dev->mii, &ecmd); 687 688 if (ecmd.duplex & DUPLEX_FULL) { 689 int eee_lp, eee_cap, eee_adv; 690 u32 lp, cap, adv, supported = 0; 691 692 eee_cap = ax88179_phy_read_mmd_indirect(dev, 693 MDIO_PCS_EEE_ABLE, 694 MDIO_MMD_PCS); 695 if (eee_cap < 0) { 696 priv->eee_active = 0; 697 return false; 698 } 699 700 cap = mmd_eee_cap_to_ethtool_sup_t(eee_cap); 701 if (!cap) { 702 priv->eee_active = 0; 703 return false; 704 } 705 706 eee_lp = ax88179_phy_read_mmd_indirect(dev, 707 MDIO_AN_EEE_LPABLE, 708 MDIO_MMD_AN); 709 if (eee_lp < 0) { 710 priv->eee_active = 0; 711 return false; 712 } 713 714 eee_adv = ax88179_phy_read_mmd_indirect(dev, 715 MDIO_AN_EEE_ADV, 716 MDIO_MMD_AN); 717 718 if (eee_adv < 0) { 719 priv->eee_active = 0; 720 return false; 721 } 722 723 adv = mmd_eee_adv_to_ethtool_adv_t(eee_adv); 724 lp = mmd_eee_adv_to_ethtool_adv_t(eee_lp); 725 supported = (ecmd.speed == SPEED_1000) ? 726 SUPPORTED_1000baseT_Full : 727 SUPPORTED_100baseT_Full; 728 729 if (!(lp & adv & supported)) { 730 priv->eee_active = 0; 731 return false; 732 } 733 734 priv->eee_active = 1; 735 return true; 736 } 737 738 priv->eee_active = 0; 739 return false; 740 } 741 742 static void ax88179_disable_eee(struct usbnet *dev) 743 { 744 u16 tmp16; 745 746 tmp16 = GMII_PHY_PGSEL_PAGE3; 747 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 748 GMII_PHY_PAGE_SELECT, 2, &tmp16); 749 750 tmp16 = 0x3246; 751 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 752 MII_PHYADDR, 2, &tmp16); 753 754 tmp16 = GMII_PHY_PGSEL_PAGE0; 755 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 756 GMII_PHY_PAGE_SELECT, 2, &tmp16); 757 } 758 759 static void ax88179_enable_eee(struct usbnet *dev) 760 { 761 u16 tmp16; 762 763 tmp16 = GMII_PHY_PGSEL_PAGE3; 764 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 765 GMII_PHY_PAGE_SELECT, 2, &tmp16); 766 767 tmp16 = 0x3247; 768 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 769 MII_PHYADDR, 2, &tmp16); 770 771 tmp16 = GMII_PHY_PGSEL_PAGE5; 772 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 773 GMII_PHY_PAGE_SELECT, 2, &tmp16); 774 775 tmp16 = 0x0680; 776 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 777 MII_BMSR, 2, &tmp16); 778 779 tmp16 = GMII_PHY_PGSEL_PAGE0; 780 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 781 GMII_PHY_PAGE_SELECT, 2, &tmp16); 782 } 783 784 static int ax88179_get_eee(struct net_device *net, struct ethtool_eee *edata) 785 { 786 struct usbnet *dev = netdev_priv(net); 787 struct ax88179_data *priv = (struct ax88179_data *)dev->data; 788 789 edata->eee_enabled = priv->eee_enabled; 790 edata->eee_active = priv->eee_active; 791 792 return ax88179_ethtool_get_eee(dev, edata); 793 } 794 795 static int ax88179_set_eee(struct net_device *net, struct ethtool_eee *edata) 796 { 797 struct usbnet *dev = netdev_priv(net); 798 struct ax88179_data *priv = (struct ax88179_data *)dev->data; 799 int ret = -EOPNOTSUPP; 800 801 priv->eee_enabled = edata->eee_enabled; 802 if (!priv->eee_enabled) { 803 ax88179_disable_eee(dev); 804 } else { 805 priv->eee_enabled = ax88179_chk_eee(dev); 806 if (!priv->eee_enabled) 807 return -EOPNOTSUPP; 808 809 ax88179_enable_eee(dev); 810 } 811 812 ret = ax88179_ethtool_set_eee(dev, edata); 813 if (ret) 814 return ret; 815 816 mii_nway_restart(&dev->mii); 817 818 usbnet_link_change(dev, 0, 0); 819 820 return ret; 821 } 822 823 static int ax88179_ioctl(struct net_device *net, struct ifreq *rq, int cmd) 824 { 825 struct usbnet *dev = netdev_priv(net); 826 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); 827 } 828 829 static const struct ethtool_ops ax88179_ethtool_ops = { 830 .get_link = ethtool_op_get_link, 831 .get_msglevel = usbnet_get_msglevel, 832 .set_msglevel = usbnet_set_msglevel, 833 .get_wol = ax88179_get_wol, 834 .set_wol = ax88179_set_wol, 835 .get_eeprom_len = ax88179_get_eeprom_len, 836 .get_eeprom = ax88179_get_eeprom, 837 .get_eee = ax88179_get_eee, 838 .set_eee = ax88179_set_eee, 839 .nway_reset = usbnet_nway_reset, 840 .get_link_ksettings = ax88179_get_link_ksettings, 841 .set_link_ksettings = ax88179_set_link_ksettings, 842 }; 843 844 static void ax88179_set_multicast(struct net_device *net) 845 { 846 struct usbnet *dev = netdev_priv(net); 847 struct ax88179_data *data = (struct ax88179_data *)dev->data; 848 u8 *m_filter = ((u8 *)dev->data) + 12; 849 850 data->rxctl = (AX_RX_CTL_START | AX_RX_CTL_AB | AX_RX_CTL_IPE); 851 852 if (net->flags & IFF_PROMISC) { 853 data->rxctl |= AX_RX_CTL_PRO; 854 } else if (net->flags & IFF_ALLMULTI || 855 netdev_mc_count(net) > AX_MAX_MCAST) { 856 data->rxctl |= AX_RX_CTL_AMALL; 857 } else if (netdev_mc_empty(net)) { 858 /* just broadcast and directed */ 859 } else { 860 /* We use the 20 byte dev->data for our 8 byte filter buffer 861 * to avoid allocating memory that is tricky to free later 862 */ 863 u32 crc_bits; 864 struct netdev_hw_addr *ha; 865 866 memset(m_filter, 0, AX_MCAST_FLTSIZE); 867 868 netdev_for_each_mc_addr(ha, net) { 869 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; 870 *(m_filter + (crc_bits >> 3)) |= (1 << (crc_bits & 7)); 871 } 872 873 ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_MULFLTARY, 874 AX_MCAST_FLTSIZE, AX_MCAST_FLTSIZE, 875 m_filter); 876 877 data->rxctl |= AX_RX_CTL_AM; 878 } 879 880 ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_RX_CTL, 881 2, 2, &data->rxctl); 882 } 883 884 static int 885 ax88179_set_features(struct net_device *net, netdev_features_t features) 886 { 887 u8 tmp; 888 struct usbnet *dev = netdev_priv(net); 889 netdev_features_t changed = net->features ^ features; 890 891 if (changed & NETIF_F_IP_CSUM) { 892 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 893 tmp ^= AX_TXCOE_TCP | AX_TXCOE_UDP; 894 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 895 } 896 897 if (changed & NETIF_F_IPV6_CSUM) { 898 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 899 tmp ^= AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 900 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 901 } 902 903 if (changed & NETIF_F_RXCSUM) { 904 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp); 905 tmp ^= AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 906 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 907 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp); 908 } 909 910 return 0; 911 } 912 913 static int ax88179_change_mtu(struct net_device *net, int new_mtu) 914 { 915 struct usbnet *dev = netdev_priv(net); 916 u16 tmp16; 917 918 net->mtu = new_mtu; 919 dev->hard_mtu = net->mtu + net->hard_header_len; 920 921 if (net->mtu > 1500) { 922 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 923 2, 2, &tmp16); 924 tmp16 |= AX_MEDIUM_JUMBO_EN; 925 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 926 2, 2, &tmp16); 927 } else { 928 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 929 2, 2, &tmp16); 930 tmp16 &= ~AX_MEDIUM_JUMBO_EN; 931 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 932 2, 2, &tmp16); 933 } 934 935 /* max qlen depend on hard_mtu and rx_urb_size */ 936 usbnet_update_max_qlen(dev); 937 938 return 0; 939 } 940 941 static int ax88179_set_mac_addr(struct net_device *net, void *p) 942 { 943 struct usbnet *dev = netdev_priv(net); 944 struct sockaddr *addr = p; 945 int ret; 946 947 if (netif_running(net)) 948 return -EBUSY; 949 if (!is_valid_ether_addr(addr->sa_data)) 950 return -EADDRNOTAVAIL; 951 952 memcpy(net->dev_addr, addr->sa_data, ETH_ALEN); 953 954 /* Set the MAC address */ 955 ret = ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, 956 ETH_ALEN, net->dev_addr); 957 if (ret < 0) 958 return ret; 959 960 return 0; 961 } 962 963 static const struct net_device_ops ax88179_netdev_ops = { 964 .ndo_open = usbnet_open, 965 .ndo_stop = usbnet_stop, 966 .ndo_start_xmit = usbnet_start_xmit, 967 .ndo_tx_timeout = usbnet_tx_timeout, 968 .ndo_get_stats64 = usbnet_get_stats64, 969 .ndo_change_mtu = ax88179_change_mtu, 970 .ndo_set_mac_address = ax88179_set_mac_addr, 971 .ndo_validate_addr = eth_validate_addr, 972 .ndo_do_ioctl = ax88179_ioctl, 973 .ndo_set_rx_mode = ax88179_set_multicast, 974 .ndo_set_features = ax88179_set_features, 975 }; 976 977 static int ax88179_check_eeprom(struct usbnet *dev) 978 { 979 u8 i, buf, eeprom[20]; 980 u16 csum, delay = HZ / 10; 981 unsigned long jtimeout; 982 983 /* Read EEPROM content */ 984 for (i = 0; i < 6; i++) { 985 buf = i; 986 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR, 987 1, 1, &buf) < 0) 988 return -EINVAL; 989 990 buf = EEP_RD; 991 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 992 1, 1, &buf) < 0) 993 return -EINVAL; 994 995 jtimeout = jiffies + delay; 996 do { 997 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 998 1, 1, &buf); 999 1000 if (time_after(jiffies, jtimeout)) 1001 return -EINVAL; 1002 1003 } while (buf & EEP_BUSY); 1004 1005 __ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW, 1006 2, 2, &eeprom[i * 2], 0); 1007 1008 if ((i == 0) && (eeprom[0] == 0xFF)) 1009 return -EINVAL; 1010 } 1011 1012 csum = eeprom[6] + eeprom[7] + eeprom[8] + eeprom[9]; 1013 csum = (csum >> 8) + (csum & 0xff); 1014 if ((csum + eeprom[10]) != 0xff) 1015 return -EINVAL; 1016 1017 return 0; 1018 } 1019 1020 static int ax88179_check_efuse(struct usbnet *dev, u16 *ledmode) 1021 { 1022 u8 i; 1023 u8 efuse[64]; 1024 u16 csum = 0; 1025 1026 if (ax88179_read_cmd(dev, AX_ACCESS_EFUS, 0, 64, 64, efuse) < 0) 1027 return -EINVAL; 1028 1029 if (*efuse == 0xFF) 1030 return -EINVAL; 1031 1032 for (i = 0; i < 64; i++) 1033 csum = csum + efuse[i]; 1034 1035 while (csum > 255) 1036 csum = (csum & 0x00FF) + ((csum >> 8) & 0x00FF); 1037 1038 if (csum != 0xFF) 1039 return -EINVAL; 1040 1041 *ledmode = (efuse[51] << 8) | efuse[52]; 1042 1043 return 0; 1044 } 1045 1046 static int ax88179_convert_old_led(struct usbnet *dev, u16 *ledvalue) 1047 { 1048 u16 led; 1049 1050 /* Loaded the old eFuse LED Mode */ 1051 if (ax88179_read_cmd(dev, AX_ACCESS_EEPROM, 0x3C, 1, 2, &led) < 0) 1052 return -EINVAL; 1053 1054 led >>= 8; 1055 switch (led) { 1056 case 0xFF: 1057 led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 | 1058 LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 | 1059 LED2_LINK_100 | LED2_LINK_1000 | LED_VALID; 1060 break; 1061 case 0xFE: 1062 led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 | LED_VALID; 1063 break; 1064 case 0xFD: 1065 led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 | 1066 LED2_LINK_10 | LED_VALID; 1067 break; 1068 case 0xFC: 1069 led = LED0_ACTIVE | LED1_ACTIVE | LED1_LINK_1000 | LED2_ACTIVE | 1070 LED2_LINK_100 | LED2_LINK_10 | LED_VALID; 1071 break; 1072 default: 1073 led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 | 1074 LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 | 1075 LED2_LINK_100 | LED2_LINK_1000 | LED_VALID; 1076 break; 1077 } 1078 1079 *ledvalue = led; 1080 1081 return 0; 1082 } 1083 1084 static int ax88179_led_setting(struct usbnet *dev) 1085 { 1086 u8 ledfd, value = 0; 1087 u16 tmp, ledact, ledlink, ledvalue = 0, delay = HZ / 10; 1088 unsigned long jtimeout; 1089 1090 /* Check AX88179 version. UA1 or UA2*/ 1091 ax88179_read_cmd(dev, AX_ACCESS_MAC, GENERAL_STATUS, 1, 1, &value); 1092 1093 if (!(value & AX_SECLD)) { /* UA1 */ 1094 value = AX_GPIO_CTRL_GPIO3EN | AX_GPIO_CTRL_GPIO2EN | 1095 AX_GPIO_CTRL_GPIO1EN; 1096 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_GPIO_CTRL, 1097 1, 1, &value) < 0) 1098 return -EINVAL; 1099 } 1100 1101 /* Check EEPROM */ 1102 if (!ax88179_check_eeprom(dev)) { 1103 value = 0x42; 1104 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR, 1105 1, 1, &value) < 0) 1106 return -EINVAL; 1107 1108 value = EEP_RD; 1109 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 1110 1, 1, &value) < 0) 1111 return -EINVAL; 1112 1113 jtimeout = jiffies + delay; 1114 do { 1115 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 1116 1, 1, &value); 1117 1118 if (time_after(jiffies, jtimeout)) 1119 return -EINVAL; 1120 1121 } while (value & EEP_BUSY); 1122 1123 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_HIGH, 1124 1, 1, &value); 1125 ledvalue = (value << 8); 1126 1127 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW, 1128 1, 1, &value); 1129 ledvalue |= value; 1130 1131 /* load internal ROM for defaule setting */ 1132 if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0)) 1133 ax88179_convert_old_led(dev, &ledvalue); 1134 1135 } else if (!ax88179_check_efuse(dev, &ledvalue)) { 1136 if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0)) 1137 ax88179_convert_old_led(dev, &ledvalue); 1138 } else { 1139 ax88179_convert_old_led(dev, &ledvalue); 1140 } 1141 1142 tmp = GMII_PHY_PGSEL_EXT; 1143 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1144 GMII_PHY_PAGE_SELECT, 2, &tmp); 1145 1146 tmp = 0x2c; 1147 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1148 GMII_PHYPAGE, 2, &tmp); 1149 1150 ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1151 GMII_LED_ACT, 2, &ledact); 1152 1153 ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1154 GMII_LED_LINK, 2, &ledlink); 1155 1156 ledact &= GMII_LED_ACTIVE_MASK; 1157 ledlink &= GMII_LED_LINK_MASK; 1158 1159 if (ledvalue & LED0_ACTIVE) 1160 ledact |= GMII_LED0_ACTIVE; 1161 1162 if (ledvalue & LED1_ACTIVE) 1163 ledact |= GMII_LED1_ACTIVE; 1164 1165 if (ledvalue & LED2_ACTIVE) 1166 ledact |= GMII_LED2_ACTIVE; 1167 1168 if (ledvalue & LED0_LINK_10) 1169 ledlink |= GMII_LED0_LINK_10; 1170 1171 if (ledvalue & LED1_LINK_10) 1172 ledlink |= GMII_LED1_LINK_10; 1173 1174 if (ledvalue & LED2_LINK_10) 1175 ledlink |= GMII_LED2_LINK_10; 1176 1177 if (ledvalue & LED0_LINK_100) 1178 ledlink |= GMII_LED0_LINK_100; 1179 1180 if (ledvalue & LED1_LINK_100) 1181 ledlink |= GMII_LED1_LINK_100; 1182 1183 if (ledvalue & LED2_LINK_100) 1184 ledlink |= GMII_LED2_LINK_100; 1185 1186 if (ledvalue & LED0_LINK_1000) 1187 ledlink |= GMII_LED0_LINK_1000; 1188 1189 if (ledvalue & LED1_LINK_1000) 1190 ledlink |= GMII_LED1_LINK_1000; 1191 1192 if (ledvalue & LED2_LINK_1000) 1193 ledlink |= GMII_LED2_LINK_1000; 1194 1195 tmp = ledact; 1196 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1197 GMII_LED_ACT, 2, &tmp); 1198 1199 tmp = ledlink; 1200 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1201 GMII_LED_LINK, 2, &tmp); 1202 1203 tmp = GMII_PHY_PGSEL_PAGE0; 1204 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1205 GMII_PHY_PAGE_SELECT, 2, &tmp); 1206 1207 /* LED full duplex setting */ 1208 ledfd = 0; 1209 if (ledvalue & LED0_FD) 1210 ledfd |= 0x01; 1211 else if ((ledvalue & LED0_USB3_MASK) == 0) 1212 ledfd |= 0x02; 1213 1214 if (ledvalue & LED1_FD) 1215 ledfd |= 0x04; 1216 else if ((ledvalue & LED1_USB3_MASK) == 0) 1217 ledfd |= 0x08; 1218 1219 if (ledvalue & LED2_FD) 1220 ledfd |= 0x10; 1221 else if ((ledvalue & LED2_USB3_MASK) == 0) 1222 ledfd |= 0x20; 1223 1224 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_LEDCTRL, 1, 1, &ledfd); 1225 1226 return 0; 1227 } 1228 1229 static int ax88179_bind(struct usbnet *dev, struct usb_interface *intf) 1230 { 1231 u8 buf[5]; 1232 u16 *tmp16; 1233 u8 *tmp; 1234 struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data; 1235 struct ethtool_eee eee_data; 1236 1237 usbnet_get_endpoints(dev, intf); 1238 1239 tmp16 = (u16 *)buf; 1240 tmp = (u8 *)buf; 1241 1242 memset(ax179_data, 0, sizeof(*ax179_data)); 1243 1244 /* Power up ethernet PHY */ 1245 *tmp16 = 0; 1246 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 1247 *tmp16 = AX_PHYPWR_RSTCTL_IPRL; 1248 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 1249 msleep(200); 1250 1251 *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 1252 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); 1253 msleep(100); 1254 1255 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, 1256 ETH_ALEN, dev->net->dev_addr); 1257 memcpy(dev->net->perm_addr, dev->net->dev_addr, ETH_ALEN); 1258 1259 /* RX bulk configuration */ 1260 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 1261 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 1262 1263 dev->rx_urb_size = 1024 * 20; 1264 1265 *tmp = 0x34; 1266 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); 1267 1268 *tmp = 0x52; 1269 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1270 1, 1, tmp); 1271 1272 dev->net->netdev_ops = &ax88179_netdev_ops; 1273 dev->net->ethtool_ops = &ax88179_ethtool_ops; 1274 dev->net->needed_headroom = 8; 1275 dev->net->max_mtu = 4088; 1276 1277 /* Initialize MII structure */ 1278 dev->mii.dev = dev->net; 1279 dev->mii.mdio_read = ax88179_mdio_read; 1280 dev->mii.mdio_write = ax88179_mdio_write; 1281 dev->mii.phy_id_mask = 0xff; 1282 dev->mii.reg_num_mask = 0xff; 1283 dev->mii.phy_id = 0x03; 1284 dev->mii.supports_gmii = 1; 1285 1286 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1287 NETIF_F_RXCSUM; 1288 1289 dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1290 NETIF_F_RXCSUM; 1291 1292 /* Enable checksum offload */ 1293 *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 1294 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 1295 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); 1296 1297 *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | 1298 AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 1299 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); 1300 1301 /* Configure RX control register => start operation */ 1302 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 1303 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 1304 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); 1305 1306 *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | 1307 AX_MONITOR_MODE_RWMP; 1308 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); 1309 1310 /* Configure default medium type => giga */ 1311 *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 1312 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX | 1313 AX_MEDIUM_GIGAMODE; 1314 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1315 2, 2, tmp16); 1316 1317 ax88179_led_setting(dev); 1318 1319 ax179_data->eee_enabled = 0; 1320 ax179_data->eee_active = 0; 1321 1322 ax88179_disable_eee(dev); 1323 1324 ax88179_ethtool_get_eee(dev, &eee_data); 1325 eee_data.advertised = 0; 1326 ax88179_ethtool_set_eee(dev, &eee_data); 1327 1328 /* Restart autoneg */ 1329 mii_nway_restart(&dev->mii); 1330 1331 usbnet_link_change(dev, 0, 0); 1332 1333 return 0; 1334 } 1335 1336 static void ax88179_unbind(struct usbnet *dev, struct usb_interface *intf) 1337 { 1338 u16 tmp16; 1339 1340 /* Configure RX control register => stop operation */ 1341 tmp16 = AX_RX_CTL_STOP; 1342 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16); 1343 1344 tmp16 = 0; 1345 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp16); 1346 1347 /* Power down ethernet PHY */ 1348 tmp16 = 0; 1349 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16); 1350 } 1351 1352 static void 1353 ax88179_rx_checksum(struct sk_buff *skb, u32 *pkt_hdr) 1354 { 1355 skb->ip_summed = CHECKSUM_NONE; 1356 1357 /* checksum error bit is set */ 1358 if ((*pkt_hdr & AX_RXHDR_L3CSUM_ERR) || 1359 (*pkt_hdr & AX_RXHDR_L4CSUM_ERR)) 1360 return; 1361 1362 /* It must be a TCP or UDP packet with a valid checksum */ 1363 if (((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_TCP) || 1364 ((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_UDP)) 1365 skb->ip_summed = CHECKSUM_UNNECESSARY; 1366 } 1367 1368 static int ax88179_rx_fixup(struct usbnet *dev, struct sk_buff *skb) 1369 { 1370 struct sk_buff *ax_skb; 1371 int pkt_cnt; 1372 u32 rx_hdr; 1373 u16 hdr_off; 1374 u32 *pkt_hdr; 1375 1376 /* This check is no longer done by usbnet */ 1377 if (skb->len < dev->net->hard_header_len) 1378 return 0; 1379 1380 skb_trim(skb, skb->len - 4); 1381 memcpy(&rx_hdr, skb_tail_pointer(skb), 4); 1382 le32_to_cpus(&rx_hdr); 1383 1384 pkt_cnt = (u16)rx_hdr; 1385 hdr_off = (u16)(rx_hdr >> 16); 1386 pkt_hdr = (u32 *)(skb->data + hdr_off); 1387 1388 while (pkt_cnt--) { 1389 u16 pkt_len; 1390 1391 le32_to_cpus(pkt_hdr); 1392 pkt_len = (*pkt_hdr >> 16) & 0x1fff; 1393 1394 /* Check CRC or runt packet */ 1395 if ((*pkt_hdr & AX_RXHDR_CRC_ERR) || 1396 (*pkt_hdr & AX_RXHDR_DROP_ERR)) { 1397 skb_pull(skb, (pkt_len + 7) & 0xFFF8); 1398 pkt_hdr++; 1399 continue; 1400 } 1401 1402 if (pkt_cnt == 0) { 1403 /* Skip IP alignment psudo header */ 1404 skb_pull(skb, 2); 1405 skb->len = pkt_len; 1406 skb_set_tail_pointer(skb, pkt_len); 1407 skb->truesize = pkt_len + sizeof(struct sk_buff); 1408 ax88179_rx_checksum(skb, pkt_hdr); 1409 return 1; 1410 } 1411 1412 ax_skb = skb_clone(skb, GFP_ATOMIC); 1413 if (ax_skb) { 1414 ax_skb->len = pkt_len; 1415 ax_skb->data = skb->data + 2; 1416 skb_set_tail_pointer(ax_skb, pkt_len); 1417 ax_skb->truesize = pkt_len + sizeof(struct sk_buff); 1418 ax88179_rx_checksum(ax_skb, pkt_hdr); 1419 usbnet_skb_return(dev, ax_skb); 1420 } else { 1421 return 0; 1422 } 1423 1424 skb_pull(skb, (pkt_len + 7) & 0xFFF8); 1425 pkt_hdr++; 1426 } 1427 return 1; 1428 } 1429 1430 static struct sk_buff * 1431 ax88179_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags) 1432 { 1433 u32 tx_hdr1, tx_hdr2; 1434 int frame_size = dev->maxpacket; 1435 int mss = skb_shinfo(skb)->gso_size; 1436 int headroom; 1437 1438 tx_hdr1 = skb->len; 1439 tx_hdr2 = mss; 1440 if (((skb->len + 8) % frame_size) == 0) 1441 tx_hdr2 |= 0x80008000; /* Enable padding */ 1442 1443 headroom = skb_headroom(skb) - 8; 1444 1445 if ((skb_header_cloned(skb) || headroom < 0) && 1446 pskb_expand_head(skb, headroom < 0 ? 8 : 0, 0, GFP_ATOMIC)) { 1447 dev_kfree_skb_any(skb); 1448 return NULL; 1449 } 1450 1451 skb_push(skb, 4); 1452 cpu_to_le32s(&tx_hdr2); 1453 skb_copy_to_linear_data(skb, &tx_hdr2, 4); 1454 1455 skb_push(skb, 4); 1456 cpu_to_le32s(&tx_hdr1); 1457 skb_copy_to_linear_data(skb, &tx_hdr1, 4); 1458 1459 return skb; 1460 } 1461 1462 static int ax88179_link_reset(struct usbnet *dev) 1463 { 1464 struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data; 1465 u8 tmp[5], link_sts; 1466 u16 mode, tmp16, delay = HZ / 10; 1467 u32 tmp32 = 0x40000000; 1468 unsigned long jtimeout; 1469 1470 jtimeout = jiffies + delay; 1471 while (tmp32 & 0x40000000) { 1472 mode = 0; 1473 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &mode); 1474 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, 1475 &ax179_data->rxctl); 1476 1477 /*link up, check the usb device control TX FIFO full or empty*/ 1478 ax88179_read_cmd(dev, 0x81, 0x8c, 0, 4, &tmp32); 1479 1480 if (time_after(jiffies, jtimeout)) 1481 return 0; 1482 } 1483 1484 mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 1485 AX_MEDIUM_RXFLOW_CTRLEN; 1486 1487 ax88179_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS, 1488 1, 1, &link_sts); 1489 1490 ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1491 GMII_PHY_PHYSR, 2, &tmp16); 1492 1493 if (!(tmp16 & GMII_PHY_PHYSR_LINK)) { 1494 return 0; 1495 } else if (GMII_PHY_PHYSR_GIGA == (tmp16 & GMII_PHY_PHYSR_SMASK)) { 1496 mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ; 1497 if (dev->net->mtu > 1500) 1498 mode |= AX_MEDIUM_JUMBO_EN; 1499 1500 if (link_sts & AX_USB_SS) 1501 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 1502 else if (link_sts & AX_USB_HS) 1503 memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5); 1504 else 1505 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 1506 } else if (GMII_PHY_PHYSR_100 == (tmp16 & GMII_PHY_PHYSR_SMASK)) { 1507 mode |= AX_MEDIUM_PS; 1508 1509 if (link_sts & (AX_USB_SS | AX_USB_HS)) 1510 memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5); 1511 else 1512 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 1513 } else { 1514 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 1515 } 1516 1517 /* RX bulk configuration */ 1518 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 1519 1520 dev->rx_urb_size = (1024 * (tmp[3] + 2)); 1521 1522 if (tmp16 & GMII_PHY_PHYSR_FULL) 1523 mode |= AX_MEDIUM_FULL_DUPLEX; 1524 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1525 2, 2, &mode); 1526 1527 ax179_data->eee_enabled = ax88179_chk_eee(dev); 1528 1529 netif_carrier_on(dev->net); 1530 1531 return 0; 1532 } 1533 1534 static int ax88179_reset(struct usbnet *dev) 1535 { 1536 u8 buf[5]; 1537 u16 *tmp16; 1538 u8 *tmp; 1539 struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data; 1540 struct ethtool_eee eee_data; 1541 1542 tmp16 = (u16 *)buf; 1543 tmp = (u8 *)buf; 1544 1545 /* Power up ethernet PHY */ 1546 *tmp16 = 0; 1547 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 1548 1549 *tmp16 = AX_PHYPWR_RSTCTL_IPRL; 1550 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 1551 msleep(200); 1552 1553 *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 1554 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); 1555 msleep(100); 1556 1557 /* Ethernet PHY Auto Detach*/ 1558 ax88179_auto_detach(dev, 0); 1559 1560 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, ETH_ALEN, 1561 dev->net->dev_addr); 1562 1563 /* RX bulk configuration */ 1564 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 1565 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 1566 1567 dev->rx_urb_size = 1024 * 20; 1568 1569 *tmp = 0x34; 1570 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); 1571 1572 *tmp = 0x52; 1573 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1574 1, 1, tmp); 1575 1576 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1577 NETIF_F_RXCSUM; 1578 1579 dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1580 NETIF_F_RXCSUM; 1581 1582 /* Enable checksum offload */ 1583 *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 1584 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 1585 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); 1586 1587 *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | 1588 AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 1589 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); 1590 1591 /* Configure RX control register => start operation */ 1592 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 1593 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 1594 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); 1595 1596 *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | 1597 AX_MONITOR_MODE_RWMP; 1598 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); 1599 1600 /* Configure default medium type => giga */ 1601 *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 1602 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX | 1603 AX_MEDIUM_GIGAMODE; 1604 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1605 2, 2, tmp16); 1606 1607 ax88179_led_setting(dev); 1608 1609 ax179_data->eee_enabled = 0; 1610 ax179_data->eee_active = 0; 1611 1612 ax88179_disable_eee(dev); 1613 1614 ax88179_ethtool_get_eee(dev, &eee_data); 1615 eee_data.advertised = 0; 1616 ax88179_ethtool_set_eee(dev, &eee_data); 1617 1618 /* Restart autoneg */ 1619 mii_nway_restart(&dev->mii); 1620 1621 usbnet_link_change(dev, 0, 0); 1622 1623 return 0; 1624 } 1625 1626 static int ax88179_stop(struct usbnet *dev) 1627 { 1628 u16 tmp16; 1629 1630 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1631 2, 2, &tmp16); 1632 tmp16 &= ~AX_MEDIUM_RECEIVE_EN; 1633 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1634 2, 2, &tmp16); 1635 1636 return 0; 1637 } 1638 1639 static const struct driver_info ax88179_info = { 1640 .description = "ASIX AX88179 USB 3.0 Gigabit Ethernet", 1641 .bind = ax88179_bind, 1642 .unbind = ax88179_unbind, 1643 .status = ax88179_status, 1644 .link_reset = ax88179_link_reset, 1645 .reset = ax88179_reset, 1646 .stop = ax88179_stop, 1647 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1648 .rx_fixup = ax88179_rx_fixup, 1649 .tx_fixup = ax88179_tx_fixup, 1650 }; 1651 1652 static const struct driver_info ax88178a_info = { 1653 .description = "ASIX AX88178A USB 2.0 Gigabit Ethernet", 1654 .bind = ax88179_bind, 1655 .unbind = ax88179_unbind, 1656 .status = ax88179_status, 1657 .link_reset = ax88179_link_reset, 1658 .reset = ax88179_reset, 1659 .stop = ax88179_stop, 1660 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1661 .rx_fixup = ax88179_rx_fixup, 1662 .tx_fixup = ax88179_tx_fixup, 1663 }; 1664 1665 static const struct driver_info cypress_GX3_info = { 1666 .description = "Cypress GX3 SuperSpeed to Gigabit Ethernet Controller", 1667 .bind = ax88179_bind, 1668 .unbind = ax88179_unbind, 1669 .status = ax88179_status, 1670 .link_reset = ax88179_link_reset, 1671 .reset = ax88179_reset, 1672 .stop = ax88179_stop, 1673 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1674 .rx_fixup = ax88179_rx_fixup, 1675 .tx_fixup = ax88179_tx_fixup, 1676 }; 1677 1678 static const struct driver_info dlink_dub1312_info = { 1679 .description = "D-Link DUB-1312 USB 3.0 to Gigabit Ethernet Adapter", 1680 .bind = ax88179_bind, 1681 .unbind = ax88179_unbind, 1682 .status = ax88179_status, 1683 .link_reset = ax88179_link_reset, 1684 .reset = ax88179_reset, 1685 .stop = ax88179_stop, 1686 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1687 .rx_fixup = ax88179_rx_fixup, 1688 .tx_fixup = ax88179_tx_fixup, 1689 }; 1690 1691 static const struct driver_info sitecom_info = { 1692 .description = "Sitecom USB 3.0 to Gigabit Adapter", 1693 .bind = ax88179_bind, 1694 .unbind = ax88179_unbind, 1695 .status = ax88179_status, 1696 .link_reset = ax88179_link_reset, 1697 .reset = ax88179_reset, 1698 .stop = ax88179_stop, 1699 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1700 .rx_fixup = ax88179_rx_fixup, 1701 .tx_fixup = ax88179_tx_fixup, 1702 }; 1703 1704 static const struct driver_info samsung_info = { 1705 .description = "Samsung USB Ethernet Adapter", 1706 .bind = ax88179_bind, 1707 .unbind = ax88179_unbind, 1708 .status = ax88179_status, 1709 .link_reset = ax88179_link_reset, 1710 .reset = ax88179_reset, 1711 .stop = ax88179_stop, 1712 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1713 .rx_fixup = ax88179_rx_fixup, 1714 .tx_fixup = ax88179_tx_fixup, 1715 }; 1716 1717 static const struct driver_info lenovo_info = { 1718 .description = "Lenovo OneLinkDock Gigabit LAN", 1719 .bind = ax88179_bind, 1720 .unbind = ax88179_unbind, 1721 .status = ax88179_status, 1722 .link_reset = ax88179_link_reset, 1723 .reset = ax88179_reset, 1724 .stop = ax88179_stop, 1725 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1726 .rx_fixup = ax88179_rx_fixup, 1727 .tx_fixup = ax88179_tx_fixup, 1728 }; 1729 1730 static const struct driver_info belkin_info = { 1731 .description = "Belkin USB Ethernet Adapter", 1732 .bind = ax88179_bind, 1733 .unbind = ax88179_unbind, 1734 .status = ax88179_status, 1735 .link_reset = ax88179_link_reset, 1736 .reset = ax88179_reset, 1737 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1738 .rx_fixup = ax88179_rx_fixup, 1739 .tx_fixup = ax88179_tx_fixup, 1740 }; 1741 1742 static const struct usb_device_id products[] = { 1743 { 1744 /* ASIX AX88179 10/100/1000 */ 1745 USB_DEVICE(0x0b95, 0x1790), 1746 .driver_info = (unsigned long)&ax88179_info, 1747 }, { 1748 /* ASIX AX88178A 10/100/1000 */ 1749 USB_DEVICE(0x0b95, 0x178a), 1750 .driver_info = (unsigned long)&ax88178a_info, 1751 }, { 1752 /* Cypress GX3 SuperSpeed to Gigabit Ethernet Bridge Controller */ 1753 USB_DEVICE(0x04b4, 0x3610), 1754 .driver_info = (unsigned long)&cypress_GX3_info, 1755 }, { 1756 /* D-Link DUB-1312 USB 3.0 to Gigabit Ethernet Adapter */ 1757 USB_DEVICE(0x2001, 0x4a00), 1758 .driver_info = (unsigned long)&dlink_dub1312_info, 1759 }, { 1760 /* Sitecom USB 3.0 to Gigabit Adapter */ 1761 USB_DEVICE(0x0df6, 0x0072), 1762 .driver_info = (unsigned long)&sitecom_info, 1763 }, { 1764 /* Samsung USB Ethernet Adapter */ 1765 USB_DEVICE(0x04e8, 0xa100), 1766 .driver_info = (unsigned long)&samsung_info, 1767 }, { 1768 /* Lenovo OneLinkDock Gigabit LAN */ 1769 USB_DEVICE(0x17ef, 0x304b), 1770 .driver_info = (unsigned long)&lenovo_info, 1771 }, { 1772 /* Belkin B2B128 USB 3.0 Hub + Gigabit Ethernet Adapter */ 1773 USB_DEVICE(0x050d, 0x0128), 1774 .driver_info = (unsigned long)&belkin_info, 1775 }, 1776 { }, 1777 }; 1778 MODULE_DEVICE_TABLE(usb, products); 1779 1780 static struct usb_driver ax88179_178a_driver = { 1781 .name = "ax88179_178a", 1782 .id_table = products, 1783 .probe = usbnet_probe, 1784 .suspend = ax88179_suspend, 1785 .resume = ax88179_resume, 1786 .reset_resume = ax88179_resume, 1787 .disconnect = usbnet_disconnect, 1788 .supports_autosuspend = 1, 1789 .disable_hub_initiated_lpm = 1, 1790 }; 1791 1792 module_usb_driver(ax88179_178a_driver); 1793 1794 MODULE_DESCRIPTION("ASIX AX88179/178A based USB 3.0/2.0 Gigabit Ethernet Devices"); 1795 MODULE_LICENSE("GPL"); 1796