1 /* 2 * ASIX AX88179/178A USB 3.0/2.0 to Gigabit Ethernet Devices 3 * 4 * Copyright (C) 2011-2013 ASIX 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21 #include <linux/module.h> 22 #include <linux/etherdevice.h> 23 #include <linux/mii.h> 24 #include <linux/usb.h> 25 #include <linux/crc32.h> 26 #include <linux/usb/usbnet.h> 27 28 #define AX88179_PHY_ID 0x03 29 #define AX_EEPROM_LEN 0x100 30 #define AX88179_EEPROM_MAGIC 0x17900b95 31 #define AX_MCAST_FLTSIZE 8 32 #define AX_MAX_MCAST 64 33 #define AX_INT_PPLS_LINK ((u32)BIT(16)) 34 #define AX_RXHDR_L4_TYPE_MASK 0x1c 35 #define AX_RXHDR_L4_TYPE_UDP 4 36 #define AX_RXHDR_L4_TYPE_TCP 16 37 #define AX_RXHDR_L3CSUM_ERR 2 38 #define AX_RXHDR_L4CSUM_ERR 1 39 #define AX_RXHDR_CRC_ERR ((u32)BIT(29)) 40 #define AX_RXHDR_DROP_ERR ((u32)BIT(31)) 41 #define AX_ACCESS_MAC 0x01 42 #define AX_ACCESS_PHY 0x02 43 #define AX_ACCESS_EEPROM 0x04 44 #define AX_ACCESS_EFUS 0x05 45 #define AX_PAUSE_WATERLVL_HIGH 0x54 46 #define AX_PAUSE_WATERLVL_LOW 0x55 47 48 #define PHYSICAL_LINK_STATUS 0x02 49 #define AX_USB_SS 0x04 50 #define AX_USB_HS 0x02 51 52 #define GENERAL_STATUS 0x03 53 /* Check AX88179 version. UA1:Bit2 = 0, UA2:Bit2 = 1 */ 54 #define AX_SECLD 0x04 55 56 #define AX_SROM_ADDR 0x07 57 #define AX_SROM_CMD 0x0a 58 #define EEP_RD 0x04 59 #define EEP_BUSY 0x10 60 61 #define AX_SROM_DATA_LOW 0x08 62 #define AX_SROM_DATA_HIGH 0x09 63 64 #define AX_RX_CTL 0x0b 65 #define AX_RX_CTL_DROPCRCERR 0x0100 66 #define AX_RX_CTL_IPE 0x0200 67 #define AX_RX_CTL_START 0x0080 68 #define AX_RX_CTL_AP 0x0020 69 #define AX_RX_CTL_AM 0x0010 70 #define AX_RX_CTL_AB 0x0008 71 #define AX_RX_CTL_AMALL 0x0002 72 #define AX_RX_CTL_PRO 0x0001 73 #define AX_RX_CTL_STOP 0x0000 74 75 #define AX_NODE_ID 0x10 76 #define AX_MULFLTARY 0x16 77 78 #define AX_MEDIUM_STATUS_MODE 0x22 79 #define AX_MEDIUM_GIGAMODE 0x01 80 #define AX_MEDIUM_FULL_DUPLEX 0x02 81 #define AX_MEDIUM_EN_125MHZ 0x08 82 #define AX_MEDIUM_RXFLOW_CTRLEN 0x10 83 #define AX_MEDIUM_TXFLOW_CTRLEN 0x20 84 #define AX_MEDIUM_RECEIVE_EN 0x100 85 #define AX_MEDIUM_PS 0x200 86 #define AX_MEDIUM_JUMBO_EN 0x8040 87 88 #define AX_MONITOR_MOD 0x24 89 #define AX_MONITOR_MODE_RWLC 0x02 90 #define AX_MONITOR_MODE_RWMP 0x04 91 #define AX_MONITOR_MODE_PMEPOL 0x20 92 #define AX_MONITOR_MODE_PMETYPE 0x40 93 94 #define AX_GPIO_CTRL 0x25 95 #define AX_GPIO_CTRL_GPIO3EN 0x80 96 #define AX_GPIO_CTRL_GPIO2EN 0x40 97 #define AX_GPIO_CTRL_GPIO1EN 0x20 98 99 #define AX_PHYPWR_RSTCTL 0x26 100 #define AX_PHYPWR_RSTCTL_BZ 0x0010 101 #define AX_PHYPWR_RSTCTL_IPRL 0x0020 102 #define AX_PHYPWR_RSTCTL_AT 0x1000 103 104 #define AX_RX_BULKIN_QCTRL 0x2e 105 #define AX_CLK_SELECT 0x33 106 #define AX_CLK_SELECT_BCS 0x01 107 #define AX_CLK_SELECT_ACS 0x02 108 #define AX_CLK_SELECT_ULR 0x08 109 110 #define AX_RXCOE_CTL 0x34 111 #define AX_RXCOE_IP 0x01 112 #define AX_RXCOE_TCP 0x02 113 #define AX_RXCOE_UDP 0x04 114 #define AX_RXCOE_TCPV6 0x20 115 #define AX_RXCOE_UDPV6 0x40 116 117 #define AX_TXCOE_CTL 0x35 118 #define AX_TXCOE_IP 0x01 119 #define AX_TXCOE_TCP 0x02 120 #define AX_TXCOE_UDP 0x04 121 #define AX_TXCOE_TCPV6 0x20 122 #define AX_TXCOE_UDPV6 0x40 123 124 #define AX_LEDCTRL 0x73 125 126 #define GMII_PHY_PHYSR 0x11 127 #define GMII_PHY_PHYSR_SMASK 0xc000 128 #define GMII_PHY_PHYSR_GIGA 0x8000 129 #define GMII_PHY_PHYSR_100 0x4000 130 #define GMII_PHY_PHYSR_FULL 0x2000 131 #define GMII_PHY_PHYSR_LINK 0x400 132 133 #define GMII_LED_ACT 0x1a 134 #define GMII_LED_ACTIVE_MASK 0xff8f 135 #define GMII_LED0_ACTIVE BIT(4) 136 #define GMII_LED1_ACTIVE BIT(5) 137 #define GMII_LED2_ACTIVE BIT(6) 138 139 #define GMII_LED_LINK 0x1c 140 #define GMII_LED_LINK_MASK 0xf888 141 #define GMII_LED0_LINK_10 BIT(0) 142 #define GMII_LED0_LINK_100 BIT(1) 143 #define GMII_LED0_LINK_1000 BIT(2) 144 #define GMII_LED1_LINK_10 BIT(4) 145 #define GMII_LED1_LINK_100 BIT(5) 146 #define GMII_LED1_LINK_1000 BIT(6) 147 #define GMII_LED2_LINK_10 BIT(8) 148 #define GMII_LED2_LINK_100 BIT(9) 149 #define GMII_LED2_LINK_1000 BIT(10) 150 #define LED0_ACTIVE BIT(0) 151 #define LED0_LINK_10 BIT(1) 152 #define LED0_LINK_100 BIT(2) 153 #define LED0_LINK_1000 BIT(3) 154 #define LED0_FD BIT(4) 155 #define LED0_USB3_MASK 0x001f 156 #define LED1_ACTIVE BIT(5) 157 #define LED1_LINK_10 BIT(6) 158 #define LED1_LINK_100 BIT(7) 159 #define LED1_LINK_1000 BIT(8) 160 #define LED1_FD BIT(9) 161 #define LED1_USB3_MASK 0x03e0 162 #define LED2_ACTIVE BIT(10) 163 #define LED2_LINK_1000 BIT(13) 164 #define LED2_LINK_100 BIT(12) 165 #define LED2_LINK_10 BIT(11) 166 #define LED2_FD BIT(14) 167 #define LED_VALID BIT(15) 168 #define LED2_USB3_MASK 0x7c00 169 170 #define GMII_PHYPAGE 0x1e 171 #define GMII_PHY_PAGE_SELECT 0x1f 172 #define GMII_PHY_PGSEL_EXT 0x0007 173 #define GMII_PHY_PGSEL_PAGE0 0x0000 174 175 struct ax88179_data { 176 u16 rxctl; 177 u16 reserved; 178 }; 179 180 struct ax88179_int_data { 181 __le32 intdata1; 182 __le32 intdata2; 183 }; 184 185 static const struct { 186 unsigned char ctrl, timer_l, timer_h, size, ifg; 187 } AX88179_BULKIN_SIZE[] = { 188 {7, 0x4f, 0, 0x12, 0xff}, 189 {7, 0x20, 3, 0x16, 0xff}, 190 {7, 0xae, 7, 0x18, 0xff}, 191 {7, 0xcc, 0x4c, 0x18, 8}, 192 }; 193 194 static int __ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 195 u16 size, void *data, int in_pm) 196 { 197 int ret; 198 int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16); 199 200 BUG_ON(!dev); 201 202 if (!in_pm) 203 fn = usbnet_read_cmd; 204 else 205 fn = usbnet_read_cmd_nopm; 206 207 ret = fn(dev, cmd, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 208 value, index, data, size); 209 210 if (unlikely(ret < 0)) 211 netdev_warn(dev->net, "Failed to read reg index 0x%04x: %d\n", 212 index, ret); 213 214 return ret; 215 } 216 217 static int __ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 218 u16 size, void *data, int in_pm) 219 { 220 int ret; 221 int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16); 222 223 BUG_ON(!dev); 224 225 if (!in_pm) 226 fn = usbnet_write_cmd; 227 else 228 fn = usbnet_write_cmd_nopm; 229 230 ret = fn(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 231 value, index, data, size); 232 233 if (unlikely(ret < 0)) 234 netdev_warn(dev->net, "Failed to write reg index 0x%04x: %d\n", 235 index, ret); 236 237 return ret; 238 } 239 240 static void ax88179_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, 241 u16 index, u16 size, void *data) 242 { 243 u16 buf; 244 245 if (2 == size) { 246 buf = *((u16 *)data); 247 cpu_to_le16s(&buf); 248 usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | 249 USB_RECIP_DEVICE, value, index, &buf, 250 size); 251 } else { 252 usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | 253 USB_RECIP_DEVICE, value, index, data, 254 size); 255 } 256 } 257 258 static int ax88179_read_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value, 259 u16 index, u16 size, void *data) 260 { 261 int ret; 262 263 if (2 == size) { 264 u16 buf; 265 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1); 266 le16_to_cpus(&buf); 267 *((u16 *)data) = buf; 268 } else if (4 == size) { 269 u32 buf; 270 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1); 271 le32_to_cpus(&buf); 272 *((u32 *)data) = buf; 273 } else { 274 ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 1); 275 } 276 277 return ret; 278 } 279 280 static int ax88179_write_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value, 281 u16 index, u16 size, void *data) 282 { 283 int ret; 284 285 if (2 == size) { 286 u16 buf; 287 buf = *((u16 *)data); 288 cpu_to_le16s(&buf); 289 ret = __ax88179_write_cmd(dev, cmd, value, index, 290 size, &buf, 1); 291 } else { 292 ret = __ax88179_write_cmd(dev, cmd, value, index, 293 size, data, 1); 294 } 295 296 return ret; 297 } 298 299 static int ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 300 u16 size, void *data) 301 { 302 int ret; 303 304 if (2 == size) { 305 u16 buf; 306 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0); 307 le16_to_cpus(&buf); 308 *((u16 *)data) = buf; 309 } else if (4 == size) { 310 u32 buf; 311 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0); 312 le32_to_cpus(&buf); 313 *((u32 *)data) = buf; 314 } else { 315 ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 0); 316 } 317 318 return ret; 319 } 320 321 static int ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 322 u16 size, void *data) 323 { 324 int ret; 325 326 if (2 == size) { 327 u16 buf; 328 buf = *((u16 *)data); 329 cpu_to_le16s(&buf); 330 ret = __ax88179_write_cmd(dev, cmd, value, index, 331 size, &buf, 0); 332 } else { 333 ret = __ax88179_write_cmd(dev, cmd, value, index, 334 size, data, 0); 335 } 336 337 return ret; 338 } 339 340 static void ax88179_status(struct usbnet *dev, struct urb *urb) 341 { 342 struct ax88179_int_data *event; 343 u32 link; 344 345 if (urb->actual_length < 8) 346 return; 347 348 event = urb->transfer_buffer; 349 le32_to_cpus((void *)&event->intdata1); 350 351 link = (((__force u32)event->intdata1) & AX_INT_PPLS_LINK) >> 16; 352 353 if (netif_carrier_ok(dev->net) != link) { 354 usbnet_link_change(dev, link, 1); 355 netdev_info(dev->net, "ax88179 - Link status is: %d\n", link); 356 } 357 } 358 359 static int ax88179_mdio_read(struct net_device *netdev, int phy_id, int loc) 360 { 361 struct usbnet *dev = netdev_priv(netdev); 362 u16 res; 363 364 ax88179_read_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res); 365 return res; 366 } 367 368 static void ax88179_mdio_write(struct net_device *netdev, int phy_id, int loc, 369 int val) 370 { 371 struct usbnet *dev = netdev_priv(netdev); 372 u16 res = (u16) val; 373 374 ax88179_write_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res); 375 } 376 377 static int ax88179_suspend(struct usb_interface *intf, pm_message_t message) 378 { 379 struct usbnet *dev = usb_get_intfdata(intf); 380 u16 tmp16; 381 u8 tmp8; 382 383 usbnet_suspend(intf, message); 384 385 /* Disable RX path */ 386 ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 387 2, 2, &tmp16); 388 tmp16 &= ~AX_MEDIUM_RECEIVE_EN; 389 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 390 2, 2, &tmp16); 391 392 /* Force bulk-in zero length */ 393 ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 394 2, 2, &tmp16); 395 396 tmp16 |= AX_PHYPWR_RSTCTL_BZ | AX_PHYPWR_RSTCTL_IPRL; 397 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 398 2, 2, &tmp16); 399 400 /* change clock */ 401 tmp8 = 0; 402 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 403 404 /* Configure RX control register => stop operation */ 405 tmp16 = AX_RX_CTL_STOP; 406 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16); 407 408 return 0; 409 } 410 411 /* This function is used to enable the autodetach function. */ 412 /* This function is determined by offset 0x43 of EEPROM */ 413 static int ax88179_auto_detach(struct usbnet *dev, int in_pm) 414 { 415 u16 tmp16; 416 u8 tmp8; 417 int (*fnr)(struct usbnet *, u8, u16, u16, u16, void *); 418 int (*fnw)(struct usbnet *, u8, u16, u16, u16, void *); 419 420 if (!in_pm) { 421 fnr = ax88179_read_cmd; 422 fnw = ax88179_write_cmd; 423 } else { 424 fnr = ax88179_read_cmd_nopm; 425 fnw = ax88179_write_cmd_nopm; 426 } 427 428 if (fnr(dev, AX_ACCESS_EEPROM, 0x43, 1, 2, &tmp16) < 0) 429 return 0; 430 431 if ((tmp16 == 0xFFFF) || (!(tmp16 & 0x0100))) 432 return 0; 433 434 /* Enable Auto Detach bit */ 435 tmp8 = 0; 436 fnr(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 437 tmp8 |= AX_CLK_SELECT_ULR; 438 fnw(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 439 440 fnr(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16); 441 tmp16 |= AX_PHYPWR_RSTCTL_AT; 442 fnw(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16); 443 444 return 0; 445 } 446 447 static int ax88179_resume(struct usb_interface *intf) 448 { 449 struct usbnet *dev = usb_get_intfdata(intf); 450 u16 tmp16; 451 u8 tmp8; 452 453 usbnet_link_change(dev, 0, 0); 454 455 /* Power up ethernet PHY */ 456 tmp16 = 0; 457 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 458 2, 2, &tmp16); 459 udelay(1000); 460 461 tmp16 = AX_PHYPWR_RSTCTL_IPRL; 462 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 463 2, 2, &tmp16); 464 msleep(200); 465 466 /* Ethernet PHY Auto Detach*/ 467 ax88179_auto_detach(dev, 1); 468 469 /* Enable clock */ 470 ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 471 tmp8 |= AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 472 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 473 msleep(100); 474 475 /* Configure RX control register => start operation */ 476 tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 477 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 478 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16); 479 480 return usbnet_resume(intf); 481 } 482 483 static void 484 ax88179_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) 485 { 486 struct usbnet *dev = netdev_priv(net); 487 u8 opt; 488 489 if (ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 490 1, 1, &opt) < 0) { 491 wolinfo->supported = 0; 492 wolinfo->wolopts = 0; 493 return; 494 } 495 496 wolinfo->supported = WAKE_PHY | WAKE_MAGIC; 497 wolinfo->wolopts = 0; 498 if (opt & AX_MONITOR_MODE_RWLC) 499 wolinfo->wolopts |= WAKE_PHY; 500 if (opt & AX_MONITOR_MODE_RWMP) 501 wolinfo->wolopts |= WAKE_MAGIC; 502 } 503 504 static int 505 ax88179_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) 506 { 507 struct usbnet *dev = netdev_priv(net); 508 u8 opt = 0; 509 510 if (wolinfo->wolopts & WAKE_PHY) 511 opt |= AX_MONITOR_MODE_RWLC; 512 if (wolinfo->wolopts & WAKE_MAGIC) 513 opt |= AX_MONITOR_MODE_RWMP; 514 515 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 516 1, 1, &opt) < 0) 517 return -EINVAL; 518 519 return 0; 520 } 521 522 static int ax88179_get_eeprom_len(struct net_device *net) 523 { 524 return AX_EEPROM_LEN; 525 } 526 527 static int 528 ax88179_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom, 529 u8 *data) 530 { 531 struct usbnet *dev = netdev_priv(net); 532 u16 *eeprom_buff; 533 int first_word, last_word; 534 int i, ret; 535 536 if (eeprom->len == 0) 537 return -EINVAL; 538 539 eeprom->magic = AX88179_EEPROM_MAGIC; 540 541 first_word = eeprom->offset >> 1; 542 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 543 eeprom_buff = kmalloc(sizeof(u16) * (last_word - first_word + 1), 544 GFP_KERNEL); 545 if (!eeprom_buff) 546 return -ENOMEM; 547 548 /* ax88179/178A returns 2 bytes from eeprom on read */ 549 for (i = first_word; i <= last_word; i++) { 550 ret = __ax88179_read_cmd(dev, AX_ACCESS_EEPROM, i, 1, 2, 551 &eeprom_buff[i - first_word], 552 0); 553 if (ret < 0) { 554 kfree(eeprom_buff); 555 return -EIO; 556 } 557 } 558 559 memcpy(data, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); 560 kfree(eeprom_buff); 561 return 0; 562 } 563 564 static int ax88179_get_settings(struct net_device *net, struct ethtool_cmd *cmd) 565 { 566 struct usbnet *dev = netdev_priv(net); 567 return mii_ethtool_gset(&dev->mii, cmd); 568 } 569 570 static int ax88179_set_settings(struct net_device *net, struct ethtool_cmd *cmd) 571 { 572 struct usbnet *dev = netdev_priv(net); 573 return mii_ethtool_sset(&dev->mii, cmd); 574 } 575 576 577 static int ax88179_ioctl(struct net_device *net, struct ifreq *rq, int cmd) 578 { 579 struct usbnet *dev = netdev_priv(net); 580 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); 581 } 582 583 static const struct ethtool_ops ax88179_ethtool_ops = { 584 .get_link = ethtool_op_get_link, 585 .get_msglevel = usbnet_get_msglevel, 586 .set_msglevel = usbnet_set_msglevel, 587 .get_wol = ax88179_get_wol, 588 .set_wol = ax88179_set_wol, 589 .get_eeprom_len = ax88179_get_eeprom_len, 590 .get_eeprom = ax88179_get_eeprom, 591 .get_settings = ax88179_get_settings, 592 .set_settings = ax88179_set_settings, 593 .nway_reset = usbnet_nway_reset, 594 }; 595 596 static void ax88179_set_multicast(struct net_device *net) 597 { 598 struct usbnet *dev = netdev_priv(net); 599 struct ax88179_data *data = (struct ax88179_data *)dev->data; 600 u8 *m_filter = ((u8 *)dev->data) + 12; 601 602 data->rxctl = (AX_RX_CTL_START | AX_RX_CTL_AB | AX_RX_CTL_IPE); 603 604 if (net->flags & IFF_PROMISC) { 605 data->rxctl |= AX_RX_CTL_PRO; 606 } else if (net->flags & IFF_ALLMULTI || 607 netdev_mc_count(net) > AX_MAX_MCAST) { 608 data->rxctl |= AX_RX_CTL_AMALL; 609 } else if (netdev_mc_empty(net)) { 610 /* just broadcast and directed */ 611 } else { 612 /* We use the 20 byte dev->data for our 8 byte filter buffer 613 * to avoid allocating memory that is tricky to free later 614 */ 615 u32 crc_bits; 616 struct netdev_hw_addr *ha; 617 618 memset(m_filter, 0, AX_MCAST_FLTSIZE); 619 620 netdev_for_each_mc_addr(ha, net) { 621 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; 622 *(m_filter + (crc_bits >> 3)) |= (1 << (crc_bits & 7)); 623 } 624 625 ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_MULFLTARY, 626 AX_MCAST_FLTSIZE, AX_MCAST_FLTSIZE, 627 m_filter); 628 629 data->rxctl |= AX_RX_CTL_AM; 630 } 631 632 ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_RX_CTL, 633 2, 2, &data->rxctl); 634 } 635 636 static int 637 ax88179_set_features(struct net_device *net, netdev_features_t features) 638 { 639 u8 tmp; 640 struct usbnet *dev = netdev_priv(net); 641 netdev_features_t changed = net->features ^ features; 642 643 if (changed & NETIF_F_IP_CSUM) { 644 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 645 tmp ^= AX_TXCOE_TCP | AX_TXCOE_UDP; 646 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 647 } 648 649 if (changed & NETIF_F_IPV6_CSUM) { 650 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 651 tmp ^= AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 652 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 653 } 654 655 if (changed & NETIF_F_RXCSUM) { 656 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp); 657 tmp ^= AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 658 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 659 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp); 660 } 661 662 return 0; 663 } 664 665 static int ax88179_change_mtu(struct net_device *net, int new_mtu) 666 { 667 struct usbnet *dev = netdev_priv(net); 668 u16 tmp16; 669 670 if (new_mtu <= 0 || new_mtu > 4088) 671 return -EINVAL; 672 673 net->mtu = new_mtu; 674 dev->hard_mtu = net->mtu + net->hard_header_len; 675 676 if (net->mtu > 1500) { 677 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 678 2, 2, &tmp16); 679 tmp16 |= AX_MEDIUM_JUMBO_EN; 680 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 681 2, 2, &tmp16); 682 } else { 683 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 684 2, 2, &tmp16); 685 tmp16 &= ~AX_MEDIUM_JUMBO_EN; 686 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 687 2, 2, &tmp16); 688 } 689 690 /* max qlen depend on hard_mtu and rx_urb_size */ 691 usbnet_update_max_qlen(dev); 692 693 return 0; 694 } 695 696 static int ax88179_set_mac_addr(struct net_device *net, void *p) 697 { 698 struct usbnet *dev = netdev_priv(net); 699 struct sockaddr *addr = p; 700 701 if (netif_running(net)) 702 return -EBUSY; 703 if (!is_valid_ether_addr(addr->sa_data)) 704 return -EADDRNOTAVAIL; 705 706 memcpy(net->dev_addr, addr->sa_data, ETH_ALEN); 707 708 /* Set the MAC address */ 709 return ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, 710 ETH_ALEN, net->dev_addr); 711 } 712 713 static const struct net_device_ops ax88179_netdev_ops = { 714 .ndo_open = usbnet_open, 715 .ndo_stop = usbnet_stop, 716 .ndo_start_xmit = usbnet_start_xmit, 717 .ndo_tx_timeout = usbnet_tx_timeout, 718 .ndo_change_mtu = ax88179_change_mtu, 719 .ndo_set_mac_address = ax88179_set_mac_addr, 720 .ndo_validate_addr = eth_validate_addr, 721 .ndo_do_ioctl = ax88179_ioctl, 722 .ndo_set_rx_mode = ax88179_set_multicast, 723 .ndo_set_features = ax88179_set_features, 724 }; 725 726 static int ax88179_check_eeprom(struct usbnet *dev) 727 { 728 u8 i, buf, eeprom[20]; 729 u16 csum, delay = HZ / 10; 730 unsigned long jtimeout; 731 732 /* Read EEPROM content */ 733 for (i = 0; i < 6; i++) { 734 buf = i; 735 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR, 736 1, 1, &buf) < 0) 737 return -EINVAL; 738 739 buf = EEP_RD; 740 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 741 1, 1, &buf) < 0) 742 return -EINVAL; 743 744 jtimeout = jiffies + delay; 745 do { 746 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 747 1, 1, &buf); 748 749 if (time_after(jiffies, jtimeout)) 750 return -EINVAL; 751 752 } while (buf & EEP_BUSY); 753 754 __ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW, 755 2, 2, &eeprom[i * 2], 0); 756 757 if ((i == 0) && (eeprom[0] == 0xFF)) 758 return -EINVAL; 759 } 760 761 csum = eeprom[6] + eeprom[7] + eeprom[8] + eeprom[9]; 762 csum = (csum >> 8) + (csum & 0xff); 763 if ((csum + eeprom[10]) != 0xff) 764 return -EINVAL; 765 766 return 0; 767 } 768 769 static int ax88179_check_efuse(struct usbnet *dev, u16 *ledmode) 770 { 771 u8 i; 772 u8 efuse[64]; 773 u16 csum = 0; 774 775 if (ax88179_read_cmd(dev, AX_ACCESS_EFUS, 0, 64, 64, efuse) < 0) 776 return -EINVAL; 777 778 if (*efuse == 0xFF) 779 return -EINVAL; 780 781 for (i = 0; i < 64; i++) 782 csum = csum + efuse[i]; 783 784 while (csum > 255) 785 csum = (csum & 0x00FF) + ((csum >> 8) & 0x00FF); 786 787 if (csum != 0xFF) 788 return -EINVAL; 789 790 *ledmode = (efuse[51] << 8) | efuse[52]; 791 792 return 0; 793 } 794 795 static int ax88179_convert_old_led(struct usbnet *dev, u16 *ledvalue) 796 { 797 u16 led; 798 799 /* Loaded the old eFuse LED Mode */ 800 if (ax88179_read_cmd(dev, AX_ACCESS_EEPROM, 0x3C, 1, 2, &led) < 0) 801 return -EINVAL; 802 803 led >>= 8; 804 switch (led) { 805 case 0xFF: 806 led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 | 807 LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 | 808 LED2_LINK_100 | LED2_LINK_1000 | LED_VALID; 809 break; 810 case 0xFE: 811 led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 | LED_VALID; 812 break; 813 case 0xFD: 814 led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 | 815 LED2_LINK_10 | LED_VALID; 816 break; 817 case 0xFC: 818 led = LED0_ACTIVE | LED1_ACTIVE | LED1_LINK_1000 | LED2_ACTIVE | 819 LED2_LINK_100 | LED2_LINK_10 | LED_VALID; 820 break; 821 default: 822 led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 | 823 LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 | 824 LED2_LINK_100 | LED2_LINK_1000 | LED_VALID; 825 break; 826 } 827 828 *ledvalue = led; 829 830 return 0; 831 } 832 833 static int ax88179_led_setting(struct usbnet *dev) 834 { 835 u8 ledfd, value = 0; 836 u16 tmp, ledact, ledlink, ledvalue = 0, delay = HZ / 10; 837 unsigned long jtimeout; 838 839 /* Check AX88179 version. UA1 or UA2*/ 840 ax88179_read_cmd(dev, AX_ACCESS_MAC, GENERAL_STATUS, 1, 1, &value); 841 842 if (!(value & AX_SECLD)) { /* UA1 */ 843 value = AX_GPIO_CTRL_GPIO3EN | AX_GPIO_CTRL_GPIO2EN | 844 AX_GPIO_CTRL_GPIO1EN; 845 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_GPIO_CTRL, 846 1, 1, &value) < 0) 847 return -EINVAL; 848 } 849 850 /* Check EEPROM */ 851 if (!ax88179_check_eeprom(dev)) { 852 value = 0x42; 853 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR, 854 1, 1, &value) < 0) 855 return -EINVAL; 856 857 value = EEP_RD; 858 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 859 1, 1, &value) < 0) 860 return -EINVAL; 861 862 jtimeout = jiffies + delay; 863 do { 864 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 865 1, 1, &value); 866 867 if (time_after(jiffies, jtimeout)) 868 return -EINVAL; 869 870 } while (value & EEP_BUSY); 871 872 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_HIGH, 873 1, 1, &value); 874 ledvalue = (value << 8); 875 876 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW, 877 1, 1, &value); 878 ledvalue |= value; 879 880 /* load internal ROM for defaule setting */ 881 if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0)) 882 ax88179_convert_old_led(dev, &ledvalue); 883 884 } else if (!ax88179_check_efuse(dev, &ledvalue)) { 885 if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0)) 886 ax88179_convert_old_led(dev, &ledvalue); 887 } else { 888 ax88179_convert_old_led(dev, &ledvalue); 889 } 890 891 tmp = GMII_PHY_PGSEL_EXT; 892 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 893 GMII_PHY_PAGE_SELECT, 2, &tmp); 894 895 tmp = 0x2c; 896 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 897 GMII_PHYPAGE, 2, &tmp); 898 899 ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 900 GMII_LED_ACT, 2, &ledact); 901 902 ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 903 GMII_LED_LINK, 2, &ledlink); 904 905 ledact &= GMII_LED_ACTIVE_MASK; 906 ledlink &= GMII_LED_LINK_MASK; 907 908 if (ledvalue & LED0_ACTIVE) 909 ledact |= GMII_LED0_ACTIVE; 910 911 if (ledvalue & LED1_ACTIVE) 912 ledact |= GMII_LED1_ACTIVE; 913 914 if (ledvalue & LED2_ACTIVE) 915 ledact |= GMII_LED2_ACTIVE; 916 917 if (ledvalue & LED0_LINK_10) 918 ledlink |= GMII_LED0_LINK_10; 919 920 if (ledvalue & LED1_LINK_10) 921 ledlink |= GMII_LED1_LINK_10; 922 923 if (ledvalue & LED2_LINK_10) 924 ledlink |= GMII_LED2_LINK_10; 925 926 if (ledvalue & LED0_LINK_100) 927 ledlink |= GMII_LED0_LINK_100; 928 929 if (ledvalue & LED1_LINK_100) 930 ledlink |= GMII_LED1_LINK_100; 931 932 if (ledvalue & LED2_LINK_100) 933 ledlink |= GMII_LED2_LINK_100; 934 935 if (ledvalue & LED0_LINK_1000) 936 ledlink |= GMII_LED0_LINK_1000; 937 938 if (ledvalue & LED1_LINK_1000) 939 ledlink |= GMII_LED1_LINK_1000; 940 941 if (ledvalue & LED2_LINK_1000) 942 ledlink |= GMII_LED2_LINK_1000; 943 944 tmp = ledact; 945 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 946 GMII_LED_ACT, 2, &tmp); 947 948 tmp = ledlink; 949 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 950 GMII_LED_LINK, 2, &tmp); 951 952 tmp = GMII_PHY_PGSEL_PAGE0; 953 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 954 GMII_PHY_PAGE_SELECT, 2, &tmp); 955 956 /* LED full duplex setting */ 957 ledfd = 0; 958 if (ledvalue & LED0_FD) 959 ledfd |= 0x01; 960 else if ((ledvalue & LED0_USB3_MASK) == 0) 961 ledfd |= 0x02; 962 963 if (ledvalue & LED1_FD) 964 ledfd |= 0x04; 965 else if ((ledvalue & LED1_USB3_MASK) == 0) 966 ledfd |= 0x08; 967 968 if (ledvalue & LED2_FD) 969 ledfd |= 0x10; 970 else if ((ledvalue & LED2_USB3_MASK) == 0) 971 ledfd |= 0x20; 972 973 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_LEDCTRL, 1, 1, &ledfd); 974 975 return 0; 976 } 977 978 static int ax88179_bind(struct usbnet *dev, struct usb_interface *intf) 979 { 980 u8 buf[5]; 981 u16 *tmp16; 982 u8 *tmp; 983 struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data; 984 985 usbnet_get_endpoints(dev, intf); 986 987 tmp16 = (u16 *)buf; 988 tmp = (u8 *)buf; 989 990 memset(ax179_data, 0, sizeof(*ax179_data)); 991 992 /* Power up ethernet PHY */ 993 *tmp16 = 0; 994 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 995 *tmp16 = AX_PHYPWR_RSTCTL_IPRL; 996 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 997 msleep(200); 998 999 *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 1000 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); 1001 msleep(100); 1002 1003 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, 1004 ETH_ALEN, dev->net->dev_addr); 1005 memcpy(dev->net->perm_addr, dev->net->dev_addr, ETH_ALEN); 1006 1007 /* RX bulk configuration */ 1008 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 1009 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 1010 1011 dev->rx_urb_size = 1024 * 20; 1012 1013 *tmp = 0x34; 1014 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); 1015 1016 *tmp = 0x52; 1017 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1018 1, 1, tmp); 1019 1020 dev->net->netdev_ops = &ax88179_netdev_ops; 1021 dev->net->ethtool_ops = &ax88179_ethtool_ops; 1022 dev->net->needed_headroom = 8; 1023 1024 /* Initialize MII structure */ 1025 dev->mii.dev = dev->net; 1026 dev->mii.mdio_read = ax88179_mdio_read; 1027 dev->mii.mdio_write = ax88179_mdio_write; 1028 dev->mii.phy_id_mask = 0xff; 1029 dev->mii.reg_num_mask = 0xff; 1030 dev->mii.phy_id = 0x03; 1031 dev->mii.supports_gmii = 1; 1032 1033 if (usb_device_no_sg_constraint(dev->udev)) 1034 dev->can_dma_sg = 1; 1035 1036 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1037 NETIF_F_RXCSUM; 1038 1039 dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1040 NETIF_F_RXCSUM; 1041 1042 if (dev->can_dma_sg) { 1043 dev->net->features |= NETIF_F_SG | NETIF_F_TSO; 1044 dev->net->hw_features |= NETIF_F_SG | NETIF_F_TSO; 1045 } 1046 1047 /* Enable checksum offload */ 1048 *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 1049 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 1050 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); 1051 1052 *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | 1053 AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 1054 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); 1055 1056 /* Configure RX control register => start operation */ 1057 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 1058 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 1059 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); 1060 1061 *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | 1062 AX_MONITOR_MODE_RWMP; 1063 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); 1064 1065 /* Configure default medium type => giga */ 1066 *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 1067 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX | 1068 AX_MEDIUM_GIGAMODE; 1069 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1070 2, 2, tmp16); 1071 1072 ax88179_led_setting(dev); 1073 1074 /* Restart autoneg */ 1075 mii_nway_restart(&dev->mii); 1076 1077 usbnet_link_change(dev, 0, 0); 1078 1079 return 0; 1080 } 1081 1082 static void ax88179_unbind(struct usbnet *dev, struct usb_interface *intf) 1083 { 1084 u16 tmp16; 1085 1086 /* Configure RX control register => stop operation */ 1087 tmp16 = AX_RX_CTL_STOP; 1088 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16); 1089 1090 tmp16 = 0; 1091 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp16); 1092 1093 /* Power down ethernet PHY */ 1094 tmp16 = 0; 1095 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16); 1096 } 1097 1098 static void 1099 ax88179_rx_checksum(struct sk_buff *skb, u32 *pkt_hdr) 1100 { 1101 skb->ip_summed = CHECKSUM_NONE; 1102 1103 /* checksum error bit is set */ 1104 if ((*pkt_hdr & AX_RXHDR_L3CSUM_ERR) || 1105 (*pkt_hdr & AX_RXHDR_L4CSUM_ERR)) 1106 return; 1107 1108 /* It must be a TCP or UDP packet with a valid checksum */ 1109 if (((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_TCP) || 1110 ((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_UDP)) 1111 skb->ip_summed = CHECKSUM_UNNECESSARY; 1112 } 1113 1114 static int ax88179_rx_fixup(struct usbnet *dev, struct sk_buff *skb) 1115 { 1116 struct sk_buff *ax_skb; 1117 int pkt_cnt; 1118 u32 rx_hdr; 1119 u16 hdr_off; 1120 u32 *pkt_hdr; 1121 1122 skb_trim(skb, skb->len - 4); 1123 memcpy(&rx_hdr, skb_tail_pointer(skb), 4); 1124 le32_to_cpus(&rx_hdr); 1125 1126 pkt_cnt = (u16)rx_hdr; 1127 hdr_off = (u16)(rx_hdr >> 16); 1128 pkt_hdr = (u32 *)(skb->data + hdr_off); 1129 1130 while (pkt_cnt--) { 1131 u16 pkt_len; 1132 1133 le32_to_cpus(pkt_hdr); 1134 pkt_len = (*pkt_hdr >> 16) & 0x1fff; 1135 1136 /* Check CRC or runt packet */ 1137 if ((*pkt_hdr & AX_RXHDR_CRC_ERR) || 1138 (*pkt_hdr & AX_RXHDR_DROP_ERR)) { 1139 skb_pull(skb, (pkt_len + 7) & 0xFFF8); 1140 pkt_hdr++; 1141 continue; 1142 } 1143 1144 if (pkt_cnt == 0) { 1145 /* Skip IP alignment psudo header */ 1146 skb_pull(skb, 2); 1147 skb->len = pkt_len; 1148 skb_set_tail_pointer(skb, pkt_len); 1149 skb->truesize = pkt_len + sizeof(struct sk_buff); 1150 ax88179_rx_checksum(skb, pkt_hdr); 1151 return 1; 1152 } 1153 1154 ax_skb = skb_clone(skb, GFP_ATOMIC); 1155 if (ax_skb) { 1156 ax_skb->len = pkt_len; 1157 ax_skb->data = skb->data + 2; 1158 skb_set_tail_pointer(ax_skb, pkt_len); 1159 ax_skb->truesize = pkt_len + sizeof(struct sk_buff); 1160 ax88179_rx_checksum(ax_skb, pkt_hdr); 1161 usbnet_skb_return(dev, ax_skb); 1162 } else { 1163 return 0; 1164 } 1165 1166 skb_pull(skb, (pkt_len + 7) & 0xFFF8); 1167 pkt_hdr++; 1168 } 1169 return 1; 1170 } 1171 1172 static struct sk_buff * 1173 ax88179_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags) 1174 { 1175 u32 tx_hdr1, tx_hdr2; 1176 int frame_size = dev->maxpacket; 1177 int mss = skb_shinfo(skb)->gso_size; 1178 int headroom; 1179 1180 tx_hdr1 = skb->len; 1181 tx_hdr2 = mss; 1182 if (((skb->len + 8) % frame_size) == 0) 1183 tx_hdr2 |= 0x80008000; /* Enable padding */ 1184 1185 headroom = skb_headroom(skb) - 8; 1186 1187 if ((skb_header_cloned(skb) || headroom < 0) && 1188 pskb_expand_head(skb, headroom < 0 ? 8 : 0, 0, GFP_ATOMIC)) { 1189 dev_kfree_skb_any(skb); 1190 return NULL; 1191 } 1192 1193 skb_push(skb, 4); 1194 cpu_to_le32s(&tx_hdr2); 1195 skb_copy_to_linear_data(skb, &tx_hdr2, 4); 1196 1197 skb_push(skb, 4); 1198 cpu_to_le32s(&tx_hdr1); 1199 skb_copy_to_linear_data(skb, &tx_hdr1, 4); 1200 1201 return skb; 1202 } 1203 1204 static int ax88179_link_reset(struct usbnet *dev) 1205 { 1206 struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data; 1207 u8 tmp[5], link_sts; 1208 u16 mode, tmp16, delay = HZ / 10; 1209 u32 tmp32 = 0x40000000; 1210 unsigned long jtimeout; 1211 1212 jtimeout = jiffies + delay; 1213 while (tmp32 & 0x40000000) { 1214 mode = 0; 1215 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &mode); 1216 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, 1217 &ax179_data->rxctl); 1218 1219 /*link up, check the usb device control TX FIFO full or empty*/ 1220 ax88179_read_cmd(dev, 0x81, 0x8c, 0, 4, &tmp32); 1221 1222 if (time_after(jiffies, jtimeout)) 1223 return 0; 1224 } 1225 1226 mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 1227 AX_MEDIUM_RXFLOW_CTRLEN; 1228 1229 ax88179_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS, 1230 1, 1, &link_sts); 1231 1232 ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1233 GMII_PHY_PHYSR, 2, &tmp16); 1234 1235 if (!(tmp16 & GMII_PHY_PHYSR_LINK)) { 1236 return 0; 1237 } else if (GMII_PHY_PHYSR_GIGA == (tmp16 & GMII_PHY_PHYSR_SMASK)) { 1238 mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ; 1239 if (dev->net->mtu > 1500) 1240 mode |= AX_MEDIUM_JUMBO_EN; 1241 1242 if (link_sts & AX_USB_SS) 1243 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 1244 else if (link_sts & AX_USB_HS) 1245 memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5); 1246 else 1247 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 1248 } else if (GMII_PHY_PHYSR_100 == (tmp16 & GMII_PHY_PHYSR_SMASK)) { 1249 mode |= AX_MEDIUM_PS; 1250 1251 if (link_sts & (AX_USB_SS | AX_USB_HS)) 1252 memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5); 1253 else 1254 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 1255 } else { 1256 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 1257 } 1258 1259 /* RX bulk configuration */ 1260 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 1261 1262 dev->rx_urb_size = (1024 * (tmp[3] + 2)); 1263 1264 if (tmp16 & GMII_PHY_PHYSR_FULL) 1265 mode |= AX_MEDIUM_FULL_DUPLEX; 1266 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1267 2, 2, &mode); 1268 1269 netif_carrier_on(dev->net); 1270 1271 return 0; 1272 } 1273 1274 static int ax88179_reset(struct usbnet *dev) 1275 { 1276 u8 buf[5]; 1277 u16 *tmp16; 1278 u8 *tmp; 1279 1280 tmp16 = (u16 *)buf; 1281 tmp = (u8 *)buf; 1282 1283 /* Power up ethernet PHY */ 1284 *tmp16 = 0; 1285 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 1286 1287 *tmp16 = AX_PHYPWR_RSTCTL_IPRL; 1288 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 1289 msleep(200); 1290 1291 *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 1292 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); 1293 msleep(100); 1294 1295 /* Ethernet PHY Auto Detach*/ 1296 ax88179_auto_detach(dev, 0); 1297 1298 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, ETH_ALEN, 1299 dev->net->dev_addr); 1300 memcpy(dev->net->perm_addr, dev->net->dev_addr, ETH_ALEN); 1301 1302 /* RX bulk configuration */ 1303 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 1304 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 1305 1306 dev->rx_urb_size = 1024 * 20; 1307 1308 *tmp = 0x34; 1309 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); 1310 1311 *tmp = 0x52; 1312 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1313 1, 1, tmp); 1314 1315 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1316 NETIF_F_RXCSUM; 1317 1318 dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1319 NETIF_F_RXCSUM; 1320 1321 /* Enable checksum offload */ 1322 *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 1323 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 1324 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); 1325 1326 *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | 1327 AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 1328 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); 1329 1330 /* Configure RX control register => start operation */ 1331 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 1332 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 1333 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); 1334 1335 *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | 1336 AX_MONITOR_MODE_RWMP; 1337 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); 1338 1339 /* Configure default medium type => giga */ 1340 *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 1341 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX | 1342 AX_MEDIUM_GIGAMODE; 1343 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1344 2, 2, tmp16); 1345 1346 ax88179_led_setting(dev); 1347 1348 /* Restart autoneg */ 1349 mii_nway_restart(&dev->mii); 1350 1351 usbnet_link_change(dev, 0, 0); 1352 1353 return 0; 1354 } 1355 1356 static int ax88179_stop(struct usbnet *dev) 1357 { 1358 u16 tmp16; 1359 1360 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1361 2, 2, &tmp16); 1362 tmp16 &= ~AX_MEDIUM_RECEIVE_EN; 1363 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1364 2, 2, &tmp16); 1365 1366 return 0; 1367 } 1368 1369 static const struct driver_info ax88179_info = { 1370 .description = "ASIX AX88179 USB 3.0 Gigabit Ethernet", 1371 .bind = ax88179_bind, 1372 .unbind = ax88179_unbind, 1373 .status = ax88179_status, 1374 .link_reset = ax88179_link_reset, 1375 .reset = ax88179_reset, 1376 .stop = ax88179_stop, 1377 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1378 .rx_fixup = ax88179_rx_fixup, 1379 .tx_fixup = ax88179_tx_fixup, 1380 }; 1381 1382 static const struct driver_info ax88178a_info = { 1383 .description = "ASIX AX88178A USB 2.0 Gigabit Ethernet", 1384 .bind = ax88179_bind, 1385 .unbind = ax88179_unbind, 1386 .status = ax88179_status, 1387 .link_reset = ax88179_link_reset, 1388 .reset = ax88179_reset, 1389 .stop = ax88179_stop, 1390 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1391 .rx_fixup = ax88179_rx_fixup, 1392 .tx_fixup = ax88179_tx_fixup, 1393 }; 1394 1395 static const struct driver_info sitecom_info = { 1396 .description = "Sitecom USB 3.0 to Gigabit Adapter", 1397 .bind = ax88179_bind, 1398 .unbind = ax88179_unbind, 1399 .status = ax88179_status, 1400 .link_reset = ax88179_link_reset, 1401 .reset = ax88179_reset, 1402 .stop = ax88179_stop, 1403 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1404 .rx_fixup = ax88179_rx_fixup, 1405 .tx_fixup = ax88179_tx_fixup, 1406 }; 1407 1408 static const struct driver_info samsung_info = { 1409 .description = "Samsung USB Ethernet Adapter", 1410 .bind = ax88179_bind, 1411 .unbind = ax88179_unbind, 1412 .status = ax88179_status, 1413 .link_reset = ax88179_link_reset, 1414 .reset = ax88179_reset, 1415 .stop = ax88179_stop, 1416 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1417 .rx_fixup = ax88179_rx_fixup, 1418 .tx_fixup = ax88179_tx_fixup, 1419 }; 1420 1421 static const struct usb_device_id products[] = { 1422 { 1423 /* ASIX AX88179 10/100/1000 */ 1424 USB_DEVICE(0x0b95, 0x1790), 1425 .driver_info = (unsigned long)&ax88179_info, 1426 }, { 1427 /* ASIX AX88178A 10/100/1000 */ 1428 USB_DEVICE(0x0b95, 0x178a), 1429 .driver_info = (unsigned long)&ax88178a_info, 1430 }, { 1431 /* Sitecom USB 3.0 to Gigabit Adapter */ 1432 USB_DEVICE(0x0df6, 0x0072), 1433 .driver_info = (unsigned long)&sitecom_info, 1434 }, { 1435 /* Samsung USB Ethernet Adapter */ 1436 USB_DEVICE(0x04e8, 0xa100), 1437 .driver_info = (unsigned long)&samsung_info, 1438 }, 1439 { }, 1440 }; 1441 MODULE_DEVICE_TABLE(usb, products); 1442 1443 static struct usb_driver ax88179_178a_driver = { 1444 .name = "ax88179_178a", 1445 .id_table = products, 1446 .probe = usbnet_probe, 1447 .suspend = ax88179_suspend, 1448 .resume = ax88179_resume, 1449 .reset_resume = ax88179_resume, 1450 .disconnect = usbnet_disconnect, 1451 .supports_autosuspend = 1, 1452 .disable_hub_initiated_lpm = 1, 1453 }; 1454 1455 module_usb_driver(ax88179_178a_driver); 1456 1457 MODULE_DESCRIPTION("ASIX AX88179/178A based USB 3.0/2.0 Gigabit Ethernet Devices"); 1458 MODULE_LICENSE("GPL"); 1459