1 /* 2 * ASIX AX88179/178A USB 3.0/2.0 to Gigabit Ethernet Devices 3 * 4 * Copyright (C) 2011-2013 ASIX 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/module.h> 21 #include <linux/etherdevice.h> 22 #include <linux/mii.h> 23 #include <linux/usb.h> 24 #include <linux/crc32.h> 25 #include <linux/usb/usbnet.h> 26 27 #define AX88179_PHY_ID 0x03 28 #define AX_EEPROM_LEN 0x100 29 #define AX88179_EEPROM_MAGIC 0x17900b95 30 #define AX_MCAST_FLTSIZE 8 31 #define AX_MAX_MCAST 64 32 #define AX_INT_PPLS_LINK ((u32)BIT(16)) 33 #define AX_RXHDR_L4_TYPE_MASK 0x1c 34 #define AX_RXHDR_L4_TYPE_UDP 4 35 #define AX_RXHDR_L4_TYPE_TCP 16 36 #define AX_RXHDR_L3CSUM_ERR 2 37 #define AX_RXHDR_L4CSUM_ERR 1 38 #define AX_RXHDR_CRC_ERR ((u32)BIT(29)) 39 #define AX_RXHDR_DROP_ERR ((u32)BIT(31)) 40 #define AX_ACCESS_MAC 0x01 41 #define AX_ACCESS_PHY 0x02 42 #define AX_ACCESS_EEPROM 0x04 43 #define AX_ACCESS_EFUS 0x05 44 #define AX_PAUSE_WATERLVL_HIGH 0x54 45 #define AX_PAUSE_WATERLVL_LOW 0x55 46 47 #define PHYSICAL_LINK_STATUS 0x02 48 #define AX_USB_SS 0x04 49 #define AX_USB_HS 0x02 50 51 #define GENERAL_STATUS 0x03 52 /* Check AX88179 version. UA1:Bit2 = 0, UA2:Bit2 = 1 */ 53 #define AX_SECLD 0x04 54 55 #define AX_SROM_ADDR 0x07 56 #define AX_SROM_CMD 0x0a 57 #define EEP_RD 0x04 58 #define EEP_BUSY 0x10 59 60 #define AX_SROM_DATA_LOW 0x08 61 #define AX_SROM_DATA_HIGH 0x09 62 63 #define AX_RX_CTL 0x0b 64 #define AX_RX_CTL_DROPCRCERR 0x0100 65 #define AX_RX_CTL_IPE 0x0200 66 #define AX_RX_CTL_START 0x0080 67 #define AX_RX_CTL_AP 0x0020 68 #define AX_RX_CTL_AM 0x0010 69 #define AX_RX_CTL_AB 0x0008 70 #define AX_RX_CTL_AMALL 0x0002 71 #define AX_RX_CTL_PRO 0x0001 72 #define AX_RX_CTL_STOP 0x0000 73 74 #define AX_NODE_ID 0x10 75 #define AX_MULFLTARY 0x16 76 77 #define AX_MEDIUM_STATUS_MODE 0x22 78 #define AX_MEDIUM_GIGAMODE 0x01 79 #define AX_MEDIUM_FULL_DUPLEX 0x02 80 #define AX_MEDIUM_EN_125MHZ 0x08 81 #define AX_MEDIUM_RXFLOW_CTRLEN 0x10 82 #define AX_MEDIUM_TXFLOW_CTRLEN 0x20 83 #define AX_MEDIUM_RECEIVE_EN 0x100 84 #define AX_MEDIUM_PS 0x200 85 #define AX_MEDIUM_JUMBO_EN 0x8040 86 87 #define AX_MONITOR_MOD 0x24 88 #define AX_MONITOR_MODE_RWLC 0x02 89 #define AX_MONITOR_MODE_RWMP 0x04 90 #define AX_MONITOR_MODE_PMEPOL 0x20 91 #define AX_MONITOR_MODE_PMETYPE 0x40 92 93 #define AX_GPIO_CTRL 0x25 94 #define AX_GPIO_CTRL_GPIO3EN 0x80 95 #define AX_GPIO_CTRL_GPIO2EN 0x40 96 #define AX_GPIO_CTRL_GPIO1EN 0x20 97 98 #define AX_PHYPWR_RSTCTL 0x26 99 #define AX_PHYPWR_RSTCTL_BZ 0x0010 100 #define AX_PHYPWR_RSTCTL_IPRL 0x0020 101 #define AX_PHYPWR_RSTCTL_AT 0x1000 102 103 #define AX_RX_BULKIN_QCTRL 0x2e 104 #define AX_CLK_SELECT 0x33 105 #define AX_CLK_SELECT_BCS 0x01 106 #define AX_CLK_SELECT_ACS 0x02 107 #define AX_CLK_SELECT_ULR 0x08 108 109 #define AX_RXCOE_CTL 0x34 110 #define AX_RXCOE_IP 0x01 111 #define AX_RXCOE_TCP 0x02 112 #define AX_RXCOE_UDP 0x04 113 #define AX_RXCOE_TCPV6 0x20 114 #define AX_RXCOE_UDPV6 0x40 115 116 #define AX_TXCOE_CTL 0x35 117 #define AX_TXCOE_IP 0x01 118 #define AX_TXCOE_TCP 0x02 119 #define AX_TXCOE_UDP 0x04 120 #define AX_TXCOE_TCPV6 0x20 121 #define AX_TXCOE_UDPV6 0x40 122 123 #define AX_LEDCTRL 0x73 124 125 #define GMII_PHY_PHYSR 0x11 126 #define GMII_PHY_PHYSR_SMASK 0xc000 127 #define GMII_PHY_PHYSR_GIGA 0x8000 128 #define GMII_PHY_PHYSR_100 0x4000 129 #define GMII_PHY_PHYSR_FULL 0x2000 130 #define GMII_PHY_PHYSR_LINK 0x400 131 132 #define GMII_LED_ACT 0x1a 133 #define GMII_LED_ACTIVE_MASK 0xff8f 134 #define GMII_LED0_ACTIVE BIT(4) 135 #define GMII_LED1_ACTIVE BIT(5) 136 #define GMII_LED2_ACTIVE BIT(6) 137 138 #define GMII_LED_LINK 0x1c 139 #define GMII_LED_LINK_MASK 0xf888 140 #define GMII_LED0_LINK_10 BIT(0) 141 #define GMII_LED0_LINK_100 BIT(1) 142 #define GMII_LED0_LINK_1000 BIT(2) 143 #define GMII_LED1_LINK_10 BIT(4) 144 #define GMII_LED1_LINK_100 BIT(5) 145 #define GMII_LED1_LINK_1000 BIT(6) 146 #define GMII_LED2_LINK_10 BIT(8) 147 #define GMII_LED2_LINK_100 BIT(9) 148 #define GMII_LED2_LINK_1000 BIT(10) 149 #define LED0_ACTIVE BIT(0) 150 #define LED0_LINK_10 BIT(1) 151 #define LED0_LINK_100 BIT(2) 152 #define LED0_LINK_1000 BIT(3) 153 #define LED0_FD BIT(4) 154 #define LED0_USB3_MASK 0x001f 155 #define LED1_ACTIVE BIT(5) 156 #define LED1_LINK_10 BIT(6) 157 #define LED1_LINK_100 BIT(7) 158 #define LED1_LINK_1000 BIT(8) 159 #define LED1_FD BIT(9) 160 #define LED1_USB3_MASK 0x03e0 161 #define LED2_ACTIVE BIT(10) 162 #define LED2_LINK_1000 BIT(13) 163 #define LED2_LINK_100 BIT(12) 164 #define LED2_LINK_10 BIT(11) 165 #define LED2_FD BIT(14) 166 #define LED_VALID BIT(15) 167 #define LED2_USB3_MASK 0x7c00 168 169 #define GMII_PHYPAGE 0x1e 170 #define GMII_PHY_PAGE_SELECT 0x1f 171 #define GMII_PHY_PGSEL_EXT 0x0007 172 #define GMII_PHY_PGSEL_PAGE0 0x0000 173 174 struct ax88179_data { 175 u16 rxctl; 176 u16 reserved; 177 }; 178 179 struct ax88179_int_data { 180 __le32 intdata1; 181 __le32 intdata2; 182 }; 183 184 static const struct { 185 unsigned char ctrl, timer_l, timer_h, size, ifg; 186 } AX88179_BULKIN_SIZE[] = { 187 {7, 0x4f, 0, 0x12, 0xff}, 188 {7, 0x20, 3, 0x16, 0xff}, 189 {7, 0xae, 7, 0x18, 0xff}, 190 {7, 0xcc, 0x4c, 0x18, 8}, 191 }; 192 193 static int __ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 194 u16 size, void *data, int in_pm) 195 { 196 int ret; 197 int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16); 198 199 BUG_ON(!dev); 200 201 if (!in_pm) 202 fn = usbnet_read_cmd; 203 else 204 fn = usbnet_read_cmd_nopm; 205 206 ret = fn(dev, cmd, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 207 value, index, data, size); 208 209 if (unlikely(ret < 0)) 210 netdev_warn(dev->net, "Failed to read reg index 0x%04x: %d\n", 211 index, ret); 212 213 return ret; 214 } 215 216 static int __ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 217 u16 size, void *data, int in_pm) 218 { 219 int ret; 220 int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16); 221 222 BUG_ON(!dev); 223 224 if (!in_pm) 225 fn = usbnet_write_cmd; 226 else 227 fn = usbnet_write_cmd_nopm; 228 229 ret = fn(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 230 value, index, data, size); 231 232 if (unlikely(ret < 0)) 233 netdev_warn(dev->net, "Failed to write reg index 0x%04x: %d\n", 234 index, ret); 235 236 return ret; 237 } 238 239 static void ax88179_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, 240 u16 index, u16 size, void *data) 241 { 242 u16 buf; 243 244 if (2 == size) { 245 buf = *((u16 *)data); 246 cpu_to_le16s(&buf); 247 usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | 248 USB_RECIP_DEVICE, value, index, &buf, 249 size); 250 } else { 251 usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | 252 USB_RECIP_DEVICE, value, index, data, 253 size); 254 } 255 } 256 257 static int ax88179_read_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value, 258 u16 index, u16 size, void *data) 259 { 260 int ret; 261 262 if (2 == size) { 263 u16 buf; 264 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1); 265 le16_to_cpus(&buf); 266 *((u16 *)data) = buf; 267 } else if (4 == size) { 268 u32 buf; 269 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1); 270 le32_to_cpus(&buf); 271 *((u32 *)data) = buf; 272 } else { 273 ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 1); 274 } 275 276 return ret; 277 } 278 279 static int ax88179_write_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value, 280 u16 index, u16 size, void *data) 281 { 282 int ret; 283 284 if (2 == size) { 285 u16 buf; 286 buf = *((u16 *)data); 287 cpu_to_le16s(&buf); 288 ret = __ax88179_write_cmd(dev, cmd, value, index, 289 size, &buf, 1); 290 } else { 291 ret = __ax88179_write_cmd(dev, cmd, value, index, 292 size, data, 1); 293 } 294 295 return ret; 296 } 297 298 static int ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 299 u16 size, void *data) 300 { 301 int ret; 302 303 if (2 == size) { 304 u16 buf; 305 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0); 306 le16_to_cpus(&buf); 307 *((u16 *)data) = buf; 308 } else if (4 == size) { 309 u32 buf; 310 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0); 311 le32_to_cpus(&buf); 312 *((u32 *)data) = buf; 313 } else { 314 ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 0); 315 } 316 317 return ret; 318 } 319 320 static int ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 321 u16 size, void *data) 322 { 323 int ret; 324 325 if (2 == size) { 326 u16 buf; 327 buf = *((u16 *)data); 328 cpu_to_le16s(&buf); 329 ret = __ax88179_write_cmd(dev, cmd, value, index, 330 size, &buf, 0); 331 } else { 332 ret = __ax88179_write_cmd(dev, cmd, value, index, 333 size, data, 0); 334 } 335 336 return ret; 337 } 338 339 static void ax88179_status(struct usbnet *dev, struct urb *urb) 340 { 341 struct ax88179_int_data *event; 342 u32 link; 343 344 if (urb->actual_length < 8) 345 return; 346 347 event = urb->transfer_buffer; 348 le32_to_cpus((void *)&event->intdata1); 349 350 link = (((__force u32)event->intdata1) & AX_INT_PPLS_LINK) >> 16; 351 352 if (netif_carrier_ok(dev->net) != link) { 353 usbnet_link_change(dev, link, 1); 354 netdev_info(dev->net, "ax88179 - Link status is: %d\n", link); 355 } 356 } 357 358 static int ax88179_mdio_read(struct net_device *netdev, int phy_id, int loc) 359 { 360 struct usbnet *dev = netdev_priv(netdev); 361 u16 res; 362 363 ax88179_read_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res); 364 return res; 365 } 366 367 static void ax88179_mdio_write(struct net_device *netdev, int phy_id, int loc, 368 int val) 369 { 370 struct usbnet *dev = netdev_priv(netdev); 371 u16 res = (u16) val; 372 373 ax88179_write_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res); 374 } 375 376 static int ax88179_suspend(struct usb_interface *intf, pm_message_t message) 377 { 378 struct usbnet *dev = usb_get_intfdata(intf); 379 u16 tmp16; 380 u8 tmp8; 381 382 usbnet_suspend(intf, message); 383 384 /* Disable RX path */ 385 ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 386 2, 2, &tmp16); 387 tmp16 &= ~AX_MEDIUM_RECEIVE_EN; 388 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 389 2, 2, &tmp16); 390 391 /* Force bulk-in zero length */ 392 ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 393 2, 2, &tmp16); 394 395 tmp16 |= AX_PHYPWR_RSTCTL_BZ | AX_PHYPWR_RSTCTL_IPRL; 396 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 397 2, 2, &tmp16); 398 399 /* change clock */ 400 tmp8 = 0; 401 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 402 403 /* Configure RX control register => stop operation */ 404 tmp16 = AX_RX_CTL_STOP; 405 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16); 406 407 return 0; 408 } 409 410 /* This function is used to enable the autodetach function. */ 411 /* This function is determined by offset 0x43 of EEPROM */ 412 static int ax88179_auto_detach(struct usbnet *dev, int in_pm) 413 { 414 u16 tmp16; 415 u8 tmp8; 416 int (*fnr)(struct usbnet *, u8, u16, u16, u16, void *); 417 int (*fnw)(struct usbnet *, u8, u16, u16, u16, void *); 418 419 if (!in_pm) { 420 fnr = ax88179_read_cmd; 421 fnw = ax88179_write_cmd; 422 } else { 423 fnr = ax88179_read_cmd_nopm; 424 fnw = ax88179_write_cmd_nopm; 425 } 426 427 if (fnr(dev, AX_ACCESS_EEPROM, 0x43, 1, 2, &tmp16) < 0) 428 return 0; 429 430 if ((tmp16 == 0xFFFF) || (!(tmp16 & 0x0100))) 431 return 0; 432 433 /* Enable Auto Detach bit */ 434 tmp8 = 0; 435 fnr(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 436 tmp8 |= AX_CLK_SELECT_ULR; 437 fnw(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 438 439 fnr(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16); 440 tmp16 |= AX_PHYPWR_RSTCTL_AT; 441 fnw(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16); 442 443 return 0; 444 } 445 446 static int ax88179_resume(struct usb_interface *intf) 447 { 448 struct usbnet *dev = usb_get_intfdata(intf); 449 u16 tmp16; 450 u8 tmp8; 451 452 usbnet_link_change(dev, 0, 0); 453 454 /* Power up ethernet PHY */ 455 tmp16 = 0; 456 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 457 2, 2, &tmp16); 458 udelay(1000); 459 460 tmp16 = AX_PHYPWR_RSTCTL_IPRL; 461 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 462 2, 2, &tmp16); 463 msleep(200); 464 465 /* Ethernet PHY Auto Detach*/ 466 ax88179_auto_detach(dev, 1); 467 468 /* Enable clock */ 469 ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 470 tmp8 |= AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 471 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 472 msleep(100); 473 474 /* Configure RX control register => start operation */ 475 tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 476 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 477 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16); 478 479 return usbnet_resume(intf); 480 } 481 482 static void 483 ax88179_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) 484 { 485 struct usbnet *dev = netdev_priv(net); 486 u8 opt; 487 488 if (ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 489 1, 1, &opt) < 0) { 490 wolinfo->supported = 0; 491 wolinfo->wolopts = 0; 492 return; 493 } 494 495 wolinfo->supported = WAKE_PHY | WAKE_MAGIC; 496 wolinfo->wolopts = 0; 497 if (opt & AX_MONITOR_MODE_RWLC) 498 wolinfo->wolopts |= WAKE_PHY; 499 if (opt & AX_MONITOR_MODE_RWMP) 500 wolinfo->wolopts |= WAKE_MAGIC; 501 } 502 503 static int 504 ax88179_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) 505 { 506 struct usbnet *dev = netdev_priv(net); 507 u8 opt = 0; 508 509 if (wolinfo->wolopts & WAKE_PHY) 510 opt |= AX_MONITOR_MODE_RWLC; 511 if (wolinfo->wolopts & WAKE_MAGIC) 512 opt |= AX_MONITOR_MODE_RWMP; 513 514 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 515 1, 1, &opt) < 0) 516 return -EINVAL; 517 518 return 0; 519 } 520 521 static int ax88179_get_eeprom_len(struct net_device *net) 522 { 523 return AX_EEPROM_LEN; 524 } 525 526 static int 527 ax88179_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom, 528 u8 *data) 529 { 530 struct usbnet *dev = netdev_priv(net); 531 u16 *eeprom_buff; 532 int first_word, last_word; 533 int i, ret; 534 535 if (eeprom->len == 0) 536 return -EINVAL; 537 538 eeprom->magic = AX88179_EEPROM_MAGIC; 539 540 first_word = eeprom->offset >> 1; 541 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 542 eeprom_buff = kmalloc(sizeof(u16) * (last_word - first_word + 1), 543 GFP_KERNEL); 544 if (!eeprom_buff) 545 return -ENOMEM; 546 547 /* ax88179/178A returns 2 bytes from eeprom on read */ 548 for (i = first_word; i <= last_word; i++) { 549 ret = __ax88179_read_cmd(dev, AX_ACCESS_EEPROM, i, 1, 2, 550 &eeprom_buff[i - first_word], 551 0); 552 if (ret < 0) { 553 kfree(eeprom_buff); 554 return -EIO; 555 } 556 } 557 558 memcpy(data, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); 559 kfree(eeprom_buff); 560 return 0; 561 } 562 563 static int ax88179_get_settings(struct net_device *net, struct ethtool_cmd *cmd) 564 { 565 struct usbnet *dev = netdev_priv(net); 566 return mii_ethtool_gset(&dev->mii, cmd); 567 } 568 569 static int ax88179_set_settings(struct net_device *net, struct ethtool_cmd *cmd) 570 { 571 struct usbnet *dev = netdev_priv(net); 572 return mii_ethtool_sset(&dev->mii, cmd); 573 } 574 575 576 static int ax88179_ioctl(struct net_device *net, struct ifreq *rq, int cmd) 577 { 578 struct usbnet *dev = netdev_priv(net); 579 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); 580 } 581 582 static const struct ethtool_ops ax88179_ethtool_ops = { 583 .get_link = ethtool_op_get_link, 584 .get_msglevel = usbnet_get_msglevel, 585 .set_msglevel = usbnet_set_msglevel, 586 .get_wol = ax88179_get_wol, 587 .set_wol = ax88179_set_wol, 588 .get_eeprom_len = ax88179_get_eeprom_len, 589 .get_eeprom = ax88179_get_eeprom, 590 .get_settings = ax88179_get_settings, 591 .set_settings = ax88179_set_settings, 592 .nway_reset = usbnet_nway_reset, 593 }; 594 595 static void ax88179_set_multicast(struct net_device *net) 596 { 597 struct usbnet *dev = netdev_priv(net); 598 struct ax88179_data *data = (struct ax88179_data *)dev->data; 599 u8 *m_filter = ((u8 *)dev->data) + 12; 600 601 data->rxctl = (AX_RX_CTL_START | AX_RX_CTL_AB | AX_RX_CTL_IPE); 602 603 if (net->flags & IFF_PROMISC) { 604 data->rxctl |= AX_RX_CTL_PRO; 605 } else if (net->flags & IFF_ALLMULTI || 606 netdev_mc_count(net) > AX_MAX_MCAST) { 607 data->rxctl |= AX_RX_CTL_AMALL; 608 } else if (netdev_mc_empty(net)) { 609 /* just broadcast and directed */ 610 } else { 611 /* We use the 20 byte dev->data for our 8 byte filter buffer 612 * to avoid allocating memory that is tricky to free later 613 */ 614 u32 crc_bits; 615 struct netdev_hw_addr *ha; 616 617 memset(m_filter, 0, AX_MCAST_FLTSIZE); 618 619 netdev_for_each_mc_addr(ha, net) { 620 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; 621 *(m_filter + (crc_bits >> 3)) |= (1 << (crc_bits & 7)); 622 } 623 624 ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_MULFLTARY, 625 AX_MCAST_FLTSIZE, AX_MCAST_FLTSIZE, 626 m_filter); 627 628 data->rxctl |= AX_RX_CTL_AM; 629 } 630 631 ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_RX_CTL, 632 2, 2, &data->rxctl); 633 } 634 635 static int 636 ax88179_set_features(struct net_device *net, netdev_features_t features) 637 { 638 u8 tmp; 639 struct usbnet *dev = netdev_priv(net); 640 netdev_features_t changed = net->features ^ features; 641 642 if (changed & NETIF_F_IP_CSUM) { 643 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 644 tmp ^= AX_TXCOE_TCP | AX_TXCOE_UDP; 645 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 646 } 647 648 if (changed & NETIF_F_IPV6_CSUM) { 649 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 650 tmp ^= AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 651 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 652 } 653 654 if (changed & NETIF_F_RXCSUM) { 655 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp); 656 tmp ^= AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 657 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 658 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp); 659 } 660 661 return 0; 662 } 663 664 static int ax88179_change_mtu(struct net_device *net, int new_mtu) 665 { 666 struct usbnet *dev = netdev_priv(net); 667 u16 tmp16; 668 669 if (new_mtu <= 0 || new_mtu > 4088) 670 return -EINVAL; 671 672 net->mtu = new_mtu; 673 dev->hard_mtu = net->mtu + net->hard_header_len; 674 675 if (net->mtu > 1500) { 676 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 677 2, 2, &tmp16); 678 tmp16 |= AX_MEDIUM_JUMBO_EN; 679 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 680 2, 2, &tmp16); 681 } else { 682 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 683 2, 2, &tmp16); 684 tmp16 &= ~AX_MEDIUM_JUMBO_EN; 685 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 686 2, 2, &tmp16); 687 } 688 689 /* max qlen depend on hard_mtu and rx_urb_size */ 690 usbnet_update_max_qlen(dev); 691 692 return 0; 693 } 694 695 static int ax88179_set_mac_addr(struct net_device *net, void *p) 696 { 697 struct usbnet *dev = netdev_priv(net); 698 struct sockaddr *addr = p; 699 700 if (netif_running(net)) 701 return -EBUSY; 702 if (!is_valid_ether_addr(addr->sa_data)) 703 return -EADDRNOTAVAIL; 704 705 memcpy(net->dev_addr, addr->sa_data, ETH_ALEN); 706 707 /* Set the MAC address */ 708 return ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, 709 ETH_ALEN, net->dev_addr); 710 } 711 712 static const struct net_device_ops ax88179_netdev_ops = { 713 .ndo_open = usbnet_open, 714 .ndo_stop = usbnet_stop, 715 .ndo_start_xmit = usbnet_start_xmit, 716 .ndo_tx_timeout = usbnet_tx_timeout, 717 .ndo_change_mtu = ax88179_change_mtu, 718 .ndo_set_mac_address = ax88179_set_mac_addr, 719 .ndo_validate_addr = eth_validate_addr, 720 .ndo_do_ioctl = ax88179_ioctl, 721 .ndo_set_rx_mode = ax88179_set_multicast, 722 .ndo_set_features = ax88179_set_features, 723 }; 724 725 static int ax88179_check_eeprom(struct usbnet *dev) 726 { 727 u8 i, buf, eeprom[20]; 728 u16 csum, delay = HZ / 10; 729 unsigned long jtimeout; 730 731 /* Read EEPROM content */ 732 for (i = 0; i < 6; i++) { 733 buf = i; 734 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR, 735 1, 1, &buf) < 0) 736 return -EINVAL; 737 738 buf = EEP_RD; 739 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 740 1, 1, &buf) < 0) 741 return -EINVAL; 742 743 jtimeout = jiffies + delay; 744 do { 745 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 746 1, 1, &buf); 747 748 if (time_after(jiffies, jtimeout)) 749 return -EINVAL; 750 751 } while (buf & EEP_BUSY); 752 753 __ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW, 754 2, 2, &eeprom[i * 2], 0); 755 756 if ((i == 0) && (eeprom[0] == 0xFF)) 757 return -EINVAL; 758 } 759 760 csum = eeprom[6] + eeprom[7] + eeprom[8] + eeprom[9]; 761 csum = (csum >> 8) + (csum & 0xff); 762 if ((csum + eeprom[10]) != 0xff) 763 return -EINVAL; 764 765 return 0; 766 } 767 768 static int ax88179_check_efuse(struct usbnet *dev, u16 *ledmode) 769 { 770 u8 i; 771 u8 efuse[64]; 772 u16 csum = 0; 773 774 if (ax88179_read_cmd(dev, AX_ACCESS_EFUS, 0, 64, 64, efuse) < 0) 775 return -EINVAL; 776 777 if (*efuse == 0xFF) 778 return -EINVAL; 779 780 for (i = 0; i < 64; i++) 781 csum = csum + efuse[i]; 782 783 while (csum > 255) 784 csum = (csum & 0x00FF) + ((csum >> 8) & 0x00FF); 785 786 if (csum != 0xFF) 787 return -EINVAL; 788 789 *ledmode = (efuse[51] << 8) | efuse[52]; 790 791 return 0; 792 } 793 794 static int ax88179_convert_old_led(struct usbnet *dev, u16 *ledvalue) 795 { 796 u16 led; 797 798 /* Loaded the old eFuse LED Mode */ 799 if (ax88179_read_cmd(dev, AX_ACCESS_EEPROM, 0x3C, 1, 2, &led) < 0) 800 return -EINVAL; 801 802 led >>= 8; 803 switch (led) { 804 case 0xFF: 805 led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 | 806 LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 | 807 LED2_LINK_100 | LED2_LINK_1000 | LED_VALID; 808 break; 809 case 0xFE: 810 led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 | LED_VALID; 811 break; 812 case 0xFD: 813 led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 | 814 LED2_LINK_10 | LED_VALID; 815 break; 816 case 0xFC: 817 led = LED0_ACTIVE | LED1_ACTIVE | LED1_LINK_1000 | LED2_ACTIVE | 818 LED2_LINK_100 | LED2_LINK_10 | LED_VALID; 819 break; 820 default: 821 led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 | 822 LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 | 823 LED2_LINK_100 | LED2_LINK_1000 | LED_VALID; 824 break; 825 } 826 827 *ledvalue = led; 828 829 return 0; 830 } 831 832 static int ax88179_led_setting(struct usbnet *dev) 833 { 834 u8 ledfd, value = 0; 835 u16 tmp, ledact, ledlink, ledvalue = 0, delay = HZ / 10; 836 unsigned long jtimeout; 837 838 /* Check AX88179 version. UA1 or UA2*/ 839 ax88179_read_cmd(dev, AX_ACCESS_MAC, GENERAL_STATUS, 1, 1, &value); 840 841 if (!(value & AX_SECLD)) { /* UA1 */ 842 value = AX_GPIO_CTRL_GPIO3EN | AX_GPIO_CTRL_GPIO2EN | 843 AX_GPIO_CTRL_GPIO1EN; 844 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_GPIO_CTRL, 845 1, 1, &value) < 0) 846 return -EINVAL; 847 } 848 849 /* Check EEPROM */ 850 if (!ax88179_check_eeprom(dev)) { 851 value = 0x42; 852 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR, 853 1, 1, &value) < 0) 854 return -EINVAL; 855 856 value = EEP_RD; 857 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 858 1, 1, &value) < 0) 859 return -EINVAL; 860 861 jtimeout = jiffies + delay; 862 do { 863 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 864 1, 1, &value); 865 866 if (time_after(jiffies, jtimeout)) 867 return -EINVAL; 868 869 } while (value & EEP_BUSY); 870 871 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_HIGH, 872 1, 1, &value); 873 ledvalue = (value << 8); 874 875 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW, 876 1, 1, &value); 877 ledvalue |= value; 878 879 /* load internal ROM for defaule setting */ 880 if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0)) 881 ax88179_convert_old_led(dev, &ledvalue); 882 883 } else if (!ax88179_check_efuse(dev, &ledvalue)) { 884 if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0)) 885 ax88179_convert_old_led(dev, &ledvalue); 886 } else { 887 ax88179_convert_old_led(dev, &ledvalue); 888 } 889 890 tmp = GMII_PHY_PGSEL_EXT; 891 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 892 GMII_PHY_PAGE_SELECT, 2, &tmp); 893 894 tmp = 0x2c; 895 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 896 GMII_PHYPAGE, 2, &tmp); 897 898 ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 899 GMII_LED_ACT, 2, &ledact); 900 901 ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 902 GMII_LED_LINK, 2, &ledlink); 903 904 ledact &= GMII_LED_ACTIVE_MASK; 905 ledlink &= GMII_LED_LINK_MASK; 906 907 if (ledvalue & LED0_ACTIVE) 908 ledact |= GMII_LED0_ACTIVE; 909 910 if (ledvalue & LED1_ACTIVE) 911 ledact |= GMII_LED1_ACTIVE; 912 913 if (ledvalue & LED2_ACTIVE) 914 ledact |= GMII_LED2_ACTIVE; 915 916 if (ledvalue & LED0_LINK_10) 917 ledlink |= GMII_LED0_LINK_10; 918 919 if (ledvalue & LED1_LINK_10) 920 ledlink |= GMII_LED1_LINK_10; 921 922 if (ledvalue & LED2_LINK_10) 923 ledlink |= GMII_LED2_LINK_10; 924 925 if (ledvalue & LED0_LINK_100) 926 ledlink |= GMII_LED0_LINK_100; 927 928 if (ledvalue & LED1_LINK_100) 929 ledlink |= GMII_LED1_LINK_100; 930 931 if (ledvalue & LED2_LINK_100) 932 ledlink |= GMII_LED2_LINK_100; 933 934 if (ledvalue & LED0_LINK_1000) 935 ledlink |= GMII_LED0_LINK_1000; 936 937 if (ledvalue & LED1_LINK_1000) 938 ledlink |= GMII_LED1_LINK_1000; 939 940 if (ledvalue & LED2_LINK_1000) 941 ledlink |= GMII_LED2_LINK_1000; 942 943 tmp = ledact; 944 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 945 GMII_LED_ACT, 2, &tmp); 946 947 tmp = ledlink; 948 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 949 GMII_LED_LINK, 2, &tmp); 950 951 tmp = GMII_PHY_PGSEL_PAGE0; 952 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 953 GMII_PHY_PAGE_SELECT, 2, &tmp); 954 955 /* LED full duplex setting */ 956 ledfd = 0; 957 if (ledvalue & LED0_FD) 958 ledfd |= 0x01; 959 else if ((ledvalue & LED0_USB3_MASK) == 0) 960 ledfd |= 0x02; 961 962 if (ledvalue & LED1_FD) 963 ledfd |= 0x04; 964 else if ((ledvalue & LED1_USB3_MASK) == 0) 965 ledfd |= 0x08; 966 967 if (ledvalue & LED2_FD) 968 ledfd |= 0x10; 969 else if ((ledvalue & LED2_USB3_MASK) == 0) 970 ledfd |= 0x20; 971 972 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_LEDCTRL, 1, 1, &ledfd); 973 974 return 0; 975 } 976 977 static int ax88179_bind(struct usbnet *dev, struct usb_interface *intf) 978 { 979 u8 buf[5]; 980 u16 *tmp16; 981 u8 *tmp; 982 struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data; 983 984 usbnet_get_endpoints(dev, intf); 985 986 tmp16 = (u16 *)buf; 987 tmp = (u8 *)buf; 988 989 memset(ax179_data, 0, sizeof(*ax179_data)); 990 991 /* Power up ethernet PHY */ 992 *tmp16 = 0; 993 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 994 *tmp16 = AX_PHYPWR_RSTCTL_IPRL; 995 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 996 msleep(200); 997 998 *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 999 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); 1000 msleep(100); 1001 1002 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, 1003 ETH_ALEN, dev->net->dev_addr); 1004 memcpy(dev->net->perm_addr, dev->net->dev_addr, ETH_ALEN); 1005 1006 /* RX bulk configuration */ 1007 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 1008 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 1009 1010 dev->rx_urb_size = 1024 * 20; 1011 1012 *tmp = 0x34; 1013 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); 1014 1015 *tmp = 0x52; 1016 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1017 1, 1, tmp); 1018 1019 dev->net->netdev_ops = &ax88179_netdev_ops; 1020 dev->net->ethtool_ops = &ax88179_ethtool_ops; 1021 dev->net->needed_headroom = 8; 1022 1023 /* Initialize MII structure */ 1024 dev->mii.dev = dev->net; 1025 dev->mii.mdio_read = ax88179_mdio_read; 1026 dev->mii.mdio_write = ax88179_mdio_write; 1027 dev->mii.phy_id_mask = 0xff; 1028 dev->mii.reg_num_mask = 0xff; 1029 dev->mii.phy_id = 0x03; 1030 dev->mii.supports_gmii = 1; 1031 1032 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1033 NETIF_F_RXCSUM; 1034 1035 dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1036 NETIF_F_RXCSUM; 1037 1038 /* Enable checksum offload */ 1039 *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 1040 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 1041 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); 1042 1043 *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | 1044 AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 1045 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); 1046 1047 /* Configure RX control register => start operation */ 1048 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 1049 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 1050 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); 1051 1052 *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | 1053 AX_MONITOR_MODE_RWMP; 1054 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); 1055 1056 /* Configure default medium type => giga */ 1057 *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 1058 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX | 1059 AX_MEDIUM_GIGAMODE; 1060 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1061 2, 2, tmp16); 1062 1063 ax88179_led_setting(dev); 1064 1065 /* Restart autoneg */ 1066 mii_nway_restart(&dev->mii); 1067 1068 usbnet_link_change(dev, 0, 0); 1069 1070 return 0; 1071 } 1072 1073 static void ax88179_unbind(struct usbnet *dev, struct usb_interface *intf) 1074 { 1075 u16 tmp16; 1076 1077 /* Configure RX control register => stop operation */ 1078 tmp16 = AX_RX_CTL_STOP; 1079 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16); 1080 1081 tmp16 = 0; 1082 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp16); 1083 1084 /* Power down ethernet PHY */ 1085 tmp16 = 0; 1086 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16); 1087 } 1088 1089 static void 1090 ax88179_rx_checksum(struct sk_buff *skb, u32 *pkt_hdr) 1091 { 1092 skb->ip_summed = CHECKSUM_NONE; 1093 1094 /* checksum error bit is set */ 1095 if ((*pkt_hdr & AX_RXHDR_L3CSUM_ERR) || 1096 (*pkt_hdr & AX_RXHDR_L4CSUM_ERR)) 1097 return; 1098 1099 /* It must be a TCP or UDP packet with a valid checksum */ 1100 if (((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_TCP) || 1101 ((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_UDP)) 1102 skb->ip_summed = CHECKSUM_UNNECESSARY; 1103 } 1104 1105 static int ax88179_rx_fixup(struct usbnet *dev, struct sk_buff *skb) 1106 { 1107 struct sk_buff *ax_skb; 1108 int pkt_cnt; 1109 u32 rx_hdr; 1110 u16 hdr_off; 1111 u32 *pkt_hdr; 1112 1113 /* This check is no longer done by usbnet */ 1114 if (skb->len < dev->net->hard_header_len) 1115 return 0; 1116 1117 skb_trim(skb, skb->len - 4); 1118 memcpy(&rx_hdr, skb_tail_pointer(skb), 4); 1119 le32_to_cpus(&rx_hdr); 1120 1121 pkt_cnt = (u16)rx_hdr; 1122 hdr_off = (u16)(rx_hdr >> 16); 1123 pkt_hdr = (u32 *)(skb->data + hdr_off); 1124 1125 while (pkt_cnt--) { 1126 u16 pkt_len; 1127 1128 le32_to_cpus(pkt_hdr); 1129 pkt_len = (*pkt_hdr >> 16) & 0x1fff; 1130 1131 /* Check CRC or runt packet */ 1132 if ((*pkt_hdr & AX_RXHDR_CRC_ERR) || 1133 (*pkt_hdr & AX_RXHDR_DROP_ERR)) { 1134 skb_pull(skb, (pkt_len + 7) & 0xFFF8); 1135 pkt_hdr++; 1136 continue; 1137 } 1138 1139 if (pkt_cnt == 0) { 1140 /* Skip IP alignment psudo header */ 1141 skb_pull(skb, 2); 1142 skb->len = pkt_len; 1143 skb_set_tail_pointer(skb, pkt_len); 1144 skb->truesize = pkt_len + sizeof(struct sk_buff); 1145 ax88179_rx_checksum(skb, pkt_hdr); 1146 return 1; 1147 } 1148 1149 ax_skb = skb_clone(skb, GFP_ATOMIC); 1150 if (ax_skb) { 1151 ax_skb->len = pkt_len; 1152 ax_skb->data = skb->data + 2; 1153 skb_set_tail_pointer(ax_skb, pkt_len); 1154 ax_skb->truesize = pkt_len + sizeof(struct sk_buff); 1155 ax88179_rx_checksum(ax_skb, pkt_hdr); 1156 usbnet_skb_return(dev, ax_skb); 1157 } else { 1158 return 0; 1159 } 1160 1161 skb_pull(skb, (pkt_len + 7) & 0xFFF8); 1162 pkt_hdr++; 1163 } 1164 return 1; 1165 } 1166 1167 static struct sk_buff * 1168 ax88179_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags) 1169 { 1170 u32 tx_hdr1, tx_hdr2; 1171 int frame_size = dev->maxpacket; 1172 int mss = skb_shinfo(skb)->gso_size; 1173 int headroom; 1174 1175 tx_hdr1 = skb->len; 1176 tx_hdr2 = mss; 1177 if (((skb->len + 8) % frame_size) == 0) 1178 tx_hdr2 |= 0x80008000; /* Enable padding */ 1179 1180 headroom = skb_headroom(skb) - 8; 1181 1182 if ((skb_header_cloned(skb) || headroom < 0) && 1183 pskb_expand_head(skb, headroom < 0 ? 8 : 0, 0, GFP_ATOMIC)) { 1184 dev_kfree_skb_any(skb); 1185 return NULL; 1186 } 1187 1188 skb_push(skb, 4); 1189 cpu_to_le32s(&tx_hdr2); 1190 skb_copy_to_linear_data(skb, &tx_hdr2, 4); 1191 1192 skb_push(skb, 4); 1193 cpu_to_le32s(&tx_hdr1); 1194 skb_copy_to_linear_data(skb, &tx_hdr1, 4); 1195 1196 return skb; 1197 } 1198 1199 static int ax88179_link_reset(struct usbnet *dev) 1200 { 1201 struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data; 1202 u8 tmp[5], link_sts; 1203 u16 mode, tmp16, delay = HZ / 10; 1204 u32 tmp32 = 0x40000000; 1205 unsigned long jtimeout; 1206 1207 jtimeout = jiffies + delay; 1208 while (tmp32 & 0x40000000) { 1209 mode = 0; 1210 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &mode); 1211 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, 1212 &ax179_data->rxctl); 1213 1214 /*link up, check the usb device control TX FIFO full or empty*/ 1215 ax88179_read_cmd(dev, 0x81, 0x8c, 0, 4, &tmp32); 1216 1217 if (time_after(jiffies, jtimeout)) 1218 return 0; 1219 } 1220 1221 mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 1222 AX_MEDIUM_RXFLOW_CTRLEN; 1223 1224 ax88179_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS, 1225 1, 1, &link_sts); 1226 1227 ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1228 GMII_PHY_PHYSR, 2, &tmp16); 1229 1230 if (!(tmp16 & GMII_PHY_PHYSR_LINK)) { 1231 return 0; 1232 } else if (GMII_PHY_PHYSR_GIGA == (tmp16 & GMII_PHY_PHYSR_SMASK)) { 1233 mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ; 1234 if (dev->net->mtu > 1500) 1235 mode |= AX_MEDIUM_JUMBO_EN; 1236 1237 if (link_sts & AX_USB_SS) 1238 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 1239 else if (link_sts & AX_USB_HS) 1240 memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5); 1241 else 1242 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 1243 } else if (GMII_PHY_PHYSR_100 == (tmp16 & GMII_PHY_PHYSR_SMASK)) { 1244 mode |= AX_MEDIUM_PS; 1245 1246 if (link_sts & (AX_USB_SS | AX_USB_HS)) 1247 memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5); 1248 else 1249 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 1250 } else { 1251 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 1252 } 1253 1254 /* RX bulk configuration */ 1255 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 1256 1257 dev->rx_urb_size = (1024 * (tmp[3] + 2)); 1258 1259 if (tmp16 & GMII_PHY_PHYSR_FULL) 1260 mode |= AX_MEDIUM_FULL_DUPLEX; 1261 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1262 2, 2, &mode); 1263 1264 netif_carrier_on(dev->net); 1265 1266 return 0; 1267 } 1268 1269 static int ax88179_reset(struct usbnet *dev) 1270 { 1271 u8 buf[5]; 1272 u16 *tmp16; 1273 u8 *tmp; 1274 1275 tmp16 = (u16 *)buf; 1276 tmp = (u8 *)buf; 1277 1278 /* Power up ethernet PHY */ 1279 *tmp16 = 0; 1280 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 1281 1282 *tmp16 = AX_PHYPWR_RSTCTL_IPRL; 1283 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 1284 msleep(200); 1285 1286 *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 1287 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); 1288 msleep(100); 1289 1290 /* Ethernet PHY Auto Detach*/ 1291 ax88179_auto_detach(dev, 0); 1292 1293 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, ETH_ALEN, 1294 dev->net->dev_addr); 1295 memcpy(dev->net->perm_addr, dev->net->dev_addr, ETH_ALEN); 1296 1297 /* RX bulk configuration */ 1298 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 1299 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 1300 1301 dev->rx_urb_size = 1024 * 20; 1302 1303 *tmp = 0x34; 1304 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); 1305 1306 *tmp = 0x52; 1307 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1308 1, 1, tmp); 1309 1310 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1311 NETIF_F_RXCSUM; 1312 1313 dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1314 NETIF_F_RXCSUM; 1315 1316 /* Enable checksum offload */ 1317 *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 1318 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 1319 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); 1320 1321 *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | 1322 AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 1323 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); 1324 1325 /* Configure RX control register => start operation */ 1326 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 1327 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 1328 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); 1329 1330 *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | 1331 AX_MONITOR_MODE_RWMP; 1332 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); 1333 1334 /* Configure default medium type => giga */ 1335 *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 1336 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX | 1337 AX_MEDIUM_GIGAMODE; 1338 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1339 2, 2, tmp16); 1340 1341 ax88179_led_setting(dev); 1342 1343 /* Restart autoneg */ 1344 mii_nway_restart(&dev->mii); 1345 1346 usbnet_link_change(dev, 0, 0); 1347 1348 return 0; 1349 } 1350 1351 static int ax88179_stop(struct usbnet *dev) 1352 { 1353 u16 tmp16; 1354 1355 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1356 2, 2, &tmp16); 1357 tmp16 &= ~AX_MEDIUM_RECEIVE_EN; 1358 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1359 2, 2, &tmp16); 1360 1361 return 0; 1362 } 1363 1364 static const struct driver_info ax88179_info = { 1365 .description = "ASIX AX88179 USB 3.0 Gigabit Ethernet", 1366 .bind = ax88179_bind, 1367 .unbind = ax88179_unbind, 1368 .status = ax88179_status, 1369 .link_reset = ax88179_link_reset, 1370 .reset = ax88179_reset, 1371 .stop = ax88179_stop, 1372 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1373 .rx_fixup = ax88179_rx_fixup, 1374 .tx_fixup = ax88179_tx_fixup, 1375 }; 1376 1377 static const struct driver_info ax88178a_info = { 1378 .description = "ASIX AX88178A USB 2.0 Gigabit Ethernet", 1379 .bind = ax88179_bind, 1380 .unbind = ax88179_unbind, 1381 .status = ax88179_status, 1382 .link_reset = ax88179_link_reset, 1383 .reset = ax88179_reset, 1384 .stop = ax88179_stop, 1385 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1386 .rx_fixup = ax88179_rx_fixup, 1387 .tx_fixup = ax88179_tx_fixup, 1388 }; 1389 1390 static const struct driver_info dlink_dub1312_info = { 1391 .description = "D-Link DUB-1312 USB 3.0 to Gigabit Ethernet Adapter", 1392 .bind = ax88179_bind, 1393 .unbind = ax88179_unbind, 1394 .status = ax88179_status, 1395 .link_reset = ax88179_link_reset, 1396 .reset = ax88179_reset, 1397 .stop = ax88179_stop, 1398 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1399 .rx_fixup = ax88179_rx_fixup, 1400 .tx_fixup = ax88179_tx_fixup, 1401 }; 1402 1403 static const struct driver_info sitecom_info = { 1404 .description = "Sitecom USB 3.0 to Gigabit Adapter", 1405 .bind = ax88179_bind, 1406 .unbind = ax88179_unbind, 1407 .status = ax88179_status, 1408 .link_reset = ax88179_link_reset, 1409 .reset = ax88179_reset, 1410 .stop = ax88179_stop, 1411 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1412 .rx_fixup = ax88179_rx_fixup, 1413 .tx_fixup = ax88179_tx_fixup, 1414 }; 1415 1416 static const struct driver_info samsung_info = { 1417 .description = "Samsung USB Ethernet Adapter", 1418 .bind = ax88179_bind, 1419 .unbind = ax88179_unbind, 1420 .status = ax88179_status, 1421 .link_reset = ax88179_link_reset, 1422 .reset = ax88179_reset, 1423 .stop = ax88179_stop, 1424 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1425 .rx_fixup = ax88179_rx_fixup, 1426 .tx_fixup = ax88179_tx_fixup, 1427 }; 1428 1429 static const struct driver_info lenovo_info = { 1430 .description = "Lenovo OneLinkDock Gigabit LAN", 1431 .bind = ax88179_bind, 1432 .unbind = ax88179_unbind, 1433 .status = ax88179_status, 1434 .link_reset = ax88179_link_reset, 1435 .reset = ax88179_reset, 1436 .stop = ax88179_stop, 1437 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1438 .rx_fixup = ax88179_rx_fixup, 1439 .tx_fixup = ax88179_tx_fixup, 1440 }; 1441 1442 static const struct usb_device_id products[] = { 1443 { 1444 /* ASIX AX88179 10/100/1000 */ 1445 USB_DEVICE(0x0b95, 0x1790), 1446 .driver_info = (unsigned long)&ax88179_info, 1447 }, { 1448 /* ASIX AX88178A 10/100/1000 */ 1449 USB_DEVICE(0x0b95, 0x178a), 1450 .driver_info = (unsigned long)&ax88178a_info, 1451 }, { 1452 /* D-Link DUB-1312 USB 3.0 to Gigabit Ethernet Adapter */ 1453 USB_DEVICE(0x2001, 0x4a00), 1454 .driver_info = (unsigned long)&dlink_dub1312_info, 1455 }, { 1456 /* Sitecom USB 3.0 to Gigabit Adapter */ 1457 USB_DEVICE(0x0df6, 0x0072), 1458 .driver_info = (unsigned long)&sitecom_info, 1459 }, { 1460 /* Samsung USB Ethernet Adapter */ 1461 USB_DEVICE(0x04e8, 0xa100), 1462 .driver_info = (unsigned long)&samsung_info, 1463 }, { 1464 /* Lenovo OneLinkDock Gigabit LAN */ 1465 USB_DEVICE(0x17ef, 0x304b), 1466 .driver_info = (unsigned long)&lenovo_info, 1467 }, 1468 { }, 1469 }; 1470 MODULE_DEVICE_TABLE(usb, products); 1471 1472 static struct usb_driver ax88179_178a_driver = { 1473 .name = "ax88179_178a", 1474 .id_table = products, 1475 .probe = usbnet_probe, 1476 .suspend = ax88179_suspend, 1477 .resume = ax88179_resume, 1478 .reset_resume = ax88179_resume, 1479 .disconnect = usbnet_disconnect, 1480 .supports_autosuspend = 1, 1481 .disable_hub_initiated_lpm = 1, 1482 }; 1483 1484 module_usb_driver(ax88179_178a_driver); 1485 1486 MODULE_DESCRIPTION("ASIX AX88179/178A based USB 3.0/2.0 Gigabit Ethernet Devices"); 1487 MODULE_LICENSE("GPL"); 1488