1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ASIX AX88179/178A USB 3.0/2.0 to Gigabit Ethernet Devices 4 * 5 * Copyright (C) 2011-2013 ASIX 6 */ 7 8 #include <linux/module.h> 9 #include <linux/etherdevice.h> 10 #include <linux/mii.h> 11 #include <linux/usb.h> 12 #include <linux/crc32.h> 13 #include <linux/usb/usbnet.h> 14 #include <uapi/linux/mdio.h> 15 #include <linux/mdio.h> 16 17 #define AX88179_PHY_ID 0x03 18 #define AX_EEPROM_LEN 0x100 19 #define AX88179_EEPROM_MAGIC 0x17900b95 20 #define AX_MCAST_FLTSIZE 8 21 #define AX_MAX_MCAST 64 22 #define AX_INT_PPLS_LINK ((u32)BIT(16)) 23 #define AX_RXHDR_L4_TYPE_MASK 0x1c 24 #define AX_RXHDR_L4_TYPE_UDP 4 25 #define AX_RXHDR_L4_TYPE_TCP 16 26 #define AX_RXHDR_L3CSUM_ERR 2 27 #define AX_RXHDR_L4CSUM_ERR 1 28 #define AX_RXHDR_CRC_ERR ((u32)BIT(29)) 29 #define AX_RXHDR_DROP_ERR ((u32)BIT(31)) 30 #define AX_ACCESS_MAC 0x01 31 #define AX_ACCESS_PHY 0x02 32 #define AX_ACCESS_EEPROM 0x04 33 #define AX_ACCESS_EFUS 0x05 34 #define AX_PAUSE_WATERLVL_HIGH 0x54 35 #define AX_PAUSE_WATERLVL_LOW 0x55 36 37 #define PHYSICAL_LINK_STATUS 0x02 38 #define AX_USB_SS 0x04 39 #define AX_USB_HS 0x02 40 41 #define GENERAL_STATUS 0x03 42 /* Check AX88179 version. UA1:Bit2 = 0, UA2:Bit2 = 1 */ 43 #define AX_SECLD 0x04 44 45 #define AX_SROM_ADDR 0x07 46 #define AX_SROM_CMD 0x0a 47 #define EEP_RD 0x04 48 #define EEP_BUSY 0x10 49 50 #define AX_SROM_DATA_LOW 0x08 51 #define AX_SROM_DATA_HIGH 0x09 52 53 #define AX_RX_CTL 0x0b 54 #define AX_RX_CTL_DROPCRCERR 0x0100 55 #define AX_RX_CTL_IPE 0x0200 56 #define AX_RX_CTL_START 0x0080 57 #define AX_RX_CTL_AP 0x0020 58 #define AX_RX_CTL_AM 0x0010 59 #define AX_RX_CTL_AB 0x0008 60 #define AX_RX_CTL_AMALL 0x0002 61 #define AX_RX_CTL_PRO 0x0001 62 #define AX_RX_CTL_STOP 0x0000 63 64 #define AX_NODE_ID 0x10 65 #define AX_MULFLTARY 0x16 66 67 #define AX_MEDIUM_STATUS_MODE 0x22 68 #define AX_MEDIUM_GIGAMODE 0x01 69 #define AX_MEDIUM_FULL_DUPLEX 0x02 70 #define AX_MEDIUM_EN_125MHZ 0x08 71 #define AX_MEDIUM_RXFLOW_CTRLEN 0x10 72 #define AX_MEDIUM_TXFLOW_CTRLEN 0x20 73 #define AX_MEDIUM_RECEIVE_EN 0x100 74 #define AX_MEDIUM_PS 0x200 75 #define AX_MEDIUM_JUMBO_EN 0x8040 76 77 #define AX_MONITOR_MOD 0x24 78 #define AX_MONITOR_MODE_RWLC 0x02 79 #define AX_MONITOR_MODE_RWMP 0x04 80 #define AX_MONITOR_MODE_PMEPOL 0x20 81 #define AX_MONITOR_MODE_PMETYPE 0x40 82 83 #define AX_GPIO_CTRL 0x25 84 #define AX_GPIO_CTRL_GPIO3EN 0x80 85 #define AX_GPIO_CTRL_GPIO2EN 0x40 86 #define AX_GPIO_CTRL_GPIO1EN 0x20 87 88 #define AX_PHYPWR_RSTCTL 0x26 89 #define AX_PHYPWR_RSTCTL_BZ 0x0010 90 #define AX_PHYPWR_RSTCTL_IPRL 0x0020 91 #define AX_PHYPWR_RSTCTL_AT 0x1000 92 93 #define AX_RX_BULKIN_QCTRL 0x2e 94 #define AX_CLK_SELECT 0x33 95 #define AX_CLK_SELECT_BCS 0x01 96 #define AX_CLK_SELECT_ACS 0x02 97 #define AX_CLK_SELECT_ULR 0x08 98 99 #define AX_RXCOE_CTL 0x34 100 #define AX_RXCOE_IP 0x01 101 #define AX_RXCOE_TCP 0x02 102 #define AX_RXCOE_UDP 0x04 103 #define AX_RXCOE_TCPV6 0x20 104 #define AX_RXCOE_UDPV6 0x40 105 106 #define AX_TXCOE_CTL 0x35 107 #define AX_TXCOE_IP 0x01 108 #define AX_TXCOE_TCP 0x02 109 #define AX_TXCOE_UDP 0x04 110 #define AX_TXCOE_TCPV6 0x20 111 #define AX_TXCOE_UDPV6 0x40 112 113 #define AX_LEDCTRL 0x73 114 115 #define GMII_PHY_PHYSR 0x11 116 #define GMII_PHY_PHYSR_SMASK 0xc000 117 #define GMII_PHY_PHYSR_GIGA 0x8000 118 #define GMII_PHY_PHYSR_100 0x4000 119 #define GMII_PHY_PHYSR_FULL 0x2000 120 #define GMII_PHY_PHYSR_LINK 0x400 121 122 #define GMII_LED_ACT 0x1a 123 #define GMII_LED_ACTIVE_MASK 0xff8f 124 #define GMII_LED0_ACTIVE BIT(4) 125 #define GMII_LED1_ACTIVE BIT(5) 126 #define GMII_LED2_ACTIVE BIT(6) 127 128 #define GMII_LED_LINK 0x1c 129 #define GMII_LED_LINK_MASK 0xf888 130 #define GMII_LED0_LINK_10 BIT(0) 131 #define GMII_LED0_LINK_100 BIT(1) 132 #define GMII_LED0_LINK_1000 BIT(2) 133 #define GMII_LED1_LINK_10 BIT(4) 134 #define GMII_LED1_LINK_100 BIT(5) 135 #define GMII_LED1_LINK_1000 BIT(6) 136 #define GMII_LED2_LINK_10 BIT(8) 137 #define GMII_LED2_LINK_100 BIT(9) 138 #define GMII_LED2_LINK_1000 BIT(10) 139 #define LED0_ACTIVE BIT(0) 140 #define LED0_LINK_10 BIT(1) 141 #define LED0_LINK_100 BIT(2) 142 #define LED0_LINK_1000 BIT(3) 143 #define LED0_FD BIT(4) 144 #define LED0_USB3_MASK 0x001f 145 #define LED1_ACTIVE BIT(5) 146 #define LED1_LINK_10 BIT(6) 147 #define LED1_LINK_100 BIT(7) 148 #define LED1_LINK_1000 BIT(8) 149 #define LED1_FD BIT(9) 150 #define LED1_USB3_MASK 0x03e0 151 #define LED2_ACTIVE BIT(10) 152 #define LED2_LINK_1000 BIT(13) 153 #define LED2_LINK_100 BIT(12) 154 #define LED2_LINK_10 BIT(11) 155 #define LED2_FD BIT(14) 156 #define LED_VALID BIT(15) 157 #define LED2_USB3_MASK 0x7c00 158 159 #define GMII_PHYPAGE 0x1e 160 #define GMII_PHY_PAGE_SELECT 0x1f 161 #define GMII_PHY_PGSEL_EXT 0x0007 162 #define GMII_PHY_PGSEL_PAGE0 0x0000 163 #define GMII_PHY_PGSEL_PAGE3 0x0003 164 #define GMII_PHY_PGSEL_PAGE5 0x0005 165 166 struct ax88179_data { 167 u8 eee_enabled; 168 u8 eee_active; 169 u16 rxctl; 170 u16 reserved; 171 }; 172 173 struct ax88179_int_data { 174 __le32 intdata1; 175 __le32 intdata2; 176 }; 177 178 static const struct { 179 unsigned char ctrl, timer_l, timer_h, size, ifg; 180 } AX88179_BULKIN_SIZE[] = { 181 {7, 0x4f, 0, 0x12, 0xff}, 182 {7, 0x20, 3, 0x16, 0xff}, 183 {7, 0xae, 7, 0x18, 0xff}, 184 {7, 0xcc, 0x4c, 0x18, 8}, 185 }; 186 187 static int __ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 188 u16 size, void *data, int in_pm) 189 { 190 int ret; 191 int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16); 192 193 BUG_ON(!dev); 194 195 if (!in_pm) 196 fn = usbnet_read_cmd; 197 else 198 fn = usbnet_read_cmd_nopm; 199 200 ret = fn(dev, cmd, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 201 value, index, data, size); 202 203 if (unlikely(ret < 0)) 204 netdev_warn(dev->net, "Failed to read reg index 0x%04x: %d\n", 205 index, ret); 206 207 return ret; 208 } 209 210 static int __ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 211 u16 size, void *data, int in_pm) 212 { 213 int ret; 214 int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16); 215 216 BUG_ON(!dev); 217 218 if (!in_pm) 219 fn = usbnet_write_cmd; 220 else 221 fn = usbnet_write_cmd_nopm; 222 223 ret = fn(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 224 value, index, data, size); 225 226 if (unlikely(ret < 0)) 227 netdev_warn(dev->net, "Failed to write reg index 0x%04x: %d\n", 228 index, ret); 229 230 return ret; 231 } 232 233 static void ax88179_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, 234 u16 index, u16 size, void *data) 235 { 236 u16 buf; 237 238 if (2 == size) { 239 buf = *((u16 *)data); 240 cpu_to_le16s(&buf); 241 usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | 242 USB_RECIP_DEVICE, value, index, &buf, 243 size); 244 } else { 245 usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | 246 USB_RECIP_DEVICE, value, index, data, 247 size); 248 } 249 } 250 251 static int ax88179_read_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value, 252 u16 index, u16 size, void *data) 253 { 254 int ret; 255 256 if (2 == size) { 257 u16 buf; 258 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1); 259 le16_to_cpus(&buf); 260 *((u16 *)data) = buf; 261 } else if (4 == size) { 262 u32 buf; 263 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1); 264 le32_to_cpus(&buf); 265 *((u32 *)data) = buf; 266 } else { 267 ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 1); 268 } 269 270 return ret; 271 } 272 273 static int ax88179_write_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value, 274 u16 index, u16 size, void *data) 275 { 276 int ret; 277 278 if (2 == size) { 279 u16 buf; 280 buf = *((u16 *)data); 281 cpu_to_le16s(&buf); 282 ret = __ax88179_write_cmd(dev, cmd, value, index, 283 size, &buf, 1); 284 } else { 285 ret = __ax88179_write_cmd(dev, cmd, value, index, 286 size, data, 1); 287 } 288 289 return ret; 290 } 291 292 static int ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 293 u16 size, void *data) 294 { 295 int ret; 296 297 if (2 == size) { 298 u16 buf; 299 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0); 300 le16_to_cpus(&buf); 301 *((u16 *)data) = buf; 302 } else if (4 == size) { 303 u32 buf; 304 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0); 305 le32_to_cpus(&buf); 306 *((u32 *)data) = buf; 307 } else { 308 ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 0); 309 } 310 311 return ret; 312 } 313 314 static int ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 315 u16 size, void *data) 316 { 317 int ret; 318 319 if (2 == size) { 320 u16 buf; 321 buf = *((u16 *)data); 322 cpu_to_le16s(&buf); 323 ret = __ax88179_write_cmd(dev, cmd, value, index, 324 size, &buf, 0); 325 } else { 326 ret = __ax88179_write_cmd(dev, cmd, value, index, 327 size, data, 0); 328 } 329 330 return ret; 331 } 332 333 static void ax88179_status(struct usbnet *dev, struct urb *urb) 334 { 335 struct ax88179_int_data *event; 336 u32 link; 337 338 if (urb->actual_length < 8) 339 return; 340 341 event = urb->transfer_buffer; 342 le32_to_cpus((void *)&event->intdata1); 343 344 link = (((__force u32)event->intdata1) & AX_INT_PPLS_LINK) >> 16; 345 346 if (netif_carrier_ok(dev->net) != link) { 347 usbnet_link_change(dev, link, 1); 348 netdev_info(dev->net, "ax88179 - Link status is: %d\n", link); 349 } 350 } 351 352 static int ax88179_mdio_read(struct net_device *netdev, int phy_id, int loc) 353 { 354 struct usbnet *dev = netdev_priv(netdev); 355 u16 res; 356 357 ax88179_read_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res); 358 return res; 359 } 360 361 static void ax88179_mdio_write(struct net_device *netdev, int phy_id, int loc, 362 int val) 363 { 364 struct usbnet *dev = netdev_priv(netdev); 365 u16 res = (u16) val; 366 367 ax88179_write_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res); 368 } 369 370 static inline int ax88179_phy_mmd_indirect(struct usbnet *dev, u16 prtad, 371 u16 devad) 372 { 373 u16 tmp16; 374 int ret; 375 376 tmp16 = devad; 377 ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 378 MII_MMD_CTRL, 2, &tmp16); 379 380 tmp16 = prtad; 381 ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 382 MII_MMD_DATA, 2, &tmp16); 383 384 tmp16 = devad | MII_MMD_CTRL_NOINCR; 385 ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 386 MII_MMD_CTRL, 2, &tmp16); 387 388 return ret; 389 } 390 391 static int 392 ax88179_phy_read_mmd_indirect(struct usbnet *dev, u16 prtad, u16 devad) 393 { 394 int ret; 395 u16 tmp16; 396 397 ax88179_phy_mmd_indirect(dev, prtad, devad); 398 399 ret = ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 400 MII_MMD_DATA, 2, &tmp16); 401 if (ret < 0) 402 return ret; 403 404 return tmp16; 405 } 406 407 static int 408 ax88179_phy_write_mmd_indirect(struct usbnet *dev, u16 prtad, u16 devad, 409 u16 data) 410 { 411 int ret; 412 413 ax88179_phy_mmd_indirect(dev, prtad, devad); 414 415 ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 416 MII_MMD_DATA, 2, &data); 417 418 if (ret < 0) 419 return ret; 420 421 return 0; 422 } 423 424 static int ax88179_suspend(struct usb_interface *intf, pm_message_t message) 425 { 426 struct usbnet *dev = usb_get_intfdata(intf); 427 u16 tmp16; 428 u8 tmp8; 429 430 usbnet_suspend(intf, message); 431 432 /* Disable RX path */ 433 ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 434 2, 2, &tmp16); 435 tmp16 &= ~AX_MEDIUM_RECEIVE_EN; 436 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 437 2, 2, &tmp16); 438 439 /* Force bulk-in zero length */ 440 ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 441 2, 2, &tmp16); 442 443 tmp16 |= AX_PHYPWR_RSTCTL_BZ | AX_PHYPWR_RSTCTL_IPRL; 444 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 445 2, 2, &tmp16); 446 447 /* change clock */ 448 tmp8 = 0; 449 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 450 451 /* Configure RX control register => stop operation */ 452 tmp16 = AX_RX_CTL_STOP; 453 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16); 454 455 return 0; 456 } 457 458 /* This function is used to enable the autodetach function. */ 459 /* This function is determined by offset 0x43 of EEPROM */ 460 static int ax88179_auto_detach(struct usbnet *dev, int in_pm) 461 { 462 u16 tmp16; 463 u8 tmp8; 464 int (*fnr)(struct usbnet *, u8, u16, u16, u16, void *); 465 int (*fnw)(struct usbnet *, u8, u16, u16, u16, void *); 466 467 if (!in_pm) { 468 fnr = ax88179_read_cmd; 469 fnw = ax88179_write_cmd; 470 } else { 471 fnr = ax88179_read_cmd_nopm; 472 fnw = ax88179_write_cmd_nopm; 473 } 474 475 if (fnr(dev, AX_ACCESS_EEPROM, 0x43, 1, 2, &tmp16) < 0) 476 return 0; 477 478 if ((tmp16 == 0xFFFF) || (!(tmp16 & 0x0100))) 479 return 0; 480 481 /* Enable Auto Detach bit */ 482 tmp8 = 0; 483 fnr(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 484 tmp8 |= AX_CLK_SELECT_ULR; 485 fnw(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 486 487 fnr(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16); 488 tmp16 |= AX_PHYPWR_RSTCTL_AT; 489 fnw(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16); 490 491 return 0; 492 } 493 494 static int ax88179_resume(struct usb_interface *intf) 495 { 496 struct usbnet *dev = usb_get_intfdata(intf); 497 u16 tmp16; 498 u8 tmp8; 499 500 usbnet_link_change(dev, 0, 0); 501 502 /* Power up ethernet PHY */ 503 tmp16 = 0; 504 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 505 2, 2, &tmp16); 506 udelay(1000); 507 508 tmp16 = AX_PHYPWR_RSTCTL_IPRL; 509 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 510 2, 2, &tmp16); 511 msleep(200); 512 513 /* Ethernet PHY Auto Detach*/ 514 ax88179_auto_detach(dev, 1); 515 516 /* Enable clock */ 517 ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 518 tmp8 |= AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 519 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 520 msleep(100); 521 522 /* Configure RX control register => start operation */ 523 tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 524 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 525 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16); 526 527 return usbnet_resume(intf); 528 } 529 530 static void 531 ax88179_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) 532 { 533 struct usbnet *dev = netdev_priv(net); 534 u8 opt; 535 536 if (ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 537 1, 1, &opt) < 0) { 538 wolinfo->supported = 0; 539 wolinfo->wolopts = 0; 540 return; 541 } 542 543 wolinfo->supported = WAKE_PHY | WAKE_MAGIC; 544 wolinfo->wolopts = 0; 545 if (opt & AX_MONITOR_MODE_RWLC) 546 wolinfo->wolopts |= WAKE_PHY; 547 if (opt & AX_MONITOR_MODE_RWMP) 548 wolinfo->wolopts |= WAKE_MAGIC; 549 } 550 551 static int 552 ax88179_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) 553 { 554 struct usbnet *dev = netdev_priv(net); 555 u8 opt = 0; 556 557 if (wolinfo->wolopts & ~(WAKE_PHY | WAKE_MAGIC)) 558 return -EINVAL; 559 560 if (wolinfo->wolopts & WAKE_PHY) 561 opt |= AX_MONITOR_MODE_RWLC; 562 if (wolinfo->wolopts & WAKE_MAGIC) 563 opt |= AX_MONITOR_MODE_RWMP; 564 565 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 566 1, 1, &opt) < 0) 567 return -EINVAL; 568 569 return 0; 570 } 571 572 static int ax88179_get_eeprom_len(struct net_device *net) 573 { 574 return AX_EEPROM_LEN; 575 } 576 577 static int 578 ax88179_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom, 579 u8 *data) 580 { 581 struct usbnet *dev = netdev_priv(net); 582 u16 *eeprom_buff; 583 int first_word, last_word; 584 int i, ret; 585 586 if (eeprom->len == 0) 587 return -EINVAL; 588 589 eeprom->magic = AX88179_EEPROM_MAGIC; 590 591 first_word = eeprom->offset >> 1; 592 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 593 eeprom_buff = kmalloc_array(last_word - first_word + 1, sizeof(u16), 594 GFP_KERNEL); 595 if (!eeprom_buff) 596 return -ENOMEM; 597 598 /* ax88179/178A returns 2 bytes from eeprom on read */ 599 for (i = first_word; i <= last_word; i++) { 600 ret = __ax88179_read_cmd(dev, AX_ACCESS_EEPROM, i, 1, 2, 601 &eeprom_buff[i - first_word], 602 0); 603 if (ret < 0) { 604 kfree(eeprom_buff); 605 return -EIO; 606 } 607 } 608 609 memcpy(data, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); 610 kfree(eeprom_buff); 611 return 0; 612 } 613 614 static int ax88179_get_link_ksettings(struct net_device *net, 615 struct ethtool_link_ksettings *cmd) 616 { 617 struct usbnet *dev = netdev_priv(net); 618 619 mii_ethtool_get_link_ksettings(&dev->mii, cmd); 620 621 return 0; 622 } 623 624 static int ax88179_set_link_ksettings(struct net_device *net, 625 const struct ethtool_link_ksettings *cmd) 626 { 627 struct usbnet *dev = netdev_priv(net); 628 return mii_ethtool_set_link_ksettings(&dev->mii, cmd); 629 } 630 631 static int 632 ax88179_ethtool_get_eee(struct usbnet *dev, struct ethtool_eee *data) 633 { 634 int val; 635 636 /* Get Supported EEE */ 637 val = ax88179_phy_read_mmd_indirect(dev, MDIO_PCS_EEE_ABLE, 638 MDIO_MMD_PCS); 639 if (val < 0) 640 return val; 641 data->supported = mmd_eee_cap_to_ethtool_sup_t(val); 642 643 /* Get advertisement EEE */ 644 val = ax88179_phy_read_mmd_indirect(dev, MDIO_AN_EEE_ADV, 645 MDIO_MMD_AN); 646 if (val < 0) 647 return val; 648 data->advertised = mmd_eee_adv_to_ethtool_adv_t(val); 649 650 /* Get LP advertisement EEE */ 651 val = ax88179_phy_read_mmd_indirect(dev, MDIO_AN_EEE_LPABLE, 652 MDIO_MMD_AN); 653 if (val < 0) 654 return val; 655 data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val); 656 657 return 0; 658 } 659 660 static int 661 ax88179_ethtool_set_eee(struct usbnet *dev, struct ethtool_eee *data) 662 { 663 u16 tmp16 = ethtool_adv_to_mmd_eee_adv_t(data->advertised); 664 665 return ax88179_phy_write_mmd_indirect(dev, MDIO_AN_EEE_ADV, 666 MDIO_MMD_AN, tmp16); 667 } 668 669 static int ax88179_chk_eee(struct usbnet *dev) 670 { 671 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 672 struct ax88179_data *priv = (struct ax88179_data *)dev->data; 673 674 mii_ethtool_gset(&dev->mii, &ecmd); 675 676 if (ecmd.duplex & DUPLEX_FULL) { 677 int eee_lp, eee_cap, eee_adv; 678 u32 lp, cap, adv, supported = 0; 679 680 eee_cap = ax88179_phy_read_mmd_indirect(dev, 681 MDIO_PCS_EEE_ABLE, 682 MDIO_MMD_PCS); 683 if (eee_cap < 0) { 684 priv->eee_active = 0; 685 return false; 686 } 687 688 cap = mmd_eee_cap_to_ethtool_sup_t(eee_cap); 689 if (!cap) { 690 priv->eee_active = 0; 691 return false; 692 } 693 694 eee_lp = ax88179_phy_read_mmd_indirect(dev, 695 MDIO_AN_EEE_LPABLE, 696 MDIO_MMD_AN); 697 if (eee_lp < 0) { 698 priv->eee_active = 0; 699 return false; 700 } 701 702 eee_adv = ax88179_phy_read_mmd_indirect(dev, 703 MDIO_AN_EEE_ADV, 704 MDIO_MMD_AN); 705 706 if (eee_adv < 0) { 707 priv->eee_active = 0; 708 return false; 709 } 710 711 adv = mmd_eee_adv_to_ethtool_adv_t(eee_adv); 712 lp = mmd_eee_adv_to_ethtool_adv_t(eee_lp); 713 supported = (ecmd.speed == SPEED_1000) ? 714 SUPPORTED_1000baseT_Full : 715 SUPPORTED_100baseT_Full; 716 717 if (!(lp & adv & supported)) { 718 priv->eee_active = 0; 719 return false; 720 } 721 722 priv->eee_active = 1; 723 return true; 724 } 725 726 priv->eee_active = 0; 727 return false; 728 } 729 730 static void ax88179_disable_eee(struct usbnet *dev) 731 { 732 u16 tmp16; 733 734 tmp16 = GMII_PHY_PGSEL_PAGE3; 735 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 736 GMII_PHY_PAGE_SELECT, 2, &tmp16); 737 738 tmp16 = 0x3246; 739 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 740 MII_PHYADDR, 2, &tmp16); 741 742 tmp16 = GMII_PHY_PGSEL_PAGE0; 743 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 744 GMII_PHY_PAGE_SELECT, 2, &tmp16); 745 } 746 747 static void ax88179_enable_eee(struct usbnet *dev) 748 { 749 u16 tmp16; 750 751 tmp16 = GMII_PHY_PGSEL_PAGE3; 752 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 753 GMII_PHY_PAGE_SELECT, 2, &tmp16); 754 755 tmp16 = 0x3247; 756 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 757 MII_PHYADDR, 2, &tmp16); 758 759 tmp16 = GMII_PHY_PGSEL_PAGE5; 760 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 761 GMII_PHY_PAGE_SELECT, 2, &tmp16); 762 763 tmp16 = 0x0680; 764 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 765 MII_BMSR, 2, &tmp16); 766 767 tmp16 = GMII_PHY_PGSEL_PAGE0; 768 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 769 GMII_PHY_PAGE_SELECT, 2, &tmp16); 770 } 771 772 static int ax88179_get_eee(struct net_device *net, struct ethtool_eee *edata) 773 { 774 struct usbnet *dev = netdev_priv(net); 775 struct ax88179_data *priv = (struct ax88179_data *)dev->data; 776 777 edata->eee_enabled = priv->eee_enabled; 778 edata->eee_active = priv->eee_active; 779 780 return ax88179_ethtool_get_eee(dev, edata); 781 } 782 783 static int ax88179_set_eee(struct net_device *net, struct ethtool_eee *edata) 784 { 785 struct usbnet *dev = netdev_priv(net); 786 struct ax88179_data *priv = (struct ax88179_data *)dev->data; 787 int ret = -EOPNOTSUPP; 788 789 priv->eee_enabled = edata->eee_enabled; 790 if (!priv->eee_enabled) { 791 ax88179_disable_eee(dev); 792 } else { 793 priv->eee_enabled = ax88179_chk_eee(dev); 794 if (!priv->eee_enabled) 795 return -EOPNOTSUPP; 796 797 ax88179_enable_eee(dev); 798 } 799 800 ret = ax88179_ethtool_set_eee(dev, edata); 801 if (ret) 802 return ret; 803 804 mii_nway_restart(&dev->mii); 805 806 usbnet_link_change(dev, 0, 0); 807 808 return ret; 809 } 810 811 static int ax88179_ioctl(struct net_device *net, struct ifreq *rq, int cmd) 812 { 813 struct usbnet *dev = netdev_priv(net); 814 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); 815 } 816 817 static const struct ethtool_ops ax88179_ethtool_ops = { 818 .get_link = ethtool_op_get_link, 819 .get_msglevel = usbnet_get_msglevel, 820 .set_msglevel = usbnet_set_msglevel, 821 .get_wol = ax88179_get_wol, 822 .set_wol = ax88179_set_wol, 823 .get_eeprom_len = ax88179_get_eeprom_len, 824 .get_eeprom = ax88179_get_eeprom, 825 .get_eee = ax88179_get_eee, 826 .set_eee = ax88179_set_eee, 827 .nway_reset = usbnet_nway_reset, 828 .get_link_ksettings = ax88179_get_link_ksettings, 829 .set_link_ksettings = ax88179_set_link_ksettings, 830 .get_ts_info = ethtool_op_get_ts_info, 831 }; 832 833 static void ax88179_set_multicast(struct net_device *net) 834 { 835 struct usbnet *dev = netdev_priv(net); 836 struct ax88179_data *data = (struct ax88179_data *)dev->data; 837 u8 *m_filter = ((u8 *)dev->data) + 12; 838 839 data->rxctl = (AX_RX_CTL_START | AX_RX_CTL_AB | AX_RX_CTL_IPE); 840 841 if (net->flags & IFF_PROMISC) { 842 data->rxctl |= AX_RX_CTL_PRO; 843 } else if (net->flags & IFF_ALLMULTI || 844 netdev_mc_count(net) > AX_MAX_MCAST) { 845 data->rxctl |= AX_RX_CTL_AMALL; 846 } else if (netdev_mc_empty(net)) { 847 /* just broadcast and directed */ 848 } else { 849 /* We use the 20 byte dev->data for our 8 byte filter buffer 850 * to avoid allocating memory that is tricky to free later 851 */ 852 u32 crc_bits; 853 struct netdev_hw_addr *ha; 854 855 memset(m_filter, 0, AX_MCAST_FLTSIZE); 856 857 netdev_for_each_mc_addr(ha, net) { 858 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; 859 *(m_filter + (crc_bits >> 3)) |= (1 << (crc_bits & 7)); 860 } 861 862 ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_MULFLTARY, 863 AX_MCAST_FLTSIZE, AX_MCAST_FLTSIZE, 864 m_filter); 865 866 data->rxctl |= AX_RX_CTL_AM; 867 } 868 869 ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_RX_CTL, 870 2, 2, &data->rxctl); 871 } 872 873 static int 874 ax88179_set_features(struct net_device *net, netdev_features_t features) 875 { 876 u8 tmp; 877 struct usbnet *dev = netdev_priv(net); 878 netdev_features_t changed = net->features ^ features; 879 880 if (changed & NETIF_F_IP_CSUM) { 881 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 882 tmp ^= AX_TXCOE_TCP | AX_TXCOE_UDP; 883 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 884 } 885 886 if (changed & NETIF_F_IPV6_CSUM) { 887 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 888 tmp ^= AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 889 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 890 } 891 892 if (changed & NETIF_F_RXCSUM) { 893 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp); 894 tmp ^= AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 895 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 896 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp); 897 } 898 899 return 0; 900 } 901 902 static int ax88179_change_mtu(struct net_device *net, int new_mtu) 903 { 904 struct usbnet *dev = netdev_priv(net); 905 u16 tmp16; 906 907 net->mtu = new_mtu; 908 dev->hard_mtu = net->mtu + net->hard_header_len; 909 910 if (net->mtu > 1500) { 911 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 912 2, 2, &tmp16); 913 tmp16 |= AX_MEDIUM_JUMBO_EN; 914 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 915 2, 2, &tmp16); 916 } else { 917 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 918 2, 2, &tmp16); 919 tmp16 &= ~AX_MEDIUM_JUMBO_EN; 920 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 921 2, 2, &tmp16); 922 } 923 924 /* max qlen depend on hard_mtu and rx_urb_size */ 925 usbnet_update_max_qlen(dev); 926 927 return 0; 928 } 929 930 static int ax88179_set_mac_addr(struct net_device *net, void *p) 931 { 932 struct usbnet *dev = netdev_priv(net); 933 struct sockaddr *addr = p; 934 int ret; 935 936 if (netif_running(net)) 937 return -EBUSY; 938 if (!is_valid_ether_addr(addr->sa_data)) 939 return -EADDRNOTAVAIL; 940 941 memcpy(net->dev_addr, addr->sa_data, ETH_ALEN); 942 943 /* Set the MAC address */ 944 ret = ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, 945 ETH_ALEN, net->dev_addr); 946 if (ret < 0) 947 return ret; 948 949 return 0; 950 } 951 952 static const struct net_device_ops ax88179_netdev_ops = { 953 .ndo_open = usbnet_open, 954 .ndo_stop = usbnet_stop, 955 .ndo_start_xmit = usbnet_start_xmit, 956 .ndo_tx_timeout = usbnet_tx_timeout, 957 .ndo_get_stats64 = usbnet_get_stats64, 958 .ndo_change_mtu = ax88179_change_mtu, 959 .ndo_set_mac_address = ax88179_set_mac_addr, 960 .ndo_validate_addr = eth_validate_addr, 961 .ndo_do_ioctl = ax88179_ioctl, 962 .ndo_set_rx_mode = ax88179_set_multicast, 963 .ndo_set_features = ax88179_set_features, 964 }; 965 966 static int ax88179_check_eeprom(struct usbnet *dev) 967 { 968 u8 i, buf, eeprom[20]; 969 u16 csum, delay = HZ / 10; 970 unsigned long jtimeout; 971 972 /* Read EEPROM content */ 973 for (i = 0; i < 6; i++) { 974 buf = i; 975 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR, 976 1, 1, &buf) < 0) 977 return -EINVAL; 978 979 buf = EEP_RD; 980 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 981 1, 1, &buf) < 0) 982 return -EINVAL; 983 984 jtimeout = jiffies + delay; 985 do { 986 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 987 1, 1, &buf); 988 989 if (time_after(jiffies, jtimeout)) 990 return -EINVAL; 991 992 } while (buf & EEP_BUSY); 993 994 __ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW, 995 2, 2, &eeprom[i * 2], 0); 996 997 if ((i == 0) && (eeprom[0] == 0xFF)) 998 return -EINVAL; 999 } 1000 1001 csum = eeprom[6] + eeprom[7] + eeprom[8] + eeprom[9]; 1002 csum = (csum >> 8) + (csum & 0xff); 1003 if ((csum + eeprom[10]) != 0xff) 1004 return -EINVAL; 1005 1006 return 0; 1007 } 1008 1009 static int ax88179_check_efuse(struct usbnet *dev, u16 *ledmode) 1010 { 1011 u8 i; 1012 u8 efuse[64]; 1013 u16 csum = 0; 1014 1015 if (ax88179_read_cmd(dev, AX_ACCESS_EFUS, 0, 64, 64, efuse) < 0) 1016 return -EINVAL; 1017 1018 if (*efuse == 0xFF) 1019 return -EINVAL; 1020 1021 for (i = 0; i < 64; i++) 1022 csum = csum + efuse[i]; 1023 1024 while (csum > 255) 1025 csum = (csum & 0x00FF) + ((csum >> 8) & 0x00FF); 1026 1027 if (csum != 0xFF) 1028 return -EINVAL; 1029 1030 *ledmode = (efuse[51] << 8) | efuse[52]; 1031 1032 return 0; 1033 } 1034 1035 static int ax88179_convert_old_led(struct usbnet *dev, u16 *ledvalue) 1036 { 1037 u16 led; 1038 1039 /* Loaded the old eFuse LED Mode */ 1040 if (ax88179_read_cmd(dev, AX_ACCESS_EEPROM, 0x3C, 1, 2, &led) < 0) 1041 return -EINVAL; 1042 1043 led >>= 8; 1044 switch (led) { 1045 case 0xFF: 1046 led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 | 1047 LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 | 1048 LED2_LINK_100 | LED2_LINK_1000 | LED_VALID; 1049 break; 1050 case 0xFE: 1051 led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 | LED_VALID; 1052 break; 1053 case 0xFD: 1054 led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 | 1055 LED2_LINK_10 | LED_VALID; 1056 break; 1057 case 0xFC: 1058 led = LED0_ACTIVE | LED1_ACTIVE | LED1_LINK_1000 | LED2_ACTIVE | 1059 LED2_LINK_100 | LED2_LINK_10 | LED_VALID; 1060 break; 1061 default: 1062 led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 | 1063 LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 | 1064 LED2_LINK_100 | LED2_LINK_1000 | LED_VALID; 1065 break; 1066 } 1067 1068 *ledvalue = led; 1069 1070 return 0; 1071 } 1072 1073 static int ax88179_led_setting(struct usbnet *dev) 1074 { 1075 u8 ledfd, value = 0; 1076 u16 tmp, ledact, ledlink, ledvalue = 0, delay = HZ / 10; 1077 unsigned long jtimeout; 1078 1079 /* Check AX88179 version. UA1 or UA2*/ 1080 ax88179_read_cmd(dev, AX_ACCESS_MAC, GENERAL_STATUS, 1, 1, &value); 1081 1082 if (!(value & AX_SECLD)) { /* UA1 */ 1083 value = AX_GPIO_CTRL_GPIO3EN | AX_GPIO_CTRL_GPIO2EN | 1084 AX_GPIO_CTRL_GPIO1EN; 1085 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_GPIO_CTRL, 1086 1, 1, &value) < 0) 1087 return -EINVAL; 1088 } 1089 1090 /* Check EEPROM */ 1091 if (!ax88179_check_eeprom(dev)) { 1092 value = 0x42; 1093 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR, 1094 1, 1, &value) < 0) 1095 return -EINVAL; 1096 1097 value = EEP_RD; 1098 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 1099 1, 1, &value) < 0) 1100 return -EINVAL; 1101 1102 jtimeout = jiffies + delay; 1103 do { 1104 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 1105 1, 1, &value); 1106 1107 if (time_after(jiffies, jtimeout)) 1108 return -EINVAL; 1109 1110 } while (value & EEP_BUSY); 1111 1112 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_HIGH, 1113 1, 1, &value); 1114 ledvalue = (value << 8); 1115 1116 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW, 1117 1, 1, &value); 1118 ledvalue |= value; 1119 1120 /* load internal ROM for defaule setting */ 1121 if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0)) 1122 ax88179_convert_old_led(dev, &ledvalue); 1123 1124 } else if (!ax88179_check_efuse(dev, &ledvalue)) { 1125 if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0)) 1126 ax88179_convert_old_led(dev, &ledvalue); 1127 } else { 1128 ax88179_convert_old_led(dev, &ledvalue); 1129 } 1130 1131 tmp = GMII_PHY_PGSEL_EXT; 1132 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1133 GMII_PHY_PAGE_SELECT, 2, &tmp); 1134 1135 tmp = 0x2c; 1136 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1137 GMII_PHYPAGE, 2, &tmp); 1138 1139 ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1140 GMII_LED_ACT, 2, &ledact); 1141 1142 ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1143 GMII_LED_LINK, 2, &ledlink); 1144 1145 ledact &= GMII_LED_ACTIVE_MASK; 1146 ledlink &= GMII_LED_LINK_MASK; 1147 1148 if (ledvalue & LED0_ACTIVE) 1149 ledact |= GMII_LED0_ACTIVE; 1150 1151 if (ledvalue & LED1_ACTIVE) 1152 ledact |= GMII_LED1_ACTIVE; 1153 1154 if (ledvalue & LED2_ACTIVE) 1155 ledact |= GMII_LED2_ACTIVE; 1156 1157 if (ledvalue & LED0_LINK_10) 1158 ledlink |= GMII_LED0_LINK_10; 1159 1160 if (ledvalue & LED1_LINK_10) 1161 ledlink |= GMII_LED1_LINK_10; 1162 1163 if (ledvalue & LED2_LINK_10) 1164 ledlink |= GMII_LED2_LINK_10; 1165 1166 if (ledvalue & LED0_LINK_100) 1167 ledlink |= GMII_LED0_LINK_100; 1168 1169 if (ledvalue & LED1_LINK_100) 1170 ledlink |= GMII_LED1_LINK_100; 1171 1172 if (ledvalue & LED2_LINK_100) 1173 ledlink |= GMII_LED2_LINK_100; 1174 1175 if (ledvalue & LED0_LINK_1000) 1176 ledlink |= GMII_LED0_LINK_1000; 1177 1178 if (ledvalue & LED1_LINK_1000) 1179 ledlink |= GMII_LED1_LINK_1000; 1180 1181 if (ledvalue & LED2_LINK_1000) 1182 ledlink |= GMII_LED2_LINK_1000; 1183 1184 tmp = ledact; 1185 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1186 GMII_LED_ACT, 2, &tmp); 1187 1188 tmp = ledlink; 1189 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1190 GMII_LED_LINK, 2, &tmp); 1191 1192 tmp = GMII_PHY_PGSEL_PAGE0; 1193 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1194 GMII_PHY_PAGE_SELECT, 2, &tmp); 1195 1196 /* LED full duplex setting */ 1197 ledfd = 0; 1198 if (ledvalue & LED0_FD) 1199 ledfd |= 0x01; 1200 else if ((ledvalue & LED0_USB3_MASK) == 0) 1201 ledfd |= 0x02; 1202 1203 if (ledvalue & LED1_FD) 1204 ledfd |= 0x04; 1205 else if ((ledvalue & LED1_USB3_MASK) == 0) 1206 ledfd |= 0x08; 1207 1208 if (ledvalue & LED2_FD) 1209 ledfd |= 0x10; 1210 else if ((ledvalue & LED2_USB3_MASK) == 0) 1211 ledfd |= 0x20; 1212 1213 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_LEDCTRL, 1, 1, &ledfd); 1214 1215 return 0; 1216 } 1217 1218 static void ax88179_get_mac_addr(struct usbnet *dev) 1219 { 1220 u8 mac[ETH_ALEN]; 1221 1222 /* Maybe the boot loader passed the MAC address via device tree */ 1223 if (!eth_platform_get_mac_address(&dev->udev->dev, mac)) { 1224 netif_dbg(dev, ifup, dev->net, 1225 "MAC address read from device tree"); 1226 } else { 1227 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, 1228 ETH_ALEN, mac); 1229 netif_dbg(dev, ifup, dev->net, 1230 "MAC address read from ASIX chip"); 1231 } 1232 1233 if (is_valid_ether_addr(mac)) { 1234 memcpy(dev->net->dev_addr, mac, ETH_ALEN); 1235 } else { 1236 netdev_info(dev->net, "invalid MAC address, using random\n"); 1237 eth_hw_addr_random(dev->net); 1238 } 1239 1240 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, ETH_ALEN, 1241 dev->net->dev_addr); 1242 } 1243 1244 static int ax88179_bind(struct usbnet *dev, struct usb_interface *intf) 1245 { 1246 u8 buf[5]; 1247 u16 *tmp16; 1248 u8 *tmp; 1249 struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data; 1250 struct ethtool_eee eee_data; 1251 1252 usbnet_get_endpoints(dev, intf); 1253 1254 tmp16 = (u16 *)buf; 1255 tmp = (u8 *)buf; 1256 1257 memset(ax179_data, 0, sizeof(*ax179_data)); 1258 1259 /* Power up ethernet PHY */ 1260 *tmp16 = 0; 1261 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 1262 *tmp16 = AX_PHYPWR_RSTCTL_IPRL; 1263 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 1264 msleep(200); 1265 1266 *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 1267 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); 1268 msleep(100); 1269 1270 /* Read MAC address from DTB or asix chip */ 1271 ax88179_get_mac_addr(dev); 1272 memcpy(dev->net->perm_addr, dev->net->dev_addr, ETH_ALEN); 1273 1274 /* RX bulk configuration */ 1275 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 1276 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 1277 1278 dev->rx_urb_size = 1024 * 20; 1279 1280 *tmp = 0x34; 1281 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); 1282 1283 *tmp = 0x52; 1284 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1285 1, 1, tmp); 1286 1287 dev->net->netdev_ops = &ax88179_netdev_ops; 1288 dev->net->ethtool_ops = &ax88179_ethtool_ops; 1289 dev->net->needed_headroom = 8; 1290 dev->net->max_mtu = 4088; 1291 1292 /* Initialize MII structure */ 1293 dev->mii.dev = dev->net; 1294 dev->mii.mdio_read = ax88179_mdio_read; 1295 dev->mii.mdio_write = ax88179_mdio_write; 1296 dev->mii.phy_id_mask = 0xff; 1297 dev->mii.reg_num_mask = 0xff; 1298 dev->mii.phy_id = 0x03; 1299 dev->mii.supports_gmii = 1; 1300 1301 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1302 NETIF_F_RXCSUM; 1303 1304 dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1305 NETIF_F_RXCSUM; 1306 1307 /* Enable checksum offload */ 1308 *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 1309 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 1310 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); 1311 1312 *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | 1313 AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 1314 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); 1315 1316 /* Configure RX control register => start operation */ 1317 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 1318 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 1319 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); 1320 1321 *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | 1322 AX_MONITOR_MODE_RWMP; 1323 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); 1324 1325 /* Configure default medium type => giga */ 1326 *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 1327 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX | 1328 AX_MEDIUM_GIGAMODE; 1329 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1330 2, 2, tmp16); 1331 1332 ax88179_led_setting(dev); 1333 1334 ax179_data->eee_enabled = 0; 1335 ax179_data->eee_active = 0; 1336 1337 ax88179_disable_eee(dev); 1338 1339 ax88179_ethtool_get_eee(dev, &eee_data); 1340 eee_data.advertised = 0; 1341 ax88179_ethtool_set_eee(dev, &eee_data); 1342 1343 /* Restart autoneg */ 1344 mii_nway_restart(&dev->mii); 1345 1346 usbnet_link_change(dev, 0, 0); 1347 1348 return 0; 1349 } 1350 1351 static void ax88179_unbind(struct usbnet *dev, struct usb_interface *intf) 1352 { 1353 u16 tmp16; 1354 1355 /* Configure RX control register => stop operation */ 1356 tmp16 = AX_RX_CTL_STOP; 1357 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16); 1358 1359 tmp16 = 0; 1360 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp16); 1361 1362 /* Power down ethernet PHY */ 1363 tmp16 = 0; 1364 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16); 1365 } 1366 1367 static void 1368 ax88179_rx_checksum(struct sk_buff *skb, u32 *pkt_hdr) 1369 { 1370 skb->ip_summed = CHECKSUM_NONE; 1371 1372 /* checksum error bit is set */ 1373 if ((*pkt_hdr & AX_RXHDR_L3CSUM_ERR) || 1374 (*pkt_hdr & AX_RXHDR_L4CSUM_ERR)) 1375 return; 1376 1377 /* It must be a TCP or UDP packet with a valid checksum */ 1378 if (((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_TCP) || 1379 ((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_UDP)) 1380 skb->ip_summed = CHECKSUM_UNNECESSARY; 1381 } 1382 1383 static int ax88179_rx_fixup(struct usbnet *dev, struct sk_buff *skb) 1384 { 1385 struct sk_buff *ax_skb; 1386 int pkt_cnt; 1387 u32 rx_hdr; 1388 u16 hdr_off; 1389 u32 *pkt_hdr; 1390 1391 /* This check is no longer done by usbnet */ 1392 if (skb->len < dev->net->hard_header_len) 1393 return 0; 1394 1395 skb_trim(skb, skb->len - 4); 1396 rx_hdr = get_unaligned_le32(skb_tail_pointer(skb)); 1397 1398 pkt_cnt = (u16)rx_hdr; 1399 hdr_off = (u16)(rx_hdr >> 16); 1400 pkt_hdr = (u32 *)(skb->data + hdr_off); 1401 1402 while (pkt_cnt--) { 1403 u16 pkt_len; 1404 1405 le32_to_cpus(pkt_hdr); 1406 pkt_len = (*pkt_hdr >> 16) & 0x1fff; 1407 1408 /* Check CRC or runt packet */ 1409 if ((*pkt_hdr & AX_RXHDR_CRC_ERR) || 1410 (*pkt_hdr & AX_RXHDR_DROP_ERR)) { 1411 skb_pull(skb, (pkt_len + 7) & 0xFFF8); 1412 pkt_hdr++; 1413 continue; 1414 } 1415 1416 if (pkt_cnt == 0) { 1417 /* Skip IP alignment psudo header */ 1418 skb_pull(skb, 2); 1419 skb->len = pkt_len; 1420 skb_set_tail_pointer(skb, pkt_len); 1421 skb->truesize = pkt_len + sizeof(struct sk_buff); 1422 ax88179_rx_checksum(skb, pkt_hdr); 1423 return 1; 1424 } 1425 1426 ax_skb = skb_clone(skb, GFP_ATOMIC); 1427 if (ax_skb) { 1428 ax_skb->len = pkt_len; 1429 ax_skb->data = skb->data + 2; 1430 skb_set_tail_pointer(ax_skb, pkt_len); 1431 ax_skb->truesize = pkt_len + sizeof(struct sk_buff); 1432 ax88179_rx_checksum(ax_skb, pkt_hdr); 1433 usbnet_skb_return(dev, ax_skb); 1434 } else { 1435 return 0; 1436 } 1437 1438 skb_pull(skb, (pkt_len + 7) & 0xFFF8); 1439 pkt_hdr++; 1440 } 1441 return 1; 1442 } 1443 1444 static struct sk_buff * 1445 ax88179_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags) 1446 { 1447 u32 tx_hdr1, tx_hdr2; 1448 int frame_size = dev->maxpacket; 1449 int mss = skb_shinfo(skb)->gso_size; 1450 int headroom; 1451 void *ptr; 1452 1453 tx_hdr1 = skb->len; 1454 tx_hdr2 = mss; 1455 if (((skb->len + 8) % frame_size) == 0) 1456 tx_hdr2 |= 0x80008000; /* Enable padding */ 1457 1458 headroom = skb_headroom(skb) - 8; 1459 1460 if ((skb_header_cloned(skb) || headroom < 0) && 1461 pskb_expand_head(skb, headroom < 0 ? 8 : 0, 0, GFP_ATOMIC)) { 1462 dev_kfree_skb_any(skb); 1463 return NULL; 1464 } 1465 1466 ptr = skb_push(skb, 8); 1467 put_unaligned_le32(tx_hdr1, ptr); 1468 put_unaligned_le32(tx_hdr2, ptr + 4); 1469 1470 return skb; 1471 } 1472 1473 static int ax88179_link_reset(struct usbnet *dev) 1474 { 1475 struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data; 1476 u8 tmp[5], link_sts; 1477 u16 mode, tmp16, delay = HZ / 10; 1478 u32 tmp32 = 0x40000000; 1479 unsigned long jtimeout; 1480 1481 jtimeout = jiffies + delay; 1482 while (tmp32 & 0x40000000) { 1483 mode = 0; 1484 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &mode); 1485 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, 1486 &ax179_data->rxctl); 1487 1488 /*link up, check the usb device control TX FIFO full or empty*/ 1489 ax88179_read_cmd(dev, 0x81, 0x8c, 0, 4, &tmp32); 1490 1491 if (time_after(jiffies, jtimeout)) 1492 return 0; 1493 } 1494 1495 mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 1496 AX_MEDIUM_RXFLOW_CTRLEN; 1497 1498 ax88179_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS, 1499 1, 1, &link_sts); 1500 1501 ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1502 GMII_PHY_PHYSR, 2, &tmp16); 1503 1504 if (!(tmp16 & GMII_PHY_PHYSR_LINK)) { 1505 return 0; 1506 } else if (GMII_PHY_PHYSR_GIGA == (tmp16 & GMII_PHY_PHYSR_SMASK)) { 1507 mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ; 1508 if (dev->net->mtu > 1500) 1509 mode |= AX_MEDIUM_JUMBO_EN; 1510 1511 if (link_sts & AX_USB_SS) 1512 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 1513 else if (link_sts & AX_USB_HS) 1514 memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5); 1515 else 1516 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 1517 } else if (GMII_PHY_PHYSR_100 == (tmp16 & GMII_PHY_PHYSR_SMASK)) { 1518 mode |= AX_MEDIUM_PS; 1519 1520 if (link_sts & (AX_USB_SS | AX_USB_HS)) 1521 memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5); 1522 else 1523 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 1524 } else { 1525 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 1526 } 1527 1528 /* RX bulk configuration */ 1529 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 1530 1531 dev->rx_urb_size = (1024 * (tmp[3] + 2)); 1532 1533 if (tmp16 & GMII_PHY_PHYSR_FULL) 1534 mode |= AX_MEDIUM_FULL_DUPLEX; 1535 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1536 2, 2, &mode); 1537 1538 ax179_data->eee_enabled = ax88179_chk_eee(dev); 1539 1540 netif_carrier_on(dev->net); 1541 1542 return 0; 1543 } 1544 1545 static int ax88179_reset(struct usbnet *dev) 1546 { 1547 u8 buf[5]; 1548 u16 *tmp16; 1549 u8 *tmp; 1550 struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data; 1551 struct ethtool_eee eee_data; 1552 1553 tmp16 = (u16 *)buf; 1554 tmp = (u8 *)buf; 1555 1556 /* Power up ethernet PHY */ 1557 *tmp16 = 0; 1558 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 1559 1560 *tmp16 = AX_PHYPWR_RSTCTL_IPRL; 1561 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 1562 msleep(200); 1563 1564 *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 1565 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); 1566 msleep(100); 1567 1568 /* Ethernet PHY Auto Detach*/ 1569 ax88179_auto_detach(dev, 0); 1570 1571 /* Read MAC address from DTB or asix chip */ 1572 ax88179_get_mac_addr(dev); 1573 1574 /* RX bulk configuration */ 1575 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 1576 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 1577 1578 dev->rx_urb_size = 1024 * 20; 1579 1580 *tmp = 0x34; 1581 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); 1582 1583 *tmp = 0x52; 1584 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1585 1, 1, tmp); 1586 1587 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1588 NETIF_F_RXCSUM; 1589 1590 dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1591 NETIF_F_RXCSUM; 1592 1593 /* Enable checksum offload */ 1594 *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 1595 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 1596 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); 1597 1598 *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | 1599 AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 1600 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); 1601 1602 /* Configure RX control register => start operation */ 1603 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 1604 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 1605 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); 1606 1607 *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | 1608 AX_MONITOR_MODE_RWMP; 1609 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); 1610 1611 /* Configure default medium type => giga */ 1612 *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 1613 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX | 1614 AX_MEDIUM_GIGAMODE; 1615 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1616 2, 2, tmp16); 1617 1618 ax88179_led_setting(dev); 1619 1620 ax179_data->eee_enabled = 0; 1621 ax179_data->eee_active = 0; 1622 1623 ax88179_disable_eee(dev); 1624 1625 ax88179_ethtool_get_eee(dev, &eee_data); 1626 eee_data.advertised = 0; 1627 ax88179_ethtool_set_eee(dev, &eee_data); 1628 1629 /* Restart autoneg */ 1630 mii_nway_restart(&dev->mii); 1631 1632 usbnet_link_change(dev, 0, 0); 1633 1634 return 0; 1635 } 1636 1637 static int ax88179_stop(struct usbnet *dev) 1638 { 1639 u16 tmp16; 1640 1641 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1642 2, 2, &tmp16); 1643 tmp16 &= ~AX_MEDIUM_RECEIVE_EN; 1644 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1645 2, 2, &tmp16); 1646 1647 return 0; 1648 } 1649 1650 static const struct driver_info ax88179_info = { 1651 .description = "ASIX AX88179 USB 3.0 Gigabit Ethernet", 1652 .bind = ax88179_bind, 1653 .unbind = ax88179_unbind, 1654 .status = ax88179_status, 1655 .link_reset = ax88179_link_reset, 1656 .reset = ax88179_reset, 1657 .stop = ax88179_stop, 1658 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1659 .rx_fixup = ax88179_rx_fixup, 1660 .tx_fixup = ax88179_tx_fixup, 1661 }; 1662 1663 static const struct driver_info ax88178a_info = { 1664 .description = "ASIX AX88178A USB 2.0 Gigabit Ethernet", 1665 .bind = ax88179_bind, 1666 .unbind = ax88179_unbind, 1667 .status = ax88179_status, 1668 .link_reset = ax88179_link_reset, 1669 .reset = ax88179_reset, 1670 .stop = ax88179_stop, 1671 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1672 .rx_fixup = ax88179_rx_fixup, 1673 .tx_fixup = ax88179_tx_fixup, 1674 }; 1675 1676 static const struct driver_info cypress_GX3_info = { 1677 .description = "Cypress GX3 SuperSpeed to Gigabit Ethernet Controller", 1678 .bind = ax88179_bind, 1679 .unbind = ax88179_unbind, 1680 .status = ax88179_status, 1681 .link_reset = ax88179_link_reset, 1682 .reset = ax88179_reset, 1683 .stop = ax88179_stop, 1684 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1685 .rx_fixup = ax88179_rx_fixup, 1686 .tx_fixup = ax88179_tx_fixup, 1687 }; 1688 1689 static const struct driver_info dlink_dub1312_info = { 1690 .description = "D-Link DUB-1312 USB 3.0 to Gigabit Ethernet Adapter", 1691 .bind = ax88179_bind, 1692 .unbind = ax88179_unbind, 1693 .status = ax88179_status, 1694 .link_reset = ax88179_link_reset, 1695 .reset = ax88179_reset, 1696 .stop = ax88179_stop, 1697 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1698 .rx_fixup = ax88179_rx_fixup, 1699 .tx_fixup = ax88179_tx_fixup, 1700 }; 1701 1702 static const struct driver_info sitecom_info = { 1703 .description = "Sitecom USB 3.0 to Gigabit Adapter", 1704 .bind = ax88179_bind, 1705 .unbind = ax88179_unbind, 1706 .status = ax88179_status, 1707 .link_reset = ax88179_link_reset, 1708 .reset = ax88179_reset, 1709 .stop = ax88179_stop, 1710 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1711 .rx_fixup = ax88179_rx_fixup, 1712 .tx_fixup = ax88179_tx_fixup, 1713 }; 1714 1715 static const struct driver_info samsung_info = { 1716 .description = "Samsung USB Ethernet Adapter", 1717 .bind = ax88179_bind, 1718 .unbind = ax88179_unbind, 1719 .status = ax88179_status, 1720 .link_reset = ax88179_link_reset, 1721 .reset = ax88179_reset, 1722 .stop = ax88179_stop, 1723 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1724 .rx_fixup = ax88179_rx_fixup, 1725 .tx_fixup = ax88179_tx_fixup, 1726 }; 1727 1728 static const struct driver_info lenovo_info = { 1729 .description = "Lenovo OneLinkDock Gigabit LAN", 1730 .bind = ax88179_bind, 1731 .unbind = ax88179_unbind, 1732 .status = ax88179_status, 1733 .link_reset = ax88179_link_reset, 1734 .reset = ax88179_reset, 1735 .stop = ax88179_stop, 1736 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1737 .rx_fixup = ax88179_rx_fixup, 1738 .tx_fixup = ax88179_tx_fixup, 1739 }; 1740 1741 static const struct driver_info belkin_info = { 1742 .description = "Belkin USB Ethernet Adapter", 1743 .bind = ax88179_bind, 1744 .unbind = ax88179_unbind, 1745 .status = ax88179_status, 1746 .link_reset = ax88179_link_reset, 1747 .reset = ax88179_reset, 1748 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1749 .rx_fixup = ax88179_rx_fixup, 1750 .tx_fixup = ax88179_tx_fixup, 1751 }; 1752 1753 static const struct usb_device_id products[] = { 1754 { 1755 /* ASIX AX88179 10/100/1000 */ 1756 USB_DEVICE(0x0b95, 0x1790), 1757 .driver_info = (unsigned long)&ax88179_info, 1758 }, { 1759 /* ASIX AX88178A 10/100/1000 */ 1760 USB_DEVICE(0x0b95, 0x178a), 1761 .driver_info = (unsigned long)&ax88178a_info, 1762 }, { 1763 /* Cypress GX3 SuperSpeed to Gigabit Ethernet Bridge Controller */ 1764 USB_DEVICE(0x04b4, 0x3610), 1765 .driver_info = (unsigned long)&cypress_GX3_info, 1766 }, { 1767 /* D-Link DUB-1312 USB 3.0 to Gigabit Ethernet Adapter */ 1768 USB_DEVICE(0x2001, 0x4a00), 1769 .driver_info = (unsigned long)&dlink_dub1312_info, 1770 }, { 1771 /* Sitecom USB 3.0 to Gigabit Adapter */ 1772 USB_DEVICE(0x0df6, 0x0072), 1773 .driver_info = (unsigned long)&sitecom_info, 1774 }, { 1775 /* Samsung USB Ethernet Adapter */ 1776 USB_DEVICE(0x04e8, 0xa100), 1777 .driver_info = (unsigned long)&samsung_info, 1778 }, { 1779 /* Lenovo OneLinkDock Gigabit LAN */ 1780 USB_DEVICE(0x17ef, 0x304b), 1781 .driver_info = (unsigned long)&lenovo_info, 1782 }, { 1783 /* Belkin B2B128 USB 3.0 Hub + Gigabit Ethernet Adapter */ 1784 USB_DEVICE(0x050d, 0x0128), 1785 .driver_info = (unsigned long)&belkin_info, 1786 }, 1787 { }, 1788 }; 1789 MODULE_DEVICE_TABLE(usb, products); 1790 1791 static struct usb_driver ax88179_178a_driver = { 1792 .name = "ax88179_178a", 1793 .id_table = products, 1794 .probe = usbnet_probe, 1795 .suspend = ax88179_suspend, 1796 .resume = ax88179_resume, 1797 .reset_resume = ax88179_resume, 1798 .disconnect = usbnet_disconnect, 1799 .supports_autosuspend = 1, 1800 .disable_hub_initiated_lpm = 1, 1801 }; 1802 1803 module_usb_driver(ax88179_178a_driver); 1804 1805 MODULE_DESCRIPTION("ASIX AX88179/178A based USB 3.0/2.0 Gigabit Ethernet Devices"); 1806 MODULE_LICENSE("GPL"); 1807