1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ASIX AX8817X based USB 2.0 Ethernet Devices 4 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com> 5 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> 6 * Copyright (C) 2006 James Painter <jamie.painter@iname.com> 7 * Copyright (c) 2002-2003 TiVo Inc. 8 */ 9 10 #include "asix.h" 11 12 #define PHY_MODE_MARVELL 0x0000 13 #define MII_MARVELL_LED_CTRL 0x0018 14 #define MII_MARVELL_STATUS 0x001b 15 #define MII_MARVELL_CTRL 0x0014 16 17 #define MARVELL_LED_MANUAL 0x0019 18 19 #define MARVELL_STATUS_HWCFG 0x0004 20 21 #define MARVELL_CTRL_TXDELAY 0x0002 22 #define MARVELL_CTRL_RXDELAY 0x0080 23 24 #define PHY_MODE_RTL8211CL 0x000C 25 26 #define AX88772A_PHY14H 0x14 27 #define AX88772A_PHY14H_DEFAULT 0x442C 28 29 #define AX88772A_PHY15H 0x15 30 #define AX88772A_PHY15H_DEFAULT 0x03C8 31 32 #define AX88772A_PHY16H 0x16 33 #define AX88772A_PHY16H_DEFAULT 0x4044 34 35 struct ax88172_int_data { 36 __le16 res1; 37 u8 link; 38 __le16 res2; 39 u8 status; 40 __le16 res3; 41 } __packed; 42 43 static void asix_status(struct usbnet *dev, struct urb *urb) 44 { 45 struct ax88172_int_data *event; 46 int link; 47 48 if (urb->actual_length < 8) 49 return; 50 51 event = urb->transfer_buffer; 52 link = event->link & 0x01; 53 if (netif_carrier_ok(dev->net) != link) { 54 usbnet_link_change(dev, link, 1); 55 netdev_dbg(dev->net, "Link Status is: %d\n", link); 56 } 57 } 58 59 static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr) 60 { 61 if (is_valid_ether_addr(addr)) { 62 eth_hw_addr_set(dev->net, addr); 63 } else { 64 netdev_info(dev->net, "invalid hw address, using random\n"); 65 eth_hw_addr_random(dev->net); 66 } 67 } 68 69 /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */ 70 static u32 asix_get_phyid(struct usbnet *dev) 71 { 72 int phy_reg; 73 u32 phy_id; 74 int i; 75 76 /* Poll for the rare case the FW or phy isn't ready yet. */ 77 for (i = 0; i < 100; i++) { 78 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); 79 if (phy_reg < 0) 80 return 0; 81 if (phy_reg != 0 && phy_reg != 0xFFFF) 82 break; 83 mdelay(1); 84 } 85 86 if (phy_reg <= 0 || phy_reg == 0xFFFF) 87 return 0; 88 89 phy_id = (phy_reg & 0xffff) << 16; 90 91 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); 92 if (phy_reg < 0) 93 return 0; 94 95 phy_id |= (phy_reg & 0xffff); 96 97 return phy_id; 98 } 99 100 static u32 asix_get_link(struct net_device *net) 101 { 102 struct usbnet *dev = netdev_priv(net); 103 104 return mii_link_ok(&dev->mii); 105 } 106 107 static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd) 108 { 109 struct usbnet *dev = netdev_priv(net); 110 111 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); 112 } 113 114 /* We need to override some ethtool_ops so we require our 115 own structure so we don't interfere with other usbnet 116 devices that may be connected at the same time. */ 117 static const struct ethtool_ops ax88172_ethtool_ops = { 118 .get_drvinfo = asix_get_drvinfo, 119 .get_link = asix_get_link, 120 .get_msglevel = usbnet_get_msglevel, 121 .set_msglevel = usbnet_set_msglevel, 122 .get_wol = asix_get_wol, 123 .set_wol = asix_set_wol, 124 .get_eeprom_len = asix_get_eeprom_len, 125 .get_eeprom = asix_get_eeprom, 126 .set_eeprom = asix_set_eeprom, 127 .nway_reset = usbnet_nway_reset, 128 .get_link_ksettings = usbnet_get_link_ksettings_mii, 129 .set_link_ksettings = usbnet_set_link_ksettings_mii, 130 }; 131 132 static void ax88172_set_multicast(struct net_device *net) 133 { 134 struct usbnet *dev = netdev_priv(net); 135 struct asix_data *data = (struct asix_data *)&dev->data; 136 u8 rx_ctl = 0x8c; 137 138 if (net->flags & IFF_PROMISC) { 139 rx_ctl |= 0x01; 140 } else if (net->flags & IFF_ALLMULTI || 141 netdev_mc_count(net) > AX_MAX_MCAST) { 142 rx_ctl |= 0x02; 143 } else if (netdev_mc_empty(net)) { 144 /* just broadcast and directed */ 145 } else { 146 /* We use the 20 byte dev->data 147 * for our 8 byte filter buffer 148 * to avoid allocating memory that 149 * is tricky to free later */ 150 struct netdev_hw_addr *ha; 151 u32 crc_bits; 152 153 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); 154 155 /* Build the multicast hash filter. */ 156 netdev_for_each_mc_addr(ha, net) { 157 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; 158 data->multi_filter[crc_bits >> 3] |= 159 1 << (crc_bits & 7); 160 } 161 162 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, 163 AX_MCAST_FILTER_SIZE, data->multi_filter); 164 165 rx_ctl |= 0x10; 166 } 167 168 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); 169 } 170 171 static int ax88172_link_reset(struct usbnet *dev) 172 { 173 u8 mode; 174 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 175 176 mii_check_media(&dev->mii, 1, 1); 177 mii_ethtool_gset(&dev->mii, &ecmd); 178 mode = AX88172_MEDIUM_DEFAULT; 179 180 if (ecmd.duplex != DUPLEX_FULL) 181 mode |= ~AX88172_MEDIUM_FD; 182 183 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 184 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode); 185 186 asix_write_medium_mode(dev, mode, 0); 187 188 return 0; 189 } 190 191 static const struct net_device_ops ax88172_netdev_ops = { 192 .ndo_open = usbnet_open, 193 .ndo_stop = usbnet_stop, 194 .ndo_start_xmit = usbnet_start_xmit, 195 .ndo_tx_timeout = usbnet_tx_timeout, 196 .ndo_change_mtu = usbnet_change_mtu, 197 .ndo_get_stats64 = dev_get_tstats64, 198 .ndo_set_mac_address = eth_mac_addr, 199 .ndo_validate_addr = eth_validate_addr, 200 .ndo_eth_ioctl = asix_ioctl, 201 .ndo_set_rx_mode = ax88172_set_multicast, 202 }; 203 204 static void asix_phy_reset(struct usbnet *dev, unsigned int reset_bits) 205 { 206 unsigned int timeout = 5000; 207 208 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits); 209 210 /* give phy_id a chance to process reset */ 211 udelay(500); 212 213 /* See IEEE 802.3 "22.2.4.1.1 Reset": 500ms max */ 214 while (timeout--) { 215 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR) 216 & BMCR_RESET) 217 udelay(100); 218 else 219 return; 220 } 221 222 netdev_err(dev->net, "BMCR_RESET timeout on phy_id %d\n", 223 dev->mii.phy_id); 224 } 225 226 static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf) 227 { 228 int ret = 0; 229 u8 buf[ETH_ALEN] = {0}; 230 int i; 231 unsigned long gpio_bits = dev->driver_info->data; 232 233 usbnet_get_endpoints(dev,intf); 234 235 /* Toggle the GPIOs in a manufacturer/model specific way */ 236 for (i = 2; i >= 0; i--) { 237 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, 238 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL, 0); 239 if (ret < 0) 240 goto out; 241 msleep(5); 242 } 243 244 ret = asix_write_rx_ctl(dev, 0x80, 0); 245 if (ret < 0) 246 goto out; 247 248 /* Get the MAC address */ 249 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 250 0, 0, ETH_ALEN, buf, 0); 251 if (ret < 0) { 252 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n", 253 ret); 254 goto out; 255 } 256 257 asix_set_netdev_dev_addr(dev, buf); 258 259 /* Initialize MII structure */ 260 dev->mii.dev = dev->net; 261 dev->mii.mdio_read = asix_mdio_read; 262 dev->mii.mdio_write = asix_mdio_write; 263 dev->mii.phy_id_mask = 0x3f; 264 dev->mii.reg_num_mask = 0x1f; 265 266 dev->mii.phy_id = asix_read_phy_addr(dev, true); 267 if (dev->mii.phy_id < 0) 268 return dev->mii.phy_id; 269 270 dev->net->netdev_ops = &ax88172_netdev_ops; 271 dev->net->ethtool_ops = &ax88172_ethtool_ops; 272 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ 273 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ 274 275 asix_phy_reset(dev, BMCR_RESET); 276 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 277 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); 278 mii_nway_restart(&dev->mii); 279 280 return 0; 281 282 out: 283 return ret; 284 } 285 286 static void ax88772_ethtool_get_strings(struct net_device *netdev, u32 sset, 287 u8 *data) 288 { 289 switch (sset) { 290 case ETH_SS_TEST: 291 net_selftest_get_strings(data); 292 break; 293 } 294 } 295 296 static int ax88772_ethtool_get_sset_count(struct net_device *ndev, int sset) 297 { 298 switch (sset) { 299 case ETH_SS_TEST: 300 return net_selftest_get_count(); 301 default: 302 return -EOPNOTSUPP; 303 } 304 } 305 306 static const struct ethtool_ops ax88772_ethtool_ops = { 307 .get_drvinfo = asix_get_drvinfo, 308 .get_link = usbnet_get_link, 309 .get_msglevel = usbnet_get_msglevel, 310 .set_msglevel = usbnet_set_msglevel, 311 .get_wol = asix_get_wol, 312 .set_wol = asix_set_wol, 313 .get_eeprom_len = asix_get_eeprom_len, 314 .get_eeprom = asix_get_eeprom, 315 .set_eeprom = asix_set_eeprom, 316 .nway_reset = phy_ethtool_nway_reset, 317 .get_link_ksettings = phy_ethtool_get_link_ksettings, 318 .set_link_ksettings = phy_ethtool_set_link_ksettings, 319 .self_test = net_selftest, 320 .get_strings = ax88772_ethtool_get_strings, 321 .get_sset_count = ax88772_ethtool_get_sset_count, 322 }; 323 324 static int ax88772_reset(struct usbnet *dev) 325 { 326 struct asix_data *data = (struct asix_data *)&dev->data; 327 struct asix_common_private *priv = dev->driver_priv; 328 int ret; 329 330 /* Rewrite MAC address */ 331 ether_addr_copy(data->mac_addr, dev->net->dev_addr); 332 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, 333 ETH_ALEN, data->mac_addr, 0); 334 if (ret < 0) 335 goto out; 336 337 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 338 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0); 339 if (ret < 0) 340 goto out; 341 342 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, 0); 343 if (ret < 0) 344 goto out; 345 346 phy_start(priv->phydev); 347 348 return 0; 349 350 out: 351 return ret; 352 } 353 354 static int ax88772_hw_reset(struct usbnet *dev, int in_pm) 355 { 356 struct asix_data *data = (struct asix_data *)&dev->data; 357 struct asix_common_private *priv = dev->driver_priv; 358 u16 rx_ctl; 359 int ret; 360 361 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 362 AX_GPIO_GPO2EN, 5, in_pm); 363 if (ret < 0) 364 goto out; 365 366 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, priv->embd_phy, 367 0, 0, NULL, in_pm); 368 if (ret < 0) { 369 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); 370 goto out; 371 } 372 373 if (priv->embd_phy) { 374 ret = asix_sw_reset(dev, AX_SWRESET_IPPD, in_pm); 375 if (ret < 0) 376 goto out; 377 378 usleep_range(10000, 11000); 379 380 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm); 381 if (ret < 0) 382 goto out; 383 384 msleep(60); 385 386 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL, 387 in_pm); 388 if (ret < 0) 389 goto out; 390 } else { 391 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL, 392 in_pm); 393 if (ret < 0) 394 goto out; 395 } 396 397 msleep(150); 398 399 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 400 MII_PHYSID1))){ 401 ret = -EIO; 402 goto out; 403 } 404 405 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 406 if (ret < 0) 407 goto out; 408 409 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm); 410 if (ret < 0) 411 goto out; 412 413 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, 414 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, 415 AX88772_IPG2_DEFAULT, 0, NULL, in_pm); 416 if (ret < 0) { 417 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret); 418 goto out; 419 } 420 421 /* Rewrite MAC address */ 422 ether_addr_copy(data->mac_addr, dev->net->dev_addr); 423 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, 424 ETH_ALEN, data->mac_addr, in_pm); 425 if (ret < 0) 426 goto out; 427 428 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 429 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 430 if (ret < 0) 431 goto out; 432 433 rx_ctl = asix_read_rx_ctl(dev, in_pm); 434 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n", 435 rx_ctl); 436 437 rx_ctl = asix_read_medium_status(dev, in_pm); 438 netdev_dbg(dev->net, 439 "Medium Status is 0x%04x after all initializations\n", 440 rx_ctl); 441 442 return 0; 443 444 out: 445 return ret; 446 } 447 448 static int ax88772a_hw_reset(struct usbnet *dev, int in_pm) 449 { 450 struct asix_data *data = (struct asix_data *)&dev->data; 451 struct asix_common_private *priv = dev->driver_priv; 452 u16 rx_ctl, phy14h, phy15h, phy16h; 453 int ret; 454 455 ret = asix_write_gpio(dev, AX_GPIO_RSE, 5, in_pm); 456 if (ret < 0) 457 goto out; 458 459 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, priv->embd_phy | 460 AX_PHYSEL_SSEN, 0, 0, NULL, in_pm); 461 if (ret < 0) { 462 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); 463 goto out; 464 } 465 usleep_range(10000, 11000); 466 467 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_IPRL, in_pm); 468 if (ret < 0) 469 goto out; 470 471 usleep_range(10000, 11000); 472 473 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm); 474 if (ret < 0) 475 goto out; 476 477 msleep(160); 478 479 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm); 480 if (ret < 0) 481 goto out; 482 483 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm); 484 if (ret < 0) 485 goto out; 486 487 msleep(200); 488 489 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 490 MII_PHYSID1))) { 491 ret = -1; 492 goto out; 493 } 494 495 if (priv->chipcode == AX_AX88772B_CHIPCODE) { 496 ret = asix_write_cmd(dev, AX_QCTCTRL, 0x8000, 0x8001, 497 0, NULL, in_pm); 498 if (ret < 0) { 499 netdev_dbg(dev->net, "Write BQ setting failed: %d\n", 500 ret); 501 goto out; 502 } 503 } else if (priv->chipcode == AX_AX88772A_CHIPCODE) { 504 /* Check if the PHY registers have default settings */ 505 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 506 AX88772A_PHY14H); 507 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 508 AX88772A_PHY15H); 509 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 510 AX88772A_PHY16H); 511 512 netdev_dbg(dev->net, 513 "772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\n", 514 phy14h, phy15h, phy16h); 515 516 /* Restore PHY registers default setting if not */ 517 if (phy14h != AX88772A_PHY14H_DEFAULT) 518 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, 519 AX88772A_PHY14H, 520 AX88772A_PHY14H_DEFAULT); 521 if (phy15h != AX88772A_PHY15H_DEFAULT) 522 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, 523 AX88772A_PHY15H, 524 AX88772A_PHY15H_DEFAULT); 525 if (phy16h != AX88772A_PHY16H_DEFAULT) 526 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, 527 AX88772A_PHY16H, 528 AX88772A_PHY16H_DEFAULT); 529 } 530 531 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, 532 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, 533 AX88772_IPG2_DEFAULT, 0, NULL, in_pm); 534 if (ret < 0) { 535 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret); 536 goto out; 537 } 538 539 /* Rewrite MAC address */ 540 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); 541 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, 542 data->mac_addr, in_pm); 543 if (ret < 0) 544 goto out; 545 546 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 547 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 548 if (ret < 0) 549 goto out; 550 551 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm); 552 if (ret < 0) 553 return ret; 554 555 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 556 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 557 if (ret < 0) 558 goto out; 559 560 rx_ctl = asix_read_rx_ctl(dev, in_pm); 561 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n", 562 rx_ctl); 563 564 rx_ctl = asix_read_medium_status(dev, in_pm); 565 netdev_dbg(dev->net, 566 "Medium Status is 0x%04x after all initializations\n", 567 rx_ctl); 568 569 return 0; 570 571 out: 572 return ret; 573 } 574 575 static const struct net_device_ops ax88772_netdev_ops = { 576 .ndo_open = usbnet_open, 577 .ndo_stop = usbnet_stop, 578 .ndo_start_xmit = usbnet_start_xmit, 579 .ndo_tx_timeout = usbnet_tx_timeout, 580 .ndo_change_mtu = usbnet_change_mtu, 581 .ndo_get_stats64 = dev_get_tstats64, 582 .ndo_set_mac_address = asix_set_mac_address, 583 .ndo_validate_addr = eth_validate_addr, 584 .ndo_eth_ioctl = phy_do_ioctl_running, 585 .ndo_set_rx_mode = asix_set_multicast, 586 }; 587 588 static void ax88772_suspend(struct usbnet *dev) 589 { 590 struct asix_common_private *priv = dev->driver_priv; 591 u16 medium; 592 593 if (netif_running(dev->net)) 594 phy_stop(priv->phydev); 595 596 /* Stop MAC operation */ 597 medium = asix_read_medium_status(dev, 1); 598 medium &= ~AX_MEDIUM_RE; 599 asix_write_medium_mode(dev, medium, 1); 600 601 netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n", 602 asix_read_medium_status(dev, 1)); 603 } 604 605 static int asix_suspend(struct usb_interface *intf, pm_message_t message) 606 { 607 struct usbnet *dev = usb_get_intfdata(intf); 608 struct asix_common_private *priv = dev->driver_priv; 609 610 if (priv && priv->suspend) 611 priv->suspend(dev); 612 613 return usbnet_suspend(intf, message); 614 } 615 616 static void ax88772_resume(struct usbnet *dev) 617 { 618 struct asix_common_private *priv = dev->driver_priv; 619 int i; 620 621 for (i = 0; i < 3; i++) 622 if (!priv->reset(dev, 1)) 623 break; 624 625 if (netif_running(dev->net)) 626 phy_start(priv->phydev); 627 } 628 629 static int asix_resume(struct usb_interface *intf) 630 { 631 struct usbnet *dev = usb_get_intfdata(intf); 632 struct asix_common_private *priv = dev->driver_priv; 633 634 if (priv && priv->resume) 635 priv->resume(dev); 636 637 return usbnet_resume(intf); 638 } 639 640 static int ax88772_init_mdio(struct usbnet *dev) 641 { 642 struct asix_common_private *priv = dev->driver_priv; 643 644 priv->mdio = devm_mdiobus_alloc(&dev->udev->dev); 645 if (!priv->mdio) 646 return -ENOMEM; 647 648 priv->mdio->priv = dev; 649 priv->mdio->read = &asix_mdio_bus_read; 650 priv->mdio->write = &asix_mdio_bus_write; 651 priv->mdio->name = "Asix MDIO Bus"; 652 /* mii bus name is usb-<usb bus number>-<usb device number> */ 653 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "usb-%03d:%03d", 654 dev->udev->bus->busnum, dev->udev->devnum); 655 656 return devm_mdiobus_register(&dev->udev->dev, priv->mdio); 657 } 658 659 static int ax88772_init_phy(struct usbnet *dev) 660 { 661 struct asix_common_private *priv = dev->driver_priv; 662 int ret; 663 664 priv->phydev = mdiobus_get_phy(priv->mdio, priv->phy_addr); 665 if (!priv->phydev) { 666 netdev_err(dev->net, "Could not find PHY\n"); 667 return -ENODEV; 668 } 669 670 ret = phy_connect_direct(dev->net, priv->phydev, &asix_adjust_link, 671 PHY_INTERFACE_MODE_INTERNAL); 672 if (ret) { 673 netdev_err(dev->net, "Could not connect PHY\n"); 674 return ret; 675 } 676 677 phy_suspend(priv->phydev); 678 priv->phydev->mac_managed_pm = 1; 679 680 phy_attached_info(priv->phydev); 681 682 if (priv->embd_phy) 683 return 0; 684 685 /* In case main PHY is not the embedded PHY and MAC is RMII clock 686 * provider, we need to suspend embedded PHY by keeping PLL enabled 687 * (AX_SWRESET_IPPD == 0). 688 */ 689 priv->phydev_int = mdiobus_get_phy(priv->mdio, AX_EMBD_PHY_ADDR); 690 if (!priv->phydev_int) { 691 netdev_err(dev->net, "Could not find internal PHY\n"); 692 return -ENODEV; 693 } 694 695 priv->phydev_int->mac_managed_pm = 1; 696 phy_suspend(priv->phydev_int); 697 698 return 0; 699 } 700 701 static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf) 702 { 703 struct asix_common_private *priv; 704 u8 buf[ETH_ALEN] = {0}; 705 int ret, i; 706 707 priv = devm_kzalloc(&dev->udev->dev, sizeof(*priv), GFP_KERNEL); 708 if (!priv) 709 return -ENOMEM; 710 711 dev->driver_priv = priv; 712 713 usbnet_get_endpoints(dev, intf); 714 715 /* Maybe the boot loader passed the MAC address via device tree */ 716 if (!eth_platform_get_mac_address(&dev->udev->dev, buf)) { 717 netif_dbg(dev, ifup, dev->net, 718 "MAC address read from device tree"); 719 } else { 720 /* Try getting the MAC address from EEPROM */ 721 if (dev->driver_info->data & FLAG_EEPROM_MAC) { 722 for (i = 0; i < (ETH_ALEN >> 1); i++) { 723 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 724 0x04 + i, 0, 2, buf + i * 2, 725 0); 726 if (ret < 0) 727 break; 728 } 729 } else { 730 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 731 0, 0, ETH_ALEN, buf, 0); 732 } 733 734 if (ret < 0) { 735 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", 736 ret); 737 return ret; 738 } 739 } 740 741 asix_set_netdev_dev_addr(dev, buf); 742 743 dev->net->netdev_ops = &ax88772_netdev_ops; 744 dev->net->ethtool_ops = &ax88772_ethtool_ops; 745 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ 746 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ 747 748 ret = asix_read_phy_addr(dev, true); 749 if (ret < 0) 750 return ret; 751 752 priv->phy_addr = ret; 753 priv->embd_phy = ((priv->phy_addr & 0x1f) == AX_EMBD_PHY_ADDR); 754 755 ret = asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 0, 1, 756 &priv->chipcode, 0); 757 if (ret < 0) { 758 netdev_dbg(dev->net, "Failed to read STATMNGSTS_REG: %d\n", ret); 759 return ret; 760 } 761 762 priv->chipcode &= AX_CHIPCODE_MASK; 763 764 priv->resume = ax88772_resume; 765 priv->suspend = ax88772_suspend; 766 if (priv->chipcode == AX_AX88772_CHIPCODE) 767 priv->reset = ax88772_hw_reset; 768 else 769 priv->reset = ax88772a_hw_reset; 770 771 ret = priv->reset(dev, 0); 772 if (ret < 0) { 773 netdev_dbg(dev->net, "Failed to reset AX88772: %d\n", ret); 774 return ret; 775 } 776 777 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ 778 if (dev->driver_info->flags & FLAG_FRAMING_AX) { 779 /* hard_mtu is still the default - the device does not support 780 jumbo eth frames */ 781 dev->rx_urb_size = 2048; 782 } 783 784 priv->presvd_phy_bmcr = 0; 785 priv->presvd_phy_advertise = 0; 786 787 ret = ax88772_init_mdio(dev); 788 if (ret) 789 return ret; 790 791 return ax88772_init_phy(dev); 792 } 793 794 static int ax88772_stop(struct usbnet *dev) 795 { 796 struct asix_common_private *priv = dev->driver_priv; 797 798 /* On unplugged USB, we will get MDIO communication errors and the 799 * PHY will be set in to PHY_HALTED state. 800 */ 801 if (priv->phydev->state != PHY_HALTED) 802 phy_stop(priv->phydev); 803 804 return 0; 805 } 806 807 static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf) 808 { 809 struct asix_common_private *priv = dev->driver_priv; 810 811 phy_disconnect(priv->phydev); 812 asix_rx_fixup_common_free(dev->driver_priv); 813 } 814 815 static void ax88178_unbind(struct usbnet *dev, struct usb_interface *intf) 816 { 817 asix_rx_fixup_common_free(dev->driver_priv); 818 kfree(dev->driver_priv); 819 } 820 821 static const struct ethtool_ops ax88178_ethtool_ops = { 822 .get_drvinfo = asix_get_drvinfo, 823 .get_link = asix_get_link, 824 .get_msglevel = usbnet_get_msglevel, 825 .set_msglevel = usbnet_set_msglevel, 826 .get_wol = asix_get_wol, 827 .set_wol = asix_set_wol, 828 .get_eeprom_len = asix_get_eeprom_len, 829 .get_eeprom = asix_get_eeprom, 830 .set_eeprom = asix_set_eeprom, 831 .nway_reset = usbnet_nway_reset, 832 .get_link_ksettings = usbnet_get_link_ksettings_mii, 833 .set_link_ksettings = usbnet_set_link_ksettings_mii, 834 }; 835 836 static int marvell_phy_init(struct usbnet *dev) 837 { 838 struct asix_data *data = (struct asix_data *)&dev->data; 839 u16 reg; 840 841 netdev_dbg(dev->net, "marvell_phy_init()\n"); 842 843 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS); 844 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg); 845 846 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL, 847 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY); 848 849 if (data->ledmode) { 850 reg = asix_mdio_read(dev->net, dev->mii.phy_id, 851 MII_MARVELL_LED_CTRL); 852 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg); 853 854 reg &= 0xf8ff; 855 reg |= (1 + 0x0100); 856 asix_mdio_write(dev->net, dev->mii.phy_id, 857 MII_MARVELL_LED_CTRL, reg); 858 859 reg = asix_mdio_read(dev->net, dev->mii.phy_id, 860 MII_MARVELL_LED_CTRL); 861 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg); 862 } 863 864 return 0; 865 } 866 867 static int rtl8211cl_phy_init(struct usbnet *dev) 868 { 869 struct asix_data *data = (struct asix_data *)&dev->data; 870 871 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n"); 872 873 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005); 874 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0); 875 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01, 876 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080); 877 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); 878 879 if (data->ledmode == 12) { 880 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002); 881 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb); 882 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); 883 } 884 885 return 0; 886 } 887 888 static int marvell_led_status(struct usbnet *dev, u16 speed) 889 { 890 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL); 891 892 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg); 893 894 /* Clear out the center LED bits - 0x03F0 */ 895 reg &= 0xfc0f; 896 897 switch (speed) { 898 case SPEED_1000: 899 reg |= 0x03e0; 900 break; 901 case SPEED_100: 902 reg |= 0x03b0; 903 break; 904 default: 905 reg |= 0x02f0; 906 } 907 908 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg); 909 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg); 910 911 return 0; 912 } 913 914 static int ax88178_reset(struct usbnet *dev) 915 { 916 struct asix_data *data = (struct asix_data *)&dev->data; 917 int ret; 918 __le16 eeprom; 919 u8 status; 920 int gpio0 = 0; 921 u32 phyid; 922 923 ret = asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status, 0); 924 if (ret < 0) { 925 netdev_dbg(dev->net, "Failed to read GPIOS: %d\n", ret); 926 return ret; 927 } 928 929 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status); 930 931 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL, 0); 932 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom, 0); 933 if (ret < 0) { 934 netdev_dbg(dev->net, "Failed to read EEPROM: %d\n", ret); 935 return ret; 936 } 937 938 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL, 0); 939 940 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom); 941 942 if (eeprom == cpu_to_le16(0xffff)) { 943 data->phymode = PHY_MODE_MARVELL; 944 data->ledmode = 0; 945 gpio0 = 1; 946 } else { 947 data->phymode = le16_to_cpu(eeprom) & 0x7F; 948 data->ledmode = le16_to_cpu(eeprom) >> 8; 949 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1; 950 } 951 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode); 952 953 /* Power up external GigaPHY through AX88178 GPIO pin */ 954 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | 955 AX_GPIO_GPO1EN, 40, 0); 956 if ((le16_to_cpu(eeprom) >> 8) != 1) { 957 asix_write_gpio(dev, 0x003c, 30, 0); 958 asix_write_gpio(dev, 0x001c, 300, 0); 959 asix_write_gpio(dev, 0x003c, 30, 0); 960 } else { 961 netdev_dbg(dev->net, "gpio phymode == 1 path\n"); 962 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30, 0); 963 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30, 0); 964 } 965 966 /* Read PHYID register *AFTER* powering up PHY */ 967 phyid = asix_get_phyid(dev); 968 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid); 969 970 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */ 971 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL, 0); 972 973 asix_sw_reset(dev, 0, 0); 974 msleep(150); 975 976 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0); 977 msleep(150); 978 979 asix_write_rx_ctl(dev, 0, 0); 980 981 if (data->phymode == PHY_MODE_MARVELL) { 982 marvell_phy_init(dev); 983 msleep(60); 984 } else if (data->phymode == PHY_MODE_RTL8211CL) 985 rtl8211cl_phy_init(dev); 986 987 asix_phy_reset(dev, BMCR_RESET | BMCR_ANENABLE); 988 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 989 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); 990 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000, 991 ADVERTISE_1000FULL); 992 993 asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT, 0); 994 mii_nway_restart(&dev->mii); 995 996 /* Rewrite MAC address */ 997 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); 998 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, 999 data->mac_addr, 0); 1000 if (ret < 0) 1001 return ret; 1002 1003 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0); 1004 if (ret < 0) 1005 return ret; 1006 1007 return 0; 1008 } 1009 1010 static int ax88178_link_reset(struct usbnet *dev) 1011 { 1012 u16 mode; 1013 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 1014 struct asix_data *data = (struct asix_data *)&dev->data; 1015 u32 speed; 1016 1017 netdev_dbg(dev->net, "ax88178_link_reset()\n"); 1018 1019 mii_check_media(&dev->mii, 1, 1); 1020 mii_ethtool_gset(&dev->mii, &ecmd); 1021 mode = AX88178_MEDIUM_DEFAULT; 1022 speed = ethtool_cmd_speed(&ecmd); 1023 1024 if (speed == SPEED_1000) 1025 mode |= AX_MEDIUM_GM; 1026 else if (speed == SPEED_100) 1027 mode |= AX_MEDIUM_PS; 1028 else 1029 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM); 1030 1031 mode |= AX_MEDIUM_ENCK; 1032 1033 if (ecmd.duplex == DUPLEX_FULL) 1034 mode |= AX_MEDIUM_FD; 1035 else 1036 mode &= ~AX_MEDIUM_FD; 1037 1038 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 1039 speed, ecmd.duplex, mode); 1040 1041 asix_write_medium_mode(dev, mode, 0); 1042 1043 if (data->phymode == PHY_MODE_MARVELL && data->ledmode) 1044 marvell_led_status(dev, speed); 1045 1046 return 0; 1047 } 1048 1049 static void ax88178_set_mfb(struct usbnet *dev) 1050 { 1051 u16 mfb = AX_RX_CTL_MFB_16384; 1052 u16 rxctl; 1053 u16 medium; 1054 int old_rx_urb_size = dev->rx_urb_size; 1055 1056 if (dev->hard_mtu < 2048) { 1057 dev->rx_urb_size = 2048; 1058 mfb = AX_RX_CTL_MFB_2048; 1059 } else if (dev->hard_mtu < 4096) { 1060 dev->rx_urb_size = 4096; 1061 mfb = AX_RX_CTL_MFB_4096; 1062 } else if (dev->hard_mtu < 8192) { 1063 dev->rx_urb_size = 8192; 1064 mfb = AX_RX_CTL_MFB_8192; 1065 } else if (dev->hard_mtu < 16384) { 1066 dev->rx_urb_size = 16384; 1067 mfb = AX_RX_CTL_MFB_16384; 1068 } 1069 1070 rxctl = asix_read_rx_ctl(dev, 0); 1071 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb, 0); 1072 1073 medium = asix_read_medium_status(dev, 0); 1074 if (dev->net->mtu > 1500) 1075 medium |= AX_MEDIUM_JFE; 1076 else 1077 medium &= ~AX_MEDIUM_JFE; 1078 asix_write_medium_mode(dev, medium, 0); 1079 1080 if (dev->rx_urb_size > old_rx_urb_size) 1081 usbnet_unlink_rx_urbs(dev); 1082 } 1083 1084 static int ax88178_change_mtu(struct net_device *net, int new_mtu) 1085 { 1086 struct usbnet *dev = netdev_priv(net); 1087 int ll_mtu = new_mtu + net->hard_header_len + 4; 1088 1089 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu); 1090 1091 if ((ll_mtu % dev->maxpacket) == 0) 1092 return -EDOM; 1093 1094 net->mtu = new_mtu; 1095 dev->hard_mtu = net->mtu + net->hard_header_len; 1096 ax88178_set_mfb(dev); 1097 1098 /* max qlen depend on hard_mtu and rx_urb_size */ 1099 usbnet_update_max_qlen(dev); 1100 1101 return 0; 1102 } 1103 1104 static const struct net_device_ops ax88178_netdev_ops = { 1105 .ndo_open = usbnet_open, 1106 .ndo_stop = usbnet_stop, 1107 .ndo_start_xmit = usbnet_start_xmit, 1108 .ndo_tx_timeout = usbnet_tx_timeout, 1109 .ndo_get_stats64 = dev_get_tstats64, 1110 .ndo_set_mac_address = asix_set_mac_address, 1111 .ndo_validate_addr = eth_validate_addr, 1112 .ndo_set_rx_mode = asix_set_multicast, 1113 .ndo_eth_ioctl = asix_ioctl, 1114 .ndo_change_mtu = ax88178_change_mtu, 1115 }; 1116 1117 static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf) 1118 { 1119 int ret; 1120 u8 buf[ETH_ALEN] = {0}; 1121 1122 usbnet_get_endpoints(dev,intf); 1123 1124 /* Get the MAC address */ 1125 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf, 0); 1126 if (ret < 0) { 1127 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret); 1128 return ret; 1129 } 1130 1131 asix_set_netdev_dev_addr(dev, buf); 1132 1133 /* Initialize MII structure */ 1134 dev->mii.dev = dev->net; 1135 dev->mii.mdio_read = asix_mdio_read; 1136 dev->mii.mdio_write = asix_mdio_write; 1137 dev->mii.phy_id_mask = 0x1f; 1138 dev->mii.reg_num_mask = 0xff; 1139 dev->mii.supports_gmii = 1; 1140 1141 dev->mii.phy_id = asix_read_phy_addr(dev, true); 1142 if (dev->mii.phy_id < 0) 1143 return dev->mii.phy_id; 1144 1145 dev->net->netdev_ops = &ax88178_netdev_ops; 1146 dev->net->ethtool_ops = &ax88178_ethtool_ops; 1147 dev->net->max_mtu = 16384 - (dev->net->hard_header_len + 4); 1148 1149 /* Blink LEDS so users know driver saw dongle */ 1150 asix_sw_reset(dev, 0, 0); 1151 msleep(150); 1152 1153 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0); 1154 msleep(150); 1155 1156 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ 1157 if (dev->driver_info->flags & FLAG_FRAMING_AX) { 1158 /* hard_mtu is still the default - the device does not support 1159 jumbo eth frames */ 1160 dev->rx_urb_size = 2048; 1161 } 1162 1163 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL); 1164 if (!dev->driver_priv) 1165 return -ENOMEM; 1166 1167 return 0; 1168 } 1169 1170 static const struct driver_info ax8817x_info = { 1171 .description = "ASIX AX8817x USB 2.0 Ethernet", 1172 .bind = ax88172_bind, 1173 .status = asix_status, 1174 .link_reset = ax88172_link_reset, 1175 .reset = ax88172_link_reset, 1176 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1177 .data = 0x00130103, 1178 }; 1179 1180 static const struct driver_info dlink_dub_e100_info = { 1181 .description = "DLink DUB-E100 USB Ethernet", 1182 .bind = ax88172_bind, 1183 .status = asix_status, 1184 .link_reset = ax88172_link_reset, 1185 .reset = ax88172_link_reset, 1186 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1187 .data = 0x009f9d9f, 1188 }; 1189 1190 static const struct driver_info netgear_fa120_info = { 1191 .description = "Netgear FA-120 USB Ethernet", 1192 .bind = ax88172_bind, 1193 .status = asix_status, 1194 .link_reset = ax88172_link_reset, 1195 .reset = ax88172_link_reset, 1196 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1197 .data = 0x00130103, 1198 }; 1199 1200 static const struct driver_info hawking_uf200_info = { 1201 .description = "Hawking UF200 USB Ethernet", 1202 .bind = ax88172_bind, 1203 .status = asix_status, 1204 .link_reset = ax88172_link_reset, 1205 .reset = ax88172_link_reset, 1206 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1207 .data = 0x001f1d1f, 1208 }; 1209 1210 static const struct driver_info ax88772_info = { 1211 .description = "ASIX AX88772 USB 2.0 Ethernet", 1212 .bind = ax88772_bind, 1213 .unbind = ax88772_unbind, 1214 .status = asix_status, 1215 .reset = ax88772_reset, 1216 .stop = ax88772_stop, 1217 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET, 1218 .rx_fixup = asix_rx_fixup_common, 1219 .tx_fixup = asix_tx_fixup, 1220 }; 1221 1222 static const struct driver_info ax88772b_info = { 1223 .description = "ASIX AX88772B USB 2.0 Ethernet", 1224 .bind = ax88772_bind, 1225 .unbind = ax88772_unbind, 1226 .status = asix_status, 1227 .reset = ax88772_reset, 1228 .stop = ax88772_stop, 1229 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | 1230 FLAG_MULTI_PACKET, 1231 .rx_fixup = asix_rx_fixup_common, 1232 .tx_fixup = asix_tx_fixup, 1233 .data = FLAG_EEPROM_MAC, 1234 }; 1235 1236 static const struct driver_info ax88178_info = { 1237 .description = "ASIX AX88178 USB 2.0 Ethernet", 1238 .bind = ax88178_bind, 1239 .unbind = ax88178_unbind, 1240 .status = asix_status, 1241 .link_reset = ax88178_link_reset, 1242 .reset = ax88178_reset, 1243 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | 1244 FLAG_MULTI_PACKET, 1245 .rx_fixup = asix_rx_fixup_common, 1246 .tx_fixup = asix_tx_fixup, 1247 }; 1248 1249 /* 1250 * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in 1251 * no-name packaging. 1252 * USB device strings are: 1253 * 1: Manufacturer: USBLINK 1254 * 2: Product: HG20F9 USB2.0 1255 * 3: Serial: 000003 1256 * Appears to be compatible with Asix 88772B. 1257 */ 1258 static const struct driver_info hg20f9_info = { 1259 .description = "HG20F9 USB 2.0 Ethernet", 1260 .bind = ax88772_bind, 1261 .unbind = ax88772_unbind, 1262 .status = asix_status, 1263 .reset = ax88772_reset, 1264 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | 1265 FLAG_MULTI_PACKET, 1266 .rx_fixup = asix_rx_fixup_common, 1267 .tx_fixup = asix_tx_fixup, 1268 .data = FLAG_EEPROM_MAC, 1269 }; 1270 1271 static const struct usb_device_id products [] = { 1272 { 1273 // Linksys USB200M 1274 USB_DEVICE (0x077b, 0x2226), 1275 .driver_info = (unsigned long) &ax8817x_info, 1276 }, { 1277 // Netgear FA120 1278 USB_DEVICE (0x0846, 0x1040), 1279 .driver_info = (unsigned long) &netgear_fa120_info, 1280 }, { 1281 // DLink DUB-E100 1282 USB_DEVICE (0x2001, 0x1a00), 1283 .driver_info = (unsigned long) &dlink_dub_e100_info, 1284 }, { 1285 // Intellinet, ST Lab USB Ethernet 1286 USB_DEVICE (0x0b95, 0x1720), 1287 .driver_info = (unsigned long) &ax8817x_info, 1288 }, { 1289 // Hawking UF200, TrendNet TU2-ET100 1290 USB_DEVICE (0x07b8, 0x420a), 1291 .driver_info = (unsigned long) &hawking_uf200_info, 1292 }, { 1293 // Billionton Systems, USB2AR 1294 USB_DEVICE (0x08dd, 0x90ff), 1295 .driver_info = (unsigned long) &ax8817x_info, 1296 }, { 1297 // Billionton Systems, GUSB2AM-1G-B 1298 USB_DEVICE(0x08dd, 0x0114), 1299 .driver_info = (unsigned long) &ax88178_info, 1300 }, { 1301 // ATEN UC210T 1302 USB_DEVICE (0x0557, 0x2009), 1303 .driver_info = (unsigned long) &ax8817x_info, 1304 }, { 1305 // Buffalo LUA-U2-KTX 1306 USB_DEVICE (0x0411, 0x003d), 1307 .driver_info = (unsigned long) &ax8817x_info, 1308 }, { 1309 // Buffalo LUA-U2-GT 10/100/1000 1310 USB_DEVICE (0x0411, 0x006e), 1311 .driver_info = (unsigned long) &ax88178_info, 1312 }, { 1313 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter" 1314 USB_DEVICE (0x6189, 0x182d), 1315 .driver_info = (unsigned long) &ax8817x_info, 1316 }, { 1317 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter" 1318 USB_DEVICE (0x0df6, 0x0056), 1319 .driver_info = (unsigned long) &ax88178_info, 1320 }, { 1321 // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter" 1322 USB_DEVICE (0x0df6, 0x061c), 1323 .driver_info = (unsigned long) &ax88178_info, 1324 }, { 1325 // corega FEther USB2-TX 1326 USB_DEVICE (0x07aa, 0x0017), 1327 .driver_info = (unsigned long) &ax8817x_info, 1328 }, { 1329 // Surecom EP-1427X-2 1330 USB_DEVICE (0x1189, 0x0893), 1331 .driver_info = (unsigned long) &ax8817x_info, 1332 }, { 1333 // goodway corp usb gwusb2e 1334 USB_DEVICE (0x1631, 0x6200), 1335 .driver_info = (unsigned long) &ax8817x_info, 1336 }, { 1337 // JVC MP-PRX1 Port Replicator 1338 USB_DEVICE (0x04f1, 0x3008), 1339 .driver_info = (unsigned long) &ax8817x_info, 1340 }, { 1341 // Lenovo U2L100P 10/100 1342 USB_DEVICE (0x17ef, 0x7203), 1343 .driver_info = (unsigned long)&ax88772b_info, 1344 }, { 1345 // ASIX AX88772B 10/100 1346 USB_DEVICE (0x0b95, 0x772b), 1347 .driver_info = (unsigned long) &ax88772b_info, 1348 }, { 1349 // ASIX AX88772 10/100 1350 USB_DEVICE (0x0b95, 0x7720), 1351 .driver_info = (unsigned long) &ax88772_info, 1352 }, { 1353 // ASIX AX88178 10/100/1000 1354 USB_DEVICE (0x0b95, 0x1780), 1355 .driver_info = (unsigned long) &ax88178_info, 1356 }, { 1357 // Logitec LAN-GTJ/U2A 1358 USB_DEVICE (0x0789, 0x0160), 1359 .driver_info = (unsigned long) &ax88178_info, 1360 }, { 1361 // Linksys USB200M Rev 2 1362 USB_DEVICE (0x13b1, 0x0018), 1363 .driver_info = (unsigned long) &ax88772_info, 1364 }, { 1365 // 0Q0 cable ethernet 1366 USB_DEVICE (0x1557, 0x7720), 1367 .driver_info = (unsigned long) &ax88772_info, 1368 }, { 1369 // DLink DUB-E100 H/W Ver B1 1370 USB_DEVICE (0x07d1, 0x3c05), 1371 .driver_info = (unsigned long) &ax88772_info, 1372 }, { 1373 // DLink DUB-E100 H/W Ver B1 Alternate 1374 USB_DEVICE (0x2001, 0x3c05), 1375 .driver_info = (unsigned long) &ax88772_info, 1376 }, { 1377 // DLink DUB-E100 H/W Ver C1 1378 USB_DEVICE (0x2001, 0x1a02), 1379 .driver_info = (unsigned long) &ax88772_info, 1380 }, { 1381 // Linksys USB1000 1382 USB_DEVICE (0x1737, 0x0039), 1383 .driver_info = (unsigned long) &ax88178_info, 1384 }, { 1385 // IO-DATA ETG-US2 1386 USB_DEVICE (0x04bb, 0x0930), 1387 .driver_info = (unsigned long) &ax88178_info, 1388 }, { 1389 // Belkin F5D5055 1390 USB_DEVICE(0x050d, 0x5055), 1391 .driver_info = (unsigned long) &ax88178_info, 1392 }, { 1393 // Apple USB Ethernet Adapter 1394 USB_DEVICE(0x05ac, 0x1402), 1395 .driver_info = (unsigned long) &ax88772_info, 1396 }, { 1397 // Cables-to-Go USB Ethernet Adapter 1398 USB_DEVICE(0x0b95, 0x772a), 1399 .driver_info = (unsigned long) &ax88772_info, 1400 }, { 1401 // ABOCOM for pci 1402 USB_DEVICE(0x14ea, 0xab11), 1403 .driver_info = (unsigned long) &ax88178_info, 1404 }, { 1405 // ASIX 88772a 1406 USB_DEVICE(0x0db0, 0xa877), 1407 .driver_info = (unsigned long) &ax88772_info, 1408 }, { 1409 // Asus USB Ethernet Adapter 1410 USB_DEVICE (0x0b95, 0x7e2b), 1411 .driver_info = (unsigned long)&ax88772b_info, 1412 }, { 1413 /* ASIX 88172a demo board */ 1414 USB_DEVICE(0x0b95, 0x172a), 1415 .driver_info = (unsigned long) &ax88172a_info, 1416 }, { 1417 /* 1418 * USBLINK HG20F9 "USB 2.0 LAN" 1419 * Appears to have gazumped Linksys's manufacturer ID but 1420 * doesn't (yet) conflict with any known Linksys product. 1421 */ 1422 USB_DEVICE(0x066b, 0x20f9), 1423 .driver_info = (unsigned long) &hg20f9_info, 1424 }, 1425 { }, // END 1426 }; 1427 MODULE_DEVICE_TABLE(usb, products); 1428 1429 static struct usb_driver asix_driver = { 1430 .name = DRIVER_NAME, 1431 .id_table = products, 1432 .probe = usbnet_probe, 1433 .suspend = asix_suspend, 1434 .resume = asix_resume, 1435 .reset_resume = asix_resume, 1436 .disconnect = usbnet_disconnect, 1437 .supports_autosuspend = 1, 1438 .disable_hub_initiated_lpm = 1, 1439 }; 1440 1441 module_usb_driver(asix_driver); 1442 1443 MODULE_AUTHOR("David Hollis"); 1444 MODULE_VERSION(DRIVER_VERSION); 1445 MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices"); 1446 MODULE_LICENSE("GPL"); 1447 1448