1 /* 2 * ASIX AX8817X based USB 2.0 Ethernet Devices 3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com> 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> 5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com> 6 * Copyright (c) 2002-2003 TiVo Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "asix.h" 23 24 #define PHY_MODE_MARVELL 0x0000 25 #define MII_MARVELL_LED_CTRL 0x0018 26 #define MII_MARVELL_STATUS 0x001b 27 #define MII_MARVELL_CTRL 0x0014 28 29 #define MARVELL_LED_MANUAL 0x0019 30 31 #define MARVELL_STATUS_HWCFG 0x0004 32 33 #define MARVELL_CTRL_TXDELAY 0x0002 34 #define MARVELL_CTRL_RXDELAY 0x0080 35 36 #define PHY_MODE_RTL8211CL 0x000C 37 38 #define AX88772A_PHY14H 0x14 39 #define AX88772A_PHY14H_DEFAULT 0x442C 40 41 #define AX88772A_PHY15H 0x15 42 #define AX88772A_PHY15H_DEFAULT 0x03C8 43 44 #define AX88772A_PHY16H 0x16 45 #define AX88772A_PHY16H_DEFAULT 0x4044 46 47 struct ax88172_int_data { 48 __le16 res1; 49 u8 link; 50 __le16 res2; 51 u8 status; 52 __le16 res3; 53 } __packed; 54 55 static void asix_status(struct usbnet *dev, struct urb *urb) 56 { 57 struct ax88172_int_data *event; 58 int link; 59 60 if (urb->actual_length < 8) 61 return; 62 63 event = urb->transfer_buffer; 64 link = event->link & 0x01; 65 if (netif_carrier_ok(dev->net) != link) { 66 usbnet_link_change(dev, link, 1); 67 netdev_dbg(dev->net, "Link Status is: %d\n", link); 68 } 69 } 70 71 static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr) 72 { 73 if (is_valid_ether_addr(addr)) { 74 memcpy(dev->net->dev_addr, addr, ETH_ALEN); 75 } else { 76 netdev_info(dev->net, "invalid hw address, using random\n"); 77 eth_hw_addr_random(dev->net); 78 } 79 } 80 81 /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */ 82 static u32 asix_get_phyid(struct usbnet *dev) 83 { 84 int phy_reg; 85 u32 phy_id; 86 int i; 87 88 /* Poll for the rare case the FW or phy isn't ready yet. */ 89 for (i = 0; i < 100; i++) { 90 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); 91 if (phy_reg < 0) 92 return 0; 93 if (phy_reg != 0 && phy_reg != 0xFFFF) 94 break; 95 mdelay(1); 96 } 97 98 if (phy_reg <= 0 || phy_reg == 0xFFFF) 99 return 0; 100 101 phy_id = (phy_reg & 0xffff) << 16; 102 103 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); 104 if (phy_reg < 0) 105 return 0; 106 107 phy_id |= (phy_reg & 0xffff); 108 109 return phy_id; 110 } 111 112 static u32 asix_get_link(struct net_device *net) 113 { 114 struct usbnet *dev = netdev_priv(net); 115 116 return mii_link_ok(&dev->mii); 117 } 118 119 static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd) 120 { 121 struct usbnet *dev = netdev_priv(net); 122 123 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); 124 } 125 126 /* We need to override some ethtool_ops so we require our 127 own structure so we don't interfere with other usbnet 128 devices that may be connected at the same time. */ 129 static const struct ethtool_ops ax88172_ethtool_ops = { 130 .get_drvinfo = asix_get_drvinfo, 131 .get_link = asix_get_link, 132 .get_msglevel = usbnet_get_msglevel, 133 .set_msglevel = usbnet_set_msglevel, 134 .get_wol = asix_get_wol, 135 .set_wol = asix_set_wol, 136 .get_eeprom_len = asix_get_eeprom_len, 137 .get_eeprom = asix_get_eeprom, 138 .set_eeprom = asix_set_eeprom, 139 .nway_reset = usbnet_nway_reset, 140 .get_link_ksettings = usbnet_get_link_ksettings, 141 .set_link_ksettings = usbnet_set_link_ksettings, 142 }; 143 144 static void ax88172_set_multicast(struct net_device *net) 145 { 146 struct usbnet *dev = netdev_priv(net); 147 struct asix_data *data = (struct asix_data *)&dev->data; 148 u8 rx_ctl = 0x8c; 149 150 if (net->flags & IFF_PROMISC) { 151 rx_ctl |= 0x01; 152 } else if (net->flags & IFF_ALLMULTI || 153 netdev_mc_count(net) > AX_MAX_MCAST) { 154 rx_ctl |= 0x02; 155 } else if (netdev_mc_empty(net)) { 156 /* just broadcast and directed */ 157 } else { 158 /* We use the 20 byte dev->data 159 * for our 8 byte filter buffer 160 * to avoid allocating memory that 161 * is tricky to free later */ 162 struct netdev_hw_addr *ha; 163 u32 crc_bits; 164 165 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); 166 167 /* Build the multicast hash filter. */ 168 netdev_for_each_mc_addr(ha, net) { 169 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; 170 data->multi_filter[crc_bits >> 3] |= 171 1 << (crc_bits & 7); 172 } 173 174 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, 175 AX_MCAST_FILTER_SIZE, data->multi_filter); 176 177 rx_ctl |= 0x10; 178 } 179 180 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); 181 } 182 183 static int ax88172_link_reset(struct usbnet *dev) 184 { 185 u8 mode; 186 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 187 188 mii_check_media(&dev->mii, 1, 1); 189 mii_ethtool_gset(&dev->mii, &ecmd); 190 mode = AX88172_MEDIUM_DEFAULT; 191 192 if (ecmd.duplex != DUPLEX_FULL) 193 mode |= ~AX88172_MEDIUM_FD; 194 195 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 196 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode); 197 198 asix_write_medium_mode(dev, mode, 0); 199 200 return 0; 201 } 202 203 static const struct net_device_ops ax88172_netdev_ops = { 204 .ndo_open = usbnet_open, 205 .ndo_stop = usbnet_stop, 206 .ndo_start_xmit = usbnet_start_xmit, 207 .ndo_tx_timeout = usbnet_tx_timeout, 208 .ndo_change_mtu = usbnet_change_mtu, 209 .ndo_get_stats64 = usbnet_get_stats64, 210 .ndo_set_mac_address = eth_mac_addr, 211 .ndo_validate_addr = eth_validate_addr, 212 .ndo_do_ioctl = asix_ioctl, 213 .ndo_set_rx_mode = ax88172_set_multicast, 214 }; 215 216 static void asix_phy_reset(struct usbnet *dev, unsigned int reset_bits) 217 { 218 unsigned int timeout = 5000; 219 220 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits); 221 222 /* give phy_id a chance to process reset */ 223 udelay(500); 224 225 /* See IEEE 802.3 "22.2.4.1.1 Reset": 500ms max */ 226 while (timeout--) { 227 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR) 228 & BMCR_RESET) 229 udelay(100); 230 else 231 return; 232 } 233 234 netdev_err(dev->net, "BMCR_RESET timeout on phy_id %d\n", 235 dev->mii.phy_id); 236 } 237 238 static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf) 239 { 240 int ret = 0; 241 u8 buf[ETH_ALEN]; 242 int i; 243 unsigned long gpio_bits = dev->driver_info->data; 244 245 usbnet_get_endpoints(dev,intf); 246 247 /* Toggle the GPIOs in a manufacturer/model specific way */ 248 for (i = 2; i >= 0; i--) { 249 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, 250 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL, 0); 251 if (ret < 0) 252 goto out; 253 msleep(5); 254 } 255 256 ret = asix_write_rx_ctl(dev, 0x80, 0); 257 if (ret < 0) 258 goto out; 259 260 /* Get the MAC address */ 261 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 262 0, 0, ETH_ALEN, buf, 0); 263 if (ret < 0) { 264 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n", 265 ret); 266 goto out; 267 } 268 269 asix_set_netdev_dev_addr(dev, buf); 270 271 /* Initialize MII structure */ 272 dev->mii.dev = dev->net; 273 dev->mii.mdio_read = asix_mdio_read; 274 dev->mii.mdio_write = asix_mdio_write; 275 dev->mii.phy_id_mask = 0x3f; 276 dev->mii.reg_num_mask = 0x1f; 277 dev->mii.phy_id = asix_get_phy_addr(dev); 278 279 dev->net->netdev_ops = &ax88172_netdev_ops; 280 dev->net->ethtool_ops = &ax88172_ethtool_ops; 281 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ 282 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ 283 284 asix_phy_reset(dev, BMCR_RESET); 285 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 286 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); 287 mii_nway_restart(&dev->mii); 288 289 return 0; 290 291 out: 292 return ret; 293 } 294 295 static const struct ethtool_ops ax88772_ethtool_ops = { 296 .get_drvinfo = asix_get_drvinfo, 297 .get_link = asix_get_link, 298 .get_msglevel = usbnet_get_msglevel, 299 .set_msglevel = usbnet_set_msglevel, 300 .get_wol = asix_get_wol, 301 .set_wol = asix_set_wol, 302 .get_eeprom_len = asix_get_eeprom_len, 303 .get_eeprom = asix_get_eeprom, 304 .set_eeprom = asix_set_eeprom, 305 .nway_reset = usbnet_nway_reset, 306 .get_link_ksettings = usbnet_get_link_ksettings, 307 .set_link_ksettings = usbnet_set_link_ksettings, 308 }; 309 310 static int ax88772_link_reset(struct usbnet *dev) 311 { 312 u16 mode; 313 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 314 315 mii_check_media(&dev->mii, 1, 1); 316 mii_ethtool_gset(&dev->mii, &ecmd); 317 mode = AX88772_MEDIUM_DEFAULT; 318 319 if (ethtool_cmd_speed(&ecmd) != SPEED_100) 320 mode &= ~AX_MEDIUM_PS; 321 322 if (ecmd.duplex != DUPLEX_FULL) 323 mode &= ~AX_MEDIUM_FD; 324 325 netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 326 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode); 327 328 asix_write_medium_mode(dev, mode, 0); 329 330 return 0; 331 } 332 333 static int ax88772_reset(struct usbnet *dev) 334 { 335 struct asix_data *data = (struct asix_data *)&dev->data; 336 int ret; 337 338 /* Rewrite MAC address */ 339 ether_addr_copy(data->mac_addr, dev->net->dev_addr); 340 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, 341 ETH_ALEN, data->mac_addr, 0); 342 if (ret < 0) 343 goto out; 344 345 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 346 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0); 347 if (ret < 0) 348 goto out; 349 350 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, 0); 351 if (ret < 0) 352 goto out; 353 354 return 0; 355 356 out: 357 return ret; 358 } 359 360 static int ax88772_hw_reset(struct usbnet *dev, int in_pm) 361 { 362 struct asix_data *data = (struct asix_data *)&dev->data; 363 int ret, embd_phy; 364 u16 rx_ctl; 365 366 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 367 AX_GPIO_GPO2EN, 5, in_pm); 368 if (ret < 0) 369 goto out; 370 371 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0); 372 373 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 374 0, 0, NULL, in_pm); 375 if (ret < 0) { 376 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); 377 goto out; 378 } 379 380 if (embd_phy) { 381 ret = asix_sw_reset(dev, AX_SWRESET_IPPD, in_pm); 382 if (ret < 0) 383 goto out; 384 385 usleep_range(10000, 11000); 386 387 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm); 388 if (ret < 0) 389 goto out; 390 391 msleep(60); 392 393 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL, 394 in_pm); 395 if (ret < 0) 396 goto out; 397 } else { 398 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL, 399 in_pm); 400 if (ret < 0) 401 goto out; 402 } 403 404 msleep(150); 405 406 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 407 MII_PHYSID1))){ 408 ret = -EIO; 409 goto out; 410 } 411 412 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 413 if (ret < 0) 414 goto out; 415 416 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm); 417 if (ret < 0) 418 goto out; 419 420 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, 421 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, 422 AX88772_IPG2_DEFAULT, 0, NULL, in_pm); 423 if (ret < 0) { 424 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret); 425 goto out; 426 } 427 428 /* Rewrite MAC address */ 429 ether_addr_copy(data->mac_addr, dev->net->dev_addr); 430 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, 431 ETH_ALEN, data->mac_addr, in_pm); 432 if (ret < 0) 433 goto out; 434 435 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 436 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 437 if (ret < 0) 438 goto out; 439 440 rx_ctl = asix_read_rx_ctl(dev, in_pm); 441 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n", 442 rx_ctl); 443 444 rx_ctl = asix_read_medium_status(dev, in_pm); 445 netdev_dbg(dev->net, 446 "Medium Status is 0x%04x after all initializations\n", 447 rx_ctl); 448 449 return 0; 450 451 out: 452 return ret; 453 } 454 455 static int ax88772a_hw_reset(struct usbnet *dev, int in_pm) 456 { 457 struct asix_data *data = (struct asix_data *)&dev->data; 458 int ret, embd_phy; 459 u16 rx_ctl, phy14h, phy15h, phy16h; 460 u8 chipcode = 0; 461 462 ret = asix_write_gpio(dev, AX_GPIO_RSE, 5, in_pm); 463 if (ret < 0) 464 goto out; 465 466 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0); 467 468 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy | 469 AX_PHYSEL_SSEN, 0, 0, NULL, in_pm); 470 if (ret < 0) { 471 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); 472 goto out; 473 } 474 usleep_range(10000, 11000); 475 476 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_IPRL, in_pm); 477 if (ret < 0) 478 goto out; 479 480 usleep_range(10000, 11000); 481 482 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm); 483 if (ret < 0) 484 goto out; 485 486 msleep(160); 487 488 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm); 489 if (ret < 0) 490 goto out; 491 492 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm); 493 if (ret < 0) 494 goto out; 495 496 msleep(200); 497 498 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 499 MII_PHYSID1))) { 500 ret = -1; 501 goto out; 502 } 503 504 ret = asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 505 0, 1, &chipcode, in_pm); 506 if (ret < 0) 507 goto out; 508 509 if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772B_CHIPCODE) { 510 ret = asix_write_cmd(dev, AX_QCTCTRL, 0x8000, 0x8001, 511 0, NULL, in_pm); 512 if (ret < 0) { 513 netdev_dbg(dev->net, "Write BQ setting failed: %d\n", 514 ret); 515 goto out; 516 } 517 } else if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772A_CHIPCODE) { 518 /* Check if the PHY registers have default settings */ 519 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 520 AX88772A_PHY14H); 521 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 522 AX88772A_PHY15H); 523 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 524 AX88772A_PHY16H); 525 526 netdev_dbg(dev->net, 527 "772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\n", 528 phy14h, phy15h, phy16h); 529 530 /* Restore PHY registers default setting if not */ 531 if (phy14h != AX88772A_PHY14H_DEFAULT) 532 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, 533 AX88772A_PHY14H, 534 AX88772A_PHY14H_DEFAULT); 535 if (phy15h != AX88772A_PHY15H_DEFAULT) 536 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, 537 AX88772A_PHY15H, 538 AX88772A_PHY15H_DEFAULT); 539 if (phy16h != AX88772A_PHY16H_DEFAULT) 540 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, 541 AX88772A_PHY16H, 542 AX88772A_PHY16H_DEFAULT); 543 } 544 545 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, 546 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, 547 AX88772_IPG2_DEFAULT, 0, NULL, in_pm); 548 if (ret < 0) { 549 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret); 550 goto out; 551 } 552 553 /* Rewrite MAC address */ 554 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); 555 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, 556 data->mac_addr, in_pm); 557 if (ret < 0) 558 goto out; 559 560 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 561 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 562 if (ret < 0) 563 goto out; 564 565 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm); 566 if (ret < 0) 567 return ret; 568 569 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 570 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 571 if (ret < 0) 572 goto out; 573 574 rx_ctl = asix_read_rx_ctl(dev, in_pm); 575 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n", 576 rx_ctl); 577 578 rx_ctl = asix_read_medium_status(dev, in_pm); 579 netdev_dbg(dev->net, 580 "Medium Status is 0x%04x after all initializations\n", 581 rx_ctl); 582 583 return 0; 584 585 out: 586 return ret; 587 } 588 589 static const struct net_device_ops ax88772_netdev_ops = { 590 .ndo_open = usbnet_open, 591 .ndo_stop = usbnet_stop, 592 .ndo_start_xmit = usbnet_start_xmit, 593 .ndo_tx_timeout = usbnet_tx_timeout, 594 .ndo_change_mtu = usbnet_change_mtu, 595 .ndo_get_stats64 = usbnet_get_stats64, 596 .ndo_set_mac_address = asix_set_mac_address, 597 .ndo_validate_addr = eth_validate_addr, 598 .ndo_do_ioctl = asix_ioctl, 599 .ndo_set_rx_mode = asix_set_multicast, 600 }; 601 602 static void ax88772_suspend(struct usbnet *dev) 603 { 604 struct asix_common_private *priv = dev->driver_priv; 605 u16 medium; 606 607 /* Stop MAC operation */ 608 medium = asix_read_medium_status(dev, 1); 609 medium &= ~AX_MEDIUM_RE; 610 asix_write_medium_mode(dev, medium, 1); 611 612 netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n", 613 asix_read_medium_status(dev, 1)); 614 615 /* Preserve BMCR for restoring */ 616 priv->presvd_phy_bmcr = 617 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_BMCR); 618 619 /* Preserve ANAR for restoring */ 620 priv->presvd_phy_advertise = 621 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE); 622 } 623 624 static int asix_suspend(struct usb_interface *intf, pm_message_t message) 625 { 626 struct usbnet *dev = usb_get_intfdata(intf); 627 struct asix_common_private *priv = dev->driver_priv; 628 629 if (priv && priv->suspend) 630 priv->suspend(dev); 631 632 return usbnet_suspend(intf, message); 633 } 634 635 static void ax88772_restore_phy(struct usbnet *dev) 636 { 637 struct asix_common_private *priv = dev->driver_priv; 638 639 if (priv->presvd_phy_advertise) { 640 /* Restore Advertisement control reg */ 641 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE, 642 priv->presvd_phy_advertise); 643 644 /* Restore BMCR */ 645 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_BMCR, 646 priv->presvd_phy_bmcr); 647 648 mii_nway_restart(&dev->mii); 649 priv->presvd_phy_advertise = 0; 650 priv->presvd_phy_bmcr = 0; 651 } 652 } 653 654 static void ax88772_resume(struct usbnet *dev) 655 { 656 int i; 657 658 for (i = 0; i < 3; i++) 659 if (!ax88772_hw_reset(dev, 1)) 660 break; 661 ax88772_restore_phy(dev); 662 } 663 664 static void ax88772a_resume(struct usbnet *dev) 665 { 666 int i; 667 668 for (i = 0; i < 3; i++) { 669 if (!ax88772a_hw_reset(dev, 1)) 670 break; 671 } 672 673 ax88772_restore_phy(dev); 674 } 675 676 static int asix_resume(struct usb_interface *intf) 677 { 678 struct usbnet *dev = usb_get_intfdata(intf); 679 struct asix_common_private *priv = dev->driver_priv; 680 681 if (priv && priv->resume) 682 priv->resume(dev); 683 684 return usbnet_resume(intf); 685 } 686 687 static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf) 688 { 689 int ret, i; 690 u8 buf[ETH_ALEN], chipcode = 0; 691 u32 phyid; 692 struct asix_common_private *priv; 693 694 usbnet_get_endpoints(dev, intf); 695 696 /* Maybe the boot loader passed the MAC address via device tree */ 697 if (!eth_platform_get_mac_address(&dev->udev->dev, buf)) { 698 netif_dbg(dev, ifup, dev->net, 699 "MAC address read from device tree"); 700 } else { 701 /* Try getting the MAC address from EEPROM */ 702 if (dev->driver_info->data & FLAG_EEPROM_MAC) { 703 for (i = 0; i < (ETH_ALEN >> 1); i++) { 704 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 705 0x04 + i, 0, 2, buf + i * 2, 706 0); 707 if (ret < 0) 708 break; 709 } 710 } else { 711 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 712 0, 0, ETH_ALEN, buf, 0); 713 } 714 715 if (ret < 0) { 716 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", 717 ret); 718 return ret; 719 } 720 } 721 722 asix_set_netdev_dev_addr(dev, buf); 723 724 /* Initialize MII structure */ 725 dev->mii.dev = dev->net; 726 dev->mii.mdio_read = asix_mdio_read; 727 dev->mii.mdio_write = asix_mdio_write; 728 dev->mii.phy_id_mask = 0x1f; 729 dev->mii.reg_num_mask = 0x1f; 730 dev->mii.phy_id = asix_get_phy_addr(dev); 731 732 dev->net->netdev_ops = &ax88772_netdev_ops; 733 dev->net->ethtool_ops = &ax88772_ethtool_ops; 734 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ 735 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ 736 737 asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 0, 1, &chipcode, 0); 738 chipcode &= AX_CHIPCODE_MASK; 739 740 (chipcode == AX_AX88772_CHIPCODE) ? ax88772_hw_reset(dev, 0) : 741 ax88772a_hw_reset(dev, 0); 742 743 /* Read PHYID register *AFTER* the PHY was reset properly */ 744 phyid = asix_get_phyid(dev); 745 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid); 746 747 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ 748 if (dev->driver_info->flags & FLAG_FRAMING_AX) { 749 /* hard_mtu is still the default - the device does not support 750 jumbo eth frames */ 751 dev->rx_urb_size = 2048; 752 } 753 754 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL); 755 if (!dev->driver_priv) 756 return -ENOMEM; 757 758 priv = dev->driver_priv; 759 760 priv->presvd_phy_bmcr = 0; 761 priv->presvd_phy_advertise = 0; 762 if (chipcode == AX_AX88772_CHIPCODE) { 763 priv->resume = ax88772_resume; 764 priv->suspend = ax88772_suspend; 765 } else { 766 priv->resume = ax88772a_resume; 767 priv->suspend = ax88772_suspend; 768 } 769 770 return 0; 771 } 772 773 static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf) 774 { 775 asix_rx_fixup_common_free(dev->driver_priv); 776 kfree(dev->driver_priv); 777 } 778 779 static const struct ethtool_ops ax88178_ethtool_ops = { 780 .get_drvinfo = asix_get_drvinfo, 781 .get_link = asix_get_link, 782 .get_msglevel = usbnet_get_msglevel, 783 .set_msglevel = usbnet_set_msglevel, 784 .get_wol = asix_get_wol, 785 .set_wol = asix_set_wol, 786 .get_eeprom_len = asix_get_eeprom_len, 787 .get_eeprom = asix_get_eeprom, 788 .set_eeprom = asix_set_eeprom, 789 .nway_reset = usbnet_nway_reset, 790 .get_link_ksettings = usbnet_get_link_ksettings, 791 .set_link_ksettings = usbnet_set_link_ksettings, 792 }; 793 794 static int marvell_phy_init(struct usbnet *dev) 795 { 796 struct asix_data *data = (struct asix_data *)&dev->data; 797 u16 reg; 798 799 netdev_dbg(dev->net, "marvell_phy_init()\n"); 800 801 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS); 802 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg); 803 804 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL, 805 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY); 806 807 if (data->ledmode) { 808 reg = asix_mdio_read(dev->net, dev->mii.phy_id, 809 MII_MARVELL_LED_CTRL); 810 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg); 811 812 reg &= 0xf8ff; 813 reg |= (1 + 0x0100); 814 asix_mdio_write(dev->net, dev->mii.phy_id, 815 MII_MARVELL_LED_CTRL, reg); 816 817 reg = asix_mdio_read(dev->net, dev->mii.phy_id, 818 MII_MARVELL_LED_CTRL); 819 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg); 820 reg &= 0xfc0f; 821 } 822 823 return 0; 824 } 825 826 static int rtl8211cl_phy_init(struct usbnet *dev) 827 { 828 struct asix_data *data = (struct asix_data *)&dev->data; 829 830 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n"); 831 832 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005); 833 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0); 834 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01, 835 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080); 836 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); 837 838 if (data->ledmode == 12) { 839 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002); 840 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb); 841 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); 842 } 843 844 return 0; 845 } 846 847 static int marvell_led_status(struct usbnet *dev, u16 speed) 848 { 849 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL); 850 851 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg); 852 853 /* Clear out the center LED bits - 0x03F0 */ 854 reg &= 0xfc0f; 855 856 switch (speed) { 857 case SPEED_1000: 858 reg |= 0x03e0; 859 break; 860 case SPEED_100: 861 reg |= 0x03b0; 862 break; 863 default: 864 reg |= 0x02f0; 865 } 866 867 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg); 868 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg); 869 870 return 0; 871 } 872 873 static int ax88178_reset(struct usbnet *dev) 874 { 875 struct asix_data *data = (struct asix_data *)&dev->data; 876 int ret; 877 __le16 eeprom; 878 u8 status; 879 int gpio0 = 0; 880 u32 phyid; 881 882 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status, 0); 883 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status); 884 885 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL, 0); 886 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom, 0); 887 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL, 0); 888 889 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom); 890 891 if (eeprom == cpu_to_le16(0xffff)) { 892 data->phymode = PHY_MODE_MARVELL; 893 data->ledmode = 0; 894 gpio0 = 1; 895 } else { 896 data->phymode = le16_to_cpu(eeprom) & 0x7F; 897 data->ledmode = le16_to_cpu(eeprom) >> 8; 898 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1; 899 } 900 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode); 901 902 /* Power up external GigaPHY through AX88178 GPIO pin */ 903 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | 904 AX_GPIO_GPO1EN, 40, 0); 905 if ((le16_to_cpu(eeprom) >> 8) != 1) { 906 asix_write_gpio(dev, 0x003c, 30, 0); 907 asix_write_gpio(dev, 0x001c, 300, 0); 908 asix_write_gpio(dev, 0x003c, 30, 0); 909 } else { 910 netdev_dbg(dev->net, "gpio phymode == 1 path\n"); 911 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30, 0); 912 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30, 0); 913 } 914 915 /* Read PHYID register *AFTER* powering up PHY */ 916 phyid = asix_get_phyid(dev); 917 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid); 918 919 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */ 920 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL, 0); 921 922 asix_sw_reset(dev, 0, 0); 923 msleep(150); 924 925 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0); 926 msleep(150); 927 928 asix_write_rx_ctl(dev, 0, 0); 929 930 if (data->phymode == PHY_MODE_MARVELL) { 931 marvell_phy_init(dev); 932 msleep(60); 933 } else if (data->phymode == PHY_MODE_RTL8211CL) 934 rtl8211cl_phy_init(dev); 935 936 asix_phy_reset(dev, BMCR_RESET | BMCR_ANENABLE); 937 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 938 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); 939 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000, 940 ADVERTISE_1000FULL); 941 942 asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT, 0); 943 mii_nway_restart(&dev->mii); 944 945 /* Rewrite MAC address */ 946 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); 947 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, 948 data->mac_addr, 0); 949 if (ret < 0) 950 return ret; 951 952 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0); 953 if (ret < 0) 954 return ret; 955 956 return 0; 957 } 958 959 static int ax88178_link_reset(struct usbnet *dev) 960 { 961 u16 mode; 962 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 963 struct asix_data *data = (struct asix_data *)&dev->data; 964 u32 speed; 965 966 netdev_dbg(dev->net, "ax88178_link_reset()\n"); 967 968 mii_check_media(&dev->mii, 1, 1); 969 mii_ethtool_gset(&dev->mii, &ecmd); 970 mode = AX88178_MEDIUM_DEFAULT; 971 speed = ethtool_cmd_speed(&ecmd); 972 973 if (speed == SPEED_1000) 974 mode |= AX_MEDIUM_GM; 975 else if (speed == SPEED_100) 976 mode |= AX_MEDIUM_PS; 977 else 978 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM); 979 980 mode |= AX_MEDIUM_ENCK; 981 982 if (ecmd.duplex == DUPLEX_FULL) 983 mode |= AX_MEDIUM_FD; 984 else 985 mode &= ~AX_MEDIUM_FD; 986 987 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 988 speed, ecmd.duplex, mode); 989 990 asix_write_medium_mode(dev, mode, 0); 991 992 if (data->phymode == PHY_MODE_MARVELL && data->ledmode) 993 marvell_led_status(dev, speed); 994 995 return 0; 996 } 997 998 static void ax88178_set_mfb(struct usbnet *dev) 999 { 1000 u16 mfb = AX_RX_CTL_MFB_16384; 1001 u16 rxctl; 1002 u16 medium; 1003 int old_rx_urb_size = dev->rx_urb_size; 1004 1005 if (dev->hard_mtu < 2048) { 1006 dev->rx_urb_size = 2048; 1007 mfb = AX_RX_CTL_MFB_2048; 1008 } else if (dev->hard_mtu < 4096) { 1009 dev->rx_urb_size = 4096; 1010 mfb = AX_RX_CTL_MFB_4096; 1011 } else if (dev->hard_mtu < 8192) { 1012 dev->rx_urb_size = 8192; 1013 mfb = AX_RX_CTL_MFB_8192; 1014 } else if (dev->hard_mtu < 16384) { 1015 dev->rx_urb_size = 16384; 1016 mfb = AX_RX_CTL_MFB_16384; 1017 } 1018 1019 rxctl = asix_read_rx_ctl(dev, 0); 1020 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb, 0); 1021 1022 medium = asix_read_medium_status(dev, 0); 1023 if (dev->net->mtu > 1500) 1024 medium |= AX_MEDIUM_JFE; 1025 else 1026 medium &= ~AX_MEDIUM_JFE; 1027 asix_write_medium_mode(dev, medium, 0); 1028 1029 if (dev->rx_urb_size > old_rx_urb_size) 1030 usbnet_unlink_rx_urbs(dev); 1031 } 1032 1033 static int ax88178_change_mtu(struct net_device *net, int new_mtu) 1034 { 1035 struct usbnet *dev = netdev_priv(net); 1036 int ll_mtu = new_mtu + net->hard_header_len + 4; 1037 1038 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu); 1039 1040 if ((ll_mtu % dev->maxpacket) == 0) 1041 return -EDOM; 1042 1043 net->mtu = new_mtu; 1044 dev->hard_mtu = net->mtu + net->hard_header_len; 1045 ax88178_set_mfb(dev); 1046 1047 /* max qlen depend on hard_mtu and rx_urb_size */ 1048 usbnet_update_max_qlen(dev); 1049 1050 return 0; 1051 } 1052 1053 static const struct net_device_ops ax88178_netdev_ops = { 1054 .ndo_open = usbnet_open, 1055 .ndo_stop = usbnet_stop, 1056 .ndo_start_xmit = usbnet_start_xmit, 1057 .ndo_tx_timeout = usbnet_tx_timeout, 1058 .ndo_get_stats64 = usbnet_get_stats64, 1059 .ndo_set_mac_address = asix_set_mac_address, 1060 .ndo_validate_addr = eth_validate_addr, 1061 .ndo_set_rx_mode = asix_set_multicast, 1062 .ndo_do_ioctl = asix_ioctl, 1063 .ndo_change_mtu = ax88178_change_mtu, 1064 }; 1065 1066 static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf) 1067 { 1068 int ret; 1069 u8 buf[ETH_ALEN]; 1070 1071 usbnet_get_endpoints(dev,intf); 1072 1073 /* Get the MAC address */ 1074 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf, 0); 1075 if (ret < 0) { 1076 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret); 1077 return ret; 1078 } 1079 1080 asix_set_netdev_dev_addr(dev, buf); 1081 1082 /* Initialize MII structure */ 1083 dev->mii.dev = dev->net; 1084 dev->mii.mdio_read = asix_mdio_read; 1085 dev->mii.mdio_write = asix_mdio_write; 1086 dev->mii.phy_id_mask = 0x1f; 1087 dev->mii.reg_num_mask = 0xff; 1088 dev->mii.supports_gmii = 1; 1089 dev->mii.phy_id = asix_get_phy_addr(dev); 1090 1091 dev->net->netdev_ops = &ax88178_netdev_ops; 1092 dev->net->ethtool_ops = &ax88178_ethtool_ops; 1093 dev->net->max_mtu = 16384 - (dev->net->hard_header_len + 4); 1094 1095 /* Blink LEDS so users know driver saw dongle */ 1096 asix_sw_reset(dev, 0, 0); 1097 msleep(150); 1098 1099 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0); 1100 msleep(150); 1101 1102 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ 1103 if (dev->driver_info->flags & FLAG_FRAMING_AX) { 1104 /* hard_mtu is still the default - the device does not support 1105 jumbo eth frames */ 1106 dev->rx_urb_size = 2048; 1107 } 1108 1109 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL); 1110 if (!dev->driver_priv) 1111 return -ENOMEM; 1112 1113 return 0; 1114 } 1115 1116 static const struct driver_info ax8817x_info = { 1117 .description = "ASIX AX8817x USB 2.0 Ethernet", 1118 .bind = ax88172_bind, 1119 .status = asix_status, 1120 .link_reset = ax88172_link_reset, 1121 .reset = ax88172_link_reset, 1122 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1123 .data = 0x00130103, 1124 }; 1125 1126 static const struct driver_info dlink_dub_e100_info = { 1127 .description = "DLink DUB-E100 USB Ethernet", 1128 .bind = ax88172_bind, 1129 .status = asix_status, 1130 .link_reset = ax88172_link_reset, 1131 .reset = ax88172_link_reset, 1132 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1133 .data = 0x009f9d9f, 1134 }; 1135 1136 static const struct driver_info netgear_fa120_info = { 1137 .description = "Netgear FA-120 USB Ethernet", 1138 .bind = ax88172_bind, 1139 .status = asix_status, 1140 .link_reset = ax88172_link_reset, 1141 .reset = ax88172_link_reset, 1142 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1143 .data = 0x00130103, 1144 }; 1145 1146 static const struct driver_info hawking_uf200_info = { 1147 .description = "Hawking UF200 USB Ethernet", 1148 .bind = ax88172_bind, 1149 .status = asix_status, 1150 .link_reset = ax88172_link_reset, 1151 .reset = ax88172_link_reset, 1152 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1153 .data = 0x001f1d1f, 1154 }; 1155 1156 static const struct driver_info ax88772_info = { 1157 .description = "ASIX AX88772 USB 2.0 Ethernet", 1158 .bind = ax88772_bind, 1159 .unbind = ax88772_unbind, 1160 .status = asix_status, 1161 .link_reset = ax88772_link_reset, 1162 .reset = ax88772_reset, 1163 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET, 1164 .rx_fixup = asix_rx_fixup_common, 1165 .tx_fixup = asix_tx_fixup, 1166 }; 1167 1168 static const struct driver_info ax88772b_info = { 1169 .description = "ASIX AX88772B USB 2.0 Ethernet", 1170 .bind = ax88772_bind, 1171 .unbind = ax88772_unbind, 1172 .status = asix_status, 1173 .link_reset = ax88772_link_reset, 1174 .reset = ax88772_reset, 1175 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | 1176 FLAG_MULTI_PACKET, 1177 .rx_fixup = asix_rx_fixup_common, 1178 .tx_fixup = asix_tx_fixup, 1179 .data = FLAG_EEPROM_MAC, 1180 }; 1181 1182 static const struct driver_info ax88178_info = { 1183 .description = "ASIX AX88178 USB 2.0 Ethernet", 1184 .bind = ax88178_bind, 1185 .unbind = ax88772_unbind, 1186 .status = asix_status, 1187 .link_reset = ax88178_link_reset, 1188 .reset = ax88178_reset, 1189 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | 1190 FLAG_MULTI_PACKET, 1191 .rx_fixup = asix_rx_fixup_common, 1192 .tx_fixup = asix_tx_fixup, 1193 }; 1194 1195 /* 1196 * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in 1197 * no-name packaging. 1198 * USB device strings are: 1199 * 1: Manufacturer: USBLINK 1200 * 2: Product: HG20F9 USB2.0 1201 * 3: Serial: 000003 1202 * Appears to be compatible with Asix 88772B. 1203 */ 1204 static const struct driver_info hg20f9_info = { 1205 .description = "HG20F9 USB 2.0 Ethernet", 1206 .bind = ax88772_bind, 1207 .unbind = ax88772_unbind, 1208 .status = asix_status, 1209 .link_reset = ax88772_link_reset, 1210 .reset = ax88772_reset, 1211 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | 1212 FLAG_MULTI_PACKET, 1213 .rx_fixup = asix_rx_fixup_common, 1214 .tx_fixup = asix_tx_fixup, 1215 .data = FLAG_EEPROM_MAC, 1216 }; 1217 1218 static const struct usb_device_id products [] = { 1219 { 1220 // Linksys USB200M 1221 USB_DEVICE (0x077b, 0x2226), 1222 .driver_info = (unsigned long) &ax8817x_info, 1223 }, { 1224 // Netgear FA120 1225 USB_DEVICE (0x0846, 0x1040), 1226 .driver_info = (unsigned long) &netgear_fa120_info, 1227 }, { 1228 // DLink DUB-E100 1229 USB_DEVICE (0x2001, 0x1a00), 1230 .driver_info = (unsigned long) &dlink_dub_e100_info, 1231 }, { 1232 // Intellinet, ST Lab USB Ethernet 1233 USB_DEVICE (0x0b95, 0x1720), 1234 .driver_info = (unsigned long) &ax8817x_info, 1235 }, { 1236 // Hawking UF200, TrendNet TU2-ET100 1237 USB_DEVICE (0x07b8, 0x420a), 1238 .driver_info = (unsigned long) &hawking_uf200_info, 1239 }, { 1240 // Billionton Systems, USB2AR 1241 USB_DEVICE (0x08dd, 0x90ff), 1242 .driver_info = (unsigned long) &ax8817x_info, 1243 }, { 1244 // Billionton Systems, GUSB2AM-1G-B 1245 USB_DEVICE(0x08dd, 0x0114), 1246 .driver_info = (unsigned long) &ax88178_info, 1247 }, { 1248 // ATEN UC210T 1249 USB_DEVICE (0x0557, 0x2009), 1250 .driver_info = (unsigned long) &ax8817x_info, 1251 }, { 1252 // Buffalo LUA-U2-KTX 1253 USB_DEVICE (0x0411, 0x003d), 1254 .driver_info = (unsigned long) &ax8817x_info, 1255 }, { 1256 // Buffalo LUA-U2-GT 10/100/1000 1257 USB_DEVICE (0x0411, 0x006e), 1258 .driver_info = (unsigned long) &ax88178_info, 1259 }, { 1260 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter" 1261 USB_DEVICE (0x6189, 0x182d), 1262 .driver_info = (unsigned long) &ax8817x_info, 1263 }, { 1264 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter" 1265 USB_DEVICE (0x0df6, 0x0056), 1266 .driver_info = (unsigned long) &ax88178_info, 1267 }, { 1268 // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter" 1269 USB_DEVICE (0x0df6, 0x061c), 1270 .driver_info = (unsigned long) &ax88178_info, 1271 }, { 1272 // corega FEther USB2-TX 1273 USB_DEVICE (0x07aa, 0x0017), 1274 .driver_info = (unsigned long) &ax8817x_info, 1275 }, { 1276 // Surecom EP-1427X-2 1277 USB_DEVICE (0x1189, 0x0893), 1278 .driver_info = (unsigned long) &ax8817x_info, 1279 }, { 1280 // goodway corp usb gwusb2e 1281 USB_DEVICE (0x1631, 0x6200), 1282 .driver_info = (unsigned long) &ax8817x_info, 1283 }, { 1284 // JVC MP-PRX1 Port Replicator 1285 USB_DEVICE (0x04f1, 0x3008), 1286 .driver_info = (unsigned long) &ax8817x_info, 1287 }, { 1288 // Lenovo U2L100P 10/100 1289 USB_DEVICE (0x17ef, 0x7203), 1290 .driver_info = (unsigned long)&ax88772b_info, 1291 }, { 1292 // ASIX AX88772B 10/100 1293 USB_DEVICE (0x0b95, 0x772b), 1294 .driver_info = (unsigned long) &ax88772b_info, 1295 }, { 1296 // ASIX AX88772 10/100 1297 USB_DEVICE (0x0b95, 0x7720), 1298 .driver_info = (unsigned long) &ax88772_info, 1299 }, { 1300 // ASIX AX88178 10/100/1000 1301 USB_DEVICE (0x0b95, 0x1780), 1302 .driver_info = (unsigned long) &ax88178_info, 1303 }, { 1304 // Logitec LAN-GTJ/U2A 1305 USB_DEVICE (0x0789, 0x0160), 1306 .driver_info = (unsigned long) &ax88178_info, 1307 }, { 1308 // Linksys USB200M Rev 2 1309 USB_DEVICE (0x13b1, 0x0018), 1310 .driver_info = (unsigned long) &ax88772_info, 1311 }, { 1312 // 0Q0 cable ethernet 1313 USB_DEVICE (0x1557, 0x7720), 1314 .driver_info = (unsigned long) &ax88772_info, 1315 }, { 1316 // DLink DUB-E100 H/W Ver B1 1317 USB_DEVICE (0x07d1, 0x3c05), 1318 .driver_info = (unsigned long) &ax88772_info, 1319 }, { 1320 // DLink DUB-E100 H/W Ver B1 Alternate 1321 USB_DEVICE (0x2001, 0x3c05), 1322 .driver_info = (unsigned long) &ax88772_info, 1323 }, { 1324 // DLink DUB-E100 H/W Ver C1 1325 USB_DEVICE (0x2001, 0x1a02), 1326 .driver_info = (unsigned long) &ax88772_info, 1327 }, { 1328 // Linksys USB1000 1329 USB_DEVICE (0x1737, 0x0039), 1330 .driver_info = (unsigned long) &ax88178_info, 1331 }, { 1332 // IO-DATA ETG-US2 1333 USB_DEVICE (0x04bb, 0x0930), 1334 .driver_info = (unsigned long) &ax88178_info, 1335 }, { 1336 // Belkin F5D5055 1337 USB_DEVICE(0x050d, 0x5055), 1338 .driver_info = (unsigned long) &ax88178_info, 1339 }, { 1340 // Apple USB Ethernet Adapter 1341 USB_DEVICE(0x05ac, 0x1402), 1342 .driver_info = (unsigned long) &ax88772_info, 1343 }, { 1344 // Cables-to-Go USB Ethernet Adapter 1345 USB_DEVICE(0x0b95, 0x772a), 1346 .driver_info = (unsigned long) &ax88772_info, 1347 }, { 1348 // ABOCOM for pci 1349 USB_DEVICE(0x14ea, 0xab11), 1350 .driver_info = (unsigned long) &ax88178_info, 1351 }, { 1352 // ASIX 88772a 1353 USB_DEVICE(0x0db0, 0xa877), 1354 .driver_info = (unsigned long) &ax88772_info, 1355 }, { 1356 // Asus USB Ethernet Adapter 1357 USB_DEVICE (0x0b95, 0x7e2b), 1358 .driver_info = (unsigned long)&ax88772b_info, 1359 }, { 1360 /* ASIX 88172a demo board */ 1361 USB_DEVICE(0x0b95, 0x172a), 1362 .driver_info = (unsigned long) &ax88172a_info, 1363 }, { 1364 /* 1365 * USBLINK HG20F9 "USB 2.0 LAN" 1366 * Appears to have gazumped Linksys's manufacturer ID but 1367 * doesn't (yet) conflict with any known Linksys product. 1368 */ 1369 USB_DEVICE(0x066b, 0x20f9), 1370 .driver_info = (unsigned long) &hg20f9_info, 1371 }, 1372 { }, // END 1373 }; 1374 MODULE_DEVICE_TABLE(usb, products); 1375 1376 static struct usb_driver asix_driver = { 1377 .name = DRIVER_NAME, 1378 .id_table = products, 1379 .probe = usbnet_probe, 1380 .suspend = asix_suspend, 1381 .resume = asix_resume, 1382 .reset_resume = asix_resume, 1383 .disconnect = usbnet_disconnect, 1384 .supports_autosuspend = 1, 1385 .disable_hub_initiated_lpm = 1, 1386 }; 1387 1388 module_usb_driver(asix_driver); 1389 1390 MODULE_AUTHOR("David Hollis"); 1391 MODULE_VERSION(DRIVER_VERSION); 1392 MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices"); 1393 MODULE_LICENSE("GPL"); 1394 1395