1 /* 2 * ASIX AX8817X based USB 2.0 Ethernet Devices 3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com> 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> 5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com> 6 * Copyright (c) 2002-2003 TiVo Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #include "asix.h" 24 25 #define PHY_MODE_MARVELL 0x0000 26 #define MII_MARVELL_LED_CTRL 0x0018 27 #define MII_MARVELL_STATUS 0x001b 28 #define MII_MARVELL_CTRL 0x0014 29 30 #define MARVELL_LED_MANUAL 0x0019 31 32 #define MARVELL_STATUS_HWCFG 0x0004 33 34 #define MARVELL_CTRL_TXDELAY 0x0002 35 #define MARVELL_CTRL_RXDELAY 0x0080 36 37 #define PHY_MODE_RTL8211CL 0x000C 38 39 struct ax88172_int_data { 40 __le16 res1; 41 u8 link; 42 __le16 res2; 43 u8 status; 44 __le16 res3; 45 } __packed; 46 47 static void asix_status(struct usbnet *dev, struct urb *urb) 48 { 49 struct ax88172_int_data *event; 50 int link; 51 52 if (urb->actual_length < 8) 53 return; 54 55 event = urb->transfer_buffer; 56 link = event->link & 0x01; 57 if (netif_carrier_ok(dev->net) != link) { 58 if (link) { 59 netif_carrier_on(dev->net); 60 usbnet_defer_kevent (dev, EVENT_LINK_RESET ); 61 } else 62 netif_carrier_off(dev->net); 63 netdev_dbg(dev->net, "Link Status is: %d\n", link); 64 } 65 } 66 67 static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr) 68 { 69 if (is_valid_ether_addr(addr)) { 70 memcpy(dev->net->dev_addr, addr, ETH_ALEN); 71 } else { 72 netdev_info(dev->net, "invalid hw address, using random\n"); 73 eth_hw_addr_random(dev->net); 74 } 75 } 76 77 /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */ 78 static u32 asix_get_phyid(struct usbnet *dev) 79 { 80 int phy_reg; 81 u32 phy_id; 82 int i; 83 84 /* Poll for the rare case the FW or phy isn't ready yet. */ 85 for (i = 0; i < 100; i++) { 86 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); 87 if (phy_reg != 0 && phy_reg != 0xFFFF) 88 break; 89 mdelay(1); 90 } 91 92 if (phy_reg <= 0 || phy_reg == 0xFFFF) 93 return 0; 94 95 phy_id = (phy_reg & 0xffff) << 16; 96 97 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); 98 if (phy_reg < 0) 99 return 0; 100 101 phy_id |= (phy_reg & 0xffff); 102 103 return phy_id; 104 } 105 106 static u32 asix_get_link(struct net_device *net) 107 { 108 struct usbnet *dev = netdev_priv(net); 109 110 return mii_link_ok(&dev->mii); 111 } 112 113 static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd) 114 { 115 struct usbnet *dev = netdev_priv(net); 116 117 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); 118 } 119 120 /* We need to override some ethtool_ops so we require our 121 own structure so we don't interfere with other usbnet 122 devices that may be connected at the same time. */ 123 static const struct ethtool_ops ax88172_ethtool_ops = { 124 .get_drvinfo = asix_get_drvinfo, 125 .get_link = asix_get_link, 126 .get_msglevel = usbnet_get_msglevel, 127 .set_msglevel = usbnet_set_msglevel, 128 .get_wol = asix_get_wol, 129 .set_wol = asix_set_wol, 130 .get_eeprom_len = asix_get_eeprom_len, 131 .get_eeprom = asix_get_eeprom, 132 .set_eeprom = asix_set_eeprom, 133 .get_settings = usbnet_get_settings, 134 .set_settings = usbnet_set_settings, 135 .nway_reset = usbnet_nway_reset, 136 }; 137 138 static void ax88172_set_multicast(struct net_device *net) 139 { 140 struct usbnet *dev = netdev_priv(net); 141 struct asix_data *data = (struct asix_data *)&dev->data; 142 u8 rx_ctl = 0x8c; 143 144 if (net->flags & IFF_PROMISC) { 145 rx_ctl |= 0x01; 146 } else if (net->flags & IFF_ALLMULTI || 147 netdev_mc_count(net) > AX_MAX_MCAST) { 148 rx_ctl |= 0x02; 149 } else if (netdev_mc_empty(net)) { 150 /* just broadcast and directed */ 151 } else { 152 /* We use the 20 byte dev->data 153 * for our 8 byte filter buffer 154 * to avoid allocating memory that 155 * is tricky to free later */ 156 struct netdev_hw_addr *ha; 157 u32 crc_bits; 158 159 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); 160 161 /* Build the multicast hash filter. */ 162 netdev_for_each_mc_addr(ha, net) { 163 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; 164 data->multi_filter[crc_bits >> 3] |= 165 1 << (crc_bits & 7); 166 } 167 168 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, 169 AX_MCAST_FILTER_SIZE, data->multi_filter); 170 171 rx_ctl |= 0x10; 172 } 173 174 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); 175 } 176 177 static int ax88172_link_reset(struct usbnet *dev) 178 { 179 u8 mode; 180 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 181 182 mii_check_media(&dev->mii, 1, 1); 183 mii_ethtool_gset(&dev->mii, &ecmd); 184 mode = AX88172_MEDIUM_DEFAULT; 185 186 if (ecmd.duplex != DUPLEX_FULL) 187 mode |= ~AX88172_MEDIUM_FD; 188 189 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 190 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode); 191 192 asix_write_medium_mode(dev, mode); 193 194 return 0; 195 } 196 197 static const struct net_device_ops ax88172_netdev_ops = { 198 .ndo_open = usbnet_open, 199 .ndo_stop = usbnet_stop, 200 .ndo_start_xmit = usbnet_start_xmit, 201 .ndo_tx_timeout = usbnet_tx_timeout, 202 .ndo_change_mtu = usbnet_change_mtu, 203 .ndo_set_mac_address = eth_mac_addr, 204 .ndo_validate_addr = eth_validate_addr, 205 .ndo_do_ioctl = asix_ioctl, 206 .ndo_set_rx_mode = ax88172_set_multicast, 207 }; 208 209 static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf) 210 { 211 int ret = 0; 212 u8 buf[ETH_ALEN]; 213 int i; 214 unsigned long gpio_bits = dev->driver_info->data; 215 216 usbnet_get_endpoints(dev,intf); 217 218 /* Toggle the GPIOs in a manufacturer/model specific way */ 219 for (i = 2; i >= 0; i--) { 220 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, 221 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL); 222 if (ret < 0) 223 goto out; 224 msleep(5); 225 } 226 227 ret = asix_write_rx_ctl(dev, 0x80); 228 if (ret < 0) 229 goto out; 230 231 /* Get the MAC address */ 232 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf); 233 if (ret < 0) { 234 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n", 235 ret); 236 goto out; 237 } 238 239 asix_set_netdev_dev_addr(dev, buf); 240 241 /* Initialize MII structure */ 242 dev->mii.dev = dev->net; 243 dev->mii.mdio_read = asix_mdio_read; 244 dev->mii.mdio_write = asix_mdio_write; 245 dev->mii.phy_id_mask = 0x3f; 246 dev->mii.reg_num_mask = 0x1f; 247 dev->mii.phy_id = asix_get_phy_addr(dev); 248 249 dev->net->netdev_ops = &ax88172_netdev_ops; 250 dev->net->ethtool_ops = &ax88172_ethtool_ops; 251 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ 252 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ 253 254 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); 255 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 256 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); 257 mii_nway_restart(&dev->mii); 258 259 return 0; 260 261 out: 262 return ret; 263 } 264 265 static const struct ethtool_ops ax88772_ethtool_ops = { 266 .get_drvinfo = asix_get_drvinfo, 267 .get_link = asix_get_link, 268 .get_msglevel = usbnet_get_msglevel, 269 .set_msglevel = usbnet_set_msglevel, 270 .get_wol = asix_get_wol, 271 .set_wol = asix_set_wol, 272 .get_eeprom_len = asix_get_eeprom_len, 273 .get_eeprom = asix_get_eeprom, 274 .set_eeprom = asix_set_eeprom, 275 .get_settings = usbnet_get_settings, 276 .set_settings = usbnet_set_settings, 277 .nway_reset = usbnet_nway_reset, 278 }; 279 280 static int ax88772_link_reset(struct usbnet *dev) 281 { 282 u16 mode; 283 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 284 285 mii_check_media(&dev->mii, 1, 1); 286 mii_ethtool_gset(&dev->mii, &ecmd); 287 mode = AX88772_MEDIUM_DEFAULT; 288 289 if (ethtool_cmd_speed(&ecmd) != SPEED_100) 290 mode &= ~AX_MEDIUM_PS; 291 292 if (ecmd.duplex != DUPLEX_FULL) 293 mode &= ~AX_MEDIUM_FD; 294 295 netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 296 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode); 297 298 asix_write_medium_mode(dev, mode); 299 300 return 0; 301 } 302 303 static int ax88772_reset(struct usbnet *dev) 304 { 305 struct asix_data *data = (struct asix_data *)&dev->data; 306 int ret, embd_phy; 307 u16 rx_ctl; 308 309 ret = asix_write_gpio(dev, 310 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5); 311 if (ret < 0) 312 goto out; 313 314 embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0); 315 316 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL); 317 if (ret < 0) { 318 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); 319 goto out; 320 } 321 322 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL); 323 if (ret < 0) 324 goto out; 325 326 msleep(150); 327 328 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR); 329 if (ret < 0) 330 goto out; 331 332 msleep(150); 333 334 if (embd_phy) { 335 ret = asix_sw_reset(dev, AX_SWRESET_IPRL); 336 if (ret < 0) 337 goto out; 338 } else { 339 ret = asix_sw_reset(dev, AX_SWRESET_PRTE); 340 if (ret < 0) 341 goto out; 342 } 343 344 msleep(150); 345 rx_ctl = asix_read_rx_ctl(dev); 346 netdev_dbg(dev->net, "RX_CTL is 0x%04x after software reset\n", rx_ctl); 347 ret = asix_write_rx_ctl(dev, 0x0000); 348 if (ret < 0) 349 goto out; 350 351 rx_ctl = asix_read_rx_ctl(dev); 352 netdev_dbg(dev->net, "RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl); 353 354 ret = asix_sw_reset(dev, AX_SWRESET_PRL); 355 if (ret < 0) 356 goto out; 357 358 msleep(150); 359 360 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL); 361 if (ret < 0) 362 goto out; 363 364 msleep(150); 365 366 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); 367 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 368 ADVERTISE_ALL | ADVERTISE_CSMA); 369 mii_nway_restart(&dev->mii); 370 371 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT); 372 if (ret < 0) 373 goto out; 374 375 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, 376 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, 377 AX88772_IPG2_DEFAULT, 0, NULL); 378 if (ret < 0) { 379 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret); 380 goto out; 381 } 382 383 /* Rewrite MAC address */ 384 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); 385 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, 386 data->mac_addr); 387 if (ret < 0) 388 goto out; 389 390 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 391 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL); 392 if (ret < 0) 393 goto out; 394 395 rx_ctl = asix_read_rx_ctl(dev); 396 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n", 397 rx_ctl); 398 399 rx_ctl = asix_read_medium_status(dev); 400 netdev_dbg(dev->net, 401 "Medium Status is 0x%04x after all initializations\n", 402 rx_ctl); 403 404 return 0; 405 406 out: 407 return ret; 408 409 } 410 411 static const struct net_device_ops ax88772_netdev_ops = { 412 .ndo_open = usbnet_open, 413 .ndo_stop = usbnet_stop, 414 .ndo_start_xmit = usbnet_start_xmit, 415 .ndo_tx_timeout = usbnet_tx_timeout, 416 .ndo_change_mtu = usbnet_change_mtu, 417 .ndo_set_mac_address = asix_set_mac_address, 418 .ndo_validate_addr = eth_validate_addr, 419 .ndo_do_ioctl = asix_ioctl, 420 .ndo_set_rx_mode = asix_set_multicast, 421 }; 422 423 static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf) 424 { 425 int ret, embd_phy; 426 u8 buf[ETH_ALEN]; 427 u32 phyid; 428 429 usbnet_get_endpoints(dev,intf); 430 431 /* Get the MAC address */ 432 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf); 433 if (ret < 0) { 434 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret); 435 return ret; 436 } 437 438 asix_set_netdev_dev_addr(dev, buf); 439 440 /* Initialize MII structure */ 441 dev->mii.dev = dev->net; 442 dev->mii.mdio_read = asix_mdio_read; 443 dev->mii.mdio_write = asix_mdio_write; 444 dev->mii.phy_id_mask = 0x1f; 445 dev->mii.reg_num_mask = 0x1f; 446 dev->mii.phy_id = asix_get_phy_addr(dev); 447 448 dev->net->netdev_ops = &ax88772_netdev_ops; 449 dev->net->ethtool_ops = &ax88772_ethtool_ops; 450 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ 451 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ 452 453 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0); 454 455 /* Reset the PHY to normal operation mode */ 456 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL); 457 if (ret < 0) { 458 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); 459 return ret; 460 } 461 462 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL); 463 if (ret < 0) 464 return ret; 465 466 msleep(150); 467 468 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR); 469 if (ret < 0) 470 return ret; 471 472 msleep(150); 473 474 ret = asix_sw_reset(dev, embd_phy ? AX_SWRESET_IPRL : AX_SWRESET_PRTE); 475 476 /* Read PHYID register *AFTER* the PHY was reset properly */ 477 phyid = asix_get_phyid(dev); 478 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid); 479 480 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ 481 if (dev->driver_info->flags & FLAG_FRAMING_AX) { 482 /* hard_mtu is still the default - the device does not support 483 jumbo eth frames */ 484 dev->rx_urb_size = 2048; 485 } 486 487 return 0; 488 } 489 490 static const struct ethtool_ops ax88178_ethtool_ops = { 491 .get_drvinfo = asix_get_drvinfo, 492 .get_link = asix_get_link, 493 .get_msglevel = usbnet_get_msglevel, 494 .set_msglevel = usbnet_set_msglevel, 495 .get_wol = asix_get_wol, 496 .set_wol = asix_set_wol, 497 .get_eeprom_len = asix_get_eeprom_len, 498 .get_eeprom = asix_get_eeprom, 499 .set_eeprom = asix_set_eeprom, 500 .get_settings = usbnet_get_settings, 501 .set_settings = usbnet_set_settings, 502 .nway_reset = usbnet_nway_reset, 503 }; 504 505 static int marvell_phy_init(struct usbnet *dev) 506 { 507 struct asix_data *data = (struct asix_data *)&dev->data; 508 u16 reg; 509 510 netdev_dbg(dev->net, "marvell_phy_init()\n"); 511 512 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS); 513 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg); 514 515 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL, 516 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY); 517 518 if (data->ledmode) { 519 reg = asix_mdio_read(dev->net, dev->mii.phy_id, 520 MII_MARVELL_LED_CTRL); 521 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg); 522 523 reg &= 0xf8ff; 524 reg |= (1 + 0x0100); 525 asix_mdio_write(dev->net, dev->mii.phy_id, 526 MII_MARVELL_LED_CTRL, reg); 527 528 reg = asix_mdio_read(dev->net, dev->mii.phy_id, 529 MII_MARVELL_LED_CTRL); 530 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg); 531 reg &= 0xfc0f; 532 } 533 534 return 0; 535 } 536 537 static int rtl8211cl_phy_init(struct usbnet *dev) 538 { 539 struct asix_data *data = (struct asix_data *)&dev->data; 540 541 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n"); 542 543 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005); 544 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0); 545 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01, 546 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080); 547 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); 548 549 if (data->ledmode == 12) { 550 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002); 551 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb); 552 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); 553 } 554 555 return 0; 556 } 557 558 static int marvell_led_status(struct usbnet *dev, u16 speed) 559 { 560 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL); 561 562 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg); 563 564 /* Clear out the center LED bits - 0x03F0 */ 565 reg &= 0xfc0f; 566 567 switch (speed) { 568 case SPEED_1000: 569 reg |= 0x03e0; 570 break; 571 case SPEED_100: 572 reg |= 0x03b0; 573 break; 574 default: 575 reg |= 0x02f0; 576 } 577 578 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg); 579 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg); 580 581 return 0; 582 } 583 584 static int ax88178_reset(struct usbnet *dev) 585 { 586 struct asix_data *data = (struct asix_data *)&dev->data; 587 int ret; 588 __le16 eeprom; 589 u8 status; 590 int gpio0 = 0; 591 u32 phyid; 592 593 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status); 594 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status); 595 596 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL); 597 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom); 598 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL); 599 600 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom); 601 602 if (eeprom == cpu_to_le16(0xffff)) { 603 data->phymode = PHY_MODE_MARVELL; 604 data->ledmode = 0; 605 gpio0 = 1; 606 } else { 607 data->phymode = le16_to_cpu(eeprom) & 0x7F; 608 data->ledmode = le16_to_cpu(eeprom) >> 8; 609 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1; 610 } 611 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode); 612 613 /* Power up external GigaPHY through AX88178 GPIO pin */ 614 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40); 615 if ((le16_to_cpu(eeprom) >> 8) != 1) { 616 asix_write_gpio(dev, 0x003c, 30); 617 asix_write_gpio(dev, 0x001c, 300); 618 asix_write_gpio(dev, 0x003c, 30); 619 } else { 620 netdev_dbg(dev->net, "gpio phymode == 1 path\n"); 621 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30); 622 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30); 623 } 624 625 /* Read PHYID register *AFTER* powering up PHY */ 626 phyid = asix_get_phyid(dev); 627 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid); 628 629 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */ 630 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL); 631 632 asix_sw_reset(dev, 0); 633 msleep(150); 634 635 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD); 636 msleep(150); 637 638 asix_write_rx_ctl(dev, 0); 639 640 if (data->phymode == PHY_MODE_MARVELL) { 641 marvell_phy_init(dev); 642 msleep(60); 643 } else if (data->phymode == PHY_MODE_RTL8211CL) 644 rtl8211cl_phy_init(dev); 645 646 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, 647 BMCR_RESET | BMCR_ANENABLE); 648 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 649 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); 650 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000, 651 ADVERTISE_1000FULL); 652 653 mii_nway_restart(&dev->mii); 654 655 ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT); 656 if (ret < 0) 657 return ret; 658 659 /* Rewrite MAC address */ 660 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); 661 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, 662 data->mac_addr); 663 if (ret < 0) 664 return ret; 665 666 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL); 667 if (ret < 0) 668 return ret; 669 670 return 0; 671 } 672 673 static int ax88178_link_reset(struct usbnet *dev) 674 { 675 u16 mode; 676 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 677 struct asix_data *data = (struct asix_data *)&dev->data; 678 u32 speed; 679 680 netdev_dbg(dev->net, "ax88178_link_reset()\n"); 681 682 mii_check_media(&dev->mii, 1, 1); 683 mii_ethtool_gset(&dev->mii, &ecmd); 684 mode = AX88178_MEDIUM_DEFAULT; 685 speed = ethtool_cmd_speed(&ecmd); 686 687 if (speed == SPEED_1000) 688 mode |= AX_MEDIUM_GM; 689 else if (speed == SPEED_100) 690 mode |= AX_MEDIUM_PS; 691 else 692 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM); 693 694 mode |= AX_MEDIUM_ENCK; 695 696 if (ecmd.duplex == DUPLEX_FULL) 697 mode |= AX_MEDIUM_FD; 698 else 699 mode &= ~AX_MEDIUM_FD; 700 701 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 702 speed, ecmd.duplex, mode); 703 704 asix_write_medium_mode(dev, mode); 705 706 if (data->phymode == PHY_MODE_MARVELL && data->ledmode) 707 marvell_led_status(dev, speed); 708 709 return 0; 710 } 711 712 static void ax88178_set_mfb(struct usbnet *dev) 713 { 714 u16 mfb = AX_RX_CTL_MFB_16384; 715 u16 rxctl; 716 u16 medium; 717 int old_rx_urb_size = dev->rx_urb_size; 718 719 if (dev->hard_mtu < 2048) { 720 dev->rx_urb_size = 2048; 721 mfb = AX_RX_CTL_MFB_2048; 722 } else if (dev->hard_mtu < 4096) { 723 dev->rx_urb_size = 4096; 724 mfb = AX_RX_CTL_MFB_4096; 725 } else if (dev->hard_mtu < 8192) { 726 dev->rx_urb_size = 8192; 727 mfb = AX_RX_CTL_MFB_8192; 728 } else if (dev->hard_mtu < 16384) { 729 dev->rx_urb_size = 16384; 730 mfb = AX_RX_CTL_MFB_16384; 731 } 732 733 rxctl = asix_read_rx_ctl(dev); 734 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb); 735 736 medium = asix_read_medium_status(dev); 737 if (dev->net->mtu > 1500) 738 medium |= AX_MEDIUM_JFE; 739 else 740 medium &= ~AX_MEDIUM_JFE; 741 asix_write_medium_mode(dev, medium); 742 743 if (dev->rx_urb_size > old_rx_urb_size) 744 usbnet_unlink_rx_urbs(dev); 745 } 746 747 static int ax88178_change_mtu(struct net_device *net, int new_mtu) 748 { 749 struct usbnet *dev = netdev_priv(net); 750 int ll_mtu = new_mtu + net->hard_header_len + 4; 751 752 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu); 753 754 if (new_mtu <= 0 || ll_mtu > 16384) 755 return -EINVAL; 756 757 if ((ll_mtu % dev->maxpacket) == 0) 758 return -EDOM; 759 760 net->mtu = new_mtu; 761 dev->hard_mtu = net->mtu + net->hard_header_len; 762 ax88178_set_mfb(dev); 763 764 return 0; 765 } 766 767 static const struct net_device_ops ax88178_netdev_ops = { 768 .ndo_open = usbnet_open, 769 .ndo_stop = usbnet_stop, 770 .ndo_start_xmit = usbnet_start_xmit, 771 .ndo_tx_timeout = usbnet_tx_timeout, 772 .ndo_set_mac_address = asix_set_mac_address, 773 .ndo_validate_addr = eth_validate_addr, 774 .ndo_set_rx_mode = asix_set_multicast, 775 .ndo_do_ioctl = asix_ioctl, 776 .ndo_change_mtu = ax88178_change_mtu, 777 }; 778 779 static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf) 780 { 781 int ret; 782 u8 buf[ETH_ALEN]; 783 784 usbnet_get_endpoints(dev,intf); 785 786 /* Get the MAC address */ 787 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf); 788 if (ret < 0) { 789 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret); 790 return ret; 791 } 792 793 asix_set_netdev_dev_addr(dev, buf); 794 795 /* Initialize MII structure */ 796 dev->mii.dev = dev->net; 797 dev->mii.mdio_read = asix_mdio_read; 798 dev->mii.mdio_write = asix_mdio_write; 799 dev->mii.phy_id_mask = 0x1f; 800 dev->mii.reg_num_mask = 0xff; 801 dev->mii.supports_gmii = 1; 802 dev->mii.phy_id = asix_get_phy_addr(dev); 803 804 dev->net->netdev_ops = &ax88178_netdev_ops; 805 dev->net->ethtool_ops = &ax88178_ethtool_ops; 806 807 /* Blink LEDS so users know driver saw dongle */ 808 asix_sw_reset(dev, 0); 809 msleep(150); 810 811 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD); 812 msleep(150); 813 814 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ 815 if (dev->driver_info->flags & FLAG_FRAMING_AX) { 816 /* hard_mtu is still the default - the device does not support 817 jumbo eth frames */ 818 dev->rx_urb_size = 2048; 819 } 820 821 return 0; 822 } 823 824 static const struct driver_info ax8817x_info = { 825 .description = "ASIX AX8817x USB 2.0 Ethernet", 826 .bind = ax88172_bind, 827 .status = asix_status, 828 .link_reset = ax88172_link_reset, 829 .reset = ax88172_link_reset, 830 .flags = FLAG_ETHER | FLAG_LINK_INTR, 831 .data = 0x00130103, 832 }; 833 834 static const struct driver_info dlink_dub_e100_info = { 835 .description = "DLink DUB-E100 USB Ethernet", 836 .bind = ax88172_bind, 837 .status = asix_status, 838 .link_reset = ax88172_link_reset, 839 .reset = ax88172_link_reset, 840 .flags = FLAG_ETHER | FLAG_LINK_INTR, 841 .data = 0x009f9d9f, 842 }; 843 844 static const struct driver_info netgear_fa120_info = { 845 .description = "Netgear FA-120 USB Ethernet", 846 .bind = ax88172_bind, 847 .status = asix_status, 848 .link_reset = ax88172_link_reset, 849 .reset = ax88172_link_reset, 850 .flags = FLAG_ETHER | FLAG_LINK_INTR, 851 .data = 0x00130103, 852 }; 853 854 static const struct driver_info hawking_uf200_info = { 855 .description = "Hawking UF200 USB Ethernet", 856 .bind = ax88172_bind, 857 .status = asix_status, 858 .link_reset = ax88172_link_reset, 859 .reset = ax88172_link_reset, 860 .flags = FLAG_ETHER | FLAG_LINK_INTR, 861 .data = 0x001f1d1f, 862 }; 863 864 static const struct driver_info ax88772_info = { 865 .description = "ASIX AX88772 USB 2.0 Ethernet", 866 .bind = ax88772_bind, 867 .status = asix_status, 868 .link_reset = ax88772_link_reset, 869 .reset = ax88772_reset, 870 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET, 871 .rx_fixup = asix_rx_fixup, 872 .tx_fixup = asix_tx_fixup, 873 }; 874 875 static const struct driver_info ax88178_info = { 876 .description = "ASIX AX88178 USB 2.0 Ethernet", 877 .bind = ax88178_bind, 878 .status = asix_status, 879 .link_reset = ax88178_link_reset, 880 .reset = ax88178_reset, 881 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR, 882 .rx_fixup = asix_rx_fixup, 883 .tx_fixup = asix_tx_fixup, 884 }; 885 886 extern const struct driver_info ax88172a_info; 887 888 static const struct usb_device_id products [] = { 889 { 890 // Linksys USB200M 891 USB_DEVICE (0x077b, 0x2226), 892 .driver_info = (unsigned long) &ax8817x_info, 893 }, { 894 // Netgear FA120 895 USB_DEVICE (0x0846, 0x1040), 896 .driver_info = (unsigned long) &netgear_fa120_info, 897 }, { 898 // DLink DUB-E100 899 USB_DEVICE (0x2001, 0x1a00), 900 .driver_info = (unsigned long) &dlink_dub_e100_info, 901 }, { 902 // Intellinet, ST Lab USB Ethernet 903 USB_DEVICE (0x0b95, 0x1720), 904 .driver_info = (unsigned long) &ax8817x_info, 905 }, { 906 // Hawking UF200, TrendNet TU2-ET100 907 USB_DEVICE (0x07b8, 0x420a), 908 .driver_info = (unsigned long) &hawking_uf200_info, 909 }, { 910 // Billionton Systems, USB2AR 911 USB_DEVICE (0x08dd, 0x90ff), 912 .driver_info = (unsigned long) &ax8817x_info, 913 }, { 914 // ATEN UC210T 915 USB_DEVICE (0x0557, 0x2009), 916 .driver_info = (unsigned long) &ax8817x_info, 917 }, { 918 // Buffalo LUA-U2-KTX 919 USB_DEVICE (0x0411, 0x003d), 920 .driver_info = (unsigned long) &ax8817x_info, 921 }, { 922 // Buffalo LUA-U2-GT 10/100/1000 923 USB_DEVICE (0x0411, 0x006e), 924 .driver_info = (unsigned long) &ax88178_info, 925 }, { 926 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter" 927 USB_DEVICE (0x6189, 0x182d), 928 .driver_info = (unsigned long) &ax8817x_info, 929 }, { 930 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter" 931 USB_DEVICE (0x0df6, 0x0056), 932 .driver_info = (unsigned long) &ax88178_info, 933 }, { 934 // corega FEther USB2-TX 935 USB_DEVICE (0x07aa, 0x0017), 936 .driver_info = (unsigned long) &ax8817x_info, 937 }, { 938 // Surecom EP-1427X-2 939 USB_DEVICE (0x1189, 0x0893), 940 .driver_info = (unsigned long) &ax8817x_info, 941 }, { 942 // goodway corp usb gwusb2e 943 USB_DEVICE (0x1631, 0x6200), 944 .driver_info = (unsigned long) &ax8817x_info, 945 }, { 946 // JVC MP-PRX1 Port Replicator 947 USB_DEVICE (0x04f1, 0x3008), 948 .driver_info = (unsigned long) &ax8817x_info, 949 }, { 950 // Lenovo U2L100P 10/100 951 USB_DEVICE (0x17ef, 0x7203), 952 .driver_info = (unsigned long) &ax88772_info, 953 }, { 954 // ASIX AX88772B 10/100 955 USB_DEVICE (0x0b95, 0x772b), 956 .driver_info = (unsigned long) &ax88772_info, 957 }, { 958 // ASIX AX88772 10/100 959 USB_DEVICE (0x0b95, 0x7720), 960 .driver_info = (unsigned long) &ax88772_info, 961 }, { 962 // ASIX AX88178 10/100/1000 963 USB_DEVICE (0x0b95, 0x1780), 964 .driver_info = (unsigned long) &ax88178_info, 965 }, { 966 // Logitec LAN-GTJ/U2A 967 USB_DEVICE (0x0789, 0x0160), 968 .driver_info = (unsigned long) &ax88178_info, 969 }, { 970 // Linksys USB200M Rev 2 971 USB_DEVICE (0x13b1, 0x0018), 972 .driver_info = (unsigned long) &ax88772_info, 973 }, { 974 // 0Q0 cable ethernet 975 USB_DEVICE (0x1557, 0x7720), 976 .driver_info = (unsigned long) &ax88772_info, 977 }, { 978 // DLink DUB-E100 H/W Ver B1 979 USB_DEVICE (0x07d1, 0x3c05), 980 .driver_info = (unsigned long) &ax88772_info, 981 }, { 982 // DLink DUB-E100 H/W Ver B1 Alternate 983 USB_DEVICE (0x2001, 0x3c05), 984 .driver_info = (unsigned long) &ax88772_info, 985 }, { 986 // DLink DUB-E100 H/W Ver C1 987 USB_DEVICE (0x2001, 0x1a02), 988 .driver_info = (unsigned long) &ax88772_info, 989 }, { 990 // Linksys USB1000 991 USB_DEVICE (0x1737, 0x0039), 992 .driver_info = (unsigned long) &ax88178_info, 993 }, { 994 // IO-DATA ETG-US2 995 USB_DEVICE (0x04bb, 0x0930), 996 .driver_info = (unsigned long) &ax88178_info, 997 }, { 998 // Belkin F5D5055 999 USB_DEVICE(0x050d, 0x5055), 1000 .driver_info = (unsigned long) &ax88178_info, 1001 }, { 1002 // Apple USB Ethernet Adapter 1003 USB_DEVICE(0x05ac, 0x1402), 1004 .driver_info = (unsigned long) &ax88772_info, 1005 }, { 1006 // Cables-to-Go USB Ethernet Adapter 1007 USB_DEVICE(0x0b95, 0x772a), 1008 .driver_info = (unsigned long) &ax88772_info, 1009 }, { 1010 // ABOCOM for pci 1011 USB_DEVICE(0x14ea, 0xab11), 1012 .driver_info = (unsigned long) &ax88178_info, 1013 }, { 1014 // ASIX 88772a 1015 USB_DEVICE(0x0db0, 0xa877), 1016 .driver_info = (unsigned long) &ax88772_info, 1017 }, { 1018 // Asus USB Ethernet Adapter 1019 USB_DEVICE (0x0b95, 0x7e2b), 1020 .driver_info = (unsigned long) &ax88772_info, 1021 }, { 1022 /* ASIX 88172a demo board */ 1023 USB_DEVICE(0x0b95, 0x172a), 1024 .driver_info = (unsigned long) &ax88172a_info, 1025 }, 1026 { }, // END 1027 }; 1028 MODULE_DEVICE_TABLE(usb, products); 1029 1030 static struct usb_driver asix_driver = { 1031 .name = DRIVER_NAME, 1032 .id_table = products, 1033 .probe = usbnet_probe, 1034 .suspend = usbnet_suspend, 1035 .resume = usbnet_resume, 1036 .disconnect = usbnet_disconnect, 1037 .supports_autosuspend = 1, 1038 .disable_hub_initiated_lpm = 1, 1039 }; 1040 1041 module_usb_driver(asix_driver); 1042 1043 MODULE_AUTHOR("David Hollis"); 1044 MODULE_VERSION(DRIVER_VERSION); 1045 MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices"); 1046 MODULE_LICENSE("GPL"); 1047 1048