1 /* 2 * ASIX AX8817X based USB 2.0 Ethernet Devices 3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com> 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> 5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com> 6 * Copyright (c) 2002-2003 TiVo Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "asix.h" 23 24 #define PHY_MODE_MARVELL 0x0000 25 #define MII_MARVELL_LED_CTRL 0x0018 26 #define MII_MARVELL_STATUS 0x001b 27 #define MII_MARVELL_CTRL 0x0014 28 29 #define MARVELL_LED_MANUAL 0x0019 30 31 #define MARVELL_STATUS_HWCFG 0x0004 32 33 #define MARVELL_CTRL_TXDELAY 0x0002 34 #define MARVELL_CTRL_RXDELAY 0x0080 35 36 #define PHY_MODE_RTL8211CL 0x000C 37 38 #define AX88772A_PHY14H 0x14 39 #define AX88772A_PHY14H_DEFAULT 0x442C 40 41 #define AX88772A_PHY15H 0x15 42 #define AX88772A_PHY15H_DEFAULT 0x03C8 43 44 #define AX88772A_PHY16H 0x16 45 #define AX88772A_PHY16H_DEFAULT 0x4044 46 47 struct ax88172_int_data { 48 __le16 res1; 49 u8 link; 50 __le16 res2; 51 u8 status; 52 __le16 res3; 53 } __packed; 54 55 static void asix_status(struct usbnet *dev, struct urb *urb) 56 { 57 struct ax88172_int_data *event; 58 int link; 59 60 if (urb->actual_length < 8) 61 return; 62 63 event = urb->transfer_buffer; 64 link = event->link & 0x01; 65 if (netif_carrier_ok(dev->net) != link) { 66 usbnet_link_change(dev, link, 1); 67 netdev_dbg(dev->net, "Link Status is: %d\n", link); 68 } 69 } 70 71 static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr) 72 { 73 if (is_valid_ether_addr(addr)) { 74 memcpy(dev->net->dev_addr, addr, ETH_ALEN); 75 } else { 76 netdev_info(dev->net, "invalid hw address, using random\n"); 77 eth_hw_addr_random(dev->net); 78 } 79 } 80 81 /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */ 82 static u32 asix_get_phyid(struct usbnet *dev) 83 { 84 int phy_reg; 85 u32 phy_id; 86 int i; 87 88 /* Poll for the rare case the FW or phy isn't ready yet. */ 89 for (i = 0; i < 100; i++) { 90 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); 91 if (phy_reg < 0) 92 return 0; 93 if (phy_reg != 0 && phy_reg != 0xFFFF) 94 break; 95 mdelay(1); 96 } 97 98 if (phy_reg <= 0 || phy_reg == 0xFFFF) 99 return 0; 100 101 phy_id = (phy_reg & 0xffff) << 16; 102 103 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); 104 if (phy_reg < 0) 105 return 0; 106 107 phy_id |= (phy_reg & 0xffff); 108 109 return phy_id; 110 } 111 112 static u32 asix_get_link(struct net_device *net) 113 { 114 struct usbnet *dev = netdev_priv(net); 115 116 return mii_link_ok(&dev->mii); 117 } 118 119 static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd) 120 { 121 struct usbnet *dev = netdev_priv(net); 122 123 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); 124 } 125 126 /* We need to override some ethtool_ops so we require our 127 own structure so we don't interfere with other usbnet 128 devices that may be connected at the same time. */ 129 static const struct ethtool_ops ax88172_ethtool_ops = { 130 .get_drvinfo = asix_get_drvinfo, 131 .get_link = asix_get_link, 132 .get_msglevel = usbnet_get_msglevel, 133 .set_msglevel = usbnet_set_msglevel, 134 .get_wol = asix_get_wol, 135 .set_wol = asix_set_wol, 136 .get_eeprom_len = asix_get_eeprom_len, 137 .get_eeprom = asix_get_eeprom, 138 .set_eeprom = asix_set_eeprom, 139 .nway_reset = usbnet_nway_reset, 140 .get_link_ksettings = usbnet_get_link_ksettings, 141 .set_link_ksettings = usbnet_set_link_ksettings, 142 }; 143 144 static void ax88172_set_multicast(struct net_device *net) 145 { 146 struct usbnet *dev = netdev_priv(net); 147 struct asix_data *data = (struct asix_data *)&dev->data; 148 u8 rx_ctl = 0x8c; 149 150 if (net->flags & IFF_PROMISC) { 151 rx_ctl |= 0x01; 152 } else if (net->flags & IFF_ALLMULTI || 153 netdev_mc_count(net) > AX_MAX_MCAST) { 154 rx_ctl |= 0x02; 155 } else if (netdev_mc_empty(net)) { 156 /* just broadcast and directed */ 157 } else { 158 /* We use the 20 byte dev->data 159 * for our 8 byte filter buffer 160 * to avoid allocating memory that 161 * is tricky to free later */ 162 struct netdev_hw_addr *ha; 163 u32 crc_bits; 164 165 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); 166 167 /* Build the multicast hash filter. */ 168 netdev_for_each_mc_addr(ha, net) { 169 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; 170 data->multi_filter[crc_bits >> 3] |= 171 1 << (crc_bits & 7); 172 } 173 174 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, 175 AX_MCAST_FILTER_SIZE, data->multi_filter); 176 177 rx_ctl |= 0x10; 178 } 179 180 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); 181 } 182 183 static int ax88172_link_reset(struct usbnet *dev) 184 { 185 u8 mode; 186 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 187 188 mii_check_media(&dev->mii, 1, 1); 189 mii_ethtool_gset(&dev->mii, &ecmd); 190 mode = AX88172_MEDIUM_DEFAULT; 191 192 if (ecmd.duplex != DUPLEX_FULL) 193 mode |= ~AX88172_MEDIUM_FD; 194 195 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 196 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode); 197 198 asix_write_medium_mode(dev, mode, 0); 199 200 return 0; 201 } 202 203 static const struct net_device_ops ax88172_netdev_ops = { 204 .ndo_open = usbnet_open, 205 .ndo_stop = usbnet_stop, 206 .ndo_start_xmit = usbnet_start_xmit, 207 .ndo_tx_timeout = usbnet_tx_timeout, 208 .ndo_change_mtu = usbnet_change_mtu, 209 .ndo_get_stats64 = usbnet_get_stats64, 210 .ndo_set_mac_address = eth_mac_addr, 211 .ndo_validate_addr = eth_validate_addr, 212 .ndo_do_ioctl = asix_ioctl, 213 .ndo_set_rx_mode = ax88172_set_multicast, 214 }; 215 216 static void asix_phy_reset(struct usbnet *dev, unsigned int reset_bits) 217 { 218 unsigned int timeout = 5000; 219 220 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits); 221 222 /* give phy_id a chance to process reset */ 223 udelay(500); 224 225 /* See IEEE 802.3 "22.2.4.1.1 Reset": 500ms max */ 226 while (timeout--) { 227 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR) 228 & BMCR_RESET) 229 udelay(100); 230 else 231 return; 232 } 233 234 netdev_err(dev->net, "BMCR_RESET timeout on phy_id %d\n", 235 dev->mii.phy_id); 236 } 237 238 static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf) 239 { 240 int ret = 0; 241 u8 buf[ETH_ALEN]; 242 int i; 243 unsigned long gpio_bits = dev->driver_info->data; 244 245 usbnet_get_endpoints(dev,intf); 246 247 /* Toggle the GPIOs in a manufacturer/model specific way */ 248 for (i = 2; i >= 0; i--) { 249 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, 250 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL, 0); 251 if (ret < 0) 252 goto out; 253 msleep(5); 254 } 255 256 ret = asix_write_rx_ctl(dev, 0x80, 0); 257 if (ret < 0) 258 goto out; 259 260 /* Get the MAC address */ 261 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 262 0, 0, ETH_ALEN, buf, 0); 263 if (ret < 0) { 264 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n", 265 ret); 266 goto out; 267 } 268 269 asix_set_netdev_dev_addr(dev, buf); 270 271 /* Initialize MII structure */ 272 dev->mii.dev = dev->net; 273 dev->mii.mdio_read = asix_mdio_read; 274 dev->mii.mdio_write = asix_mdio_write; 275 dev->mii.phy_id_mask = 0x3f; 276 dev->mii.reg_num_mask = 0x1f; 277 dev->mii.phy_id = asix_get_phy_addr(dev); 278 279 dev->net->netdev_ops = &ax88172_netdev_ops; 280 dev->net->ethtool_ops = &ax88172_ethtool_ops; 281 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ 282 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ 283 284 asix_phy_reset(dev, BMCR_RESET); 285 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 286 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); 287 mii_nway_restart(&dev->mii); 288 289 return 0; 290 291 out: 292 return ret; 293 } 294 295 static const struct ethtool_ops ax88772_ethtool_ops = { 296 .get_drvinfo = asix_get_drvinfo, 297 .get_link = asix_get_link, 298 .get_msglevel = usbnet_get_msglevel, 299 .set_msglevel = usbnet_set_msglevel, 300 .get_wol = asix_get_wol, 301 .set_wol = asix_set_wol, 302 .get_eeprom_len = asix_get_eeprom_len, 303 .get_eeprom = asix_get_eeprom, 304 .set_eeprom = asix_set_eeprom, 305 .nway_reset = usbnet_nway_reset, 306 .get_link_ksettings = usbnet_get_link_ksettings, 307 .set_link_ksettings = usbnet_set_link_ksettings, 308 }; 309 310 static int ax88772_link_reset(struct usbnet *dev) 311 { 312 u16 mode; 313 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 314 315 mii_check_media(&dev->mii, 1, 1); 316 mii_ethtool_gset(&dev->mii, &ecmd); 317 mode = AX88772_MEDIUM_DEFAULT; 318 319 if (ethtool_cmd_speed(&ecmd) != SPEED_100) 320 mode &= ~AX_MEDIUM_PS; 321 322 if (ecmd.duplex != DUPLEX_FULL) 323 mode &= ~AX_MEDIUM_FD; 324 325 netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 326 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode); 327 328 asix_write_medium_mode(dev, mode, 0); 329 330 return 0; 331 } 332 333 static int ax88772_reset(struct usbnet *dev) 334 { 335 struct asix_data *data = (struct asix_data *)&dev->data; 336 int ret; 337 338 /* Rewrite MAC address */ 339 ether_addr_copy(data->mac_addr, dev->net->dev_addr); 340 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, 341 ETH_ALEN, data->mac_addr, 0); 342 if (ret < 0) 343 goto out; 344 345 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 346 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0); 347 if (ret < 0) 348 goto out; 349 350 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, 0); 351 if (ret < 0) 352 goto out; 353 354 return 0; 355 356 out: 357 return ret; 358 } 359 360 static int ax88772_hw_reset(struct usbnet *dev, int in_pm) 361 { 362 struct asix_data *data = (struct asix_data *)&dev->data; 363 int ret, embd_phy; 364 u16 rx_ctl; 365 366 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 367 AX_GPIO_GPO2EN, 5, in_pm); 368 if (ret < 0) 369 goto out; 370 371 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0); 372 373 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 374 0, 0, NULL, in_pm); 375 if (ret < 0) { 376 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); 377 goto out; 378 } 379 380 if (embd_phy) { 381 ret = asix_sw_reset(dev, AX_SWRESET_IPPD, in_pm); 382 if (ret < 0) 383 goto out; 384 385 usleep_range(10000, 11000); 386 387 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm); 388 if (ret < 0) 389 goto out; 390 391 msleep(60); 392 393 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL, 394 in_pm); 395 if (ret < 0) 396 goto out; 397 } else { 398 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL, 399 in_pm); 400 if (ret < 0) 401 goto out; 402 } 403 404 msleep(150); 405 406 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 407 MII_PHYSID1))){ 408 ret = -EIO; 409 goto out; 410 } 411 412 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 413 if (ret < 0) 414 goto out; 415 416 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm); 417 if (ret < 0) 418 goto out; 419 420 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, 421 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, 422 AX88772_IPG2_DEFAULT, 0, NULL, in_pm); 423 if (ret < 0) { 424 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret); 425 goto out; 426 } 427 428 /* Rewrite MAC address */ 429 ether_addr_copy(data->mac_addr, dev->net->dev_addr); 430 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, 431 ETH_ALEN, data->mac_addr, in_pm); 432 if (ret < 0) 433 goto out; 434 435 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 436 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 437 if (ret < 0) 438 goto out; 439 440 rx_ctl = asix_read_rx_ctl(dev, in_pm); 441 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n", 442 rx_ctl); 443 444 rx_ctl = asix_read_medium_status(dev, in_pm); 445 netdev_dbg(dev->net, 446 "Medium Status is 0x%04x after all initializations\n", 447 rx_ctl); 448 449 return 0; 450 451 out: 452 return ret; 453 } 454 455 static int ax88772a_hw_reset(struct usbnet *dev, int in_pm) 456 { 457 struct asix_data *data = (struct asix_data *)&dev->data; 458 int ret, embd_phy; 459 u16 rx_ctl, phy14h, phy15h, phy16h; 460 u8 chipcode = 0; 461 462 ret = asix_write_gpio(dev, AX_GPIO_RSE, 5, in_pm); 463 if (ret < 0) 464 goto out; 465 466 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0); 467 468 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy | 469 AX_PHYSEL_SSEN, 0, 0, NULL, in_pm); 470 if (ret < 0) { 471 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); 472 goto out; 473 } 474 usleep_range(10000, 11000); 475 476 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_IPRL, in_pm); 477 if (ret < 0) 478 goto out; 479 480 usleep_range(10000, 11000); 481 482 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm); 483 if (ret < 0) 484 goto out; 485 486 msleep(160); 487 488 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm); 489 if (ret < 0) 490 goto out; 491 492 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm); 493 if (ret < 0) 494 goto out; 495 496 msleep(200); 497 498 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 499 MII_PHYSID1))) { 500 ret = -1; 501 goto out; 502 } 503 504 ret = asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 505 0, 1, &chipcode, in_pm); 506 if (ret < 0) 507 goto out; 508 509 if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772B_CHIPCODE) { 510 ret = asix_write_cmd(dev, AX_QCTCTRL, 0x8000, 0x8001, 511 0, NULL, in_pm); 512 if (ret < 0) { 513 netdev_dbg(dev->net, "Write BQ setting failed: %d\n", 514 ret); 515 goto out; 516 } 517 } else if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772A_CHIPCODE) { 518 /* Check if the PHY registers have default settings */ 519 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 520 AX88772A_PHY14H); 521 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 522 AX88772A_PHY15H); 523 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 524 AX88772A_PHY16H); 525 526 netdev_dbg(dev->net, 527 "772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\n", 528 phy14h, phy15h, phy16h); 529 530 /* Restore PHY registers default setting if not */ 531 if (phy14h != AX88772A_PHY14H_DEFAULT) 532 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, 533 AX88772A_PHY14H, 534 AX88772A_PHY14H_DEFAULT); 535 if (phy15h != AX88772A_PHY15H_DEFAULT) 536 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, 537 AX88772A_PHY15H, 538 AX88772A_PHY15H_DEFAULT); 539 if (phy16h != AX88772A_PHY16H_DEFAULT) 540 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, 541 AX88772A_PHY16H, 542 AX88772A_PHY16H_DEFAULT); 543 } 544 545 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, 546 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, 547 AX88772_IPG2_DEFAULT, 0, NULL, in_pm); 548 if (ret < 0) { 549 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret); 550 goto out; 551 } 552 553 /* Rewrite MAC address */ 554 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); 555 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, 556 data->mac_addr, in_pm); 557 if (ret < 0) 558 goto out; 559 560 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 561 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 562 if (ret < 0) 563 goto out; 564 565 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm); 566 if (ret < 0) 567 return ret; 568 569 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 570 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 571 if (ret < 0) 572 goto out; 573 574 rx_ctl = asix_read_rx_ctl(dev, in_pm); 575 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n", 576 rx_ctl); 577 578 rx_ctl = asix_read_medium_status(dev, in_pm); 579 netdev_dbg(dev->net, 580 "Medium Status is 0x%04x after all initializations\n", 581 rx_ctl); 582 583 return 0; 584 585 out: 586 return ret; 587 } 588 589 static const struct net_device_ops ax88772_netdev_ops = { 590 .ndo_open = usbnet_open, 591 .ndo_stop = usbnet_stop, 592 .ndo_start_xmit = usbnet_start_xmit, 593 .ndo_tx_timeout = usbnet_tx_timeout, 594 .ndo_change_mtu = usbnet_change_mtu, 595 .ndo_get_stats64 = usbnet_get_stats64, 596 .ndo_set_mac_address = asix_set_mac_address, 597 .ndo_validate_addr = eth_validate_addr, 598 .ndo_do_ioctl = asix_ioctl, 599 .ndo_set_rx_mode = asix_set_multicast, 600 }; 601 602 static void ax88772_suspend(struct usbnet *dev) 603 { 604 struct asix_common_private *priv = dev->driver_priv; 605 u16 medium; 606 607 /* Stop MAC operation */ 608 medium = asix_read_medium_status(dev, 1); 609 medium &= ~AX_MEDIUM_RE; 610 asix_write_medium_mode(dev, medium, 1); 611 612 netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n", 613 asix_read_medium_status(dev, 1)); 614 615 /* Preserve BMCR for restoring */ 616 priv->presvd_phy_bmcr = 617 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_BMCR); 618 619 /* Preserve ANAR for restoring */ 620 priv->presvd_phy_advertise = 621 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE); 622 } 623 624 static int asix_suspend(struct usb_interface *intf, pm_message_t message) 625 { 626 struct usbnet *dev = usb_get_intfdata(intf); 627 struct asix_common_private *priv = dev->driver_priv; 628 629 if (priv && priv->suspend) 630 priv->suspend(dev); 631 632 return usbnet_suspend(intf, message); 633 } 634 635 static void ax88772_restore_phy(struct usbnet *dev) 636 { 637 struct asix_common_private *priv = dev->driver_priv; 638 639 if (priv->presvd_phy_advertise) { 640 /* Restore Advertisement control reg */ 641 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE, 642 priv->presvd_phy_advertise); 643 644 /* Restore BMCR */ 645 if (priv->presvd_phy_bmcr & BMCR_ANENABLE) 646 priv->presvd_phy_bmcr |= BMCR_ANRESTART; 647 648 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_BMCR, 649 priv->presvd_phy_bmcr); 650 651 priv->presvd_phy_advertise = 0; 652 priv->presvd_phy_bmcr = 0; 653 } 654 } 655 656 static void ax88772_resume(struct usbnet *dev) 657 { 658 int i; 659 660 for (i = 0; i < 3; i++) 661 if (!ax88772_hw_reset(dev, 1)) 662 break; 663 ax88772_restore_phy(dev); 664 } 665 666 static void ax88772a_resume(struct usbnet *dev) 667 { 668 int i; 669 670 for (i = 0; i < 3; i++) { 671 if (!ax88772a_hw_reset(dev, 1)) 672 break; 673 } 674 675 ax88772_restore_phy(dev); 676 } 677 678 static int asix_resume(struct usb_interface *intf) 679 { 680 struct usbnet *dev = usb_get_intfdata(intf); 681 struct asix_common_private *priv = dev->driver_priv; 682 683 if (priv && priv->resume) 684 priv->resume(dev); 685 686 return usbnet_resume(intf); 687 } 688 689 static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf) 690 { 691 int ret, i; 692 u8 buf[ETH_ALEN], chipcode = 0; 693 u32 phyid; 694 struct asix_common_private *priv; 695 696 usbnet_get_endpoints(dev, intf); 697 698 /* Maybe the boot loader passed the MAC address via device tree */ 699 if (!eth_platform_get_mac_address(&dev->udev->dev, buf)) { 700 netif_dbg(dev, ifup, dev->net, 701 "MAC address read from device tree"); 702 } else { 703 /* Try getting the MAC address from EEPROM */ 704 if (dev->driver_info->data & FLAG_EEPROM_MAC) { 705 for (i = 0; i < (ETH_ALEN >> 1); i++) { 706 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 707 0x04 + i, 0, 2, buf + i * 2, 708 0); 709 if (ret < 0) 710 break; 711 } 712 } else { 713 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 714 0, 0, ETH_ALEN, buf, 0); 715 } 716 717 if (ret < 0) { 718 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", 719 ret); 720 return ret; 721 } 722 } 723 724 asix_set_netdev_dev_addr(dev, buf); 725 726 /* Initialize MII structure */ 727 dev->mii.dev = dev->net; 728 dev->mii.mdio_read = asix_mdio_read; 729 dev->mii.mdio_write = asix_mdio_write; 730 dev->mii.phy_id_mask = 0x1f; 731 dev->mii.reg_num_mask = 0x1f; 732 dev->mii.phy_id = asix_get_phy_addr(dev); 733 734 dev->net->netdev_ops = &ax88772_netdev_ops; 735 dev->net->ethtool_ops = &ax88772_ethtool_ops; 736 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ 737 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ 738 739 asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 0, 1, &chipcode, 0); 740 chipcode &= AX_CHIPCODE_MASK; 741 742 (chipcode == AX_AX88772_CHIPCODE) ? ax88772_hw_reset(dev, 0) : 743 ax88772a_hw_reset(dev, 0); 744 745 /* Read PHYID register *AFTER* the PHY was reset properly */ 746 phyid = asix_get_phyid(dev); 747 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid); 748 749 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ 750 if (dev->driver_info->flags & FLAG_FRAMING_AX) { 751 /* hard_mtu is still the default - the device does not support 752 jumbo eth frames */ 753 dev->rx_urb_size = 2048; 754 } 755 756 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL); 757 if (!dev->driver_priv) 758 return -ENOMEM; 759 760 priv = dev->driver_priv; 761 762 priv->presvd_phy_bmcr = 0; 763 priv->presvd_phy_advertise = 0; 764 if (chipcode == AX_AX88772_CHIPCODE) { 765 priv->resume = ax88772_resume; 766 priv->suspend = ax88772_suspend; 767 } else { 768 priv->resume = ax88772a_resume; 769 priv->suspend = ax88772_suspend; 770 } 771 772 return 0; 773 } 774 775 static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf) 776 { 777 asix_rx_fixup_common_free(dev->driver_priv); 778 kfree(dev->driver_priv); 779 } 780 781 static const struct ethtool_ops ax88178_ethtool_ops = { 782 .get_drvinfo = asix_get_drvinfo, 783 .get_link = asix_get_link, 784 .get_msglevel = usbnet_get_msglevel, 785 .set_msglevel = usbnet_set_msglevel, 786 .get_wol = asix_get_wol, 787 .set_wol = asix_set_wol, 788 .get_eeprom_len = asix_get_eeprom_len, 789 .get_eeprom = asix_get_eeprom, 790 .set_eeprom = asix_set_eeprom, 791 .nway_reset = usbnet_nway_reset, 792 .get_link_ksettings = usbnet_get_link_ksettings, 793 .set_link_ksettings = usbnet_set_link_ksettings, 794 }; 795 796 static int marvell_phy_init(struct usbnet *dev) 797 { 798 struct asix_data *data = (struct asix_data *)&dev->data; 799 u16 reg; 800 801 netdev_dbg(dev->net, "marvell_phy_init()\n"); 802 803 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS); 804 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg); 805 806 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL, 807 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY); 808 809 if (data->ledmode) { 810 reg = asix_mdio_read(dev->net, dev->mii.phy_id, 811 MII_MARVELL_LED_CTRL); 812 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg); 813 814 reg &= 0xf8ff; 815 reg |= (1 + 0x0100); 816 asix_mdio_write(dev->net, dev->mii.phy_id, 817 MII_MARVELL_LED_CTRL, reg); 818 819 reg = asix_mdio_read(dev->net, dev->mii.phy_id, 820 MII_MARVELL_LED_CTRL); 821 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg); 822 reg &= 0xfc0f; 823 } 824 825 return 0; 826 } 827 828 static int rtl8211cl_phy_init(struct usbnet *dev) 829 { 830 struct asix_data *data = (struct asix_data *)&dev->data; 831 832 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n"); 833 834 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005); 835 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0); 836 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01, 837 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080); 838 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); 839 840 if (data->ledmode == 12) { 841 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002); 842 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb); 843 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); 844 } 845 846 return 0; 847 } 848 849 static int marvell_led_status(struct usbnet *dev, u16 speed) 850 { 851 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL); 852 853 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg); 854 855 /* Clear out the center LED bits - 0x03F0 */ 856 reg &= 0xfc0f; 857 858 switch (speed) { 859 case SPEED_1000: 860 reg |= 0x03e0; 861 break; 862 case SPEED_100: 863 reg |= 0x03b0; 864 break; 865 default: 866 reg |= 0x02f0; 867 } 868 869 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg); 870 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg); 871 872 return 0; 873 } 874 875 static int ax88178_reset(struct usbnet *dev) 876 { 877 struct asix_data *data = (struct asix_data *)&dev->data; 878 int ret; 879 __le16 eeprom; 880 u8 status; 881 int gpio0 = 0; 882 u32 phyid; 883 884 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status, 0); 885 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status); 886 887 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL, 0); 888 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom, 0); 889 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL, 0); 890 891 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom); 892 893 if (eeprom == cpu_to_le16(0xffff)) { 894 data->phymode = PHY_MODE_MARVELL; 895 data->ledmode = 0; 896 gpio0 = 1; 897 } else { 898 data->phymode = le16_to_cpu(eeprom) & 0x7F; 899 data->ledmode = le16_to_cpu(eeprom) >> 8; 900 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1; 901 } 902 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode); 903 904 /* Power up external GigaPHY through AX88178 GPIO pin */ 905 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | 906 AX_GPIO_GPO1EN, 40, 0); 907 if ((le16_to_cpu(eeprom) >> 8) != 1) { 908 asix_write_gpio(dev, 0x003c, 30, 0); 909 asix_write_gpio(dev, 0x001c, 300, 0); 910 asix_write_gpio(dev, 0x003c, 30, 0); 911 } else { 912 netdev_dbg(dev->net, "gpio phymode == 1 path\n"); 913 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30, 0); 914 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30, 0); 915 } 916 917 /* Read PHYID register *AFTER* powering up PHY */ 918 phyid = asix_get_phyid(dev); 919 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid); 920 921 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */ 922 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL, 0); 923 924 asix_sw_reset(dev, 0, 0); 925 msleep(150); 926 927 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0); 928 msleep(150); 929 930 asix_write_rx_ctl(dev, 0, 0); 931 932 if (data->phymode == PHY_MODE_MARVELL) { 933 marvell_phy_init(dev); 934 msleep(60); 935 } else if (data->phymode == PHY_MODE_RTL8211CL) 936 rtl8211cl_phy_init(dev); 937 938 asix_phy_reset(dev, BMCR_RESET | BMCR_ANENABLE); 939 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 940 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); 941 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000, 942 ADVERTISE_1000FULL); 943 944 asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT, 0); 945 mii_nway_restart(&dev->mii); 946 947 /* Rewrite MAC address */ 948 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); 949 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, 950 data->mac_addr, 0); 951 if (ret < 0) 952 return ret; 953 954 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0); 955 if (ret < 0) 956 return ret; 957 958 return 0; 959 } 960 961 static int ax88178_link_reset(struct usbnet *dev) 962 { 963 u16 mode; 964 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 965 struct asix_data *data = (struct asix_data *)&dev->data; 966 u32 speed; 967 968 netdev_dbg(dev->net, "ax88178_link_reset()\n"); 969 970 mii_check_media(&dev->mii, 1, 1); 971 mii_ethtool_gset(&dev->mii, &ecmd); 972 mode = AX88178_MEDIUM_DEFAULT; 973 speed = ethtool_cmd_speed(&ecmd); 974 975 if (speed == SPEED_1000) 976 mode |= AX_MEDIUM_GM; 977 else if (speed == SPEED_100) 978 mode |= AX_MEDIUM_PS; 979 else 980 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM); 981 982 mode |= AX_MEDIUM_ENCK; 983 984 if (ecmd.duplex == DUPLEX_FULL) 985 mode |= AX_MEDIUM_FD; 986 else 987 mode &= ~AX_MEDIUM_FD; 988 989 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 990 speed, ecmd.duplex, mode); 991 992 asix_write_medium_mode(dev, mode, 0); 993 994 if (data->phymode == PHY_MODE_MARVELL && data->ledmode) 995 marvell_led_status(dev, speed); 996 997 return 0; 998 } 999 1000 static void ax88178_set_mfb(struct usbnet *dev) 1001 { 1002 u16 mfb = AX_RX_CTL_MFB_16384; 1003 u16 rxctl; 1004 u16 medium; 1005 int old_rx_urb_size = dev->rx_urb_size; 1006 1007 if (dev->hard_mtu < 2048) { 1008 dev->rx_urb_size = 2048; 1009 mfb = AX_RX_CTL_MFB_2048; 1010 } else if (dev->hard_mtu < 4096) { 1011 dev->rx_urb_size = 4096; 1012 mfb = AX_RX_CTL_MFB_4096; 1013 } else if (dev->hard_mtu < 8192) { 1014 dev->rx_urb_size = 8192; 1015 mfb = AX_RX_CTL_MFB_8192; 1016 } else if (dev->hard_mtu < 16384) { 1017 dev->rx_urb_size = 16384; 1018 mfb = AX_RX_CTL_MFB_16384; 1019 } 1020 1021 rxctl = asix_read_rx_ctl(dev, 0); 1022 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb, 0); 1023 1024 medium = asix_read_medium_status(dev, 0); 1025 if (dev->net->mtu > 1500) 1026 medium |= AX_MEDIUM_JFE; 1027 else 1028 medium &= ~AX_MEDIUM_JFE; 1029 asix_write_medium_mode(dev, medium, 0); 1030 1031 if (dev->rx_urb_size > old_rx_urb_size) 1032 usbnet_unlink_rx_urbs(dev); 1033 } 1034 1035 static int ax88178_change_mtu(struct net_device *net, int new_mtu) 1036 { 1037 struct usbnet *dev = netdev_priv(net); 1038 int ll_mtu = new_mtu + net->hard_header_len + 4; 1039 1040 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu); 1041 1042 if ((ll_mtu % dev->maxpacket) == 0) 1043 return -EDOM; 1044 1045 net->mtu = new_mtu; 1046 dev->hard_mtu = net->mtu + net->hard_header_len; 1047 ax88178_set_mfb(dev); 1048 1049 /* max qlen depend on hard_mtu and rx_urb_size */ 1050 usbnet_update_max_qlen(dev); 1051 1052 return 0; 1053 } 1054 1055 static const struct net_device_ops ax88178_netdev_ops = { 1056 .ndo_open = usbnet_open, 1057 .ndo_stop = usbnet_stop, 1058 .ndo_start_xmit = usbnet_start_xmit, 1059 .ndo_tx_timeout = usbnet_tx_timeout, 1060 .ndo_get_stats64 = usbnet_get_stats64, 1061 .ndo_set_mac_address = asix_set_mac_address, 1062 .ndo_validate_addr = eth_validate_addr, 1063 .ndo_set_rx_mode = asix_set_multicast, 1064 .ndo_do_ioctl = asix_ioctl, 1065 .ndo_change_mtu = ax88178_change_mtu, 1066 }; 1067 1068 static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf) 1069 { 1070 int ret; 1071 u8 buf[ETH_ALEN]; 1072 1073 usbnet_get_endpoints(dev,intf); 1074 1075 /* Get the MAC address */ 1076 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf, 0); 1077 if (ret < 0) { 1078 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret); 1079 return ret; 1080 } 1081 1082 asix_set_netdev_dev_addr(dev, buf); 1083 1084 /* Initialize MII structure */ 1085 dev->mii.dev = dev->net; 1086 dev->mii.mdio_read = asix_mdio_read; 1087 dev->mii.mdio_write = asix_mdio_write; 1088 dev->mii.phy_id_mask = 0x1f; 1089 dev->mii.reg_num_mask = 0xff; 1090 dev->mii.supports_gmii = 1; 1091 dev->mii.phy_id = asix_get_phy_addr(dev); 1092 1093 dev->net->netdev_ops = &ax88178_netdev_ops; 1094 dev->net->ethtool_ops = &ax88178_ethtool_ops; 1095 dev->net->max_mtu = 16384 - (dev->net->hard_header_len + 4); 1096 1097 /* Blink LEDS so users know driver saw dongle */ 1098 asix_sw_reset(dev, 0, 0); 1099 msleep(150); 1100 1101 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0); 1102 msleep(150); 1103 1104 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ 1105 if (dev->driver_info->flags & FLAG_FRAMING_AX) { 1106 /* hard_mtu is still the default - the device does not support 1107 jumbo eth frames */ 1108 dev->rx_urb_size = 2048; 1109 } 1110 1111 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL); 1112 if (!dev->driver_priv) 1113 return -ENOMEM; 1114 1115 return 0; 1116 } 1117 1118 static const struct driver_info ax8817x_info = { 1119 .description = "ASIX AX8817x USB 2.0 Ethernet", 1120 .bind = ax88172_bind, 1121 .status = asix_status, 1122 .link_reset = ax88172_link_reset, 1123 .reset = ax88172_link_reset, 1124 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1125 .data = 0x00130103, 1126 }; 1127 1128 static const struct driver_info dlink_dub_e100_info = { 1129 .description = "DLink DUB-E100 USB Ethernet", 1130 .bind = ax88172_bind, 1131 .status = asix_status, 1132 .link_reset = ax88172_link_reset, 1133 .reset = ax88172_link_reset, 1134 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1135 .data = 0x009f9d9f, 1136 }; 1137 1138 static const struct driver_info netgear_fa120_info = { 1139 .description = "Netgear FA-120 USB Ethernet", 1140 .bind = ax88172_bind, 1141 .status = asix_status, 1142 .link_reset = ax88172_link_reset, 1143 .reset = ax88172_link_reset, 1144 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1145 .data = 0x00130103, 1146 }; 1147 1148 static const struct driver_info hawking_uf200_info = { 1149 .description = "Hawking UF200 USB Ethernet", 1150 .bind = ax88172_bind, 1151 .status = asix_status, 1152 .link_reset = ax88172_link_reset, 1153 .reset = ax88172_link_reset, 1154 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1155 .data = 0x001f1d1f, 1156 }; 1157 1158 static const struct driver_info ax88772_info = { 1159 .description = "ASIX AX88772 USB 2.0 Ethernet", 1160 .bind = ax88772_bind, 1161 .unbind = ax88772_unbind, 1162 .status = asix_status, 1163 .link_reset = ax88772_link_reset, 1164 .reset = ax88772_reset, 1165 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET, 1166 .rx_fixup = asix_rx_fixup_common, 1167 .tx_fixup = asix_tx_fixup, 1168 }; 1169 1170 static const struct driver_info ax88772b_info = { 1171 .description = "ASIX AX88772B USB 2.0 Ethernet", 1172 .bind = ax88772_bind, 1173 .unbind = ax88772_unbind, 1174 .status = asix_status, 1175 .link_reset = ax88772_link_reset, 1176 .reset = ax88772_reset, 1177 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | 1178 FLAG_MULTI_PACKET, 1179 .rx_fixup = asix_rx_fixup_common, 1180 .tx_fixup = asix_tx_fixup, 1181 .data = FLAG_EEPROM_MAC, 1182 }; 1183 1184 static const struct driver_info ax88178_info = { 1185 .description = "ASIX AX88178 USB 2.0 Ethernet", 1186 .bind = ax88178_bind, 1187 .unbind = ax88772_unbind, 1188 .status = asix_status, 1189 .link_reset = ax88178_link_reset, 1190 .reset = ax88178_reset, 1191 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | 1192 FLAG_MULTI_PACKET, 1193 .rx_fixup = asix_rx_fixup_common, 1194 .tx_fixup = asix_tx_fixup, 1195 }; 1196 1197 /* 1198 * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in 1199 * no-name packaging. 1200 * USB device strings are: 1201 * 1: Manufacturer: USBLINK 1202 * 2: Product: HG20F9 USB2.0 1203 * 3: Serial: 000003 1204 * Appears to be compatible with Asix 88772B. 1205 */ 1206 static const struct driver_info hg20f9_info = { 1207 .description = "HG20F9 USB 2.0 Ethernet", 1208 .bind = ax88772_bind, 1209 .unbind = ax88772_unbind, 1210 .status = asix_status, 1211 .link_reset = ax88772_link_reset, 1212 .reset = ax88772_reset, 1213 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | 1214 FLAG_MULTI_PACKET, 1215 .rx_fixup = asix_rx_fixup_common, 1216 .tx_fixup = asix_tx_fixup, 1217 .data = FLAG_EEPROM_MAC, 1218 }; 1219 1220 static const struct usb_device_id products [] = { 1221 { 1222 // Linksys USB200M 1223 USB_DEVICE (0x077b, 0x2226), 1224 .driver_info = (unsigned long) &ax8817x_info, 1225 }, { 1226 // Netgear FA120 1227 USB_DEVICE (0x0846, 0x1040), 1228 .driver_info = (unsigned long) &netgear_fa120_info, 1229 }, { 1230 // DLink DUB-E100 1231 USB_DEVICE (0x2001, 0x1a00), 1232 .driver_info = (unsigned long) &dlink_dub_e100_info, 1233 }, { 1234 // Intellinet, ST Lab USB Ethernet 1235 USB_DEVICE (0x0b95, 0x1720), 1236 .driver_info = (unsigned long) &ax8817x_info, 1237 }, { 1238 // Hawking UF200, TrendNet TU2-ET100 1239 USB_DEVICE (0x07b8, 0x420a), 1240 .driver_info = (unsigned long) &hawking_uf200_info, 1241 }, { 1242 // Billionton Systems, USB2AR 1243 USB_DEVICE (0x08dd, 0x90ff), 1244 .driver_info = (unsigned long) &ax8817x_info, 1245 }, { 1246 // Billionton Systems, GUSB2AM-1G-B 1247 USB_DEVICE(0x08dd, 0x0114), 1248 .driver_info = (unsigned long) &ax88178_info, 1249 }, { 1250 // ATEN UC210T 1251 USB_DEVICE (0x0557, 0x2009), 1252 .driver_info = (unsigned long) &ax8817x_info, 1253 }, { 1254 // Buffalo LUA-U2-KTX 1255 USB_DEVICE (0x0411, 0x003d), 1256 .driver_info = (unsigned long) &ax8817x_info, 1257 }, { 1258 // Buffalo LUA-U2-GT 10/100/1000 1259 USB_DEVICE (0x0411, 0x006e), 1260 .driver_info = (unsigned long) &ax88178_info, 1261 }, { 1262 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter" 1263 USB_DEVICE (0x6189, 0x182d), 1264 .driver_info = (unsigned long) &ax8817x_info, 1265 }, { 1266 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter" 1267 USB_DEVICE (0x0df6, 0x0056), 1268 .driver_info = (unsigned long) &ax88178_info, 1269 }, { 1270 // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter" 1271 USB_DEVICE (0x0df6, 0x061c), 1272 .driver_info = (unsigned long) &ax88178_info, 1273 }, { 1274 // corega FEther USB2-TX 1275 USB_DEVICE (0x07aa, 0x0017), 1276 .driver_info = (unsigned long) &ax8817x_info, 1277 }, { 1278 // Surecom EP-1427X-2 1279 USB_DEVICE (0x1189, 0x0893), 1280 .driver_info = (unsigned long) &ax8817x_info, 1281 }, { 1282 // goodway corp usb gwusb2e 1283 USB_DEVICE (0x1631, 0x6200), 1284 .driver_info = (unsigned long) &ax8817x_info, 1285 }, { 1286 // JVC MP-PRX1 Port Replicator 1287 USB_DEVICE (0x04f1, 0x3008), 1288 .driver_info = (unsigned long) &ax8817x_info, 1289 }, { 1290 // Lenovo U2L100P 10/100 1291 USB_DEVICE (0x17ef, 0x7203), 1292 .driver_info = (unsigned long)&ax88772b_info, 1293 }, { 1294 // ASIX AX88772B 10/100 1295 USB_DEVICE (0x0b95, 0x772b), 1296 .driver_info = (unsigned long) &ax88772b_info, 1297 }, { 1298 // ASIX AX88772 10/100 1299 USB_DEVICE (0x0b95, 0x7720), 1300 .driver_info = (unsigned long) &ax88772_info, 1301 }, { 1302 // ASIX AX88178 10/100/1000 1303 USB_DEVICE (0x0b95, 0x1780), 1304 .driver_info = (unsigned long) &ax88178_info, 1305 }, { 1306 // Logitec LAN-GTJ/U2A 1307 USB_DEVICE (0x0789, 0x0160), 1308 .driver_info = (unsigned long) &ax88178_info, 1309 }, { 1310 // Linksys USB200M Rev 2 1311 USB_DEVICE (0x13b1, 0x0018), 1312 .driver_info = (unsigned long) &ax88772_info, 1313 }, { 1314 // 0Q0 cable ethernet 1315 USB_DEVICE (0x1557, 0x7720), 1316 .driver_info = (unsigned long) &ax88772_info, 1317 }, { 1318 // DLink DUB-E100 H/W Ver B1 1319 USB_DEVICE (0x07d1, 0x3c05), 1320 .driver_info = (unsigned long) &ax88772_info, 1321 }, { 1322 // DLink DUB-E100 H/W Ver B1 Alternate 1323 USB_DEVICE (0x2001, 0x3c05), 1324 .driver_info = (unsigned long) &ax88772_info, 1325 }, { 1326 // DLink DUB-E100 H/W Ver C1 1327 USB_DEVICE (0x2001, 0x1a02), 1328 .driver_info = (unsigned long) &ax88772_info, 1329 }, { 1330 // Linksys USB1000 1331 USB_DEVICE (0x1737, 0x0039), 1332 .driver_info = (unsigned long) &ax88178_info, 1333 }, { 1334 // IO-DATA ETG-US2 1335 USB_DEVICE (0x04bb, 0x0930), 1336 .driver_info = (unsigned long) &ax88178_info, 1337 }, { 1338 // Belkin F5D5055 1339 USB_DEVICE(0x050d, 0x5055), 1340 .driver_info = (unsigned long) &ax88178_info, 1341 }, { 1342 // Apple USB Ethernet Adapter 1343 USB_DEVICE(0x05ac, 0x1402), 1344 .driver_info = (unsigned long) &ax88772_info, 1345 }, { 1346 // Cables-to-Go USB Ethernet Adapter 1347 USB_DEVICE(0x0b95, 0x772a), 1348 .driver_info = (unsigned long) &ax88772_info, 1349 }, { 1350 // ABOCOM for pci 1351 USB_DEVICE(0x14ea, 0xab11), 1352 .driver_info = (unsigned long) &ax88178_info, 1353 }, { 1354 // ASIX 88772a 1355 USB_DEVICE(0x0db0, 0xa877), 1356 .driver_info = (unsigned long) &ax88772_info, 1357 }, { 1358 // Asus USB Ethernet Adapter 1359 USB_DEVICE (0x0b95, 0x7e2b), 1360 .driver_info = (unsigned long)&ax88772b_info, 1361 }, { 1362 /* ASIX 88172a demo board */ 1363 USB_DEVICE(0x0b95, 0x172a), 1364 .driver_info = (unsigned long) &ax88172a_info, 1365 }, { 1366 /* 1367 * USBLINK HG20F9 "USB 2.0 LAN" 1368 * Appears to have gazumped Linksys's manufacturer ID but 1369 * doesn't (yet) conflict with any known Linksys product. 1370 */ 1371 USB_DEVICE(0x066b, 0x20f9), 1372 .driver_info = (unsigned long) &hg20f9_info, 1373 }, 1374 { }, // END 1375 }; 1376 MODULE_DEVICE_TABLE(usb, products); 1377 1378 static struct usb_driver asix_driver = { 1379 .name = DRIVER_NAME, 1380 .id_table = products, 1381 .probe = usbnet_probe, 1382 .suspend = asix_suspend, 1383 .resume = asix_resume, 1384 .reset_resume = asix_resume, 1385 .disconnect = usbnet_disconnect, 1386 .supports_autosuspend = 1, 1387 .disable_hub_initiated_lpm = 1, 1388 }; 1389 1390 module_usb_driver(asix_driver); 1391 1392 MODULE_AUTHOR("David Hollis"); 1393 MODULE_VERSION(DRIVER_VERSION); 1394 MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices"); 1395 MODULE_LICENSE("GPL"); 1396 1397