1619fcb44SDmitry Bezrukov /* SPDX-License-Identifier: GPL-2.0-or-later 2619fcb44SDmitry Bezrukov * Aquantia Corp. Aquantia AQtion USB to 5GbE Controller 3619fcb44SDmitry Bezrukov * Copyright (C) 2003-2005 David Hollis <dhollis@davehollis.com> 4619fcb44SDmitry Bezrukov * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> 5619fcb44SDmitry Bezrukov * Copyright (C) 2002-2003 TiVo Inc. 6619fcb44SDmitry Bezrukov * Copyright (C) 2017-2018 ASIX 7619fcb44SDmitry Bezrukov * Copyright (C) 2018 Aquantia Corp. 8619fcb44SDmitry Bezrukov */ 9619fcb44SDmitry Bezrukov 10619fcb44SDmitry Bezrukov #ifndef __LINUX_USBNET_AQC111_H 11619fcb44SDmitry Bezrukov #define __LINUX_USBNET_AQC111_H 12619fcb44SDmitry Bezrukov 13361459cdSDmitry Bezrukov #define URB_SIZE (1024 * 62) 14361459cdSDmitry Bezrukov 1559b04eeaSDmitry Bezrukov #define AQ_MCAST_FILTER_SIZE 8 1659b04eeaSDmitry Bezrukov #define AQ_MAX_MCAST 64 1759b04eeaSDmitry Bezrukov 18f3aa095aSDmitry Bezrukov #define AQ_ACCESS_MAC 0x01 19df2d59a2SDmitry Bezrukov #define AQ_FLASH_PARAMETERS 0x20 20619fcb44SDmitry Bezrukov #define AQ_PHY_POWER 0x31 2133cd597fSDmitry Bezrukov #define AQ_PHY_OPS 0x61 22619fcb44SDmitry Bezrukov 23619fcb44SDmitry Bezrukov #define AQ_USB_PHY_SET_TIMEOUT 10000 24619fcb44SDmitry Bezrukov #define AQ_USB_SET_TIMEOUT 4000 25619fcb44SDmitry Bezrukov 264a3576d2SDmitry Bezrukov /* Feature. ********************************************/ 2702031466SDmitry Bezrukov #define AQ_SUPPORT_FEATURE (NETIF_F_SG | NETIF_F_IP_CSUM |\ 28de074e7aSDmitry Bezrukov NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |\ 29de074e7aSDmitry Bezrukov NETIF_F_TSO) 3002031466SDmitry Bezrukov 3102031466SDmitry Bezrukov #define AQ_SUPPORT_HW_FEATURE (NETIF_F_SG | NETIF_F_IP_CSUM |\ 32de074e7aSDmitry Bezrukov NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |\ 33de074e7aSDmitry Bezrukov NETIF_F_TSO) 344a3576d2SDmitry Bezrukov 35f3aa095aSDmitry Bezrukov /* SFR Reg. ********************************************/ 36f3aa095aSDmitry Bezrukov 37f3aa095aSDmitry Bezrukov #define SFR_GENERAL_STATUS 0x03 38f3aa095aSDmitry Bezrukov #define SFR_CHIP_STATUS 0x05 39f3aa095aSDmitry Bezrukov #define SFR_RX_CTL 0x0B 40f3aa095aSDmitry Bezrukov #define SFR_RX_CTL_TXPADCRC 0x0400 41f3aa095aSDmitry Bezrukov #define SFR_RX_CTL_IPE 0x0200 42f3aa095aSDmitry Bezrukov #define SFR_RX_CTL_DROPCRCERR 0x0100 43f3aa095aSDmitry Bezrukov #define SFR_RX_CTL_START 0x0080 44f3aa095aSDmitry Bezrukov #define SFR_RX_CTL_RF_WAK 0x0040 45f3aa095aSDmitry Bezrukov #define SFR_RX_CTL_AP 0x0020 46f3aa095aSDmitry Bezrukov #define SFR_RX_CTL_AM 0x0010 47f3aa095aSDmitry Bezrukov #define SFR_RX_CTL_AB 0x0008 48f3aa095aSDmitry Bezrukov #define SFR_RX_CTL_AMALL 0x0002 49f3aa095aSDmitry Bezrukov #define SFR_RX_CTL_PRO 0x0001 50f3aa095aSDmitry Bezrukov #define SFR_RX_CTL_STOP 0x0000 51f3aa095aSDmitry Bezrukov #define SFR_INTER_PACKET_GAP_0 0x0D 52f3aa095aSDmitry Bezrukov #define SFR_NODE_ID 0x10 53f3aa095aSDmitry Bezrukov #define SFR_MULTI_FILTER_ARRY 0x16 54f3aa095aSDmitry Bezrukov #define SFR_MEDIUM_STATUS_MODE 0x22 55f3aa095aSDmitry Bezrukov #define SFR_MEDIUM_XGMIIMODE 0x0001 56f3aa095aSDmitry Bezrukov #define SFR_MEDIUM_FULL_DUPLEX 0x0002 57f3aa095aSDmitry Bezrukov #define SFR_MEDIUM_RXFLOW_CTRLEN 0x0010 58f3aa095aSDmitry Bezrukov #define SFR_MEDIUM_TXFLOW_CTRLEN 0x0020 59f3aa095aSDmitry Bezrukov #define SFR_MEDIUM_JUMBO_EN 0x0040 60f3aa095aSDmitry Bezrukov #define SFR_MEDIUM_RECEIVE_EN 0x0100 61f3aa095aSDmitry Bezrukov #define SFR_MONITOR_MODE 0x24 62f3aa095aSDmitry Bezrukov #define SFR_MONITOR_MODE_EPHYRW 0x01 63f3aa095aSDmitry Bezrukov #define SFR_MONITOR_MODE_RWLC 0x02 64f3aa095aSDmitry Bezrukov #define SFR_MONITOR_MODE_RWMP 0x04 65f3aa095aSDmitry Bezrukov #define SFR_MONITOR_MODE_RWWF 0x08 66f3aa095aSDmitry Bezrukov #define SFR_MONITOR_MODE_RW_FLAG 0x10 67f3aa095aSDmitry Bezrukov #define SFR_MONITOR_MODE_PMEPOL 0x20 68f3aa095aSDmitry Bezrukov #define SFR_MONITOR_MODE_PMETYPE 0x40 69f3aa095aSDmitry Bezrukov #define SFR_PHYPWR_RSTCTL 0x26 70f3aa095aSDmitry Bezrukov #define SFR_PHYPWR_RSTCTL_BZ 0x0010 71f3aa095aSDmitry Bezrukov #define SFR_PHYPWR_RSTCTL_IPRL 0x0020 72f3aa095aSDmitry Bezrukov #define SFR_VLAN_ID_ADDRESS 0x2A 73f3aa095aSDmitry Bezrukov #define SFR_VLAN_ID_CONTROL 0x2B 74f3aa095aSDmitry Bezrukov #define SFR_VLAN_CONTROL_WE 0x0001 75f3aa095aSDmitry Bezrukov #define SFR_VLAN_CONTROL_RD 0x0002 76f3aa095aSDmitry Bezrukov #define SFR_VLAN_CONTROL_VSO 0x0010 77f3aa095aSDmitry Bezrukov #define SFR_VLAN_CONTROL_VFE 0x0020 78f3aa095aSDmitry Bezrukov #define SFR_VLAN_ID_DATA0 0x2C 79f3aa095aSDmitry Bezrukov #define SFR_VLAN_ID_DATA1 0x2D 80f3aa095aSDmitry Bezrukov #define SFR_RX_BULKIN_QCTRL 0x2E 81f3aa095aSDmitry Bezrukov #define SFR_RX_BULKIN_QCTRL_TIME 0x01 82f3aa095aSDmitry Bezrukov #define SFR_RX_BULKIN_QCTRL_IFG 0x02 83f3aa095aSDmitry Bezrukov #define SFR_RX_BULKIN_QCTRL_SIZE 0x04 84f3aa095aSDmitry Bezrukov #define SFR_RX_BULKIN_QTIMR_LOW 0x2F 85f3aa095aSDmitry Bezrukov #define SFR_RX_BULKIN_QTIMR_HIGH 0x30 86f3aa095aSDmitry Bezrukov #define SFR_RX_BULKIN_QSIZE 0x31 87f3aa095aSDmitry Bezrukov #define SFR_RX_BULKIN_QIFG 0x32 88f3aa095aSDmitry Bezrukov #define SFR_RXCOE_CTL 0x34 89f3aa095aSDmitry Bezrukov #define SFR_RXCOE_IP 0x01 90f3aa095aSDmitry Bezrukov #define SFR_RXCOE_TCP 0x02 91f3aa095aSDmitry Bezrukov #define SFR_RXCOE_UDP 0x04 92f3aa095aSDmitry Bezrukov #define SFR_RXCOE_ICMP 0x08 93f3aa095aSDmitry Bezrukov #define SFR_RXCOE_IGMP 0x10 94f3aa095aSDmitry Bezrukov #define SFR_RXCOE_TCPV6 0x20 95f3aa095aSDmitry Bezrukov #define SFR_RXCOE_UDPV6 0x40 96f3aa095aSDmitry Bezrukov #define SFR_RXCOE_ICMV6 0x80 97f3aa095aSDmitry Bezrukov #define SFR_TXCOE_CTL 0x35 98f3aa095aSDmitry Bezrukov #define SFR_TXCOE_IP 0x01 99f3aa095aSDmitry Bezrukov #define SFR_TXCOE_TCP 0x02 100f3aa095aSDmitry Bezrukov #define SFR_TXCOE_UDP 0x04 101f3aa095aSDmitry Bezrukov #define SFR_TXCOE_ICMP 0x08 102f3aa095aSDmitry Bezrukov #define SFR_TXCOE_IGMP 0x10 103f3aa095aSDmitry Bezrukov #define SFR_TXCOE_TCPV6 0x20 104f3aa095aSDmitry Bezrukov #define SFR_TXCOE_UDPV6 0x40 105f3aa095aSDmitry Bezrukov #define SFR_TXCOE_ICMV6 0x80 106f3aa095aSDmitry Bezrukov #define SFR_BM_INT_MASK 0x41 107f3aa095aSDmitry Bezrukov #define SFR_BMRX_DMA_CONTROL 0x43 108f3aa095aSDmitry Bezrukov #define SFR_BMRX_DMA_EN 0x80 109f3aa095aSDmitry Bezrukov #define SFR_BMTX_DMA_CONTROL 0x46 110f3aa095aSDmitry Bezrukov #define SFR_PAUSE_WATERLVL_LOW 0x54 111f3aa095aSDmitry Bezrukov #define SFR_PAUSE_WATERLVL_HIGH 0x55 112f3aa095aSDmitry Bezrukov #define SFR_ARC_CTRL 0x9E 113f3aa095aSDmitry Bezrukov #define SFR_SWP_CTRL 0xB1 114f3aa095aSDmitry Bezrukov #define SFR_TX_PAUSE_RESEND_T 0xB2 115f3aa095aSDmitry Bezrukov #define SFR_ETH_MAC_PATH 0xB7 116f3aa095aSDmitry Bezrukov #define SFR_RX_PATH_READY 0x01 117f3aa095aSDmitry Bezrukov #define SFR_BULK_OUT_CTRL 0xB9 118f3aa095aSDmitry Bezrukov #define SFR_BULK_OUT_FLUSH_EN 0x01 119f3aa095aSDmitry Bezrukov #define SFR_BULK_OUT_EFF_EN 0x02 120f3aa095aSDmitry Bezrukov 12133cd597fSDmitry Bezrukov #define AQ_FW_VER_MAJOR 0xDA 12233cd597fSDmitry Bezrukov #define AQ_FW_VER_MINOR 0xDB 12333cd597fSDmitry Bezrukov #define AQ_FW_VER_REV 0xDC 12433cd597fSDmitry Bezrukov 12533cd597fSDmitry Bezrukov /*PHY_OPS**********************************************************************/ 12633cd597fSDmitry Bezrukov 12733cd597fSDmitry Bezrukov #define AQ_ADV_100M BIT(0) 12833cd597fSDmitry Bezrukov #define AQ_ADV_1G BIT(1) 12933cd597fSDmitry Bezrukov #define AQ_ADV_2G5 BIT(2) 13033cd597fSDmitry Bezrukov #define AQ_ADV_5G BIT(3) 1317b8b0654SDmitry Bezrukov #define AQ_ADV_MASK 0x0F 13233cd597fSDmitry Bezrukov 13333cd597fSDmitry Bezrukov #define AQ_PAUSE BIT(16) 13433cd597fSDmitry Bezrukov #define AQ_ASYM_PAUSE BIT(17) 13533cd597fSDmitry Bezrukov #define AQ_LOW_POWER BIT(18) 13633cd597fSDmitry Bezrukov #define AQ_PHY_POWER_EN BIT(19) 13733cd597fSDmitry Bezrukov #define AQ_WOL BIT(20) 13833cd597fSDmitry Bezrukov #define AQ_DOWNSHIFT BIT(21) 13933cd597fSDmitry Bezrukov 14033cd597fSDmitry Bezrukov #define AQ_DSH_RETRIES_SHIFT 0x18 14133cd597fSDmitry Bezrukov #define AQ_DSH_RETRIES_MASK 0xF000000 14233cd597fSDmitry Bezrukov 14333cd597fSDmitry Bezrukov /******************************************************************************/ 14433cd597fSDmitry Bezrukov 14533cd597fSDmitry Bezrukov struct aqc111_data { 14659b04eeaSDmitry Bezrukov u16 rxctl; 1476649d2a6SDmitry Bezrukov u8 rx_checksum; 1487b8b0654SDmitry Bezrukov u8 link_speed; 1497b8b0654SDmitry Bezrukov u8 link; 1507b8b0654SDmitry Bezrukov u8 autoneg; 1517b8b0654SDmitry Bezrukov u32 advertised_speed; 15233cd597fSDmitry Bezrukov struct { 15333cd597fSDmitry Bezrukov u8 major; 15433cd597fSDmitry Bezrukov u8 minor; 15533cd597fSDmitry Bezrukov u8 rev; 15633cd597fSDmitry Bezrukov } fw_ver; 15733cd597fSDmitry Bezrukov u32 phy_cfg; 15833cd597fSDmitry Bezrukov }; 15933cd597fSDmitry Bezrukov 1607b8b0654SDmitry Bezrukov #define AQ_LS_MASK 0x8000 1617b8b0654SDmitry Bezrukov #define AQ_SPEED_MASK 0x7F00 1627b8b0654SDmitry Bezrukov #define AQ_SPEED_SHIFT 0x0008 1637b8b0654SDmitry Bezrukov #define AQ_INT_SPEED_5G 0x000F 1647b8b0654SDmitry Bezrukov #define AQ_INT_SPEED_2_5G 0x0010 1657b8b0654SDmitry Bezrukov #define AQ_INT_SPEED_1G 0x0011 1667b8b0654SDmitry Bezrukov #define AQ_INT_SPEED_100M 0x0013 1677b8b0654SDmitry Bezrukov 1684a3576d2SDmitry Bezrukov /* TX Descriptor */ 1694a3576d2SDmitry Bezrukov #define AQ_TX_DESC_LEN_MASK 0x1FFFFF 1704a3576d2SDmitry Bezrukov #define AQ_TX_DESC_DROP_PADD BIT(28) 171de074e7aSDmitry Bezrukov #define AQ_TX_DESC_MSS_MASK 0x7FFF 172de074e7aSDmitry Bezrukov #define AQ_TX_DESC_MSS_SHIFT 0x20 1734a3576d2SDmitry Bezrukov 174361459cdSDmitry Bezrukov #define AQ_RX_HW_PAD 0x02 175361459cdSDmitry Bezrukov 176361459cdSDmitry Bezrukov /* RX Packet Descriptor */ 17702031466SDmitry Bezrukov #define AQ_RX_PD_L4_ERR BIT(0) 17802031466SDmitry Bezrukov #define AQ_RX_PD_L3_ERR BIT(1) 17902031466SDmitry Bezrukov #define AQ_RX_PD_L4_TYPE_MASK 0x1C 18002031466SDmitry Bezrukov #define AQ_RX_PD_L4_UDP 0x04 18102031466SDmitry Bezrukov #define AQ_RX_PD_L4_TCP 0x10 18202031466SDmitry Bezrukov #define AQ_RX_PD_L3_TYPE_MASK 0x60 18302031466SDmitry Bezrukov #define AQ_RX_PD_L3_IP 0x20 18402031466SDmitry Bezrukov #define AQ_RX_PD_L3_IP6 0x40 18502031466SDmitry Bezrukov 186361459cdSDmitry Bezrukov #define AQ_RX_PD_RX_OK BIT(11) 187361459cdSDmitry Bezrukov #define AQ_RX_PD_DROP BIT(31) 188361459cdSDmitry Bezrukov #define AQ_RX_PD_LEN_MASK 0x7FFF0000 189361459cdSDmitry Bezrukov #define AQ_RX_PD_LEN_SHIFT 0x10 190361459cdSDmitry Bezrukov 191361459cdSDmitry Bezrukov /* RX Descriptor header */ 192361459cdSDmitry Bezrukov #define AQ_RX_DH_PKT_CNT_MASK 0x1FFF 193361459cdSDmitry Bezrukov #define AQ_RX_DH_DESC_OFFSET_MASK 0xFFFFE000 194361459cdSDmitry Bezrukov #define AQ_RX_DH_DESC_OFFSET_SHIFT 0x0D 195361459cdSDmitry Bezrukov 196f3aa095aSDmitry Bezrukov static struct { 197f3aa095aSDmitry Bezrukov unsigned char ctrl; 198f3aa095aSDmitry Bezrukov unsigned char timer_l; 199f3aa095aSDmitry Bezrukov unsigned char timer_h; 200f3aa095aSDmitry Bezrukov unsigned char size; 201f3aa095aSDmitry Bezrukov unsigned char ifg; 202f3aa095aSDmitry Bezrukov } AQC111_BULKIN_SIZE[] = { 203f3aa095aSDmitry Bezrukov /* xHCI & EHCI & OHCI */ 204f3aa095aSDmitry Bezrukov {7, 0x00, 0x01, 0x1E, 0xFF},/* 10G, 5G, 2.5G, 1G */ 205f3aa095aSDmitry Bezrukov {7, 0xA0, 0x00, 0x14, 0x00},/* 100M */ 206f3aa095aSDmitry Bezrukov /* Jumbo packet */ 207f3aa095aSDmitry Bezrukov {7, 0x00, 0x01, 0x18, 0xFF}, 208f3aa095aSDmitry Bezrukov }; 209f3aa095aSDmitry Bezrukov 210619fcb44SDmitry Bezrukov #endif /* __LINUX_USBNET_AQC111_H */ 211