1 /* 2 * drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 #include <linux/bitops.h> 17 #include <linux/phy.h> 18 #include <linux/module.h> 19 20 #define RTL821x_PHYSR 0x11 21 #define RTL821x_PHYSR_DUPLEX BIT(13) 22 #define RTL821x_PHYSR_SPEED GENMASK(15, 14) 23 24 #define RTL821x_INER 0x12 25 #define RTL8211B_INER_INIT 0x6400 26 #define RTL8211E_INER_LINK_STATUS BIT(10) 27 #define RTL8211F_INER_LINK_STATUS BIT(4) 28 29 #define RTL821x_INSR 0x13 30 31 #define RTL821x_PAGE_SELECT 0x1f 32 33 #define RTL8211F_INSR 0x1d 34 35 #define RTL8211F_TX_DELAY BIT(8) 36 37 #define RTL8201F_ISR 0x1e 38 #define RTL8201F_IER 0x13 39 40 MODULE_DESCRIPTION("Realtek PHY driver"); 41 MODULE_AUTHOR("Johnson Leung"); 42 MODULE_LICENSE("GPL"); 43 44 static int rtl8211x_page_read(struct phy_device *phydev, u16 page, u16 address) 45 { 46 int ret; 47 48 ret = phy_write(phydev, RTL821x_PAGE_SELECT, page); 49 if (ret) 50 return ret; 51 52 ret = phy_read(phydev, address); 53 54 /* restore to default page 0 */ 55 phy_write(phydev, RTL821x_PAGE_SELECT, 0x0); 56 57 return ret; 58 } 59 60 static int rtl8211x_page_write(struct phy_device *phydev, u16 page, 61 u16 address, u16 val) 62 { 63 int ret; 64 65 ret = phy_write(phydev, RTL821x_PAGE_SELECT, page); 66 if (ret) 67 return ret; 68 69 ret = phy_write(phydev, address, val); 70 71 /* restore to default page 0 */ 72 phy_write(phydev, RTL821x_PAGE_SELECT, 0x0); 73 74 return ret; 75 } 76 77 static int rtl8201_ack_interrupt(struct phy_device *phydev) 78 { 79 int err; 80 81 err = phy_read(phydev, RTL8201F_ISR); 82 83 return (err < 0) ? err : 0; 84 } 85 86 static int rtl821x_ack_interrupt(struct phy_device *phydev) 87 { 88 int err; 89 90 err = phy_read(phydev, RTL821x_INSR); 91 92 return (err < 0) ? err : 0; 93 } 94 95 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 96 { 97 int err; 98 99 err = rtl8211x_page_read(phydev, 0xa43, RTL8211F_INSR); 100 101 return (err < 0) ? err : 0; 102 } 103 104 static int rtl8201_config_intr(struct phy_device *phydev) 105 { 106 u16 val; 107 108 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 109 val = BIT(13) | BIT(12) | BIT(11); 110 else 111 val = 0; 112 113 return rtl8211x_page_write(phydev, 0x7, RTL8201F_IER, val); 114 } 115 116 static int rtl8211b_config_intr(struct phy_device *phydev) 117 { 118 int err; 119 120 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 121 err = phy_write(phydev, RTL821x_INER, 122 RTL8211B_INER_INIT); 123 else 124 err = phy_write(phydev, RTL821x_INER, 0); 125 126 return err; 127 } 128 129 static int rtl8211e_config_intr(struct phy_device *phydev) 130 { 131 int err; 132 133 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 134 err = phy_write(phydev, RTL821x_INER, 135 RTL8211E_INER_LINK_STATUS); 136 else 137 err = phy_write(phydev, RTL821x_INER, 0); 138 139 return err; 140 } 141 142 static int rtl8211f_config_intr(struct phy_device *phydev) 143 { 144 u16 val; 145 146 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 147 val = RTL8211F_INER_LINK_STATUS; 148 else 149 val = 0; 150 151 return rtl8211x_page_write(phydev, 0xa42, RTL821x_INER, val); 152 } 153 154 static int rtl8211f_config_init(struct phy_device *phydev) 155 { 156 int ret; 157 u16 val; 158 159 ret = genphy_config_init(phydev); 160 if (ret < 0) 161 return ret; 162 163 ret = rtl8211x_page_read(phydev, 0xd08, 0x11); 164 if (ret < 0) 165 return ret; 166 167 val = ret & 0xffff; 168 169 /* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */ 170 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 171 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 172 val |= RTL8211F_TX_DELAY; 173 else 174 val &= ~RTL8211F_TX_DELAY; 175 176 ret = rtl8211x_page_write(phydev, 0xd08, 0x11, val); 177 if (ret) 178 return ret; 179 180 return 0; 181 } 182 183 static struct phy_driver realtek_drvs[] = { 184 { 185 .phy_id = 0x00008201, 186 .name = "RTL8201CP Ethernet", 187 .phy_id_mask = 0x0000ffff, 188 .features = PHY_BASIC_FEATURES, 189 .flags = PHY_HAS_INTERRUPT, 190 }, { 191 .phy_id = 0x001cc816, 192 .name = "RTL8201F 10/100Mbps Ethernet", 193 .phy_id_mask = 0x001fffff, 194 .features = PHY_BASIC_FEATURES, 195 .flags = PHY_HAS_INTERRUPT, 196 .ack_interrupt = &rtl8201_ack_interrupt, 197 .config_intr = &rtl8201_config_intr, 198 .suspend = genphy_suspend, 199 .resume = genphy_resume, 200 }, { 201 .phy_id = 0x001cc912, 202 .name = "RTL8211B Gigabit Ethernet", 203 .phy_id_mask = 0x001fffff, 204 .features = PHY_GBIT_FEATURES, 205 .flags = PHY_HAS_INTERRUPT, 206 .ack_interrupt = &rtl821x_ack_interrupt, 207 .config_intr = &rtl8211b_config_intr, 208 }, { 209 .phy_id = 0x001cc914, 210 .name = "RTL8211DN Gigabit Ethernet", 211 .phy_id_mask = 0x001fffff, 212 .features = PHY_GBIT_FEATURES, 213 .flags = PHY_HAS_INTERRUPT, 214 .ack_interrupt = rtl821x_ack_interrupt, 215 .config_intr = rtl8211e_config_intr, 216 .suspend = genphy_suspend, 217 .resume = genphy_resume, 218 }, { 219 .phy_id = 0x001cc915, 220 .name = "RTL8211E Gigabit Ethernet", 221 .phy_id_mask = 0x001fffff, 222 .features = PHY_GBIT_FEATURES, 223 .flags = PHY_HAS_INTERRUPT, 224 .ack_interrupt = &rtl821x_ack_interrupt, 225 .config_intr = &rtl8211e_config_intr, 226 .suspend = genphy_suspend, 227 .resume = genphy_resume, 228 }, { 229 .phy_id = 0x001cc916, 230 .name = "RTL8211F Gigabit Ethernet", 231 .phy_id_mask = 0x001fffff, 232 .features = PHY_GBIT_FEATURES, 233 .flags = PHY_HAS_INTERRUPT, 234 .config_init = &rtl8211f_config_init, 235 .ack_interrupt = &rtl8211f_ack_interrupt, 236 .config_intr = &rtl8211f_config_intr, 237 .suspend = genphy_suspend, 238 .resume = genphy_resume, 239 }, 240 }; 241 242 module_phy_driver(realtek_drvs); 243 244 static struct mdio_device_id __maybe_unused realtek_tbl[] = { 245 { 0x001cc816, 0x001fffff }, 246 { 0x001cc912, 0x001fffff }, 247 { 0x001cc914, 0x001fffff }, 248 { 0x001cc915, 0x001fffff }, 249 { 0x001cc916, 0x001fffff }, 250 { } 251 }; 252 253 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 254