1 // SPDX-License-Identifier: GPL-2.0+ 2 /* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 #include <linux/bitops.h> 11 #include <linux/phy.h> 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 15 #define RTL821x_PHYSR 0x11 16 #define RTL821x_PHYSR_DUPLEX BIT(13) 17 #define RTL821x_PHYSR_SPEED GENMASK(15, 14) 18 19 #define RTL821x_INER 0x12 20 #define RTL8211B_INER_INIT 0x6400 21 #define RTL8211E_INER_LINK_STATUS BIT(10) 22 #define RTL8211F_INER_LINK_STATUS BIT(4) 23 24 #define RTL821x_INSR 0x13 25 26 #define RTL821x_EXT_PAGE_SELECT 0x1e 27 #define RTL821x_PAGE_SELECT 0x1f 28 29 #define RTL8211F_PHYCR1 0x18 30 #define RTL8211F_INSR 0x1d 31 32 #define RTL8211F_TX_DELAY BIT(8) 33 #define RTL8211F_RX_DELAY BIT(3) 34 35 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 36 #define RTL8211F_ALDPS_ENABLE BIT(2) 37 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 38 39 #define RTL8211E_CTRL_DELAY BIT(13) 40 #define RTL8211E_TX_DELAY BIT(12) 41 #define RTL8211E_RX_DELAY BIT(11) 42 43 #define RTL8201F_ISR 0x1e 44 #define RTL8201F_ISR_ANERR BIT(15) 45 #define RTL8201F_ISR_DUPLEX BIT(13) 46 #define RTL8201F_ISR_LINK BIT(11) 47 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 48 RTL8201F_ISR_DUPLEX | \ 49 RTL8201F_ISR_LINK) 50 #define RTL8201F_IER 0x13 51 52 #define RTL8366RB_POWER_SAVE 0x15 53 #define RTL8366RB_POWER_SAVE_ON BIT(12) 54 55 #define RTL_SUPPORTS_5000FULL BIT(14) 56 #define RTL_SUPPORTS_2500FULL BIT(13) 57 #define RTL_SUPPORTS_10000FULL BIT(0) 58 #define RTL_ADV_2500FULL BIT(7) 59 #define RTL_LPADV_10000FULL BIT(11) 60 #define RTL_LPADV_5000FULL BIT(6) 61 #define RTL_LPADV_2500FULL BIT(5) 62 63 #define RTLGEN_SPEED_MASK 0x0630 64 65 #define RTL_GENERIC_PHYID 0x001cc800 66 67 MODULE_DESCRIPTION("Realtek PHY driver"); 68 MODULE_AUTHOR("Johnson Leung"); 69 MODULE_LICENSE("GPL"); 70 71 static int rtl821x_read_page(struct phy_device *phydev) 72 { 73 return __phy_read(phydev, RTL821x_PAGE_SELECT); 74 } 75 76 static int rtl821x_write_page(struct phy_device *phydev, int page) 77 { 78 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 79 } 80 81 static int rtl8201_ack_interrupt(struct phy_device *phydev) 82 { 83 int err; 84 85 err = phy_read(phydev, RTL8201F_ISR); 86 87 return (err < 0) ? err : 0; 88 } 89 90 static int rtl821x_ack_interrupt(struct phy_device *phydev) 91 { 92 int err; 93 94 err = phy_read(phydev, RTL821x_INSR); 95 96 return (err < 0) ? err : 0; 97 } 98 99 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 100 { 101 int err; 102 103 err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR); 104 105 return (err < 0) ? err : 0; 106 } 107 108 static int rtl8201_config_intr(struct phy_device *phydev) 109 { 110 u16 val; 111 int err; 112 113 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 114 err = rtl8201_ack_interrupt(phydev); 115 if (err) 116 return err; 117 118 val = BIT(13) | BIT(12) | BIT(11); 119 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 120 } else { 121 val = 0; 122 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 123 if (err) 124 return err; 125 126 err = rtl8201_ack_interrupt(phydev); 127 } 128 129 return err; 130 } 131 132 static int rtl8211b_config_intr(struct phy_device *phydev) 133 { 134 int err; 135 136 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 137 err = rtl821x_ack_interrupt(phydev); 138 if (err) 139 return err; 140 141 err = phy_write(phydev, RTL821x_INER, 142 RTL8211B_INER_INIT); 143 } else { 144 err = phy_write(phydev, RTL821x_INER, 0); 145 if (err) 146 return err; 147 148 err = rtl821x_ack_interrupt(phydev); 149 } 150 151 return err; 152 } 153 154 static int rtl8211e_config_intr(struct phy_device *phydev) 155 { 156 int err; 157 158 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 159 err = rtl821x_ack_interrupt(phydev); 160 if (err) 161 return err; 162 163 err = phy_write(phydev, RTL821x_INER, 164 RTL8211E_INER_LINK_STATUS); 165 } else { 166 err = phy_write(phydev, RTL821x_INER, 0); 167 if (err) 168 return err; 169 170 err = rtl821x_ack_interrupt(phydev); 171 } 172 173 return err; 174 } 175 176 static int rtl8211f_config_intr(struct phy_device *phydev) 177 { 178 u16 val; 179 int err; 180 181 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 182 err = rtl8211f_ack_interrupt(phydev); 183 if (err) 184 return err; 185 186 val = RTL8211F_INER_LINK_STATUS; 187 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 188 } else { 189 val = 0; 190 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 191 if (err) 192 return err; 193 194 err = rtl8211f_ack_interrupt(phydev); 195 } 196 197 return err; 198 } 199 200 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 201 { 202 int irq_status; 203 204 irq_status = phy_read(phydev, RTL8201F_ISR); 205 if (irq_status < 0) { 206 phy_error(phydev); 207 return IRQ_NONE; 208 } 209 210 if (!(irq_status & RTL8201F_ISR_MASK)) 211 return IRQ_NONE; 212 213 phy_trigger_machine(phydev); 214 215 return IRQ_HANDLED; 216 } 217 218 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 219 { 220 int irq_status, irq_enabled; 221 222 irq_status = phy_read(phydev, RTL821x_INSR); 223 if (irq_status < 0) { 224 phy_error(phydev); 225 return IRQ_NONE; 226 } 227 228 irq_enabled = phy_read(phydev, RTL821x_INER); 229 if (irq_enabled < 0) { 230 phy_error(phydev); 231 return IRQ_NONE; 232 } 233 234 if (!(irq_status & irq_enabled)) 235 return IRQ_NONE; 236 237 phy_trigger_machine(phydev); 238 239 return IRQ_HANDLED; 240 } 241 242 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 243 { 244 int irq_status; 245 246 irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR); 247 if (irq_status < 0) { 248 phy_error(phydev); 249 return IRQ_NONE; 250 } 251 252 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 253 return IRQ_NONE; 254 255 phy_trigger_machine(phydev); 256 257 return IRQ_HANDLED; 258 } 259 260 static int rtl8211_config_aneg(struct phy_device *phydev) 261 { 262 int ret; 263 264 ret = genphy_config_aneg(phydev); 265 if (ret < 0) 266 return ret; 267 268 /* Quirk was copied from vendor driver. Unfortunately it includes no 269 * description of the magic numbers. 270 */ 271 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 272 phy_write(phydev, 0x17, 0x2138); 273 phy_write(phydev, 0x0e, 0x0260); 274 } else { 275 phy_write(phydev, 0x17, 0x2108); 276 phy_write(phydev, 0x0e, 0x0000); 277 } 278 279 return 0; 280 } 281 282 static int rtl8211c_config_init(struct phy_device *phydev) 283 { 284 /* RTL8211C has an issue when operating in Gigabit slave mode */ 285 return phy_set_bits(phydev, MII_CTRL1000, 286 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 287 } 288 289 static int rtl8211f_config_init(struct phy_device *phydev) 290 { 291 struct device *dev = &phydev->mdio.dev; 292 u16 val_txdly, val_rxdly; 293 u16 val; 294 int ret; 295 296 val = RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_XTAL_OFF; 297 phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1, val, val); 298 299 switch (phydev->interface) { 300 case PHY_INTERFACE_MODE_RGMII: 301 val_txdly = 0; 302 val_rxdly = 0; 303 break; 304 305 case PHY_INTERFACE_MODE_RGMII_RXID: 306 val_txdly = 0; 307 val_rxdly = RTL8211F_RX_DELAY; 308 break; 309 310 case PHY_INTERFACE_MODE_RGMII_TXID: 311 val_txdly = RTL8211F_TX_DELAY; 312 val_rxdly = 0; 313 break; 314 315 case PHY_INTERFACE_MODE_RGMII_ID: 316 val_txdly = RTL8211F_TX_DELAY; 317 val_rxdly = RTL8211F_RX_DELAY; 318 break; 319 320 default: /* the rest of the modes imply leaving delay as is. */ 321 return 0; 322 } 323 324 ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, 325 val_txdly); 326 if (ret < 0) { 327 dev_err(dev, "Failed to update the TX delay register\n"); 328 return ret; 329 } else if (ret) { 330 dev_dbg(dev, 331 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 332 val_txdly ? "Enabling" : "Disabling"); 333 } else { 334 dev_dbg(dev, 335 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 336 val_txdly ? "enabled" : "disabled"); 337 } 338 339 ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY, 340 val_rxdly); 341 if (ret < 0) { 342 dev_err(dev, "Failed to update the RX delay register\n"); 343 return ret; 344 } else if (ret) { 345 dev_dbg(dev, 346 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 347 val_rxdly ? "Enabling" : "Disabling"); 348 } else { 349 dev_dbg(dev, 350 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 351 val_rxdly ? "enabled" : "disabled"); 352 } 353 354 return 0; 355 } 356 357 static int rtl8211e_config_init(struct phy_device *phydev) 358 { 359 int ret = 0, oldpage; 360 u16 val; 361 362 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 363 switch (phydev->interface) { 364 case PHY_INTERFACE_MODE_RGMII: 365 val = RTL8211E_CTRL_DELAY | 0; 366 break; 367 case PHY_INTERFACE_MODE_RGMII_ID: 368 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 369 break; 370 case PHY_INTERFACE_MODE_RGMII_RXID: 371 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 372 break; 373 case PHY_INTERFACE_MODE_RGMII_TXID: 374 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 375 break; 376 default: /* the rest of the modes imply leaving delays as is. */ 377 return 0; 378 } 379 380 /* According to a sample driver there is a 0x1c config register on the 381 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 382 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 383 * The configuration register definition: 384 * 14 = reserved 385 * 13 = Force Tx RX Delay controlled by bit12 bit11, 386 * 12 = RX Delay, 11 = TX Delay 387 * 10:0 = Test && debug settings reserved by realtek 388 */ 389 oldpage = phy_select_page(phydev, 0x7); 390 if (oldpage < 0) 391 goto err_restore_page; 392 393 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4); 394 if (ret) 395 goto err_restore_page; 396 397 ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY 398 | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY, 399 val); 400 401 err_restore_page: 402 return phy_restore_page(phydev, oldpage, ret); 403 } 404 405 static int rtl8211b_suspend(struct phy_device *phydev) 406 { 407 phy_write(phydev, MII_MMD_DATA, BIT(9)); 408 409 return genphy_suspend(phydev); 410 } 411 412 static int rtl8211b_resume(struct phy_device *phydev) 413 { 414 phy_write(phydev, MII_MMD_DATA, 0); 415 416 return genphy_resume(phydev); 417 } 418 419 static int rtl8366rb_config_init(struct phy_device *phydev) 420 { 421 int ret; 422 423 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 424 RTL8366RB_POWER_SAVE_ON); 425 if (ret) { 426 dev_err(&phydev->mdio.dev, 427 "error enabling power management\n"); 428 } 429 430 return ret; 431 } 432 433 /* get actual speed to cover the downshift case */ 434 static int rtlgen_get_speed(struct phy_device *phydev) 435 { 436 int val; 437 438 if (!phydev->link) 439 return 0; 440 441 val = phy_read_paged(phydev, 0xa43, 0x12); 442 if (val < 0) 443 return val; 444 445 switch (val & RTLGEN_SPEED_MASK) { 446 case 0x0000: 447 phydev->speed = SPEED_10; 448 break; 449 case 0x0010: 450 phydev->speed = SPEED_100; 451 break; 452 case 0x0020: 453 phydev->speed = SPEED_1000; 454 break; 455 case 0x0200: 456 phydev->speed = SPEED_10000; 457 break; 458 case 0x0210: 459 phydev->speed = SPEED_2500; 460 break; 461 case 0x0220: 462 phydev->speed = SPEED_5000; 463 break; 464 default: 465 break; 466 } 467 468 return 0; 469 } 470 471 static int rtlgen_read_status(struct phy_device *phydev) 472 { 473 int ret; 474 475 ret = genphy_read_status(phydev); 476 if (ret < 0) 477 return ret; 478 479 return rtlgen_get_speed(phydev); 480 } 481 482 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 483 { 484 int ret; 485 486 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) { 487 rtl821x_write_page(phydev, 0xa5c); 488 ret = __phy_read(phydev, 0x12); 489 rtl821x_write_page(phydev, 0); 490 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) { 491 rtl821x_write_page(phydev, 0xa5d); 492 ret = __phy_read(phydev, 0x10); 493 rtl821x_write_page(phydev, 0); 494 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) { 495 rtl821x_write_page(phydev, 0xa5d); 496 ret = __phy_read(phydev, 0x11); 497 rtl821x_write_page(phydev, 0); 498 } else { 499 ret = -EOPNOTSUPP; 500 } 501 502 return ret; 503 } 504 505 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 506 u16 val) 507 { 508 int ret; 509 510 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) { 511 rtl821x_write_page(phydev, 0xa5d); 512 ret = __phy_write(phydev, 0x10, val); 513 rtl821x_write_page(phydev, 0); 514 } else { 515 ret = -EOPNOTSUPP; 516 } 517 518 return ret; 519 } 520 521 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 522 { 523 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 524 525 if (ret != -EOPNOTSUPP) 526 return ret; 527 528 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) { 529 rtl821x_write_page(phydev, 0xa6e); 530 ret = __phy_read(phydev, 0x16); 531 rtl821x_write_page(phydev, 0); 532 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) { 533 rtl821x_write_page(phydev, 0xa6d); 534 ret = __phy_read(phydev, 0x12); 535 rtl821x_write_page(phydev, 0); 536 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) { 537 rtl821x_write_page(phydev, 0xa6d); 538 ret = __phy_read(phydev, 0x10); 539 rtl821x_write_page(phydev, 0); 540 } 541 542 return ret; 543 } 544 545 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 546 u16 val) 547 { 548 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 549 550 if (ret != -EOPNOTSUPP) 551 return ret; 552 553 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) { 554 rtl821x_write_page(phydev, 0xa6d); 555 ret = __phy_write(phydev, 0x12, val); 556 rtl821x_write_page(phydev, 0); 557 } 558 559 return ret; 560 } 561 562 static int rtl822x_get_features(struct phy_device *phydev) 563 { 564 int val; 565 566 val = phy_read_paged(phydev, 0xa61, 0x13); 567 if (val < 0) 568 return val; 569 570 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 571 phydev->supported, val & RTL_SUPPORTS_2500FULL); 572 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 573 phydev->supported, val & RTL_SUPPORTS_5000FULL); 574 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 575 phydev->supported, val & RTL_SUPPORTS_10000FULL); 576 577 return genphy_read_abilities(phydev); 578 } 579 580 static int rtl822x_config_aneg(struct phy_device *phydev) 581 { 582 int ret = 0; 583 584 if (phydev->autoneg == AUTONEG_ENABLE) { 585 u16 adv2500 = 0; 586 587 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 588 phydev->advertising)) 589 adv2500 = RTL_ADV_2500FULL; 590 591 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12, 592 RTL_ADV_2500FULL, adv2500); 593 if (ret < 0) 594 return ret; 595 } 596 597 return __genphy_config_aneg(phydev, ret); 598 } 599 600 static int rtl822x_read_status(struct phy_device *phydev) 601 { 602 int ret; 603 604 if (phydev->autoneg == AUTONEG_ENABLE) { 605 int lpadv = phy_read_paged(phydev, 0xa5d, 0x13); 606 607 if (lpadv < 0) 608 return lpadv; 609 610 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 611 phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL); 612 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 613 phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL); 614 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 615 phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL); 616 } 617 618 ret = genphy_read_status(phydev); 619 if (ret < 0) 620 return ret; 621 622 return rtlgen_get_speed(phydev); 623 } 624 625 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 626 { 627 int val; 628 629 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 630 val = phy_read(phydev, 0x13); 631 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 632 633 return val >= 0 && val & RTL_SUPPORTS_2500FULL; 634 } 635 636 static int rtlgen_match_phy_device(struct phy_device *phydev) 637 { 638 return phydev->phy_id == RTL_GENERIC_PHYID && 639 !rtlgen_supports_2_5gbps(phydev); 640 } 641 642 static int rtl8226_match_phy_device(struct phy_device *phydev) 643 { 644 return phydev->phy_id == RTL_GENERIC_PHYID && 645 rtlgen_supports_2_5gbps(phydev); 646 } 647 648 static int rtlgen_resume(struct phy_device *phydev) 649 { 650 int ret = genphy_resume(phydev); 651 652 /* Internal PHY's from RTL8168h up may not be instantly ready */ 653 msleep(20); 654 655 return ret; 656 } 657 658 static struct phy_driver realtek_drvs[] = { 659 { 660 PHY_ID_MATCH_EXACT(0x00008201), 661 .name = "RTL8201CP Ethernet", 662 .read_page = rtl821x_read_page, 663 .write_page = rtl821x_write_page, 664 }, { 665 PHY_ID_MATCH_EXACT(0x001cc816), 666 .name = "RTL8201F Fast Ethernet", 667 .config_intr = &rtl8201_config_intr, 668 .handle_interrupt = rtl8201_handle_interrupt, 669 .suspend = genphy_suspend, 670 .resume = genphy_resume, 671 .read_page = rtl821x_read_page, 672 .write_page = rtl821x_write_page, 673 }, { 674 PHY_ID_MATCH_MODEL(0x001cc880), 675 .name = "RTL8208 Fast Ethernet", 676 .read_mmd = genphy_read_mmd_unsupported, 677 .write_mmd = genphy_write_mmd_unsupported, 678 .suspend = genphy_suspend, 679 .resume = genphy_resume, 680 .read_page = rtl821x_read_page, 681 .write_page = rtl821x_write_page, 682 }, { 683 PHY_ID_MATCH_EXACT(0x001cc910), 684 .name = "RTL8211 Gigabit Ethernet", 685 .config_aneg = rtl8211_config_aneg, 686 .read_mmd = &genphy_read_mmd_unsupported, 687 .write_mmd = &genphy_write_mmd_unsupported, 688 .read_page = rtl821x_read_page, 689 .write_page = rtl821x_write_page, 690 }, { 691 PHY_ID_MATCH_EXACT(0x001cc912), 692 .name = "RTL8211B Gigabit Ethernet", 693 .config_intr = &rtl8211b_config_intr, 694 .handle_interrupt = rtl821x_handle_interrupt, 695 .read_mmd = &genphy_read_mmd_unsupported, 696 .write_mmd = &genphy_write_mmd_unsupported, 697 .suspend = rtl8211b_suspend, 698 .resume = rtl8211b_resume, 699 .read_page = rtl821x_read_page, 700 .write_page = rtl821x_write_page, 701 }, { 702 PHY_ID_MATCH_EXACT(0x001cc913), 703 .name = "RTL8211C Gigabit Ethernet", 704 .config_init = rtl8211c_config_init, 705 .read_mmd = &genphy_read_mmd_unsupported, 706 .write_mmd = &genphy_write_mmd_unsupported, 707 .read_page = rtl821x_read_page, 708 .write_page = rtl821x_write_page, 709 }, { 710 PHY_ID_MATCH_EXACT(0x001cc914), 711 .name = "RTL8211DN Gigabit Ethernet", 712 .config_intr = rtl8211e_config_intr, 713 .handle_interrupt = rtl821x_handle_interrupt, 714 .suspend = genphy_suspend, 715 .resume = genphy_resume, 716 .read_page = rtl821x_read_page, 717 .write_page = rtl821x_write_page, 718 }, { 719 PHY_ID_MATCH_EXACT(0x001cc915), 720 .name = "RTL8211E Gigabit Ethernet", 721 .config_init = &rtl8211e_config_init, 722 .config_intr = &rtl8211e_config_intr, 723 .handle_interrupt = rtl821x_handle_interrupt, 724 .suspend = genphy_suspend, 725 .resume = genphy_resume, 726 .read_page = rtl821x_read_page, 727 .write_page = rtl821x_write_page, 728 }, { 729 PHY_ID_MATCH_EXACT(0x001cc916), 730 .name = "RTL8211F Gigabit Ethernet", 731 .config_init = &rtl8211f_config_init, 732 .read_status = rtlgen_read_status, 733 .config_intr = &rtl8211f_config_intr, 734 .handle_interrupt = rtl8211f_handle_interrupt, 735 .suspend = genphy_suspend, 736 .resume = genphy_resume, 737 .read_page = rtl821x_read_page, 738 .write_page = rtl821x_write_page, 739 }, { 740 .name = "Generic FE-GE Realtek PHY", 741 .match_phy_device = rtlgen_match_phy_device, 742 .read_status = rtlgen_read_status, 743 .suspend = genphy_suspend, 744 .resume = rtlgen_resume, 745 .read_page = rtl821x_read_page, 746 .write_page = rtl821x_write_page, 747 .read_mmd = rtlgen_read_mmd, 748 .write_mmd = rtlgen_write_mmd, 749 }, { 750 .name = "RTL8226 2.5Gbps PHY", 751 .match_phy_device = rtl8226_match_phy_device, 752 .get_features = rtl822x_get_features, 753 .config_aneg = rtl822x_config_aneg, 754 .read_status = rtl822x_read_status, 755 .suspend = genphy_suspend, 756 .resume = rtlgen_resume, 757 .read_page = rtl821x_read_page, 758 .write_page = rtl821x_write_page, 759 .read_mmd = rtl822x_read_mmd, 760 .write_mmd = rtl822x_write_mmd, 761 }, { 762 PHY_ID_MATCH_EXACT(0x001cc840), 763 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 764 .get_features = rtl822x_get_features, 765 .config_aneg = rtl822x_config_aneg, 766 .read_status = rtl822x_read_status, 767 .suspend = genphy_suspend, 768 .resume = rtlgen_resume, 769 .read_page = rtl821x_read_page, 770 .write_page = rtl821x_write_page, 771 .read_mmd = rtl822x_read_mmd, 772 .write_mmd = rtl822x_write_mmd, 773 }, { 774 PHY_ID_MATCH_EXACT(0x001cc838), 775 .name = "RTL8226-CG 2.5Gbps PHY", 776 .get_features = rtl822x_get_features, 777 .config_aneg = rtl822x_config_aneg, 778 .read_status = rtl822x_read_status, 779 .suspend = genphy_suspend, 780 .resume = rtlgen_resume, 781 .read_page = rtl821x_read_page, 782 .write_page = rtl821x_write_page, 783 }, { 784 PHY_ID_MATCH_EXACT(0x001cc848), 785 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 786 .get_features = rtl822x_get_features, 787 .config_aneg = rtl822x_config_aneg, 788 .read_status = rtl822x_read_status, 789 .suspend = genphy_suspend, 790 .resume = rtlgen_resume, 791 .read_page = rtl821x_read_page, 792 .write_page = rtl821x_write_page, 793 }, { 794 PHY_ID_MATCH_EXACT(0x001cc849), 795 .name = "RTL8221B-VB-CG 2.5Gbps PHY", 796 .get_features = rtl822x_get_features, 797 .config_aneg = rtl822x_config_aneg, 798 .read_status = rtl822x_read_status, 799 .suspend = genphy_suspend, 800 .resume = rtlgen_resume, 801 .read_page = rtl821x_read_page, 802 .write_page = rtl821x_write_page, 803 }, { 804 PHY_ID_MATCH_EXACT(0x001cc84a), 805 .name = "RTL8221B-VM-CG 2.5Gbps PHY", 806 .get_features = rtl822x_get_features, 807 .config_aneg = rtl822x_config_aneg, 808 .read_status = rtl822x_read_status, 809 .suspend = genphy_suspend, 810 .resume = rtlgen_resume, 811 .read_page = rtl821x_read_page, 812 .write_page = rtl821x_write_page, 813 }, { 814 PHY_ID_MATCH_EXACT(0x001cc961), 815 .name = "RTL8366RB Gigabit Ethernet", 816 .config_init = &rtl8366rb_config_init, 817 /* These interrupts are handled by the irq controller 818 * embedded inside the RTL8366RB, they get unmasked when the 819 * irq is requested and ACKed by reading the status register, 820 * which is done by the irqchip code. 821 */ 822 .config_intr = genphy_no_config_intr, 823 .handle_interrupt = genphy_handle_interrupt_no_ack, 824 .suspend = genphy_suspend, 825 .resume = genphy_resume, 826 }, 827 }; 828 829 module_phy_driver(realtek_drvs); 830 831 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 832 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 833 { } 834 }; 835 836 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 837