1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/realtek.c 4 * 5 * Driver for Realtek PHYs 6 * 7 * Author: Johnson Leung <r58129@freescale.com> 8 * 9 * Copyright (c) 2004 Freescale Semiconductor, Inc. 10 */ 11 #include <linux/bitops.h> 12 #include <linux/phy.h> 13 #include <linux/module.h> 14 #include <linux/delay.h> 15 16 #define RTL821x_PHYSR 0x11 17 #define RTL821x_PHYSR_DUPLEX BIT(13) 18 #define RTL821x_PHYSR_SPEED GENMASK(15, 14) 19 20 #define RTL821x_INER 0x12 21 #define RTL8211B_INER_INIT 0x6400 22 #define RTL8211E_INER_LINK_STATUS BIT(10) 23 #define RTL8211F_INER_LINK_STATUS BIT(4) 24 25 #define RTL821x_INSR 0x13 26 27 #define RTL821x_EXT_PAGE_SELECT 0x1e 28 #define RTL821x_PAGE_SELECT 0x1f 29 30 #define RTL8211F_PHYCR1 0x18 31 #define RTL8211F_INSR 0x1d 32 33 #define RTL8211F_TX_DELAY BIT(8) 34 #define RTL8211F_RX_DELAY BIT(3) 35 36 #define RTL8211F_ALDPS_PLL_OFF BIT(1) 37 #define RTL8211F_ALDPS_ENABLE BIT(2) 38 #define RTL8211F_ALDPS_XTAL_OFF BIT(12) 39 40 #define RTL8211E_TX_DELAY BIT(1) 41 #define RTL8211E_RX_DELAY BIT(2) 42 #define RTL8211E_MODE_MII_GMII BIT(3) 43 44 #define RTL8201F_ISR 0x1e 45 #define RTL8201F_IER 0x13 46 47 #define RTL8366RB_POWER_SAVE 0x15 48 #define RTL8366RB_POWER_SAVE_ON BIT(12) 49 50 #define RTL_SUPPORTS_5000FULL BIT(14) 51 #define RTL_SUPPORTS_2500FULL BIT(13) 52 #define RTL_SUPPORTS_10000FULL BIT(0) 53 #define RTL_ADV_2500FULL BIT(7) 54 #define RTL_LPADV_10000FULL BIT(11) 55 #define RTL_LPADV_5000FULL BIT(6) 56 #define RTL_LPADV_2500FULL BIT(5) 57 58 #define RTLGEN_SPEED_MASK 0x0630 59 60 #define RTL_GENERIC_PHYID 0x001cc800 61 62 MODULE_DESCRIPTION("Realtek PHY driver"); 63 MODULE_AUTHOR("Johnson Leung"); 64 MODULE_LICENSE("GPL"); 65 66 static int rtl821x_read_page(struct phy_device *phydev) 67 { 68 return __phy_read(phydev, RTL821x_PAGE_SELECT); 69 } 70 71 static int rtl821x_write_page(struct phy_device *phydev, int page) 72 { 73 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 74 } 75 76 static int rtl8201_ack_interrupt(struct phy_device *phydev) 77 { 78 int err; 79 80 err = phy_read(phydev, RTL8201F_ISR); 81 82 return (err < 0) ? err : 0; 83 } 84 85 static int rtl821x_ack_interrupt(struct phy_device *phydev) 86 { 87 int err; 88 89 err = phy_read(phydev, RTL821x_INSR); 90 91 return (err < 0) ? err : 0; 92 } 93 94 static int rtl8211f_ack_interrupt(struct phy_device *phydev) 95 { 96 int err; 97 98 err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR); 99 100 return (err < 0) ? err : 0; 101 } 102 103 static int rtl8201_config_intr(struct phy_device *phydev) 104 { 105 u16 val; 106 107 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 108 val = BIT(13) | BIT(12) | BIT(11); 109 else 110 val = 0; 111 112 return phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 113 } 114 115 static int rtl8211b_config_intr(struct phy_device *phydev) 116 { 117 int err; 118 119 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 120 err = phy_write(phydev, RTL821x_INER, 121 RTL8211B_INER_INIT); 122 else 123 err = phy_write(phydev, RTL821x_INER, 0); 124 125 return err; 126 } 127 128 static int rtl8211e_config_intr(struct phy_device *phydev) 129 { 130 int err; 131 132 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 133 err = phy_write(phydev, RTL821x_INER, 134 RTL8211E_INER_LINK_STATUS); 135 else 136 err = phy_write(phydev, RTL821x_INER, 0); 137 138 return err; 139 } 140 141 static int rtl8211f_config_intr(struct phy_device *phydev) 142 { 143 u16 val; 144 145 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 146 val = RTL8211F_INER_LINK_STATUS; 147 else 148 val = 0; 149 150 return phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 151 } 152 153 static int rtl8211_config_aneg(struct phy_device *phydev) 154 { 155 int ret; 156 157 ret = genphy_config_aneg(phydev); 158 if (ret < 0) 159 return ret; 160 161 /* Quirk was copied from vendor driver. Unfortunately it includes no 162 * description of the magic numbers. 163 */ 164 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 165 phy_write(phydev, 0x17, 0x2138); 166 phy_write(phydev, 0x0e, 0x0260); 167 } else { 168 phy_write(phydev, 0x17, 0x2108); 169 phy_write(phydev, 0x0e, 0x0000); 170 } 171 172 return 0; 173 } 174 175 static int rtl8211c_config_init(struct phy_device *phydev) 176 { 177 /* RTL8211C has an issue when operating in Gigabit slave mode */ 178 return phy_set_bits(phydev, MII_CTRL1000, 179 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 180 } 181 182 static int rtl8211f_config_init(struct phy_device *phydev) 183 { 184 struct device *dev = &phydev->mdio.dev; 185 u16 val_txdly, val_rxdly; 186 u16 val; 187 int ret; 188 189 val = RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_XTAL_OFF; 190 phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1, val, val); 191 192 switch (phydev->interface) { 193 case PHY_INTERFACE_MODE_RGMII: 194 val_txdly = 0; 195 val_rxdly = 0; 196 break; 197 198 case PHY_INTERFACE_MODE_RGMII_RXID: 199 val_txdly = 0; 200 val_rxdly = RTL8211F_RX_DELAY; 201 break; 202 203 case PHY_INTERFACE_MODE_RGMII_TXID: 204 val_txdly = RTL8211F_TX_DELAY; 205 val_rxdly = 0; 206 break; 207 208 case PHY_INTERFACE_MODE_RGMII_ID: 209 val_txdly = RTL8211F_TX_DELAY; 210 val_rxdly = RTL8211F_RX_DELAY; 211 break; 212 213 default: /* the rest of the modes imply leaving delay as is. */ 214 return 0; 215 } 216 217 ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, 218 val_txdly); 219 if (ret < 0) { 220 dev_err(dev, "Failed to update the TX delay register\n"); 221 return ret; 222 } else if (ret) { 223 dev_dbg(dev, 224 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 225 val_txdly ? "Enabling" : "Disabling"); 226 } else { 227 dev_dbg(dev, 228 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 229 val_txdly ? "enabled" : "disabled"); 230 } 231 232 ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY, 233 val_rxdly); 234 if (ret < 0) { 235 dev_err(dev, "Failed to update the RX delay register\n"); 236 return ret; 237 } else if (ret) { 238 dev_dbg(dev, 239 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 240 val_rxdly ? "Enabling" : "Disabling"); 241 } else { 242 dev_dbg(dev, 243 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 244 val_rxdly ? "enabled" : "disabled"); 245 } 246 247 return 0; 248 } 249 250 static int rtl8211e_config_init(struct phy_device *phydev) 251 { 252 int ret = 0, oldpage; 253 u16 val; 254 255 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 256 switch (phydev->interface) { 257 case PHY_INTERFACE_MODE_RGMII: 258 val = 0; 259 break; 260 case PHY_INTERFACE_MODE_RGMII_ID: 261 val = RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 262 break; 263 case PHY_INTERFACE_MODE_RGMII_RXID: 264 val = RTL8211E_RX_DELAY; 265 break; 266 case PHY_INTERFACE_MODE_RGMII_TXID: 267 val = RTL8211E_TX_DELAY; 268 break; 269 default: /* the rest of the modes imply leaving delays as is. */ 270 return 0; 271 } 272 273 /* According to a sample driver there is a 0x1c config register on the 274 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 275 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. It can 276 * also be used to customize the whole configuration register: 277 * 8:6 = PHY Address, 5:4 = Auto-Negotiation, 3 = Interface Mode Select, 278 * 2 = RX Delay, 1 = TX Delay, 0 = SELRGV (see original PHY datasheet 279 * for details). 280 */ 281 oldpage = phy_select_page(phydev, 0x7); 282 if (oldpage < 0) 283 goto err_restore_page; 284 285 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4); 286 if (ret) 287 goto err_restore_page; 288 289 ret = __phy_modify(phydev, 0x1c, RTL8211E_TX_DELAY | RTL8211E_RX_DELAY, 290 val); 291 292 err_restore_page: 293 return phy_restore_page(phydev, oldpage, ret); 294 } 295 296 static int rtl8211b_suspend(struct phy_device *phydev) 297 { 298 phy_write(phydev, MII_MMD_DATA, BIT(9)); 299 300 return genphy_suspend(phydev); 301 } 302 303 static int rtl8211b_resume(struct phy_device *phydev) 304 { 305 phy_write(phydev, MII_MMD_DATA, 0); 306 307 return genphy_resume(phydev); 308 } 309 310 static int rtl8366rb_config_init(struct phy_device *phydev) 311 { 312 int ret; 313 314 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 315 RTL8366RB_POWER_SAVE_ON); 316 if (ret) { 317 dev_err(&phydev->mdio.dev, 318 "error enabling power management\n"); 319 } 320 321 return ret; 322 } 323 324 /* get actual speed to cover the downshift case */ 325 static int rtlgen_get_speed(struct phy_device *phydev) 326 { 327 int val; 328 329 if (!phydev->link) 330 return 0; 331 332 val = phy_read_paged(phydev, 0xa43, 0x12); 333 if (val < 0) 334 return val; 335 336 switch (val & RTLGEN_SPEED_MASK) { 337 case 0x0000: 338 phydev->speed = SPEED_10; 339 break; 340 case 0x0010: 341 phydev->speed = SPEED_100; 342 break; 343 case 0x0020: 344 phydev->speed = SPEED_1000; 345 break; 346 case 0x0200: 347 phydev->speed = SPEED_10000; 348 break; 349 case 0x0210: 350 phydev->speed = SPEED_2500; 351 break; 352 case 0x0220: 353 phydev->speed = SPEED_5000; 354 break; 355 default: 356 break; 357 } 358 359 return 0; 360 } 361 362 static int rtlgen_read_status(struct phy_device *phydev) 363 { 364 int ret; 365 366 ret = genphy_read_status(phydev); 367 if (ret < 0) 368 return ret; 369 370 return rtlgen_get_speed(phydev); 371 } 372 373 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 374 { 375 int ret; 376 377 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) { 378 rtl821x_write_page(phydev, 0xa5c); 379 ret = __phy_read(phydev, 0x12); 380 rtl821x_write_page(phydev, 0); 381 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) { 382 rtl821x_write_page(phydev, 0xa5d); 383 ret = __phy_read(phydev, 0x10); 384 rtl821x_write_page(phydev, 0); 385 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) { 386 rtl821x_write_page(phydev, 0xa5d); 387 ret = __phy_read(phydev, 0x11); 388 rtl821x_write_page(phydev, 0); 389 } else { 390 ret = -EOPNOTSUPP; 391 } 392 393 return ret; 394 } 395 396 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 397 u16 val) 398 { 399 int ret; 400 401 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) { 402 rtl821x_write_page(phydev, 0xa5d); 403 ret = __phy_write(phydev, 0x10, val); 404 rtl821x_write_page(phydev, 0); 405 } else { 406 ret = -EOPNOTSUPP; 407 } 408 409 return ret; 410 } 411 412 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 413 { 414 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 415 416 if (ret != -EOPNOTSUPP) 417 return ret; 418 419 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) { 420 rtl821x_write_page(phydev, 0xa6e); 421 ret = __phy_read(phydev, 0x16); 422 rtl821x_write_page(phydev, 0); 423 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) { 424 rtl821x_write_page(phydev, 0xa6d); 425 ret = __phy_read(phydev, 0x12); 426 rtl821x_write_page(phydev, 0); 427 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) { 428 rtl821x_write_page(phydev, 0xa6d); 429 ret = __phy_read(phydev, 0x10); 430 rtl821x_write_page(phydev, 0); 431 } 432 433 return ret; 434 } 435 436 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 437 u16 val) 438 { 439 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 440 441 if (ret != -EOPNOTSUPP) 442 return ret; 443 444 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) { 445 rtl821x_write_page(phydev, 0xa6d); 446 ret = __phy_write(phydev, 0x12, val); 447 rtl821x_write_page(phydev, 0); 448 } 449 450 return ret; 451 } 452 453 static int rtl822x_get_features(struct phy_device *phydev) 454 { 455 int val; 456 457 val = phy_read_paged(phydev, 0xa61, 0x13); 458 if (val < 0) 459 return val; 460 461 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 462 phydev->supported, val & RTL_SUPPORTS_2500FULL); 463 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 464 phydev->supported, val & RTL_SUPPORTS_5000FULL); 465 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 466 phydev->supported, val & RTL_SUPPORTS_10000FULL); 467 468 return genphy_read_abilities(phydev); 469 } 470 471 static int rtl822x_config_aneg(struct phy_device *phydev) 472 { 473 int ret = 0; 474 475 if (phydev->autoneg == AUTONEG_ENABLE) { 476 u16 adv2500 = 0; 477 478 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 479 phydev->advertising)) 480 adv2500 = RTL_ADV_2500FULL; 481 482 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12, 483 RTL_ADV_2500FULL, adv2500); 484 if (ret < 0) 485 return ret; 486 } 487 488 return __genphy_config_aneg(phydev, ret); 489 } 490 491 static int rtl822x_read_status(struct phy_device *phydev) 492 { 493 int ret; 494 495 if (phydev->autoneg == AUTONEG_ENABLE) { 496 int lpadv = phy_read_paged(phydev, 0xa5d, 0x13); 497 498 if (lpadv < 0) 499 return lpadv; 500 501 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 502 phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL); 503 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 504 phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL); 505 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 506 phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL); 507 } 508 509 ret = genphy_read_status(phydev); 510 if (ret < 0) 511 return ret; 512 513 return rtlgen_get_speed(phydev); 514 } 515 516 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 517 { 518 int val; 519 520 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 521 val = phy_read(phydev, 0x13); 522 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 523 524 return val >= 0 && val & RTL_SUPPORTS_2500FULL; 525 } 526 527 static int rtlgen_match_phy_device(struct phy_device *phydev) 528 { 529 return phydev->phy_id == RTL_GENERIC_PHYID && 530 !rtlgen_supports_2_5gbps(phydev); 531 } 532 533 static int rtl8226_match_phy_device(struct phy_device *phydev) 534 { 535 return phydev->phy_id == RTL_GENERIC_PHYID && 536 rtlgen_supports_2_5gbps(phydev); 537 } 538 539 static int rtlgen_resume(struct phy_device *phydev) 540 { 541 int ret = genphy_resume(phydev); 542 543 /* Internal PHY's from RTL8168h up may not be instantly ready */ 544 msleep(20); 545 546 return ret; 547 } 548 549 static struct phy_driver realtek_drvs[] = { 550 { 551 PHY_ID_MATCH_EXACT(0x00008201), 552 .name = "RTL8201CP Ethernet", 553 }, { 554 PHY_ID_MATCH_EXACT(0x001cc816), 555 .name = "RTL8201F Fast Ethernet", 556 .ack_interrupt = &rtl8201_ack_interrupt, 557 .config_intr = &rtl8201_config_intr, 558 .suspend = genphy_suspend, 559 .resume = genphy_resume, 560 .read_page = rtl821x_read_page, 561 .write_page = rtl821x_write_page, 562 }, { 563 PHY_ID_MATCH_MODEL(0x001cc880), 564 .name = "RTL8208 Fast Ethernet", 565 .read_mmd = genphy_read_mmd_unsupported, 566 .write_mmd = genphy_write_mmd_unsupported, 567 .suspend = genphy_suspend, 568 .resume = genphy_resume, 569 .read_page = rtl821x_read_page, 570 .write_page = rtl821x_write_page, 571 }, { 572 PHY_ID_MATCH_EXACT(0x001cc910), 573 .name = "RTL8211 Gigabit Ethernet", 574 .config_aneg = rtl8211_config_aneg, 575 .read_mmd = &genphy_read_mmd_unsupported, 576 .write_mmd = &genphy_write_mmd_unsupported, 577 .read_page = rtl821x_read_page, 578 .write_page = rtl821x_write_page, 579 }, { 580 PHY_ID_MATCH_EXACT(0x001cc912), 581 .name = "RTL8211B Gigabit Ethernet", 582 .ack_interrupt = &rtl821x_ack_interrupt, 583 .config_intr = &rtl8211b_config_intr, 584 .read_mmd = &genphy_read_mmd_unsupported, 585 .write_mmd = &genphy_write_mmd_unsupported, 586 .suspend = rtl8211b_suspend, 587 .resume = rtl8211b_resume, 588 .read_page = rtl821x_read_page, 589 .write_page = rtl821x_write_page, 590 }, { 591 PHY_ID_MATCH_EXACT(0x001cc913), 592 .name = "RTL8211C Gigabit Ethernet", 593 .config_init = rtl8211c_config_init, 594 .read_mmd = &genphy_read_mmd_unsupported, 595 .write_mmd = &genphy_write_mmd_unsupported, 596 .read_page = rtl821x_read_page, 597 .write_page = rtl821x_write_page, 598 }, { 599 PHY_ID_MATCH_EXACT(0x001cc914), 600 .name = "RTL8211DN Gigabit Ethernet", 601 .ack_interrupt = rtl821x_ack_interrupt, 602 .config_intr = rtl8211e_config_intr, 603 .suspend = genphy_suspend, 604 .resume = genphy_resume, 605 .read_page = rtl821x_read_page, 606 .write_page = rtl821x_write_page, 607 }, { 608 PHY_ID_MATCH_EXACT(0x001cc915), 609 .name = "RTL8211E Gigabit Ethernet", 610 .config_init = &rtl8211e_config_init, 611 .ack_interrupt = &rtl821x_ack_interrupt, 612 .config_intr = &rtl8211e_config_intr, 613 .suspend = genphy_suspend, 614 .resume = genphy_resume, 615 .read_page = rtl821x_read_page, 616 .write_page = rtl821x_write_page, 617 }, { 618 PHY_ID_MATCH_EXACT(0x001cc916), 619 .name = "RTL8211F Gigabit Ethernet", 620 .config_init = &rtl8211f_config_init, 621 .ack_interrupt = &rtl8211f_ack_interrupt, 622 .config_intr = &rtl8211f_config_intr, 623 .suspend = genphy_suspend, 624 .resume = genphy_resume, 625 .read_page = rtl821x_read_page, 626 .write_page = rtl821x_write_page, 627 }, { 628 .name = "Generic FE-GE Realtek PHY", 629 .match_phy_device = rtlgen_match_phy_device, 630 .read_status = rtlgen_read_status, 631 .suspend = genphy_suspend, 632 .resume = rtlgen_resume, 633 .read_page = rtl821x_read_page, 634 .write_page = rtl821x_write_page, 635 .read_mmd = rtlgen_read_mmd, 636 .write_mmd = rtlgen_write_mmd, 637 }, { 638 .name = "RTL8226 2.5Gbps PHY", 639 .match_phy_device = rtl8226_match_phy_device, 640 .get_features = rtl822x_get_features, 641 .config_aneg = rtl822x_config_aneg, 642 .read_status = rtl822x_read_status, 643 .suspend = genphy_suspend, 644 .resume = rtlgen_resume, 645 .read_page = rtl821x_read_page, 646 .write_page = rtl821x_write_page, 647 .read_mmd = rtl822x_read_mmd, 648 .write_mmd = rtl822x_write_mmd, 649 }, { 650 PHY_ID_MATCH_EXACT(0x001cc840), 651 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 652 .get_features = rtl822x_get_features, 653 .config_aneg = rtl822x_config_aneg, 654 .read_status = rtl822x_read_status, 655 .suspend = genphy_suspend, 656 .resume = rtlgen_resume, 657 .read_page = rtl821x_read_page, 658 .write_page = rtl821x_write_page, 659 .read_mmd = rtl822x_read_mmd, 660 .write_mmd = rtl822x_write_mmd, 661 }, { 662 PHY_ID_MATCH_EXACT(0x001cc961), 663 .name = "RTL8366RB Gigabit Ethernet", 664 .config_init = &rtl8366rb_config_init, 665 /* These interrupts are handled by the irq controller 666 * embedded inside the RTL8366RB, they get unmasked when the 667 * irq is requested and ACKed by reading the status register, 668 * which is done by the irqchip code. 669 */ 670 .ack_interrupt = genphy_no_ack_interrupt, 671 .config_intr = genphy_no_config_intr, 672 .suspend = genphy_suspend, 673 .resume = genphy_resume, 674 }, 675 }; 676 677 module_phy_driver(realtek_drvs); 678 679 static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 680 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 681 { } 682 }; 683 684 MODULE_DEVICE_TABLE(mdio, realtek_tbl); 685