1 /* 2 * drivers/net/phy/qsemi.c 3 * 4 * Driver for Quality Semiconductor PHYs 5 * 6 * Author: Andy Fleming 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 #include <linux/config.h> 17 #include <linux/kernel.h> 18 #include <linux/sched.h> 19 #include <linux/string.h> 20 #include <linux/errno.h> 21 #include <linux/unistd.h> 22 #include <linux/slab.h> 23 #include <linux/interrupt.h> 24 #include <linux/init.h> 25 #include <linux/delay.h> 26 #include <linux/netdevice.h> 27 #include <linux/etherdevice.h> 28 #include <linux/skbuff.h> 29 #include <linux/spinlock.h> 30 #include <linux/mm.h> 31 #include <linux/module.h> 32 #include <linux/mii.h> 33 #include <linux/ethtool.h> 34 #include <linux/phy.h> 35 36 #include <asm/io.h> 37 #include <asm/irq.h> 38 #include <asm/uaccess.h> 39 40 /* ------------------------------------------------------------------------- */ 41 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */ 42 43 /* register definitions */ 44 45 #define MII_QS6612_MCR 17 /* Mode Control Register */ 46 #define MII_QS6612_FTR 27 /* Factory Test Register */ 47 #define MII_QS6612_MCO 28 /* Misc. Control Register */ 48 #define MII_QS6612_ISR 29 /* Interrupt Source Register */ 49 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */ 50 #define MII_QS6612_IMR_INIT 0x003a 51 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ 52 53 #define QS6612_PCR_AN_COMPLETE 0x1000 54 #define QS6612_PCR_RLBEN 0x0200 55 #define QS6612_PCR_DCREN 0x0100 56 #define QS6612_PCR_4B5BEN 0x0040 57 #define QS6612_PCR_TX_ISOLATE 0x0020 58 #define QS6612_PCR_MLT3_DIS 0x0002 59 #define QS6612_PCR_SCRM_DESCRM 0x0001 60 61 MODULE_DESCRIPTION("Quality Semiconductor PHY driver"); 62 MODULE_AUTHOR("Andy Fleming"); 63 MODULE_LICENSE("GPL"); 64 65 /* Returns 0, unless there's a write error */ 66 static int qs6612_config_init(struct phy_device *phydev) 67 { 68 /* The PHY powers up isolated on the RPX, 69 * so send a command to allow operation. 70 * XXX - My docs indicate this should be 0x0940 71 * ...or something. The current value sets three 72 * reserved bits, bit 11, which specifies it should be 73 * set to one, bit 10, which specifies it should be set 74 * to 0, and bit 7, which doesn't specify. However, my 75 * docs are preliminary, and I will leave it like this 76 * until someone more knowledgable corrects me or it. 77 * -- Andy Fleming 78 */ 79 return phy_write(phydev, MII_QS6612_PCR, 0x0dc0); 80 } 81 82 static int qs6612_ack_interrupt(struct phy_device *phydev) 83 { 84 int err; 85 86 err = phy_read(phydev, MII_QS6612_ISR); 87 88 if (err < 0) 89 return err; 90 91 err = phy_read(phydev, MII_BMSR); 92 93 if (err < 0) 94 return err; 95 96 err = phy_read(phydev, MII_EXPANSION); 97 98 if (err < 0) 99 return err; 100 101 return 0; 102 } 103 104 static int qs6612_config_intr(struct phy_device *phydev) 105 { 106 int err; 107 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 108 err = phy_write(phydev, MII_QS6612_IMR, 109 MII_QS6612_IMR_INIT); 110 else 111 err = phy_write(phydev, MII_QS6612_IMR, 0); 112 113 return err; 114 115 } 116 117 static struct phy_driver qs6612_driver = { 118 .phy_id = 0x00181440, 119 .name = "QS6612", 120 .phy_id_mask = 0xfffffff0, 121 .features = PHY_BASIC_FEATURES, 122 .flags = PHY_HAS_INTERRUPT, 123 .config_init = qs6612_config_init, 124 .config_aneg = genphy_config_aneg, 125 .read_status = genphy_read_status, 126 .ack_interrupt = qs6612_ack_interrupt, 127 .config_intr = qs6612_config_intr, 128 .driver = { .owner = THIS_MODULE,}, 129 }; 130 131 static int __init qs6612_init(void) 132 { 133 return phy_driver_register(&qs6612_driver); 134 } 135 136 static void __exit qs6612_exit(void) 137 { 138 phy_driver_unregister(&qs6612_driver); 139 } 140 141 module_init(qs6612_init); 142 module_exit(qs6612_exit); 143