1 /* 2 * drivers/net/phy/qsemi.c 3 * 4 * Driver for Quality Semiconductor PHYs 5 * 6 * Author: Andy Fleming 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 #include <linux/kernel.h> 17 #include <linux/string.h> 18 #include <linux/errno.h> 19 #include <linux/unistd.h> 20 #include <linux/slab.h> 21 #include <linux/interrupt.h> 22 #include <linux/init.h> 23 #include <linux/delay.h> 24 #include <linux/netdevice.h> 25 #include <linux/etherdevice.h> 26 #include <linux/skbuff.h> 27 #include <linux/spinlock.h> 28 #include <linux/mm.h> 29 #include <linux/module.h> 30 #include <linux/mii.h> 31 #include <linux/ethtool.h> 32 #include <linux/phy.h> 33 34 #include <asm/io.h> 35 #include <asm/irq.h> 36 #include <asm/uaccess.h> 37 38 /* ------------------------------------------------------------------------- */ 39 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */ 40 41 /* register definitions */ 42 43 #define MII_QS6612_MCR 17 /* Mode Control Register */ 44 #define MII_QS6612_FTR 27 /* Factory Test Register */ 45 #define MII_QS6612_MCO 28 /* Misc. Control Register */ 46 #define MII_QS6612_ISR 29 /* Interrupt Source Register */ 47 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */ 48 #define MII_QS6612_IMR_INIT 0x003a 49 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ 50 51 #define QS6612_PCR_AN_COMPLETE 0x1000 52 #define QS6612_PCR_RLBEN 0x0200 53 #define QS6612_PCR_DCREN 0x0100 54 #define QS6612_PCR_4B5BEN 0x0040 55 #define QS6612_PCR_TX_ISOLATE 0x0020 56 #define QS6612_PCR_MLT3_DIS 0x0002 57 #define QS6612_PCR_SCRM_DESCRM 0x0001 58 59 MODULE_DESCRIPTION("Quality Semiconductor PHY driver"); 60 MODULE_AUTHOR("Andy Fleming"); 61 MODULE_LICENSE("GPL"); 62 63 /* Returns 0, unless there's a write error */ 64 static int qs6612_config_init(struct phy_device *phydev) 65 { 66 /* The PHY powers up isolated on the RPX, 67 * so send a command to allow operation. 68 * XXX - My docs indicate this should be 0x0940 69 * ...or something. The current value sets three 70 * reserved bits, bit 11, which specifies it should be 71 * set to one, bit 10, which specifies it should be set 72 * to 0, and bit 7, which doesn't specify. However, my 73 * docs are preliminary, and I will leave it like this 74 * until someone more knowledgable corrects me or it. 75 * -- Andy Fleming 76 */ 77 return phy_write(phydev, MII_QS6612_PCR, 0x0dc0); 78 } 79 80 static int qs6612_ack_interrupt(struct phy_device *phydev) 81 { 82 int err; 83 84 err = phy_read(phydev, MII_QS6612_ISR); 85 86 if (err < 0) 87 return err; 88 89 err = phy_read(phydev, MII_BMSR); 90 91 if (err < 0) 92 return err; 93 94 err = phy_read(phydev, MII_EXPANSION); 95 96 if (err < 0) 97 return err; 98 99 return 0; 100 } 101 102 static int qs6612_config_intr(struct phy_device *phydev) 103 { 104 int err; 105 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 106 err = phy_write(phydev, MII_QS6612_IMR, 107 MII_QS6612_IMR_INIT); 108 else 109 err = phy_write(phydev, MII_QS6612_IMR, 0); 110 111 return err; 112 113 } 114 115 static struct phy_driver qs6612_driver = { 116 .phy_id = 0x00181440, 117 .name = "QS6612", 118 .phy_id_mask = 0xfffffff0, 119 .features = PHY_BASIC_FEATURES, 120 .flags = PHY_HAS_INTERRUPT, 121 .config_init = qs6612_config_init, 122 .config_aneg = genphy_config_aneg, 123 .read_status = genphy_read_status, 124 .ack_interrupt = qs6612_ack_interrupt, 125 .config_intr = qs6612_config_intr, 126 .driver = { .owner = THIS_MODULE,}, 127 }; 128 129 static int __init qs6612_init(void) 130 { 131 return phy_driver_register(&qs6612_driver); 132 } 133 134 static void __exit qs6612_exit(void) 135 { 136 phy_driver_unregister(&qs6612_driver); 137 } 138 139 module_init(qs6612_init); 140 module_exit(qs6612_exit); 141